= 0\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n%ifidn %1, dct\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%elifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%elifidn %1, flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd ;0\n%ifidn %2, dct\n%ifnidn %1, dct\n pmulhrsw m0, [o(pw_2896x8)]\n%else\n pmulhrsw m0, m1\n%endif\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end2\n%else ; adst / flipadst\n pmulhrsw m1, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n TAIL_CALL m(i%2_4x4_internal).end2\n%endif\n%endif\n%endmacro\n\nINIT_XMM ssse3\n\nINV_TXFM_4X4_FN dct, dct, 0\nINV_TXFM_4X4_FN dct, adst, 0\nINV_TXFM_4X4_FN dct, flipadst, 0\nINV_TXFM_4X4_FN dct, identity, 3\n\ncglobal idct_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0] ;high: in1 ;low: in0\n mova m1, [coeffq+16*1] ;high: in3 ;low in2\n\n IDCT4_1D_PACKED\n\n mova m2, [o(deint_shuf)]\n shufps m3, m0, m1, q1331\n shufps m0, m1, q0220\n pshufb m0, m2 ;high: in1 ;low: in0\n pshufb m1, m3, m2 ;high: in3 ;low :in2\n jmp tx2q\n\n.pass2:\n IDCT4_1D_PACKED\n\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2 ;memset(coeff, 0, sizeof(*coeff) * sh * sw);\n\n ITX4_END 0, 1, 3, 2\n\nINV_TXFM_4X4_FN adst, dct, 0\nINV_TXFM_4X4_FN adst, adst, 0\nINV_TXFM_4X4_FN adst, flipadst, 0\nINV_TXFM_4X4_FN adst, identity\n\ncglobal iadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call .main\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 0, 1, 2, 3\n\nALIGN function_align\n.main:\n punpcklwd m2, m0, m1 ;unpacked in0 in2\n punpckhwd m0, m1 ;unpacked in1 in3\n mova m3, m0\n pmaddwd m1, m2, [o(pw_3344_m3344)];3344 * in0 - 3344 * in2\n pmaddwd m0, [o(pw_0_3344)] ;3344 * in3\n paddd m1, m0 ;t2\n pmaddwd m0, m2, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m2, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m4, m3, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m3, [o(pw_3344_m3803)];3344 * in1 - 3803 * in3\n paddd m4, m0 ;t0 + t3\n pmaddwd m3, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m0, [o(pd_2048)]\n paddd m1, m0 ;t2 + 2048\n paddd m2, m0\n paddd m0, m4 ;t0 + t3 + 2048\n paddd m5, m2 ;t1 + t3 + 2048\n paddd m2, m4\n paddd m2, m3 ;t0 + t1 - t3 + 2048\n REPX {psrad x, 12}, m1, m0, m5, m2\n packssdw m0, m5 ;high: out1 ;low: out0\n packssdw m1, m2 ;high: out3 ;low: out3\n ret\n\nINV_TXFM_4X4_FN flipadst, dct, 0\nINV_TXFM_4X4_FN flipadst, adst, 0\nINV_TXFM_4X4_FN flipadst, flipadst, 0\nINV_TXFM_4X4_FN flipadst, identity\n\ncglobal iflipadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call m(iadst_4x4_internal).main\n punpcklwd m2, m1, m0\n punpckhwd m1, m0\n punpcklwd m0, m1, m2 ;high: in3 ;low :in2\n punpckhwd m1, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call m(iadst_4x4_internal).main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 3, 2, 1, 0\n\nINV_TXFM_4X4_FN identity, dct, 3\nINV_TXFM_4X4_FN identity, adst\nINV_TXFM_4X4_FN identity, flipadst\nINV_TXFM_4X4_FN identity, identity\n\ncglobal iidentity_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m0, m3\n pmulhrsw m3, m1\n paddsw m0, m2\n paddsw m1, m3\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddsw m0, m2\n paddsw m1, m3\n jmp m(iadst_4x4_internal).end\n\n%macro IWHT4_1D_PACKED 0\n punpckhqdq m3, m0, m1 ;low: in1 high: in3\n punpcklqdq m0, m1 ;low: in0 high: in2\n psubw m2, m0, m3 ;low: in0 - in1 high: in2 - in3\n paddw m0, m3 ;low: in0 + in1 high: in2 + in3\n punpckhqdq m2, m2 ;t2 t2\n punpcklqdq m0, m0 ;t0 t0\n psubw m1, m0, m2\n psraw m1, 1 ;t4 t4\n psubw m1, m3 ;low: t1/out2 high: t3/out1\n psubw m0, m1 ;high: out0\n paddw m2, m1 ;low: out3\n%endmacro\n\ncglobal inv_txfm_add_wht_wht_4x4, 3, 3, 4, dst, stride, coeff\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n psraw m0, 2\n psraw m1, 2\n\n IWHT4_1D_PACKED\n\n punpckhwd m0, m1\n punpcklwd m3, m1, m2\n punpckhdq m1, m0, m3\n punpckldq m0, m3\n\n IWHT4_1D_PACKED\n\n shufpd m0, m2, 0x01\n ITX4_END 0, 3, 2, 1, 0\n\n\n%macro IDCT8_1D_PACKED 0\n mova m6, [o(pd_2048)]\n punpckhwd m4, m0, m3 ;unpacked in1 in7\n punpcklwd m0, m2 ;unpacked in0 in4\n punpckhwd m2, m1 ;unpacked in5 in3\n punpcklwd m1, m3 ;unpacked in2 in6\n ITX_MUL2X_PACK 4, 3, 6, 799, 4017 ;low: t7a high: t4a\n ITX_MUL2X_PACK 2, 3, 6, 3406, 2276 ;low: t6a high: t5a\n ITX_MUL2X_PACK 1, 3, 6, 1567, 3784 ;low: t3 high: t2\n psubsw m3, m4, m2 ;low: t6a high: t5a\n paddsw m4, m2 ;low: t7 high: t4\n pshufb m3, [o(deint_shuf1)]\n ITX_MUL2X_PACK 0, 2, 6, 2896, 2896 ;low: t0 high: t1\n ITX_MUL2X_PACK 3, 2, 6, 2896, 2896 ;low: t6 high: t5\n psubsw m2, m0, m1 ;low: tmp3 high: tmp2\n paddsw m0, m1 ;low: tmp0 high: tmp1\n punpcklqdq m1, m4, m3 ;low: t7 high: t6\n punpckhqdq m4, m3 ;low: t4 high: t5\n psubsw m3, m0, m1 ;low: out7 high: out6\n paddsw m0, m1 ;low: out0 high: out1\n paddsw m1, m2, m4 ;low: out3 high: out2\n psubsw m2, m4 ;low: out4 high: out5\n%endmacro\n\n;dst1 = (src1 * coef1 - src2 * coef2 + rnd) >> 12\n;dst2 = (src1 * coef2 + src2 * coef1 + rnd) >> 12\n%macro ITX_MULSUB_2W 7-8 0 ; dst/src[1-2], tmp[1-2], rnd, coef[1-2], dst2_in_tmp1\n punpckhwd m%4, m%1, m%2\n punpcklwd m%1, m%2\n%if %7 < 8\n pmaddwd m%2, m%7, m%1\n pmaddwd m%3, m%7, m%4\n%else\n mova m%2, [o(pw_%7_%6)]\n%if %8\n pmaddwd m%3, m%1, m%2\n pmaddwd m%2, m%4\n%else\n pmaddwd m%3, m%4, m%2\n pmaddwd m%2, m%1\n%endif\n%endif\n paddd m%3, m%5\n paddd m%2, m%5\n psrad m%3, 12\n psrad m%2, 12\n%if %8\n packssdw m%3, m%2\n%else\n packssdw m%2, m%3 ;dst2\n%endif\n%if %7 < 8\n pmaddwd m%4, m%6\n pmaddwd m%1, m%6\n%elif %8\n mova m%2, [o(pw_%6_m%7)]\n pmaddwd m%4, m%2\n pmaddwd m%1, m%2\n%else\n mova m%3, [o(pw_%6_m%7)]\n pmaddwd m%4, m%3\n pmaddwd m%1, m%3\n%endif\n paddd m%4, m%5\n paddd m%1, m%5\n psrad m%4, 12\n psrad m%1, 12\n packssdw m%1, m%4 ;dst1\n%endmacro\n\n%macro IDCT4_1D 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %2, %4, %5, %6, %7, 1567, 3784, 1 ;t2, t3\n ITX_MULSUB_2W %1, %3, %4, %6, %7, 2896, 2896, 1 ;t1, t0\n psubsw m%3, m%1, m%2 ;out2\n paddsw m%2, m%1 ;out1\n paddsw m%1, m%5, m%4 ;out0\n psubsw m%4, m%5 ;out3\n%endmacro\n\n%macro WRITE_4X8 4 ;row[1-4]\n WRITE_4X4 0, 1, 4, 5, 6, %1, %2, %3, %4\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 2, 3, 4, 5, 6, %1, %2, %3, %4\n%endmacro\n\n%macro INV_4X8 0\n punpckhwd m4, m2, m3\n punpcklwd m2, m3\n punpckhwd m3, m0, m1\n punpcklwd m0, m1\n punpckhdq m1, m0, m2 ;low: in2 high: in3\n punpckldq m0, m2 ;low: in0 high: in1\n punpckldq m2, m3, m4 ;low: in4 high: in5\n punpckhdq m3, m4 ;low: in6 high: in7\n%endmacro\n\n%macro INV_TXFM_4X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x8, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_4096)]\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n movd m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n mova m2, [o(pw_2896x8)]\n punpckldq m0, m1\n pmulhrsw m0, m2\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n pmulhrsw m0, m2\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%endif\n%endif\n%endmacro\n\nINV_TXFM_4X8_FN dct, dct, 0\nINV_TXFM_4X8_FN dct, identity, 7\nINV_TXFM_4X8_FN dct, adst\nINV_TXFM_4X8_FN dct, flipadst\n\ncglobal idct_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(idct_8x4_internal).main\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n call .main\n shufps m1, m1, q1032\n shufps m3, m3, q1032\n mova m4, [o(pw_2048)]\n jmp m(iadst_4x8_internal).end2\n\nALIGN function_align\n.main:\n IDCT8_1D_PACKED\n ret\n\n\nINV_TXFM_4X8_FN adst, dct, 0\nINV_TXFM_4X8_FN adst, adst\nINV_TXFM_4X8_FN adst, flipadst\nINV_TXFM_4X8_FN adst, identity\n\ncglobal iadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n.pass1_end:\n INV_4X8\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call .main\n mova m4, [o(pw_2048)]\n pxor m5, m5\n psubw m5, m4\n\n.end:\n punpcklqdq m4, m5\n\n.end2:\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end3:\n pxor m5, m5\n mova [coeffq+16*0], m5\n mova [coeffq+16*1], m5\n mova [coeffq+16*2], m5\n mova [coeffq+16*3], m5\n\n.end4:\n WRITE_4X8 0, 1, 2, 3\n RET\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n punpckhwd m4, m3, m0 ;unpacked in7 in0\n punpckhwd m5, m2, m1 ;unpacked in5 in2\n punpcklwd m1, m2 ;unpacked in3 in4\n punpcklwd m0, m3 ;unpacked in1 in6\n ITX_MUL2X_PACK 4, 2, 6, 401, 4076 ;low: t0a high: t1a\n ITX_MUL2X_PACK 5, 2, 6, 1931, 3612 ;low: t2a high: t3a\n ITX_MUL2X_PACK 1, 2, 6, 3166, 2598 ;low: t4a high: t5a\n ITX_MUL2X_PACK 0, 2, 6, 3920, 1189 ;low: t6a high: t7a\n\n psubsw m3, m4, m1 ;low: t4 high: t5\n paddsw m4, m1 ;low: t0 high: t1\n psubsw m2, m5, m0 ;low: t6 high: t7\n paddsw m5, m0 ;low: t2 high: t3\n\n shufps m1, m3, m2, q1032\n punpckhwd m2, m1\n punpcklwd m3, m1\n ITX_MUL2X_PACK 3, 0, 6, 1567, 3784, 1 ;low: t5a high: t4a\n ITX_MUL2X_PACK 2, 0, 6, 3784, 1567 ;low: t7a high: t6a\n\n psubsw m1, m4, m5 ;low: t2 high: t3\n paddsw m4, m5 ;low: out0 high: -out7\n psubsw m5, m3, m2 ;low: t7 high: t6\n paddsw m3, m2 ;low: out6 high: -out1\n shufps m0, m4, m3, q3210 ;low: out0 high: -out1\n shufps m3, m4, q3210 ;low: out6 high: -out7\n\n mova m2, [o(pw_2896_m2896)]\n mova m7, [o(pw_2896_2896)]\n shufps m4, m1, m5, q1032 ;low: t3 high: t7\n shufps m1, m5, q3210 ;low: t2 high: t6\n punpcklwd m5, m1, m4\n punpckhwd m1, m4\n pmaddwd m4, m2, m1 ;-out5\n pmaddwd m2, m5 ; out4\n pmaddwd m1, m7 ; out2\n pmaddwd m5, m7 ;-out3\n REPX {paddd x, m6}, m4, m2, m1, m5\n REPX {psrad x, 12}, m4, m2, m1, m5\n packssdw m1, m5 ;low: out2 high: -out3\n packssdw m2, m4 ;low: out4 high: -out5\n ret\n\nINV_TXFM_4X8_FN flipadst, dct, 0\nINV_TXFM_4X8_FN flipadst, adst\nINV_TXFM_4X8_FN flipadst, flipadst\nINV_TXFM_4X8_FN flipadst, identity\n\ncglobal iflipadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n punpcklwd m4, m3, m2\n punpckhwd m3, m2\n punpcklwd m5, m1, m0\n punpckhwd m1, m0\n punpckldq m2, m3, m1 ;low: in4 high: in5\n punpckhdq m3, m1 ;low: in6 high: in7\n punpckldq m0, m4, m5 ;low: in0 high: in1\n punpckhdq m1, m4, m5 ;low: in2 high: in3\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n mova m4, m0\n mova m5, m1\n pshufd m0, m3, q1032\n pshufd m1, m2, q1032\n pshufd m2, m5, q1032\n pshufd m3, m4, q1032\n mova m5, [o(pw_2048)]\n pxor m4, m4\n psubw m4, m5\n jmp m(iadst_4x8_internal).end\n\nINV_TXFM_4X8_FN identity, dct, 3\nINV_TXFM_4X8_FN identity, adst\nINV_TXFM_4X8_FN identity, flipadst\nINV_TXFM_4X8_FN identity, identity\n\ncglobal iidentity_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddsw m0, m4\n paddsw m1, m5\n paddsw m2, m6\n paddsw m3, m7\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n mova m4, [o(pw_4096)]\n jmp m(iadst_4x8_internal).end2\n\n\n%macro WRITE_8X2 5 ;coefs[1-2], tmp[1-3]\n movq m%3, [dstq ]\n movq m%4, [dstq+strideq]\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n%ifnum %1\n paddw m%3, m%1\n%else\n paddw m%3, %1\n%endif\n%ifnum %2\n paddw m%4, m%2\n%else\n paddw m%4, %2\n%endif\n packuswb m%3, m%4\n movq [dstq ], m%3\n punpckhqdq m%3, m%3\n movq [dstq+strideq], m%3\n%endmacro\n\n%macro WRITE_8X4 7 ;coefs[1-4], tmp[1-3]\n WRITE_8X2 %1, %2, %5, %6, %7\n lea dstq, [dstq+strideq*2]\n WRITE_8X2 %3, %4, %5, %6, %7\n%endmacro\n\n%macro INV_TXFM_8X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m1, m0, [coeffq]\n pmulhrsw m1, m0\n pmulhrsw m0, m1, [o(pw_1697x8)]\n paddw m1, m0\n pmulhrsw m1, [o(pw_2048)]\n punpcklwd m1, m1\n punpckhdq m2, m1, m1\n punpckldq m1, m1\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckldq m0, m1, m1\n punpckhdq m1, m1\n%elifidn %1_%2, identity_dct\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m5, m2, m3\n punpcklwd m2, m3\n punpcklwd m0, m4\n punpcklwd m2, m5\n punpcklqdq m0, m2\n mova m4, [o(pw_2896x8)]\n pmulhrsw m0, m4\n paddw m0, m0\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n%ifidn %2, dct\n mova m2, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else ; adst / flipadst\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n%endif\n%endif\n TAIL_CALL m(iadst_8x4_internal).end2\n%endif\n%endmacro\n\nINV_TXFM_8X4_FN dct, dct, 0\nINV_TXFM_8X4_FN dct, adst, 0\nINV_TXFM_8X4_FN dct, flipadst, 0\nINV_TXFM_8X4_FN dct, identity, 3\n\ncglobal idct_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n call m(idct_4x8_internal).main\n\n mova m4, [o(deint_shuf1)]\n mova m5, [o(deint_shuf2)]\n pshufb m0, m4\n pshufb m1, m5\n pshufb m2, m4\n pshufb m3, m5\n punpckhdq m4, m0, m1\n punpckldq m0, m1\n punpckhdq m5, m2, m3\n punpckldq m2, m3\n punpckhqdq m1, m0, m2 ;in1\n punpcklqdq m0, m2 ;in0\n punpckhqdq m3, m4, m5 ;in3\n punpcklqdq m2 ,m4, m5 ;in2\n jmp tx2q\n\n.pass2:\n call .main\n jmp m(iadst_8x4_internal).end\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n IDCT4_1D 0, 1, 2, 3, 4, 5, 6\n ret\n\nINV_TXFM_8X4_FN adst, dct\nINV_TXFM_8X4_FN adst, adst\nINV_TXFM_8X4_FN adst, flipadst\nINV_TXFM_8X4_FN adst, identity\n\ncglobal iadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n pxor m5, m5\n psubsw m3, m5, m1\n psubsw m5, m4\n punpckhdq m4, m5, m3\n punpckldq m5, m3\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m5 ;in1\n punpcklwd m0, m5 ;in0\n punpcklwd m2, m3, m4 ;in2\n punpckhwd m3, m4 ;in3\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end2:\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n mova [coeffq+16*2], m6\n mova [coeffq+16*3], m6\n.end3:\n WRITE_8X4 0, 1, 2, 3, 4, 5, 6\n RET\n\nALIGN function_align\n.main:\n punpckhwd m6, m0, m2 ;unpacked in0 in2\n punpcklwd m0, m2 ;unpacked in0 in2\n punpckhwd m7, m1, m3 ;unpacked in1 in3\n punpcklwd m1, m3 ;unpacked in1 in3\n\n mova m2, [o(pw_3344_m3344)]\n mova m4, [o(pw_0_3344)]\n pmaddwd m3, m2, m6 ;3344 * in0 - 3344 * in2\n pmaddwd m5, m4, m7 ;3344 * in3\n pmaddwd m2, m0\n pmaddwd m4, m1\n paddd m3, m5\n paddd m2, m4\n mova m4, [o(pd_2048)]\n paddd m3, m4 ;t2 + 2048\n paddd m2, m4\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n\n pmaddwd m4, m0, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m0, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m3, m1, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m1, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m3, m4 ;t0 + t3\n\n pmaddwd m1, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m4, [o(pd_2048)]\n paddd m0, m4\n paddd m4, m3 ;t0 + t3 + 2048\n paddd m5, m0 ;t1 + t3 + 2048\n paddd m3, m0\n paddd m3, m1 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m3, 12 ;out3\n packssdw m0, m4, m5 ;low: out0 high: out1\n\n pmaddwd m4, m6, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m6, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m1, m7, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m7, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m1, m4 ;t0 + t3\n pmaddwd m7, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n\n mova m4, [o(pd_2048)]\n paddd m6, m4\n paddd m4, m1 ;t0 + t3 + 2048\n paddd m5, m6 ;t1 + t3 + 2048\n paddd m1, m6\n paddd m1, m7 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m1, 12 ;out3\n packssdw m3, m1 ;out3\n packssdw m4, m5 ;low: out0 high: out1\n\n punpckhqdq m1, m0, m4 ;out1\n punpcklqdq m0, m4 ;out0\n ret\n\nINV_TXFM_8X4_FN flipadst, dct\nINV_TXFM_8X4_FN flipadst, adst\nINV_TXFM_8X4_FN flipadst, flipadst\nINV_TXFM_8X4_FN flipadst, identity\n\ncglobal iflipadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m5, m3, m2\n punpcklwd m3, m2\n punpckhwd m2, m1, m0\n punpcklwd m1, m0\n\n pxor m0, m0\n psubsw m4, m0, m2\n psubsw m0, m5\n punpckhdq m2, m0, m4\n punpckldq m0, m4\n punpckhdq m4, m3, m1\n punpckldq m3, m1\n punpckhwd m1, m0, m3 ;in1\n punpcklwd m0, m3 ;in0\n punpckhwd m3, m2, m4 ;in3\n punpcklwd m2, m4 ;in2\n jmp tx2q\n\n.pass2:\n call m(iadst_8x4_internal).main\n mova m4, m0\n mova m5, m1\n mova m0, m3\n mova m1, m2\n mova m2, m5\n mova m3, m4\n jmp m(iadst_8x4_internal).end\n\nINV_TXFM_8X4_FN identity, dct, 7\nINV_TXFM_8X4_FN identity, adst\nINV_TXFM_8X4_FN identity, flipadst\nINV_TXFM_8X4_FN identity, identity\n\ncglobal iidentity_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n paddw m0, m0\n paddw m1, m1\n paddw m2, m2\n paddw m3, m3\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n punpckhdq m5, m4, m1\n punpckldq m4, m1\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m4 ;in1\n punpcklwd m0, m4 ;in0\n punpcklwd m2, m3, m5 ;in2\n punpckhwd m3, m5 ;in3\n jmp tx2q\n\n.pass2:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddw m0, m4\n paddw m1, m5\n paddw m2, m6\n paddw m3, m7\n jmp m(iadst_8x4_internal).end\n\n%macro INV_TXFM_8X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x8, 8, 16*4\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n mova m1, [o(pw_16384)]\n pmulhrsw m0, m1\n psrlw m1, 2\n pmulhrsw m0, m1\n punpckhwd m7, m0, m0\n punpcklwd m0, m0\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end2\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n TAIL_CALL m(iadst_8x4_internal).end3\n%elif %3 >= 0\n%ifidn %1, dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 3\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n.end:\n mov r3d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x8).end3)]\n.loop:\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n jmp tx2q\n.end3:\n RET\n%else ; identity\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpcklwd m0, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n punpcklwd m2, [coeffq+16*6]\n punpcklwd m3, [coeffq+16*7]\n punpcklwd m0, m2\n punpcklwd m1, m3\n punpcklwd m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n pxor m4, m4\n REPX {mova [coeffq+16*x], m4}, 0, 1, 2, 3, 4, 5, 6, 7\n jmp m(inv_txfm_add_dct_dct_8x8).end\n%endif\n%endif\n%endmacro\n\n%macro LOAD_8ROWS 2-3 0 ; src, stride, is_rect2\n%if %3\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [%1+%2*0]\n pmulhrsw m1, m7, [%1+%2*1]\n pmulhrsw m2, m7, [%1+%2*2]\n pmulhrsw m3, m7, [%1+%2*3]\n pmulhrsw m4, m7, [%1+%2*4]\n pmulhrsw m5, m7, [%1+%2*5]\n pmulhrsw m6, m7, [%1+%2*6]\n pmulhrsw m7, [%1+%2*7]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n mova m7, [%1+%2*7]\n%endif\n%endmacro\n\n%macro IDCT8_1D_ODDHALF 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %1, %4, %5, %6, %7, 799, 4017 ;t4a, t7a\n ITX_MULSUB_2W %3, %2, %5, %6, %7, 3406, 2276, 1 ;t5a, t6a\n psubsw m%2, m%4, m%5 ;t6a\n paddsw m%4, m%5 ;t7\n psubsw m%5, m%1, m%3 ;t5a\n paddsw m%1, m%3 ;t4\n ITX_MULSUB_2W %2, %5, %3, %6, %7, 2896, 2896, 1 ;t5, t6\n%endmacro\n\nINV_TXFM_8X8_FN dct, dct, 0\nINV_TXFM_8X8_FN dct, identity, 7\nINV_TXFM_8X8_FN dct, adst\nINV_TXFM_8X8_FN dct, flipadst\n\ncglobal idct_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.pass1_end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n\n.pass1_end3:\n punpcklwd m6, m1, m5 ;10 50 11 51 12 52 13 53\n punpckhwd m1, m5 ;14 54 15 55 16 56 17 57\n punpckhwd m5, m0, m4 ;04 44 05 45 06 46 07 47\n punpcklwd m0, m4 ;00 40 01 41 02 42 03 43\n punpckhwd m4, m3, m7 ;34 74 35 75 36 76 37 77\n punpcklwd m3, m7 ;30 70 31 71 32 72 33 73\n punpckhwd m7, m1, m4 ;16 36 56 76 17 37 57 77\n punpcklwd m1, m4 ;14 34 54 74 15 35 55 75\n punpckhwd m4, m6, m3 ;12 32 52 72 13 33 53 73\n punpcklwd m6, m3 ;10 30 50 70 11 31 51 71\n mova [rsp+gprsize+16*2], m6\n mova m6, [rsp+gprsize+16*1]\n punpckhwd m3, m2, m6 ;24 64 25 65 26 66 27 67\n punpcklwd m2, m6 ;20 60 21 61 22 62 23 63\n punpckhwd m6, m5, m3 ;06 26 46 66 07 27 47 67\n punpcklwd m5, m3 ;04 24 44 64 05 25 45 65\n punpckhwd m3, m0, m2 ;02 22 42 62 03 23 43 63\n punpcklwd m0, m2 ;00 20 40 60 01 21 41 61\n\n punpckhwd m2, m6, m7 ;07 17 27 37 47 57 67 77\n punpcklwd m6, m7 ;06 16 26 36 46 56 66 76\n mova [rsp+gprsize+16*0], m2\n punpcklwd m2, m3, m4 ;02 12 22 32 42 52 62 72\n punpckhwd m3, m4 ;03 13 23 33 43 53 63 73\n punpcklwd m4, m5, m1 ;04 14 24 34 44 54 64 74\n punpckhwd m5, m1 ;05 15 25 35 45 55 65 75\n mova m7, [rsp+gprsize+16*2]\n punpckhwd m1, m0, m7 ;01 11 21 31 41 51 61 71\n punpcklwd m0, m7 ;00 10 20 30 40 50 60 70\n mova m7, [rsp+gprsize+16*0]\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*0], m7\n\n.end3:\n WRITE_8X4 0, 1, 2, 3, 5, 6, 7\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 4, [rsp+gprsize+16*2], [rsp+gprsize+16*1], [rsp+gprsize+16*0], 5, 6, 7\n jmp tx2q\n\n.end4:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m1\n mova m7, [o(pd_2048)]\n IDCT4_1D 0, 2, 4, 6, 1, 3, 7\n mova m3, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m2\n mova m2, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m4\n mova m4, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m6\n IDCT8_1D_ODDHALF 3, 2, 5, 4, 1, 6, 7\n mova m6, [rsp+gprsize*2+16*0]\n psubsw m7, m0, m4 ;out7\n paddsw m0, m4 ;out0\n mova [rsp+gprsize*2+16*0], m7\n mova m1, [rsp+gprsize*2+16*2]\n psubsw m4, m6, m3 ;out4\n paddsw m3, m6 ;out3\n mova m7, [rsp+gprsize*2+16*1]\n psubsw m6, m1, m5 ;out6\n paddsw m1, m5 ;out1\n psubsw m5, m7, m2 ;out5\n paddsw m2, m7 ;out2\n ret\n\n\nINV_TXFM_8X8_FN adst, dct\nINV_TXFM_8X8_FN adst, adst\nINV_TXFM_8X8_FN adst, flipadst\nINV_TXFM_8X8_FN adst, identity\n\ncglobal iadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n call .main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).pass1_end2\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n call .main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).end2\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m4\n mova m7, [o(pd_2048)]\n ITX_MULSUB_2W 5, 2, 3, 4, 7, 1931, 3612 ;t3a, t2a\n ITX_MULSUB_2W 1, 6, 3, 4, 7, 3920, 1189 ;t7a, t6a\n paddsw m3, m2, m6 ;t2\n psubsw m2, m6 ;t6\n paddsw m4, m5, m1 ;t3\n psubsw m5, m1 ;t7\n ITX_MULSUB_2W 5, 2, 1, 6, 7, 3784, 1567 ;t6a, t7a\n\n mova m6, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m5\n mova m1, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m2\n mova m5, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m3\n ITX_MULSUB_2W 5, 0, 2, 3, 7, 401, 4076 ;t1a, t0a\n ITX_MULSUB_2W 1, 6, 2, 3, 7, 3166, 2598 ;t5a, t4a\n psubsw m2, m0, m6 ;t4\n paddsw m0, m6 ;t0\n paddsw m3, m5, m1 ;t1\n psubsw m5, m1 ;t5\n ITX_MULSUB_2W 2, 5, 1, 6, 7, 1567, 3784 ;t5a, t4a\n\n mova m7, [rsp+gprsize*2+16*0]\n paddsw m1, m3, m4 ;-out7\n psubsw m3, m4 ;t3\n mova [rsp+gprsize*2+16*0], m1\n psubsw m4, m0, m7 ;t2\n paddsw m0, m7 ;out0\n mova m6, [rsp+gprsize*2+16*2]\n mova m7, [rsp+gprsize*2+16*1]\n paddsw m1, m5, m6 ;-out1\n psubsw m5, m6 ;t6\n paddsw m6, m2, m7 ;out6\n psubsw m2, m7 ;t7\n ret\nALIGN function_align\n.main_pass1_end:\n mova [rsp+gprsize*2+16*1], m1\n mova [rsp+gprsize*2+16*2], m6\n punpckhwd m1, m4, m3\n punpcklwd m4, m3\n punpckhwd m7, m5, m2\n punpcklwd m5, m2\n mova m2, [o(pw_2896_2896)]\n mova m6, [o(pd_2048)]\n pmaddwd m3, m2, m7\n pmaddwd m2, m5\n paddd m3, m6\n paddd m2, m6\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n mova m3, [o(pw_2896_m2896)]\n pmaddwd m7, m3\n pmaddwd m5, m3\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m5, m7 ;-out5\n mova m3, [o(pw_2896_2896)]\n pmaddwd m7, m3, m1\n pmaddwd m3, m4\n paddd m7, m6\n paddd m3, m6\n psrad m7, 12\n psrad m3, 12\n packssdw m3, m7 ;-out3\n mova m7, [o(pw_2896_m2896)]\n pmaddwd m1, m7\n pmaddwd m4, m7\n paddd m1, m6\n paddd m4, m6\n psrad m1, 12\n psrad m4, 12\n packssdw m4, m1 ;-out5\n mova m1, [rsp+gprsize*2+16*1]\n mova m6, [rsp+gprsize*2+16*2]\n ret\nALIGN function_align\n.main_pass2_end:\n paddsw m7, m4, m3 ;t2 + t3\n psubsw m4, m3 ;t2 - t3\n paddsw m3, m5, m2 ;t6 + t7\n psubsw m5, m2 ;t6 - t7\n mova m2, [o(pw_2896x8)]\n pmulhrsw m4, m2 ;out4\n pmulhrsw m5, m2 ;-out5\n pmulhrsw m7, m2 ;-out3\n pmulhrsw m2, m3 ;out2\n mova m3, m7\n ret\n\nINV_TXFM_8X8_FN flipadst, dct\nINV_TXFM_8X8_FN flipadst, adst\nINV_TXFM_8X8_FN flipadst, flipadst\nINV_TXFM_8X8_FN flipadst, identity\n\ncglobal iflipadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_m16384)]\n\n.pass1_end1:\n pmulhrsw m1, m7\n mova [rsp+gprsize+16*1], m1\n mova m1, m6\n mova m6, m2\n pmulhrsw m2, m5, m7\n mova m5, m6\n mova m6, m4\n pmulhrsw m4, m3, m7\n mova m3, m6\n mova m6, m0\n mova m0, m7\n pxor m7, m7\n psubw m7, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*2], m2\n mova m2, m0\n pxor m0, m0\n psubw m0, m7\n mova m7, m2\n pmulhrsw m1, m0\n pmulhrsw m2, m5, m0\n mova [rsp+gprsize+16*1], m1\n mova m5, m4\n mova m1, m6\n pmulhrsw m4, m3, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n mova m3, m5\n mova [rsp+gprsize+16*0], m7\n jmp m(idct_8x8_internal).end3\n\nINV_TXFM_8X8_FN identity, dct, 7\nINV_TXFM_8X8_FN identity, adst\nINV_TXFM_8X8_FN identity, flipadst\nINV_TXFM_8X8_FN identity, identity\n\ncglobal iidentity_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.end:\n pmulhrsw m7, [o(pw_4096)]\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_4096)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).end3\n\n\n%macro INV_TXFM_4X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x16, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n mova m1, m0\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m1, [coeffq+16*1]\n mova m2, [o(pw_16384)]\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddsw m0, m0\n paddsw m1, m1\n paddsw m0, m2\n paddsw m1, m3\n pmulhrsw m0, m4\n pmulhrsw m4, m1\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhwd m6, m4, m4\n punpcklwd m4, m4\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckhdq m5, m4, m4\n punpckldq m4, m4\n punpckhdq m7, m6, m6\n punpckldq m6, m6\n mova [coeffq+16*4], m4\n TAIL_CALL m(iadst_4x16_internal).end2\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n punpckldq m0, m1\n pmulhrsw m1, m0, [o(pw_1697x8)]\n pcmpeqw m2, m2\n pcmpeqw m2, m0\n pxor m0, m2\n pavgw m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n pxor m1, m1\n REPX {mova [coeffq+32*x], m1}, 0, 1, 2, 3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, [o(pw_16384)]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mova m1, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%endif\n.end:\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n RET\n%endif\n%endmacro\n\nINV_TXFM_4X16_FN dct, dct, 0\nINV_TXFM_4X16_FN dct, identity, 15\nINV_TXFM_4X16_FN dct, adst\nINV_TXFM_4X16_FN dct, flipadst\n\ncglobal idct_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_4x8_internal).pass1)]\n\n.pass1:\n mova m0, [coeffq+16*1]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n push tx2q\n lea tx2q, [o(m(idct_4x16_internal).pass1_2)]\n jmp r3\n\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(m(idct_4x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n pop tx2q\n\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*7], m7\n jmp tx2q\n\n.pass2:\n call m(idct_16x4_internal).main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n\n.end1:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 3, 2\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 3, 2\n\n.end2:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nINV_TXFM_4X16_FN adst, dct, 0\nINV_TXFM_4X16_FN adst, adst\nINV_TXFM_4X16_FN adst, flipadst\nINV_TXFM_4X16_FN adst, identity\n\ncglobal iadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpcklqdq m6, m5, m4 ;low: -out5 high: -out7\n punpckhqdq m4, m5 ;low: out8 high: out10\n punpcklqdq m5, m7, m2 ;low: out4 high: out6\n punpckhqdq m2, m7 ;low: -out9 high: -out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpckhqdq m1, m6, m0 ;low: -out13 high: -out15\n punpcklqdq m0, m6 ;low: out0 high: out2\n punpckhqdq m6, m3, m2 ;low: out12 high: out14\n punpcklqdq m2, m3 ;low: -out1 high: -out3\n\n mova m7, [o(pw_2048)]\n\n.end1:\n REPX {pmulhrsw x, m7}, m0, m5, m4, m6\n pxor m3, m3\n psubw m3, m7\n mova m7, [coeffq+16*4]\n REPX {pmulhrsw x, m3}, m2, m7, m1\n pmulhrsw m3, [coeffq+16*5]\n mova [coeffq+16*7], m5\n\n punpckhqdq m5, m4, m7 ;low: out10 high: out11\n punpcklqdq m4, m7 ;low: out8 high: out9\n punpckhqdq m7, m6, m1 ;low: out14 high: out15\n punpcklqdq m6, m1 ;low: out12 high: out13\n punpckhqdq m1, m0, m2 ;low: out2 high: out3\n punpcklqdq m0, m2 ;low: out0 high: out1\n mova [coeffq+16*4], m4\n mova m4, [coeffq+16*7]\n punpcklqdq m2, m4, m3 ;low: out4 high: out5\n punpckhqdq m4, m3 ;low: out6 high: out7\n mova m3, m4\n\n.end2:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 2, 3\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 2, 3\n\n.end3:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\n\nINV_TXFM_4X16_FN flipadst, dct, 0\nINV_TXFM_4X16_FN flipadst, adst\nINV_TXFM_4X16_FN flipadst, flipadst\nINV_TXFM_4X16_FN flipadst, identity\n\ncglobal iflipadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpckhqdq m6, m5, m4 ;low: out5 high: out7\n punpcklqdq m4, m5 ;low: -out8 high: -out10\n punpckhqdq m5, m7, m2 ;low: -out4 high: -out6\n punpcklqdq m2, m7 ;low: out9 high: out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpcklqdq m1, m6, m0 ;low: out13 high: out15\n punpckhqdq m0, m6 ;low: -out0 high: -out2\n punpcklqdq m6, m3, m2 ;low: -out12 high: -out14\n punpckhqdq m2, m3 ;low: out1 high: out3\n\n mova m7, [o(pw_m2048)]\n jmp m(iadst_4x16_internal).end1\n\n\nINV_TXFM_4X16_FN identity, dct, 3\nINV_TXFM_4X16_FN identity, adst\nINV_TXFM_4X16_FN identity, flipadst\nINV_TXFM_4X16_FN identity, identity\n\n%macro IDTX16 3-4 ; src/dst, tmp, pw_1697x16, [pw_16394]\n pmulhrsw m%2, m%3, m%1\n%if %0 == 4 ; if downshifting by 1\n pmulhrsw m%2, m%4\n%else\n paddsw m%1, m%1\n%endif\n paddsw m%1, m%2\n%endmacro\n\ncglobal iidentity_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*1]\n mova m6, [o(pw_1697x8)]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n pcmpeqw m7, m7\n mov r3, tx2q\n lea tx2q, [o(.pass1_2)]\n.pass1:\n pmulhrsw m4, m6, m0\n pmulhrsw m5, m6, m1\n pavgw m4, m0\n pcmpeqw m0, m7\n pavgw m5, m1\n pcmpeqw m1, m7\n pandn m0, m4\n pmulhrsw m4, m6, m2\n pandn m1, m5\n pmulhrsw m5, m6, m3\n pavgw m4, m2\n pcmpeqw m2, m7\n pavgw m5, m3\n pcmpeqw m3, m7\n pandn m2, m4\n pandn m3, m5\n jmp m(iadst_4x8_internal).pass1_end\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(.pass1_end)]\n jmp .pass1\n.pass1_end:\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n jmp r3\n.pass2:\n mova m7, [o(pw_1697x16)]\n mova [coeffq+16*6], m6\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [coeffq+16*7]\n IDTX16 6, 7, 7\n mova [coeffq+16*7], m6\n mova m6, [coeffq+16*6]\n pmulhrsw m7, m6, [o(pw_1697x16)]\n paddsw m6, m6\n paddsw m6, m7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n jmp m(iadst_4x16_internal).end2\n\n\n%macro INV_TXFM_16X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m3, [coeffq]\n mova m0, [o(pw_16384)]\n pmulhrsw m3, m0\n psrlw m0, 3 ; pw_2048\n pmulhrsw m1, m3, [o(pw_1697x8)]\n paddsw m3, m1\n pmulhrsw m3, m0\n punpcklwd m3, m3\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_16384)]\n mova m6, [o(pw_2896x8)]\n mov r3d, 2\n psrlw m7, m5, 3 ; pw_2048\n.main_loop:\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpcklwd m0, m2\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*3]\n punpckhwd m3, m1, m2\n punpcklwd m1, m2\n punpcklwd m1, m3\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n pmulhrsw m1, m5\n paddsw m0, m1\n pmulhrsw m0, m6\n pmulhrsw m0, m7\n.end:\n pxor m3, m3\n mova [coeffq+16*0], m3\n mova [coeffq+16*1], m3\n mova [coeffq+16*2], m3\n mova [coeffq+16*3], m3\n add coeffq, 16*4\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%else\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n%ifidn %2, dct\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n mov r2d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x4).end)]\n.dconly:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n.dconly_loop:\n mova m1, [dstq]\n mova m3, [dstq+strideq]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq], m1\n mova [dstq+strideq], m3\n lea dstq, [dstq+strideq*2]\n dec r2d\n jg .dconly_loop\n jmp tx2q\n.end:\n RET\n%else ; adst / flipadst\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov [coeffq], eobd\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end3\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end3\n%endif\n%endif\n%endif\n%endmacro\n\n%macro LOAD_7ROWS 2 ;src, stride\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n%endmacro\n\n%macro SAVE_7ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n%endmacro\n\n%macro IDCT16_1D_PACKED_ODDHALF 7 ;src[1-4], tmp[1-3]\n punpckhwd m%5, m%4, m%1 ;packed in13 in3\n punpcklwd m%1, m%4 ;packed in1 in15\n punpcklwd m%4, m%3, m%2 ;packed in9 in7\n punpckhwd m%2, m%3 ;packed in5 in11\n mova m%7, [o(pd_2048)]\n ITX_MUL2X_PACK %1, %6, %7, 401, 4076, 1 ;low: t8a high: t15a\n ITX_MUL2X_PACK %4, %6, %7, 3166, 2598, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %2, %6, %7, 1931, 3612, 1 ;low: t10a high: t13a\n ITX_MUL2X_PACK %5, %6, %7, 3920, 1189, 1 ;low: t11a high: t12a\n psubsw m%6, m%1, m%4 ;low: t9 high: t14\n paddsw m%1, m%4 ;low: t8 high: t15\n psubsw m%3, m%5, m%2 ;low: t10 high: t13\n paddsw m%5, m%2 ;low: t11 high: t12\n mova m%2, [o(deint_shuf2)]\n pshufb m%6, m%2\n pshufb m%3, [o(deint_shuf1)]\n pxor m%4, m%4\n psubw m%4, m%3 ;packed -t10 -t13\n ITX_MUL2X_PACK %6, %3, %7, 1567, 3784, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %4, %3, %7, 3784, 1567 ;low: t10a high: t13a\n psubsw m%3, m%1, m%5 ;low: t11a high: t12a\n paddsw m%1, m%5 ;low: t8a high: t15a\n psubsw m%5, m%6, m%4 ;low: t10 high: t13\n paddsw m%6, m%4 ;low: t9 high: t14\n pshufb m%3, m%2\n pshufb m%5, m%2\n ITX_MUL2X_PACK %3, %2, %7, 2896, 2896, 4 ;t12, t11\n ITX_MUL2X_PACK %5, %4, %7, 2896, 2896, 4 ;t13a, t10a\n packssdw m%2, m%4 ;low: t11 high: t10a\n packssdw m%3, m%5 ;low: t12 high: t13a\n punpckhqdq m%4, m%1, m%6 ;low: t15a high: t14\n punpcklqdq m%1, m%6 ;low: t8a high: t9\n%endmacro\n\nINV_TXFM_16X4_FN dct, dct, 0\nINV_TXFM_16X4_FN dct, adst, 0\nINV_TXFM_16X4_FN dct, flipadst, 0\nINV_TXFM_16X4_FN dct, identity, 3\n\ncglobal idct_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n\n.pass1_end:\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpcklwd m2, m1, m3 ;packed out3, out7\n punpckhwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpcklwd m6, m5, m7 ;packed out11, out15\n punpckhwd m5, m7 ;packed out10, out14\n\n.pass1_end2:\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*6]\n mova [coeffq+16*6], m7\n\n.pass1_end3:\n punpckhwd m7, m3, m6 ;packed 9, 11, 13, 15 high\n punpcklwd m3, m6 ;packed 9, 10, 13, 15 low\n punpckhwd m6, m4, m5 ;packed 8, 10, 12, 14 high\n punpcklwd m4, m5 ;packed 8, 10, 12, 14 low\n punpckhwd m5, m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(1)\n punpcklwd m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(0)\n punpckhwd m3, m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(3)\n punpcklwd m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(2)\n mova [coeffq+16*7], m3\n mova m3, [coeffq+16*6]\n punpckhwd m7, m3, m2 ;packed 1, 3, 5, 7 high\n punpcklwd m3, m2 ;packed 1, 3, 5, 7 low\n punpckhwd m2, m0, m1 ;packed 0, 2, 4, 6 high\n punpcklwd m0, m1 ;packed 0, 2, 4, 6 low\n punpckhwd m1, m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(1)\n punpcklwd m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(0)\n punpckhwd m3, m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(3)\n punpcklwd m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(2)\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x4_internal).pass2)]\n\n.pass2_end:\n mova [coeffq+16*4], m4\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n lea r3, [dstq+8]\n call tx2q\n\n add coeffq, 16*4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mov dstq, r3\n jmp tx2q\n\nALIGN function_align\n.main:\n punpckhqdq m7, m0, m1 ;low:in1 high:in3\n punpcklqdq m0, m1\n punpcklqdq m1, m2, m3\n punpckhqdq m3, m2 ;low:in7 high:in5\n mova [coeffq+16*4], m7\n mova [coeffq+16*5], m3\n mova m7, [coeffq+16*7]\n punpcklqdq m2, m4, m5\n punpckhqdq m4, m5 ;low:in9 high:in11\n punpcklqdq m3, m6, m7\n punpckhqdq m7, m6 ;low:in15 high:in13\n mova [coeffq+16*6], m4\n IDCT8_1D_PACKED\n mova m6, [coeffq+16*4]\n mova m4, [coeffq+16*5]\n mova m5, [coeffq+16*6]\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*6], m3\n\n IDCT16_1D_PACKED_ODDHALF 6, 4, 5, 7, 1, 2, 3\n\n mova m1, [coeffq+16*4]\n psubsw m3, m0, m7 ;low:out15 high:out14\n paddsw m0, m7 ;low:out0 high:out1\n psubsw m7, m1, m5 ;low:out12 high:out13\n paddsw m1, m5 ;low:out3 high:out2\n mova [coeffq+16*7], m3\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*6]\n psubsw m5, m2, m4 ;low:out11 high:out10\n paddsw m2, m4 ;low:out4 high:out5\n psubsw m4, m3, m6 ;low:out8 high:out9\n paddsw m3, m6 ;low:out7 high:out6\n mova m6, m7\n ret\n\nINV_TXFM_16X4_FN adst, dct\nINV_TXFM_16X4_FN adst, adst\nINV_TXFM_16X4_FN adst, flipadst\nINV_TXFM_16X4_FN adst, identity\n\ncglobal iadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n call .main_pass1_end\n\n punpckhwd m6, m7, m0 ;packed -out11, -out15\n punpcklwd m0, m7 ;packed out0, out4\n punpcklwd m7, m3, m4 ;packed -out3, -out7\n punpckhwd m4, m3 ;packed out8, out12\n mova m1, [coeffq+16*6]\n punpcklwd m3, m1, m5 ;packed -out1, -out5\n punpckhwd m5, m1 ;packed out10, out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpckhwd m3, m2, m1 ;packed -out9, -out13\n punpcklwd m1, m2 ;packed out2, out6\n\n mova m7, [o(pw_16384)]\n\n.pass1_end:\n REPX {pmulhrsw x, m7}, m0, m1, m4, m5\n pxor m2, m2\n psubw m2, m7\n mova m7, [coeffq+16*6]\n REPX {pmulhrsw x, m2}, m7, m3, m6\n pmulhrsw m2, [coeffq+16*7]\n mova [coeffq+16*6], m7\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\nALIGN function_align\n.main:\n mova [coeffq+16*6], m0\n pshufd m0, m1, q1032\n pshufd m2, m2, q1032\n punpckhwd m1, m6, m0 ;packed in13, in2\n punpcklwd m0, m6 ;packed in3, in12\n punpckhwd m7, m5, m2 ;packed in11, in4\n punpcklwd m2, m5 ;packed in5, in10\n mova m6, [o(pd_2048)]\n ITX_MUL2X_PACK 1, 5, 6, 995, 3973 ;low:t2 high:t3\n ITX_MUL2X_PACK 7, 5, 6, 1751, 3703 ;low:t4 high:t5\n ITX_MUL2X_PACK 2, 5, 6, 3513, 2106 ;low:t10 high:t11\n ITX_MUL2X_PACK 0, 5, 6, 3857, 1380 ;low:t12 high:t13\n psubsw m5, m1, m2 ;low:t10a high:t11a\n paddsw m1, m2 ;low:t2a high:t3a\n psubsw m2, m7, m0 ;low:t12a high:t13a\n paddsw m7, m0 ;low:t4a high:t5a\n punpcklqdq m0, m5\n punpckhwd m0, m5 ;packed t10a, t11a\n punpcklqdq m5, m2\n punpckhwd m2, m5 ;packed t13a, t12a\n ITX_MUL2X_PACK 0, 5, 6, 3406, 2276 ;low:t10 high:t11\n ITX_MUL2X_PACK 2, 5, 6, 4017, 799, 1 ;low:t12 high:t13\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m7\n mova m1, [coeffq+16*6]\n mova m7, [coeffq+16*7]\n pshufd m1, m1, q1032\n pshufd m3, m3, q1032\n punpckhwd m5, m7, m1 ;packed in15, in0\n punpcklwd m1, m7 ;packed in1, in14\n punpckhwd m7, m4, m3 ;packed in9, in6\n punpcklwd m3, m4 ;packed in7, in8\n ITX_MUL2X_PACK 5, 4, 6, 201, 4091 ;low:t0 high:t1\n ITX_MUL2X_PACK 7, 4, 6, 2440, 3290 ;low:t6 high:t7\n ITX_MUL2X_PACK 3, 4, 6, 3035, 2751 ;low:t8 high:t9\n ITX_MUL2X_PACK 1, 4, 6, 4052, 601 ;low:t14 high:t15\n psubsw m4, m5, m3 ;low:t8a high:t9a\n paddsw m5, m3 ;low:t0a high:t1a\n psubsw m3, m7, m1 ;low:t14a high:t15a\n paddsw m7, m1 ;low:t6a high:t7a\n punpcklqdq m1, m4\n punpckhwd m1, m4 ;packed t8a, t9a\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t15a, t14a\n ITX_MUL2X_PACK 1, 4, 6, 799, 4017 ;low:t8 high:t9\n ITX_MUL2X_PACK 3, 4, 6, 2276, 3406, 1 ;low:t14 high:t15\n paddsw m4, m1, m2 ;low:t12a high:t13a\n psubsw m1, m2 ;low:t8a high:t9a\n psubsw m2, m0, m3 ;low:t14a high:t15a\n paddsw m0, m3 ;low:t10a high:t11a\n punpcklqdq m3, m1\n punpckhwd m3, m1 ;packed t12a, t13a\n punpcklqdq m1, m2\n punpckhwd m2, m1 ;packed t15a, t14a\n ITX_MUL2X_PACK 3, 1, 6, 1567, 3784 ;low:t12 high:t13\n ITX_MUL2X_PACK 2, 1, 6, 3784, 1567, 1 ;low:t14 high:t15\n psubsw m1, m3, m2 ;low:t14a high:t15a\n paddsw m3, m2 ;low:out2 high:-out13\n psubsw m2, m4, m0 ;low:t10 high:t11\n paddsw m0, m4 ;low:-out1 high:out14\n mova [coeffq+16*6], m0\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n psubsw m4, m5, m3 ;low:t4 high:t5\n paddsw m5, m3 ;low:t0 high:t1\n psubsw m3, m0, m7 ;low:t6 high:t7\n paddsw m0, m7 ;low:t2 high:t3\n punpcklqdq m7, m4\n punpckhwd m7, m4 ;packed t4, t5\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t7, t6\n ITX_MUL2X_PACK 7, 4, 6, 1567, 3784 ;low:t4a high:t5a\n ITX_MUL2X_PACK 3, 4, 6, 3784, 1567, 1 ;low:t6a high:t7a\n psubsw m4, m5, m0 ;low:t2a high:t3a\n paddsw m0, m5 ;low:out0 high:-out15\n psubsw m5, m7, m3 ;low:t6 high:t7\n paddsw m3, m7 ;low:-out3 high:out12\n ret\nALIGN function_align\n.main_pass1_end:\n mova m7, [o(deint_shuf1)]\n mova [coeffq+16*4], m0\n mova [coeffq+16*5], m3\n mova m0, [o(pw_2896_m2896)]\n mova m3, [o(pw_2896_2896)]\n pshufb m1, m7 ;t14a t15a\n pshufb m2, m7 ;t10 t11\n pshufb m4, m7 ;t2a t3a\n pshufb m5, m7 ;t6 t7\n pmaddwd m7, m0, m2\n pmaddwd m2, m3\n paddd m7, m6\n paddd m2, m6\n psrad m7, 12\n psrad m2, 12\n packssdw m2, m7 ;low:out6 high:-out9\n pmaddwd m7, m0, m4\n pmaddwd m4, m3\n paddd m7, m6\n paddd m4, m6\n psrad m7, 12\n psrad m4, 12\n packssdw m4, m7 ;low:-out7 high:out8\n pmaddwd m7, m3, m5\n pmaddwd m5, m0\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m7, m5 ;low:out4 high:-out11\n pmaddwd m5, m3, m1\n pmaddwd m1, m0\n paddd m5, m6\n paddd m1, m6\n psrad m5, 12\n psrad m1, 12\n packssdw m5, m1 ;low:-out5 high:out10\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n punpckhqdq m6, m2, m1 ;low:t11 high:t15a\n punpcklqdq m2, m1 ;low:t10 high:t14a\n psubsw m1, m2, m6\n paddsw m2, m6\n punpckhqdq m6, m4, m5 ;low:t3a high:t7\n punpcklqdq m4, m5 ;low:t2a high:t6\n psubsw m5, m4, m6\n paddsw m4, m6\n pmulhrsw m1, m7 ;low:-out9 high:out10\n pmulhrsw m2, m7 ;low:out6 high:-out5\n pmulhrsw m5, m7 ;low:out8 high:-out11\n pmulhrsw m4, m7 ;low:-out7 high:out4\n punpckhqdq m7, m4, m5 ;low:out4 high:-out11\n punpcklqdq m4, m5 ;low:-out7 high:out8\n punpckhqdq m5, m2, m1 ;low:-out5 high:out10\n punpcklqdq m2, m1 ;low:out6 high:-out9\n ret\n\n\nINV_TXFM_16X4_FN flipadst, dct\nINV_TXFM_16X4_FN flipadst, adst\nINV_TXFM_16X4_FN flipadst, flipadst\nINV_TXFM_16X4_FN flipadst, identity\n\ncglobal iflipadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass1_end\n\n punpcklwd m6, m7, m0 ;packed out11, out15\n punpckhwd m0, m7 ;packed -out0, -out4\n punpckhwd m7, m3, m4 ;packed out3, out7\n punpcklwd m4, m3 ;packed -out8, -out12\n mova m1, [coeffq+16*6]\n punpckhwd m3, m1, m5 ;packed out1, out5\n punpcklwd m5, m1 ;packed -out10, -out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpcklwd m3, m2, m1 ;packed out9, out13\n punpckhwd m1, m2 ;packed -out2, -out6\n\n mova m7, [o(pw_m16384)]\n jmp m(iadst_16x4_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\nINV_TXFM_16X4_FN identity, dct, 15\nINV_TXFM_16X4_FN identity, adst\nINV_TXFM_16X4_FN identity, flipadst\nINV_TXFM_16X4_FN identity, identity\n\ncglobal iidentity_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m1, [coeffq+16*6]\n mova m0, [coeffq+16*5]\n mova m2, [coeffq+16*7]\n mova m6, [o(pw_1697x16)]\n mova m7, [o(pw_16384)]\n pmulhrsw m4, m6, m1\n pmulhrsw m3, m6, m0\n pmulhrsw m5, m6, m2\n pmulhrsw m4, m7\n pmulhrsw m3, m7\n pmulhrsw m5, m7\n paddsw m1, m4\n paddsw m0, m3\n paddsw m5, m2\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mova m4, [coeffq+16*4]\n mova [coeffq+16*6], m1\n mova [coeffq+16*5], m0\n mova [coeffq+16*7], m5\n pmulhrsw m0, m6, m2\n pmulhrsw m1, m6, m3\n pmulhrsw m5, m6, m4\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n pmulhrsw m5, m7\n paddsw m2, m0\n paddsw m3, m1\n paddsw m4, m5\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pmulhrsw m5, m6, m0\n pmulhrsw m6, m1\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n paddsw m0, m5\n paddsw m1, m6\n mova m6, [coeffq+16*6]\n mova m5, [coeffq+16*5]\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpckhwd m2, m1, m3 ;packed out3, out7\n punpcklwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpckhwd m6, m5, m7 ;packed out11, out15\n punpcklwd m5, m7 ;packed out10, out14\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\n%macro SAVE_8ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n mova [%1+%2*7], m7\n%endmacro\n\n%macro INV_TXFM_8X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n psrlw m2, 3 ; pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mov r3d, 2\n.loop:\n mova m0, [o(pw_2896x8)]\n pmulhrsw m7, m0, [coeffq]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, m7, [o(pw_1697x16)]\n paddsw m7, m7\n paddsw m7, m0\n pmulhrsw m7, m1\n punpcklwd m0, m7, m7\n punpckhwd m7, m7\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end3\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n call m(iadst_8x4_internal).end3\n\n add coeffq, 16\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n add coeffq, 32*4\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m3, [coeffq+32*2]\n punpcklwd m3, [coeffq+32*3]\n mova m4, [o(pw_2896x8)]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m0, m2\n punpckldq m1, m3\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_identity_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%endif\n%endmacro\n\nINV_TXFM_8X16_FN dct, dct, 0\nINV_TXFM_8X16_FN dct, identity, 15\nINV_TXFM_8X16_FN dct, adst\nINV_TXFM_8X16_FN dct, flipadst\n\ncglobal idct_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_8x8_internal).pass1)]\n\n.pass1:\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov [rsp+gprsize+16*11], tx2q\n lea tx2q, [o(m(idct_8x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, [rsp+gprsize+16*11]\n jmp r3\n\n.pass2:\n lea tx2q, [o(m(idct_8x16_internal).end)]\n\n.pass2_pre:\n mova [coeffq+16*2 ], m1\n mova [coeffq+16*6 ], m3\n mova [coeffq+16*10], m5\n mova [coeffq+16*14], m7\n mova m1, m2\n mova m2, m4\n mova m3, m6\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n\n.pass2_main:\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+16*2 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*10]\n mova m3, [coeffq+16*14]\n mova m4, [coeffq+16*3 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*15]\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n ret\n\nINV_TXFM_8X16_FN adst, dct\nINV_TXFM_8X16_FN adst, adst\nINV_TXFM_8X16_FN adst, flipadst\nINV_TXFM_8X16_FN adst, identity\n\ncglobal iadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(iadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN flipadst, dct\nINV_TXFM_8X16_FN flipadst, adst\nINV_TXFM_8X16_FN flipadst, flipadst\nINV_TXFM_8X16_FN flipadst, identity\n\ncglobal iflipadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x16_internal).end)]\n lea r3, [dstq+strideq*8]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n jmp m(iflipadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN identity, dct, 7\nINV_TXFM_8X16_FN identity, adst\nINV_TXFM_8X16_FN identity, flipadst\nINV_TXFM_8X16_FN identity, identity\n\ncglobal iidentity_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_8x16_internal).pass1_end)]\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, r3\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m6\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*2], m5\n IDTX16 6, 5, 7\n mova m5, [rsp+gprsize+16*0]\n IDTX16 5, 7, 7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [rsp+gprsize+16*2]\n mova [rsp+gprsize+16*0], m5\n mova [rsp+gprsize+16*1], m6\n mova [rsp+gprsize+16*2], m7\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\n%macro INV_TXFM_16X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x8, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x8).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m7, [coeffq]\n mova m0, [o(pw_2896x8)]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 2 ; pw_4096\n pmulhrsw m7, m1\n punpcklwd m3, m7, m7\n punpckhwd m7, m7\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea r3, [dstq+strideq*4]\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n call m(iadst_8x4_internal).end2\n mov dstq, r3\n add coeffq, 16*4\n pshufd m0, m7, q0000\n pshufd m1, m7, q1111\n pshufd m2, m7, q2222\n pshufd m3, m7, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_2896x8)]\n mova m5, [o(pw_1697x16)]\n mova m6, [o(pw_16384)]\n psrlw m7, m6, 3 ; pw_2048\n mov r3d, 2\n.main_loop:\n mova m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n mova m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n punpckldq m0, m1\n mova m1, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n mova m2, [coeffq+16*6]\n punpcklwd m2, [coeffq+16*7]\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m1, m5, m0\n pmulhrsw m1, m6\n paddsw m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m7\n.end:\n pxor m1, m1\n REPX {mova [coeffq+16*x], m1}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16*8\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X8_FN dct, dct, 0\nINV_TXFM_16X8_FN dct, identity, 7\nINV_TXFM_16X8_FN dct, adst\nINV_TXFM_16X8_FN dct, flipadst\n\ncglobal idct_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*0, 32, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*1, 32, 1\n call .main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x8_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(idct_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).pass2_main\n\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n mova [rsp+gprsize*2+32*5], m5\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 0, 7, 2, 5, 6, 401, 4076 ;t8a, t15a\n ITX_MULSUB_2W 4, 3, 2, 5, 6, 3166, 2598 ;t9a, t14a\n psubsw m2, m0, m4 ;t9\n paddsw m0, m4 ;t8\n psubsw m4, m7, m3 ;t14\n paddsw m7, m3 ;t15\n ITX_MULSUB_2W 4, 2, 3, 5, 6, 1567, 3784 ;t9a, t14a\n mova m3, [rsp+gprsize*2+16*1]\n mova m5, [rsp+gprsize*2+32*5]\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+32*5], m4\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m7\n ITX_MULSUB_2W 3, 5, 7, 4, 6, 1931, 3612 ;t10a, t13a\n ITX_MULSUB_2W 2, 1, 7, 4, 6, 3920, 1189 ;t11a, t12a\n pxor m4, m4\n psubsw m7, m2, m3 ;t10\n paddsw m2, m3 ;t11\n psubsw m3, m1, m5 ;t13\n paddsw m1, m5 ;t12\n psubw m4, m7\n ITX_MULSUB_2W 4, 3, 7, 5, 6, 1567, 3784 ;t10a, t13a\n mova m7, [rsp+gprsize*2+32*5]\n psubsw m6, m0, m2 ;t11a\n paddsw m0, m2 ;t8a\n paddsw m2, m7, m4 ;t9\n psubsw m7, m4 ;t10\n mova m5, [rsp+gprsize*2+16*0]\n psubsw m4, m5, m0 ;out8\n paddsw m0, m5 ;out7\n mova [rsp+gprsize*2+32*5], m0\n mova m5, [rsp+gprsize*2+16*9]\n psubsw m0, m5, m2 ;out9\n paddsw m2, m5 ;out6\n mova [rsp+gprsize*2+16*0], m0\n mova [rsp+gprsize*2+16*9], m2\n mova m0, [rsp+gprsize*2+16*1]\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*1], m4\n psubsw m5, m0, m3 ;t13\n paddsw m0, m3 ;t14\n mova m3, [o(pd_2048)]\n psubsw m4, m2, m1 ;t12a\n paddsw m1, m2 ;t15a\n mova [rsp+gprsize*2+16*2], m1\n ITX_MULSUB_2W 5, 7, 1, 2, 3, 2896, 2896 ;t10a, t13a\n ITX_MULSUB_2W 4, 6, 1, 2, 3, 2896, 2896 ;t11, t12\n mova m3, [rsp+gprsize*2+16*8]\n psubsw m2, m3, m5 ;out10\n paddsw m3, m5 ;out5\n mova m5, [rsp+gprsize*2+16*7]\n mova [rsp+gprsize*2+16*8], m3\n psubsw m3, m5, m4 ;out11\n paddsw m5, m4 ;out4\n mova m4, [rsp+gprsize*2+16*6]\n mova [rsp+gprsize*2+16*7], m5\n paddsw m5, m4, m6 ;out3\n psubsw m4, m6 ;out12\n mova m6, [rsp+gprsize*2+16*5]\n mova [rsp+gprsize*2+16*6], m5\n psubsw m5, m6, m7 ;out13\n paddsw m6, m7 ;out2\n mova m7, [rsp+gprsize*2+16*4]\n mova [rsp+gprsize*2+16*5], m6\n psubsw m6, m7, m0 ;out14\n paddsw m7, m0 ;out1\n mova m1, [rsp+gprsize*2+16*2]\n mova m0, [rsp+gprsize*2+16*3]\n mova [rsp+gprsize*2+16*4], m7\n psubsw m7, m0, m1 ;out15\n paddsw m0, m1 ;out0\n mova [rsp+gprsize*2+16*3], m0\n mova m1, [rsp+gprsize*2+16*0]\n mova m0, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*0], m7\n ret\n\nINV_TXFM_16X8_FN adst, dct\nINV_TXFM_16X8_FN adst, adst\nINV_TXFM_16X8_FN adst, flipadst\nINV_TXFM_16X8_FN adst, identity\n\ncglobal iadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call .main\n call .main_pass1_end\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x8_internal).pass1_end)]\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).pass2_main\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m1\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 7, 0, 1, 2, 6, 995, 3973 ;t3, t2\n ITX_MULSUB_2W 3, 4, 1, 2, 6, 3513, 2106 ;t11, t10\n psubsw m1, m0, m4 ;t10a\n paddsw m0, m4 ;t2a\n psubsw m4, m7, m3 ;t11a\n paddsw m3, m7 ;t3a\n ITX_MULSUB_2W 1, 4, 7, 2, 6, 3406, 2276 ;t11, t10\n mova m2, [rsp+gprsize*2+16*0] ;in3\n mova m7, [rsp+gprsize*2+16*1] ;in4\n mova [rsp+gprsize*2+16*0], m1 ;t11\n mova [rsp+gprsize*2+16*1], m4 ;t10\n mova m1, [rsp+gprsize*2+16*2] ;in12\n mova [rsp+gprsize*2+16*2], m0 ;t2a\n ITX_MULSUB_2W 5, 7, 0, 4, 6, 1751, 3703 ;t5, t4\n ITX_MULSUB_2W 2, 1, 0, 4, 6, 3857, 1380 ;t13, t12\n psubsw m0, m7, m1 ;t12a\n paddsw m1, m7 ;t4a\n psubsw m4, m5, m2 ;t13a\n paddsw m5, m2 ;t5a\n ITX_MULSUB_2W 4, 0, 7, 2, 6, 4017, 799 ;t12, t13\n mova m2, [rsp+gprsize*2+16*8] ;in1\n mova m7, [rsp+gprsize*2+16*9] ;in14\n mova [rsp+gprsize*2+16*8], m4 ;t12\n mova [rsp+gprsize*2+16*9], m0 ;t13\n mova m4, [rsp+gprsize*2+16*4] ;in9\n mova m0, [rsp+gprsize*2+16*5] ;in6\n mova [rsp+gprsize*2+16*4], m1 ;t4a\n mova [rsp+gprsize*2+16*5], m5 ;t5a\n ITX_MULSUB_2W 2, 7, 1, 5, 6, 4052, 601 ;t15, t14\n ITX_MULSUB_2W 4, 0, 1, 5, 6, 2440, 3290 ;t7, t6\n psubsw m1, m0, m7 ;t14a\n paddsw m0, m7 ;t6a\n psubsw m5, m4, m2 ;t15a\n paddsw m4, m2 ;t7a\n ITX_MULSUB_2W 5, 1, 7, 2, 6, 2276, 3406 ;t14, t15\n mova m2, [rsp+gprsize*2+16*2] ;t2a\n mova [rsp+gprsize*2+16*2], m5 ;t14\n psubsw m7, m2, m0 ;t6\n paddsw m2, m0 ;t2\n psubsw m0, m3, m4 ;t7\n paddsw m3, m4 ;t3\n ITX_MULSUB_2W 0, 7, 4, 5, 6, 3784, 1567 ;t6a, t7a\n mova m4, [rsp+gprsize*2+16*7] ;in0\n mova m5, [rsp+gprsize*2+32*5] ;in15\n mova [rsp+gprsize*2+16*7], m3 ;t3\n mova [rsp+gprsize*2+32*5], m1 ;t15\n mova m1, [rsp+gprsize*2+16*6] ;in7\n mova m3, [rsp+gprsize*2+16*3] ;in8\n mova [rsp+gprsize*2+16*6], m7 ;t7a\n mova [rsp+gprsize*2+16*3], m0 ;t6a\n ITX_MULSUB_2W 5, 4, 0, 7, 6, 201, 4091 ;t1, t0\n ITX_MULSUB_2W 1, 3, 0, 7, 6, 3035, 2751 ;t9, t8\n psubsw m0, m4, m3 ;t8a\n paddsw m4, m3 ;t0a\n psubsw m3, m5, m1 ;t9a\n paddsw m5, m1 ;t1a\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 799, 4017 ;t9, t8\n mova m1, [rsp+gprsize*2+16*4] ;t4a\n mova m7, [rsp+gprsize*2+16*5] ;t5a\n mova [rsp+gprsize*2+16*4], m3 ;t8\n mova [rsp+gprsize*2+16*5], m0 ;t9\n psubsw m0, m4, m1 ;t4\n paddsw m4, m1 ;t0\n psubsw m3, m5, m7 ;t5\n paddsw m5, m7 ;t1\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 1567, 3784 ;t5a, t4a\n mova m7, [rsp+gprsize*2+16*3] ;t6a\n psubsw m1, m4, m2 ;t2a\n paddsw m4, m2 ;out0\n mova [rsp+gprsize*2+16*3], m4 ;out0\n mova m4, [rsp+gprsize*2+16*6] ;t7a\n psubsw m2, m3, m7 ;t6\n paddsw m3, m7 ;-out3\n mova [rsp+gprsize*2+16*6], m3 ;-out3\n psubsw m3, m0, m4 ;t7\n paddsw m0, m4 ;out12\n mova [rsp+gprsize*2+16*12], m3\n mova m3, [rsp+gprsize*2+16*7] ;t3\n mova [rsp+gprsize*2+16* 7], m2 ;out4\n psubsw m2, m5, m3 ;t3a\n paddsw m5, m3 ;-out15\n mova [rsp+gprsize*2+16*11], m2\n mova m2, [rsp+gprsize*2+32*5] ;t15\n mova [rsp+gprsize*2+16*10], m1 ;-out7\n mova m1, [rsp+gprsize*2+16*0] ;t11\n mova [rsp+gprsize*2+16*0 ], m5 ;-out15\n mova m3, [rsp+gprsize*2+16*1] ;t10\n mova [rsp+gprsize*2+16*1 ], m4 ;-out11\n mova m4, [rsp+gprsize*2+16*2] ;t14\n mova [rsp+gprsize*2+16*2 ], m0 ;out12\n psubsw m0, m3, m4 ;t14a\n paddsw m3, m4 ;t10a\n psubsw m5, m1, m2 ;t15a\n paddsw m1, m2 ;t11a\n ITX_MULSUB_2W 5, 0, 2, 4, 6, 3784, 1567 ;t14, t15\n mova m2, [rsp+gprsize*2+16*4] ;t8\n mova m4, [rsp+gprsize*2+16*5] ;t9\n mova [rsp+gprsize*2+16*4], m3 ;t10a\n mova [rsp+gprsize*2+16*5], m1 ;t11a\n mova m3, [rsp+gprsize*2+16*8] ;t12\n mova m1, [rsp+gprsize*2+16*9] ;t13\n mova [rsp+gprsize*2+16*8], m5 ;t14\n mova [rsp+gprsize*2+16*9], m0 ;t15\n psubsw m5, m2, m3 ;t12a\n paddsw m2, m3 ;t8a\n psubsw m0, m4, m1 ;t13a\n paddsw m4, m1 ;t9a\n ITX_MULSUB_2W 5, 0, 1, 3, 6, 1567, 3784 ;t13, t12\n mova m6, [rsp+gprsize*2+16*4] ;t10a\n mova m1, [rsp+gprsize*2+16*5] ;t11a\n psubsw m3, m2, m6 ;t10\n paddsw m2, m6 ;-out1\n paddsw m6, m4, m1 ;out14\n psubsw m4, m1 ;t11\n mova [rsp+gprsize*2+16*14], m4\n mova [rsp+gprsize*2+16* 4], m2 ;-out1\n mova m4, [rsp+gprsize*2+16*8] ;t14\n mova m2, [rsp+gprsize*2+16*9] ;t15\n mova [rsp+gprsize*2+16* 9], m3 ;out6\n psubsw m3, m0, m4 ;t14a\n paddsw m0, m4 ;out2\n psubsw m4, m5, m2 ;t15a\n paddsw m5, m2 ;-out13\n mova [rsp+gprsize*2+16* 5], m0 ;out2\n ret\nALIGN function_align\n.main_pass1_end:\n mova m0, [rsp+gprsize*2+16*14]\n mova [rsp+gprsize*2+16*14], m5\n mova [rsp+gprsize*2+16*15], m6\n mova m5, [o(pw_2896_2896)]\n mova m6, [o(pw_2896_m2896)]\n mova m7, [o(pd_2048)]\n punpcklwd m2, m3, m4\n punpckhwd m3, m4\n pmaddwd m4, m5, m2\n pmaddwd m2, m6\n pmaddwd m1, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m4, m2, m1, m3\n REPX {psrad x, 12}, m4, m1, m2, m3\n packssdw m4, m1 ;-out5\n packssdw m2, m3 ;out10\n mova [rsp+gprsize*2+16* 8], m4\n mova m3, [rsp+gprsize*2+16* 9]\n punpcklwd m1, m3, m0\n punpckhwd m3, m0\n pmaddwd m0, m5, m1\n pmaddwd m1, m6\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m0, m1, m4, m3\n REPX {psrad x, 12}, m0, m4, m1, m3\n packssdw m0, m4 ;out6\n packssdw m1, m3 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n mova m0, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n punpcklwd m3, m0, m4\n punpckhwd m0, m4\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n pmaddwd m5, m0\n pmaddwd m0, m6\n REPX {paddd x, m7}, m4, m3, m5, m0\n REPX {psrad x, 12}, m4, m5, m3, m0\n packssdw m4, m5 ;out4\n packssdw m3, m0 ;-out11\n mova [rsp+gprsize*2+16* 7], m4\n mova m4, [rsp+gprsize*2+16*10]\n mova m5, [rsp+gprsize*2+16*11]\n punpcklwd m0, m4, m5\n punpckhwd m4, m5\n pmaddwd m5, m0, [o(pw_2896_2896)]\n pmaddwd m0, m6\n pmaddwd m6, m4\n pmaddwd m4, [o(pw_2896_2896)]\n REPX {paddd x, m7}, m5, m0, m6, m4\n REPX {psrad x, 12}, m0, m6, m5, m4\n packssdw m0, m6 ;out8\n packssdw m5, m4 ;-out7\n mova [rsp+gprsize*2+16*10], m5\n mova m4, [rsp+gprsize*2+16* 2] ;out12\n mova m5, [rsp+gprsize*2+16*14] ;-out13\n mova m6, [rsp+gprsize*2+16*15] ;out14\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n mova m1, [rsp+gprsize*2+16* 9]\n mova m2, [rsp+gprsize*2+16*14]\n paddsw m0, m1, m2\n psubsw m1, m2\n pmulhrsw m0, m7 ;out6\n pmulhrsw m1, m7 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n psubsw m2, m3, m4\n paddsw m3, m4\n pmulhrsw m2, m7 ;out10\n pmulhrsw m3, m7 ;-out5\n mova [rsp+gprsize*2+16* 8], m3\n mova m3, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n paddsw m0, m3, m4\n psubsw m3, m4\n pmulhrsw m0, m7 ;out4\n pmulhrsw m3, m7 ;-out11\n mova [rsp+gprsize*2+16* 7], m0\n mova m0, [rsp+gprsize*2+16*10]\n paddsw m4, m0, [rsp+gprsize*2+16*11]\n psubsw m0, [rsp+gprsize*2+16*11]\n pmulhrsw m4, m7 ;-out7\n pmulhrsw m0, m7 ;out8\n mova [rsp+gprsize*2+16*10], m4\n mova m4, [rsp+gprsize*2+16*2 ] ;out12\n ret\n\nINV_TXFM_16X8_FN flipadst, dct\nINV_TXFM_16X8_FN flipadst, adst\nINV_TXFM_16X8_FN flipadst, flipadst\nINV_TXFM_16X8_FN flipadst, identity\n\ncglobal iflipadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x8_internal).pass1_end)]\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).pass2_main\n\n\nINV_TXFM_16X8_FN identity, dct, 15\nINV_TXFM_16X8_FN identity, adst\nINV_TXFM_16X8_FN identity, flipadst\nINV_TXFM_16X8_FN identity, identity\n\ncglobal iidentity_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*16\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x8_internal).pass1_end)]\n\n.pass1:\n mova m0, [o(pw_2896x8)]\n mova m2, [o(pw_1697x16)]\n mova m3, [o(pw_16384)]\n sub coeffq, 8*16\n REPX {pmulhrsw x, m0}, m4, m5, m6, m7\n pmulhrsw m1, m2, m4\n pmulhrsw m1, m3\n paddsw m1, m4 ; 1\n pmulhrsw m4, m2, m5\n pmulhrsw m4, m3\n paddsw m4, m5 ; 3\n pmulhrsw m5, m2, m6\n pmulhrsw m5, m3\n paddsw m5, m6 ; 5\n pmulhrsw m6, m2, m7\n pmulhrsw m6, m3\n paddsw m7, m6 ; 7\n pmulhrsw m6, m0, [coeffq+16*6]\n mova [rsp+gprsize+16*0], m4\n pmulhrsw m4, m2, m6\n pmulhrsw m4, m3\n paddsw m6, m4 ; 6\n pmulhrsw m4, m0, [coeffq+16*4]\n mova [rsp+gprsize+16*1], m6\n pmulhrsw m6, m2, m4\n pmulhrsw m6, m3\n paddsw m4, m6 ; 4\n pmulhrsw m6, m0, [coeffq+16*2]\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m2, m6\n pmulhrsw m2, m3\n paddsw m2, m6 ; 2\n pmulhrsw m6, m0, [o(pw_1697x16)]\n pmulhrsw m6, m3\n mova m3, [rsp+gprsize+16*0]\n paddsw m0, m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n mova [coeffq+16*1], m4\n mova [coeffq+16*3], m5\n mova [coeffq+16*5], m6\n mova [coeffq+16*7], m7\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mova [coeffq-16*7], m0\n mova [coeffq-16*5], m1\n mova [coeffq-16*3], m2\n mova [coeffq-16*1], m3\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea tx2q, [o(m(iidentity_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iidentity_8x8_internal).end\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iidentity_8x8_internal).end\n\n\n%macro INV_TXFM_16X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x16).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m2, m3, [coeffq+16*0]\n pmulhrsw m3, [coeffq+16*1]\n mova m0, [o(pw_8192)]\n mova m1, [o(pw_1697x16)]\n pshuflw m4, [o(deint_shuf)], q0000 ;pb_0_1\n punpcklwd m4, m4\n pcmpeqb m5, m5\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n paddb m5, m5 ;pb_m2\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n psrlw m0, 2 ;pw_2048\n pmulhrsw m7, m1, m2\n pmulhrsw m1, m3\n paddsw m2, m2\n paddsw m3, m3\n paddsw m2, m7\n paddsw m3, m1\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n mov r3d, 8\n.loop:\n mova m1, [dstq]\n pshufb m0, m2, m4\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq], m1\n mova m1, [dstq+strideq*8]\n pshufb m0, m3, m4\n psubb m4, m5 ; += 2\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq+strideq*8], m1\n add dstq, strideq\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_2896x8)]\n mova m6, [o(pw_2048)]\n xor eobd, eobd\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end)]\n lea r3, [dstq+8]\n mov [rsp+16*0], r3\n.main:\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n add coeffq, 32*4\n punpckldq m0, m1\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n psraw m1, 1\n pavgw m0, m1\n pmulhrsw m0, m5\n pmulhrsw m0, m6\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end1)]\n add coeffq, 32*4\n mov dstq, [rsp+16*0]\n jmp .main\n.end1:\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X16_FN dct, dct, 0\nINV_TXFM_16X16_FN dct, identity, 15\nINV_TXFM_16X16_FN dct, adst\nINV_TXFM_16X16_FN dct, flipadst\n\ncglobal idct_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_16x8_internal).main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(idct_16x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*4 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*12]\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n lea tx2q, [o(m(idct_8x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_main\n\n\n%macro ITX_16X16_ADST_LOAD_ODD_COEFS 0\n mova m0, [coeffq+16*1 ]\n mova m1, [coeffq+16*3 ]\n mova m2, [coeffq+16*29]\n mova m3, [coeffq+16*31]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*13]\n mova m1, [coeffq+16*15]\n mova m2, [coeffq+16*17]\n mova m3, [coeffq+16*19]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*5 ]\n mova m1, [coeffq+16*7 ]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*11]\n mova m4, [coeffq+16*21]\n mova m5, [coeffq+16*23]\n mova m6, [coeffq+16*25]\n mova m7, [coeffq+16*27]\n%endmacro\n\n%macro ITX_16X16_ADST_LOAD_EVEN_COEFS 0\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*2 ]\n mova m2, [coeffq+16*28]\n mova m3, [coeffq+16*30]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*12]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*16]\n mova m3, [coeffq+16*18]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m4, [coeffq+16*20]\n mova m5, [coeffq+16*22]\n mova m6, [coeffq+16*24]\n mova m7, [coeffq+16*26]\n%endmacro\n\nINV_TXFM_16X16_FN adst, dct\nINV_TXFM_16X16_FN adst, adst\nINV_TXFM_16X16_FN adst, flipadst\n\ncglobal iadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iadst_16x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_main\n\n\nINV_TXFM_16X16_FN flipadst, dct\nINV_TXFM_16X16_FN flipadst, adst\nINV_TXFM_16X16_FN flipadst, flipadst\n\ncglobal iflipadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*17, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS coeffq+16* 0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x16_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n\n lea tx2q, [o(m(iflipadst_16x16_internal).end2)]\n mov dstq, r3\n jmp m(iflipadst_8x16_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n\n%macro IDTX16B 3 ; src/dst, tmp, pw_1697x16\n pmulhrsw m%2, m%3, m%1\n psraw m%2, 1\n pavgw m%1, m%2\n%endmacro\n\nINV_TXFM_16X16_FN identity, dct, 15\nINV_TXFM_16X16_FN identity, identity\n\ncglobal iidentity_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*17\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end)]\n\n.pass1:\n mova m6, [o(pw_1697x16)]\n mova m7, [coeffq+32*6]\n mova m0, [coeffq+32*0]\n mova m1, [coeffq+32*1]\n mova m2, [coeffq+32*2]\n mova m3, [coeffq+32*3]\n mova m4, [coeffq+32*4]\n REPX {IDTX16B x, 5, 6}, 7, 0, 1, 2, 3, 4\n mova m5, [coeffq+32*5]\n mova [rsp+gprsize+16*1], m7\n IDTX16B 5, 7, 6\n mova m7, [coeffq+32*7]\n IDTX16B 7, 6, 6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end1)]\n jmp .pass1\n\n.pass1_end1:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 15*16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end2)]\n jmp .pass1\n\n.pass1_end2:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea r3, [dstq+8]\n lea tx2q, [o(m(iidentity_16x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m4\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 4, 7}, 5, 6, 0, 1, 2, 3\n mova m4, [o(pw_2048)]\n pmulhrsw m5, m4\n pmulhrsw m6, m4\n mova [rsp+gprsize+16*2], m5\n mova m5, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*1], m6\n IDTX16 5, 6, 7\n mova m6, [rsp+gprsize+16*0]\n IDTX16 6, 7, 7\n REPX {pmulhrsw x, m4}, m0, m1, m2, m3, m6\n pmulhrsw m4, m5\n mova [rsp+gprsize+16*0], m6\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end2)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n.end2:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n LOAD_8ROWS coeffq, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end3)]\n mov dstq, r3\n jmp .end\n\n.end3:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\ncglobal inv_txfm_add_dct_dct_8x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_8x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 2 ;pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x32).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n\n.end:\n RET\n\n\n\ncglobal idct_8x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n cmp eobd, 106\n jle .fast\n\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1:\n mova [rsp+gprsize+16*9 ], m0 ;in24\n mova [rsp+gprsize+16*10], m4 ;in28\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_1:\n mova [rsp+gprsize+16*7 ], m0 ;in16\n mova [rsp+gprsize+16*8 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n.fast:\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n mova [rsp+gprsize+16*5 ], m0 ;in8\n mova [rsp+gprsize+16*6 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n mova m1, m4 ;in4\n mova m2, [rsp+gprsize+16*5 ] ;in8\n mova m3, [rsp+gprsize+16*6 ] ;in12\n\n cmp eobd, 106\n jg .full\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n mova m0, [rsp+gprsize+16*11]\n mova m1, [rsp+gprsize+16*12]\n mova m2, [rsp+gprsize+16*13]\n mova m3, [rsp+gprsize+16*14]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call .main_fast\n jmp .pass2\n\n.full:\n mova m4, [rsp+gprsize+16*7 ] ;in16\n mova m5, [rsp+gprsize+16*8 ] ;in20\n mova m6, [rsp+gprsize+16*9 ] ;in24\n mova m7, [rsp+gprsize+16*10] ;in28\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n call .main\n\n.pass2:\n lea r3, [o(m(idct_8x32_internal).end6)]\n\n.end:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_8x32_internal).end2)]\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, \\\n 8, 9, 10, 11, 12, 13, 14, 15, \\\n 16, 17, 18, 19, 20, 21, 22, 23, \\\n 24, 25, 26, 27, 28, 29, 30, 31\n\n jmp tx2q\n\n.end2:\n lea tx2q, [o(m(idct_8x32_internal).end3)]\n jmp m(idct_8x8_internal).end\n\n.end3:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end4)]\n jmp m(idct_8x8_internal).end\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end5)]\n jmp m(idct_8x8_internal).end\n\n.end5:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n mov tx2q, r3\n jmp m(idct_8x8_internal).end\n\n.end6:\n ret\n\nALIGN function_align\n.main_veryfast:\n mova m0, [rsp+gprsize*2+16*19] ;in1\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t30,t31\n pmulhrsw m0, [o(pw_201x8)] ;t16,t17\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*34], m3 ;t31\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*20], m3 ;t17a\n mova [rsp+gprsize*2+16*33], m0 ;t30a\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m2, m1, [o(pw_3857x8)] ;t28,t29\n pmulhrsw m1, [o(pw_m1380x8)] ;t18,t19\n mova [rsp+gprsize*2+16*22], m1 ;t19\n mova [rsp+gprsize*2+16*31], m2 ;t28\n pxor m0, m0\n psubw m0, m1\n ITX_MULSUB_2W 0, 2, 1, 3, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m0 ;t18a\n mova [rsp+gprsize*2+16*32], m2 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n pmulhrsw m3, m0, [o(pw_3973x8)] ;t26, t27\n pmulhrsw m0, [o(pw_995x8)] ;t20, t21\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*30], m3 ;t27\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m3 ;t21a\n mova [rsp+gprsize*2+16*29], m0 ;t26a\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pxor m0, m0\n mova m3, m0\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main_fast: ;bottom half is zero\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t31a\n pmulhrsw m0, [o(pw_201x8)] ;t16a\n pmulhrsw m2, m1, [o(pw_3035x8)] ;t30a\n pmulhrsw m1, [o(pw_m2751x8)] ;t17a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t17\n paddsw m0, m1 ;t16\n psubsw m5, m3, m2 ;t30\n paddsw m3, m2 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m3, m0, [o(pw_3703x8)]\n pmulhrsw m0, [o(pw_1751x8)]\n pmulhrsw m2, m1, [o(pw_3857x8)]\n pmulhrsw m1, [o(pw_m1380x8)]\n psubsw m4, m1, m0 ;t18\n paddsw m0, m1 ;t19\n psubsw m5, m2, m3 ;t29\n paddsw m3, m2 ;t28\n pxor m2, m2\n psubw m2, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m5 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n pmulhrsw m3, m0, [o(pw_3973x8)]\n pmulhrsw m0, [o(pw_995x8)]\n pmulhrsw m2, m1, [o(pw_3513x8)]\n pmulhrsw m1, [o(pw_m2106x8)]\n psubsw m4, m0, m1 ;t21\n paddsw m0, m1 ;t20\n psubsw m5, m3, m2 ;t26\n paddsw m3, m2 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pmulhrsw m3, m0, [o(pw_3290x8)]\n pmulhrsw m0, [o(pw_2440x8)]\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main:\n mova m7, [o(pd_2048)]\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n mova m2, [rsp+gprsize*2+16*33] ;in17\n mova m3, [rsp+gprsize*2+16*34] ;in31\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 201, 4091 ;t16a, t31a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3035, 2751 ;t17a, t30a\n psubsw m4, m0, m2 ;t17\n paddsw m0, m2 ;t16\n psubsw m5, m3, m1 ;t30\n paddsw m3, m1 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n mova m2, [rsp+gprsize*2+16*31] ;in25\n mova m3, [rsp+gprsize*2+16*32] ;in23\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 1751, 3703 ;t18a, t29a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3857, 1380 ;t19a, t28a\n psubsw m4, m2, m0 ;t18\n paddsw m0, m2 ;t19\n psubsw m5, m1, m3 ;t29\n paddsw m3, m1 ;t28\n pxor m2, m2\n psubw m2, m4 ;-t18\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m5 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n mova m2, [rsp+gprsize*2+16*29] ;in21\n mova m3, [rsp+gprsize*2+16*30] ;in27\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 995, 3973 ;t20a, t27a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3513, 2106 ;t21a, t26a\n psubsw m4, m0, m2 ;t21\n paddsw m0, m2 ;t20\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m1, [rsp+gprsize*2+16*26] ;in3\n mova m2, [rsp+gprsize*2+16*27] ;in29\n mova m3, [rsp+gprsize*2+16*28] ;in19\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 2440, 3290 ;t22a, t25a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 4052, 601 ;t23a, t24a\n\n.main2:\n psubsw m4, m2, m0 ;t22\n paddsw m0, m2 ;t23\n psubsw m5, m1, m3 ;t25\n paddsw m3, m1 ;t24\n pxor m6, m6\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 3406, 2276 ;t22a, t25a\n\n mova m4, [rsp+gprsize*2+16*24] ;t21a\n psubsw m1, m2, m4 ;t21\n paddsw m2, m4 ;t22\n psubw m4, m6, m1 ;-t21\n mova [rsp+gprsize*2+16*25], m2 ;t22\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n psubsw m2, m5, m1 ;t26\n paddsw m5, m1 ;t25\n mova [rsp+gprsize*2+16*28], m5 ;t25\n ITX_MULSUB_2W 4, 2, 1, 5, 7, 1567, 3784 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m4 ;t21a\n mova [rsp+gprsize*2+16*29], m2 ;t26a\n\n mova m1, [rsp+gprsize*2+16*23] ;t20\n mova m5, [rsp+gprsize*2+16*30] ;t27\n psubsw m2, m0, m1 ;t20a\n paddsw m0, m1 ;t23a\n psubsw m4, m3, m5 ;t27a\n paddsw m3, m5 ;t24a\n psubw m6, m2 ;-t20a\n ITX_MULSUB_2W 6, 4, 1, 5, 7, 1567, 3784 ;t20, t27\n mova [rsp+gprsize*2+16*26], m0 ;t23a\n mova [rsp+gprsize*2+16*27], m3 ;t24a\n mova [rsp+gprsize*2+16*30], m4 ;t27\n\n mova m0, [rsp+gprsize*2+16*20] ;t17a\n mova m1, [rsp+gprsize*2+16*21] ;t18a\n mova m2, [rsp+gprsize*2+16*32] ;t29a\n mova m3, [rsp+gprsize*2+16*33] ;t30a\n psubsw m4, m0, m1 ;t18\n paddsw m0, m1 ;t17\n psubsw m5, m3, m2 ;t29\n paddsw m3, m2 ;t30\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t18a, t29a\n mova [rsp+gprsize*2+16*20], m0 ;t17\n mova [rsp+gprsize*2+16*21], m5 ;t18a\n mova [rsp+gprsize*2+16*32], m4 ;t29a\n mova [rsp+gprsize*2+16*33], m3 ;t30\n mova m0, [rsp+gprsize*2+16*19] ;t16\n mova m1, [rsp+gprsize*2+16*22] ;t19\n mova m2, [rsp+gprsize*2+16*31] ;t28\n mova m3, [rsp+gprsize*2+16*34] ;t31\n psubsw m4, m0, m1 ;t19a\n paddsw m0, m1 ;t16a\n psubsw m5, m3, m2 ;t28a\n paddsw m3, m2 ;t31a\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t19, t28\n mova m2, [rsp+gprsize*2+16*15] ;tmp12\n psubsw m1, m5, m6 ;t20a\n paddsw m5, m6 ;t19a\n psubsw m6, m2, m5 ;out19\n paddsw m2, m5 ;out12\n mova m5, [rsp+gprsize*2+16*30] ;t27\n mova [rsp+gprsize*2+16*22], m6 ;out19\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m6, m4, m5 ;t27a\n paddsw m4, m5 ;t28a\n ITX_MULSUB_2W 6, 1, 2, 5, 7, 2896, 2896 ;t20, t27\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp3\n psubsw m5, m2, m4 ;out28\n paddsw m2, m4 ;out3\n mova m4, [rsp+gprsize*2+16*14] ;tmp11\n mova [rsp+gprsize*2+16*31], m5 ;out28\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m5, m4, m6 ;out20\n paddsw m4, m6 ;out11\n mova m2, [rsp+gprsize*2+16*7 ] ;tmp4\n mova [rsp+gprsize*2+16*23], m5 ;out20\n mova [rsp+gprsize*2+16*14], m4 ;out11\n psubsw m5, m2, m1 ;out27\n paddsw m2, m1 ;out4\n mova m1, [rsp+gprsize*2+16*26] ;t23a\n mova m4, [rsp+gprsize*2+16*27] ;t24a\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*7 ], m2 ;out4\n psubsw m5, m0, m1 ;t23\n paddsw m0, m1 ;t16\n psubsw m2, m3, m4 ;t24\n paddsw m3, m4 ;t31\n ITX_MULSUB_2W 2, 5, 4, 6, 7, 2896, 2896 ;t23a, t24a\n mova m6, [rsp+gprsize*2+16*18] ;tmp15\n psubsw m4, m6, m0 ;out16\n paddsw m6, m0 ;out15\n mova m0, [rsp+gprsize*2+16*3 ] ;tmp0\n mova m1, [rsp+gprsize*2+16*11] ;tmp8\n mova [rsp+gprsize*2+16*18], m6 ;out15\n mova [rsp+gprsize*2+16*19], m4 ;out16\n psubsw m6, m0, m3 ;out31\n paddsw m0, m3 ;out0\n psubsw m4, m1, m2 ;out23\n paddsw m1, m2 ;out8\n mova m3, [rsp+gprsize*2+16*10] ;tmp7\n mova [rsp+gprsize*2+16*34], m6 ;out31\n mova [rsp+gprsize*2+16*11], m1 ;out8\n mova [rsp+gprsize*2+16*26], m4 ;out23\n paddsw m6, m3, m5 ;out7\n psubsw m3, m5 ;out24\n mova m1, [rsp+gprsize*2+16*20] ;t17\n mova m5, [rsp+gprsize*2+16*25] ;t22\n mova m2, [rsp+gprsize*2+16*17] ;tmp14\n mova [rsp+gprsize*2+16*27], m3 ;out24\n psubsw m4, m1, m5 ;t22a\n paddsw m1, m5 ;t17a\n psubsw m3, m2, m1 ;out17\n paddsw m2, m1 ;out14\n mova m5, [rsp+gprsize*2+16*28] ;t25\n mova m1, [rsp+gprsize*2+16*33] ;t30\n mova [rsp+gprsize*2+16*17], m2 ;out14\n mova [rsp+gprsize*2+16*20], m3 ;out17\n psubsw m2, m1, m5 ;t25a\n paddsw m1, m5 ;t30a\n ITX_MULSUB_2W 2, 4, 3, 5, 7, 2896, 2896 ;t22, t25\n mova m5, [rsp+gprsize*2+16*4 ] ;tmp1\n psubsw m3, m5, m1 ;out30\n paddsw m5, m1 ;out1\n mova m1, [rsp+gprsize*2+16*12] ;tmp9\n mova [rsp+gprsize*2+16*33], m3 ;out30\n mova [rsp+gprsize*2+16*4 ], m5 ;out1\n psubsw m3, m1, m2 ;out22\n paddsw m1, m2 ;out9\n mova m5, [rsp+gprsize*2+16*9 ] ;tmp6\n mova [rsp+gprsize*2+16*25], m3 ;out22\n mova [rsp+gprsize*2+16*12], m1 ;out9\n psubsw m3, m5, m4 ;out25\n paddsw m5, m4 ;out6\n mova m4, [rsp+gprsize*2+16*21] ;t18a\n mova m1, [rsp+gprsize*2+16*24] ;t21a\n mova m2, [rsp+gprsize*2+16*16] ;tmp13\n mova [rsp+gprsize*2+16*28], m3 ;out25\n mova [rsp+gprsize*2+16*9 ], m5 ;out6\n paddsw m3, m4, m1 ;t18\n psubsw m4, m1 ;t21\n psubsw m5, m2, m3 ;out18\n paddsw m2, m3 ;out13\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n mova m3, [rsp+gprsize*2+16*32] ;t29a\n mova [rsp+gprsize*2+16*21], m5 ;out18\n mova [rsp+gprsize*2+16*16], m2 ;out13\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t29\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 2896, 2896 ;t21a, t26a\n mova m2, [rsp+gprsize*2+16*5 ] ;tmp2\n psubsw m1, m2, m3 ;out29\n paddsw m2, m3 ;out2\n mova m3, [rsp+gprsize*2+16*13] ;tmp10\n mova [rsp+gprsize*2+16*32], m1 ;out29\n psubsw m7, m3, m5 ;out21\n paddsw m3, m5 ;out10\n mova m5, [rsp+gprsize*2+16*8 ] ;tmp5\n mova [rsp+gprsize*2+16*24], m7 ;out21\n mova [rsp+gprsize*2+16*13], m3 ;out10\n psubsw m1, m5, m4 ;out26\n paddsw m5, m4 ;out5\n mova m7, m6 ;out7\n mova m3, [rsp+gprsize*2+16*6 ] ;out3\n mova m4, [rsp+gprsize*2+16*7 ] ;out4\n mova [rsp+gprsize*2+16*29], m1 ;out26\n mova m6, [rsp+gprsize*2+16*9 ] ;out6\n mova m1, [rsp+gprsize*2+16*4 ] ;out1\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x8, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_32x8_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\ncglobal idct_32x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*1, 32\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n cmp eobd, 106\n jg .full\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n LOAD_8ROWS coeffq+16*17, 32\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass2:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x8_internal).end)]\n jmp m(idct_8x32_internal).end1\n\n.end:\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end1:\n lea r3, [dstq+8]\n lea tx2q, [o(m(idct_32x8_internal).end2)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end3:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end4)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end5:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end6)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end6:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end7:\n mov dstq, r3\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end8:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_8x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n.loop:\n LOAD_8ROWS coeffq+16*0, 64\n paddsw m6, [o(pw_5)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_5)]\n REPX {paddsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n call m(idct_8x8_internal).pass1_end3\n REPX {psraw x, 3 }, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16\n dec r3d\n jg .loop\n RET\n\ncglobal inv_txfm_add_identity_identity_32x8, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n.loop:\n LOAD_8ROWS coeffq+16*0, 16\n pmulhrsw m6, [o(pw_4096)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_4096)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n call m(idct_8x8_internal).pass1_end3\n\n mov [rsp+16*3], dstq\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n call m(idct_8x8_internal).end3\n\n add coeffq, 16*8\n mov dstq, [rsp+16*3]\n lea dstq, [dstq+8]\n dec r3d\n jg .loop\n jnc .loop\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_16x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x32).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\ncglobal idct_16x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n LOAD_8ROWS coeffq+16*1, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*5, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*33, 64 ;in8~in15\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n mova [coeffq+16*1 ], m0 ;in8\n mova [coeffq+16*5 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*32, 64 ;in0~in7\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n\n cmp eobd, 150\n jg .full\n\n mova m1, m4 ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [rsp+gprsize+16*11] ;in2\n mova m1, [rsp+gprsize+16*12] ;in6\n mova m2, [rsp+gprsize+16*13] ;in10\n mova m3, [rsp+gprsize+16*14] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n mova [coeffq+16*0 ], m0 ;in0\n mova [coeffq+16*4 ], m4 ;in4\n\n LOAD_8ROWS coeffq+16*2, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*6, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*34, 64 ;in16~in23\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n mova [coeffq+16*2 ], m0 ;in16\n mova [coeffq+16*6 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n LOAD_8ROWS coeffq+16*3, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*7, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS coeffq+16*35, 64 ;in24~in31\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n mova m6, m0 ;in24\n mova m7, m4 ;in28\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*4 ] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*6 ] ;in20\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main\n\n.pass2:\n mov [rsp+gprsize*1+16*35], eobd\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n lea r3, [o(m(idct_16x32_internal).end)]\n jmp m(idct_8x32_internal).end\n\n.end:\n mov dstq, [rsp+gprsize*2+16*35]\n mov eobd, [rsp+gprsize*1+16*35]\n add coeffq, 16*32\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*16] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*17] ;in12\n\n cmp eobd, 150\n jg .full1\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .end1\n\n.full1:\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*18] ;in20\n mova m6, [coeffq+16*3 ] ;in24\n mova m7, [coeffq+16*19] ;in26\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n mova m4, [coeffq+16*10] ;in18\n mova m5, [coeffq+16*26] ;in22\n mova m6, [coeffq+16*11] ;in26\n mova m7, [coeffq+16*27] ;in30\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n\n.end1:\n jmp m(idct_8x32_internal).pass2\n\n\n\ncglobal inv_txfm_add_dct_dct_32x16, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x16_internal)\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*11, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*19, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*27, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n add coeffq, 16\n lea r3, [o(m(idct_32x16_internal).pass1_end1)]\n.pass1:\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*2, 64, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n LOAD_8ROWS coeffq+16*34, 64, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass1_end:\n mova [rsp+gprsize+16*0 ], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+16*32, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*48, 32\n\n sub coeffq, 16\n lea r3, [o(m(idct_32x16_internal).end)]\n jmp .pass1\n\n.end:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_16x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 1\n mov r5, 2\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 278 ;if (eob > 278)\n cmovg r4, r5 ; iteration_count++\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n mov [rsp+gprsize+16*3], r4\n mov [rsp+gprsize*2+16*3], coeffq\n\n.loop:\n LOAD_8ROWS coeffq, 64, 1\n mova [rsp+16*1], m6\n pxor m6, m6\n REPX {mova [coeffq+64*x], m6}, 0, 1, 2, 3, 4, 5, 6, 7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*0], m2\n mova [rsp+16*1], m3\n mova [rsp+16*2], m4\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_16384)]\n REPX {IDTX16 x, 2, 3, 4}, 5, 6, 7, 0, 1\n mova m2, [o(pw_8192)]\n REPX {pmulhrsw x, m2}, m5, m6, m7, m0, m1\n mova m2, [rsp+16*0]\n mova [rsp+16*0], m7\n IDTX16 2, 7, 3, 4\n mova m7, [rsp+16*2]\n mova [rsp+16*2], m5\n IDTX16 7, 5, 3, 4\n mova m5, [rsp+16*1]\n mova [rsp+16*1], m6\n pmulhrsw m3, m5\n pmulhrsw m3, m4\n psrlw m4, 1 ; pw_8192\n paddsw m3, m5\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n pmulhrsw m4, m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n add coeffq, 16\n dec r3\n jg .loop\n mov coeffq, [rsp+gprsize*2+16*3]\n add coeffq, 64*8\n mov r3, [rsp+gprsize+16*3]\n xor dstq, dstq\n mov [rsp+gprsize+16*3], dstq\n mov dstq, [rsp+16*3]\n test r3, r3\n jnz .loop\n RET\n\n\ncglobal inv_txfm_add_identity_identity_32x16, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 12 ;0100b\n mov r5, 136 ;1000 1000b\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count+2\n mov r5, 34952 ;1000 1000 1000 1000b\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count += 4\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 32, 1\n REPX {paddsw x, x}, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*1], m5\n mova [rsp+16*2], m6\n mova m6, [o(pw_1697x16)]\n REPX {IDTX16 x, 5, 6}, 7, 0, 1, 2, 3, 4\n pmulhrsw m7, [o(pw_2048)]\n mova m5, [rsp+16*1]\n mova [rsp+16*0], m7\n IDTX16 5, 7, 6\n mova m7, [rsp+16*2]\n IDTX16 7, 6, 6\n mova m6, [o(pw_2048)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n mova [rsp+16*2], m5\n mova [rsp+16*1], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n pxor m7, m7\n REPX {mova [coeffq+32*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n.loop_end:\n add coeffq, 16\n shr r3, 2\n test r3, r3\n jz .ret\n test r3, 2\n jnz .loop\n mov r4, r3\n and r4, 1\n shl r4, 3\n add coeffq, r4\n add coeffq, 32*7\n mov dstq, [rsp+16*3]\n lea r4, [dstq+8]\n mov [rsp+16*3], r4\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_32x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*35], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*35], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*35]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n mova m0, [coeffq+256*0]\n mova m1, [coeffq+256*1]\n mova m2, [coeffq+256*2]\n mova m3, [coeffq+256*3]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+128*1]\n mova m1, [coeffq+128*3]\n mova m2, [coeffq+128*5]\n mova m3, [coeffq+128*7]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*35]\n mov r3, 4\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*35], r3\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*12]\n mova m2, [coeffq+16*20]\n mova m3, [coeffq+16*28]\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*13]\n mova m6, [coeffq+16*21]\n mova m7, [coeffq+16*29]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov eobd, [rsp+gprsize*1+16*35]\n test eobd, eobd\n jl .fast1\n\n.full1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n mova m4, [coeffq+16*2 ]\n mova m5, [coeffq+16*18]\n mova m6, [coeffq+16*3 ]\n mova m7, [coeffq+16*19]\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*22]\n mova m3, [coeffq+16*30]\n mova m4, [coeffq+16*7 ]\n mova m5, [coeffq+16*15]\n mova m6, [coeffq+16*23]\n mova m7, [coeffq+16*31]\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp tx2q\n\n.fast1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp tx2q\n\n.pass2_end:\n lea r3, [o(m(idct_32x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end\n\n.pass2_end1:\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg .pass2_loop\n\n ret\n\n\ncglobal inv_txfm_add_identity_identity_32x32, 4, 6, 8, 16*5, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 2\n mov r5, 4\n cmp eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n lea r3, [dstq+8]\n mov [rsp+gprsize*0+16*3], r3\n mov [rsp+gprsize*1+16*3], r4\n mov [rsp+gprsize*2+16*3], r4\n mov [rsp+gprsize*3+16*3], coeffq\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 64\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n pmulhrsw m7, [o(pw_8192)]\n mova [rsp+16*0], m7\n mova m7, [o(pw_8192)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+16*1], m6\n mova [rsp+16*2], m5\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n add coeffq, 16\n dec r3\n jg .loop\n\n mov r4, [rsp+gprsize*2+16*3]\n dec r4\n jle .ret\n\n mov dstq, [rsp+gprsize*0+16*3]\n mov coeffq, [rsp+gprsize*3+16*3]\n mov [rsp+gprsize*2+16*3], r4\n lea r3, [dstq+8]\n add coeffq, 64*8\n mov [rsp+gprsize*0+16*3], r3\n mov r3, [rsp+gprsize*1+16*3]\n mov [rsp+gprsize*3+16*3], coeffq\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_16x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x64).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\n\ncglobal idct_16x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 151\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*0, 64*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*1, 64*2\n call m(idct_16x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 2\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*67], r3\n mov eobd, [rsp+gprsize*1+16*67]\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n pxor m4, m4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n\n test eobd, eobd\n jl .fast\n\n.full:\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n mova m2, [coeffq+16*18]\n mova m3, [coeffq+16*19]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call .main\n jmp .end\n\n.fast:\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n\n call m(idct_8x32_internal).main_veryfast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n call .main_fast\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, r4\n jmp m(idct_8x32_internal).end2\n\n.end1:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n lea r3, [o(m(idct_16x64_internal).end2)]\n jmp m(idct_8x32_internal).end\n\n.end2:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n dec r3\n jg .pass2_loop\n ret\n\n\nALIGN function_align\n.main_fast:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t62,t63\n pmulhrsw m0, [o(pw_101x8)] ;t32,t33\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*66], m3 ;t63\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*36], m3 ;t33a\n mova [rsp+gprsize*2+16*65], m0 ;t62a\n\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60,t61\n pmulhrsw m1, [o(pw_m1474x8)] ;t34,t35\n mova [rsp+gprsize*2+16*38], m1 ;t35\n mova [rsp+gprsize*2+16*63], m2 ;t60\n pxor m6, m6\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 401, 4076 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m3 ;t34a\n mova [rsp+gprsize*2+16*64], m2 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t58,t59\n pmulhrsw m0, [o(pw_897x8)] ;t36,t37\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*62], m3 ;t59\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56,t57\n pmulhrsw m1, [o(pw_m700x8)] ;t38,t39\n mova [rsp+gprsize*2+16*42], m1 ;t39\n mova [rsp+gprsize*2+16*59], m2 ;t56\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 3166, 2598 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m3 ;t38a\n mova [rsp+gprsize*2+16*60], m2 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t54,t55\n pmulhrsw m0, [o(pw_501x8)] ;t40,t41\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*58], m3 ;t55\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*44], m3 ;t41a\n mova [rsp+gprsize*2+16*57], m0 ;t54a\n\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52,t53\n pmulhrsw m1, [o(pw_m1092x8)] ;t42,t43\n mova [rsp+gprsize*2+16*46], m1 ;t43\n mova [rsp+gprsize*2+16*55], m2 ;t52\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 1931, 3612 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m3 ;t42a\n mova [rsp+gprsize*2+16*56], m2 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t50,t51\n pmulhrsw m0, [o(pw_1285x8)] ;t44,t45\n mova m6, m0\n mova [rsp+gprsize*2+16*54], m3 ;t51\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m3 ;t45a\n mova [rsp+gprsize*2+16*53], m0 ;t50a\n\n mova m0, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_4085x8)] ;t48,t49\n pmulhrsw m0, [o(pw_m301x8)] ;t46,t47\n mova m4, m3\n mova m5, m0\n\n jmp .main2\n\nALIGN function_align\n.main:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n mova m1, [rsp+gprsize*2+16*65] ;in31\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t63a\n pmulhrsw m0, [o(pw_101x8)] ;t32a\n pmulhrsw m2, m1, [o(pw_2967x8)] ;t62a\n pmulhrsw m1, [o(pw_m2824x8)] ;t33a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t33\n paddsw m0, m1 ;t32\n psubsw m5, m3, m2 ;t62\n paddsw m3, m2 ;t63\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*36], m5 ;t33a\n mova [rsp+gprsize*2+16*65], m4 ;t62a\n mova [rsp+gprsize*2+16*66], m3 ;t63\n\n mova m0, [rsp+gprsize*2+16*63] ;in17\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m3, m0, [o(pw_3745x8)] ;t61a\n pmulhrsw m0, [o(pw_1660x8)] ;t34a\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60a\n pmulhrsw m1, [o(pw_m1474x8)] ;t35a\n psubsw m4, m1, m0 ;t34\n paddsw m0, m1 ;t35\n psubsw m5, m2, m3 ;t61\n paddsw m3, m2 ;t60\n pxor m6, m6\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 401, 4076 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m2 ;t34a\n mova [rsp+gprsize*2+16*38], m0 ;t35\n mova [rsp+gprsize*2+16*63], m3 ;t60\n mova [rsp+gprsize*2+16*64], m5 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n mova m1, [rsp+gprsize*2+16*61] ;in23\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t59a\n pmulhrsw m0, [o(pw_897x8)] ;t36a\n pmulhrsw m2, m1, [o(pw_3461x8)] ;t58a\n pmulhrsw m1, [o(pw_m2191x8)] ;t37a\n psubsw m4, m0, m1 ;t37\n paddsw m0, m1 ;t36\n psubsw m5, m3, m2 ;t58\n paddsw m3, m2 ;t59\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*40], m5 ;t37a\n mova [rsp+gprsize*2+16*61], m4 ;t58a\n mova [rsp+gprsize*2+16*62], m3 ;t59\n\n mova m0, [rsp+gprsize*2+16*59] ;in25\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m3, m0, [o(pw_3349x8)] ;t57a\n pmulhrsw m0, [o(pw_2359x8)] ;t38a\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56a\n pmulhrsw m1, [o(pw_m700x8)] ;t39a\n psubsw m4, m1, m0 ;t38\n paddsw m0, m1 ;t39\n psubsw m5, m2, m3 ;t57\n paddsw m3, m2 ;t56\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 3166, 2598 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m2 ;t38a\n mova [rsp+gprsize*2+16*42], m0 ;t39\n mova [rsp+gprsize*2+16*59], m3 ;t56\n mova [rsp+gprsize*2+16*60], m5 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n mova m1, [rsp+gprsize*2+16*57] ;in27\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t55a\n pmulhrsw m0, [o(pw_501x8)] ;t40a\n pmulhrsw m2, m1, [o(pw_3229x8)] ;t54a\n pmulhrsw m1, [o(pw_m2520x8)] ;t41a\n psubsw m4, m0, m1 ;t41\n paddsw m0, m1 ;t40\n psubsw m5, m3, m2 ;t54\n paddsw m3, m2 ;t55\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*44], m5 ;t41a\n mova [rsp+gprsize*2+16*57], m4 ;t54a\n mova [rsp+gprsize*2+16*58], m3 ;t55\n\n mova m0, [rsp+gprsize*2+16*55] ;in21\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m3, m0, [o(pw_3564x8)] ;t53a\n pmulhrsw m0, [o(pw_2019x8)] ;t42a\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52a\n pmulhrsw m1, [o(pw_m1092x8)] ;t43a\n psubsw m4, m1, m0 ;t42\n paddsw m0, m1 ;t43\n psubsw m5, m2, m3 ;t53\n paddsw m3, m2 ;t52\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 1931, 3612 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m2 ;t42a\n mova [rsp+gprsize*2+16*46], m0 ;t43\n mova [rsp+gprsize*2+16*55], m3 ;t52\n mova [rsp+gprsize*2+16*56], m5 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n mova m1, [rsp+gprsize*2+16*53] ;in19\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t51a\n pmulhrsw m0, [o(pw_1285x8)] ;t44a\n pmulhrsw m2, m1, [o(pw_3659x8)] ;t50a\n pmulhrsw m1, [o(pw_m1842x8)] ;t45a\n psubsw m4, m0, m1 ;t45\n paddsw m0, m1 ;t44\n psubsw m5, m3, m2 ;t50\n paddsw m3, m2 ;t51\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova m6, m0\n mova [rsp+gprsize*2+16*48], m5 ;t45a\n mova [rsp+gprsize*2+16*53], m4 ;t50a\n mova [rsp+gprsize*2+16*54], m3 ;t51\n\n mova m0, [rsp+gprsize*2+16*51] ;in29\n mova m1, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_3102x8)] ;t49a\n pmulhrsw m0, [o(pw_2675x8)] ;t46a\n pmulhrsw m2, m1, [o(pw_4085x8)] ;t48a\n pmulhrsw m1, [o(pw_m301x8)] ;t47a\n psubsw m5, m1, m0 ;t46\n paddsw m0, m1 ;t47\n psubsw m4, m2, m3 ;t49\n paddsw m3, m2 ;t48\n\nALIGN function_align\n.main2:\n pxor m2, m2\n psubw m2, m5\n ITX_MULSUB_2W 2, 4, 1, 5, 7, 3920, 1189 ;t46a, t49a\n\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m5, m0, m6 ;t44a\n paddsw m0, m6 ;t47a\n psubsw m6, m3, m1 ;t51a\n paddsw m3, m1 ;t48a\n mova [rsp+gprsize*2+16*50], m0 ;t47a\n mova [rsp+gprsize*2+16*51], m3 ;t48a\n pxor m1, m1\n psubw m3, m1, m5\n ITX_MULSUB_2W 3, 6, 0, 5, 7, 3406, 2276 ;t44, t51\n mova [rsp+gprsize*2+16*47], m3 ;t44\n mova [rsp+gprsize*2+16*54], m6 ;t51\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m3, [rsp+gprsize*2+16*53] ;t50a\n psubsw m5, m2, m0 ;t45\n paddsw m2, m0 ;t46\n psubsw m6, m4, m3 ;t50\n paddsw m4, m3 ;t49\n psubw m1, m5\n ITX_MULSUB_2W 1, 6, 0, 3, 7, 3406, 2276 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m1 ;t45a\n mova [rsp+gprsize*2+16*49], m2 ;t46\n mova [rsp+gprsize*2+16*52], m4 ;t49\n mova [rsp+gprsize*2+16*53], m6 ;t50a\n\n mova m0, [rsp+gprsize*2+16*43] ;t40\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m3, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*58] ;t55\n psubsw m4, m0, m2 ;t43a\n paddsw m0, m2 ;t40a\n psubsw m5, m1, m3 ;t52a\n paddsw m1, m3 ;t55a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t43, t52\n mova [rsp+gprsize*2+16*43], m0 ;t40a\n mova [rsp+gprsize*2+16*46], m5 ;t43\n mova [rsp+gprsize*2+16*55], m4 ;t52\n mova [rsp+gprsize*2+16*58], m1 ;t55a\n\n mova m0, [rsp+gprsize*2+16*44] ;t41a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*57] ;t54a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t41\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t54\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t42a, t53a\n mova [rsp+gprsize*2+16*44], m0 ;t41\n mova [rsp+gprsize*2+16*45], m5 ;t42a\n mova [rsp+gprsize*2+16*56], m4 ;t53a\n mova [rsp+gprsize*2+16*57], m1 ;t54\n\n mova m0, [rsp+gprsize*2+16*41] ;t38a\n mova m2, [rsp+gprsize*2+16*40] ;t37a\n mova m3, [rsp+gprsize*2+16*61] ;t58a\n mova m1, [rsp+gprsize*2+16*60] ;t57a\n psubsw m4, m0, m2 ;t37\n paddsw m0, m2 ;t38\n psubsw m5, m1, m3 ;t58\n paddsw m1, m3 ;t57\n pxor m6, m6\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 799, 4017 ;t37a, t58a\n mova [rsp+gprsize*2+16*41], m0 ;t38\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m5 ;t58a\n mova [rsp+gprsize*2+16*60], m1 ;t57\n\n mova m0, [rsp+gprsize*2+16*42] ;t39\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*59] ;t56\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t39a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t56a\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 799, 4017 ;t36, t59\n mova [rsp+gprsize*2+16*42], m0 ;t39a\n mova [rsp+gprsize*2+16*39], m3 ;t36\n mova [rsp+gprsize*2+16*62], m5 ;t59\n mova [rsp+gprsize*2+16*59], m1 ;t56a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m2, [rsp+gprsize*2+16*38] ;t35\n mova m3, [rsp+gprsize*2+16*63] ;t60\n mova m1, [rsp+gprsize*2+16*66] ;t63\n psubsw m4, m0, m2 ;t35a\n paddsw m0, m2 ;t32a\n psubsw m5, m1, m3 ;t60a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t35, t60\n mova [rsp+gprsize*2+16*35], m0 ;t32a\n mova [rsp+gprsize*2+16*38], m5 ;t35\n mova [rsp+gprsize*2+16*63], m4 ;t60\n mova [rsp+gprsize*2+16*66], m1 ;t63a\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m2, [rsp+gprsize*2+16*37] ;t34a\n mova m3, [rsp+gprsize*2+16*64] ;t61a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n psubsw m4, m0, m2 ;t34\n paddsw m0, m2 ;t33\n psubsw m5, m1, m3 ;t61\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t34a, t61a\n\n mova m2, [rsp+gprsize*2+16*41] ;t38\n mova m3, [rsp+gprsize*2+16*60] ;t57\n psubsw m6, m0, m2 ;t38a\n paddsw m0, m2 ;t33a\n psubsw m2, m1, m3 ;t57a\n paddsw m1, m3 ;t62a\n mova [rsp+gprsize*2+16*36], m0 ;t33a\n mova [rsp+gprsize*2+16*65], m1 ;t62a\n ITX_MULSUB_2W 2, 6, 0, 3, 7, 1567, 3784 ;t38, t57\n mova [rsp+gprsize*2+16*41], m2 ;t38\n mova [rsp+gprsize*2+16*60], m6 ;t57\n\n mova m2, [rsp+gprsize*2+16*40] ;t37\n mova m3, [rsp+gprsize*2+16*61] ;t58\n psubsw m0, m5, m2 ;t37\n paddsw m5, m2 ;t34\n psubsw m1, m4, m3 ;t58\n paddsw m4, m3 ;t61\n ITX_MULSUB_2W 1, 0, 2, 3, 7, 1567, 3784 ;t37a, t58a\n mova [rsp+gprsize*2+16*37], m5 ;t34\n mova [rsp+gprsize*2+16*64], m4 ;t61\n mova [rsp+gprsize*2+16*40], m1 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m0, [rsp+gprsize*2+16*38] ;t35\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*63] ;t60\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t35a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t60a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t36, t59\n mova [rsp+gprsize*2+16*38], m0 ;t35a\n mova [rsp+gprsize*2+16*39], m5 ;t36\n mova [rsp+gprsize*2+16*62], m4 ;t59\n mova [rsp+gprsize*2+16*63], m1 ;t60a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32a\n mova m2, [rsp+gprsize*2+16*42] ;t39a\n mova m3, [rsp+gprsize*2+16*59] ;t56a\n mova m1, [rsp+gprsize*2+16*66] ;t63a\n psubsw m4, m0, m2 ;t39\n paddsw m0, m2 ;t32\n psubsw m5, m1, m3 ;t56\n paddsw m1, m3 ;t63\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t39a, t56a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*42], m5 ;t39a\n mova [rsp+gprsize*2+16*59], m4 ;t56a\n mova [rsp+gprsize*2+16*66], m1 ;t63\n\n mova m0, [rsp+gprsize*2+16*50] ;t47a\n mova m2, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*51] ;t48a\n psubsw m4, m0, m2 ;t40\n paddsw m0, m2 ;t47\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t48\n pxor m6, m6\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t40a, t55a\n mova [rsp+gprsize*2+16*50], m0 ;t47\n mova [rsp+gprsize*2+16*43], m3 ;t40a\n mova [rsp+gprsize*2+16*58], m5 ;t55a\n mova [rsp+gprsize*2+16*51], m1 ;t48\n\n mova m0, [rsp+gprsize*2+16*49] ;t46\n mova m2, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*52] ;t49\n psubsw m4, m0, m2 ;t41a\n paddsw m0, m2 ;t46a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t49a\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t41, t54\n mova [rsp+gprsize*2+16*49], m0 ;t46a\n mova [rsp+gprsize*2+16*44], m3 ;t41\n mova [rsp+gprsize*2+16*57], m5 ;t54\n mova [rsp+gprsize*2+16*52], m1 ;t49a\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*53] ;t50a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t45\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t50\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t42a, t53a\n mova [rsp+gprsize*2+16*48], m0 ;t45\n mova [rsp+gprsize*2+16*45], m3 ;t42a\n mova [rsp+gprsize*2+16*56], m5 ;t53a\n mova [rsp+gprsize*2+16*53], m1 ;t50\n\n mova m0, [rsp+gprsize*2+16*47] ;t44\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m5, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m3, m0, m2 ;t43a\n paddsw m0, m2 ;t44a\n psubsw m4, m1, m5 ;t52a\n paddsw m1, m5 ;t51a\n psubw m5, m6, m3\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t43, t52\n\n mova m2, [rsp+gprsize*2+16*38] ;t35a\n mova m3, [rsp+gprsize*2+16*31] ;tmp[28]\n psubsw m6, m2, m0 ;t44\n paddsw m2, m0 ;t35\n psubsw m0, m3, m2 ;out35\n paddsw m2, m3 ;out28\n mova m3, [rsp+gprsize*2+16*63] ;t60a\n mova [rsp+gprsize*2+16*38], m0 ;out35\n mova [rsp+gprsize*2+16*31], m2 ;out28\n psubsw m0, m3, m1 ;t51\n paddsw m3, m1 ;t60\n ITX_MULSUB_2W 0, 6, 1, 2, 7, 2896, 2896 ;t44a, t51a\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp[3]\n psubsw m1, m2, m3 ;out60\n paddsw m2, m3 ;out3\n mova m3, [rsp+gprsize*2+16*22] ;tmp[19]\n mova [rsp+gprsize*2+16*63], m1 ;out60\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m1, m3, m0 ;out44\n paddsw m3, m0 ;out19\n mova m2, [rsp+gprsize*2+16*15] ;tmp[12]\n\n mova m0, [rsp+gprsize*2+16*39] ;t36\n mova [rsp+gprsize*2+16*47], m1 ;out44\n mova [rsp+gprsize*2+16*22], m3 ;out19\n mova m1, [rsp+gprsize*2+16*62] ;t59\n psubsw m3, m2, m6 ;out51\n paddsw m2, m6 ;out12\n mova [rsp+gprsize*2+16*54], m3 ;out51\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m2, m0, m5 ;t43a\n paddsw m0, m5 ;t36a\n mova m5, [rsp+gprsize*2+16*30] ;tmp[27]\n psubsw m3, m1, m4 ;t52a\n paddsw m1, m4 ;t59a\n ITX_MULSUB_2W 3, 2, 4, 6, 7, 2896, 2896 ;t43, t52\n mova m4, [rsp+gprsize*2+16*7 ] ;tmp[4 ]\n psubsw m6, m5, m0 ;out36\n paddsw m5, m0 ;out27\n psubsw m0, m4, m1 ;out59\n paddsw m4, m1 ;out4\n mova [rsp+gprsize*2+16*39], m6 ;out36\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*62], m0 ;out59\n mova [rsp+gprsize*2+16*7 ], m4 ;out4\n mova m0, [rsp+gprsize*2+16*23] ;tmp[20]\n mova m5, [rsp+gprsize*2+16*14] ;tmp[11]\n psubsw m4, m0, m3 ;out43\n paddsw m0, m3 ;out20\n psubsw m6, m5, m2 ;out52\n paddsw m5, m2 ;out11\n mova [rsp+gprsize*2+16*46], m4 ;out43\n mova [rsp+gprsize*2+16*23], m0 ;out20\n mova [rsp+gprsize*2+16*55], m6 ;out52\n mova [rsp+gprsize*2+16*14], m5 ;out11\n\n mova m0, [rsp+gprsize*2+16*40] ;t37a\n mova m5, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*61] ;t58a\n mova m2, [rsp+gprsize*2+16*29] ;tmp[26]\n psubsw m4, m0, m5 ;t42\n paddsw m0, m5 ;t37\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t58\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t43, t52\n mova m3, [rsp+gprsize*2+16*8 ] ;tmp[5 ]\n psubsw m6, m2, m0 ;out37\n paddsw m2, m0 ;out26\n psubsw m0, m3, m1 ;out58\n paddsw m3, m1 ;out5\n mova [rsp+gprsize*2+16*40], m6 ;out37\n mova [rsp+gprsize*2+16*29], m2 ;out26\n mova [rsp+gprsize*2+16*61], m0 ;out58\n mova [rsp+gprsize*2+16*8 ], m3 ;out5\n mova m0, [rsp+gprsize*2+16*24] ;tmp[21]\n mova m1, [rsp+gprsize*2+16*13] ;tmp[10]\n psubsw m2, m0, m5 ;out42\n paddsw m0, m5 ;out21\n psubsw m3, m1, m4 ;out53\n paddsw m1, m4 ;out10\n mova [rsp+gprsize*2+16*45], m2 ;out42\n mova [rsp+gprsize*2+16*24], m0 ;out21\n mova [rsp+gprsize*2+16*56], m3 ;out53\n mova [rsp+gprsize*2+16*13], m1 ;out10\n\n mova m0, [rsp+gprsize*2+16*41] ;t38\n mova m5, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*60] ;t57\n mova m2, [rsp+gprsize*2+16*28] ;tmp[25]\n psubsw m4, m0, m5 ;t41a\n paddsw m0, m5 ;t38a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t57a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t41a, t54a\n mova m3, [rsp+gprsize*2+16*9 ] ;tmp[6 ]\n psubsw m6, m2, m0 ;out38\n paddsw m2, m0 ;out25\n psubsw m0, m3, m1 ;out57\n paddsw m3, m1 ;out6\n mova [rsp+gprsize*2+16*41], m6 ;out38\n mova [rsp+gprsize*2+16*28], m2 ;out25\n mova [rsp+gprsize*2+16*60], m0 ;out57\n mova [rsp+gprsize*2+16*9 ], m3 ;out6\n mova m0, [rsp+gprsize*2+16*25] ;tmp[22]\n mova m1, [rsp+gprsize*2+16*12] ;tmp[9 ]\n psubsw m2, m0, m5 ;out41\n paddsw m0, m5 ;out22\n psubsw m3, m1, m4 ;out54\n paddsw m1, m4 ;out9\n mova [rsp+gprsize*2+16*44], m2 ;out41\n mova [rsp+gprsize*2+16*25], m0 ;out22\n mova [rsp+gprsize*2+16*57], m3 ;out54\n mova [rsp+gprsize*2+16*12], m1 ;out9\n\n mova m0, [rsp+gprsize*2+16*42] ;t39a\n mova m5, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*59] ;t56a\n mova m2, [rsp+gprsize*2+16*27] ;tmp[24]\n psubsw m4, m0, m5 ;t40\n paddsw m0, m5 ;t39\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t56\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t40a, t55a\n mova m3, [rsp+gprsize*2+16*10] ;tmp[7 ]\n psubsw m6, m2, m0 ;out39\n paddsw m2, m0 ;out24\n psubsw m0, m3, m1 ;out56\n paddsw m3, m1 ;out7\n mova [rsp+gprsize*2+16*42], m6 ;out39\n mova [rsp+gprsize*2+16*27], m2 ;out24\n mova [rsp+gprsize*2+16*59], m0 ;out56\n mova [rsp+gprsize*2+16*10], m3 ;out7\n mova m0, [rsp+gprsize*2+16*26] ;tmp[23]\n mova m1, [rsp+gprsize*2+16*11] ;tmp[8 ]\n psubsw m2, m0, m5 ;out40\n paddsw m0, m5 ;out23\n psubsw m3, m1, m4 ;out55\n paddsw m1, m4 ;out8\n mova [rsp+gprsize*2+16*43], m2 ;out40\n mova [rsp+gprsize*2+16*26], m0 ;out23\n mova [rsp+gprsize*2+16*58], m3 ;out55\n mova [rsp+gprsize*2+16*11], m1 ;out8\n\n mova m0, [rsp+gprsize*2+16*37] ;t34\n mova m5, [rsp+gprsize*2+16*48] ;t45\n mova m3, [rsp+gprsize*2+16*53] ;t50\n mova m1, [rsp+gprsize*2+16*64] ;t61\n mova m2, [rsp+gprsize*2+16*32] ;tmp[29]\n psubsw m4, m0, m5 ;t45a\n paddsw m0, m5 ;t34a\n psubsw m5, m1, m3 ;t50a\n paddsw m1, m3 ;t61a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*5 ] ;tmp[2 ]\n psubsw m6, m2, m0 ;out34\n paddsw m2, m0 ;out29\n psubsw m0, m3, m1 ;out61\n paddsw m3, m1 ;out2\n mova [rsp+gprsize*2+16*37], m6 ;out34\n mova [rsp+gprsize*2+16*32], m2 ;out29\n mova [rsp+gprsize*2+16*64], m0 ;out61\n mova [rsp+gprsize*2+16*5 ], m3 ;out2\n mova m0, [rsp+gprsize*2+16*21] ;tmp[18]\n mova m1, [rsp+gprsize*2+16*16] ;tmp[13]\n psubsw m2, m0, m5 ;out45\n paddsw m0, m5 ;out18\n psubsw m3, m1, m4 ;out50\n paddsw m1, m4 ;out13\n mova [rsp+gprsize*2+16*48], m2 ;out45\n mova [rsp+gprsize*2+16*21], m0 ;out18\n mova [rsp+gprsize*2+16*53], m3 ;out50\n mova [rsp+gprsize*2+16*16], m1 ;out13\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m5, [rsp+gprsize*2+16*49] ;t46a\n mova m3, [rsp+gprsize*2+16*52] ;t49a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n mova m2, [rsp+gprsize*2+16*33] ;tmp[30]\n psubsw m4, m0, m5 ;t46\n paddsw m0, m5 ;t33\n psubsw m5, m1, m3 ;t49\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*4 ] ;tmp[1 ]\n psubsw m6, m2, m0 ;out33\n paddsw m2, m0 ;out30\n psubsw m0, m3, m1 ;out62\n paddsw m3, m1 ;out1\n mova [rsp+gprsize*2+16*36], m6 ;out33\n mova [rsp+gprsize*2+16*33], m2 ;out30\n mova [rsp+gprsize*2+16*65], m0 ;out62\n mova [rsp+gprsize*2+16*4 ], m3 ;out1\n mova m0, [rsp+gprsize*2+16*20] ;tmp[17]\n mova m1, [rsp+gprsize*2+16*17] ;tmp[14]\n psubsw m2, m0, m5 ;out46\n paddsw m0, m5 ;out17\n psubsw m3, m1, m4 ;out49\n paddsw m1, m4 ;out14\n mova [rsp+gprsize*2+16*49], m2 ;out46\n mova [rsp+gprsize*2+16*20], m0 ;out17\n mova [rsp+gprsize*2+16*52], m3 ;out49\n mova [rsp+gprsize*2+16*17], m1 ;out14\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m5, [rsp+gprsize*2+16*50] ;t47\n mova m3, [rsp+gprsize*2+16*51] ;t48\n mova m1, [rsp+gprsize*2+16*66] ;t63\n mova m2, [rsp+gprsize*2+16*34] ;tmp[31]\n psubsw m4, m0, m5 ;t47a\n paddsw m0, m5 ;t32a\n psubsw m5, m1, m3 ;t48a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t47, t48\n mova m3, [rsp+gprsize*2+16*3 ] ;tmp[0 ]\n psubsw m6, m2, m0 ;out32\n paddsw m2, m0 ;out31\n psubsw m0, m3, m1 ;out63\n paddsw m3, m1 ;out0\n mova [rsp+gprsize*2+16*35], m6 ;out32\n mova [rsp+gprsize*2+16*34], m2 ;out31\n mova [rsp+gprsize*2+16*66], m0 ;out63\n mova [rsp+gprsize*2+16*3 ], m3 ;out0\n mova m0, [rsp+gprsize*2+16*19] ;tmp[16]\n mova m1, [rsp+gprsize*2+16*18] ;tmp[15]\n psubsw m2, m0, m5 ;out47\n paddsw m0, m5 ;out16\n psubsw m3, m1, m4 ;out48\n paddsw m1, m4 ;out15\n mova [rsp+gprsize*2+16*50], m2 ;out47\n mova [rsp+gprsize*2+16*19], m0 ;out16\n mova [rsp+gprsize*2+16*51], m3 ;out48\n mova [rsp+gprsize*2+16*18], m1 ;out15\n ret\n\n\ncglobal inv_txfm_add_dct_dct_64x16, 4, 6, 8, 16*132, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x16_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x16).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m7, m7\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n mova m5, [dstq+16*2]\n mova m6, [dstq+16*3]\n punpckhbw m2, m1, m7\n punpcklbw m1, m7\n punpckhbw m4, m3, m7\n punpcklbw m3, m7\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n punpckhbw m2, m5, m7\n punpcklbw m5, m7\n punpckhbw m4, m6, m7\n punpcklbw m6, m7\n paddw m2, m0\n paddw m5, m0\n paddw m4, m0\n paddw m6, m0\n packuswb m5, m2\n packuswb m6, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n mova [dstq+16*2], m5\n mova [dstq+16*3], m6\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\n%macro LOAD_4ROWS 2-3 0 ;src, stride, is_rect2\n\n%if %3\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [%1+%2*0]\n pmulhrsw m1, m3, [%1+%2*1]\n pmulhrsw m2, m3, [%1+%2*2]\n pmulhrsw m3, [%1+%2*3]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n%endif\n%endmacro\n\n%macro LOAD_4ROWS_H 2 ;src, stride\n mova m4, [%1+%2*0]\n mova m5, [%1+%2*1]\n mova m6, [%1+%2*2]\n mova m7, [%1+%2*3]\n%endmacro\n\ncglobal idct_64x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mov r3d, 2\n mov [rsp+gprsize*2+16*67], dstq\n lea dstq, [rsp+gprsize+16*68]\n\n.pass1_loop:\n LOAD_4ROWS coeffq+32*0, 32*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+32*4, 32*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+32*2, 32*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+32*1, 32*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+32*17, 32*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+32*24, 32\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+32*24, 32\n\n add coeffq, 16\n add dstq, 16\n dec r3d\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*2+16*67]\n sub coeffq, 32\n mov r3d, 4\n\n.pass2_loop:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop\n\n mov r3d, 4\n lea coeffq, [rsp+gprsize+16*68]\n.pass2_loop2:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end2)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end3)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end3:\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop2\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x64).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n.end:\n RET\n\n\ncglobal idct_32x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*67]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n LOAD_4ROWS coeffq, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+128*1, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x32, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\n.end:\n RET\n\ncglobal idct_64x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*4+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8, 1\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*3+16*67]\n mov eobd, [rsp+gprsize*1+16*67]\n lea dstq, [dstq+32]\n mov [rsp+gprsize*1+16*35], eobd\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n.pass2_end:\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg m(idct_32x32_internal).pass2_loop\n\n.pass2_end2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x64, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\ncglobal idct_64x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*4+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*2+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea dstq, [dstq+32]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n jmp m(idct_16x64_internal).pass2_loop\n\n.pass2_end:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x64_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n\n dec r3\n jg m(idct_16x64_internal).pass2_loop\n\n.pass2_end2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, 4\n sub dstq, 72\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n\nSECTION_RODATA 16\n\ndeint_shuf: db 0, 1, 4, 5, 8, 9, 12, 13, 2, 3, 6, 7, 10, 11, 14, 15\n\ndeint_shuf1: db 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\ndeint_shuf2: db 8, 9, 0, 1, 10, 11, 2, 3, 12, 13, 4, 5, 14, 15, 6, 7\n\n%macro COEF_PAIR 2\npw_%1_m%2: times 4 dw %1, -%2\npw_%2_%1: times 4 dw %2, %1\n%endmacro\n\n;adst4\npw_1321_3803: times 4 dw 1321, 3803\npw_2482_m1321: times 4 dw 2482, -1321\npw_3344_2482: times 4 dw 3344, 2482\npw_3344_m3803: times 4 dw 3344, -3803\npw_3344_m3344: times 4 dw 3344, -3344\npw_0_3344 times 4 dw 0, 3344\npw_m6688_m3803: times 4 dw -6688, -3803\n\nCOEF_PAIR 2896, 2896\nCOEF_PAIR 1567, 3784\nCOEF_PAIR 799, 4017\nCOEF_PAIR 3406, 2276\nCOEF_PAIR 401, 4076\nCOEF_PAIR 1931, 3612\nCOEF_PAIR 3166, 2598\nCOEF_PAIR 3920, 1189\nCOEF_PAIR 3784, 1567\nCOEF_PAIR 995, 3973\nCOEF_PAIR 1751, 3703\nCOEF_PAIR 3513, 2106\nCOEF_PAIR 3857, 1380\nCOEF_PAIR 4017, 799\nCOEF_PAIR 201, 4091\nCOEF_PAIR 2440, 3290\nCOEF_PAIR 3035, 2751\nCOEF_PAIR 4052, 601\nCOEF_PAIR 2276, 3406\n\npd_2048: times 4 dd 2048\npw_2048: times 8 dw 2048\npw_m2048: times 8 dw -2048\npw_4096: times 8 dw 4096\npw_16384: times 8 dw 16384\npw_m16384: times 8 dw -16384\npw_1697x16: times 8 dw 1697*16\npw_1697x8: times 8 dw 1697*8\npw_2896x8: times 8 dw 2896*8\npw_3344x8: times 8 dw 3344*8\npw_5793x4: times 8 dw 5793*4\npw_8192: times 8 dw 8192\npw_m8192: times 8 dw -8192\npw_5: times 8 dw 5\npw_201x8: times 8 dw 201*8\npw_4091x8: times 8 dw 4091*8\npw_m2751x8: times 8 dw -2751*8\npw_3035x8: times 8 dw 3035*8\npw_1751x8: times 8 dw 1751*8\npw_3703x8: times 8 dw 3703*8\npw_m1380x8: times 8 dw -1380*8\npw_3857x8: times 8 dw 3857*8\npw_995x8: times 8 dw 995*8\npw_3973x8: times 8 dw 3973*8\npw_m2106x8: times 8 dw -2106*8\npw_3513x8: times 8 dw 3513*8\npw_2440x8: times 8 dw 2440*8\npw_3290x8: times 8 dw 3290*8\npw_m601x8: times 8 dw -601*8\npw_4052x8: times 8 dw 4052*8\n\npw_4095x8: times 8 dw 4095*8\npw_101x8: times 8 dw 101*8\npw_2967x8: times 8 dw 2967*8\npw_m2824x8: times 8 dw -2824*8\npw_3745x8: times 8 dw 3745*8\npw_1660x8: times 8 dw 1660*8\npw_3822x8: times 8 dw 3822*8\npw_m1474x8: times 8 dw -1474*8\npw_3996x8: times 8 dw 3996*8\npw_897x8: times 8 dw 897*8\npw_3461x8: times 8 dw 3461*8\npw_m2191x8: times 8 dw -2191*8\npw_3349x8: times 8 dw 3349*8\npw_2359x8: times 8 dw 2359*8\npw_4036x8: times 8 dw 4036*8\npw_m700x8: times 8 dw -700*8\npw_4065x8: times 8 dw 4065*8\npw_501x8: times 8 dw 501*8\npw_3229x8: times 8 dw 3229*8\npw_m2520x8: times 8 dw -2520*8\npw_3564x8: times 8 dw 3564*8\npw_2019x8: times 8 dw 2019*8\npw_3948x8: times 8 dw 3948*8\npw_m1092x8: times 8 dw -1092*8\npw_3889x8: times 8 dw 3889*8\npw_1285x8: times 8 dw 1285*8\npw_3659x8: times 8 dw 3659*8\npw_m1842x8: times 8 dw -1842*8\npw_3102x8: times 8 dw 3102*8\npw_2675x8: times 8 dw 2675*8\npw_4085x8: times 8 dw 4085*8\npw_m301x8: times 8 dw -301*8\n\niadst4_dconly1a: times 2 dw 10568, 19856, 26752, 30424\niadst4_dconly1b: times 2 dw 30424, 26752, 19856, 10568\niadst4_dconly2a: dw 10568, 10568, 10568, 10568, 19856, 19856, 19856, 19856\niadst4_dconly2b: dw 26752, 26752, 26752, 26752, 30424, 30424, 30424, 30424\n\nSECTION .text\n\n%macro REPX 2-*\n %xdefine %%f(x) %1\n%rep %0 - 1\n %rotate 1\n %%f(%1)\n%endrep\n%endmacro\n\n%define m(x) mangle(private_prefix %+ _ %+ x %+ SUFFIX)\n\n%if ARCH_X86_64\n%define o(x) x\n%else\n%define o(x) r5-$$+x ; PIC\n%endif\n\n%macro WRITE_4X4 9 ;src[1-2], tmp[1-3], row[1-4]\n lea r2, [dstq+strideq*2]\n%assign %%i 1\n%rotate 5\n%rep 4\n %if %1 & 2\n CAT_XDEFINE %%row_adr, %%i, r2 + strideq*(%1&1)\n %else\n CAT_XDEFINE %%row_adr, %%i, dstq + strideq*(%1&1)\n %endif\n %assign %%i %%i + 1\n %rotate 1\n%endrep\n\n movd m%3, [%%row_adr1] ;dst0\n movd m%5, [%%row_adr2] ;dst1\n punpckldq m%3, m%5 ;high: dst1 :low: dst0\n movd m%4, [%%row_adr3] ;dst2\n movd m%5, [%%row_adr4] ;dst3\n punpckldq m%4, m%5 ;high: dst3 :low: dst2\n\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n\n paddw m%3, m%1 ;high: dst1 + out1 ;low: dst0 + out0\n paddw m%4, m%2 ;high: dst3 + out3 ;low: dst2 + out2\n\n packuswb m%3, m%4 ;high->low: dst3 + out3, dst2 + out2, dst1 + out1, dst0 + out0\n\n movd [%%row_adr1], m%3 ;store dst0 + out0\n pshuflw m%4, m%3, q1032\n movd [%%row_adr2], m%4 ;store dst1 + out1\n punpckhqdq m%3, m%3\n movd [%%row_adr3], m%3 ;store dst2 + out2\n psrlq m%3, 32\n movd [%%row_adr4], m%3 ;store dst3 + out3\n%endmacro\n\n%macro ITX4_END 4-5 2048 ; row[1-4], rnd\n%if %5\n mova m2, [o(pw_%5)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n%endif\n\n WRITE_4X4 0, 1, 2, 3, 4, %1, %2, %3, %4\n ret\n%endmacro\n\n; flags: 1 = swap, 2: coef_regs, 4: no_pack\n%macro ITX_MUL2X_PACK 5-6 0 ; dst/src, tmp[1], rnd, coef[1-2], flags\n%if %6 & 2\n pmaddwd m%2, m%4, m%1\n pmaddwd m%1, m%5\n%elif %6 & 1\n pmaddwd m%2, m%1, [o(pw_%5_%4)]\n pmaddwd m%1, [o(pw_%4_m%5)]\n%else\n pmaddwd m%2, m%1, [o(pw_%4_m%5)]\n pmaddwd m%1, [o(pw_%5_%4)]\n%endif\n paddd m%2, m%3\n paddd m%1, m%3\n psrad m%2, 12\n psrad m%1, 12\n%if %6 & 4 == 0\n packssdw m%1, m%2\n%endif\n%endmacro\n\n%macro IDCT4_1D_PACKED 0-1 ;pw_2896x8\n mova m3, [o(pd_2048)]\n punpckhwd m2, m0, m1 ;unpacked in1 in3\n punpcklwd m0, m1 ;unpacked in0 in2\n ITX_MUL2X_PACK 2, 1, 3, 1567, 3784\n ITX_MUL2X_PACK 0, 1, 3, 2896, 2896\n psubsw m1, m0, m2 ;high: out2 ;low: out3\n paddsw m0, m2 ;high: out1 ;low: out0\n%endmacro\n\n%macro INV_TXFM_FN 5+ ; type1, type2, fast_thresh, size, xmm/stack\ncglobal inv_txfm_add_%1_%2_%4, 4, 6, %5, dst, stride, coeff, eob, tx2\n %undef cmp\n %define %%p1 m(i%1_%4_internal)\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n%if has_epilogue\n%if %3 > 0\n cmp eobd, %3\n jle %%end\n%elif %3 == 0\n test eobd, eobd\n jz %%end\n%endif\n lea tx2q, [o(m(i%2_%4_internal).pass2)]\n call %%p1\n RET\n%%end:\n%else\n lea tx2q, [o(m(i%2_%4_internal).pass2)]\n%if %3 > 0\n cmp eobd, %3\n jg %%p1\n%elif %3 == 0\n test eobd, eobd\n jnz %%p1\n%else\n times ((%%end - %%p1) >> 31) & 1 jmp %%p1\nALIGN function_align\n%%end:\n%endif\n%endif\n%endmacro\n\n%macro INV_TXFM_4X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x4, 6\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddw m0, m1\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n TAIL_CALL m(iadst_4x4_internal).end\n%elifidn %1_%2, identity_dct\n mova m1, [coeffq+16*0]\n mova m2, [coeffq+16*1]\n punpcklwd m0, m1, m2\n punpckhwd m1, m2\n punpcklwd m0, m1\n punpcklqdq m0, m0\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddw m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end\n%elif %3 >= 0\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n%ifidn %1, dct\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%elifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%elifidn %1, flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd ;0\n%ifidn %2, dct\n%ifnidn %1, dct\n pmulhrsw m0, [o(pw_2896x8)]\n%else\n pmulhrsw m0, m1\n%endif\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end2\n%else ; adst / flipadst\n pmulhrsw m1, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n TAIL_CALL m(i%2_4x4_internal).end2\n%endif\n%endif\n%endmacro\n\nINIT_XMM ssse3\n\nINV_TXFM_4X4_FN dct, dct, 0\nINV_TXFM_4X4_FN dct, adst, 0\nINV_TXFM_4X4_FN dct, flipadst, 0\nINV_TXFM_4X4_FN dct, identity, 3\n\ncglobal idct_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0] ;high: in1 ;low: in0\n mova m1, [coeffq+16*1] ;high: in3 ;low in2\n\n IDCT4_1D_PACKED\n\n mova m2, [o(deint_shuf)]\n shufps m3, m0, m1, q1331\n shufps m0, m1, q0220\n pshufb m0, m2 ;high: in1 ;low: in0\n pshufb m1, m3, m2 ;high: in3 ;low :in2\n jmp tx2q\n\n.pass2:\n IDCT4_1D_PACKED\n\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2 ;memset(coeff, 0, sizeof(*coeff) * sh * sw);\n\n ITX4_END 0, 1, 3, 2\n\nINV_TXFM_4X4_FN adst, dct, 0\nINV_TXFM_4X4_FN adst, adst, 0\nINV_TXFM_4X4_FN adst, flipadst, 0\nINV_TXFM_4X4_FN adst, identity\n\ncglobal iadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call .main\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 0, 1, 2, 3\n\nALIGN function_align\n.main:\n punpcklwd m2, m0, m1 ;unpacked in0 in2\n punpckhwd m0, m1 ;unpacked in1 in3\n mova m3, m0\n pmaddwd m1, m2, [o(pw_3344_m3344)];3344 * in0 - 3344 * in2\n pmaddwd m0, [o(pw_0_3344)] ;3344 * in3\n paddd m1, m0 ;t2\n pmaddwd m0, m2, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m2, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m4, m3, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m3, [o(pw_3344_m3803)];3344 * in1 - 3803 * in3\n paddd m4, m0 ;t0 + t3\n pmaddwd m3, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m0, [o(pd_2048)]\n paddd m1, m0 ;t2 + 2048\n paddd m2, m0\n paddd m0, m4 ;t0 + t3 + 2048\n paddd m5, m2 ;t1 + t3 + 2048\n paddd m2, m4\n paddd m2, m3 ;t0 + t1 - t3 + 2048\n REPX {psrad x, 12}, m1, m0, m5, m2\n packssdw m0, m5 ;high: out1 ;low: out0\n packssdw m1, m2 ;high: out3 ;low: out3\n ret\n\nINV_TXFM_4X4_FN flipadst, dct, 0\nINV_TXFM_4X4_FN flipadst, adst, 0\nINV_TXFM_4X4_FN flipadst, flipadst, 0\nINV_TXFM_4X4_FN flipadst, identity\n\ncglobal iflipadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call m(iadst_4x4_internal).main\n punpcklwd m2, m1, m0\n punpckhwd m1, m0\n punpcklwd m0, m1, m2 ;high: in3 ;low :in2\n punpckhwd m1, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call m(iadst_4x4_internal).main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 3, 2, 1, 0\n\nINV_TXFM_4X4_FN identity, dct, 3\nINV_TXFM_4X4_FN identity, adst\nINV_TXFM_4X4_FN identity, flipadst\nINV_TXFM_4X4_FN identity, identity\n\ncglobal iidentity_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m0, m3\n pmulhrsw m3, m1\n paddw m0, m2\n paddw m1, m3\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddw m0, m2\n paddw m1, m3\n jmp m(iadst_4x4_internal).end\n\n%macro IWHT4_1D_PACKED 0\n punpckhqdq m3, m0, m1 ;low: in1 high: in3\n punpcklqdq m0, m1 ;low: in0 high: in2\n psubw m2, m0, m3 ;low: in0 - in1 high: in2 - in3\n paddw m0, m3 ;low: in0 + in1 high: in2 + in3\n punpckhqdq m2, m2 ;t2 t2\n punpcklqdq m0, m0 ;t0 t0\n psubw m1, m0, m2\n psraw m1, 1 ;t4 t4\n psubw m1, m3 ;low: t1/out2 high: t3/out1\n psubw m0, m1 ;high: out0\n paddw m2, m1 ;low: out3\n%endmacro\n\ncglobal inv_txfm_add_wht_wht_4x4, 3, 3, 4, dst, stride, coeff\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n psraw m0, 2\n psraw m1, 2\n\n IWHT4_1D_PACKED\n\n punpckhwd m0, m1\n punpcklwd m3, m1, m2\n punpckhdq m1, m0, m3\n punpckldq m0, m3\n\n IWHT4_1D_PACKED\n\n shufpd m0, m2, 0x01\n ITX4_END 0, 3, 2, 1, 0\n\n\n%macro IDCT8_1D_PACKED 0\n mova m6, [o(pd_2048)]\n punpckhwd m4, m0, m3 ;unpacked in1 in7\n punpcklwd m0, m2 ;unpacked in0 in4\n punpckhwd m2, m1 ;unpacked in5 in3\n punpcklwd m1, m3 ;unpacked in2 in6\n ITX_MUL2X_PACK 4, 3, 6, 799, 4017 ;low: t7a high: t4a\n ITX_MUL2X_PACK 2, 3, 6, 3406, 2276 ;low: t6a high: t5a\n ITX_MUL2X_PACK 1, 3, 6, 1567, 3784 ;low: t3 high: t2\n psubsw m3, m4, m2 ;low: t6a high: t5a\n paddsw m4, m2 ;low: t7 high: t4\n pshufb m3, [o(deint_shuf1)]\n ITX_MUL2X_PACK 0, 2, 6, 2896, 2896 ;low: t0 high: t1\n ITX_MUL2X_PACK 3, 2, 6, 2896, 2896 ;low: t6 high: t5\n psubsw m2, m0, m1 ;low: tmp3 high: tmp2\n paddsw m0, m1 ;low: tmp0 high: tmp1\n punpcklqdq m1, m4, m3 ;low: t7 high: t6\n punpckhqdq m4, m3 ;low: t4 high: t5\n psubsw m3, m0, m1 ;low: out7 high: out6\n paddsw m0, m1 ;low: out0 high: out1\n paddsw m1, m2, m4 ;low: out3 high: out2\n psubsw m2, m4 ;low: out4 high: out5\n%endmacro\n\n;dst1 = (src1 * coef1 - src2 * coef2 + rnd) >> 12\n;dst2 = (src1 * coef2 + src2 * coef1 + rnd) >> 12\n%macro ITX_MULSUB_2W 7-8 0 ; dst/src[1-2], tmp[1-2], rnd, coef[1-2], dst2_in_tmp1\n punpckhwd m%4, m%1, m%2\n punpcklwd m%1, m%2\n%if %7 < 8\n pmaddwd m%2, m%7, m%1\n pmaddwd m%3, m%7, m%4\n%else\n mova m%2, [o(pw_%7_%6)]\n%if %8\n pmaddwd m%3, m%1, m%2\n pmaddwd m%2, m%4\n%else\n pmaddwd m%3, m%4, m%2\n pmaddwd m%2, m%1\n%endif\n%endif\n paddd m%3, m%5\n paddd m%2, m%5\n psrad m%3, 12\n psrad m%2, 12\n%if %8\n packssdw m%3, m%2\n%else\n packssdw m%2, m%3 ;dst2\n%endif\n%if %7 < 8\n pmaddwd m%4, m%6\n pmaddwd m%1, m%6\n%elif %8\n mova m%2, [o(pw_%6_m%7)]\n pmaddwd m%4, m%2\n pmaddwd m%1, m%2\n%else\n mova m%3, [o(pw_%6_m%7)]\n pmaddwd m%4, m%3\n pmaddwd m%1, m%3\n%endif\n paddd m%4, m%5\n paddd m%1, m%5\n psrad m%4, 12\n psrad m%1, 12\n packssdw m%1, m%4 ;dst1\n%endmacro\n\n%macro IDCT4_1D 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %2, %4, %5, %6, %7, 1567, 3784, 1 ;t2, t3\n ITX_MULSUB_2W %1, %3, %4, %6, %7, 2896, 2896, 1 ;t1, t0\n psubsw m%3, m%1, m%2 ;out2\n paddsw m%2, m%1 ;out1\n paddsw m%1, m%5, m%4 ;out0\n psubsw m%4, m%5 ;out3\n%endmacro\n\n%macro WRITE_4X8 4 ;row[1-4]\n WRITE_4X4 0, 1, 4, 5, 6, %1, %2, %3, %4\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 2, 3, 4, 5, 6, %1, %2, %3, %4\n%endmacro\n\n%macro INV_4X8 0\n punpckhwd m4, m2, m3\n punpcklwd m2, m3\n punpckhwd m3, m0, m1\n punpcklwd m0, m1\n punpckhdq m1, m0, m2 ;low: in2 high: in3\n punpckldq m0, m2 ;low: in0 high: in1\n punpckldq m2, m3, m4 ;low: in4 high: in5\n punpckhdq m3, m4 ;low: in6 high: in7\n%endmacro\n\n%macro INV_TXFM_4X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x8, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_4096)]\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n movd m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n mova m2, [o(pw_2896x8)]\n punpckldq m0, m1\n pmulhrsw m0, m2\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddw m0, m1\n pmulhrsw m0, m2\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%endif\n%endif\n%endmacro\n\nINV_TXFM_4X8_FN dct, dct, 0\nINV_TXFM_4X8_FN dct, identity, 7\nINV_TXFM_4X8_FN dct, adst\nINV_TXFM_4X8_FN dct, flipadst\n\ncglobal idct_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(idct_8x4_internal).main\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n call .main\n shufps m1, m1, q1032\n shufps m3, m3, q1032\n mova m4, [o(pw_2048)]\n jmp m(iadst_4x8_internal).end2\n\nALIGN function_align\n.main:\n IDCT8_1D_PACKED\n ret\n\n\nINV_TXFM_4X8_FN adst, dct, 0\nINV_TXFM_4X8_FN adst, adst\nINV_TXFM_4X8_FN adst, flipadst\nINV_TXFM_4X8_FN adst, identity\n\ncglobal iadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n.pass1_end:\n INV_4X8\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call .main\n mova m4, [o(pw_2048)]\n pxor m5, m5\n psubw m5, m4\n\n.end:\n punpcklqdq m4, m5\n\n.end2:\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end3:\n pxor m5, m5\n mova [coeffq+16*0], m5\n mova [coeffq+16*1], m5\n mova [coeffq+16*2], m5\n mova [coeffq+16*3], m5\n\n.end4:\n WRITE_4X8 0, 1, 2, 3\n RET\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n punpckhwd m4, m3, m0 ;unpacked in7 in0\n punpckhwd m5, m2, m1 ;unpacked in5 in2\n punpcklwd m1, m2 ;unpacked in3 in4\n punpcklwd m0, m3 ;unpacked in1 in6\n ITX_MUL2X_PACK 4, 2, 6, 401, 4076 ;low: t0a high: t1a\n ITX_MUL2X_PACK 5, 2, 6, 1931, 3612 ;low: t2a high: t3a\n ITX_MUL2X_PACK 1, 2, 6, 3166, 2598 ;low: t4a high: t5a\n ITX_MUL2X_PACK 0, 2, 6, 3920, 1189 ;low: t6a high: t7a\n\n psubsw m3, m4, m1 ;low: t4 high: t5\n paddsw m4, m1 ;low: t0 high: t1\n psubsw m2, m5, m0 ;low: t6 high: t7\n paddsw m5, m0 ;low: t2 high: t3\n\n shufps m1, m3, m2, q1032\n punpckhwd m2, m1\n punpcklwd m3, m1\n ITX_MUL2X_PACK 3, 0, 6, 1567, 3784, 1 ;low: t5a high: t4a\n ITX_MUL2X_PACK 2, 0, 6, 3784, 1567 ;low: t7a high: t6a\n\n psubsw m1, m4, m5 ;low: t2 high: t3\n paddsw m4, m5 ;low: out0 high: -out7\n psubsw m5, m3, m2 ;low: t7 high: t6\n paddsw m3, m2 ;low: out6 high: -out1\n shufps m0, m4, m3, q3210 ;low: out0 high: -out1\n shufps m3, m4, q3210 ;low: out6 high: -out7\n\n mova m2, [o(pw_2896_m2896)]\n mova m7, [o(pw_2896_2896)]\n shufps m4, m1, m5, q1032 ;low: t3 high: t7\n shufps m1, m5, q3210 ;low: t2 high: t6\n punpcklwd m5, m1, m4\n punpckhwd m1, m4\n pmaddwd m4, m2, m1 ;-out5\n pmaddwd m2, m5 ; out4\n pmaddwd m1, m7 ; out2\n pmaddwd m5, m7 ;-out3\n REPX {paddd x, m6}, m4, m2, m1, m5\n REPX {psrad x, 12}, m4, m2, m1, m5\n packssdw m1, m5 ;low: out2 high: -out3\n packssdw m2, m4 ;low: out4 high: -out5\n ret\n\nINV_TXFM_4X8_FN flipadst, dct, 0\nINV_TXFM_4X8_FN flipadst, adst\nINV_TXFM_4X8_FN flipadst, flipadst\nINV_TXFM_4X8_FN flipadst, identity\n\ncglobal iflipadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n punpcklwd m4, m3, m2\n punpckhwd m3, m2\n punpcklwd m5, m1, m0\n punpckhwd m1, m0\n punpckldq m2, m3, m1 ;low: in4 high: in5\n punpckhdq m3, m1 ;low: in6 high: in7\n punpckldq m0, m4, m5 ;low: in0 high: in1\n punpckhdq m1, m4, m5 ;low: in2 high: in3\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n mova m4, m0\n mova m5, m1\n pshufd m0, m3, q1032\n pshufd m1, m2, q1032\n pshufd m2, m5, q1032\n pshufd m3, m4, q1032\n mova m5, [o(pw_2048)]\n pxor m4, m4\n psubw m4, m5\n jmp m(iadst_4x8_internal).end\n\nINV_TXFM_4X8_FN identity, dct, 3\nINV_TXFM_4X8_FN identity, adst\nINV_TXFM_4X8_FN identity, flipadst\nINV_TXFM_4X8_FN identity, identity\n\ncglobal iidentity_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddw m0, m4\n paddw m1, m5\n paddw m2, m6\n paddw m3, m7\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n mova m4, [o(pw_4096)]\n jmp m(iadst_4x8_internal).end2\n\n\n%macro WRITE_8X2 5 ;coefs[1-2], tmp[1-3]\n movq m%3, [dstq ]\n movq m%4, [dstq+strideq]\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n%ifnum %1\n paddw m%3, m%1\n%else\n paddw m%3, %1\n%endif\n%ifnum %2\n paddw m%4, m%2\n%else\n paddw m%4, %2\n%endif\n packuswb m%3, m%4\n movq [dstq ], m%3\n punpckhqdq m%3, m%3\n movq [dstq+strideq], m%3\n%endmacro\n\n%macro WRITE_8X4 7 ;coefs[1-4], tmp[1-3]\n WRITE_8X2 %1, %2, %5, %6, %7\n lea dstq, [dstq+strideq*2]\n WRITE_8X2 %3, %4, %5, %6, %7\n%endmacro\n\n%macro INV_TXFM_8X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m1, m0, [coeffq]\n pmulhrsw m1, m0\n pmulhrsw m0, m1, [o(pw_1697x8)]\n paddw m1, m0\n pmulhrsw m1, [o(pw_2048)]\n punpcklwd m1, m1\n punpckhdq m2, m1, m1\n punpckldq m1, m1\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckldq m0, m1, m1\n punpckhdq m1, m1\n%elifidn %1_%2, identity_dct\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m5, m2, m3\n punpcklwd m2, m3\n punpcklwd m0, m4\n punpcklwd m2, m5\n punpcklqdq m0, m2\n mova m4, [o(pw_2896x8)]\n pmulhrsw m0, m4\n paddw m0, m0\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n%ifidn %2, dct\n mova m2, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else ; adst / flipadst\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n%endif\n%endif\n TAIL_CALL m(iadst_8x4_internal).end2\n%endif\n%endmacro\n\nINV_TXFM_8X4_FN dct, dct, 0\nINV_TXFM_8X4_FN dct, adst, 0\nINV_TXFM_8X4_FN dct, flipadst, 0\nINV_TXFM_8X4_FN dct, identity, 3\n\ncglobal idct_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n call m(idct_4x8_internal).main\n\n mova m4, [o(deint_shuf1)]\n mova m5, [o(deint_shuf2)]\n pshufb m0, m4\n pshufb m1, m5\n pshufb m2, m4\n pshufb m3, m5\n punpckhdq m4, m0, m1\n punpckldq m0, m1\n punpckhdq m5, m2, m3\n punpckldq m2, m3\n punpckhqdq m1, m0, m2 ;in1\n punpcklqdq m0, m2 ;in0\n punpckhqdq m3, m4, m5 ;in3\n punpcklqdq m2 ,m4, m5 ;in2\n jmp tx2q\n\n.pass2:\n call .main\n jmp m(iadst_8x4_internal).end\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n IDCT4_1D 0, 1, 2, 3, 4, 5, 6\n ret\n\nINV_TXFM_8X4_FN adst, dct\nINV_TXFM_8X4_FN adst, adst\nINV_TXFM_8X4_FN adst, flipadst\nINV_TXFM_8X4_FN adst, identity\n\ncglobal iadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n pxor m5, m5\n psubsw m3, m5, m1\n psubsw m5, m4\n punpckhdq m4, m5, m3\n punpckldq m5, m3\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m5 ;in1\n punpcklwd m0, m5 ;in0\n punpcklwd m2, m3, m4 ;in2\n punpckhwd m3, m4 ;in3\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end2:\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n mova [coeffq+16*2], m6\n mova [coeffq+16*3], m6\n.end3:\n WRITE_8X4 0, 1, 2, 3, 4, 5, 6\n RET\n\nALIGN function_align\n.main:\n punpckhwd m6, m0, m2 ;unpacked in0 in2\n punpcklwd m0, m2 ;unpacked in0 in2\n punpckhwd m7, m1, m3 ;unpacked in1 in3\n punpcklwd m1, m3 ;unpacked in1 in3\n\n mova m2, [o(pw_3344_m3344)]\n mova m4, [o(pw_0_3344)]\n pmaddwd m3, m2, m6 ;3344 * in0 - 3344 * in2\n pmaddwd m5, m4, m7 ;3344 * in3\n pmaddwd m2, m0\n pmaddwd m4, m1\n paddd m3, m5\n paddd m2, m4\n mova m4, [o(pd_2048)]\n paddd m3, m4 ;t2 + 2048\n paddd m2, m4\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n\n pmaddwd m4, m0, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m0, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m3, m1, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m1, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m3, m4 ;t0 + t3\n\n pmaddwd m1, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m4, [o(pd_2048)]\n paddd m0, m4\n paddd m4, m3 ;t0 + t3 + 2048\n paddd m5, m0 ;t1 + t3 + 2048\n paddd m3, m0\n paddd m3, m1 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m3, 12 ;out3\n packssdw m0, m4, m5 ;low: out0 high: out1\n\n pmaddwd m4, m6, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m6, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m1, m7, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m7, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m1, m4 ;t0 + t3\n pmaddwd m7, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n\n mova m4, [o(pd_2048)]\n paddd m6, m4\n paddd m4, m1 ;t0 + t3 + 2048\n paddd m5, m6 ;t1 + t3 + 2048\n paddd m1, m6\n paddd m1, m7 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m1, 12 ;out3\n packssdw m3, m1 ;out3\n packssdw m4, m5 ;low: out0 high: out1\n\n punpckhqdq m1, m0, m4 ;out1\n punpcklqdq m0, m4 ;out0\n ret\n\nINV_TXFM_8X4_FN flipadst, dct\nINV_TXFM_8X4_FN flipadst, adst\nINV_TXFM_8X4_FN flipadst, flipadst\nINV_TXFM_8X4_FN flipadst, identity\n\ncglobal iflipadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m5, m3, m2\n punpcklwd m3, m2\n punpckhwd m2, m1, m0\n punpcklwd m1, m0\n\n pxor m0, m0\n psubsw m4, m0, m2\n psubsw m0, m5\n punpckhdq m2, m0, m4\n punpckldq m0, m4\n punpckhdq m4, m3, m1\n punpckldq m3, m1\n punpckhwd m1, m0, m3 ;in1\n punpcklwd m0, m3 ;in0\n punpckhwd m3, m2, m4 ;in3\n punpcklwd m2, m4 ;in2\n jmp tx2q\n\n.pass2:\n call m(iadst_8x4_internal).main\n mova m4, m0\n mova m5, m1\n mova m0, m3\n mova m1, m2\n mova m2, m5\n mova m3, m4\n jmp m(iadst_8x4_internal).end\n\nINV_TXFM_8X4_FN identity, dct, 7\nINV_TXFM_8X4_FN identity, adst\nINV_TXFM_8X4_FN identity, flipadst\nINV_TXFM_8X4_FN identity, identity\n\ncglobal iidentity_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n paddw m0, m0\n paddw m1, m1\n paddw m2, m2\n paddw m3, m3\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n punpckhdq m5, m4, m1\n punpckldq m4, m1\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m4 ;in1\n punpcklwd m0, m4 ;in0\n punpcklwd m2, m3, m5 ;in2\n punpckhwd m3, m5 ;in3\n jmp tx2q\n\n.pass2:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddw m0, m4\n paddw m1, m5\n paddw m2, m6\n paddw m3, m7\n jmp m(iadst_8x4_internal).end\n\n%macro INV_TXFM_8X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x8, 8, 16*4\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n mova m1, [o(pw_16384)]\n pmulhrsw m0, m1\n psrlw m1, 2\n pmulhrsw m0, m1\n punpckhwd m7, m0, m0\n punpcklwd m0, m0\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end2\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n TAIL_CALL m(iadst_8x4_internal).end3\n%elif %3 >= 0\n%ifidn %1, dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 3\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n.end:\n mov r3d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x8).end3)]\n.loop:\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n jmp tx2q\n.end3:\n RET\n%else ; identity\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpcklwd m0, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n punpcklwd m2, [coeffq+16*6]\n punpcklwd m3, [coeffq+16*7]\n punpcklwd m0, m2\n punpcklwd m1, m3\n punpcklwd m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n pxor m4, m4\n REPX {mova [coeffq+16*x], m4}, 0, 1, 2, 3, 4, 5, 6, 7\n jmp m(inv_txfm_add_dct_dct_8x8).end\n%endif\n%endif\n%endmacro\n\n%macro LOAD_8ROWS 2-3 0 ; src, stride, is_rect2\n%if %3\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [%1+%2*0]\n pmulhrsw m1, m7, [%1+%2*1]\n pmulhrsw m2, m7, [%1+%2*2]\n pmulhrsw m3, m7, [%1+%2*3]\n pmulhrsw m4, m7, [%1+%2*4]\n pmulhrsw m5, m7, [%1+%2*5]\n pmulhrsw m6, m7, [%1+%2*6]\n pmulhrsw m7, [%1+%2*7]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n mova m7, [%1+%2*7]\n%endif\n%endmacro\n\n%macro IDCT8_1D_ODDHALF 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %1, %4, %5, %6, %7, 799, 4017 ;t4a, t7a\n ITX_MULSUB_2W %3, %2, %5, %6, %7, 3406, 2276, 1 ;t5a, t6a\n psubsw m%2, m%4, m%5 ;t6a\n paddsw m%4, m%5 ;t7\n psubsw m%5, m%1, m%3 ;t5a\n paddsw m%1, m%3 ;t4\n ITX_MULSUB_2W %2, %5, %3, %6, %7, 2896, 2896, 1 ;t5, t6\n%endmacro\n\nINV_TXFM_8X8_FN dct, dct, 0\nINV_TXFM_8X8_FN dct, identity, 7\nINV_TXFM_8X8_FN dct, adst\nINV_TXFM_8X8_FN dct, flipadst\n\ncglobal idct_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.pass1_end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n\n.pass1_end3:\n punpcklwd m6, m1, m5 ;10 50 11 51 12 52 13 53\n punpckhwd m1, m5 ;14 54 15 55 16 56 17 57\n punpckhwd m5, m0, m4 ;04 44 05 45 06 46 07 47\n punpcklwd m0, m4 ;00 40 01 41 02 42 03 43\n punpckhwd m4, m3, m7 ;34 74 35 75 36 76 37 77\n punpcklwd m3, m7 ;30 70 31 71 32 72 33 73\n punpckhwd m7, m1, m4 ;16 36 56 76 17 37 57 77\n punpcklwd m1, m4 ;14 34 54 74 15 35 55 75\n punpckhwd m4, m6, m3 ;12 32 52 72 13 33 53 73\n punpcklwd m6, m3 ;10 30 50 70 11 31 51 71\n mova [rsp+gprsize+16*2], m6\n mova m6, [rsp+gprsize+16*1]\n punpckhwd m3, m2, m6 ;24 64 25 65 26 66 27 67\n punpcklwd m2, m6 ;20 60 21 61 22 62 23 63\n punpckhwd m6, m5, m3 ;06 26 46 66 07 27 47 67\n punpcklwd m5, m3 ;04 24 44 64 05 25 45 65\n punpckhwd m3, m0, m2 ;02 22 42 62 03 23 43 63\n punpcklwd m0, m2 ;00 20 40 60 01 21 41 61\n\n punpckhwd m2, m6, m7 ;07 17 27 37 47 57 67 77\n punpcklwd m6, m7 ;06 16 26 36 46 56 66 76\n mova [rsp+gprsize+16*0], m2\n punpcklwd m2, m3, m4 ;02 12 22 32 42 52 62 72\n punpckhwd m3, m4 ;03 13 23 33 43 53 63 73\n punpcklwd m4, m5, m1 ;04 14 24 34 44 54 64 74\n punpckhwd m5, m1 ;05 15 25 35 45 55 65 75\n mova m7, [rsp+gprsize+16*2]\n punpckhwd m1, m0, m7 ;01 11 21 31 41 51 61 71\n punpcklwd m0, m7 ;00 10 20 30 40 50 60 70\n mova m7, [rsp+gprsize+16*0]\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*0], m7\n\n.end3:\n WRITE_8X4 0, 1, 2, 3, 5, 6, 7\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 4, [rsp+gprsize+16*2], [rsp+gprsize+16*1], [rsp+gprsize+16*0], 5, 6, 7\n jmp tx2q\n\n.end4:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m1\n mova m7, [o(pd_2048)]\n IDCT4_1D 0, 2, 4, 6, 1, 3, 7\n mova m3, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m2\n mova m2, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m4\n mova m4, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m6\n IDCT8_1D_ODDHALF 3, 2, 5, 4, 1, 6, 7\n mova m6, [rsp+gprsize*2+16*0]\n psubsw m7, m0, m4 ;out7\n paddsw m0, m4 ;out0\n mova [rsp+gprsize*2+16*0], m7\n mova m1, [rsp+gprsize*2+16*2]\n psubsw m4, m6, m3 ;out4\n paddsw m3, m6 ;out3\n mova m7, [rsp+gprsize*2+16*1]\n psubsw m6, m1, m5 ;out6\n paddsw m1, m5 ;out1\n psubsw m5, m7, m2 ;out5\n paddsw m2, m7 ;out2\n ret\n\n\nINV_TXFM_8X8_FN adst, dct\nINV_TXFM_8X8_FN adst, adst\nINV_TXFM_8X8_FN adst, flipadst\nINV_TXFM_8X8_FN adst, identity\n\ncglobal iadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n call .main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).pass1_end2\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n call .main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).end2\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m4\n mova m7, [o(pd_2048)]\n ITX_MULSUB_2W 5, 2, 3, 4, 7, 1931, 3612 ;t3a, t2a\n ITX_MULSUB_2W 1, 6, 3, 4, 7, 3920, 1189 ;t7a, t6a\n paddsw m3, m2, m6 ;t2\n psubsw m2, m6 ;t6\n paddsw m4, m5, m1 ;t3\n psubsw m5, m1 ;t7\n ITX_MULSUB_2W 5, 2, 1, 6, 7, 3784, 1567 ;t6a, t7a\n\n mova m6, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m5\n mova m1, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m2\n mova m5, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m3\n ITX_MULSUB_2W 5, 0, 2, 3, 7, 401, 4076 ;t1a, t0a\n ITX_MULSUB_2W 1, 6, 2, 3, 7, 3166, 2598 ;t5a, t4a\n psubsw m2, m0, m6 ;t4\n paddsw m0, m6 ;t0\n paddsw m3, m5, m1 ;t1\n psubsw m5, m1 ;t5\n ITX_MULSUB_2W 2, 5, 1, 6, 7, 1567, 3784 ;t5a, t4a\n\n mova m7, [rsp+gprsize*2+16*0]\n paddsw m1, m3, m4 ;-out7\n psubsw m3, m4 ;t3\n mova [rsp+gprsize*2+16*0], m1\n psubsw m4, m0, m7 ;t2\n paddsw m0, m7 ;out0\n mova m6, [rsp+gprsize*2+16*2]\n mova m7, [rsp+gprsize*2+16*1]\n paddsw m1, m5, m6 ;-out1\n psubsw m5, m6 ;t6\n paddsw m6, m2, m7 ;out6\n psubsw m2, m7 ;t7\n ret\nALIGN function_align\n.main_pass1_end:\n mova [rsp+gprsize*2+16*1], m1\n mova [rsp+gprsize*2+16*2], m6\n punpckhwd m1, m4, m3\n punpcklwd m4, m3\n punpckhwd m7, m5, m2\n punpcklwd m5, m2\n mova m2, [o(pw_2896_2896)]\n mova m6, [o(pd_2048)]\n pmaddwd m3, m2, m7\n pmaddwd m2, m5\n paddd m3, m6\n paddd m2, m6\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n mova m3, [o(pw_2896_m2896)]\n pmaddwd m7, m3\n pmaddwd m5, m3\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m5, m7 ;-out5\n mova m3, [o(pw_2896_2896)]\n pmaddwd m7, m3, m1\n pmaddwd m3, m4\n paddd m7, m6\n paddd m3, m6\n psrad m7, 12\n psrad m3, 12\n packssdw m3, m7 ;-out3\n mova m7, [o(pw_2896_m2896)]\n pmaddwd m1, m7\n pmaddwd m4, m7\n paddd m1, m6\n paddd m4, m6\n psrad m1, 12\n psrad m4, 12\n packssdw m4, m1 ;-out5\n mova m1, [rsp+gprsize*2+16*1]\n mova m6, [rsp+gprsize*2+16*2]\n ret\nALIGN function_align\n.main_pass2_end:\n paddsw m7, m4, m3 ;t2 + t3\n psubsw m4, m3 ;t2 - t3\n paddsw m3, m5, m2 ;t6 + t7\n psubsw m5, m2 ;t6 - t7\n mova m2, [o(pw_2896x8)]\n pmulhrsw m4, m2 ;out4\n pmulhrsw m5, m2 ;-out5\n pmulhrsw m7, m2 ;-out3\n pmulhrsw m2, m3 ;out2\n mova m3, m7\n ret\n\nINV_TXFM_8X8_FN flipadst, dct\nINV_TXFM_8X8_FN flipadst, adst\nINV_TXFM_8X8_FN flipadst, flipadst\nINV_TXFM_8X8_FN flipadst, identity\n\ncglobal iflipadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_m16384)]\n\n.pass1_end1:\n pmulhrsw m1, m7\n mova [rsp+gprsize+16*1], m1\n mova m1, m6\n mova m6, m2\n pmulhrsw m2, m5, m7\n mova m5, m6\n mova m6, m4\n pmulhrsw m4, m3, m7\n mova m3, m6\n mova m6, m0\n mova m0, m7\n pxor m7, m7\n psubw m7, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*2], m2\n mova m2, m0\n pxor m0, m0\n psubw m0, m7\n mova m7, m2\n pmulhrsw m1, m0\n pmulhrsw m2, m5, m0\n mova [rsp+gprsize+16*1], m1\n mova m5, m4\n mova m1, m6\n pmulhrsw m4, m3, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n mova m3, m5\n mova [rsp+gprsize+16*0], m7\n jmp m(idct_8x8_internal).end3\n\nINV_TXFM_8X8_FN identity, dct, 7\nINV_TXFM_8X8_FN identity, adst\nINV_TXFM_8X8_FN identity, flipadst\nINV_TXFM_8X8_FN identity, identity\n\ncglobal iidentity_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.end:\n pmulhrsw m7, [o(pw_4096)]\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_4096)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).end3\n\n\n%macro INV_TXFM_4X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x16, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n mova m1, m0\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m1, [coeffq+16*1]\n mova m2, [o(pw_16384)]\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddw m0, m0\n paddw m1, m1\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m4\n pmulhrsw m4, m1\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhwd m6, m4, m4\n punpcklwd m4, m4\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckhdq m5, m4, m4\n punpckldq m4, m4\n punpckhdq m7, m6, m6\n punpckldq m6, m6\n mova [coeffq+16*4], m4\n TAIL_CALL m(iadst_4x16_internal).end2\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n mova m3, [o(pw_16384)]\n punpckldq m0, m1\n pmulhrsw m1, m0, [o(pw_1697x8)]\n mova m4, [o(pw_2896x8)]\n paddw m0, m1\n pmulhrsw m0, m3\n psrlw m3, 3 ; pw_2048\n pmulhrsw m0, m4\n pmulhrsw m0, m3\n punpcklqdq m0, m0\n pxor m7, m7\n REPX {mova [coeffq+32*x], m7}, 0, 1, 2, 3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, [o(pw_16384)]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mova m1, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%endif\n.end:\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n RET\n%endif\n%endmacro\n\nINV_TXFM_4X16_FN dct, dct, 0\nINV_TXFM_4X16_FN dct, identity, 15\nINV_TXFM_4X16_FN dct, adst\nINV_TXFM_4X16_FN dct, flipadst\n\ncglobal idct_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_4x8_internal).pass1)]\n\n.pass1:\n mova m0, [coeffq+16*1]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n push tx2q\n lea tx2q, [o(m(idct_4x16_internal).pass1_2)]\n jmp r3\n\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(m(idct_4x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n pop tx2q\n\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*7], m7\n jmp tx2q\n\n.pass2:\n call m(idct_16x4_internal).main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n\n.end1:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 3, 2\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 3, 2\n\n.end2:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nINV_TXFM_4X16_FN adst, dct, 0\nINV_TXFM_4X16_FN adst, adst\nINV_TXFM_4X16_FN adst, flipadst\nINV_TXFM_4X16_FN adst, identity\n\ncglobal iadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpcklqdq m6, m5, m4 ;low: -out5 high: -out7\n punpckhqdq m4, m5 ;low: out8 high: out10\n punpcklqdq m5, m7, m2 ;low: out4 high: out6\n punpckhqdq m2, m7 ;low: -out9 high: -out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpckhqdq m1, m6, m0 ;low: -out13 high: -out15\n punpcklqdq m0, m6 ;low: out0 high: out2\n punpckhqdq m6, m3, m2 ;low: out12 high: out14\n punpcklqdq m2, m3 ;low: -out1 high: -out3\n\n mova m7, [o(pw_2048)]\n\n.end1:\n REPX {pmulhrsw x, m7}, m0, m5, m4, m6\n pxor m3, m3\n psubw m3, m7\n mova m7, [coeffq+16*4]\n REPX {pmulhrsw x, m3}, m2, m7, m1\n pmulhrsw m3, [coeffq+16*5]\n mova [coeffq+16*7], m5\n\n punpckhqdq m5, m4, m7 ;low: out10 high: out11\n punpcklqdq m4, m7 ;low: out8 high: out9\n punpckhqdq m7, m6, m1 ;low: out14 high: out15\n punpcklqdq m6, m1 ;low: out12 high: out13\n punpckhqdq m1, m0, m2 ;low: out2 high: out3\n punpcklqdq m0, m2 ;low: out0 high: out1\n mova [coeffq+16*4], m4\n mova m4, [coeffq+16*7]\n punpcklqdq m2, m4, m3 ;low: out4 high: out5\n punpckhqdq m4, m3 ;low: out6 high: out7\n mova m3, m4\n\n.end2:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 2, 3\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 2, 3\n\n.end3:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\n\nINV_TXFM_4X16_FN flipadst, dct, 0\nINV_TXFM_4X16_FN flipadst, adst\nINV_TXFM_4X16_FN flipadst, flipadst\nINV_TXFM_4X16_FN flipadst, identity\n\ncglobal iflipadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpckhqdq m6, m5, m4 ;low: out5 high: out7\n punpcklqdq m4, m5 ;low: -out8 high: -out10\n punpckhqdq m5, m7, m2 ;low: -out4 high: -out6\n punpcklqdq m2, m7 ;low: out9 high: out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpcklqdq m1, m6, m0 ;low: out13 high: out15\n punpckhqdq m0, m6 ;low: -out0 high: -out2\n punpcklqdq m6, m3, m2 ;low: -out12 high: -out14\n punpckhqdq m2, m3 ;low: out1 high: out3\n\n mova m7, [o(pw_m2048)]\n jmp m(iadst_4x16_internal).end1\n\n\nINV_TXFM_4X16_FN identity, dct, 3\nINV_TXFM_4X16_FN identity, adst\nINV_TXFM_4X16_FN identity, flipadst\nINV_TXFM_4X16_FN identity, identity\n\n%macro IDTX16 3 ; src/dst, tmp, pw_1697x16\n pmulhrsw m%2, m%3, m%1\n paddw m%1, m%1\n paddw m%1, m%2\n%endmacro\n\ncglobal iidentity_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iidentity_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n mova m7, [o(pw_1697x16)]\n mova [coeffq+16*6], m6\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [coeffq+16*7]\n IDTX16 6, 7, 7\n mova [coeffq+16*7], m6\n mova m6, [coeffq+16*6]\n pmulhrsw m7, m6, [o(pw_1697x16)]\n paddw m6, m6\n paddw m6, m7\n\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n jmp m(iadst_4x16_internal).end2\n\n\n%macro INV_TXFM_16X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m3, [coeffq]\n mova m0, [o(pw_16384)]\n pmulhrsw m3, m0\n psrlw m0, 3 ; pw_2048\n pmulhrsw m1, m3, [o(pw_1697x8)]\n paddw m3, m1\n pmulhrsw m3, m0\n punpcklwd m3, m3\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_16384)]\n mova m6, [o(pw_2896x8)]\n mov r3d, 2\n psrlw m7, m5, 3 ; pw_2048\n.main_loop:\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpcklwd m0, m2\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*3]\n punpckhwd m3, m1, m2\n punpcklwd m1, m2\n punpcklwd m1, m3\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n pmulhrsw m1, m5\n paddw m0, m1\n pmulhrsw m0, m6\n pmulhrsw m0, m7\n.end:\n pxor m3, m3\n mova [coeffq+16*0], m3\n mova [coeffq+16*1], m3\n mova [coeffq+16*2], m3\n mova [coeffq+16*3], m3\n add coeffq, 16*4\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%else\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n%ifidn %2, dct\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n mov r2d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x4).end)]\n.dconly:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n.dconly_loop:\n mova m1, [dstq]\n mova m3, [dstq+strideq]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq], m1\n mova [dstq+strideq], m3\n lea dstq, [dstq+strideq*2]\n dec r2d\n jg .dconly_loop\n jmp tx2q\n.end:\n RET\n%else ; adst / flipadst\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov [coeffq], eobd\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end3\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end3\n%endif\n%endif\n%endif\n%endmacro\n\n%macro LOAD_7ROWS 2 ;src, stride\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n%endmacro\n\n%macro SAVE_7ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n%endmacro\n\n%macro IDCT16_1D_PACKED_ODDHALF 7 ;src[1-4], tmp[1-3]\n punpckhwd m%5, m%4, m%1 ;packed in13 in3\n punpcklwd m%1, m%4 ;packed in1 in15\n punpcklwd m%4, m%3, m%2 ;packed in9 in7\n punpckhwd m%2, m%3 ;packed in5 in11\n mova m%7, [o(pd_2048)]\n ITX_MUL2X_PACK %1, %6, %7, 401, 4076, 1 ;low: t8a high: t15a\n ITX_MUL2X_PACK %4, %6, %7, 3166, 2598, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %2, %6, %7, 1931, 3612, 1 ;low: t10a high: t13a\n ITX_MUL2X_PACK %5, %6, %7, 3920, 1189, 1 ;low: t11a high: t12a\n psubsw m%6, m%1, m%4 ;low: t9 high: t14\n paddsw m%1, m%4 ;low: t8 high: t15\n psubsw m%3, m%5, m%2 ;low: t10 high: t13\n paddsw m%5, m%2 ;low: t11 high: t12\n mova m%2, [o(deint_shuf2)]\n pshufb m%6, m%2\n pshufb m%3, [o(deint_shuf1)]\n pxor m%4, m%4\n psubw m%4, m%3 ;packed -t10 -t13\n ITX_MUL2X_PACK %6, %3, %7, 1567, 3784, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %4, %3, %7, 3784, 1567 ;low: t10a high: t13a\n psubsw m%3, m%1, m%5 ;low: t11a high: t12a\n paddsw m%1, m%5 ;low: t8a high: t15a\n psubsw m%5, m%6, m%4 ;low: t10 high: t13\n paddsw m%6, m%4 ;low: t9 high: t14\n pshufb m%3, m%2\n pshufb m%5, m%2\n ITX_MUL2X_PACK %3, %2, %7, 2896, 2896, 4 ;t12, t11\n ITX_MUL2X_PACK %5, %4, %7, 2896, 2896, 4 ;t13a, t10a\n packssdw m%2, m%4 ;low: t11 high: t10a\n packssdw m%3, m%5 ;low: t12 high: t13a\n punpckhqdq m%4, m%1, m%6 ;low: t15a high: t14\n punpcklqdq m%1, m%6 ;low: t8a high: t9\n%endmacro\n\nINV_TXFM_16X4_FN dct, dct, 0\nINV_TXFM_16X4_FN dct, adst, 0\nINV_TXFM_16X4_FN dct, flipadst, 0\nINV_TXFM_16X4_FN dct, identity, 3\n\ncglobal idct_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n\n.pass1_end:\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpcklwd m2, m1, m3 ;packed out3, out7\n punpckhwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpcklwd m6, m5, m7 ;packed out11, out15\n punpckhwd m5, m7 ;packed out10, out14\n\n.pass1_end2:\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*6]\n mova [coeffq+16*6], m7\n\n.pass1_end3:\n punpckhwd m7, m3, m6 ;packed 9, 11, 13, 15 high\n punpcklwd m3, m6 ;packed 9, 10, 13, 15 low\n punpckhwd m6, m4, m5 ;packed 8, 10, 12, 14 high\n punpcklwd m4, m5 ;packed 8, 10, 12, 14 low\n punpckhwd m5, m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(1)\n punpcklwd m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(0)\n punpckhwd m3, m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(3)\n punpcklwd m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(2)\n mova [coeffq+16*7], m3\n mova m3, [coeffq+16*6]\n punpckhwd m7, m3, m2 ;packed 1, 3, 5, 7 high\n punpcklwd m3, m2 ;packed 1, 3, 5, 7 low\n punpckhwd m2, m0, m1 ;packed 0, 2, 4, 6 high\n punpcklwd m0, m1 ;packed 0, 2, 4, 6 low\n punpckhwd m1, m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(1)\n punpcklwd m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(0)\n punpckhwd m3, m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(3)\n punpcklwd m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(2)\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x4_internal).pass2)]\n\n.pass2_end:\n mova [coeffq+16*4], m4\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n lea r3, [dstq+8]\n call tx2q\n\n add coeffq, 16*4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mov dstq, r3\n jmp tx2q\n\nALIGN function_align\n.main:\n punpckhqdq m7, m0, m1 ;low:in1 high:in3\n punpcklqdq m0, m1\n punpcklqdq m1, m2, m3\n punpckhqdq m3, m2 ;low:in7 high:in5\n mova [coeffq+16*4], m7\n mova [coeffq+16*5], m3\n mova m7, [coeffq+16*7]\n punpcklqdq m2, m4, m5\n punpckhqdq m4, m5 ;low:in9 high:in11\n punpcklqdq m3, m6, m7\n punpckhqdq m7, m6 ;low:in15 high:in13\n mova [coeffq+16*6], m4\n IDCT8_1D_PACKED\n mova m6, [coeffq+16*4]\n mova m4, [coeffq+16*5]\n mova m5, [coeffq+16*6]\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*6], m3\n\n IDCT16_1D_PACKED_ODDHALF 6, 4, 5, 7, 1, 2, 3\n\n mova m1, [coeffq+16*4]\n psubsw m3, m0, m7 ;low:out15 high:out14\n paddsw m0, m7 ;low:out0 high:out1\n psubsw m7, m1, m5 ;low:out12 high:out13\n paddsw m1, m5 ;low:out3 high:out2\n mova [coeffq+16*7], m3\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*6]\n psubsw m5, m2, m4 ;low:out11 high:out10\n paddsw m2, m4 ;low:out4 high:out5\n psubsw m4, m3, m6 ;low:out8 high:out9\n paddsw m3, m6 ;low:out7 high:out6\n mova m6, m7\n ret\n\nINV_TXFM_16X4_FN adst, dct\nINV_TXFM_16X4_FN adst, adst\nINV_TXFM_16X4_FN adst, flipadst\nINV_TXFM_16X4_FN adst, identity\n\ncglobal iadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n call .main_pass1_end\n\n punpckhwd m6, m7, m0 ;packed -out11, -out15\n punpcklwd m0, m7 ;packed out0, out4\n punpcklwd m7, m3, m4 ;packed -out3, -out7\n punpckhwd m4, m3 ;packed out8, out12\n mova m1, [coeffq+16*6]\n punpcklwd m3, m1, m5 ;packed -out1, -out5\n punpckhwd m5, m1 ;packed out10, out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpckhwd m3, m2, m1 ;packed -out9, -out13\n punpcklwd m1, m2 ;packed out2, out6\n\n mova m7, [o(pw_16384)]\n\n.pass1_end:\n REPX {pmulhrsw x, m7}, m0, m1, m4, m5\n pxor m2, m2\n psubw m2, m7\n mova m7, [coeffq+16*6]\n REPX {pmulhrsw x, m2}, m7, m3, m6\n pmulhrsw m2, [coeffq+16*7]\n mova [coeffq+16*6], m7\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\nALIGN function_align\n.main:\n mova [coeffq+16*6], m0\n pshufd m0, m1, q1032\n pshufd m2, m2, q1032\n punpckhwd m1, m6, m0 ;packed in13, in2\n punpcklwd m0, m6 ;packed in3, in12\n punpckhwd m7, m5, m2 ;packed in11, in4\n punpcklwd m2, m5 ;packed in5, in10\n mova m6, [o(pd_2048)]\n ITX_MUL2X_PACK 1, 5, 6, 995, 3973 ;low:t2 high:t3\n ITX_MUL2X_PACK 7, 5, 6, 1751, 3703 ;low:t4 high:t5\n ITX_MUL2X_PACK 2, 5, 6, 3513, 2106 ;low:t10 high:t11\n ITX_MUL2X_PACK 0, 5, 6, 3857, 1380 ;low:t12 high:t13\n psubsw m5, m1, m2 ;low:t10a high:t11a\n paddsw m1, m2 ;low:t2a high:t3a\n psubsw m2, m7, m0 ;low:t12a high:t13a\n paddsw m7, m0 ;low:t4a high:t5a\n punpcklqdq m0, m5\n punpckhwd m0, m5 ;packed t10a, t11a\n punpcklqdq m5, m2\n punpckhwd m2, m5 ;packed t13a, t12a\n ITX_MUL2X_PACK 0, 5, 6, 3406, 2276 ;low:t10 high:t11\n ITX_MUL2X_PACK 2, 5, 6, 4017, 799, 1 ;low:t12 high:t13\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m7\n mova m1, [coeffq+16*6]\n mova m7, [coeffq+16*7]\n pshufd m1, m1, q1032\n pshufd m3, m3, q1032\n punpckhwd m5, m7, m1 ;packed in15, in0\n punpcklwd m1, m7 ;packed in1, in14\n punpckhwd m7, m4, m3 ;packed in9, in6\n punpcklwd m3, m4 ;packed in7, in8\n ITX_MUL2X_PACK 5, 4, 6, 201, 4091 ;low:t0 high:t1\n ITX_MUL2X_PACK 7, 4, 6, 2440, 3290 ;low:t6 high:t7\n ITX_MUL2X_PACK 3, 4, 6, 3035, 2751 ;low:t8 high:t9\n ITX_MUL2X_PACK 1, 4, 6, 4052, 601 ;low:t14 high:t15\n psubsw m4, m5, m3 ;low:t8a high:t9a\n paddsw m5, m3 ;low:t0a high:t1a\n psubsw m3, m7, m1 ;low:t14a high:t15a\n paddsw m7, m1 ;low:t6a high:t7a\n punpcklqdq m1, m4\n punpckhwd m1, m4 ;packed t8a, t9a\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t15a, t14a\n ITX_MUL2X_PACK 1, 4, 6, 799, 4017 ;low:t8 high:t9\n ITX_MUL2X_PACK 3, 4, 6, 2276, 3406, 1 ;low:t14 high:t15\n paddsw m4, m1, m2 ;low:t12a high:t13a\n psubsw m1, m2 ;low:t8a high:t9a\n psubsw m2, m0, m3 ;low:t14a high:t15a\n paddsw m0, m3 ;low:t10a high:t11a\n punpcklqdq m3, m1\n punpckhwd m3, m1 ;packed t12a, t13a\n punpcklqdq m1, m2\n punpckhwd m2, m1 ;packed t15a, t14a\n ITX_MUL2X_PACK 3, 1, 6, 1567, 3784 ;low:t12 high:t13\n ITX_MUL2X_PACK 2, 1, 6, 3784, 1567, 1 ;low:t14 high:t15\n psubsw m1, m3, m2 ;low:t14a high:t15a\n paddsw m3, m2 ;low:out2 high:-out13\n psubsw m2, m4, m0 ;low:t10 high:t11\n paddsw m0, m4 ;low:-out1 high:out14\n mova [coeffq+16*6], m0\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n psubsw m4, m5, m3 ;low:t4 high:t5\n paddsw m5, m3 ;low:t0 high:t1\n psubsw m3, m0, m7 ;low:t6 high:t7\n paddsw m0, m7 ;low:t2 high:t3\n punpcklqdq m7, m4\n punpckhwd m7, m4 ;packed t4, t5\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t7, t6\n ITX_MUL2X_PACK 7, 4, 6, 1567, 3784 ;low:t4a high:t5a\n ITX_MUL2X_PACK 3, 4, 6, 3784, 1567, 1 ;low:t6a high:t7a\n psubsw m4, m5, m0 ;low:t2a high:t3a\n paddsw m0, m5 ;low:out0 high:-out15\n psubsw m5, m7, m3 ;low:t6 high:t7\n paddsw m3, m7 ;low:-out3 high:out12\n ret\nALIGN function_align\n.main_pass1_end:\n mova m7, [o(deint_shuf1)]\n mova [coeffq+16*4], m0\n mova [coeffq+16*5], m3\n mova m0, [o(pw_2896_m2896)]\n mova m3, [o(pw_2896_2896)]\n pshufb m1, m7 ;t14a t15a\n pshufb m2, m7 ;t10 t11\n pshufb m4, m7 ;t2a t3a\n pshufb m5, m7 ;t6 t7\n pmaddwd m7, m0, m2\n pmaddwd m2, m3\n paddd m7, m6\n paddd m2, m6\n psrad m7, 12\n psrad m2, 12\n packssdw m2, m7 ;low:out6 high:-out9\n pmaddwd m7, m0, m4\n pmaddwd m4, m3\n paddd m7, m6\n paddd m4, m6\n psrad m7, 12\n psrad m4, 12\n packssdw m4, m7 ;low:-out7 high:out8\n pmaddwd m7, m3, m5\n pmaddwd m5, m0\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m7, m5 ;low:out4 high:-out11\n pmaddwd m5, m3, m1\n pmaddwd m1, m0\n paddd m5, m6\n paddd m1, m6\n psrad m5, 12\n psrad m1, 12\n packssdw m5, m1 ;low:-out5 high:out10\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n punpckhqdq m6, m2, m1 ;low:t11 high:t15a\n punpcklqdq m2, m1 ;low:t10 high:t14a\n psubsw m1, m2, m6\n paddsw m2, m6\n punpckhqdq m6, m4, m5 ;low:t3a high:t7\n punpcklqdq m4, m5 ;low:t2a high:t6\n psubsw m5, m4, m6\n paddsw m4, m6\n pmulhrsw m1, m7 ;low:-out9 high:out10\n pmulhrsw m2, m7 ;low:out6 high:-out5\n pmulhrsw m5, m7 ;low:out8 high:-out11\n pmulhrsw m4, m7 ;low:-out7 high:out4\n punpckhqdq m7, m4, m5 ;low:out4 high:-out11\n punpcklqdq m4, m5 ;low:-out7 high:out8\n punpckhqdq m5, m2, m1 ;low:-out5 high:out10\n punpcklqdq m2, m1 ;low:out6 high:-out9\n ret\n\n\nINV_TXFM_16X4_FN flipadst, dct\nINV_TXFM_16X4_FN flipadst, adst\nINV_TXFM_16X4_FN flipadst, flipadst\nINV_TXFM_16X4_FN flipadst, identity\n\ncglobal iflipadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass1_end\n\n punpcklwd m6, m7, m0 ;packed out11, out15\n punpckhwd m0, m7 ;packed -out0, -out4\n punpckhwd m7, m3, m4 ;packed out3, out7\n punpcklwd m4, m3 ;packed -out8, -out12\n mova m1, [coeffq+16*6]\n punpckhwd m3, m1, m5 ;packed out1, out5\n punpcklwd m5, m1 ;packed -out10, -out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpcklwd m3, m2, m1 ;packed out9, out13\n punpckhwd m1, m2 ;packed -out2, -out6\n\n mova m7, [o(pw_m16384)]\n jmp m(iadst_16x4_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\nINV_TXFM_16X4_FN identity, dct, 15\nINV_TXFM_16X4_FN identity, adst\nINV_TXFM_16X4_FN identity, flipadst\nINV_TXFM_16X4_FN identity, identity\n\ncglobal iidentity_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m1, [coeffq+16*6]\n mova m0, [coeffq+16*5]\n mova m2, [coeffq+16*7]\n mova m6, [o(pw_1697x16)]\n mova m7, [o(pw_16384)]\n pmulhrsw m4, m6, m1\n pmulhrsw m3, m6, m0\n pmulhrsw m5, m6, m2\n pmulhrsw m4, m7\n pmulhrsw m3, m7\n pmulhrsw m5, m7\n paddw m1, m4\n paddw m0, m3\n paddw m5, m2\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mova m4, [coeffq+16*4]\n mova [coeffq+16*6], m1\n mova [coeffq+16*5], m0\n mova [coeffq+16*7], m5\n pmulhrsw m0, m6, m2\n pmulhrsw m1, m6, m3\n pmulhrsw m5, m6, m4\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n pmulhrsw m5, m7\n paddw m2, m0\n paddw m3, m1\n paddw m4, m5\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pmulhrsw m5, m6, m0\n pmulhrsw m6, m1\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n paddw m0, m5\n paddw m1, m6\n mova m6, [coeffq+16*6]\n mova m5, [coeffq+16*5]\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpckhwd m2, m1, m3 ;packed out3, out7\n punpcklwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpckhwd m6, m5, m7 ;packed out11, out15\n punpcklwd m5, m7 ;packed out10, out14\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\n%macro SAVE_8ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n mova [%1+%2*7], m7\n%endmacro\n\n%macro INV_TXFM_8X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n psrlw m2, 3 ; pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mov r3d, 2\n.loop:\n mova m0, [o(pw_2896x8)]\n pmulhrsw m7, m0, [coeffq]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, m7, [o(pw_1697x16)]\n paddw m7, m7\n paddw m7, m0\n pmulhrsw m7, m1\n punpcklwd m0, m7, m7\n punpckhwd m7, m7\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end3\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n call m(iadst_8x4_internal).end3\n\n add coeffq, 16\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n add coeffq, 32*4\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m3, [coeffq+32*2]\n punpcklwd m3, [coeffq+32*3]\n mova m4, [o(pw_2896x8)]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m0, m2\n punpckldq m1, m3\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_identity_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%endif\n%endmacro\n\nINV_TXFM_8X16_FN dct, dct, 0\nINV_TXFM_8X16_FN dct, identity, 15\nINV_TXFM_8X16_FN dct, adst\nINV_TXFM_8X16_FN dct, flipadst\n\ncglobal idct_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_8x8_internal).pass1)]\n\n.pass1:\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov [rsp+gprsize+16*11], tx2q\n lea tx2q, [o(m(idct_8x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, [rsp+gprsize+16*11]\n jmp r3\n\n.pass2:\n lea tx2q, [o(m(idct_8x16_internal).end)]\n\n.pass2_pre:\n mova [coeffq+16*2 ], m1\n mova [coeffq+16*6 ], m3\n mova [coeffq+16*10], m5\n mova [coeffq+16*14], m7\n mova m1, m2\n mova m2, m4\n mova m3, m6\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n\n.pass2_main:\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+16*2 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*10]\n mova m3, [coeffq+16*14]\n mova m4, [coeffq+16*3 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*15]\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n ret\n\nINV_TXFM_8X16_FN adst, dct\nINV_TXFM_8X16_FN adst, adst\nINV_TXFM_8X16_FN adst, flipadst\nINV_TXFM_8X16_FN adst, identity\n\ncglobal iadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(iadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN flipadst, dct\nINV_TXFM_8X16_FN flipadst, adst\nINV_TXFM_8X16_FN flipadst, flipadst\nINV_TXFM_8X16_FN flipadst, identity\n\ncglobal iflipadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x16_internal).end)]\n lea r3, [dstq+strideq*8]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n jmp m(iflipadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN identity, dct, 7\nINV_TXFM_8X16_FN identity, adst\nINV_TXFM_8X16_FN identity, flipadst\nINV_TXFM_8X16_FN identity, identity\n\ncglobal iidentity_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_8x16_internal).pass1_end)]\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, r3\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m6\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*2], m5\n IDTX16 6, 5, 7\n mova m5, [rsp+gprsize+16*0]\n IDTX16 5, 7, 7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [rsp+gprsize+16*2]\n mova [rsp+gprsize+16*0], m5\n mova [rsp+gprsize+16*1], m6\n mova [rsp+gprsize+16*2], m7\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\n%macro INV_TXFM_16X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x8, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x8).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m7, [coeffq]\n mova m0, [o(pw_2896x8)]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 2 ; pw_4096\n pmulhrsw m7, m1\n punpcklwd m3, m7, m7\n punpckhwd m7, m7\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea r3, [dstq+strideq*4]\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n call m(iadst_8x4_internal).end2\n mov dstq, r3\n add coeffq, 16*4\n pshufd m0, m7, q0000\n pshufd m1, m7, q1111\n pshufd m2, m7, q2222\n pshufd m3, m7, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_2896x8)]\n mova m5, [o(pw_1697x16)]\n mova m6, [o(pw_16384)]\n psrlw m7, m6, 3 ; pw_2048\n mov r3d, 2\n.main_loop:\n mova m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n mova m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n punpckldq m0, m1\n mova m1, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n mova m2, [coeffq+16*6]\n punpcklwd m2, [coeffq+16*7]\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m1, m5, m0\n pmulhrsw m1, m6\n paddw m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m7\n.end:\n pxor m1, m1\n REPX {mova [coeffq+16*x], m1}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16*8\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X8_FN dct, dct, 0\nINV_TXFM_16X8_FN dct, identity, 7\nINV_TXFM_16X8_FN dct, adst\nINV_TXFM_16X8_FN dct, flipadst\n\ncglobal idct_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*0, 32, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*1, 32, 1\n call .main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x8_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(idct_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).pass2_main\n\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n mova [rsp+gprsize*2+32*5], m5\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 0, 7, 2, 5, 6, 401, 4076 ;t8a, t15a\n ITX_MULSUB_2W 4, 3, 2, 5, 6, 3166, 2598 ;t9a, t14a\n psubsw m2, m0, m4 ;t9\n paddsw m0, m4 ;t8\n psubsw m4, m7, m3 ;t14\n paddsw m7, m3 ;t15\n ITX_MULSUB_2W 4, 2, 3, 5, 6, 1567, 3784 ;t9a, t14a\n mova m3, [rsp+gprsize*2+16*1]\n mova m5, [rsp+gprsize*2+32*5]\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+32*5], m4\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m7\n ITX_MULSUB_2W 3, 5, 7, 4, 6, 1931, 3612 ;t10a, t13a\n ITX_MULSUB_2W 2, 1, 7, 4, 6, 3920, 1189 ;t11a, t12a\n pxor m4, m4\n psubsw m7, m2, m3 ;t10\n paddsw m2, m3 ;t11\n psubsw m3, m1, m5 ;t13\n paddsw m1, m5 ;t12\n psubw m4, m7\n ITX_MULSUB_2W 4, 3, 7, 5, 6, 1567, 3784 ;t10a, t13a\n mova m7, [rsp+gprsize*2+32*5]\n psubsw m6, m0, m2 ;t11a\n paddsw m0, m2 ;t8a\n paddsw m2, m7, m4 ;t9\n psubsw m7, m4 ;t10\n mova m5, [rsp+gprsize*2+16*0]\n psubsw m4, m5, m0 ;out8\n paddsw m0, m5 ;out7\n mova [rsp+gprsize*2+32*5], m0\n mova m5, [rsp+gprsize*2+16*9]\n psubsw m0, m5, m2 ;out9\n paddsw m2, m5 ;out6\n mova [rsp+gprsize*2+16*0], m0\n mova [rsp+gprsize*2+16*9], m2\n mova m0, [rsp+gprsize*2+16*1]\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*1], m4\n psubsw m5, m0, m3 ;t13\n paddsw m0, m3 ;t14\n mova m3, [o(pd_2048)]\n psubsw m4, m2, m1 ;t12a\n paddsw m1, m2 ;t15a\n mova [rsp+gprsize*2+16*2], m1\n ITX_MULSUB_2W 5, 7, 1, 2, 3, 2896, 2896 ;t10a, t13a\n ITX_MULSUB_2W 4, 6, 1, 2, 3, 2896, 2896 ;t11, t12\n mova m3, [rsp+gprsize*2+16*8]\n psubsw m2, m3, m5 ;out10\n paddsw m3, m5 ;out5\n mova m5, [rsp+gprsize*2+16*7]\n mova [rsp+gprsize*2+16*8], m3\n psubsw m3, m5, m4 ;out11\n paddsw m5, m4 ;out4\n mova m4, [rsp+gprsize*2+16*6]\n mova [rsp+gprsize*2+16*7], m5\n paddsw m5, m4, m6 ;out3\n psubsw m4, m6 ;out12\n mova m6, [rsp+gprsize*2+16*5]\n mova [rsp+gprsize*2+16*6], m5\n psubsw m5, m6, m7 ;out13\n paddsw m6, m7 ;out2\n mova m7, [rsp+gprsize*2+16*4]\n mova [rsp+gprsize*2+16*5], m6\n psubsw m6, m7, m0 ;out14\n paddsw m7, m0 ;out1\n mova m1, [rsp+gprsize*2+16*2]\n mova m0, [rsp+gprsize*2+16*3]\n mova [rsp+gprsize*2+16*4], m7\n psubsw m7, m0, m1 ;out15\n paddsw m0, m1 ;out0\n mova [rsp+gprsize*2+16*3], m0\n mova m1, [rsp+gprsize*2+16*0]\n mova m0, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*0], m7\n ret\n\nINV_TXFM_16X8_FN adst, dct\nINV_TXFM_16X8_FN adst, adst\nINV_TXFM_16X8_FN adst, flipadst\nINV_TXFM_16X8_FN adst, identity\n\ncglobal iadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call .main\n call .main_pass1_end\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x8_internal).pass1_end)]\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).pass2_main\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m1\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 7, 0, 1, 2, 6, 995, 3973 ;t3, t2\n ITX_MULSUB_2W 3, 4, 1, 2, 6, 3513, 2106 ;t11, t10\n psubsw m1, m0, m4 ;t10a\n paddsw m0, m4 ;t2a\n psubsw m4, m7, m3 ;t11a\n paddsw m3, m7 ;t3a\n ITX_MULSUB_2W 1, 4, 7, 2, 6, 3406, 2276 ;t11, t10\n mova m2, [rsp+gprsize*2+16*0] ;in3\n mova m7, [rsp+gprsize*2+16*1] ;in4\n mova [rsp+gprsize*2+16*0], m1 ;t11\n mova [rsp+gprsize*2+16*1], m4 ;t10\n mova m1, [rsp+gprsize*2+16*2] ;in12\n mova [rsp+gprsize*2+16*2], m0 ;t2a\n ITX_MULSUB_2W 5, 7, 0, 4, 6, 1751, 3703 ;t5, t4\n ITX_MULSUB_2W 2, 1, 0, 4, 6, 3857, 1380 ;t13, t12\n psubsw m0, m7, m1 ;t12a\n paddsw m1, m7 ;t4a\n psubsw m4, m5, m2 ;t13a\n paddsw m5, m2 ;t5a\n ITX_MULSUB_2W 4, 0, 7, 2, 6, 4017, 799 ;t12, t13\n mova m2, [rsp+gprsize*2+16*8] ;in1\n mova m7, [rsp+gprsize*2+16*9] ;in14\n mova [rsp+gprsize*2+16*8], m4 ;t12\n mova [rsp+gprsize*2+16*9], m0 ;t13\n mova m4, [rsp+gprsize*2+16*4] ;in9\n mova m0, [rsp+gprsize*2+16*5] ;in6\n mova [rsp+gprsize*2+16*4], m1 ;t4a\n mova [rsp+gprsize*2+16*5], m5 ;t5a\n ITX_MULSUB_2W 2, 7, 1, 5, 6, 4052, 601 ;t15, t14\n ITX_MULSUB_2W 4, 0, 1, 5, 6, 2440, 3290 ;t7, t6\n psubsw m1, m0, m7 ;t14a\n paddsw m0, m7 ;t6a\n psubsw m5, m4, m2 ;t15a\n paddsw m4, m2 ;t7a\n ITX_MULSUB_2W 5, 1, 7, 2, 6, 2276, 3406 ;t14, t15\n mova m2, [rsp+gprsize*2+16*2] ;t2a\n mova [rsp+gprsize*2+16*2], m5 ;t14\n psubsw m7, m2, m0 ;t6\n paddsw m2, m0 ;t2\n psubsw m0, m3, m4 ;t7\n paddsw m3, m4 ;t3\n ITX_MULSUB_2W 0, 7, 4, 5, 6, 3784, 1567 ;t6a, t7a\n mova m4, [rsp+gprsize*2+16*7] ;in0\n mova m5, [rsp+gprsize*2+32*5] ;in15\n mova [rsp+gprsize*2+16*7], m3 ;t3\n mova [rsp+gprsize*2+32*5], m1 ;t15\n mova m1, [rsp+gprsize*2+16*6] ;in7\n mova m3, [rsp+gprsize*2+16*3] ;in8\n mova [rsp+gprsize*2+16*6], m7 ;t7a\n mova [rsp+gprsize*2+16*3], m0 ;t6a\n ITX_MULSUB_2W 5, 4, 0, 7, 6, 201, 4091 ;t1, t0\n ITX_MULSUB_2W 1, 3, 0, 7, 6, 3035, 2751 ;t9, t8\n psubsw m0, m4, m3 ;t8a\n paddsw m4, m3 ;t0a\n psubsw m3, m5, m1 ;t9a\n paddsw m5, m1 ;t1a\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 799, 4017 ;t9, t8\n mova m1, [rsp+gprsize*2+16*4] ;t4a\n mova m7, [rsp+gprsize*2+16*5] ;t5a\n mova [rsp+gprsize*2+16*4], m3 ;t8\n mova [rsp+gprsize*2+16*5], m0 ;t9\n psubsw m0, m4, m1 ;t4\n paddsw m4, m1 ;t0\n psubsw m3, m5, m7 ;t5\n paddsw m5, m7 ;t1\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 1567, 3784 ;t5a, t4a\n mova m7, [rsp+gprsize*2+16*3] ;t6a\n psubsw m1, m4, m2 ;t2a\n paddsw m4, m2 ;out0\n mova [rsp+gprsize*2+16*3], m4 ;out0\n mova m4, [rsp+gprsize*2+16*6] ;t7a\n psubsw m2, m3, m7 ;t6\n paddsw m3, m7 ;-out3\n mova [rsp+gprsize*2+16*6], m3 ;-out3\n psubsw m3, m0, m4 ;t7\n paddsw m0, m4 ;out12\n mova [rsp+gprsize*2+16*12], m3\n mova m3, [rsp+gprsize*2+16*7] ;t3\n mova [rsp+gprsize*2+16* 7], m2 ;out4\n psubsw m2, m5, m3 ;t3a\n paddsw m5, m3 ;-out15\n mova [rsp+gprsize*2+16*11], m2\n mova m2, [rsp+gprsize*2+32*5] ;t15\n mova [rsp+gprsize*2+16*10], m1 ;-out7\n mova m1, [rsp+gprsize*2+16*0] ;t11\n mova [rsp+gprsize*2+16*0 ], m5 ;-out15\n mova m3, [rsp+gprsize*2+16*1] ;t10\n mova [rsp+gprsize*2+16*1 ], m4 ;-out11\n mova m4, [rsp+gprsize*2+16*2] ;t14\n mova [rsp+gprsize*2+16*2 ], m0 ;out12\n psubsw m0, m3, m4 ;t14a\n paddsw m3, m4 ;t10a\n psubsw m5, m1, m2 ;t15a\n paddsw m1, m2 ;t11a\n ITX_MULSUB_2W 5, 0, 2, 4, 6, 3784, 1567 ;t14, t15\n mova m2, [rsp+gprsize*2+16*4] ;t8\n mova m4, [rsp+gprsize*2+16*5] ;t9\n mova [rsp+gprsize*2+16*4], m3 ;t10a\n mova [rsp+gprsize*2+16*5], m1 ;t11a\n mova m3, [rsp+gprsize*2+16*8] ;t12\n mova m1, [rsp+gprsize*2+16*9] ;t13\n mova [rsp+gprsize*2+16*8], m5 ;t14\n mova [rsp+gprsize*2+16*9], m0 ;t15\n psubsw m5, m2, m3 ;t12a\n paddsw m2, m3 ;t8a\n psubsw m0, m4, m1 ;t13a\n paddsw m4, m1 ;t9a\n ITX_MULSUB_2W 5, 0, 1, 3, 6, 1567, 3784 ;t13, t12\n mova m6, [rsp+gprsize*2+16*4] ;t10a\n mova m1, [rsp+gprsize*2+16*5] ;t11a\n psubsw m3, m2, m6 ;t10\n paddsw m2, m6 ;-out1\n paddsw m6, m4, m1 ;out14\n psubsw m4, m1 ;t11\n mova [rsp+gprsize*2+16*14], m4\n mova [rsp+gprsize*2+16* 4], m2 ;-out1\n mova m4, [rsp+gprsize*2+16*8] ;t14\n mova m2, [rsp+gprsize*2+16*9] ;t15\n mova [rsp+gprsize*2+16* 9], m3 ;out6\n psubsw m3, m0, m4 ;t14a\n paddsw m0, m4 ;out2\n psubsw m4, m5, m2 ;t15a\n paddsw m5, m2 ;-out13\n mova [rsp+gprsize*2+16* 5], m0 ;out2\n ret\nALIGN function_align\n.main_pass1_end:\n mova m0, [rsp+gprsize*2+16*14]\n mova [rsp+gprsize*2+16*14], m5\n mova [rsp+gprsize*2+16*15], m6\n mova m5, [o(pw_2896_2896)]\n mova m6, [o(pw_2896_m2896)]\n mova m7, [o(pd_2048)]\n punpcklwd m2, m3, m4\n punpckhwd m3, m4\n pmaddwd m4, m5, m2\n pmaddwd m2, m6\n pmaddwd m1, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m4, m2, m1, m3\n REPX {psrad x, 12}, m4, m1, m2, m3\n packssdw m4, m1 ;-out5\n packssdw m2, m3 ;out10\n mova [rsp+gprsize*2+16* 8], m4\n mova m3, [rsp+gprsize*2+16* 9]\n punpcklwd m1, m3, m0\n punpckhwd m3, m0\n pmaddwd m0, m5, m1\n pmaddwd m1, m6\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m0, m1, m4, m3\n REPX {psrad x, 12}, m0, m4, m1, m3\n packssdw m0, m4 ;out6\n packssdw m1, m3 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n mova m0, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n punpcklwd m3, m0, m4\n punpckhwd m0, m4\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n pmaddwd m5, m0\n pmaddwd m0, m6\n REPX {paddd x, m7}, m4, m3, m5, m0\n REPX {psrad x, 12}, m4, m5, m3, m0\n packssdw m4, m5 ;out4\n packssdw m3, m0 ;-out11\n mova [rsp+gprsize*2+16* 7], m4\n mova m4, [rsp+gprsize*2+16*10]\n mova m5, [rsp+gprsize*2+16*11]\n punpcklwd m0, m4, m5\n punpckhwd m4, m5\n pmaddwd m5, m0, [o(pw_2896_2896)]\n pmaddwd m0, m6\n pmaddwd m6, m4\n pmaddwd m4, [o(pw_2896_2896)]\n REPX {paddd x, m7}, m5, m0, m6, m4\n REPX {psrad x, 12}, m0, m6, m5, m4\n packssdw m0, m6 ;out8\n packssdw m5, m4 ;-out7\n mova [rsp+gprsize*2+16*10], m5\n mova m4, [rsp+gprsize*2+16* 2] ;out12\n mova m5, [rsp+gprsize*2+16*14] ;-out13\n mova m6, [rsp+gprsize*2+16*15] ;out14\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n mova m1, [rsp+gprsize*2+16* 9]\n mova m2, [rsp+gprsize*2+16*14]\n paddsw m0, m1, m2\n psubsw m1, m2\n pmulhrsw m0, m7 ;out6\n pmulhrsw m1, m7 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n psubsw m2, m3, m4\n paddsw m3, m4\n pmulhrsw m2, m7 ;out10\n pmulhrsw m3, m7 ;-out5\n mova [rsp+gprsize*2+16* 8], m3\n mova m3, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n paddsw m0, m3, m4\n psubsw m3, m4\n pmulhrsw m0, m7 ;out4\n pmulhrsw m3, m7 ;-out11\n mova [rsp+gprsize*2+16* 7], m0\n mova m0, [rsp+gprsize*2+16*10]\n paddsw m4, m0, [rsp+gprsize*2+16*11]\n psubsw m0, [rsp+gprsize*2+16*11]\n pmulhrsw m4, m7 ;-out7\n pmulhrsw m0, m7 ;out8\n mova [rsp+gprsize*2+16*10], m4\n mova m4, [rsp+gprsize*2+16*2 ] ;out12\n ret\n\nINV_TXFM_16X8_FN flipadst, dct\nINV_TXFM_16X8_FN flipadst, adst\nINV_TXFM_16X8_FN flipadst, flipadst\nINV_TXFM_16X8_FN flipadst, identity\n\ncglobal iflipadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x8_internal).pass1_end)]\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).pass2_main\n\n\nINV_TXFM_16X8_FN identity, dct, 15\nINV_TXFM_16X8_FN identity, adst\nINV_TXFM_16X8_FN identity, flipadst\nINV_TXFM_16X8_FN identity, identity\n\ncglobal iidentity_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*16\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x8_internal).pass1_end)]\n\n.pass1:\n mova m0, [o(pw_2896x8)]\n mova m2, [o(pw_1697x16)]\n mova m3, [o(pw_16384)]\n sub coeffq, 8*16\n REPX {pmulhrsw x, m0}, m4, m5, m6, m7\n pmulhrsw m1, m2, m4\n pmulhrsw m1, m3\n paddw m1, m4 ; 1\n pmulhrsw m4, m2, m5\n pmulhrsw m4, m3\n paddw m4, m5 ; 3\n pmulhrsw m5, m2, m6\n pmulhrsw m5, m3\n paddw m5, m6 ; 5\n pmulhrsw m6, m2, m7\n pmulhrsw m6, m3\n paddw m7, m6 ; 7\n pmulhrsw m6, m0, [coeffq+16*6]\n mova [rsp+gprsize+16*0], m4\n pmulhrsw m4, m2, m6\n pmulhrsw m4, m3\n paddw m6, m4 ; 6\n pmulhrsw m4, m0, [coeffq+16*4]\n mova [rsp+gprsize+16*1], m6\n pmulhrsw m6, m2, m4\n pmulhrsw m6, m3\n paddw m4, m6 ; 4\n pmulhrsw m6, m0, [coeffq+16*2]\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m2, m6\n pmulhrsw m2, m3\n paddw m2, m6 ; 2\n pmulhrsw m6, m0, [o(pw_1697x16)]\n pmulhrsw m6, m3\n mova m3, [rsp+gprsize+16*0]\n paddw m0, m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n mova [coeffq+16*1], m4\n mova [coeffq+16*3], m5\n mova [coeffq+16*5], m6\n mova [coeffq+16*7], m7\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mova [coeffq-16*7], m0\n mova [coeffq-16*5], m1\n mova [coeffq-16*3], m2\n mova [coeffq-16*1], m3\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea tx2q, [o(m(iidentity_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iidentity_8x8_internal).end\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iidentity_8x8_internal).end\n\n\n%macro INV_TXFM_16X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x16).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m2, m3, [coeffq+16*0]\n pmulhrsw m3, [coeffq+16*1]\n mova m0, [o(pw_8192)]\n mova m1, [o(pw_5793x4)]\n pshuflw m4, [o(deint_shuf)], q0000 ;pb_0_1\n punpcklwd m4, m4\n pcmpeqb m5, m5\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n paddb m5, m5 ;pb_m2\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n psrlw m0, 2 ;pw_2048\n psllw m2, 2\n psllw m3, 2\n pmulhrsw m2, m1\n pmulhrsw m3, m1\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n mov r3d, 8\n.loop:\n mova m1, [dstq]\n pshufb m0, m2, m4\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq], m1\n mova m1, [dstq+strideq*8]\n pshufb m0, m3, m4\n psubb m4, m5 ; += 2\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq+strideq*8], m1\n add dstq, strideq\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_8192)]\n mova m6, [o(pw_2896x8)]\n psrlw m7, m5, 2 ;pw_2048\n xor eobd, eobd\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end)]\n lea r3, [dstq+8]\n mov [rsp+16*0], r3\n.main:\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n add coeffq, 32*4\n punpckldq m0, m1\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n paddw m0, m0\n paddw m0, m1\n pmulhrsw m0, m5\n pmulhrsw m0, m6\n pmulhrsw m0, m7\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end1)]\n add coeffq, 32*4\n mov dstq, [rsp+16*0]\n jmp .main\n.end1:\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X16_FN dct, dct, 0\nINV_TXFM_16X16_FN dct, identity, 15\nINV_TXFM_16X16_FN dct, adst\nINV_TXFM_16X16_FN dct, flipadst\n\ncglobal idct_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_16x8_internal).main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(idct_16x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*4 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*12]\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n lea tx2q, [o(m(idct_8x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_main\n\n\n%macro ITX_16X16_ADST_LOAD_ODD_COEFS 0\n mova m0, [coeffq+16*1 ]\n mova m1, [coeffq+16*3 ]\n mova m2, [coeffq+16*29]\n mova m3, [coeffq+16*31]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*13]\n mova m1, [coeffq+16*15]\n mova m2, [coeffq+16*17]\n mova m3, [coeffq+16*19]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*5 ]\n mova m1, [coeffq+16*7 ]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*11]\n mova m4, [coeffq+16*21]\n mova m5, [coeffq+16*23]\n mova m6, [coeffq+16*25]\n mova m7, [coeffq+16*27]\n%endmacro\n\n%macro ITX_16X16_ADST_LOAD_EVEN_COEFS 0\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*2 ]\n mova m2, [coeffq+16*28]\n mova m3, [coeffq+16*30]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*12]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*16]\n mova m3, [coeffq+16*18]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m4, [coeffq+16*20]\n mova m5, [coeffq+16*22]\n mova m6, [coeffq+16*24]\n mova m7, [coeffq+16*26]\n%endmacro\n\nINV_TXFM_16X16_FN adst, dct\nINV_TXFM_16X16_FN adst, adst\nINV_TXFM_16X16_FN adst, flipadst\n\ncglobal iadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iadst_16x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_main\n\n\nINV_TXFM_16X16_FN flipadst, dct\nINV_TXFM_16X16_FN flipadst, adst\nINV_TXFM_16X16_FN flipadst, flipadst\n\ncglobal iflipadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*17, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS coeffq+16* 0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x16_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n\n lea tx2q, [o(m(iflipadst_16x16_internal).end2)]\n mov dstq, r3\n jmp m(iflipadst_8x16_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n\nINV_TXFM_16X16_FN identity, dct, 15\nINV_TXFM_16X16_FN identity, identity\n\ncglobal iidentity_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*17\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end)]\n\n.pass1:\n mova m7, [o(pw_1697x16)]\n mova m6, [coeffq+32*7]\n mova m0, [coeffq+32*0]\n mova m1, [coeffq+32*1]\n mova m2, [coeffq+32*2]\n mova m3, [coeffq+32*3]\n mova m4, [coeffq+32*4]\n REPX {IDTX16 x, 5, 7}, 6, 0, 1, 2, 3, 4\n mova m5, [coeffq+32*5]\n mova [rsp+gprsize+16*0], m6\n IDTX16 5, 6, 7\n mova m6, [coeffq+32*6]\n IDTX16 6, 7, 7\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end1)]\n jmp .pass1\n\n.pass1_end1:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 15*16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end2)]\n jmp .pass1\n\n.pass1_end2:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea r3, [dstq+8]\n lea tx2q, [o(m(iidentity_16x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m4\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 4, 7}, 5, 6, 0, 1, 2, 3\n mova m4, [o(pw_2048)]\n pmulhrsw m5, m4\n pmulhrsw m6, m4\n mova [rsp+gprsize+16*2], m5\n mova m5, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*1], m6\n IDTX16 5, 6, 7\n mova m6, [rsp+gprsize+16*0]\n IDTX16 6, 7, 7\n REPX {pmulhrsw x, m4}, m0, m1, m2, m3, m6\n pmulhrsw m4, m5\n mova [rsp+gprsize+16*0], m6\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end2)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n.end2:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n LOAD_8ROWS coeffq, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end3)]\n mov dstq, r3\n jmp .end\n\n.end3:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\ncglobal inv_txfm_add_dct_dct_8x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_8x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 2 ;pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x32).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n\n.end:\n RET\n\n\n\ncglobal idct_8x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n cmp eobd, 106\n jle .fast\n\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1:\n mova [rsp+gprsize+16*9 ], m0 ;in24\n mova [rsp+gprsize+16*10], m4 ;in28\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_1:\n mova [rsp+gprsize+16*7 ], m0 ;in16\n mova [rsp+gprsize+16*8 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n.fast:\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n mova [rsp+gprsize+16*5 ], m0 ;in8\n mova [rsp+gprsize+16*6 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n mova m1, m4 ;in4\n mova m2, [rsp+gprsize+16*5 ] ;in8\n mova m3, [rsp+gprsize+16*6 ] ;in12\n\n cmp eobd, 106\n jg .full\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n mova m0, [rsp+gprsize+16*11]\n mova m1, [rsp+gprsize+16*12]\n mova m2, [rsp+gprsize+16*13]\n mova m3, [rsp+gprsize+16*14]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call .main_fast\n jmp .pass2\n\n.full:\n mova m4, [rsp+gprsize+16*7 ] ;in16\n mova m5, [rsp+gprsize+16*8 ] ;in20\n mova m6, [rsp+gprsize+16*9 ] ;in24\n mova m7, [rsp+gprsize+16*10] ;in28\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n call .main\n\n.pass2:\n lea r3, [o(m(idct_8x32_internal).end6)]\n\n.end:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_8x32_internal).end2)]\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, \\\n 8, 9, 10, 11, 12, 13, 14, 15, \\\n 16, 17, 18, 19, 20, 21, 22, 23, \\\n 24, 25, 26, 27, 28, 29, 30, 31\n\n jmp tx2q\n\n.end2:\n lea tx2q, [o(m(idct_8x32_internal).end3)]\n jmp m(idct_8x8_internal).end\n\n.end3:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end4)]\n jmp m(idct_8x8_internal).end\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end5)]\n jmp m(idct_8x8_internal).end\n\n.end5:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n mov tx2q, r3\n jmp m(idct_8x8_internal).end\n\n.end6:\n ret\n\nALIGN function_align\n.main_veryfast:\n mova m0, [rsp+gprsize*2+16*19] ;in1\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t30,t31\n pmulhrsw m0, [o(pw_201x8)] ;t16,t17\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*34], m3 ;t31\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*20], m3 ;t17a\n mova [rsp+gprsize*2+16*33], m0 ;t30a\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m2, m1, [o(pw_3857x8)] ;t28,t29\n pmulhrsw m1, [o(pw_m1380x8)] ;t18,t19\n mova [rsp+gprsize*2+16*22], m1 ;t19\n mova [rsp+gprsize*2+16*31], m2 ;t28\n pxor m0, m0\n psubw m0, m1\n ITX_MULSUB_2W 0, 2, 1, 3, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m0 ;t18a\n mova [rsp+gprsize*2+16*32], m2 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n pmulhrsw m3, m0, [o(pw_3973x8)] ;t26, t27\n pmulhrsw m0, [o(pw_995x8)] ;t20, t21\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*30], m3 ;t27\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m3 ;t21a\n mova [rsp+gprsize*2+16*29], m0 ;t26a\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pxor m0, m0\n mova m3, m0\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main_fast: ;bottom half is zero\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t31a\n pmulhrsw m0, [o(pw_201x8)] ;t16a\n pmulhrsw m2, m1, [o(pw_3035x8)] ;t30a\n pmulhrsw m1, [o(pw_m2751x8)] ;t17a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t17\n paddsw m0, m1 ;t16\n psubsw m5, m3, m2 ;t30\n paddsw m3, m2 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m3, m0, [o(pw_3703x8)]\n pmulhrsw m0, [o(pw_1751x8)]\n pmulhrsw m2, m1, [o(pw_3857x8)]\n pmulhrsw m1, [o(pw_m1380x8)]\n psubsw m4, m1, m0 ;t18\n paddsw m0, m1 ;t19\n psubsw m5, m2, m3 ;t29\n paddsw m3, m2 ;t28\n pxor m2, m2\n psubw m2, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m5 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n pmulhrsw m3, m0, [o(pw_3973x8)]\n pmulhrsw m0, [o(pw_995x8)]\n pmulhrsw m2, m1, [o(pw_3513x8)]\n pmulhrsw m1, [o(pw_m2106x8)]\n psubsw m4, m0, m1 ;t21\n paddsw m0, m1 ;t20\n psubsw m5, m3, m2 ;t26\n paddsw m3, m2 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pmulhrsw m3, m0, [o(pw_3290x8)]\n pmulhrsw m0, [o(pw_2440x8)]\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main:\n mova m7, [o(pd_2048)]\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n mova m2, [rsp+gprsize*2+16*33] ;in17\n mova m3, [rsp+gprsize*2+16*34] ;in31\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 201, 4091 ;t16a, t31a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3035, 2751 ;t17a, t30a\n psubsw m4, m0, m2 ;t17\n paddsw m0, m2 ;t16\n psubsw m5, m3, m1 ;t30\n paddsw m3, m1 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n mova m2, [rsp+gprsize*2+16*31] ;in25\n mova m3, [rsp+gprsize*2+16*32] ;in23\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 1751, 3703 ;t18a, t29a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3857, 1380 ;t19a, t28a\n psubsw m4, m2, m0 ;t18\n paddsw m0, m2 ;t19\n psubsw m5, m1, m3 ;t29\n paddsw m3, m1 ;t28\n pxor m2, m2\n psubw m2, m4 ;-t18\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m5 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n mova m2, [rsp+gprsize*2+16*29] ;in21\n mova m3, [rsp+gprsize*2+16*30] ;in27\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 995, 3973 ;t20a, t27a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3513, 2106 ;t21a, t26a\n psubsw m4, m0, m2 ;t21\n paddsw m0, m2 ;t20\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m1, [rsp+gprsize*2+16*26] ;in3\n mova m2, [rsp+gprsize*2+16*27] ;in29\n mova m3, [rsp+gprsize*2+16*28] ;in19\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 2440, 3290 ;t22a, t25a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 4052, 601 ;t23a, t24a\n\n.main2:\n psubsw m4, m2, m0 ;t22\n paddsw m0, m2 ;t23\n psubsw m5, m1, m3 ;t25\n paddsw m3, m1 ;t24\n pxor m6, m6\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 3406, 2276 ;t22a, t25a\n\n mova m4, [rsp+gprsize*2+16*24] ;t21a\n psubsw m1, m2, m4 ;t21\n paddsw m2, m4 ;t22\n psubw m4, m6, m1 ;-t21\n mova [rsp+gprsize*2+16*25], m2 ;t22\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n psubsw m2, m5, m1 ;t26\n paddsw m5, m1 ;t25\n mova [rsp+gprsize*2+16*28], m5 ;t25\n ITX_MULSUB_2W 4, 2, 1, 5, 7, 1567, 3784 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m4 ;t21a\n mova [rsp+gprsize*2+16*29], m2 ;t26a\n\n mova m1, [rsp+gprsize*2+16*23] ;t20\n mova m5, [rsp+gprsize*2+16*30] ;t27\n psubsw m2, m0, m1 ;t20a\n paddsw m0, m1 ;t23a\n psubsw m4, m3, m5 ;t27a\n paddsw m3, m5 ;t24a\n psubw m6, m2 ;-t20a\n ITX_MULSUB_2W 6, 4, 1, 5, 7, 1567, 3784 ;t20, t27\n mova [rsp+gprsize*2+16*26], m0 ;t23a\n mova [rsp+gprsize*2+16*27], m3 ;t24a\n mova [rsp+gprsize*2+16*30], m4 ;t27\n\n mova m0, [rsp+gprsize*2+16*20] ;t17a\n mova m1, [rsp+gprsize*2+16*21] ;t18a\n mova m2, [rsp+gprsize*2+16*32] ;t29a\n mova m3, [rsp+gprsize*2+16*33] ;t30a\n psubsw m4, m0, m1 ;t18\n paddsw m0, m1 ;t17\n psubsw m5, m3, m2 ;t29\n paddsw m3, m2 ;t30\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t18a, t29a\n mova [rsp+gprsize*2+16*20], m0 ;t17\n mova [rsp+gprsize*2+16*21], m5 ;t18a\n mova [rsp+gprsize*2+16*32], m4 ;t29a\n mova [rsp+gprsize*2+16*33], m3 ;t30\n mova m0, [rsp+gprsize*2+16*19] ;t16\n mova m1, [rsp+gprsize*2+16*22] ;t19\n mova m2, [rsp+gprsize*2+16*31] ;t28\n mova m3, [rsp+gprsize*2+16*34] ;t31\n psubsw m4, m0, m1 ;t19a\n paddsw m0, m1 ;t16a\n psubsw m5, m3, m2 ;t28a\n paddsw m3, m2 ;t31a\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t19, t28\n mova m2, [rsp+gprsize*2+16*15] ;tmp12\n psubsw m1, m5, m6 ;t20a\n paddsw m5, m6 ;t19a\n psubsw m6, m2, m5 ;out19\n paddsw m2, m5 ;out12\n mova m5, [rsp+gprsize*2+16*30] ;t27\n mova [rsp+gprsize*2+16*22], m6 ;out19\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m6, m4, m5 ;t27a\n paddsw m4, m5 ;t28a\n ITX_MULSUB_2W 6, 1, 2, 5, 7, 2896, 2896 ;t20, t27\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp3\n psubsw m5, m2, m4 ;out28\n paddsw m2, m4 ;out3\n mova m4, [rsp+gprsize*2+16*14] ;tmp11\n mova [rsp+gprsize*2+16*31], m5 ;out28\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m5, m4, m6 ;out20\n paddsw m4, m6 ;out11\n mova m2, [rsp+gprsize*2+16*7 ] ;tmp4\n mova [rsp+gprsize*2+16*23], m5 ;out20\n mova [rsp+gprsize*2+16*14], m4 ;out11\n psubsw m5, m2, m1 ;out27\n paddsw m2, m1 ;out4\n mova m1, [rsp+gprsize*2+16*26] ;t23a\n mova m4, [rsp+gprsize*2+16*27] ;t24a\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*7 ], m2 ;out4\n psubsw m5, m0, m1 ;t23\n paddsw m0, m1 ;t16\n psubsw m2, m3, m4 ;t24\n paddsw m3, m4 ;t31\n ITX_MULSUB_2W 2, 5, 4, 6, 7, 2896, 2896 ;t23a, t24a\n mova m6, [rsp+gprsize*2+16*18] ;tmp15\n psubsw m4, m6, m0 ;out16\n paddsw m6, m0 ;out15\n mova m0, [rsp+gprsize*2+16*3 ] ;tmp0\n mova m1, [rsp+gprsize*2+16*11] ;tmp8\n mova [rsp+gprsize*2+16*18], m6 ;out15\n mova [rsp+gprsize*2+16*19], m4 ;out16\n psubsw m6, m0, m3 ;out31\n paddsw m0, m3 ;out0\n psubsw m4, m1, m2 ;out23\n paddsw m1, m2 ;out8\n mova m3, [rsp+gprsize*2+16*10] ;tmp7\n mova [rsp+gprsize*2+16*34], m6 ;out31\n mova [rsp+gprsize*2+16*11], m1 ;out8\n mova [rsp+gprsize*2+16*26], m4 ;out23\n paddsw m6, m3, m5 ;out7\n psubsw m3, m5 ;out24\n mova m1, [rsp+gprsize*2+16*20] ;t17\n mova m5, [rsp+gprsize*2+16*25] ;t22\n mova m2, [rsp+gprsize*2+16*17] ;tmp14\n mova [rsp+gprsize*2+16*27], m3 ;out24\n psubsw m4, m1, m5 ;t22a\n paddsw m1, m5 ;t17a\n psubsw m3, m2, m1 ;out17\n paddsw m2, m1 ;out14\n mova m5, [rsp+gprsize*2+16*28] ;t25\n mova m1, [rsp+gprsize*2+16*33] ;t30\n mova [rsp+gprsize*2+16*17], m2 ;out14\n mova [rsp+gprsize*2+16*20], m3 ;out17\n psubsw m2, m1, m5 ;t25a\n paddsw m1, m5 ;t30a\n ITX_MULSUB_2W 2, 4, 3, 5, 7, 2896, 2896 ;t22, t25\n mova m5, [rsp+gprsize*2+16*4 ] ;tmp1\n psubsw m3, m5, m1 ;out30\n paddsw m5, m1 ;out1\n mova m1, [rsp+gprsize*2+16*12] ;tmp9\n mova [rsp+gprsize*2+16*33], m3 ;out30\n mova [rsp+gprsize*2+16*4 ], m5 ;out1\n psubsw m3, m1, m2 ;out22\n paddsw m1, m2 ;out9\n mova m5, [rsp+gprsize*2+16*9 ] ;tmp6\n mova [rsp+gprsize*2+16*25], m3 ;out22\n mova [rsp+gprsize*2+16*12], m1 ;out9\n psubsw m3, m5, m4 ;out25\n paddsw m5, m4 ;out6\n mova m4, [rsp+gprsize*2+16*21] ;t18a\n mova m1, [rsp+gprsize*2+16*24] ;t21a\n mova m2, [rsp+gprsize*2+16*16] ;tmp13\n mova [rsp+gprsize*2+16*28], m3 ;out25\n mova [rsp+gprsize*2+16*9 ], m5 ;out6\n paddsw m3, m4, m1 ;t18\n psubsw m4, m1 ;t21\n psubsw m5, m2, m3 ;out18\n paddsw m2, m3 ;out13\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n mova m3, [rsp+gprsize*2+16*32] ;t29a\n mova [rsp+gprsize*2+16*21], m5 ;out18\n mova [rsp+gprsize*2+16*16], m2 ;out13\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t29\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 2896, 2896 ;t21a, t26a\n mova m2, [rsp+gprsize*2+16*5 ] ;tmp2\n psubsw m1, m2, m3 ;out29\n paddsw m2, m3 ;out2\n mova m3, [rsp+gprsize*2+16*13] ;tmp10\n mova [rsp+gprsize*2+16*32], m1 ;out29\n psubsw m7, m3, m5 ;out21\n paddsw m3, m5 ;out10\n mova m5, [rsp+gprsize*2+16*8 ] ;tmp5\n mova [rsp+gprsize*2+16*24], m7 ;out21\n mova [rsp+gprsize*2+16*13], m3 ;out10\n psubsw m1, m5, m4 ;out26\n paddsw m5, m4 ;out5\n mova m7, m6 ;out7\n mova m3, [rsp+gprsize*2+16*6 ] ;out3\n mova m4, [rsp+gprsize*2+16*7 ] ;out4\n mova [rsp+gprsize*2+16*29], m1 ;out26\n mova m6, [rsp+gprsize*2+16*9 ] ;out6\n mova m1, [rsp+gprsize*2+16*4 ] ;out1\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x8, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_32x8_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\ncglobal idct_32x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*1, 32\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n cmp eobd, 106\n jg .full\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n LOAD_8ROWS coeffq+16*17, 32\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass2:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x8_internal).end)]\n jmp m(idct_8x32_internal).end1\n\n.end:\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end1:\n lea r3, [dstq+8]\n lea tx2q, [o(m(idct_32x8_internal).end2)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end3:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end4)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end5:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end6)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end6:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end7:\n mov dstq, r3\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end8:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_8x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n\n.loop:\n LOAD_8ROWS coeffq+16*0, 64\n paddw m6, [o(pw_5)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_5)]\n REPX {paddw x, m6}, m0, m1, m2, m3, m4, m5, m7\n\n call m(idct_8x8_internal).pass1_end3\n REPX {psraw x, 3 }, m0, m1, m2, m3, m4, m5, m6, m7\n\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n add coeffq, 16\n dec r3d\n jg .loop\n RET\n\ncglobal inv_txfm_add_identity_identity_32x8, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n.loop:\n LOAD_8ROWS coeffq+16*0, 16\n pmulhrsw m6, [o(pw_4096)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_4096)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n call m(idct_8x8_internal).pass1_end3\n\n mov [rsp+16*3], dstq\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n call m(idct_8x8_internal).end3\n\n add coeffq, 16*8\n mov dstq, [rsp+16*3]\n lea dstq, [dstq+8]\n dec r3d\n jg .loop\n jnc .loop\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_16x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x32).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\ncglobal idct_16x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n LOAD_8ROWS coeffq+16*1, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*5, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*33, 64 ;in8~in15\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n mova [coeffq+16*1 ], m0 ;in8\n mova [coeffq+16*5 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*32, 64 ;in0~in7\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n\n cmp eobd, 150\n jg .full\n\n mova m1, m4 ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [rsp+gprsize+16*11] ;in2\n mova m1, [rsp+gprsize+16*12] ;in6\n mova m2, [rsp+gprsize+16*13] ;in10\n mova m3, [rsp+gprsize+16*14] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n mova [coeffq+16*0 ], m0 ;in0\n mova [coeffq+16*4 ], m4 ;in4\n\n LOAD_8ROWS coeffq+16*2, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*6, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*34, 64 ;in16~in23\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n mova [coeffq+16*2 ], m0 ;in16\n mova [coeffq+16*6 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n LOAD_8ROWS coeffq+16*3, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*7, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS coeffq+16*35, 64 ;in24~in31\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n mova m6, m0 ;in24\n mova m7, m4 ;in28\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*4 ] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*6 ] ;in20\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main\n\n.pass2:\n mov [rsp+gprsize*1+16*35], eobd\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n lea r3, [o(m(idct_16x32_internal).end)]\n jmp m(idct_8x32_internal).end\n\n.end:\n mov dstq, [rsp+gprsize*2+16*35]\n mov eobd, [rsp+gprsize*1+16*35]\n add coeffq, 16*32\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*16] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*17] ;in12\n\n cmp eobd, 150\n jg .full1\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .end1\n\n.full1:\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*18] ;in20\n mova m6, [coeffq+16*3 ] ;in24\n mova m7, [coeffq+16*19] ;in26\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n mova m4, [coeffq+16*10] ;in18\n mova m5, [coeffq+16*26] ;in22\n mova m6, [coeffq+16*11] ;in26\n mova m7, [coeffq+16*27] ;in30\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n\n.end1:\n jmp m(idct_8x32_internal).pass2\n\n\n\ncglobal inv_txfm_add_dct_dct_32x16, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x16_internal)\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*11, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*19, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*27, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n add coeffq, 16\n lea r3, [o(m(idct_32x16_internal).pass1_end1)]\n.pass1:\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*2, 64, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n LOAD_8ROWS coeffq+16*34, 64, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass1_end:\n mova [rsp+gprsize+16*0 ], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+16*32, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*48, 32\n\n sub coeffq, 16\n lea r3, [o(m(idct_32x16_internal).end)]\n jmp .pass1\n\n.end:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_16x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 1\n mov r5, 2\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 278 ;if (eob > 278)\n cmovg r4, r5 ; iteration_count++\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n mov [rsp+gprsize+16*3], r4\n mov [rsp+gprsize*2+16*3], coeffq\n\n.loop:\n LOAD_8ROWS coeffq, 64, 1\n REPX {psllw x, 2 }, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n pmulhrsw m7, [o(pw_5793x4)]\n paddw m7, [o(pw_5)]\n psraw m7, 3\n mova [rsp+16*0], m7\n mova m7, [o(pw_5793x4)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova m7, [o(pw_5)]\n REPX {paddw x, m7}, m0, m1, m2, m3, m4, m5, m6\n REPX {psraw x, 3 }, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n add coeffq, 16\n dec r3\n jg .loop\n\n mov coeffq, [rsp+gprsize*2+16*3]\n add coeffq, 64*8\n mov r3, [rsp+gprsize+16*3]\n xor dstq, dstq\n mov [rsp+gprsize+16*3], dstq\n mov dstq, [rsp+16*3]\n test r3, r3\n jnz .loop\n\n RET\n\n\ncglobal inv_txfm_add_identity_identity_32x16, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 12 ;0100b\n mov r5, 136 ;1000 1000b\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count+2\n mov r5, 34952 ;1000 1000 1000 1000b\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count += 4\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 32, 1\n REPX {psllw x, 2}, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova m5, [o(pw_1697x8)]\n pmulhrsw m6, m5, m7\n paddw m7, m6\n pmulhrsw m6, m5, m0\n paddw m0, m6\n pmulhrsw m6, m5, m1\n paddw m1, m6\n pmulhrsw m6, m5, m2\n paddw m2, m6\n pmulhrsw m6, m5, m3\n paddw m3, m6\n pmulhrsw m6, m5, m4\n pmulhrsw m7, [o(pw_2048)]\n paddw m4, m6\n mova m6, [rsp+16*1]\n mova [rsp+16*0], m7\n pmulhrsw m7, m5, m6\n paddw m6, m7\n mova m7, [rsp+16*2]\n pmulhrsw m5, m7\n paddw m5, m7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+32*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n.loop_end:\n add coeffq, 16\n shr r3, 2\n test r3, r3\n jz .ret\n test r3, 2\n jnz .loop\n mov r4, r3\n and r4, 1\n shl r4, 3\n add coeffq, r4\n add coeffq, 32*7\n mov dstq, [rsp+16*3]\n lea r4, [dstq+8]\n mov [rsp+16*3], r4\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_32x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*35], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*35], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*35]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n mova m0, [coeffq+256*0]\n mova m1, [coeffq+256*1]\n mova m2, [coeffq+256*2]\n mova m3, [coeffq+256*3]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+128*1]\n mova m1, [coeffq+128*3]\n mova m2, [coeffq+128*5]\n mova m3, [coeffq+128*7]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*35]\n mov r3, 4\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*35], r3\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*12]\n mova m2, [coeffq+16*20]\n mova m3, [coeffq+16*28]\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*13]\n mova m6, [coeffq+16*21]\n mova m7, [coeffq+16*29]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov eobd, [rsp+gprsize*1+16*35]\n test eobd, eobd\n jl .fast1\n\n.full1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n mova m4, [coeffq+16*2 ]\n mova m5, [coeffq+16*18]\n mova m6, [coeffq+16*3 ]\n mova m7, [coeffq+16*19]\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*22]\n mova m3, [coeffq+16*30]\n mova m4, [coeffq+16*7 ]\n mova m5, [coeffq+16*15]\n mova m6, [coeffq+16*23]\n mova m7, [coeffq+16*31]\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp tx2q\n\n.fast1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp tx2q\n\n.pass2_end:\n lea r3, [o(m(idct_32x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end\n\n.pass2_end1:\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg .pass2_loop\n\n ret\n\n\ncglobal inv_txfm_add_identity_identity_32x32, 4, 6, 8, 16*5, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 2\n mov r5, 4\n cmp eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n lea r3, [dstq+8]\n mov [rsp+gprsize*0+16*3], r3\n mov [rsp+gprsize*1+16*3], r4\n mov [rsp+gprsize*2+16*3], r4\n mov [rsp+gprsize*3+16*3], coeffq\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 64\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n pmulhrsw m7, [o(pw_8192)]\n mova [rsp+16*0], m7\n mova m7, [o(pw_8192)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+16*1], m6\n mova [rsp+16*2], m5\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n add coeffq, 16\n dec r3\n jg .loop\n\n mov r4, [rsp+gprsize*2+16*3]\n dec r4\n jle .ret\n\n mov dstq, [rsp+gprsize*0+16*3]\n mov coeffq, [rsp+gprsize*3+16*3]\n mov [rsp+gprsize*2+16*3], r4\n lea r3, [dstq+8]\n add coeffq, 64*8\n mov [rsp+gprsize*0+16*3], r3\n mov r3, [rsp+gprsize*1+16*3]\n mov [rsp+gprsize*3+16*3], coeffq\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_16x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x64).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\n\ncglobal idct_16x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 151\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*0, 64*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*1, 64*2\n call m(idct_16x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 2\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*67], r3\n mov eobd, [rsp+gprsize*1+16*67]\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n pxor m4, m4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n\n test eobd, eobd\n jl .fast\n\n.full:\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n mova m2, [coeffq+16*18]\n mova m3, [coeffq+16*19]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call .main\n jmp .end\n\n.fast:\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n\n call m(idct_8x32_internal).main_veryfast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n call .main_fast\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, r4\n jmp m(idct_8x32_internal).end2\n\n.end1:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n lea r3, [o(m(idct_16x64_internal).end2)]\n jmp m(idct_8x32_internal).end\n\n.end2:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n dec r3\n jg .pass2_loop\n ret\n\n\nALIGN function_align\n.main_fast:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t62,t63\n pmulhrsw m0, [o(pw_101x8)] ;t32,t33\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*66], m3 ;t63\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*36], m3 ;t33a\n mova [rsp+gprsize*2+16*65], m0 ;t62a\n\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60,t61\n pmulhrsw m1, [o(pw_m1474x8)] ;t34,t35\n mova [rsp+gprsize*2+16*38], m1 ;t35\n mova [rsp+gprsize*2+16*63], m2 ;t60\n pxor m6, m6\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 401, 4076 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m3 ;t34a\n mova [rsp+gprsize*2+16*64], m2 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t58,t59\n pmulhrsw m0, [o(pw_897x8)] ;t36,t37\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*62], m3 ;t59\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56,t57\n pmulhrsw m1, [o(pw_m700x8)] ;t38,t39\n mova [rsp+gprsize*2+16*42], m1 ;t39\n mova [rsp+gprsize*2+16*59], m2 ;t56\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 3166, 2598 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m3 ;t38a\n mova [rsp+gprsize*2+16*60], m2 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t54,t55\n pmulhrsw m0, [o(pw_501x8)] ;t40,t41\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*58], m3 ;t55\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*44], m3 ;t41a\n mova [rsp+gprsize*2+16*57], m0 ;t54a\n\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52,t53\n pmulhrsw m1, [o(pw_m1092x8)] ;t42,t43\n mova [rsp+gprsize*2+16*46], m1 ;t43\n mova [rsp+gprsize*2+16*55], m2 ;t52\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 1931, 3612 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m3 ;t42a\n mova [rsp+gprsize*2+16*56], m2 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t50,t51\n pmulhrsw m0, [o(pw_1285x8)] ;t44,t45\n mova m6, m0\n mova [rsp+gprsize*2+16*54], m3 ;t51\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m3 ;t45a\n mova [rsp+gprsize*2+16*53], m0 ;t50a\n\n mova m0, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_4085x8)] ;t48,t49\n pmulhrsw m0, [o(pw_m301x8)] ;t46,t47\n mova m4, m3\n mova m5, m0\n\n jmp .main2\n\nALIGN function_align\n.main:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n mova m1, [rsp+gprsize*2+16*65] ;in31\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t63a\n pmulhrsw m0, [o(pw_101x8)] ;t32a\n pmulhrsw m2, m1, [o(pw_2967x8)] ;t62a\n pmulhrsw m1, [o(pw_m2824x8)] ;t33a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t33\n paddsw m0, m1 ;t32\n psubsw m5, m3, m2 ;t62\n paddsw m3, m2 ;t63\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*36], m5 ;t33a\n mova [rsp+gprsize*2+16*65], m4 ;t62a\n mova [rsp+gprsize*2+16*66], m3 ;t63\n\n mova m0, [rsp+gprsize*2+16*63] ;in17\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m3, m0, [o(pw_3745x8)] ;t61a\n pmulhrsw m0, [o(pw_1660x8)] ;t34a\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60a\n pmulhrsw m1, [o(pw_m1474x8)] ;t35a\n psubsw m4, m1, m0 ;t34\n paddsw m0, m1 ;t35\n psubsw m5, m2, m3 ;t61\n paddsw m3, m2 ;t60\n pxor m6, m6\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 401, 4076 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m2 ;t34a\n mova [rsp+gprsize*2+16*38], m0 ;t35\n mova [rsp+gprsize*2+16*63], m3 ;t60\n mova [rsp+gprsize*2+16*64], m5 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n mova m1, [rsp+gprsize*2+16*61] ;in23\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t59a\n pmulhrsw m0, [o(pw_897x8)] ;t36a\n pmulhrsw m2, m1, [o(pw_3461x8)] ;t58a\n pmulhrsw m1, [o(pw_m2191x8)] ;t37a\n psubsw m4, m0, m1 ;t37\n paddsw m0, m1 ;t36\n psubsw m5, m3, m2 ;t58\n paddsw m3, m2 ;t59\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*40], m5 ;t37a\n mova [rsp+gprsize*2+16*61], m4 ;t58a\n mova [rsp+gprsize*2+16*62], m3 ;t59\n\n mova m0, [rsp+gprsize*2+16*59] ;in25\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m3, m0, [o(pw_3349x8)] ;t57a\n pmulhrsw m0, [o(pw_2359x8)] ;t38a\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56a\n pmulhrsw m1, [o(pw_m700x8)] ;t39a\n psubsw m4, m1, m0 ;t38\n paddsw m0, m1 ;t39\n psubsw m5, m2, m3 ;t57\n paddsw m3, m2 ;t56\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 3166, 2598 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m2 ;t38a\n mova [rsp+gprsize*2+16*42], m0 ;t39\n mova [rsp+gprsize*2+16*59], m3 ;t56\n mova [rsp+gprsize*2+16*60], m5 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n mova m1, [rsp+gprsize*2+16*57] ;in27\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t55a\n pmulhrsw m0, [o(pw_501x8)] ;t40a\n pmulhrsw m2, m1, [o(pw_3229x8)] ;t54a\n pmulhrsw m1, [o(pw_m2520x8)] ;t41a\n psubsw m4, m0, m1 ;t41\n paddsw m0, m1 ;t40\n psubsw m5, m3, m2 ;t54\n paddsw m3, m2 ;t55\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*44], m5 ;t41a\n mova [rsp+gprsize*2+16*57], m4 ;t54a\n mova [rsp+gprsize*2+16*58], m3 ;t55\n\n mova m0, [rsp+gprsize*2+16*55] ;in21\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m3, m0, [o(pw_3564x8)] ;t53a\n pmulhrsw m0, [o(pw_2019x8)] ;t42a\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52a\n pmulhrsw m1, [o(pw_m1092x8)] ;t43a\n psubsw m4, m1, m0 ;t42\n paddsw m0, m1 ;t43\n psubsw m5, m2, m3 ;t53\n paddsw m3, m2 ;t52\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 1931, 3612 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m2 ;t42a\n mova [rsp+gprsize*2+16*46], m0 ;t43\n mova [rsp+gprsize*2+16*55], m3 ;t52\n mova [rsp+gprsize*2+16*56], m5 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n mova m1, [rsp+gprsize*2+16*53] ;in19\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t51a\n pmulhrsw m0, [o(pw_1285x8)] ;t44a\n pmulhrsw m2, m1, [o(pw_3659x8)] ;t50a\n pmulhrsw m1, [o(pw_m1842x8)] ;t45a\n psubsw m4, m0, m1 ;t45\n paddsw m0, m1 ;t44\n psubsw m5, m3, m2 ;t50\n paddsw m3, m2 ;t51\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova m6, m0\n mova [rsp+gprsize*2+16*48], m5 ;t45a\n mova [rsp+gprsize*2+16*53], m4 ;t50a\n mova [rsp+gprsize*2+16*54], m3 ;t51\n\n mova m0, [rsp+gprsize*2+16*51] ;in29\n mova m1, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_3102x8)] ;t49a\n pmulhrsw m0, [o(pw_2675x8)] ;t46a\n pmulhrsw m2, m1, [o(pw_4085x8)] ;t48a\n pmulhrsw m1, [o(pw_m301x8)] ;t47a\n psubsw m5, m1, m0 ;t46\n paddsw m0, m1 ;t47\n psubsw m4, m2, m3 ;t49\n paddsw m3, m2 ;t48\n\nALIGN function_align\n.main2:\n pxor m2, m2\n psubw m2, m5\n ITX_MULSUB_2W 2, 4, 1, 5, 7, 3920, 1189 ;t46a, t49a\n\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m5, m0, m6 ;t44a\n paddsw m0, m6 ;t47a\n psubsw m6, m3, m1 ;t51a\n paddsw m3, m1 ;t48a\n mova [rsp+gprsize*2+16*50], m0 ;t47a\n mova [rsp+gprsize*2+16*51], m3 ;t48a\n pxor m1, m1\n psubw m3, m1, m5\n ITX_MULSUB_2W 3, 6, 0, 5, 7, 3406, 2276 ;t44, t51\n mova [rsp+gprsize*2+16*47], m3 ;t44\n mova [rsp+gprsize*2+16*54], m6 ;t51\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m3, [rsp+gprsize*2+16*53] ;t50a\n psubsw m5, m2, m0 ;t45\n paddsw m2, m0 ;t46\n psubsw m6, m4, m3 ;t50\n paddsw m4, m3 ;t49\n psubw m1, m5\n ITX_MULSUB_2W 1, 6, 0, 3, 7, 3406, 2276 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m1 ;t45a\n mova [rsp+gprsize*2+16*49], m2 ;t46\n mova [rsp+gprsize*2+16*52], m4 ;t49\n mova [rsp+gprsize*2+16*53], m6 ;t50a\n\n mova m0, [rsp+gprsize*2+16*43] ;t40\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m3, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*58] ;t55\n psubsw m4, m0, m2 ;t43a\n paddsw m0, m2 ;t40a\n psubsw m5, m1, m3 ;t52a\n paddsw m1, m3 ;t55a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t43, t52\n mova [rsp+gprsize*2+16*43], m0 ;t40a\n mova [rsp+gprsize*2+16*46], m5 ;t43\n mova [rsp+gprsize*2+16*55], m4 ;t52\n mova [rsp+gprsize*2+16*58], m1 ;t55a\n\n mova m0, [rsp+gprsize*2+16*44] ;t41a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*57] ;t54a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t41\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t54\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t42a, t53a\n mova [rsp+gprsize*2+16*44], m0 ;t41\n mova [rsp+gprsize*2+16*45], m5 ;t42a\n mova [rsp+gprsize*2+16*56], m4 ;t53a\n mova [rsp+gprsize*2+16*57], m1 ;t54\n\n mova m0, [rsp+gprsize*2+16*41] ;t38a\n mova m2, [rsp+gprsize*2+16*40] ;t37a\n mova m3, [rsp+gprsize*2+16*61] ;t58a\n mova m1, [rsp+gprsize*2+16*60] ;t57a\n psubsw m4, m0, m2 ;t37\n paddsw m0, m2 ;t38\n psubsw m5, m1, m3 ;t58\n paddsw m1, m3 ;t57\n pxor m6, m6\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 799, 4017 ;t37a, t58a\n mova [rsp+gprsize*2+16*41], m0 ;t38\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m5 ;t58a\n mova [rsp+gprsize*2+16*60], m1 ;t57\n\n mova m0, [rsp+gprsize*2+16*42] ;t39\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*59] ;t56\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t39a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t56a\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 799, 4017 ;t36, t59\n mova [rsp+gprsize*2+16*42], m0 ;t39a\n mova [rsp+gprsize*2+16*39], m3 ;t36\n mova [rsp+gprsize*2+16*62], m5 ;t59\n mova [rsp+gprsize*2+16*59], m1 ;t56a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m2, [rsp+gprsize*2+16*38] ;t35\n mova m3, [rsp+gprsize*2+16*63] ;t60\n mova m1, [rsp+gprsize*2+16*66] ;t63\n psubsw m4, m0, m2 ;t35a\n paddsw m0, m2 ;t32a\n psubsw m5, m1, m3 ;t60a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t35, t60\n mova [rsp+gprsize*2+16*35], m0 ;t32a\n mova [rsp+gprsize*2+16*38], m5 ;t35\n mova [rsp+gprsize*2+16*63], m4 ;t60\n mova [rsp+gprsize*2+16*66], m1 ;t63a\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m2, [rsp+gprsize*2+16*37] ;t34a\n mova m3, [rsp+gprsize*2+16*64] ;t61a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n psubsw m4, m0, m2 ;t34\n paddsw m0, m2 ;t33\n psubsw m5, m1, m3 ;t61\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t34a, t61a\n\n mova m2, [rsp+gprsize*2+16*41] ;t38\n mova m3, [rsp+gprsize*2+16*60] ;t57\n psubsw m6, m0, m2 ;t38a\n paddsw m0, m2 ;t33a\n psubsw m2, m1, m3 ;t57a\n paddsw m1, m3 ;t62a\n mova [rsp+gprsize*2+16*36], m0 ;t33a\n mova [rsp+gprsize*2+16*65], m1 ;t62a\n ITX_MULSUB_2W 2, 6, 0, 3, 7, 1567, 3784 ;t38, t57\n mova [rsp+gprsize*2+16*41], m2 ;t38\n mova [rsp+gprsize*2+16*60], m6 ;t57\n\n mova m2, [rsp+gprsize*2+16*40] ;t37\n mova m3, [rsp+gprsize*2+16*61] ;t58\n psubsw m0, m5, m2 ;t37\n paddsw m5, m2 ;t34\n psubsw m1, m4, m3 ;t58\n paddsw m4, m3 ;t61\n ITX_MULSUB_2W 1, 0, 2, 3, 7, 1567, 3784 ;t37a, t58a\n mova [rsp+gprsize*2+16*37], m5 ;t34\n mova [rsp+gprsize*2+16*64], m4 ;t61\n mova [rsp+gprsize*2+16*40], m1 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m0, [rsp+gprsize*2+16*38] ;t35\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*63] ;t60\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t35a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t60a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t36, t59\n mova [rsp+gprsize*2+16*38], m0 ;t35a\n mova [rsp+gprsize*2+16*39], m5 ;t36\n mova [rsp+gprsize*2+16*62], m4 ;t59\n mova [rsp+gprsize*2+16*63], m1 ;t60a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32a\n mova m2, [rsp+gprsize*2+16*42] ;t39a\n mova m3, [rsp+gprsize*2+16*59] ;t56a\n mova m1, [rsp+gprsize*2+16*66] ;t63a\n psubsw m4, m0, m2 ;t39\n paddsw m0, m2 ;t32\n psubsw m5, m1, m3 ;t56\n paddsw m1, m3 ;t63\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t39a, t56a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*42], m5 ;t39a\n mova [rsp+gprsize*2+16*59], m4 ;t56a\n mova [rsp+gprsize*2+16*66], m1 ;t63\n\n mova m0, [rsp+gprsize*2+16*50] ;t47a\n mova m2, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*51] ;t48a\n psubsw m4, m0, m2 ;t40\n paddsw m0, m2 ;t47\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t48\n pxor m6, m6\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t40a, t55a\n mova [rsp+gprsize*2+16*50], m0 ;t47\n mova [rsp+gprsize*2+16*43], m3 ;t40a\n mova [rsp+gprsize*2+16*58], m5 ;t55a\n mova [rsp+gprsize*2+16*51], m1 ;t48\n\n mova m0, [rsp+gprsize*2+16*49] ;t46\n mova m2, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*52] ;t49\n psubsw m4, m0, m2 ;t41a\n paddsw m0, m2 ;t46a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t49a\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t41, t54\n mova [rsp+gprsize*2+16*49], m0 ;t46a\n mova [rsp+gprsize*2+16*44], m3 ;t41\n mova [rsp+gprsize*2+16*57], m5 ;t54\n mova [rsp+gprsize*2+16*52], m1 ;t49a\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*53] ;t50a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t45\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t50\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t42a, t53a\n mova [rsp+gprsize*2+16*48], m0 ;t45\n mova [rsp+gprsize*2+16*45], m3 ;t42a\n mova [rsp+gprsize*2+16*56], m5 ;t53a\n mova [rsp+gprsize*2+16*53], m1 ;t50\n\n mova m0, [rsp+gprsize*2+16*47] ;t44\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m5, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m3, m0, m2 ;t43a\n paddsw m0, m2 ;t44a\n psubsw m4, m1, m5 ;t52a\n paddsw m1, m5 ;t51a\n psubw m5, m6, m3\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t43, t52\n\n mova m2, [rsp+gprsize*2+16*38] ;t35a\n mova m3, [rsp+gprsize*2+16*31] ;tmp[28]\n psubsw m6, m2, m0 ;t44\n paddsw m2, m0 ;t35\n psubsw m0, m3, m2 ;out35\n paddsw m2, m3 ;out28\n mova m3, [rsp+gprsize*2+16*63] ;t60a\n mova [rsp+gprsize*2+16*38], m0 ;out35\n mova [rsp+gprsize*2+16*31], m2 ;out28\n psubsw m0, m3, m1 ;t51\n paddsw m3, m1 ;t60\n ITX_MULSUB_2W 0, 6, 1, 2, 7, 2896, 2896 ;t44a, t51a\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp[3]\n psubsw m1, m2, m3 ;out60\n paddsw m2, m3 ;out3\n mova m3, [rsp+gprsize*2+16*22] ;tmp[19]\n mova [rsp+gprsize*2+16*63], m1 ;out60\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m1, m3, m0 ;out44\n paddsw m3, m0 ;out19\n mova m2, [rsp+gprsize*2+16*15] ;tmp[12]\n\n mova m0, [rsp+gprsize*2+16*39] ;t36\n mova [rsp+gprsize*2+16*47], m1 ;out44\n mova [rsp+gprsize*2+16*22], m3 ;out19\n mova m1, [rsp+gprsize*2+16*62] ;t59\n psubsw m3, m2, m6 ;out51\n paddsw m2, m6 ;out12\n mova [rsp+gprsize*2+16*54], m3 ;out51\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m2, m0, m5 ;t43a\n paddsw m0, m5 ;t36a\n mova m5, [rsp+gprsize*2+16*30] ;tmp[27]\n psubsw m3, m1, m4 ;t52a\n paddsw m1, m4 ;t59a\n ITX_MULSUB_2W 3, 2, 4, 6, 7, 2896, 2896 ;t43, t52\n mova m4, [rsp+gprsize*2+16*7 ] ;tmp[4 ]\n psubsw m6, m5, m0 ;out36\n paddsw m5, m0 ;out27\n psubsw m0, m4, m1 ;out59\n paddsw m4, m1 ;out4\n mova [rsp+gprsize*2+16*39], m6 ;out36\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*62], m0 ;out59\n mova [rsp+gprsize*2+16*7 ], m4 ;out4\n mova m0, [rsp+gprsize*2+16*23] ;tmp[20]\n mova m5, [rsp+gprsize*2+16*14] ;tmp[11]\n psubsw m4, m0, m3 ;out43\n paddsw m0, m3 ;out20\n psubsw m6, m5, m2 ;out52\n paddsw m5, m2 ;out11\n mova [rsp+gprsize*2+16*46], m4 ;out43\n mova [rsp+gprsize*2+16*23], m0 ;out20\n mova [rsp+gprsize*2+16*55], m6 ;out52\n mova [rsp+gprsize*2+16*14], m5 ;out11\n\n mova m0, [rsp+gprsize*2+16*40] ;t37a\n mova m5, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*61] ;t58a\n mova m2, [rsp+gprsize*2+16*29] ;tmp[26]\n psubsw m4, m0, m5 ;t42\n paddsw m0, m5 ;t37\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t58\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t43, t52\n mova m3, [rsp+gprsize*2+16*8 ] ;tmp[5 ]\n psubsw m6, m2, m0 ;out37\n paddsw m2, m0 ;out26\n psubsw m0, m3, m1 ;out58\n paddsw m3, m1 ;out5\n mova [rsp+gprsize*2+16*40], m6 ;out37\n mova [rsp+gprsize*2+16*29], m2 ;out26\n mova [rsp+gprsize*2+16*61], m0 ;out58\n mova [rsp+gprsize*2+16*8 ], m3 ;out5\n mova m0, [rsp+gprsize*2+16*24] ;tmp[21]\n mova m1, [rsp+gprsize*2+16*13] ;tmp[10]\n psubsw m2, m0, m5 ;out42\n paddsw m0, m5 ;out21\n psubsw m3, m1, m4 ;out53\n paddsw m1, m4 ;out10\n mova [rsp+gprsize*2+16*45], m2 ;out42\n mova [rsp+gprsize*2+16*24], m0 ;out21\n mova [rsp+gprsize*2+16*56], m3 ;out53\n mova [rsp+gprsize*2+16*13], m1 ;out10\n\n mova m0, [rsp+gprsize*2+16*41] ;t38\n mova m5, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*60] ;t57\n mova m2, [rsp+gprsize*2+16*28] ;tmp[25]\n psubsw m4, m0, m5 ;t41a\n paddsw m0, m5 ;t38a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t57a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t41a, t54a\n mova m3, [rsp+gprsize*2+16*9 ] ;tmp[6 ]\n psubsw m6, m2, m0 ;out38\n paddsw m2, m0 ;out25\n psubsw m0, m3, m1 ;out57\n paddsw m3, m1 ;out6\n mova [rsp+gprsize*2+16*41], m6 ;out38\n mova [rsp+gprsize*2+16*28], m2 ;out25\n mova [rsp+gprsize*2+16*60], m0 ;out57\n mova [rsp+gprsize*2+16*9 ], m3 ;out6\n mova m0, [rsp+gprsize*2+16*25] ;tmp[22]\n mova m1, [rsp+gprsize*2+16*12] ;tmp[9 ]\n psubsw m2, m0, m5 ;out41\n paddsw m0, m5 ;out22\n psubsw m3, m1, m4 ;out54\n paddsw m1, m4 ;out9\n mova [rsp+gprsize*2+16*44], m2 ;out41\n mova [rsp+gprsize*2+16*25], m0 ;out22\n mova [rsp+gprsize*2+16*57], m3 ;out54\n mova [rsp+gprsize*2+16*12], m1 ;out9\n\n mova m0, [rsp+gprsize*2+16*42] ;t39a\n mova m5, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*59] ;t56a\n mova m2, [rsp+gprsize*2+16*27] ;tmp[24]\n psubsw m4, m0, m5 ;t40\n paddsw m0, m5 ;t39\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t56\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t40a, t55a\n mova m3, [rsp+gprsize*2+16*10] ;tmp[7 ]\n psubsw m6, m2, m0 ;out39\n paddsw m2, m0 ;out24\n psubsw m0, m3, m1 ;out56\n paddsw m3, m1 ;out7\n mova [rsp+gprsize*2+16*42], m6 ;out39\n mova [rsp+gprsize*2+16*27], m2 ;out24\n mova [rsp+gprsize*2+16*59], m0 ;out56\n mova [rsp+gprsize*2+16*10], m3 ;out7\n mova m0, [rsp+gprsize*2+16*26] ;tmp[23]\n mova m1, [rsp+gprsize*2+16*11] ;tmp[8 ]\n psubsw m2, m0, m5 ;out40\n paddsw m0, m5 ;out23\n psubsw m3, m1, m4 ;out55\n paddsw m1, m4 ;out8\n mova [rsp+gprsize*2+16*43], m2 ;out40\n mova [rsp+gprsize*2+16*26], m0 ;out23\n mova [rsp+gprsize*2+16*58], m3 ;out55\n mova [rsp+gprsize*2+16*11], m1 ;out8\n\n mova m0, [rsp+gprsize*2+16*37] ;t34\n mova m5, [rsp+gprsize*2+16*48] ;t45\n mova m3, [rsp+gprsize*2+16*53] ;t50\n mova m1, [rsp+gprsize*2+16*64] ;t61\n mova m2, [rsp+gprsize*2+16*32] ;tmp[29]\n psubsw m4, m0, m5 ;t45a\n paddsw m0, m5 ;t34a\n psubsw m5, m1, m3 ;t50a\n paddsw m1, m3 ;t61a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*5 ] ;tmp[2 ]\n psubsw m6, m2, m0 ;out34\n paddsw m2, m0 ;out29\n psubsw m0, m3, m1 ;out61\n paddsw m3, m1 ;out2\n mova [rsp+gprsize*2+16*37], m6 ;out34\n mova [rsp+gprsize*2+16*32], m2 ;out29\n mova [rsp+gprsize*2+16*64], m0 ;out61\n mova [rsp+gprsize*2+16*5 ], m3 ;out2\n mova m0, [rsp+gprsize*2+16*21] ;tmp[18]\n mova m1, [rsp+gprsize*2+16*16] ;tmp[13]\n psubsw m2, m0, m5 ;out45\n paddsw m0, m5 ;out18\n psubsw m3, m1, m4 ;out50\n paddsw m1, m4 ;out13\n mova [rsp+gprsize*2+16*48], m2 ;out45\n mova [rsp+gprsize*2+16*21], m0 ;out18\n mova [rsp+gprsize*2+16*53], m3 ;out50\n mova [rsp+gprsize*2+16*16], m1 ;out13\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m5, [rsp+gprsize*2+16*49] ;t46a\n mova m3, [rsp+gprsize*2+16*52] ;t49a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n mova m2, [rsp+gprsize*2+16*33] ;tmp[30]\n psubsw m4, m0, m5 ;t46\n paddsw m0, m5 ;t33\n psubsw m5, m1, m3 ;t49\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*4 ] ;tmp[1 ]\n psubsw m6, m2, m0 ;out33\n paddsw m2, m0 ;out30\n psubsw m0, m3, m1 ;out62\n paddsw m3, m1 ;out1\n mova [rsp+gprsize*2+16*36], m6 ;out33\n mova [rsp+gprsize*2+16*33], m2 ;out30\n mova [rsp+gprsize*2+16*65], m0 ;out62\n mova [rsp+gprsize*2+16*4 ], m3 ;out1\n mova m0, [rsp+gprsize*2+16*20] ;tmp[17]\n mova m1, [rsp+gprsize*2+16*17] ;tmp[14]\n psubsw m2, m0, m5 ;out46\n paddsw m0, m5 ;out17\n psubsw m3, m1, m4 ;out49\n paddsw m1, m4 ;out14\n mova [rsp+gprsize*2+16*49], m2 ;out46\n mova [rsp+gprsize*2+16*20], m0 ;out17\n mova [rsp+gprsize*2+16*52], m3 ;out49\n mova [rsp+gprsize*2+16*17], m1 ;out14\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m5, [rsp+gprsize*2+16*50] ;t47\n mova m3, [rsp+gprsize*2+16*51] ;t48\n mova m1, [rsp+gprsize*2+16*66] ;t63\n mova m2, [rsp+gprsize*2+16*34] ;tmp[31]\n psubsw m4, m0, m5 ;t47a\n paddsw m0, m5 ;t32a\n psubsw m5, m1, m3 ;t48a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t47, t48\n mova m3, [rsp+gprsize*2+16*3 ] ;tmp[0 ]\n psubsw m6, m2, m0 ;out32\n paddsw m2, m0 ;out31\n psubsw m0, m3, m1 ;out63\n paddsw m3, m1 ;out0\n mova [rsp+gprsize*2+16*35], m6 ;out32\n mova [rsp+gprsize*2+16*34], m2 ;out31\n mova [rsp+gprsize*2+16*66], m0 ;out63\n mova [rsp+gprsize*2+16*3 ], m3 ;out0\n mova m0, [rsp+gprsize*2+16*19] ;tmp[16]\n mova m1, [rsp+gprsize*2+16*18] ;tmp[15]\n psubsw m2, m0, m5 ;out47\n paddsw m0, m5 ;out16\n psubsw m3, m1, m4 ;out48\n paddsw m1, m4 ;out15\n mova [rsp+gprsize*2+16*50], m2 ;out47\n mova [rsp+gprsize*2+16*19], m0 ;out16\n mova [rsp+gprsize*2+16*51], m3 ;out48\n mova [rsp+gprsize*2+16*18], m1 ;out15\n ret\n\n\ncglobal inv_txfm_add_dct_dct_64x16, 4, 6, 8, 16*132, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x16_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x16).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m7, m7\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n mova m5, [dstq+16*2]\n mova m6, [dstq+16*3]\n punpckhbw m2, m1, m7\n punpcklbw m1, m7\n punpckhbw m4, m3, m7\n punpcklbw m3, m7\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n punpckhbw m2, m5, m7\n punpcklbw m5, m7\n punpckhbw m4, m6, m7\n punpcklbw m6, m7\n paddw m2, m0\n paddw m5, m0\n paddw m4, m0\n paddw m6, m0\n packuswb m5, m2\n packuswb m6, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n mova [dstq+16*2], m5\n mova [dstq+16*3], m6\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\n%macro LOAD_4ROWS 2-3 0 ;src, stride, is_rect2\n\n%if %3\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [%1+%2*0]\n pmulhrsw m1, m3, [%1+%2*1]\n pmulhrsw m2, m3, [%1+%2*2]\n pmulhrsw m3, [%1+%2*3]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n%endif\n%endmacro\n\n%macro LOAD_4ROWS_H 2 ;src, stride\n mova m4, [%1+%2*0]\n mova m5, [%1+%2*1]\n mova m6, [%1+%2*2]\n mova m7, [%1+%2*3]\n%endmacro\n\ncglobal idct_64x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mov r3d, 2\n mov [rsp+gprsize*2+16*67], dstq\n lea dstq, [rsp+gprsize+16*68]\n\n.pass1_loop:\n LOAD_4ROWS coeffq+32*0, 32*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+32*4, 32*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+32*2, 32*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+32*1, 32*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+32*17, 32*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+32*24, 32\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+32*24, 32\n\n add coeffq, 16\n add dstq, 16\n dec r3d\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*2+16*67]\n sub coeffq, 32\n mov r3d, 4\n\n.pass2_loop:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop\n\n mov r3d, 4\n lea coeffq, [rsp+gprsize+16*68]\n.pass2_loop2:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end2)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end3)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end3:\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop2\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x64).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n.end:\n RET\n\n\ncglobal idct_32x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*67]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n LOAD_4ROWS coeffq, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+128*1, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x32, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\n.end:\n RET\n\ncglobal idct_64x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*4+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8, 1\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*3+16*67]\n mov eobd, [rsp+gprsize*1+16*67]\n lea dstq, [dstq+32]\n mov [rsp+gprsize*1+16*35], eobd\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n.pass2_end:\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg m(idct_32x32_internal).pass2_loop\n\n.pass2_end2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x64, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\ncglobal idct_64x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*4+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*2+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea dstq, [dstq+32]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n jmp m(idct_16x64_internal).pass2_loop\n\n.pass2_end:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x64_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n\n dec r3\n jg m(idct_16x64_internal).pass2_loop\n\n.pass2_end2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, 4\n sub dstq, 72\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n"}}},{"rowIdx":480,"cells":{"commit":{"kind":"string","value":"6f7773dff705c47245df23d19559caeca2ceee1a"},"subject":{"kind":"string","value":"x86: add avx512icl cpu flag to x86inc.asm"},"message":{"kind":"string","value":"x86: add avx512icl cpu flag to x86inc.asm\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/ext/x86/x86inc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":";*****************************************************************************\n;* x86inc.asm: x264asm abstraction layer\n;*****************************************************************************\n;* Copyright (C) 2005-2019 x264 project\n;*\n;* Authors: Loren Merritt <lorenm@u.washington.edu>\n;* Henrik Gramner <henrik@gramner.com>\n;* Anton Mitrofanov <BugMaster@narod.ru>\n;* Fiona Glaser <fiona@x264.com>\n;*\n;* Permission to use, copy, modify, and/or distribute this software for any\n;* purpose with or without fee is hereby granted, provided that the above\n;* copyright notice and this permission notice appear in all copies.\n;*\n;* THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n;*****************************************************************************\n\n; This is a header file for the x264ASM assembly language, which uses\n; NASM/YASM syntax combined with a large number of macros to provide easy\n; abstraction between different calling conventions (x86_32, win64, linux64).\n; It also has various other useful features to simplify writing the kind of\n; DSP functions that are most often used in x264.\n\n; Unlike the rest of x264, this file is available under an ISC license, as it\n; has significant usefulness outside of x264 and we want it to be available\n; to the largest audience possible. Of course, if you modify it for your own\n; purposes to add a new feature, we strongly encourage contributing a patch\n; as this feature might be useful for others as well. Send patches or ideas\n; to x264-devel@videolan.org .\n\n%include \"config.asm\"\n\n%ifndef private_prefix\n %define private_prefix dav1d\n%endif\n\n%ifndef public_prefix\n %define public_prefix private_prefix\n%endif\n\n%ifndef STACK_ALIGNMENT\n %if ARCH_X86_64\n %define STACK_ALIGNMENT 16\n %else\n %define STACK_ALIGNMENT 4\n %endif\n%endif\n\n%define WIN64 0\n%define UNIX64 0\n%if ARCH_X86_64\n %ifidn __OUTPUT_FORMAT__,win32\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,win64\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,x64\n %define WIN64 1\n %else\n %define UNIX64 1\n %endif\n%endif\n\n%define FORMAT_ELF 0\n%define FORMAT_MACHO 0\n%ifidn __OUTPUT_FORMAT__,elf\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf32\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf64\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,macho\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho32\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho64\n %define FORMAT_MACHO 1\n%endif\n\n%ifdef PREFIX\n %define mangle(x) _ %+ x\n%else\n %define mangle(x) x\n%endif\n\n%macro SECTION_RODATA 0-1 16\n %ifidn __OUTPUT_FORMAT__,win32\n SECTION .rdata align=%1\n %elif WIN64\n SECTION .rdata align=%1\n %else\n SECTION .rodata align=%1\n %endif\n%endmacro\n\n%if ARCH_X86_64\n %define PIC 1 ; always use PIC on x86-64\n default rel\n%elifidn __OUTPUT_FORMAT__,win32\n %define PIC 0 ; PIC isn't used on 32-bit Windows\n%elifndef PIC\n %define PIC 0\n%endif\n\n%define HAVE_PRIVATE_EXTERN 1\n%ifdef __NASM_VER__\n %use smartalign\n %if __NASM_VERSION_ID__ < 0x020e0000 ; 2.14\n %define HAVE_PRIVATE_EXTERN 0\n %endif\n%endif\n\n; Macros to eliminate most code duplication between x86_32 and x86_64:\n; Currently this works only for leaf functions which load all their arguments\n; into registers at the start, and make no other use of the stack. Luckily that\n; covers most of x264's asm.\n\n; PROLOGUE:\n; %1 = number of arguments. loads them from stack if needed.\n; %2 = number of registers used. pushes callee-saved regs if needed.\n; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.\n; %4 = (optional) stack size to be allocated. The stack will be aligned before\n; allocating the specified stack size. If the required stack alignment is\n; larger than the known stack alignment the stack will be manually aligned\n; and an extra register will be allocated to hold the original stack\n; pointer (to not invalidate r0m etc.). To prevent the use of an extra\n; register as stack pointer, request a negative stack size.\n; %4+/%5+ = list of names to define to registers\n; PROLOGUE can also be invoked by adding the same options to cglobal\n\n; e.g.\n; cglobal foo, 2,3,7,0x40, dst, src, tmp\n; declares a function (foo) that automatically loads two arguments (dst and\n; src) into registers, uses one additional register (tmp) plus 7 vector\n; registers (m0-m6) and allocates 0x40 bytes of stack space.\n\n; TODO Some functions can use some args directly from the stack. If they're the\n; last args then you can just not declare them, but if they're in the middle\n; we need more flexible macro.\n\n; RET:\n; Pops anything that was pushed by PROLOGUE, and returns.\n\n; REP_RET:\n; Use this instead of RET if it's a branch target.\n\n; registers:\n; rN and rNq are the native-size register holding function argument N\n; rNd, rNw, rNb are dword, word, and byte size\n; rNh is the high 8 bits of the word size\n; rNm is the original location of arg N (a register or on the stack), dword\n; rNmp is native size\n\n%macro DECLARE_REG 2-3\n %define r%1q %2\n %define r%1d %2d\n %define r%1w %2w\n %define r%1b %2b\n %define r%1h %2h\n %define %2q %2\n %if %0 == 2\n %define r%1m %2d\n %define r%1mp %2\n %elif ARCH_X86_64 ; memory\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp qword r %+ %1 %+ m\n %else\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp dword r %+ %1 %+ m\n %endif\n %define r%1 %2\n%endmacro\n\n%macro DECLARE_REG_SIZE 3\n %define r%1q r%1\n %define e%1q r%1\n %define r%1d e%1\n %define e%1d e%1\n %define r%1w %1\n %define e%1w %1\n %define r%1h %3\n %define e%1h %3\n %define r%1b %2\n %define e%1b %2\n %if ARCH_X86_64 == 0\n %define r%1 e%1\n %endif\n%endmacro\n\nDECLARE_REG_SIZE ax, al, ah\nDECLARE_REG_SIZE bx, bl, bh\nDECLARE_REG_SIZE cx, cl, ch\nDECLARE_REG_SIZE dx, dl, dh\nDECLARE_REG_SIZE si, sil, null\nDECLARE_REG_SIZE di, dil, null\nDECLARE_REG_SIZE bp, bpl, null\n\n; t# defines for when per-arch register allocation is more complex than just function arguments\n\n%macro DECLARE_REG_TMP 1-*\n %assign %%i 0\n %rep %0\n CAT_XDEFINE t, %%i, r%1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n%endmacro\n\n%macro DECLARE_REG_TMP_SIZE 0-*\n %rep %0\n %define t%1q t%1 %+ q\n %define t%1d t%1 %+ d\n %define t%1w t%1 %+ w\n %define t%1h t%1 %+ h\n %define t%1b t%1 %+ b\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14\n\n%if ARCH_X86_64\n %define gprsize 8\n%else\n %define gprsize 4\n%endif\n\n%macro LEA 2\n%if ARCH_X86_64\n lea %1, [%2]\n%elif PIC\n call $+5 ; special-cased to not affect the RSB on most CPU:s\n pop %1\n add %1, (%2)-$+1\n%else\n mov %1, %2\n%endif\n%endmacro\n\n%macro PUSH 1\n push %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset+gprsize\n %endif\n%endmacro\n\n%macro POP 1\n pop %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset-gprsize\n %endif\n%endmacro\n\n%macro PUSH_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n PUSH r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro POP_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n pop r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro LOAD_IF_USED 1-*\n %rep %0\n %if %1 < num_args\n mov r%1, r %+ %1 %+ mp\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro SUB 2\n sub %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset+(%2)\n %endif\n%endmacro\n\n%macro ADD 2\n add %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset-(%2)\n %endif\n%endmacro\n\n%macro movifnidn 2\n %ifnidn %1, %2\n mov %1, %2\n %endif\n%endmacro\n\n%if ARCH_X86_64 == 0\n %define movsxd movifnidn\n%endif\n\n%macro movsxdifnidn 2\n %ifnidn %1, %2\n movsxd %1, %2\n %endif\n%endmacro\n\n%macro ASSERT 1\n %if (%1) == 0\n %error assertion ``%1'' failed\n %endif\n%endmacro\n\n%macro DEFINE_ARGS 0-*\n %ifdef n_arg_names\n %assign %%i 0\n %rep n_arg_names\n CAT_UNDEF arg_name %+ %%i, q\n CAT_UNDEF arg_name %+ %%i, d\n CAT_UNDEF arg_name %+ %%i, w\n CAT_UNDEF arg_name %+ %%i, h\n CAT_UNDEF arg_name %+ %%i, b\n CAT_UNDEF arg_name %+ %%i, m\n CAT_UNDEF arg_name %+ %%i, mp\n CAT_UNDEF arg_name, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n\n %xdefine %%stack_offset stack_offset\n %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine\n %assign %%i 0\n %rep %0\n %xdefine %1q r %+ %%i %+ q\n %xdefine %1d r %+ %%i %+ d\n %xdefine %1w r %+ %%i %+ w\n %xdefine %1h r %+ %%i %+ h\n %xdefine %1b r %+ %%i %+ b\n %xdefine %1m r %+ %%i %+ m\n %xdefine %1mp r %+ %%i %+ mp\n CAT_XDEFINE arg_name, %%i, %1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n %xdefine stack_offset %%stack_offset\n %assign n_arg_names %0\n%endmacro\n\n%define required_stack_alignment ((mmsize + 15) & ~15)\n%define vzeroupper_required (mmsize > 16 && (ARCH_X86_64 == 0 || xmm_regs_used > 16 || notcpuflag(avx512)))\n%define high_mm_regs (16*cpuflag(avx512))\n\n%macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)\n %ifnum %1\n %if %1 != 0\n %assign %%pad 0\n %assign stack_size %1\n %if stack_size < 0\n %assign stack_size -stack_size\n %endif\n %if WIN64\n %assign %%pad %%pad + 32 ; shadow space\n %if mmsize != 8\n %assign xmm_regs_used %2\n %if xmm_regs_used > 8\n %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers\n %endif\n %endif\n %endif\n %if required_stack_alignment <= STACK_ALIGNMENT\n ; maintain the current stack alignment\n %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %else\n %assign %%reg_num (regs_used - 1)\n %xdefine rstk r %+ %%reg_num\n ; align stack, and save original stack location directly above\n ; it, i.e. in [rsp+stack_size_padded], so we can restore the\n ; stack in a single instruction (i.e. mov rsp, rstk or mov\n ; rsp, [rsp+stack_size_padded])\n %if %1 < 0 ; need to store rsp on stack\n %xdefine rstkm [rsp + stack_size + %%pad]\n %assign %%pad %%pad + gprsize\n %else ; can keep rsp in rstk during whole function\n %xdefine rstkm rstk\n %endif\n %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))\n mov rstk, rsp\n and rsp, ~(required_stack_alignment-1)\n sub rsp, stack_size_padded\n movifnidn rstkm, rstk\n %endif\n WIN64_PUSH_XMM\n %endif\n %endif\n%endmacro\n\n%macro SETUP_STACK_POINTER 1\n %ifnum %1\n %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT\n %if %1 > 0\n ; Reserve an additional register for storing the original stack pointer, but avoid using\n ; eax/rax for this purpose since it can potentially get overwritten as a return value.\n %assign regs_used (regs_used + 1)\n %if ARCH_X86_64 && regs_used == 7\n %assign regs_used 8\n %elif ARCH_X86_64 == 0 && regs_used == 1\n %assign regs_used 2\n %endif\n %endif\n %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3\n ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)\n ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.\n %assign regs_used 5 + UNIX64 * 3\n %endif\n %endif\n %endif\n%endmacro\n\n%macro DEFINE_ARGS_INTERNAL 3+\n %ifnum %2\n DEFINE_ARGS %3\n %elif %1 == 4\n DEFINE_ARGS %2\n %elif %1 > 4\n DEFINE_ARGS %2, %3\n %endif\n%endmacro\n\n%if WIN64 ; Windows x64 ;=================================================\n\nDECLARE_REG 0, rcx\nDECLARE_REG 1, rdx\nDECLARE_REG 2, R8\nDECLARE_REG 3, R9\nDECLARE_REG 4, R10, 40\nDECLARE_REG 5, R11, 48\nDECLARE_REG 6, rax, 56\nDECLARE_REG 7, rdi, 64\nDECLARE_REG 8, rsi, 72\nDECLARE_REG 9, rbx, 80\nDECLARE_REG 10, rbp, 88\nDECLARE_REG 11, R14, 96\nDECLARE_REG 12, R15, 104\nDECLARE_REG 13, R12, 112\nDECLARE_REG 14, R13, 120\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4, %3\n %if mmsize != 8 && stack_size == 0\n WIN64_SPILL_XMM %3\n %endif\n LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%macro WIN64_PUSH_XMM 0\n ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.\n %if xmm_regs_used > 6 + high_mm_regs\n movaps [rstk + stack_offset + 8], xmm6\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps [rstk + stack_offset + 24], xmm7\n %endif\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i 8\n %rep %%xmm_regs_on_stack\n movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro WIN64_SPILL_XMM 1\n %assign xmm_regs_used %1\n ASSERT xmm_regs_used <= 16 + high_mm_regs\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.\n %assign %%pad %%xmm_regs_on_stack*16 + 32\n %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %endif\n WIN64_PUSH_XMM\n%endmacro\n\n%macro WIN64_RESTORE_XMM_INTERNAL 0\n %assign %%pad_size 0\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i xmm_regs_used - high_mm_regs\n %rep %%xmm_regs_on_stack\n %assign %%i %%i-1\n movaps xmm %+ %%i, [rsp + (%%i-8)*16 + stack_size + 32]\n %endrep\n %endif\n %if stack_size_padded > 0\n %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %assign %%pad_size stack_size_padded\n %endif\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps xmm7, [rsp + stack_offset - %%pad_size + 24]\n %endif\n %if xmm_regs_used > 6 + high_mm_regs\n movaps xmm6, [rsp + stack_offset - %%pad_size + 8]\n %endif\n%endmacro\n\n%macro WIN64_RESTORE_XMM 0\n WIN64_RESTORE_XMM_INTERNAL\n %assign stack_offset (stack_offset-stack_size_padded)\n %assign stack_size_padded 0\n %assign xmm_regs_used 0\n%endmacro\n\n%define has_epilogue regs_used > 7 || stack_size > 0 || vzeroupper_required || xmm_regs_used > 6+high_mm_regs\n\n%macro RET 0\n WIN64_RESTORE_XMM_INTERNAL\n POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%elif ARCH_X86_64 ; *nix x64 ;=============================================\n\nDECLARE_REG 0, rdi\nDECLARE_REG 1, rsi\nDECLARE_REG 2, rdx\nDECLARE_REG 3, rcx\nDECLARE_REG 4, R8\nDECLARE_REG 5, R9\nDECLARE_REG 6, rax, 8\nDECLARE_REG 7, R10, 16\nDECLARE_REG 8, R11, 24\nDECLARE_REG 9, rbx, 32\nDECLARE_REG 10, rbp, 40\nDECLARE_REG 11, R14, 48\nDECLARE_REG 12, R15, 56\nDECLARE_REG 13, R12, 64\nDECLARE_REG 14, R13, 72\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n %assign xmm_regs_used %3\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4\n LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 9 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 14, 13, 12, 11, 10, 9\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%else ; X86_32 ;==============================================================\n\nDECLARE_REG 0, eax, 4\nDECLARE_REG 1, ecx, 8\nDECLARE_REG 2, edx, 12\nDECLARE_REG 3, ebx, 16\nDECLARE_REG 4, esi, 20\nDECLARE_REG 5, edi, 24\nDECLARE_REG 6, ebp, 28\n%define rsp esp\n\n%macro DECLARE_ARG 1-*\n %rep %0\n %define r%1m [rstk + stack_offset + 4*%1 + 4]\n %define r%1mp dword r%1m\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14\n\n%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n %if num_args > 7\n %assign num_args 7\n %endif\n %if regs_used > 7\n %assign regs_used 7\n %endif\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 7\n PUSH_IF_USED 3, 4, 5, 6\n ALLOC_STACK %4\n LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 3 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 6, 5, 4, 3\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%endif ;======================================================================\n\n%if WIN64 == 0\n %macro WIN64_SPILL_XMM 1\n %endmacro\n %macro WIN64_RESTORE_XMM 0\n %endmacro\n %macro WIN64_PUSH_XMM 0\n %endmacro\n%endif\n\n; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either\n; a branch or a branch target. So switch to a 2-byte form of ret in that case.\n; We can automatically detect \"follows a branch\", but not a branch target.\n; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)\n%macro REP_RET 0\n %if has_epilogue || cpuflag(ssse3)\n RET\n %else\n rep ret\n %endif\n annotate_function_size\n%endmacro\n\n%define last_branch_adr $$\n%macro AUTO_REP_RET 0\n %if notcpuflag(ssse3)\n times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.\n %endif\n ret\n annotate_function_size\n%endmacro\n\n%macro BRANCH_INSTR 0-*\n %rep %0\n %macro %1 1-2 %1\n %2 %1\n %if notcpuflag(ssse3)\n %%branch_instr equ $\n %xdefine last_branch_adr %%branch_instr\n %endif\n %endmacro\n %rotate 1\n %endrep\n%endmacro\n\nBRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp\n\n%macro TAIL_CALL 1-2 1 ; callee, is_nonadjacent\n %if has_epilogue\n call %1\n RET\n %elif %2\n jmp %1\n %endif\n annotate_function_size\n%endmacro\n\n;=============================================================================\n; arch-independent part\n;=============================================================================\n\n%assign function_align 16\n\n; Begin a function.\n; Applies any symbol mangling needed for C linkage, and sets up a define such that\n; subsequent uses of the function name automatically refer to the mangled version.\n; Appends cpuflags to the function name if cpuflags has been specified.\n; The \"\" empty default parameter is a workaround for nasm, which fails if SUFFIX\n; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).\n%macro cglobal 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 1, %1 %+ SUFFIX, %2\n%endmacro\n%macro cvisible 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 0, %1 %+ SUFFIX, %2\n%endmacro\n%macro cglobal_internal 2-3+\n annotate_function_size\n %ifndef cglobaled_%2\n %if %1\n %xdefine %2 mangle(private_prefix %+ _ %+ %2)\n %else\n %xdefine %2 mangle(public_prefix %+ _ %+ %2)\n %endif\n %xdefine %2.skip_prologue %2 %+ .skip_prologue\n CAT_XDEFINE cglobaled_, %2, 1\n %endif\n %xdefine current_function %2\n %xdefine current_function_section __SECT__\n %if FORMAT_ELF\n %if %1\n global %2:function hidden\n %else\n global %2:function\n %endif\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN && %1\n global %2:private_extern\n %else\n global %2\n %endif\n align function_align\n %2:\n RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer\n %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required\n %assign stack_offset 0 ; stack pointer offset relative to the return address\n %assign stack_size 0 ; amount of stack space that can be freely used inside a function\n %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding\n %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64 and vzeroupper\n %ifnidn %3, \"\"\n PROLOGUE %3\n %endif\n%endmacro\n\n; Create a global symbol from a local label with the correct name mangling and type\n%macro cglobal_label 1\n %if FORMAT_ELF\n global current_function %+ %1:function hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global current_function %+ %1:private_extern\n %else\n global current_function %+ %1\n %endif\n %1:\n%endmacro\n\n%macro cextern 1\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n; like cextern, but without the prefix\n%macro cextern_naked 1\n %ifdef PREFIX\n %xdefine %1 mangle(%1)\n %endif\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n%macro const 1-2+\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n %if FORMAT_ELF\n global %1:data hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global %1:private_extern\n %else\n global %1\n %endif\n %1: %2\n%endmacro\n\n; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.\n%if FORMAT_ELF\n [SECTION .note.GNU-stack noalloc noexec nowrite progbits]\n%endif\n\n; Tell debuggers how large the function was.\n; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.\n; This is invoked by RET and similar macros, and also cglobal does it for the previous function,\n; but if the last function in a source file doesn't use any of the standard macros for its epilogue,\n; then its size might be unspecified.\n%macro annotate_function_size 0\n %ifdef __YASM_VER__\n %ifdef current_function\n %if FORMAT_ELF\n current_function_section\n %%ecf equ $\n size current_function %%ecf - current_function\n __SECT__\n %endif\n %endif\n %endif\n%endmacro\n\n; cpuflags\n\n%assign cpuflags_mmx (1<<0)\n%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx\n%assign cpuflags_3dnow (1<<2) | cpuflags_mmx\n%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow\n%assign cpuflags_sse (1<<4) | cpuflags_mmx2\n%assign cpuflags_sse2 (1<<5) | cpuflags_sse\n%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2\n%assign cpuflags_lzcnt (1<<7) | cpuflags_sse2\n%assign cpuflags_sse3 (1<<8) | cpuflags_sse2\n%assign cpuflags_ssse3 (1<<9) | cpuflags_sse3\n%assign cpuflags_sse4 (1<<10) | cpuflags_ssse3\n%assign cpuflags_sse42 (1<<11) | cpuflags_sse4\n%assign cpuflags_aesni (1<<12) | cpuflags_sse42\n%assign cpuflags_gfni (1<<13) | cpuflags_sse42\n%assign cpuflags_avx (1<<14) | cpuflags_sse42\n%assign cpuflags_xop (1<<15) | cpuflags_avx\n%assign cpuflags_fma4 (1<<16) | cpuflags_avx\n%assign cpuflags_fma3 (1<<17) | cpuflags_avx\n%assign cpuflags_bmi1 (1<<18) | cpuflags_avx|cpuflags_lzcnt\n%assign cpuflags_bmi2 (1<<19) | cpuflags_bmi1\n%assign cpuflags_avx2 (1<<20) | cpuflags_fma3|cpuflags_bmi2\n%assign cpuflags_avx512 (1<<21) | cpuflags_avx2 ; F, CD, BW, DQ, VL\n%assign cpuflags_avx512icl (1<<22) | cpuflags_avx512|cpuflags_gfni ; VNNI, IFMA, VBMI, VBMI2, VPOPCNTDQ, BITALG, VAES, VPCLMULQDQ\n\n%assign cpuflags_cache32 (1<<23)\n%assign cpuflags_cache64 (1<<24)\n%assign cpuflags_aligned (1<<25) ; not a cpu feature, but a function variant\n%assign cpuflags_atom (1<<26)\n\n; Returns a boolean value expressing whether or not the specified cpuflag is enabled.\n%define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)\n%define notcpuflag(x) (cpuflag(x) ^ 1)\n\n; Takes an arbitrary number of cpuflags from the above list.\n; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.\n; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.\n%macro INIT_CPUFLAGS 0-*\n %xdefine SUFFIX\n %undef cpuname\n %assign cpuflags 0\n\n %if %0 >= 1\n %rep %0\n %ifdef cpuname\n %xdefine cpuname cpuname %+ _%1\n %else\n %xdefine cpuname %1\n %endif\n %assign cpuflags cpuflags | cpuflags_%1\n %rotate 1\n %endrep\n %xdefine SUFFIX _ %+ cpuname\n\n %if cpuflag(avx)\n %assign avx_enabled 1\n %endif\n %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))\n %define mova movaps\n %define movu movups\n %define movnta movntps\n %endif\n %if cpuflag(aligned)\n %define movu mova\n %elif cpuflag(sse3) && notcpuflag(ssse3)\n %define movu lddqu\n %endif\n %endif\n\n %if ARCH_X86_64 || cpuflag(sse2)\n %ifdef __NASM_VER__\n ALIGNMODE p6\n %else\n CPU amdnop\n %endif\n %else\n %ifdef __NASM_VER__\n ALIGNMODE nop\n %else\n CPU basicnop\n %endif\n %endif\n%endmacro\n\n; Merge mmx, sse*, and avx*\n; m# is a simd register of the currently selected size\n; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#\n; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#\n; zm# is the corresponding zmm register if mmsize >= 64, otherwise the same as m#\n; (All 4 remain in sync through SWAP.)\n\n%macro CAT_XDEFINE 3\n %xdefine %1%2 %3\n%endmacro\n\n%macro CAT_UNDEF 2\n %undef %1%2\n%endmacro\n\n%macro DEFINE_MMREGS 1 ; mmtype\n %assign %%prev_mmregs 0\n %ifdef num_mmregs\n %assign %%prev_mmregs num_mmregs\n %endif\n\n %assign num_mmregs 8\n %if ARCH_X86_64 && mmsize >= 16\n %assign num_mmregs 16\n %if cpuflag(avx512) || mmsize == 64\n %assign num_mmregs 32\n %endif\n %endif\n\n %assign %%i 0\n %rep num_mmregs\n CAT_XDEFINE m, %%i, %1 %+ %%i\n CAT_XDEFINE nn%1, %%i, %%i\n %assign %%i %%i+1\n %endrep\n %if %%prev_mmregs > num_mmregs\n %rep %%prev_mmregs - num_mmregs\n CAT_UNDEF m, %%i\n CAT_UNDEF nn %+ mmtype, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n %xdefine mmtype %1\n%endmacro\n\n; Prefer registers 16-31 over 0-15 to avoid having to use vzeroupper\n%macro AVX512_MM_PERMUTATION 0-1 0 ; start_reg\n %if ARCH_X86_64 && cpuflag(avx512)\n %assign %%i %1\n %rep 16-%1\n %assign %%i_high %%i+16\n SWAP %%i, %%i_high\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro INIT_MMX 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_MMX %1\n %define mmsize 8\n %define mova movq\n %define movu movq\n %define movh movd\n %define movnta movntq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS mm\n%endmacro\n\n%macro INIT_XMM 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_XMM %1\n %define mmsize 16\n %define mova movdqa\n %define movu movdqu\n %define movh movq\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS xmm\n %if WIN64\n AVX512_MM_PERMUTATION 6 ; Swap callee-saved registers with volatile registers\n %endif\n%endmacro\n\n%macro INIT_YMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_YMM %1\n %define mmsize 32\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS ymm\n AVX512_MM_PERMUTATION\n%endmacro\n\n%macro INIT_ZMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_ZMM %1\n %define mmsize 64\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS zmm\n AVX512_MM_PERMUTATION\n%endmacro\n\nINIT_XMM\n\n%macro DECLARE_MMCAST 1\n %define mmmm%1 mm%1\n %define mmxmm%1 mm%1\n %define mmymm%1 mm%1\n %define mmzmm%1 mm%1\n %define xmmmm%1 mm%1\n %define xmmxmm%1 xmm%1\n %define xmmymm%1 xmm%1\n %define xmmzmm%1 xmm%1\n %define ymmmm%1 mm%1\n %define ymmxmm%1 xmm%1\n %define ymmymm%1 ymm%1\n %define ymmzmm%1 ymm%1\n %define zmmmm%1 mm%1\n %define zmmxmm%1 xmm%1\n %define zmmymm%1 ymm%1\n %define zmmzmm%1 zmm%1\n %define xm%1 xmm %+ m%1\n %define ym%1 ymm %+ m%1\n %define zm%1 zmm %+ m%1\n%endmacro\n\n%assign i 0\n%rep 32\n DECLARE_MMCAST i\n %assign i i+1\n%endrep\n\n; I often want to use macros that permute their arguments. e.g. there's no\n; efficient way to implement butterfly or transpose or dct without swapping some\n; arguments.\n;\n; I would like to not have to manually keep track of the permutations:\n; If I insert a permutation in the middle of a function, it should automatically\n; change everything that follows. For more complex macros I may also have multiple\n; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.\n;\n; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that\n; permutes its arguments. It's equivalent to exchanging the contents of the\n; registers, except that this way you exchange the register names instead, so it\n; doesn't cost any cycles.\n\n%macro PERMUTE 2-* ; takes a list of pairs to swap\n %rep %0/2\n %xdefine %%tmp%2 m%2\n %rotate 2\n %endrep\n %rep %0/2\n %xdefine m%1 %%tmp%2\n CAT_XDEFINE nn, m%1, %1\n %rotate 2\n %endrep\n%endmacro\n\n%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)\n %ifnum %1 ; SWAP 0, 1, ...\n SWAP_INTERNAL_NUM %1, %2\n %else ; SWAP m0, m1, ...\n SWAP_INTERNAL_NAME %1, %2\n %endif\n%endmacro\n\n%macro SWAP_INTERNAL_NUM 2-*\n %rep %0-1\n %xdefine %%tmp m%1\n %xdefine m%1 m%2\n %xdefine m%2 %%tmp\n CAT_XDEFINE nn, m%1, %1\n CAT_XDEFINE nn, m%2, %2\n %rotate 1\n %endrep\n%endmacro\n\n%macro SWAP_INTERNAL_NAME 2-*\n %xdefine %%args nn %+ %1\n %rep %0-1\n %xdefine %%args %%args, nn %+ %2\n %rotate 1\n %endrep\n SWAP_INTERNAL_NUM %%args\n%endmacro\n\n; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later\n; calls to that function will automatically load the permutation, so values can\n; be returned in mmregs.\n%macro SAVE_MM_PERMUTATION 0-1\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp m %+ %%i\n CAT_XDEFINE %%f, %%i, regnumof %+ %%tmp\n %assign %%i %%i+1\n %endrep\n%endmacro\n\n%macro LOAD_MM_PERMUTATION 0-1 ; name to load from\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %xdefine %%tmp %%f %+ 0\n %ifnum %%tmp\n RESET_MM_PERMUTATION\n AVX512_MM_PERMUTATION\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp %%f %+ %%i\n CAT_XDEFINE %%m, %%i, m %+ %%tmp\n %assign %%i %%i+1\n %endrep\n %rep num_mmregs\n %assign %%i %%i-1\n CAT_XDEFINE m, %%i, %%m %+ %%i\n CAT_XDEFINE nn, m %+ %%i, %%i\n %endrep\n %endif\n%endmacro\n\n; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't\n%macro call 1\n %ifid %1\n call_internal %1 %+ SUFFIX, %1\n %else\n call %1\n %endif\n%endmacro\n%macro call_internal 2\n %xdefine %%i %2\n %ifndef cglobaled_%2\n %ifdef cglobaled_%1\n %xdefine %%i %1\n %endif\n %endif\n call %%i\n LOAD_MM_PERMUTATION %%i\n%endmacro\n\n; Substitutions that reduce instruction size but are functionally equivalent\n%macro add 2\n %ifnum %2\n %if %2==128\n sub %1, -128\n %else\n add %1, %2\n %endif\n %else\n add %1, %2\n %endif\n%endmacro\n\n%macro sub 2\n %ifnum %2\n %if %2==128\n add %1, -128\n %else\n sub %1, %2\n %endif\n %else\n sub %1, %2\n %endif\n%endmacro\n\n;=============================================================================\n; AVX abstraction layer\n;=============================================================================\n\n%assign i 0\n%rep 32\n %if i < 8\n CAT_XDEFINE sizeofmm, i, 8\n CAT_XDEFINE regnumofmm, i, i\n %endif\n CAT_XDEFINE sizeofxmm, i, 16\n CAT_XDEFINE sizeofymm, i, 32\n CAT_XDEFINE sizeofzmm, i, 64\n CAT_XDEFINE regnumofxmm, i, i\n CAT_XDEFINE regnumofymm, i, i\n CAT_XDEFINE regnumofzmm, i, i\n %assign i i+1\n%endrep\n%undef i\n\n%macro CHECK_AVX_INSTR_EMU 3-*\n %xdefine %%opcode %1\n %xdefine %%dst %2\n %rep %0-2\n %ifidn %%dst, %3\n %error non-avx emulation of ``%%opcode'' is not supported\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n;%6+: operands\n%macro RUN_AVX_INSTR 6-9+\n %ifnum sizeof%7\n %assign __sizeofreg sizeof%7\n %elifnum sizeof%6\n %assign __sizeofreg sizeof%6\n %else\n %assign __sizeofreg mmsize\n %endif\n %assign __emulate_avx 0\n %if avx_enabled && __sizeofreg >= 16\n %xdefine __instr v%1\n %else\n %xdefine __instr %1\n %if %0 >= 8+%4\n %assign __emulate_avx 1\n %endif\n %endif\n %ifnidn %2, fnord\n %ifdef cpuname\n %if notcpuflag(%2)\n %error use of ``%1'' %2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 16 && notcpuflag(sse2)\n %error use of ``%1'' sse2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 32 && notcpuflag(avx2)\n %error use of ``%1'' avx2 instruction in cpuname function: current_function\n %elifidn %1, pextrw ; special case because the base instruction is mmx2,\n %ifnid %6 ; but sse4 is required for memory operands\n %if notcpuflag(sse4)\n %error use of ``%1'' sse4 instruction in cpuname function: current_function\n %endif\n %endif\n %endif\n %endif\n %endif\n\n %if __emulate_avx\n %xdefine __src1 %7\n %xdefine __src2 %8\n %if %5 && %4 == 0\n %ifnidn %6, %7\n %ifidn %6, %8\n %xdefine __src1 %8\n %xdefine __src2 %7\n %elifnnum sizeof%8\n ; 3-operand AVX instructions with a memory arg can only have it in src2,\n ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).\n ; So, if the instruction is commutative with a memory arg, swap them.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n %ifnidn %6, __src1\n %if %0 >= 9\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, __src2, %9\n %else\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, __src2\n %endif\n %if __sizeofreg == 8\n MOVQ %6, __src1\n %elif %3\n MOVAPS %6, __src1\n %else\n MOVDQA %6, __src1\n %endif\n %endif\n %if %0 >= 9\n %1 %6, __src2, %9\n %else\n %1 %6, __src2\n %endif\n %elif %0 >= 9\n __instr %6, %7, %8, %9\n %elif %0 == 8\n %if avx_enabled && %5\n %xdefine __src1 %7\n %xdefine __src2 %8\n %ifnum regnumof%7\n %ifnum regnumof%8\n %if regnumof%7 < 8 && regnumof%8 >= 8 && regnumof%8 < 16 && sizeof%8 <= 32\n ; Most VEX-encoded instructions require an additional byte to encode when\n ; src2 is a high register (e.g. m8..15). If the instruction is commutative\n ; we can swap src1 and src2 when doing so reduces the instruction length.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7, %8\n %endif\n %elif %0 == 7\n %if avx_enabled && %5\n %xdefine __src1 %6\n %xdefine __src2 %7\n %ifnum regnumof%6\n %ifnum regnumof%7\n %if regnumof%6 < 8 && regnumof%7 >= 8 && regnumof%7 < 16 && sizeof%7 <= 32\n %xdefine __src1 %7\n %xdefine __src2 %6\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7\n %endif\n %else\n __instr %6\n %endif\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n%macro AVX_INSTR 1-5 fnord, 0, 255, 0\n %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5\n %ifidn %2, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1\n %elifidn %3, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2\n %elifidn %4, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3\n %elifidn %5, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4\n %else\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5\n %endif\n %endmacro\n%endmacro\n\n; Instructions with both VEX/EVEX and legacy encodings\n; Non-destructive instructions are written without parameters\nAVX_INSTR addpd, sse2, 1, 0, 1\nAVX_INSTR addps, sse, 1, 0, 1\nAVX_INSTR addsd, sse2, 1, 0, 0\nAVX_INSTR addss, sse, 1, 0, 0\nAVX_INSTR addsubpd, sse3, 1, 0, 0\nAVX_INSTR addsubps, sse3, 1, 0, 0\nAVX_INSTR aesdec, aesni, 0, 0, 0\nAVX_INSTR aesdeclast, aesni, 0, 0, 0\nAVX_INSTR aesenc, aesni, 0, 0, 0\nAVX_INSTR aesenclast, aesni, 0, 0, 0\nAVX_INSTR aesimc, aesni\nAVX_INSTR aeskeygenassist, aesni\nAVX_INSTR andnpd, sse2, 1, 0, 0\nAVX_INSTR andnps, sse, 1, 0, 0\nAVX_INSTR andpd, sse2, 1, 0, 1\nAVX_INSTR andps, sse, 1, 0, 1\nAVX_INSTR blendpd, sse4, 1, 1, 0\nAVX_INSTR blendps, sse4, 1, 1, 0\nAVX_INSTR blendvpd, sse4 ; can't be emulated\nAVX_INSTR blendvps, sse4 ; can't be emulated\nAVX_INSTR cmpeqpd, sse2, 1, 0, 1\nAVX_INSTR cmpeqps, sse, 1, 0, 1\nAVX_INSTR cmpeqsd, sse2, 1, 0, 0\nAVX_INSTR cmpeqss, sse, 1, 0, 0\nAVX_INSTR cmplepd, sse2, 1, 0, 0\nAVX_INSTR cmpleps, sse, 1, 0, 0\nAVX_INSTR cmplesd, sse2, 1, 0, 0\nAVX_INSTR cmpless, sse, 1, 0, 0\nAVX_INSTR cmpltpd, sse2, 1, 0, 0\nAVX_INSTR cmpltps, sse, 1, 0, 0\nAVX_INSTR cmpltsd, sse2, 1, 0, 0\nAVX_INSTR cmpltss, sse, 1, 0, 0\nAVX_INSTR cmpneqpd, sse2, 1, 0, 1\nAVX_INSTR cmpneqps, sse, 1, 0, 1\nAVX_INSTR cmpneqsd, sse2, 1, 0, 0\nAVX_INSTR cmpneqss, sse, 1, 0, 0\nAVX_INSTR cmpnlepd, sse2, 1, 0, 0\nAVX_INSTR cmpnleps, sse, 1, 0, 0\nAVX_INSTR cmpnlesd, sse2, 1, 0, 0\nAVX_INSTR cmpnless, sse, 1, 0, 0\nAVX_INSTR cmpnltpd, sse2, 1, 0, 0\nAVX_INSTR cmpnltps, sse, 1, 0, 0\nAVX_INSTR cmpnltsd, sse2, 1, 0, 0\nAVX_INSTR cmpnltss, sse, 1, 0, 0\nAVX_INSTR cmpordpd, sse2 1, 0, 1\nAVX_INSTR cmpordps, sse 1, 0, 1\nAVX_INSTR cmpordsd, sse2 1, 0, 0\nAVX_INSTR cmpordss, sse 1, 0, 0\nAVX_INSTR cmppd, sse2, 1, 1, 0\nAVX_INSTR cmpps, sse, 1, 1, 0\nAVX_INSTR cmpsd, sse2, 1, 1, 0\nAVX_INSTR cmpss, sse, 1, 1, 0\nAVX_INSTR cmpunordpd, sse2, 1, 0, 1\nAVX_INSTR cmpunordps, sse, 1, 0, 1\nAVX_INSTR cmpunordsd, sse2, 1, 0, 0\nAVX_INSTR cmpunordss, sse, 1, 0, 0\nAVX_INSTR comisd, sse2, 1\nAVX_INSTR comiss, sse, 1\nAVX_INSTR cvtdq2pd, sse2, 1\nAVX_INSTR cvtdq2ps, sse2, 1\nAVX_INSTR cvtpd2dq, sse2, 1\nAVX_INSTR cvtpd2ps, sse2, 1\nAVX_INSTR cvtps2dq, sse2, 1\nAVX_INSTR cvtps2pd, sse2, 1\nAVX_INSTR cvtsd2si, sse2, 1\nAVX_INSTR cvtsd2ss, sse2, 1, 0, 0\nAVX_INSTR cvtsi2sd, sse2, 1, 0, 0\nAVX_INSTR cvtsi2ss, sse, 1, 0, 0\nAVX_INSTR cvtss2sd, sse2, 1, 0, 0\nAVX_INSTR cvtss2si, sse, 1\nAVX_INSTR cvttpd2dq, sse2, 1\nAVX_INSTR cvttps2dq, sse2, 1\nAVX_INSTR cvttsd2si, sse2, 1\nAVX_INSTR cvttss2si, sse, 1\nAVX_INSTR divpd, sse2, 1, 0, 0\nAVX_INSTR divps, sse, 1, 0, 0\nAVX_INSTR divsd, sse2, 1, 0, 0\nAVX_INSTR divss, sse, 1, 0, 0\nAVX_INSTR dppd, sse4, 1, 1, 0\nAVX_INSTR dpps, sse4, 1, 1, 0\nAVX_INSTR extractps, sse4, 1\nAVX_INSTR gf2p8affineinvqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8affineqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8mulb, gfni, 0, 0, 0\nAVX_INSTR haddpd, sse3, 1, 0, 0\nAVX_INSTR haddps, sse3, 1, 0, 0\nAVX_INSTR hsubpd, sse3, 1, 0, 0\nAVX_INSTR hsubps, sse3, 1, 0, 0\nAVX_INSTR insertps, sse4, 1, 1, 0\nAVX_INSTR lddqu, sse3\nAVX_INSTR ldmxcsr, sse, 1\nAVX_INSTR maskmovdqu, sse2\nAVX_INSTR maxpd, sse2, 1, 0, 1\nAVX_INSTR maxps, sse, 1, 0, 1\nAVX_INSTR maxsd, sse2, 1, 0, 0\nAVX_INSTR maxss, sse, 1, 0, 0\nAVX_INSTR minpd, sse2, 1, 0, 1\nAVX_INSTR minps, sse, 1, 0, 1\nAVX_INSTR minsd, sse2, 1, 0, 0\nAVX_INSTR minss, sse, 1, 0, 0\nAVX_INSTR movapd, sse2, 1\nAVX_INSTR movaps, sse, 1\nAVX_INSTR movd, mmx\nAVX_INSTR movddup, sse3, 1\nAVX_INSTR movdqa, sse2\nAVX_INSTR movdqu, sse2\nAVX_INSTR movhlps, sse, 1, 0, 0\nAVX_INSTR movhpd, sse2, 1, 0, 0\nAVX_INSTR movhps, sse, 1, 0, 0\nAVX_INSTR movlhps, sse, 1, 0, 0\nAVX_INSTR movlpd, sse2, 1, 0, 0\nAVX_INSTR movlps, sse, 1, 0, 0\nAVX_INSTR movmskpd, sse2, 1\nAVX_INSTR movmskps, sse, 1\nAVX_INSTR movntdq, sse2\nAVX_INSTR movntdqa, sse4\nAVX_INSTR movntpd, sse2, 1\nAVX_INSTR movntps, sse, 1\nAVX_INSTR movq, mmx\nAVX_INSTR movsd, sse2, 1, 0, 0\nAVX_INSTR movshdup, sse3, 1\nAVX_INSTR movsldup, sse3, 1\nAVX_INSTR movss, sse, 1, 0, 0\nAVX_INSTR movupd, sse2, 1\nAVX_INSTR movups, sse, 1\nAVX_INSTR mpsadbw, sse4, 0, 1, 0\nAVX_INSTR mulpd, sse2, 1, 0, 1\nAVX_INSTR mulps, sse, 1, 0, 1\nAVX_INSTR mulsd, sse2, 1, 0, 0\nAVX_INSTR mulss, sse, 1, 0, 0\nAVX_INSTR orpd, sse2, 1, 0, 1\nAVX_INSTR orps, sse, 1, 0, 1\nAVX_INSTR pabsb, ssse3\nAVX_INSTR pabsd, ssse3\nAVX_INSTR pabsw, ssse3\nAVX_INSTR packsswb, mmx, 0, 0, 0\nAVX_INSTR packssdw, mmx, 0, 0, 0\nAVX_INSTR packuswb, mmx, 0, 0, 0\nAVX_INSTR packusdw, sse4, 0, 0, 0\nAVX_INSTR paddb, mmx, 0, 0, 1\nAVX_INSTR paddw, mmx, 0, 0, 1\nAVX_INSTR paddd, mmx, 0, 0, 1\nAVX_INSTR paddq, sse2, 0, 0, 1\nAVX_INSTR paddsb, mmx, 0, 0, 1\nAVX_INSTR paddsw, mmx, 0, 0, 1\nAVX_INSTR paddusb, mmx, 0, 0, 1\nAVX_INSTR paddusw, mmx, 0, 0, 1\nAVX_INSTR palignr, ssse3, 0, 1, 0\nAVX_INSTR pand, mmx, 0, 0, 1\nAVX_INSTR pandn, mmx, 0, 0, 0\nAVX_INSTR pavgb, mmx2, 0, 0, 1\nAVX_INSTR pavgw, mmx2, 0, 0, 1\nAVX_INSTR pblendvb, sse4 ; can't be emulated\nAVX_INSTR pblendw, sse4, 0, 1, 0\nAVX_INSTR pclmulqdq, fnord, 0, 1, 0\nAVX_INSTR pclmulhqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmulhqlqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqlqdq, fnord, 0, 0, 0\nAVX_INSTR pcmpestri, sse42\nAVX_INSTR pcmpestrm, sse42\nAVX_INSTR pcmpistri, sse42\nAVX_INSTR pcmpistrm, sse42\nAVX_INSTR pcmpeqb, mmx, 0, 0, 1\nAVX_INSTR pcmpeqw, mmx, 0, 0, 1\nAVX_INSTR pcmpeqd, mmx, 0, 0, 1\nAVX_INSTR pcmpeqq, sse4, 0, 0, 1\nAVX_INSTR pcmpgtb, mmx, 0, 0, 0\nAVX_INSTR pcmpgtw, mmx, 0, 0, 0\nAVX_INSTR pcmpgtd, mmx, 0, 0, 0\nAVX_INSTR pcmpgtq, sse42, 0, 0, 0\nAVX_INSTR pextrb, sse4\nAVX_INSTR pextrd, sse4\nAVX_INSTR pextrq, sse4\nAVX_INSTR pextrw, mmx2\nAVX_INSTR phaddw, ssse3, 0, 0, 0\nAVX_INSTR phaddd, ssse3, 0, 0, 0\nAVX_INSTR phaddsw, ssse3, 0, 0, 0\nAVX_INSTR phminposuw, sse4\nAVX_INSTR phsubw, ssse3, 0, 0, 0\nAVX_INSTR phsubd, ssse3, 0, 0, 0\nAVX_INSTR phsubsw, ssse3, 0, 0, 0\nAVX_INSTR pinsrb, sse4, 0, 1, 0\nAVX_INSTR pinsrd, sse4, 0, 1, 0\nAVX_INSTR pinsrq, sse4, 0, 1, 0\nAVX_INSTR pinsrw, mmx2, 0, 1, 0\nAVX_INSTR pmaddwd, mmx, 0, 0, 1\nAVX_INSTR pmaddubsw, ssse3, 0, 0, 0\nAVX_INSTR pmaxsb, sse4, 0, 0, 1\nAVX_INSTR pmaxsw, mmx2, 0, 0, 1\nAVX_INSTR pmaxsd, sse4, 0, 0, 1\nAVX_INSTR pmaxub, mmx2, 0, 0, 1\nAVX_INSTR pmaxuw, sse4, 0, 0, 1\nAVX_INSTR pmaxud, sse4, 0, 0, 1\nAVX_INSTR pminsb, sse4, 0, 0, 1\nAVX_INSTR pminsw, mmx2, 0, 0, 1\nAVX_INSTR pminsd, sse4, 0, 0, 1\nAVX_INSTR pminub, mmx2, 0, 0, 1\nAVX_INSTR pminuw, sse4, 0, 0, 1\nAVX_INSTR pminud, sse4, 0, 0, 1\nAVX_INSTR pmovmskb, mmx2\nAVX_INSTR pmovsxbw, sse4\nAVX_INSTR pmovsxbd, sse4\nAVX_INSTR pmovsxbq, sse4\nAVX_INSTR pmovsxwd, sse4\nAVX_INSTR pmovsxwq, sse4\nAVX_INSTR pmovsxdq, sse4\nAVX_INSTR pmovzxbw, sse4\nAVX_INSTR pmovzxbd, sse4\nAVX_INSTR pmovzxbq, sse4\nAVX_INSTR pmovzxwd, sse4\nAVX_INSTR pmovzxwq, sse4\nAVX_INSTR pmovzxdq, sse4\nAVX_INSTR pmuldq, sse4, 0, 0, 1\nAVX_INSTR pmulhrsw, ssse3, 0, 0, 1\nAVX_INSTR pmulhuw, mmx2, 0, 0, 1\nAVX_INSTR pmulhw, mmx, 0, 0, 1\nAVX_INSTR pmullw, mmx, 0, 0, 1\nAVX_INSTR pmulld, sse4, 0, 0, 1\nAVX_INSTR pmuludq, sse2, 0, 0, 1\nAVX_INSTR por, mmx, 0, 0, 1\nAVX_INSTR psadbw, mmx2, 0, 0, 1\nAVX_INSTR pshufb, ssse3, 0, 0, 0\nAVX_INSTR pshufd, sse2\nAVX_INSTR pshufhw, sse2\nAVX_INSTR pshuflw, sse2\nAVX_INSTR psignb, ssse3, 0, 0, 0\nAVX_INSTR psignw, ssse3, 0, 0, 0\nAVX_INSTR psignd, ssse3, 0, 0, 0\nAVX_INSTR psllw, mmx, 0, 0, 0\nAVX_INSTR pslld, mmx, 0, 0, 0\nAVX_INSTR psllq, mmx, 0, 0, 0\nAVX_INSTR pslldq, sse2, 0, 0, 0\nAVX_INSTR psraw, mmx, 0, 0, 0\nAVX_INSTR psrad, mmx, 0, 0, 0\nAVX_INSTR psrlw, mmx, 0, 0, 0\nAVX_INSTR psrld, mmx, 0, 0, 0\nAVX_INSTR psrlq, mmx, 0, 0, 0\nAVX_INSTR psrldq, sse2, 0, 0, 0\nAVX_INSTR psubb, mmx, 0, 0, 0\nAVX_INSTR psubw, mmx, 0, 0, 0\nAVX_INSTR psubd, mmx, 0, 0, 0\nAVX_INSTR psubq, sse2, 0, 0, 0\nAVX_INSTR psubsb, mmx, 0, 0, 0\nAVX_INSTR psubsw, mmx, 0, 0, 0\nAVX_INSTR psubusb, mmx, 0, 0, 0\nAVX_INSTR psubusw, mmx, 0, 0, 0\nAVX_INSTR ptest, sse4\nAVX_INSTR punpckhbw, mmx, 0, 0, 0\nAVX_INSTR punpckhwd, mmx, 0, 0, 0\nAVX_INSTR punpckhdq, mmx, 0, 0, 0\nAVX_INSTR punpckhqdq, sse2, 0, 0, 0\nAVX_INSTR punpcklbw, mmx, 0, 0, 0\nAVX_INSTR punpcklwd, mmx, 0, 0, 0\nAVX_INSTR punpckldq, mmx, 0, 0, 0\nAVX_INSTR punpcklqdq, sse2, 0, 0, 0\nAVX_INSTR pxor, mmx, 0, 0, 1\nAVX_INSTR rcpps, sse, 1\nAVX_INSTR rcpss, sse, 1, 0, 0\nAVX_INSTR roundpd, sse4, 1\nAVX_INSTR roundps, sse4, 1\nAVX_INSTR roundsd, sse4, 1, 1, 0\nAVX_INSTR roundss, sse4, 1, 1, 0\nAVX_INSTR rsqrtps, sse, 1\nAVX_INSTR rsqrtss, sse, 1, 0, 0\nAVX_INSTR shufpd, sse2, 1, 1, 0\nAVX_INSTR shufps, sse, 1, 1, 0\nAVX_INSTR sqrtpd, sse2, 1\nAVX_INSTR sqrtps, sse, 1\nAVX_INSTR sqrtsd, sse2, 1, 0, 0\nAVX_INSTR sqrtss, sse, 1, 0, 0\nAVX_INSTR stmxcsr, sse, 1\nAVX_INSTR subpd, sse2, 1, 0, 0\nAVX_INSTR subps, sse, 1, 0, 0\nAVX_INSTR subsd, sse2, 1, 0, 0\nAVX_INSTR subss, sse, 1, 0, 0\nAVX_INSTR ucomisd, sse2, 1\nAVX_INSTR ucomiss, sse, 1\nAVX_INSTR unpckhpd, sse2, 1, 0, 0\nAVX_INSTR unpckhps, sse, 1, 0, 0\nAVX_INSTR unpcklpd, sse2, 1, 0, 0\nAVX_INSTR unpcklps, sse, 1, 0, 0\nAVX_INSTR xorpd, sse2, 1, 0, 1\nAVX_INSTR xorps, sse, 1, 0, 1\n\n; 3DNow instructions, for sharing code between AVX, SSE and 3DN\nAVX_INSTR pfadd, 3dnow, 1, 0, 1\nAVX_INSTR pfsub, 3dnow, 1, 0, 0\nAVX_INSTR pfmul, 3dnow, 1, 0, 1\n\n;%1 == instruction\n;%2 == minimal instruction set\n%macro GPR_INSTR 2\n %macro %1 2-5 fnord, %1, %2\n %ifdef cpuname\n %if notcpuflag(%5)\n %error use of ``%4'' %5 instruction in cpuname function: current_function\n %endif\n %endif\n %ifidn %3, fnord\n %4 %1, %2\n %else\n %4 %1, %2, %3\n %endif\n %endmacro\n%endmacro\n\nGPR_INSTR andn, bmi1\nGPR_INSTR bextr, bmi1\nGPR_INSTR blsi, bmi1\nGPR_INSTR blsmsk, bmi1\nGPR_INSTR bzhi, bmi2\nGPR_INSTR mulx, bmi2\nGPR_INSTR pdep, bmi2\nGPR_INSTR pext, bmi2\nGPR_INSTR popcnt, sse42\nGPR_INSTR rorx, bmi2\nGPR_INSTR sarx, bmi2\nGPR_INSTR shlx, bmi2\nGPR_INSTR shrx, bmi2\n\n; base-4 constants for shuffles\n%assign i 0\n%rep 256\n %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)\n %if j < 10\n CAT_XDEFINE q000, j, i\n %elif j < 100\n CAT_XDEFINE q00, j, i\n %elif j < 1000\n CAT_XDEFINE q0, j, i\n %else\n CAT_XDEFINE q, j, i\n %endif\n %assign i i+1\n%endrep\n%undef i\n%undef j\n\n%macro FMA_INSTR 3\n %macro %1 4-7 %1, %2, %3\n %if cpuflag(xop)\n v%5 %1, %2, %3, %4\n %elifnidn %1, %4\n %6 %1, %2, %3\n %7 %1, %4\n %else\n %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n%endmacro\n\nFMA_INSTR pmacsww, pmullw, paddw\nFMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation\nFMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation\nFMA_INSTR pmadcswd, pmaddwd, paddd\n\n; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.\n; FMA3 is only possible if dst is the same as one of the src registers.\n; Either src2 or src3 can be a memory operand.\n%macro FMA4_INSTR 2-*\n %push fma4_instr\n %xdefine %$prefix %1\n %rep %0 - 1\n %macro %$prefix%2 4-6 %$prefix, %2\n %if notcpuflag(fma3) && notcpuflag(fma4)\n %error use of ``%5%6'' fma instruction in cpuname function: current_function\n %elif cpuflag(fma4)\n v%5%6 %1, %2, %3, %4\n %elifidn %1, %2\n ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.\n %ifnum sizeof%3\n v%{5}213%6 %2, %3, %4\n %else\n v%{5}132%6 %2, %4, %3\n %endif\n %elifidn %1, %3\n v%{5}213%6 %3, %2, %4\n %elifidn %1, %4\n v%{5}231%6 %4, %2, %3\n %else\n %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n %rotate 1\n %endrep\n %pop\n%endmacro\n\nFMA4_INSTR fmadd, pd, ps, sd, ss\nFMA4_INSTR fmaddsub, pd, ps\nFMA4_INSTR fmsub, pd, ps, sd, ss\nFMA4_INSTR fmsubadd, pd, ps\nFMA4_INSTR fnmadd, pd, ps, sd, ss\nFMA4_INSTR fnmsub, pd, ps, sd, ss\n\n; Macros for converting VEX instructions to equivalent EVEX ones.\n%macro EVEX_INSTR 2-3 0 ; vex, evex, prefer_evex\n %macro %1 2-7 fnord, fnord, %1, %2, %3\n %ifidn %3, fnord\n %define %%args %1, %2\n %elifidn %4, fnord\n %define %%args %1, %2, %3\n %else\n %define %%args %1, %2, %3, %4\n %endif\n %assign %%evex_required cpuflag(avx512) & %7\n %ifnum regnumof%1\n %if regnumof%1 >= 16 || sizeof%1 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%2\n %if regnumof%2 >= 16 || sizeof%2 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%3\n %if regnumof%3 >= 16 || sizeof%3 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %if %%evex_required\n %6 %%args\n %else\n %5 %%args ; Prefer VEX over EVEX due to shorter instruction length\n %endif\n %endmacro\n%endmacro\n\nEVEX_INSTR vbroadcastf128, vbroadcastf32x4\nEVEX_INSTR vbroadcasti128, vbroadcasti32x4\nEVEX_INSTR vextractf128, vextractf32x4\nEVEX_INSTR vextracti128, vextracti32x4\nEVEX_INSTR vinsertf128, vinsertf32x4\nEVEX_INSTR vinserti128, vinserti32x4\nEVEX_INSTR vmovdqa, vmovdqa32\nEVEX_INSTR vmovdqu, vmovdqu32\nEVEX_INSTR vpand, vpandd\nEVEX_INSTR vpandn, vpandnd\nEVEX_INSTR vpor, vpord\nEVEX_INSTR vpxor, vpxord\nEVEX_INSTR vrcpps, vrcp14ps, 1 ; EVEX versions have higher precision\nEVEX_INSTR vrcpss, vrcp14ss, 1\nEVEX_INSTR vrsqrtps, vrsqrt14ps, 1\nEVEX_INSTR vrsqrtss, vrsqrt14ss, 1\n"},"old_contents":{"kind":"string","value":";*****************************************************************************\n;* x86inc.asm: x264asm abstraction layer\n;*****************************************************************************\n;* Copyright (C) 2005-2019 x264 project\n;*\n;* Authors: Loren Merritt <lorenm@u.washington.edu>\n;* Henrik Gramner <henrik@gramner.com>\n;* Anton Mitrofanov <BugMaster@narod.ru>\n;* Fiona Glaser <fiona@x264.com>\n;*\n;* Permission to use, copy, modify, and/or distribute this software for any\n;* purpose with or without fee is hereby granted, provided that the above\n;* copyright notice and this permission notice appear in all copies.\n;*\n;* THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n;*****************************************************************************\n\n; This is a header file for the x264ASM assembly language, which uses\n; NASM/YASM syntax combined with a large number of macros to provide easy\n; abstraction between different calling conventions (x86_32, win64, linux64).\n; It also has various other useful features to simplify writing the kind of\n; DSP functions that are most often used in x264.\n\n; Unlike the rest of x264, this file is available under an ISC license, as it\n; has significant usefulness outside of x264 and we want it to be available\n; to the largest audience possible. Of course, if you modify it for your own\n; purposes to add a new feature, we strongly encourage contributing a patch\n; as this feature might be useful for others as well. Send patches or ideas\n; to x264-devel@videolan.org .\n\n%include \"config.asm\"\n\n%ifndef private_prefix\n %define private_prefix dav1d\n%endif\n\n%ifndef public_prefix\n %define public_prefix private_prefix\n%endif\n\n%ifndef STACK_ALIGNMENT\n %if ARCH_X86_64\n %define STACK_ALIGNMENT 16\n %else\n %define STACK_ALIGNMENT 4\n %endif\n%endif\n\n%define WIN64 0\n%define UNIX64 0\n%if ARCH_X86_64\n %ifidn __OUTPUT_FORMAT__,win32\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,win64\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,x64\n %define WIN64 1\n %else\n %define UNIX64 1\n %endif\n%endif\n\n%define FORMAT_ELF 0\n%define FORMAT_MACHO 0\n%ifidn __OUTPUT_FORMAT__,elf\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf32\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf64\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,macho\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho32\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho64\n %define FORMAT_MACHO 1\n%endif\n\n%ifdef PREFIX\n %define mangle(x) _ %+ x\n%else\n %define mangle(x) x\n%endif\n\n%macro SECTION_RODATA 0-1 16\n %ifidn __OUTPUT_FORMAT__,win32\n SECTION .rdata align=%1\n %elif WIN64\n SECTION .rdata align=%1\n %else\n SECTION .rodata align=%1\n %endif\n%endmacro\n\n%if ARCH_X86_64\n %define PIC 1 ; always use PIC on x86-64\n default rel\n%elifidn __OUTPUT_FORMAT__,win32\n %define PIC 0 ; PIC isn't used on 32-bit Windows\n%elifndef PIC\n %define PIC 0\n%endif\n\n%define HAVE_PRIVATE_EXTERN 1\n%ifdef __NASM_VER__\n %use smartalign\n %if __NASM_VERSION_ID__ < 0x020e0000 ; 2.14\n %define HAVE_PRIVATE_EXTERN 0\n %endif\n%endif\n\n; Macros to eliminate most code duplication between x86_32 and x86_64:\n; Currently this works only for leaf functions which load all their arguments\n; into registers at the start, and make no other use of the stack. Luckily that\n; covers most of x264's asm.\n\n; PROLOGUE:\n; %1 = number of arguments. loads them from stack if needed.\n; %2 = number of registers used. pushes callee-saved regs if needed.\n; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.\n; %4 = (optional) stack size to be allocated. The stack will be aligned before\n; allocating the specified stack size. If the required stack alignment is\n; larger than the known stack alignment the stack will be manually aligned\n; and an extra register will be allocated to hold the original stack\n; pointer (to not invalidate r0m etc.). To prevent the use of an extra\n; register as stack pointer, request a negative stack size.\n; %4+/%5+ = list of names to define to registers\n; PROLOGUE can also be invoked by adding the same options to cglobal\n\n; e.g.\n; cglobal foo, 2,3,7,0x40, dst, src, tmp\n; declares a function (foo) that automatically loads two arguments (dst and\n; src) into registers, uses one additional register (tmp) plus 7 vector\n; registers (m0-m6) and allocates 0x40 bytes of stack space.\n\n; TODO Some functions can use some args directly from the stack. If they're the\n; last args then you can just not declare them, but if they're in the middle\n; we need more flexible macro.\n\n; RET:\n; Pops anything that was pushed by PROLOGUE, and returns.\n\n; REP_RET:\n; Use this instead of RET if it's a branch target.\n\n; registers:\n; rN and rNq are the native-size register holding function argument N\n; rNd, rNw, rNb are dword, word, and byte size\n; rNh is the high 8 bits of the word size\n; rNm is the original location of arg N (a register or on the stack), dword\n; rNmp is native size\n\n%macro DECLARE_REG 2-3\n %define r%1q %2\n %define r%1d %2d\n %define r%1w %2w\n %define r%1b %2b\n %define r%1h %2h\n %define %2q %2\n %if %0 == 2\n %define r%1m %2d\n %define r%1mp %2\n %elif ARCH_X86_64 ; memory\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp qword r %+ %1 %+ m\n %else\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp dword r %+ %1 %+ m\n %endif\n %define r%1 %2\n%endmacro\n\n%macro DECLARE_REG_SIZE 3\n %define r%1q r%1\n %define e%1q r%1\n %define r%1d e%1\n %define e%1d e%1\n %define r%1w %1\n %define e%1w %1\n %define r%1h %3\n %define e%1h %3\n %define r%1b %2\n %define e%1b %2\n %if ARCH_X86_64 == 0\n %define r%1 e%1\n %endif\n%endmacro\n\nDECLARE_REG_SIZE ax, al, ah\nDECLARE_REG_SIZE bx, bl, bh\nDECLARE_REG_SIZE cx, cl, ch\nDECLARE_REG_SIZE dx, dl, dh\nDECLARE_REG_SIZE si, sil, null\nDECLARE_REG_SIZE di, dil, null\nDECLARE_REG_SIZE bp, bpl, null\n\n; t# defines for when per-arch register allocation is more complex than just function arguments\n\n%macro DECLARE_REG_TMP 1-*\n %assign %%i 0\n %rep %0\n CAT_XDEFINE t, %%i, r%1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n%endmacro\n\n%macro DECLARE_REG_TMP_SIZE 0-*\n %rep %0\n %define t%1q t%1 %+ q\n %define t%1d t%1 %+ d\n %define t%1w t%1 %+ w\n %define t%1h t%1 %+ h\n %define t%1b t%1 %+ b\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14\n\n%if ARCH_X86_64\n %define gprsize 8\n%else\n %define gprsize 4\n%endif\n\n%macro LEA 2\n%if ARCH_X86_64\n lea %1, [%2]\n%elif PIC\n call $+5 ; special-cased to not affect the RSB on most CPU:s\n pop %1\n add %1, (%2)-$+1\n%else\n mov %1, %2\n%endif\n%endmacro\n\n%macro PUSH 1\n push %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset+gprsize\n %endif\n%endmacro\n\n%macro POP 1\n pop %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset-gprsize\n %endif\n%endmacro\n\n%macro PUSH_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n PUSH r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro POP_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n pop r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro LOAD_IF_USED 1-*\n %rep %0\n %if %1 < num_args\n mov r%1, r %+ %1 %+ mp\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro SUB 2\n sub %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset+(%2)\n %endif\n%endmacro\n\n%macro ADD 2\n add %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset-(%2)\n %endif\n%endmacro\n\n%macro movifnidn 2\n %ifnidn %1, %2\n mov %1, %2\n %endif\n%endmacro\n\n%if ARCH_X86_64 == 0\n %define movsxd movifnidn\n%endif\n\n%macro movsxdifnidn 2\n %ifnidn %1, %2\n movsxd %1, %2\n %endif\n%endmacro\n\n%macro ASSERT 1\n %if (%1) == 0\n %error assertion ``%1'' failed\n %endif\n%endmacro\n\n%macro DEFINE_ARGS 0-*\n %ifdef n_arg_names\n %assign %%i 0\n %rep n_arg_names\n CAT_UNDEF arg_name %+ %%i, q\n CAT_UNDEF arg_name %+ %%i, d\n CAT_UNDEF arg_name %+ %%i, w\n CAT_UNDEF arg_name %+ %%i, h\n CAT_UNDEF arg_name %+ %%i, b\n CAT_UNDEF arg_name %+ %%i, m\n CAT_UNDEF arg_name %+ %%i, mp\n CAT_UNDEF arg_name, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n\n %xdefine %%stack_offset stack_offset\n %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine\n %assign %%i 0\n %rep %0\n %xdefine %1q r %+ %%i %+ q\n %xdefine %1d r %+ %%i %+ d\n %xdefine %1w r %+ %%i %+ w\n %xdefine %1h r %+ %%i %+ h\n %xdefine %1b r %+ %%i %+ b\n %xdefine %1m r %+ %%i %+ m\n %xdefine %1mp r %+ %%i %+ mp\n CAT_XDEFINE arg_name, %%i, %1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n %xdefine stack_offset %%stack_offset\n %assign n_arg_names %0\n%endmacro\n\n%define required_stack_alignment ((mmsize + 15) & ~15)\n%define vzeroupper_required (mmsize > 16 && (ARCH_X86_64 == 0 || xmm_regs_used > 16 || notcpuflag(avx512)))\n%define high_mm_regs (16*cpuflag(avx512))\n\n%macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)\n %ifnum %1\n %if %1 != 0\n %assign %%pad 0\n %assign stack_size %1\n %if stack_size < 0\n %assign stack_size -stack_size\n %endif\n %if WIN64\n %assign %%pad %%pad + 32 ; shadow space\n %if mmsize != 8\n %assign xmm_regs_used %2\n %if xmm_regs_used > 8\n %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers\n %endif\n %endif\n %endif\n %if required_stack_alignment <= STACK_ALIGNMENT\n ; maintain the current stack alignment\n %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %else\n %assign %%reg_num (regs_used - 1)\n %xdefine rstk r %+ %%reg_num\n ; align stack, and save original stack location directly above\n ; it, i.e. in [rsp+stack_size_padded], so we can restore the\n ; stack in a single instruction (i.e. mov rsp, rstk or mov\n ; rsp, [rsp+stack_size_padded])\n %if %1 < 0 ; need to store rsp on stack\n %xdefine rstkm [rsp + stack_size + %%pad]\n %assign %%pad %%pad + gprsize\n %else ; can keep rsp in rstk during whole function\n %xdefine rstkm rstk\n %endif\n %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))\n mov rstk, rsp\n and rsp, ~(required_stack_alignment-1)\n sub rsp, stack_size_padded\n movifnidn rstkm, rstk\n %endif\n WIN64_PUSH_XMM\n %endif\n %endif\n%endmacro\n\n%macro SETUP_STACK_POINTER 1\n %ifnum %1\n %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT\n %if %1 > 0\n ; Reserve an additional register for storing the original stack pointer, but avoid using\n ; eax/rax for this purpose since it can potentially get overwritten as a return value.\n %assign regs_used (regs_used + 1)\n %if ARCH_X86_64 && regs_used == 7\n %assign regs_used 8\n %elif ARCH_X86_64 == 0 && regs_used == 1\n %assign regs_used 2\n %endif\n %endif\n %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3\n ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)\n ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.\n %assign regs_used 5 + UNIX64 * 3\n %endif\n %endif\n %endif\n%endmacro\n\n%macro DEFINE_ARGS_INTERNAL 3+\n %ifnum %2\n DEFINE_ARGS %3\n %elif %1 == 4\n DEFINE_ARGS %2\n %elif %1 > 4\n DEFINE_ARGS %2, %3\n %endif\n%endmacro\n\n%if WIN64 ; Windows x64 ;=================================================\n\nDECLARE_REG 0, rcx\nDECLARE_REG 1, rdx\nDECLARE_REG 2, R8\nDECLARE_REG 3, R9\nDECLARE_REG 4, R10, 40\nDECLARE_REG 5, R11, 48\nDECLARE_REG 6, rax, 56\nDECLARE_REG 7, rdi, 64\nDECLARE_REG 8, rsi, 72\nDECLARE_REG 9, rbx, 80\nDECLARE_REG 10, rbp, 88\nDECLARE_REG 11, R14, 96\nDECLARE_REG 12, R15, 104\nDECLARE_REG 13, R12, 112\nDECLARE_REG 14, R13, 120\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4, %3\n %if mmsize != 8 && stack_size == 0\n WIN64_SPILL_XMM %3\n %endif\n LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%macro WIN64_PUSH_XMM 0\n ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.\n %if xmm_regs_used > 6 + high_mm_regs\n movaps [rstk + stack_offset + 8], xmm6\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps [rstk + stack_offset + 24], xmm7\n %endif\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i 8\n %rep %%xmm_regs_on_stack\n movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro WIN64_SPILL_XMM 1\n %assign xmm_regs_used %1\n ASSERT xmm_regs_used <= 16 + high_mm_regs\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.\n %assign %%pad %%xmm_regs_on_stack*16 + 32\n %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %endif\n WIN64_PUSH_XMM\n%endmacro\n\n%macro WIN64_RESTORE_XMM_INTERNAL 0\n %assign %%pad_size 0\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i xmm_regs_used - high_mm_regs\n %rep %%xmm_regs_on_stack\n %assign %%i %%i-1\n movaps xmm %+ %%i, [rsp + (%%i-8)*16 + stack_size + 32]\n %endrep\n %endif\n %if stack_size_padded > 0\n %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %assign %%pad_size stack_size_padded\n %endif\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps xmm7, [rsp + stack_offset - %%pad_size + 24]\n %endif\n %if xmm_regs_used > 6 + high_mm_regs\n movaps xmm6, [rsp + stack_offset - %%pad_size + 8]\n %endif\n%endmacro\n\n%macro WIN64_RESTORE_XMM 0\n WIN64_RESTORE_XMM_INTERNAL\n %assign stack_offset (stack_offset-stack_size_padded)\n %assign stack_size_padded 0\n %assign xmm_regs_used 0\n%endmacro\n\n%define has_epilogue regs_used > 7 || stack_size > 0 || vzeroupper_required || xmm_regs_used > 6+high_mm_regs\n\n%macro RET 0\n WIN64_RESTORE_XMM_INTERNAL\n POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%elif ARCH_X86_64 ; *nix x64 ;=============================================\n\nDECLARE_REG 0, rdi\nDECLARE_REG 1, rsi\nDECLARE_REG 2, rdx\nDECLARE_REG 3, rcx\nDECLARE_REG 4, R8\nDECLARE_REG 5, R9\nDECLARE_REG 6, rax, 8\nDECLARE_REG 7, R10, 16\nDECLARE_REG 8, R11, 24\nDECLARE_REG 9, rbx, 32\nDECLARE_REG 10, rbp, 40\nDECLARE_REG 11, R14, 48\nDECLARE_REG 12, R15, 56\nDECLARE_REG 13, R12, 64\nDECLARE_REG 14, R13, 72\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n %assign xmm_regs_used %3\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4\n LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 9 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 14, 13, 12, 11, 10, 9\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%else ; X86_32 ;==============================================================\n\nDECLARE_REG 0, eax, 4\nDECLARE_REG 1, ecx, 8\nDECLARE_REG 2, edx, 12\nDECLARE_REG 3, ebx, 16\nDECLARE_REG 4, esi, 20\nDECLARE_REG 5, edi, 24\nDECLARE_REG 6, ebp, 28\n%define rsp esp\n\n%macro DECLARE_ARG 1-*\n %rep %0\n %define r%1m [rstk + stack_offset + 4*%1 + 4]\n %define r%1mp dword r%1m\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14\n\n%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n %if num_args > 7\n %assign num_args 7\n %endif\n %if regs_used > 7\n %assign regs_used 7\n %endif\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 7\n PUSH_IF_USED 3, 4, 5, 6\n ALLOC_STACK %4\n LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 3 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 6, 5, 4, 3\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%endif ;======================================================================\n\n%if WIN64 == 0\n %macro WIN64_SPILL_XMM 1\n %endmacro\n %macro WIN64_RESTORE_XMM 0\n %endmacro\n %macro WIN64_PUSH_XMM 0\n %endmacro\n%endif\n\n; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either\n; a branch or a branch target. So switch to a 2-byte form of ret in that case.\n; We can automatically detect \"follows a branch\", but not a branch target.\n; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)\n%macro REP_RET 0\n %if has_epilogue || cpuflag(ssse3)\n RET\n %else\n rep ret\n %endif\n annotate_function_size\n%endmacro\n\n%define last_branch_adr $$\n%macro AUTO_REP_RET 0\n %if notcpuflag(ssse3)\n times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.\n %endif\n ret\n annotate_function_size\n%endmacro\n\n%macro BRANCH_INSTR 0-*\n %rep %0\n %macro %1 1-2 %1\n %2 %1\n %if notcpuflag(ssse3)\n %%branch_instr equ $\n %xdefine last_branch_adr %%branch_instr\n %endif\n %endmacro\n %rotate 1\n %endrep\n%endmacro\n\nBRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp\n\n%macro TAIL_CALL 1-2 1 ; callee, is_nonadjacent\n %if has_epilogue\n call %1\n RET\n %elif %2\n jmp %1\n %endif\n annotate_function_size\n%endmacro\n\n;=============================================================================\n; arch-independent part\n;=============================================================================\n\n%assign function_align 16\n\n; Begin a function.\n; Applies any symbol mangling needed for C linkage, and sets up a define such that\n; subsequent uses of the function name automatically refer to the mangled version.\n; Appends cpuflags to the function name if cpuflags has been specified.\n; The \"\" empty default parameter is a workaround for nasm, which fails if SUFFIX\n; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).\n%macro cglobal 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 1, %1 %+ SUFFIX, %2\n%endmacro\n%macro cvisible 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 0, %1 %+ SUFFIX, %2\n%endmacro\n%macro cglobal_internal 2-3+\n annotate_function_size\n %ifndef cglobaled_%2\n %if %1\n %xdefine %2 mangle(private_prefix %+ _ %+ %2)\n %else\n %xdefine %2 mangle(public_prefix %+ _ %+ %2)\n %endif\n %xdefine %2.skip_prologue %2 %+ .skip_prologue\n CAT_XDEFINE cglobaled_, %2, 1\n %endif\n %xdefine current_function %2\n %xdefine current_function_section __SECT__\n %if FORMAT_ELF\n %if %1\n global %2:function hidden\n %else\n global %2:function\n %endif\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN && %1\n global %2:private_extern\n %else\n global %2\n %endif\n align function_align\n %2:\n RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer\n %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required\n %assign stack_offset 0 ; stack pointer offset relative to the return address\n %assign stack_size 0 ; amount of stack space that can be freely used inside a function\n %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding\n %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64 and vzeroupper\n %ifnidn %3, \"\"\n PROLOGUE %3\n %endif\n%endmacro\n\n; Create a global symbol from a local label with the correct name mangling and type\n%macro cglobal_label 1\n %if FORMAT_ELF\n global current_function %+ %1:function hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global current_function %+ %1:private_extern\n %else\n global current_function %+ %1\n %endif\n %1:\n%endmacro\n\n%macro cextern 1\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n; like cextern, but without the prefix\n%macro cextern_naked 1\n %ifdef PREFIX\n %xdefine %1 mangle(%1)\n %endif\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n%macro const 1-2+\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n %if FORMAT_ELF\n global %1:data hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global %1:private_extern\n %else\n global %1\n %endif\n %1: %2\n%endmacro\n\n; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.\n%if FORMAT_ELF\n [SECTION .note.GNU-stack noalloc noexec nowrite progbits]\n%endif\n\n; Tell debuggers how large the function was.\n; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.\n; This is invoked by RET and similar macros, and also cglobal does it for the previous function,\n; but if the last function in a source file doesn't use any of the standard macros for its epilogue,\n; then its size might be unspecified.\n%macro annotate_function_size 0\n %ifdef __YASM_VER__\n %ifdef current_function\n %if FORMAT_ELF\n current_function_section\n %%ecf equ $\n size current_function %%ecf - current_function\n __SECT__\n %endif\n %endif\n %endif\n%endmacro\n\n; cpuflags\n\n%assign cpuflags_mmx (1<<0)\n%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx\n%assign cpuflags_3dnow (1<<2) | cpuflags_mmx\n%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow\n%assign cpuflags_sse (1<<4) | cpuflags_mmx2\n%assign cpuflags_sse2 (1<<5) | cpuflags_sse\n%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2\n%assign cpuflags_lzcnt (1<<7) | cpuflags_sse2\n%assign cpuflags_sse3 (1<<8) | cpuflags_sse2\n%assign cpuflags_ssse3 (1<<9) | cpuflags_sse3\n%assign cpuflags_sse4 (1<<10)| cpuflags_ssse3\n%assign cpuflags_sse42 (1<<11)| cpuflags_sse4\n%assign cpuflags_aesni (1<<12)| cpuflags_sse42\n%assign cpuflags_gfni (1<<13)| cpuflags_sse42\n%assign cpuflags_avx (1<<14)| cpuflags_sse42\n%assign cpuflags_xop (1<<15)| cpuflags_avx\n%assign cpuflags_fma4 (1<<16)| cpuflags_avx\n%assign cpuflags_fma3 (1<<17)| cpuflags_avx\n%assign cpuflags_bmi1 (1<<18)| cpuflags_avx|cpuflags_lzcnt\n%assign cpuflags_bmi2 (1<<19)| cpuflags_bmi1\n%assign cpuflags_avx2 (1<<20)| cpuflags_fma3|cpuflags_bmi2\n%assign cpuflags_avx512 (1<<21)| cpuflags_avx2 ; F, CD, BW, DQ, VL\n\n%assign cpuflags_cache32 (1<<22)\n%assign cpuflags_cache64 (1<<23)\n%assign cpuflags_aligned (1<<24) ; not a cpu feature, but a function variant\n%assign cpuflags_atom (1<<25)\n\n; Returns a boolean value expressing whether or not the specified cpuflag is enabled.\n%define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)\n%define notcpuflag(x) (cpuflag(x) ^ 1)\n\n; Takes an arbitrary number of cpuflags from the above list.\n; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.\n; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.\n%macro INIT_CPUFLAGS 0-*\n %xdefine SUFFIX\n %undef cpuname\n %assign cpuflags 0\n\n %if %0 >= 1\n %rep %0\n %ifdef cpuname\n %xdefine cpuname cpuname %+ _%1\n %else\n %xdefine cpuname %1\n %endif\n %assign cpuflags cpuflags | cpuflags_%1\n %rotate 1\n %endrep\n %xdefine SUFFIX _ %+ cpuname\n\n %if cpuflag(avx)\n %assign avx_enabled 1\n %endif\n %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))\n %define mova movaps\n %define movu movups\n %define movnta movntps\n %endif\n %if cpuflag(aligned)\n %define movu mova\n %elif cpuflag(sse3) && notcpuflag(ssse3)\n %define movu lddqu\n %endif\n %endif\n\n %if ARCH_X86_64 || cpuflag(sse2)\n %ifdef __NASM_VER__\n ALIGNMODE p6\n %else\n CPU amdnop\n %endif\n %else\n %ifdef __NASM_VER__\n ALIGNMODE nop\n %else\n CPU basicnop\n %endif\n %endif\n%endmacro\n\n; Merge mmx, sse*, and avx*\n; m# is a simd register of the currently selected size\n; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#\n; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#\n; zm# is the corresponding zmm register if mmsize >= 64, otherwise the same as m#\n; (All 4 remain in sync through SWAP.)\n\n%macro CAT_XDEFINE 3\n %xdefine %1%2 %3\n%endmacro\n\n%macro CAT_UNDEF 2\n %undef %1%2\n%endmacro\n\n%macro DEFINE_MMREGS 1 ; mmtype\n %assign %%prev_mmregs 0\n %ifdef num_mmregs\n %assign %%prev_mmregs num_mmregs\n %endif\n\n %assign num_mmregs 8\n %if ARCH_X86_64 && mmsize >= 16\n %assign num_mmregs 16\n %if cpuflag(avx512) || mmsize == 64\n %assign num_mmregs 32\n %endif\n %endif\n\n %assign %%i 0\n %rep num_mmregs\n CAT_XDEFINE m, %%i, %1 %+ %%i\n CAT_XDEFINE nn%1, %%i, %%i\n %assign %%i %%i+1\n %endrep\n %if %%prev_mmregs > num_mmregs\n %rep %%prev_mmregs - num_mmregs\n CAT_UNDEF m, %%i\n CAT_UNDEF nn %+ mmtype, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n %xdefine mmtype %1\n%endmacro\n\n; Prefer registers 16-31 over 0-15 to avoid having to use vzeroupper\n%macro AVX512_MM_PERMUTATION 0-1 0 ; start_reg\n %if ARCH_X86_64 && cpuflag(avx512)\n %assign %%i %1\n %rep 16-%1\n %assign %%i_high %%i+16\n SWAP %%i, %%i_high\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro INIT_MMX 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_MMX %1\n %define mmsize 8\n %define mova movq\n %define movu movq\n %define movh movd\n %define movnta movntq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS mm\n%endmacro\n\n%macro INIT_XMM 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_XMM %1\n %define mmsize 16\n %define mova movdqa\n %define movu movdqu\n %define movh movq\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS xmm\n %if WIN64\n AVX512_MM_PERMUTATION 6 ; Swap callee-saved registers with volatile registers\n %endif\n%endmacro\n\n%macro INIT_YMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_YMM %1\n %define mmsize 32\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS ymm\n AVX512_MM_PERMUTATION\n%endmacro\n\n%macro INIT_ZMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_ZMM %1\n %define mmsize 64\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS zmm\n AVX512_MM_PERMUTATION\n%endmacro\n\nINIT_XMM\n\n%macro DECLARE_MMCAST 1\n %define mmmm%1 mm%1\n %define mmxmm%1 mm%1\n %define mmymm%1 mm%1\n %define mmzmm%1 mm%1\n %define xmmmm%1 mm%1\n %define xmmxmm%1 xmm%1\n %define xmmymm%1 xmm%1\n %define xmmzmm%1 xmm%1\n %define ymmmm%1 mm%1\n %define ymmxmm%1 xmm%1\n %define ymmymm%1 ymm%1\n %define ymmzmm%1 ymm%1\n %define zmmmm%1 mm%1\n %define zmmxmm%1 xmm%1\n %define zmmymm%1 ymm%1\n %define zmmzmm%1 zmm%1\n %define xm%1 xmm %+ m%1\n %define ym%1 ymm %+ m%1\n %define zm%1 zmm %+ m%1\n%endmacro\n\n%assign i 0\n%rep 32\n DECLARE_MMCAST i\n %assign i i+1\n%endrep\n\n; I often want to use macros that permute their arguments. e.g. there's no\n; efficient way to implement butterfly or transpose or dct without swapping some\n; arguments.\n;\n; I would like to not have to manually keep track of the permutations:\n; If I insert a permutation in the middle of a function, it should automatically\n; change everything that follows. For more complex macros I may also have multiple\n; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.\n;\n; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that\n; permutes its arguments. It's equivalent to exchanging the contents of the\n; registers, except that this way you exchange the register names instead, so it\n; doesn't cost any cycles.\n\n%macro PERMUTE 2-* ; takes a list of pairs to swap\n %rep %0/2\n %xdefine %%tmp%2 m%2\n %rotate 2\n %endrep\n %rep %0/2\n %xdefine m%1 %%tmp%2\n CAT_XDEFINE nn, m%1, %1\n %rotate 2\n %endrep\n%endmacro\n\n%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)\n %ifnum %1 ; SWAP 0, 1, ...\n SWAP_INTERNAL_NUM %1, %2\n %else ; SWAP m0, m1, ...\n SWAP_INTERNAL_NAME %1, %2\n %endif\n%endmacro\n\n%macro SWAP_INTERNAL_NUM 2-*\n %rep %0-1\n %xdefine %%tmp m%1\n %xdefine m%1 m%2\n %xdefine m%2 %%tmp\n CAT_XDEFINE nn, m%1, %1\n CAT_XDEFINE nn, m%2, %2\n %rotate 1\n %endrep\n%endmacro\n\n%macro SWAP_INTERNAL_NAME 2-*\n %xdefine %%args nn %+ %1\n %rep %0-1\n %xdefine %%args %%args, nn %+ %2\n %rotate 1\n %endrep\n SWAP_INTERNAL_NUM %%args\n%endmacro\n\n; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later\n; calls to that function will automatically load the permutation, so values can\n; be returned in mmregs.\n%macro SAVE_MM_PERMUTATION 0-1\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp m %+ %%i\n CAT_XDEFINE %%f, %%i, regnumof %+ %%tmp\n %assign %%i %%i+1\n %endrep\n%endmacro\n\n%macro LOAD_MM_PERMUTATION 0-1 ; name to load from\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %xdefine %%tmp %%f %+ 0\n %ifnum %%tmp\n RESET_MM_PERMUTATION\n AVX512_MM_PERMUTATION\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp %%f %+ %%i\n CAT_XDEFINE %%m, %%i, m %+ %%tmp\n %assign %%i %%i+1\n %endrep\n %rep num_mmregs\n %assign %%i %%i-1\n CAT_XDEFINE m, %%i, %%m %+ %%i\n CAT_XDEFINE nn, m %+ %%i, %%i\n %endrep\n %endif\n%endmacro\n\n; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't\n%macro call 1\n %ifid %1\n call_internal %1 %+ SUFFIX, %1\n %else\n call %1\n %endif\n%endmacro\n%macro call_internal 2\n %xdefine %%i %2\n %ifndef cglobaled_%2\n %ifdef cglobaled_%1\n %xdefine %%i %1\n %endif\n %endif\n call %%i\n LOAD_MM_PERMUTATION %%i\n%endmacro\n\n; Substitutions that reduce instruction size but are functionally equivalent\n%macro add 2\n %ifnum %2\n %if %2==128\n sub %1, -128\n %else\n add %1, %2\n %endif\n %else\n add %1, %2\n %endif\n%endmacro\n\n%macro sub 2\n %ifnum %2\n %if %2==128\n add %1, -128\n %else\n sub %1, %2\n %endif\n %else\n sub %1, %2\n %endif\n%endmacro\n\n;=============================================================================\n; AVX abstraction layer\n;=============================================================================\n\n%assign i 0\n%rep 32\n %if i < 8\n CAT_XDEFINE sizeofmm, i, 8\n CAT_XDEFINE regnumofmm, i, i\n %endif\n CAT_XDEFINE sizeofxmm, i, 16\n CAT_XDEFINE sizeofymm, i, 32\n CAT_XDEFINE sizeofzmm, i, 64\n CAT_XDEFINE regnumofxmm, i, i\n CAT_XDEFINE regnumofymm, i, i\n CAT_XDEFINE regnumofzmm, i, i\n %assign i i+1\n%endrep\n%undef i\n\n%macro CHECK_AVX_INSTR_EMU 3-*\n %xdefine %%opcode %1\n %xdefine %%dst %2\n %rep %0-2\n %ifidn %%dst, %3\n %error non-avx emulation of ``%%opcode'' is not supported\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n;%6+: operands\n%macro RUN_AVX_INSTR 6-9+\n %ifnum sizeof%7\n %assign __sizeofreg sizeof%7\n %elifnum sizeof%6\n %assign __sizeofreg sizeof%6\n %else\n %assign __sizeofreg mmsize\n %endif\n %assign __emulate_avx 0\n %if avx_enabled && __sizeofreg >= 16\n %xdefine __instr v%1\n %else\n %xdefine __instr %1\n %if %0 >= 8+%4\n %assign __emulate_avx 1\n %endif\n %endif\n %ifnidn %2, fnord\n %ifdef cpuname\n %if notcpuflag(%2)\n %error use of ``%1'' %2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 16 && notcpuflag(sse2)\n %error use of ``%1'' sse2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 32 && notcpuflag(avx2)\n %error use of ``%1'' avx2 instruction in cpuname function: current_function\n %elifidn %1, pextrw ; special case because the base instruction is mmx2,\n %ifnid %6 ; but sse4 is required for memory operands\n %if notcpuflag(sse4)\n %error use of ``%1'' sse4 instruction in cpuname function: current_function\n %endif\n %endif\n %endif\n %endif\n %endif\n\n %if __emulate_avx\n %xdefine __src1 %7\n %xdefine __src2 %8\n %if %5 && %4 == 0\n %ifnidn %6, %7\n %ifidn %6, %8\n %xdefine __src1 %8\n %xdefine __src2 %7\n %elifnnum sizeof%8\n ; 3-operand AVX instructions with a memory arg can only have it in src2,\n ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).\n ; So, if the instruction is commutative with a memory arg, swap them.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n %ifnidn %6, __src1\n %if %0 >= 9\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, __src2, %9\n %else\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, __src2\n %endif\n %if __sizeofreg == 8\n MOVQ %6, __src1\n %elif %3\n MOVAPS %6, __src1\n %else\n MOVDQA %6, __src1\n %endif\n %endif\n %if %0 >= 9\n %1 %6, __src2, %9\n %else\n %1 %6, __src2\n %endif\n %elif %0 >= 9\n __instr %6, %7, %8, %9\n %elif %0 == 8\n %if avx_enabled && %5\n %xdefine __src1 %7\n %xdefine __src2 %8\n %ifnum regnumof%7\n %ifnum regnumof%8\n %if regnumof%7 < 8 && regnumof%8 >= 8 && regnumof%8 < 16 && sizeof%8 <= 32\n ; Most VEX-encoded instructions require an additional byte to encode when\n ; src2 is a high register (e.g. m8..15). If the instruction is commutative\n ; we can swap src1 and src2 when doing so reduces the instruction length.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7, %8\n %endif\n %elif %0 == 7\n %if avx_enabled && %5\n %xdefine __src1 %6\n %xdefine __src2 %7\n %ifnum regnumof%6\n %ifnum regnumof%7\n %if regnumof%6 < 8 && regnumof%7 >= 8 && regnumof%7 < 16 && sizeof%7 <= 32\n %xdefine __src1 %7\n %xdefine __src2 %6\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7\n %endif\n %else\n __instr %6\n %endif\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n%macro AVX_INSTR 1-5 fnord, 0, 255, 0\n %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5\n %ifidn %2, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1\n %elifidn %3, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2\n %elifidn %4, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3\n %elifidn %5, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4\n %else\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5\n %endif\n %endmacro\n%endmacro\n\n; Instructions with both VEX/EVEX and legacy encodings\n; Non-destructive instructions are written without parameters\nAVX_INSTR addpd, sse2, 1, 0, 1\nAVX_INSTR addps, sse, 1, 0, 1\nAVX_INSTR addsd, sse2, 1, 0, 0\nAVX_INSTR addss, sse, 1, 0, 0\nAVX_INSTR addsubpd, sse3, 1, 0, 0\nAVX_INSTR addsubps, sse3, 1, 0, 0\nAVX_INSTR aesdec, aesni, 0, 0, 0\nAVX_INSTR aesdeclast, aesni, 0, 0, 0\nAVX_INSTR aesenc, aesni, 0, 0, 0\nAVX_INSTR aesenclast, aesni, 0, 0, 0\nAVX_INSTR aesimc, aesni\nAVX_INSTR aeskeygenassist, aesni\nAVX_INSTR andnpd, sse2, 1, 0, 0\nAVX_INSTR andnps, sse, 1, 0, 0\nAVX_INSTR andpd, sse2, 1, 0, 1\nAVX_INSTR andps, sse, 1, 0, 1\nAVX_INSTR blendpd, sse4, 1, 1, 0\nAVX_INSTR blendps, sse4, 1, 1, 0\nAVX_INSTR blendvpd, sse4 ; can't be emulated\nAVX_INSTR blendvps, sse4 ; can't be emulated\nAVX_INSTR cmpeqpd, sse2, 1, 0, 1\nAVX_INSTR cmpeqps, sse, 1, 0, 1\nAVX_INSTR cmpeqsd, sse2, 1, 0, 0\nAVX_INSTR cmpeqss, sse, 1, 0, 0\nAVX_INSTR cmplepd, sse2, 1, 0, 0\nAVX_INSTR cmpleps, sse, 1, 0, 0\nAVX_INSTR cmplesd, sse2, 1, 0, 0\nAVX_INSTR cmpless, sse, 1, 0, 0\nAVX_INSTR cmpltpd, sse2, 1, 0, 0\nAVX_INSTR cmpltps, sse, 1, 0, 0\nAVX_INSTR cmpltsd, sse2, 1, 0, 0\nAVX_INSTR cmpltss, sse, 1, 0, 0\nAVX_INSTR cmpneqpd, sse2, 1, 0, 1\nAVX_INSTR cmpneqps, sse, 1, 0, 1\nAVX_INSTR cmpneqsd, sse2, 1, 0, 0\nAVX_INSTR cmpneqss, sse, 1, 0, 0\nAVX_INSTR cmpnlepd, sse2, 1, 0, 0\nAVX_INSTR cmpnleps, sse, 1, 0, 0\nAVX_INSTR cmpnlesd, sse2, 1, 0, 0\nAVX_INSTR cmpnless, sse, 1, 0, 0\nAVX_INSTR cmpnltpd, sse2, 1, 0, 0\nAVX_INSTR cmpnltps, sse, 1, 0, 0\nAVX_INSTR cmpnltsd, sse2, 1, 0, 0\nAVX_INSTR cmpnltss, sse, 1, 0, 0\nAVX_INSTR cmpordpd, sse2 1, 0, 1\nAVX_INSTR cmpordps, sse 1, 0, 1\nAVX_INSTR cmpordsd, sse2 1, 0, 0\nAVX_INSTR cmpordss, sse 1, 0, 0\nAVX_INSTR cmppd, sse2, 1, 1, 0\nAVX_INSTR cmpps, sse, 1, 1, 0\nAVX_INSTR cmpsd, sse2, 1, 1, 0\nAVX_INSTR cmpss, sse, 1, 1, 0\nAVX_INSTR cmpunordpd, sse2, 1, 0, 1\nAVX_INSTR cmpunordps, sse, 1, 0, 1\nAVX_INSTR cmpunordsd, sse2, 1, 0, 0\nAVX_INSTR cmpunordss, sse, 1, 0, 0\nAVX_INSTR comisd, sse2, 1\nAVX_INSTR comiss, sse, 1\nAVX_INSTR cvtdq2pd, sse2, 1\nAVX_INSTR cvtdq2ps, sse2, 1\nAVX_INSTR cvtpd2dq, sse2, 1\nAVX_INSTR cvtpd2ps, sse2, 1\nAVX_INSTR cvtps2dq, sse2, 1\nAVX_INSTR cvtps2pd, sse2, 1\nAVX_INSTR cvtsd2si, sse2, 1\nAVX_INSTR cvtsd2ss, sse2, 1, 0, 0\nAVX_INSTR cvtsi2sd, sse2, 1, 0, 0\nAVX_INSTR cvtsi2ss, sse, 1, 0, 0\nAVX_INSTR cvtss2sd, sse2, 1, 0, 0\nAVX_INSTR cvtss2si, sse, 1\nAVX_INSTR cvttpd2dq, sse2, 1\nAVX_INSTR cvttps2dq, sse2, 1\nAVX_INSTR cvttsd2si, sse2, 1\nAVX_INSTR cvttss2si, sse, 1\nAVX_INSTR divpd, sse2, 1, 0, 0\nAVX_INSTR divps, sse, 1, 0, 0\nAVX_INSTR divsd, sse2, 1, 0, 0\nAVX_INSTR divss, sse, 1, 0, 0\nAVX_INSTR dppd, sse4, 1, 1, 0\nAVX_INSTR dpps, sse4, 1, 1, 0\nAVX_INSTR extractps, sse4, 1\nAVX_INSTR gf2p8affineinvqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8affineqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8mulb, gfni, 0, 0, 0\nAVX_INSTR haddpd, sse3, 1, 0, 0\nAVX_INSTR haddps, sse3, 1, 0, 0\nAVX_INSTR hsubpd, sse3, 1, 0, 0\nAVX_INSTR hsubps, sse3, 1, 0, 0\nAVX_INSTR insertps, sse4, 1, 1, 0\nAVX_INSTR lddqu, sse3\nAVX_INSTR ldmxcsr, sse, 1\nAVX_INSTR maskmovdqu, sse2\nAVX_INSTR maxpd, sse2, 1, 0, 1\nAVX_INSTR maxps, sse, 1, 0, 1\nAVX_INSTR maxsd, sse2, 1, 0, 0\nAVX_INSTR maxss, sse, 1, 0, 0\nAVX_INSTR minpd, sse2, 1, 0, 1\nAVX_INSTR minps, sse, 1, 0, 1\nAVX_INSTR minsd, sse2, 1, 0, 0\nAVX_INSTR minss, sse, 1, 0, 0\nAVX_INSTR movapd, sse2, 1\nAVX_INSTR movaps, sse, 1\nAVX_INSTR movd, mmx\nAVX_INSTR movddup, sse3, 1\nAVX_INSTR movdqa, sse2\nAVX_INSTR movdqu, sse2\nAVX_INSTR movhlps, sse, 1, 0, 0\nAVX_INSTR movhpd, sse2, 1, 0, 0\nAVX_INSTR movhps, sse, 1, 0, 0\nAVX_INSTR movlhps, sse, 1, 0, 0\nAVX_INSTR movlpd, sse2, 1, 0, 0\nAVX_INSTR movlps, sse, 1, 0, 0\nAVX_INSTR movmskpd, sse2, 1\nAVX_INSTR movmskps, sse, 1\nAVX_INSTR movntdq, sse2\nAVX_INSTR movntdqa, sse4\nAVX_INSTR movntpd, sse2, 1\nAVX_INSTR movntps, sse, 1\nAVX_INSTR movq, mmx\nAVX_INSTR movsd, sse2, 1, 0, 0\nAVX_INSTR movshdup, sse3, 1\nAVX_INSTR movsldup, sse3, 1\nAVX_INSTR movss, sse, 1, 0, 0\nAVX_INSTR movupd, sse2, 1\nAVX_INSTR movups, sse, 1\nAVX_INSTR mpsadbw, sse4, 0, 1, 0\nAVX_INSTR mulpd, sse2, 1, 0, 1\nAVX_INSTR mulps, sse, 1, 0, 1\nAVX_INSTR mulsd, sse2, 1, 0, 0\nAVX_INSTR mulss, sse, 1, 0, 0\nAVX_INSTR orpd, sse2, 1, 0, 1\nAVX_INSTR orps, sse, 1, 0, 1\nAVX_INSTR pabsb, ssse3\nAVX_INSTR pabsd, ssse3\nAVX_INSTR pabsw, ssse3\nAVX_INSTR packsswb, mmx, 0, 0, 0\nAVX_INSTR packssdw, mmx, 0, 0, 0\nAVX_INSTR packuswb, mmx, 0, 0, 0\nAVX_INSTR packusdw, sse4, 0, 0, 0\nAVX_INSTR paddb, mmx, 0, 0, 1\nAVX_INSTR paddw, mmx, 0, 0, 1\nAVX_INSTR paddd, mmx, 0, 0, 1\nAVX_INSTR paddq, sse2, 0, 0, 1\nAVX_INSTR paddsb, mmx, 0, 0, 1\nAVX_INSTR paddsw, mmx, 0, 0, 1\nAVX_INSTR paddusb, mmx, 0, 0, 1\nAVX_INSTR paddusw, mmx, 0, 0, 1\nAVX_INSTR palignr, ssse3, 0, 1, 0\nAVX_INSTR pand, mmx, 0, 0, 1\nAVX_INSTR pandn, mmx, 0, 0, 0\nAVX_INSTR pavgb, mmx2, 0, 0, 1\nAVX_INSTR pavgw, mmx2, 0, 0, 1\nAVX_INSTR pblendvb, sse4 ; can't be emulated\nAVX_INSTR pblendw, sse4, 0, 1, 0\nAVX_INSTR pclmulqdq, fnord, 0, 1, 0\nAVX_INSTR pclmulhqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmulhqlqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqlqdq, fnord, 0, 0, 0\nAVX_INSTR pcmpestri, sse42\nAVX_INSTR pcmpestrm, sse42\nAVX_INSTR pcmpistri, sse42\nAVX_INSTR pcmpistrm, sse42\nAVX_INSTR pcmpeqb, mmx, 0, 0, 1\nAVX_INSTR pcmpeqw, mmx, 0, 0, 1\nAVX_INSTR pcmpeqd, mmx, 0, 0, 1\nAVX_INSTR pcmpeqq, sse4, 0, 0, 1\nAVX_INSTR pcmpgtb, mmx, 0, 0, 0\nAVX_INSTR pcmpgtw, mmx, 0, 0, 0\nAVX_INSTR pcmpgtd, mmx, 0, 0, 0\nAVX_INSTR pcmpgtq, sse42, 0, 0, 0\nAVX_INSTR pextrb, sse4\nAVX_INSTR pextrd, sse4\nAVX_INSTR pextrq, sse4\nAVX_INSTR pextrw, mmx2\nAVX_INSTR phaddw, ssse3, 0, 0, 0\nAVX_INSTR phaddd, ssse3, 0, 0, 0\nAVX_INSTR phaddsw, ssse3, 0, 0, 0\nAVX_INSTR phminposuw, sse4\nAVX_INSTR phsubw, ssse3, 0, 0, 0\nAVX_INSTR phsubd, ssse3, 0, 0, 0\nAVX_INSTR phsubsw, ssse3, 0, 0, 0\nAVX_INSTR pinsrb, sse4, 0, 1, 0\nAVX_INSTR pinsrd, sse4, 0, 1, 0\nAVX_INSTR pinsrq, sse4, 0, 1, 0\nAVX_INSTR pinsrw, mmx2, 0, 1, 0\nAVX_INSTR pmaddwd, mmx, 0, 0, 1\nAVX_INSTR pmaddubsw, ssse3, 0, 0, 0\nAVX_INSTR pmaxsb, sse4, 0, 0, 1\nAVX_INSTR pmaxsw, mmx2, 0, 0, 1\nAVX_INSTR pmaxsd, sse4, 0, 0, 1\nAVX_INSTR pmaxub, mmx2, 0, 0, 1\nAVX_INSTR pmaxuw, sse4, 0, 0, 1\nAVX_INSTR pmaxud, sse4, 0, 0, 1\nAVX_INSTR pminsb, sse4, 0, 0, 1\nAVX_INSTR pminsw, mmx2, 0, 0, 1\nAVX_INSTR pminsd, sse4, 0, 0, 1\nAVX_INSTR pminub, mmx2, 0, 0, 1\nAVX_INSTR pminuw, sse4, 0, 0, 1\nAVX_INSTR pminud, sse4, 0, 0, 1\nAVX_INSTR pmovmskb, mmx2\nAVX_INSTR pmovsxbw, sse4\nAVX_INSTR pmovsxbd, sse4\nAVX_INSTR pmovsxbq, sse4\nAVX_INSTR pmovsxwd, sse4\nAVX_INSTR pmovsxwq, sse4\nAVX_INSTR pmovsxdq, sse4\nAVX_INSTR pmovzxbw, sse4\nAVX_INSTR pmovzxbd, sse4\nAVX_INSTR pmovzxbq, sse4\nAVX_INSTR pmovzxwd, sse4\nAVX_INSTR pmovzxwq, sse4\nAVX_INSTR pmovzxdq, sse4\nAVX_INSTR pmuldq, sse4, 0, 0, 1\nAVX_INSTR pmulhrsw, ssse3, 0, 0, 1\nAVX_INSTR pmulhuw, mmx2, 0, 0, 1\nAVX_INSTR pmulhw, mmx, 0, 0, 1\nAVX_INSTR pmullw, mmx, 0, 0, 1\nAVX_INSTR pmulld, sse4, 0, 0, 1\nAVX_INSTR pmuludq, sse2, 0, 0, 1\nAVX_INSTR por, mmx, 0, 0, 1\nAVX_INSTR psadbw, mmx2, 0, 0, 1\nAVX_INSTR pshufb, ssse3, 0, 0, 0\nAVX_INSTR pshufd, sse2\nAVX_INSTR pshufhw, sse2\nAVX_INSTR pshuflw, sse2\nAVX_INSTR psignb, ssse3, 0, 0, 0\nAVX_INSTR psignw, ssse3, 0, 0, 0\nAVX_INSTR psignd, ssse3, 0, 0, 0\nAVX_INSTR psllw, mmx, 0, 0, 0\nAVX_INSTR pslld, mmx, 0, 0, 0\nAVX_INSTR psllq, mmx, 0, 0, 0\nAVX_INSTR pslldq, sse2, 0, 0, 0\nAVX_INSTR psraw, mmx, 0, 0, 0\nAVX_INSTR psrad, mmx, 0, 0, 0\nAVX_INSTR psrlw, mmx, 0, 0, 0\nAVX_INSTR psrld, mmx, 0, 0, 0\nAVX_INSTR psrlq, mmx, 0, 0, 0\nAVX_INSTR psrldq, sse2, 0, 0, 0\nAVX_INSTR psubb, mmx, 0, 0, 0\nAVX_INSTR psubw, mmx, 0, 0, 0\nAVX_INSTR psubd, mmx, 0, 0, 0\nAVX_INSTR psubq, sse2, 0, 0, 0\nAVX_INSTR psubsb, mmx, 0, 0, 0\nAVX_INSTR psubsw, mmx, 0, 0, 0\nAVX_INSTR psubusb, mmx, 0, 0, 0\nAVX_INSTR psubusw, mmx, 0, 0, 0\nAVX_INSTR ptest, sse4\nAVX_INSTR punpckhbw, mmx, 0, 0, 0\nAVX_INSTR punpckhwd, mmx, 0, 0, 0\nAVX_INSTR punpckhdq, mmx, 0, 0, 0\nAVX_INSTR punpckhqdq, sse2, 0, 0, 0\nAVX_INSTR punpcklbw, mmx, 0, 0, 0\nAVX_INSTR punpcklwd, mmx, 0, 0, 0\nAVX_INSTR punpckldq, mmx, 0, 0, 0\nAVX_INSTR punpcklqdq, sse2, 0, 0, 0\nAVX_INSTR pxor, mmx, 0, 0, 1\nAVX_INSTR rcpps, sse, 1\nAVX_INSTR rcpss, sse, 1, 0, 0\nAVX_INSTR roundpd, sse4, 1\nAVX_INSTR roundps, sse4, 1\nAVX_INSTR roundsd, sse4, 1, 1, 0\nAVX_INSTR roundss, sse4, 1, 1, 0\nAVX_INSTR rsqrtps, sse, 1\nAVX_INSTR rsqrtss, sse, 1, 0, 0\nAVX_INSTR shufpd, sse2, 1, 1, 0\nAVX_INSTR shufps, sse, 1, 1, 0\nAVX_INSTR sqrtpd, sse2, 1\nAVX_INSTR sqrtps, sse, 1\nAVX_INSTR sqrtsd, sse2, 1, 0, 0\nAVX_INSTR sqrtss, sse, 1, 0, 0\nAVX_INSTR stmxcsr, sse, 1\nAVX_INSTR subpd, sse2, 1, 0, 0\nAVX_INSTR subps, sse, 1, 0, 0\nAVX_INSTR subsd, sse2, 1, 0, 0\nAVX_INSTR subss, sse, 1, 0, 0\nAVX_INSTR ucomisd, sse2, 1\nAVX_INSTR ucomiss, sse, 1\nAVX_INSTR unpckhpd, sse2, 1, 0, 0\nAVX_INSTR unpckhps, sse, 1, 0, 0\nAVX_INSTR unpcklpd, sse2, 1, 0, 0\nAVX_INSTR unpcklps, sse, 1, 0, 0\nAVX_INSTR xorpd, sse2, 1, 0, 1\nAVX_INSTR xorps, sse, 1, 0, 1\n\n; 3DNow instructions, for sharing code between AVX, SSE and 3DN\nAVX_INSTR pfadd, 3dnow, 1, 0, 1\nAVX_INSTR pfsub, 3dnow, 1, 0, 0\nAVX_INSTR pfmul, 3dnow, 1, 0, 1\n\n;%1 == instruction\n;%2 == minimal instruction set\n%macro GPR_INSTR 2\n %macro %1 2-5 fnord, %1, %2\n %ifdef cpuname\n %if notcpuflag(%5)\n %error use of ``%4'' %5 instruction in cpuname function: current_function\n %endif\n %endif\n %ifidn %3, fnord\n %4 %1, %2\n %else\n %4 %1, %2, %3\n %endif\n %endmacro\n%endmacro\n\nGPR_INSTR andn, bmi1\nGPR_INSTR bextr, bmi1\nGPR_INSTR blsi, bmi1\nGPR_INSTR blsmsk, bmi1\nGPR_INSTR bzhi, bmi2\nGPR_INSTR mulx, bmi2\nGPR_INSTR pdep, bmi2\nGPR_INSTR pext, bmi2\nGPR_INSTR popcnt, sse42\nGPR_INSTR rorx, bmi2\nGPR_INSTR sarx, bmi2\nGPR_INSTR shlx, bmi2\nGPR_INSTR shrx, bmi2\n\n; base-4 constants for shuffles\n%assign i 0\n%rep 256\n %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)\n %if j < 10\n CAT_XDEFINE q000, j, i\n %elif j < 100\n CAT_XDEFINE q00, j, i\n %elif j < 1000\n CAT_XDEFINE q0, j, i\n %else\n CAT_XDEFINE q, j, i\n %endif\n %assign i i+1\n%endrep\n%undef i\n%undef j\n\n%macro FMA_INSTR 3\n %macro %1 4-7 %1, %2, %3\n %if cpuflag(xop)\n v%5 %1, %2, %3, %4\n %elifnidn %1, %4\n %6 %1, %2, %3\n %7 %1, %4\n %else\n %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n%endmacro\n\nFMA_INSTR pmacsww, pmullw, paddw\nFMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation\nFMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation\nFMA_INSTR pmadcswd, pmaddwd, paddd\n\n; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.\n; FMA3 is only possible if dst is the same as one of the src registers.\n; Either src2 or src3 can be a memory operand.\n%macro FMA4_INSTR 2-*\n %push fma4_instr\n %xdefine %$prefix %1\n %rep %0 - 1\n %macro %$prefix%2 4-6 %$prefix, %2\n %if notcpuflag(fma3) && notcpuflag(fma4)\n %error use of ``%5%6'' fma instruction in cpuname function: current_function\n %elif cpuflag(fma4)\n v%5%6 %1, %2, %3, %4\n %elifidn %1, %2\n ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.\n %ifnum sizeof%3\n v%{5}213%6 %2, %3, %4\n %else\n v%{5}132%6 %2, %4, %3\n %endif\n %elifidn %1, %3\n v%{5}213%6 %3, %2, %4\n %elifidn %1, %4\n v%{5}231%6 %4, %2, %3\n %else\n %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n %rotate 1\n %endrep\n %pop\n%endmacro\n\nFMA4_INSTR fmadd, pd, ps, sd, ss\nFMA4_INSTR fmaddsub, pd, ps\nFMA4_INSTR fmsub, pd, ps, sd, ss\nFMA4_INSTR fmsubadd, pd, ps\nFMA4_INSTR fnmadd, pd, ps, sd, ss\nFMA4_INSTR fnmsub, pd, ps, sd, ss\n\n; Macros for converting VEX instructions to equivalent EVEX ones.\n%macro EVEX_INSTR 2-3 0 ; vex, evex, prefer_evex\n %macro %1 2-7 fnord, fnord, %1, %2, %3\n %ifidn %3, fnord\n %define %%args %1, %2\n %elifidn %4, fnord\n %define %%args %1, %2, %3\n %else\n %define %%args %1, %2, %3, %4\n %endif\n %assign %%evex_required cpuflag(avx512) & %7\n %ifnum regnumof%1\n %if regnumof%1 >= 16 || sizeof%1 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%2\n %if regnumof%2 >= 16 || sizeof%2 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%3\n %if regnumof%3 >= 16 || sizeof%3 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %if %%evex_required\n %6 %%args\n %else\n %5 %%args ; Prefer VEX over EVEX due to shorter instruction length\n %endif\n %endmacro\n%endmacro\n\nEVEX_INSTR vbroadcastf128, vbroadcastf32x4\nEVEX_INSTR vbroadcasti128, vbroadcasti32x4\nEVEX_INSTR vextractf128, vextractf32x4\nEVEX_INSTR vextracti128, vextracti32x4\nEVEX_INSTR vinsertf128, vinsertf32x4\nEVEX_INSTR vinserti128, vinserti32x4\nEVEX_INSTR vmovdqa, vmovdqa32\nEVEX_INSTR vmovdqu, vmovdqu32\nEVEX_INSTR vpand, vpandd\nEVEX_INSTR vpandn, vpandnd\nEVEX_INSTR vpor, vpord\nEVEX_INSTR vpxor, vpxord\nEVEX_INSTR vrcpps, vrcp14ps, 1 ; EVEX versions have higher precision\nEVEX_INSTR vrcpss, vrcp14ss, 1\nEVEX_INSTR vrsqrtps, vrsqrt14ps, 1\nEVEX_INSTR vrsqrtss, vrsqrt14ss, 1\n"}}},{"rowIdx":481,"cells":{"commit":{"kind":"string","value":"729b09fc80014f963adfe4b57459c95d16359494"},"subject":{"kind":"string","value":"x86: add prep_bilin AVX512 asm"},"message":{"kind":"string","value":"x86: add prep_bilin AVX512 asm\n\n------------------------------------------\nmct_bilinear_w4_0_8bpc_avx2: 3.8\nmct_bilinear_w4_0_8bpc_avx512icl: 3.7\n---------------------\nmct_bilinear_w8_0_8bpc_avx2: 5.0\nmct_bilinear_w8_0_8bpc_avx512icl: 4.8\n---------------------\nmct_bilinear_w16_0_8bpc_avx2: 8.5\nmct_bilinear_w16_0_8bpc_avx512icl: 7.1\n---------------------\nmct_bilinear_w32_0_8bpc_avx2: 29.5\nmct_bilinear_w32_0_8bpc_avx512icl: 17.1\n---------------------\nmct_bilinear_w64_0_8bpc_avx2: 68.1\nmct_bilinear_w64_0_8bpc_avx512icl: 34.7\n---------------------\nmct_bilinear_w128_0_8bpc_avx2: 180.5\nmct_bilinear_w128_0_8bpc_avx512icl: 138.0\n------------------------------------------\nmct_bilinear_w4_h_8bpc_avx2: 4.0\nmct_bilinear_w4_h_8bpc_avx512icl: 3.9\n---------------------\nmct_bilinear_w8_h_8bpc_avx2: 5.3\nmct_bilinear_w8_h_8bpc_avx512icl: 5.0\n---------------------\nmct_bilinear_w16_h_8bpc_avx2: 11.7\nmct_bilinear_w16_h_8bpc_avx512icl: 7.5\n---------------------\nmct_bilinear_w32_h_8bpc_avx2: 41.8\nmct_bilinear_w32_h_8bpc_avx512icl: 20.3\n---------------------\nmct_bilinear_w64_h_8bpc_avx2: 94.9\nmct_bilinear_w64_h_8bpc_avx512icl: 35.0\n---------------------\nmct_bilinear_w128_h_8bpc_avx2: 240.1\nmct_bilinear_w128_h_8bpc_avx512icl: 143.8\n------------------------------------------\nmct_bilinear_w4_v_8bpc_avx2: 4.1\nmct_bilinear_w4_v_8bpc_avx512icl: 4.0\n---------------------\nmct_bilinear_w8_v_8bpc_avx2: 6.0\nmct_bilinear_w8_v_8bpc_avx512icl: 5.4\n---------------------\nmct_bilinear_w16_v_8bpc_avx2: 10.3\nmct_bilinear_w16_v_8bpc_avx512icl: 8.9\n---------------------\nmct_bilinear_w32_v_8bpc_avx2: 29.5\nmct_bilinear_w32_v_8bpc_avx512icl: 25.9\n---------------------\nmct_bilinear_w64_v_8bpc_avx2: 64.3\nmct_bilinear_w64_v_8bpc_avx512icl: 41.3\n---------------------\nmct_bilinear_w128_v_8bpc_avx2: 198.2\nmct_bilinear_w128_v_8bpc_avx512icl: 139.6\n------------------------------------------\nmct_bilinear_w4_hv_8bpc_avx2: 5.6\nmct_bilinear_w4_hv_8bpc_avx512icl: 5.2\n---------------------\nmct_bilinear_w8_hv_8bpc_avx2: 8.3\nmct_bilinear_w8_hv_8bpc_avx512icl: 7.0\n---------------------\nmct_bilinear_w16_hv_8bpc_avx2: 19.4\nmct_bilinear_w16_hv_8bpc_avx512icl: 12.1\n---------------------\nmct_bilinear_w32_hv_8bpc_avx2: 69.1\nmct_bilinear_w32_hv_8bpc_avx512icl: 32.5\n---------------------\nmct_bilinear_w64_hv_8bpc_avx2: 164.4\nmct_bilinear_w64_hv_8bpc_avx512icl: 71.1\n---------------------\nmct_bilinear_w128_hv_8bpc_avx2: 405.2\nmct_bilinear_w128_hv_8bpc_avx512icl: 193.1\n------------------------------------------\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/mc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\ncextern mc_warp_filter\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n mov hb, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n mov hb, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n mov hb, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n mov hb, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\nINIT_ZMM avx512icl\nPREP_BILIN\n\nINIT_YMM avx2\nPREP_BILIN\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%if WIN64\nDECLARE_REG_TMP 6, 4\n%else\nDECLARE_REG_TMP 6, 7\n%endif\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vbroadcasti128 m5, [subpel_h_shufA]\n vpbroadcastd m4, [pw_8192]\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep_avx2+4]\n add wq, r7\n jmp wq\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m3, [r7+mxq*8+subpel_filters-prep_avx2+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n phaddw m0, m1\n pmulhrsw m0, m4\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PREP_8TAP_H 0\n pshufb m1, m0, m6\n pshufb m2, m0, m7\n pshufb m0, m5\n pmaddubsw m3, m1, m8\n pmaddubsw m1, m9\n pmaddubsw m2, m9\n pmaddubsw m0, m8\n paddw m2, m3\n paddw m0, m1\n phaddw m0, m2\n pmulhrsw m0, m4\n%endmacro\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n mov r5, r6\n.h_loop:\n movu xm0, [srcq+r6+8*0]\n vinserti128 m0, m0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 m0, m0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n add r6, 32\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n vpbroadcastd m7, [pw_8192]\n lea myq, [r7+myq*8+subpel_filters-prep_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n cmp wd, 8\n jg .v_w16\n je .v_w8\n.v_w4:\n movd xm0, [srcq+strideq*0]\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd m3, m3, m2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd m0, [srcq+strideq*0]\n vpbroadcastd m2, [srcq+strideq*1]\n vpblendd m1, m1, m0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd m0, [srcq+strideq*2]\n vbroadcasti128 m6, [deint_shuf4]\n vpblendd m3, m3, m2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd m2, m3, m1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd m3, m3, m1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw m1, m2, m3 ; 01 12 23 34\n vpblendd m3, m3, m0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw m2, m3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd m3, [srcq+strideq*0]\n vpbroadcastd m4, [srcq+strideq*1]\n vpblendd m3, m3, m4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd m3, m3, m0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd m0, [srcq+strideq*2]\n vpblendd m3, m3, m0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb m3, m6 ; 67 78 89 9a\n pmaddubsw m4, m1, m8\n vperm2i128 m1, m2, m3, 0x21 ; 45 56 67 78\n pmaddubsw m2, m9\n paddw m4, m2\n mova m2, m3\n pmaddubsw m3, m11\n paddw m3, m4\n pmaddubsw m4, m1, m10\n paddw m3, m4\n pmulhrsw m3, m7\n mova [tmpq], m3\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n mova m7, [subpel_h_shuf4]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+2]\n pmovzxbd m9, [deint_shuf4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m10, [pw_8192]\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7\n pshufb m0, m7\n pshufb m3, m7\n pshufb m1, m7\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro BIDIR_FN 1 ; op\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [pw_1024+r6-avg_avx2_table]\n add wq, r6\n BIDIR_FN AVG\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [w_avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [pw_2048+r6-w_avg_avx2_table]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n vpermq m3, [maskq+(%1+0)*(mmsize/2)], q3120\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n lea r7, [mask_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n vpbroadcastd m5, [pw_2048+r7-mask_avx2_table]\n add wq, r7\n BIDIR_FN MASK\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovl r10, yq\n test yq, yq\n cmovl r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovl r10, xq\n test xq, xq\n cmovl r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovl bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovl topextq, r12\n cmp bottomextq, bhq\n cmovge bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovl rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovl leftextq, r12\n cmp rightextq, bwq\n cmovge rightextq, r2\n cmp leftextq, bwq\n cmovge leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 32\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\ncextern mc_warp_filter\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n mov hb, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n psllw m0, 4\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n add tmpq, 32*4\n sub hd, 2\n jg .prep_w32\n RET\n.prep_w64:\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n add tmpq, 32*4\n dec hd\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n add tmpq, 32*8\n add srcq, strideq\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r6m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 m4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m0, m0, xm1, 1\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16\n RET\n.h_w32:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n add tmpq, 32*4\n sub hd, 2\n jg .h_w32\n RET\n.h_w64:\n movu xm0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n add tmpq, 32*4\n dec hd\n jg .h_w64\n RET\n.h_w128:\n movu xm0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n movu xm0, [srcq+8* 8]\n vinserti128 m0, m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, m3, [srcq+8*15], 1\n add tmpq, 32*8\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n dec hd\n jg .h_w128\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n jmp wq\n.v_w4:\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n pmaddubsw m2, m6\n mova [tmpq], m2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+strideq*0]\n.v_w8_loop:\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3\n shufpd m1, m1, m0, 0x0c ; 2 4\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq m1, [srcq+strideq*1], q3120\n vpermq m2, [srcq+strideq*2], q3120\n vpermq m3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n mov hb, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n movd xm6, mxyd\n add wq, t2\n lea stride3q, [strideq*3]\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w4:\n vbroadcasti128 m4, [bilin_h_shuf4]\n vpbroadcastq m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 m1, m1, xm2, 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n vpblendd m2, m1, m0, 0xc0\n vpermq m2, m2, q2103 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n add tmpq, 32*2\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*1], 1\n movu m1, [srcq+8*2]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n jg .hv_w32_loop\n RET\n.hv_w64:\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu m0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n mov hb, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n RET\n.hv_w128:\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu m0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n mov hb, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n RET\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%if WIN64\nDECLARE_REG_TMP 6, 4\n%else\nDECLARE_REG_TMP 6, 7\n%endif\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vbroadcasti128 m5, [subpel_h_shufA]\n vpbroadcastd m4, [pw_8192]\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep_avx2+4]\n add wq, r7\n jmp wq\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m3, [r7+mxq*8+subpel_filters-prep_avx2+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n phaddw m0, m1\n pmulhrsw m0, m4\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PREP_8TAP_H 0\n pshufb m1, m0, m6\n pshufb m2, m0, m7\n pshufb m0, m5\n pmaddubsw m3, m1, m8\n pmaddubsw m1, m9\n pmaddubsw m2, m9\n pmaddubsw m0, m8\n paddw m2, m3\n paddw m0, m1\n phaddw m0, m2\n pmulhrsw m0, m4\n%endmacro\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n mov r5, r6\n.h_loop:\n movu xm0, [srcq+r6+8*0]\n vinserti128 m0, m0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 m0, m0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n add r6, 32\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n vpbroadcastd m7, [pw_8192]\n lea myq, [r7+myq*8+subpel_filters-prep_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n cmp wd, 8\n jg .v_w16\n je .v_w8\n.v_w4:\n movd xm0, [srcq+strideq*0]\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd m3, m3, m2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd m0, [srcq+strideq*0]\n vpbroadcastd m2, [srcq+strideq*1]\n vpblendd m1, m1, m0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd m0, [srcq+strideq*2]\n vbroadcasti128 m6, [deint_shuf4]\n vpblendd m3, m3, m2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd m2, m3, m1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd m3, m3, m1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw m1, m2, m3 ; 01 12 23 34\n vpblendd m3, m3, m0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw m2, m3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd m3, [srcq+strideq*0]\n vpbroadcastd m4, [srcq+strideq*1]\n vpblendd m3, m3, m4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd m3, m3, m0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd m0, [srcq+strideq*2]\n vpblendd m3, m3, m0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb m3, m6 ; 67 78 89 9a\n pmaddubsw m4, m1, m8\n vperm2i128 m1, m2, m3, 0x21 ; 45 56 67 78\n pmaddubsw m2, m9\n paddw m4, m2\n mova m2, m3\n pmaddubsw m3, m11\n paddw m3, m4\n pmaddubsw m4, m1, m10\n paddw m3, m4\n pmulhrsw m3, m7\n mova [tmpq], m3\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n mova m7, [subpel_h_shuf4]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+2]\n pmovzxbd m9, [deint_shuf4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m10, [pw_8192]\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7\n pshufb m0, m7\n pshufb m3, m7\n pshufb m1, m7\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro BIDIR_FN 1 ; op\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [pw_1024+r6-avg_avx2_table]\n add wq, r6\n BIDIR_FN AVG\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [w_avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [pw_2048+r6-w_avg_avx2_table]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n vpermq m3, [maskq+(%1+0)*(mmsize/2)], q3120\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n lea r7, [mask_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n vpbroadcastd m5, [pw_2048+r7-mask_avx2_table]\n add wq, r7\n BIDIR_FN MASK\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovl r10, yq\n test yq, yq\n cmovl r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovl r10, xq\n test xq, xq\n cmovl r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovl bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovl topextq, r12\n cmp bottomextq, bhq\n cmovge bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovl rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovl leftextq, r12\n cmp rightextq, bwq\n cmovge rightextq, r2\n cmp leftextq, bwq\n cmovge leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":482,"cells":{"commit":{"kind":"string","value":"09186ea8a715b4e479a5f16b6d56c786aac3a78f"},"subject":{"kind":"string","value":"Simplify shifting in generate_grain_y/uv AVX2"},"message":{"kind":"string","value":"Simplify shifting in generate_grain_y/uv AVX2\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/film_grain.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2019, VideoLAN and dav1d authors\n; Copyright © 2019, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 32\npw_1024: times 16 dw 1024\npb_mask: db 0, 0x80, 0x80, 0, 0x80, 0, 0, 0x80, 0x80, 0, 0, 0x80, 0, 0x80, 0x80, 0\nrnd_next_upperbit_mask: dw 0x100B, 0x2016, 0x402C, 0x8058\nbyte_blend: db 0, 0, 0, 0xff, 0, 0, 0, 0\npw_seed_xor: times 2 dw 0xb524\n times 2 dw 0x49d8\npd_m65536: dd ~0xffff\npb_23_22: times 2 db 23, 22\npb_1: times 4 db 1\nhmul_bits: dw 32768, 16384, 8192, 4096\nround: dw 2048, 1024, 512\nmul_bits: dw 256, 128, 64, 32, 16\nround_vals: dw 32, 64, 128, 256, 512\nmax: dw 255, 240, 235\nmin: dw 0, 16\npb_27_17_17_27: db 27, 17, 17, 27\npw_1: dw 1\n\n%macro JMP_TABLE 1-*\n %xdefine %1_table %%table\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .ar%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nALIGN 4\nJMP_TABLE generate_grain_y_avx2, 0, 1, 2, 3\nJMP_TABLE generate_grain_uv_420_avx2, 0, 1, 2, 3\n\nstruc FGData\n .seed: resd 1\n .num_y_points: resd 1\n .y_points: resb 14 * 2\n .chroma_scaling_from_luma: resd 1\n .num_uv_points: resd 2\n .uv_points: resb 2 * 10 * 2\n .scaling_shift: resd 1\n .ar_coeff_lag: resd 1\n .ar_coeffs_y: resb 24\n .ar_coeffs_uv: resb 2 * 28 ; includes padding\n .ar_coeff_shift: resq 1\n .grain_scale_shift: resd 1\n .uv_mult: resd 2\n .uv_luma_mult: resd 2\n .uv_offset: resd 2\n .overlap_flag: resd 1\n .clip_to_restricted_range: resd 1\nendstruc\n\ncextern gaussian_sequence\n\nSECTION .text\n\nINIT_XMM avx2\ncglobal generate_grain_y, 2, 9, 16, buf, fg_data\n lea r4, [pb_mask]\n%define base r4-pb_mask\n movq xm1, [base+rnd_next_upperbit_mask]\n movq xm4, [base+mul_bits]\n movq xm7, [base+hmul_bits]\n mov r2d, [fg_dataq+FGData.grain_scale_shift]\n vpbroadcastw xm8, [base+round+r2*2]\n mova xm5, [base+pb_mask]\n vpbroadcastw xm0, [fg_dataq+FGData.seed]\n vpbroadcastd xm9, [base+pd_m65536]\n mov r2, -73*82\n sub bufq, r2\n lea r3, [gaussian_sequence]\n.loop:\n pand xm2, xm0, xm1\n psrlw xm3, xm2, 10\n por xm2, xm3 ; bits 0xf, 0x1e, 0x3c and 0x78 are set\n pmullw xm2, xm4 ; bits 0x0f00 are set\n pshufb xm2, xm5, xm2 ; set 15th bit for next 4 seeds\n psllq xm6, xm2, 30\n por xm2, xm6\n psllq xm6, xm2, 15\n por xm2, xm6 ; aggregate each bit into next seed's high bit\n pmulhuw xm3, xm0, xm7\n por xm2, xm3 ; 4 next output seeds\n pshuflw xm0, xm2, q3333\n psrlw xm2, 5\n pmovzxwd xm3, xm2\n mova xm6, xm9\n vpgatherdd xm2, [r3+xm3*2], xm6\n pandn xm2, xm9, xm2\n packusdw xm2, xm2\n pmulhrsw xm2, xm8\n packsswb xm2, xm2\n movd [bufq+r2], xm2\n add r2, 4\n jl .loop\n\n ; auto-regression code\n movsxd r2, [fg_dataq+FGData.ar_coeff_lag]\n movsxd r2, [base+generate_grain_y_avx2_table+r2*4]\n lea r2, [r2+base+generate_grain_y_avx2_table]\n jmp r2\n\n.ar1:\n DEFINE_ARGS buf, fg_data, cf3, shift, val3, min, max, x, val0\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movsx cf3d, byte [fg_dataq+FGData.ar_coeffs_y+3]\n movd xm4, [fg_dataq+FGData.ar_coeffs_y]\n DEFINE_ARGS buf, h, cf3, shift, val3, min, max, x, val0\n pinsrb xm4, [pb_1], 3\n pmovsxbw xm4, xm4\n pshufd xm5, xm4, q1111\n pshufd xm4, xm4, q0000\n vpbroadcastw xm3, [base+round_vals+shiftq*2-12] ; rnd\n sub bufq, 82*73-(82*3+79)\n mov hd, 70\n mov mind, -128\n mov maxd, 127\n.y_loop_ar1:\n mov xq, -76\n movsx val3d, byte [bufq+xq-1]\n.x_loop_ar1:\n pmovsxbw xm0, [bufq+xq-82-1] ; top/left\n pmovsxbw xm2, [bufq+xq-82+0] ; top\n pmovsxbw xm1, [bufq+xq-82+1] ; top/right\n punpcklwd xm0, xm2\n punpcklwd xm1, xm3\n pmaddwd xm0, xm4\n pmaddwd xm1, xm5\n paddd xm0, xm1\n.x_loop_ar1_inner:\n movd val0d, xm0\n psrldq xm0, 4\n imul val3d, cf3d\n add val3d, val0d\n%if WIN64\n sarx val3d, val3d, shiftd\n%else\n sar val3d, shiftb\n%endif\n movsx val0d, byte [bufq+xq]\n add val3d, val0d\n cmp val3d, maxd\n cmovg val3d, maxd\n cmp val3d, mind\n cmovl val3d, mind\n mov byte [bufq+xq], val3b\n ; keep val3d in-place as left for next x iteration\n inc xq\n jz .x_loop_ar1_end\n test xq, 3\n jnz .x_loop_ar1_inner\n jmp .x_loop_ar1\n\n.x_loop_ar1_end:\n add bufq, 82\n dec hd\n jg .y_loop_ar1\n.ar0:\n RET\n\n.ar2:\n DEFINE_ARGS buf, fg_data, shift\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n vpbroadcastw xm14, [base+round_vals-12+shiftq*2]\n movq xm15, [base+byte_blend+1]\n pmovsxbw xm8, [fg_dataq+FGData.ar_coeffs_y+0] ; cf0-7\n movd xm9, [fg_dataq+FGData.ar_coeffs_y+8] ; cf8-11\n pmovsxbw xm9, xm9\n DEFINE_ARGS buf, fg_data, h, x\n pshufd xm12, xm9, q0000\n pshufd xm13, xm9, q1111\n pshufd xm11, xm8, q3333\n pshufd xm10, xm8, q2222\n pshufd xm9, xm8, q1111\n pshufd xm8, xm8, q0000\n pmovzxwd xm14, xm14\n sub bufq, 82*73-(82*3+79)\n mov hd, 70\n.y_loop_ar2:\n mov xq, -76\n\n.x_loop_ar2:\n pmovsxbw xm0, [bufq+xq-82*2-2] ; y=-2,x=[-2,+5]\n pmovsxbw xm1, [bufq+xq-82*1-2] ; y=-1,x=[-2,+5]\n psrldq xm2, xm0, 2 ; y=-2,x=[-1,+5]\n psrldq xm3, xm1, 2 ; y=-1,x=[-1,+5]\n psrldq xm4, xm1, 4 ; y=-1,x=[+0,+5]\n punpcklwd xm2, xm0, xm2\n punpcklwd xm3, xm4\n pmaddwd xm2, xm8\n pmaddwd xm3, xm11\n paddd xm2, xm3\n\n psrldq xm4, xm0, 4 ; y=-2,x=[+0,+5]\n psrldq xm5, xm0, 6 ; y=-2,x=[+1,+5]\n psrldq xm6, xm0, 8 ; y=-2,x=[+2,+5]\n punpcklwd xm4, xm5\n punpcklwd xm6, xm1\n psrldq xm7, xm1, 6 ; y=-1,x=[+1,+5]\n psrldq xm1, xm1, 8 ; y=-1,x=[+2,+5]\n punpcklwd xm7, xm1\n pmaddwd xm4, xm9\n pmaddwd xm6, xm10\n pmaddwd xm7, xm12\n paddd xm4, xm6\n paddd xm2, xm7\n paddd xm2, xm4\n paddd xm2, xm14\n\n movq xm0, [bufq+xq-2] ; y=0,x=[-2,+5]\n.x_loop_ar2_inner:\n pmovsxbw xm1, xm0\n pmaddwd xm3, xm1, xm13\n paddd xm3, xm2\n psrldq xm1, 4 ; y=0,x=0\n psrldq xm2, 4 ; shift top to next pixel\n psrad xm3, [fg_dataq+FGData.ar_coeff_shift]\n ; don't packssdw since we only care about one value\n paddw xm3, xm1\n packsswb xm3, xm3\n pextrb [bufq+xq], xm3, 0\n pslldq xm3, 2\n pand xm3, xm15\n pandn xm0, xm15, xm0\n por xm0, xm3\n psrldq xm0, 1\n inc xq\n jz .x_loop_ar2_end\n test xq, 3\n jnz .x_loop_ar2_inner\n jmp .x_loop_ar2\n\n.x_loop_ar2_end:\n add bufq, 82\n dec hd\n jg .y_loop_ar2\n RET\n\n.ar3:\n DEFINE_ARGS buf, fg_data, shift\n%if WIN64\n SUB rsp, 16*12\n%assign stack_size_padded (stack_size_padded+16*12)\n%assign stack_size (stack_size+16*12)\n%else\n ALLOC_STACK 16*12\n%endif\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n vpbroadcastw xm14, [base+round_vals-12+shiftq*2]\n movq xm15, [base+byte_blend]\n pmovsxbw xm0, [fg_dataq+FGData.ar_coeffs_y+ 0] ; cf0-7\n pmovsxbw xm1, [fg_dataq+FGData.ar_coeffs_y+ 8] ; cf8-15\n pmovsxbw xm2, [fg_dataq+FGData.ar_coeffs_y+16] ; cf16-23\n pshufd xm9, xm0, q1111\n pshufd xm10, xm0, q2222\n pshufd xm11, xm0, q3333\n pshufd xm0, xm0, q0000\n pshufd xm6, xm1, q1111\n pshufd xm7, xm1, q2222\n pshufd xm8, xm1, q3333\n pshufd xm1, xm1, q0000\n pshufd xm3, xm2, q1111\n psrldq xm13, xm2, 10\n pinsrw xm2, [pw_1], 5\n pshufd xm4, xm2, q2222\n pshufd xm2, xm2, q0000\n pinsrw xm13, [base+round_vals+shiftq*2-10], 3\n mova [rsp+ 0*16], xm0\n mova [rsp+ 1*16], xm9\n mova [rsp+ 2*16], xm10\n mova [rsp+ 3*16], xm11\n mova [rsp+ 4*16], xm1\n mova [rsp+ 5*16], xm6\n mova [rsp+ 6*16], xm7\n mova [rsp+ 7*16], xm8\n mova [rsp+ 8*16], xm2\n mova [rsp+ 9*16], xm3\n mova [rsp+10*16], xm4\n DEFINE_ARGS buf, fg_data, h, x\n sub bufq, 82*73-(82*3+79)\n mov hd, 70\n.y_loop_ar3:\n mov xq, -76\n\n.x_loop_ar3:\n movu xm0, [bufq+xq-82*3-3] ; y=-3,x=[-3,+12]\n movu xm1, [bufq+xq-82*2-3] ; y=-2,x=[-3,+12]\n movu xm2, [bufq+xq-82*1-3] ; y=-1,x=[-3,+12]\n pxor xm3, xm3\n pcmpgtb xm6, xm3, xm2\n pcmpgtb xm5, xm3, xm1\n pcmpgtb xm4, xm3, xm0\n punpckhbw xm3, xm0, xm4\n punpcklbw xm0, xm4\n punpckhbw xm4, xm1, xm5\n punpcklbw xm1, xm5\n punpckhbw xm5, xm2, xm6\n punpcklbw xm2, xm6\n\n psrldq xm6, xm0, 2\n psrldq xm7, xm0, 4\n psrldq xm8, xm0, 6\n psrldq xm9, xm0, 8\n palignr xm10, xm3, xm0, 10\n palignr xm11, xm3, xm0, 12\n\n punpcklwd xm0, xm6\n punpcklwd xm7, xm8\n punpcklwd xm9, xm10\n punpcklwd xm11, xm1\n pmaddwd xm0, [rsp+ 0*16]\n pmaddwd xm7, [rsp+ 1*16]\n pmaddwd xm9, [rsp+ 2*16]\n pmaddwd xm11, [rsp+ 3*16]\n paddd xm0, xm7\n paddd xm9, xm11\n paddd xm0, xm9\n\n psrldq xm6, xm1, 2\n psrldq xm7, xm1, 4\n psrldq xm8, xm1, 6\n psrldq xm9, xm1, 8\n palignr xm10, xm4, xm1, 10\n palignr xm11, xm4, xm1, 12\n psrldq xm12, xm2, 2\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm10, xm11\n punpcklwd xm12, xm2, xm12\n pmaddwd xm6, [rsp+ 4*16]\n pmaddwd xm8, [rsp+ 5*16]\n pmaddwd xm10, [rsp+ 6*16]\n pmaddwd xm12, [rsp+ 7*16]\n paddd xm6, xm8\n paddd xm10, xm12\n paddd xm6, xm10\n paddd xm0, xm6\n\n psrldq xm6, xm2, 4\n psrldq xm7, xm2, 6\n psrldq xm8, xm2, 8\n palignr xm9, xm5, xm2, 10\n palignr xm5, xm5, xm2, 12\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm5, xm14\n pmaddwd xm6, [rsp+ 8*16]\n pmaddwd xm8, [rsp+ 9*16]\n pmaddwd xm5, [rsp+10*16]\n paddd xm0, xm6\n paddd xm8, xm5\n paddd xm0, xm8\n\n movq xm1, [bufq+xq-3] ; y=0,x=[-3,+4]\n.x_loop_ar3_inner:\n pmovsxbw xm2, xm1\n pmaddwd xm2, xm13\n pshufd xm3, xm2, q1111\n paddd xm2, xm3 ; left+cur\n paddd xm2, xm0 ; add top\n psrldq xm0, 4\n psrad xm2, [fg_dataq+FGData.ar_coeff_shift]\n ; don't packssdw since we only care about one value\n packsswb xm2, xm2\n pextrb [bufq+xq], xm2, 0\n pslldq xm2, 3\n pand xm2, xm15\n pandn xm1, xm15, xm1\n por xm1, xm2\n psrldq xm1, 1\n inc xq\n jz .x_loop_ar3_end\n test xq, 3\n jnz .x_loop_ar3_inner\n jmp .x_loop_ar3\n\n.x_loop_ar3_end:\n add bufq, 82\n dec hd\n jg .y_loop_ar3\n RET\n\nINIT_XMM avx2\ncglobal generate_grain_uv_420, 4, 10, 16, buf, bufy, fg_data, uv\n lea r4, [pb_mask]\n%define base r4-pb_mask\n movq xm1, [base+rnd_next_upperbit_mask]\n movq xm4, [base+mul_bits]\n movq xm7, [base+hmul_bits]\n mov r5d, [fg_dataq+FGData.grain_scale_shift]\n vpbroadcastw xm8, [base+round+r5*2]\n mova xm5, [base+pb_mask]\n vpbroadcastw xm0, [fg_dataq+FGData.seed]\n vpbroadcastw xm9, [base+pw_seed_xor+uvq*4]\n pxor xm0, xm9\n vpbroadcastd xm9, [base+pd_m65536]\n lea r6, [gaussian_sequence]\n mov r7d, 38\n add bufq, 44\n.loop_y:\n mov r5, -44\n.loop_x:\n pand xm2, xm0, xm1\n psrlw xm3, xm2, 10\n por xm2, xm3 ; bits 0xf, 0x1e, 0x3c and 0x78 are set\n pmullw xm2, xm4 ; bits 0x0f00 are set\n pshufb xm2, xm5, xm2 ; set 15th bit for next 4 seeds\n psllq xm6, xm2, 30\n por xm2, xm6\n psllq xm6, xm2, 15\n por xm2, xm6 ; aggregate each bit into next seed's high bit\n pmulhuw xm3, xm0, xm7\n por xm2, xm3 ; 4 next output seeds\n pshuflw xm0, xm2, q3333\n psrlw xm2, 5\n pmovzxwd xm3, xm2\n mova xm6, xm9\n vpgatherdd xm2, [r6+xm3*2], xm6\n pandn xm2, xm9, xm2\n packusdw xm2, xm2\n pmulhrsw xm2, xm8\n packsswb xm2, xm2\n movd [bufq+r5], xm2\n add r5, 4\n jl .loop_x\n add bufq, 82\n dec r7d\n jg .loop_y\n\n ; auto-regression code\n movsxd r5, [fg_dataq+FGData.ar_coeff_lag]\n movsxd r5, [base+generate_grain_uv_420_avx2_table+r5*4]\n lea r5, [r5+base+generate_grain_uv_420_avx2_table]\n jmp r5\n\n.ar0:\n INIT_YMM avx2\n DEFINE_ARGS buf, bufy, fg_data, uv, unused, shift\n imul uvd, 25\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movd xm4, [fg_dataq+FGData.ar_coeffs_uv+uvq]\n movd xm3, [base+hmul_bits+shiftq*2]\n DEFINE_ARGS buf, bufy, h\n pmovsxbw xm4, xm4\n vpbroadcastd m7, [pb_1]\n vpbroadcastw m6, [hmul_bits+4]\n vpbroadcastw m4, xm4\n vpbroadcastw m3, xm3\n sub bufq, 82*38+82-(82*3+41)\n add bufyq, 3+82*3\n mov hd, 35\n.y_loop_ar0:\n ; first 32 pixels\n movu xm8, [bufyq]\n movu xm9, [bufyq+82]\n movu xm10, [bufyq+16]\n movu xm11, [bufyq+82+16]\n vinserti128 m8, [bufyq+32], 1\n vinserti128 m9, [bufyq+82+32], 1\n vinserti128 m10, [bufyq+48], 1\n vinserti128 m11, [bufyq+82+48], 1\n pmaddubsw m8, m7, m8\n pmaddubsw m9, m7, m9\n pmaddubsw m10, m7, m10\n pmaddubsw m11, m7, m11\n paddw m8, m9\n paddw m10, m11\n pmulhrsw m8, m6\n pmulhrsw m10, m6\n pmullw m8, m4\n pmullw m10, m4\n pmulhrsw m8, m3\n pmulhrsw m10, m3\n packsswb m8, m10\n movu m0, [bufq]\n punpckhbw m1, m0, m8\n punpcklbw m0, m8\n pmaddubsw m1, m7, m1\n pmaddubsw m0, m7, m0\n packsswb m0, m1\n movu [bufq], m0\n\n ; last 6 pixels\n movu xm8, [bufyq+32*2]\n movu xm9, [bufyq+32*2+82]\n pmaddubsw xm8, xm7, xm8\n pmaddubsw xm9, xm7, xm9\n paddw xm8, xm9\n pmulhrsw xm8, xm6\n pmullw xm8, xm4\n pmulhrsw xm8, xm3\n packsswb xm8, xm8\n movq xm0, [bufq+32]\n punpcklbw xm8, xm0\n pmaddubsw xm8, xm7, xm8\n packsswb xm8, xm8\n vpblendw xm0, xm8, xm0, 1000b\n movq [bufq+32], xm0\n\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar0\n RET\n\n.ar1:\n INIT_XMM avx2\n DEFINE_ARGS buf, bufy, fg_data, uv, val3, cf3, min, max, x, shift\n imul uvd, 25\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movsx cf3d, byte [fg_dataq+FGData.ar_coeffs_uv+uvq+3]\n movd xm4, [fg_dataq+FGData.ar_coeffs_uv+uvq]\n pinsrb xm4, [fg_dataq+FGData.ar_coeffs_uv+uvq+4], 3\n DEFINE_ARGS buf, bufy, h, val0, val3, cf3, min, max, x, shift\n pmovsxbw xm4, xm4\n pshufd xm5, xm4, q1111\n pshufd xm4, xm4, q0000\n pmovsxwd xm3, [base+round_vals+shiftq*2-12] ; rnd\n vpbroadcastd xm7, [pb_1]\n vpbroadcastw xm6, [hmul_bits+4]\n vpbroadcastd xm3, xm3\n sub bufq, 82*38+44-(82*3+41)\n add bufyq, 79+82*3\n mov hd, 35\n mov mind, -128\n mov maxd, 127\n.y_loop_ar1:\n mov xq, -38\n movsx val3d, byte [bufq+xq-1]\n.x_loop_ar1:\n pmovsxbw xm0, [bufq+xq-82-1] ; top/left\n movq xm8, [bufyq+xq*2]\n movq xm9, [bufyq+xq*2+82]\n psrldq xm2, xm0, 2 ; top\n psrldq xm1, xm0, 4 ; top/right\n pmaddubsw xm8, xm7, xm8\n pmaddubsw xm9, xm7, xm9\n paddw xm8, xm9\n pmulhrsw xm8, xm6\n punpcklwd xm0, xm2\n punpcklwd xm1, xm8\n pmaddwd xm0, xm4\n pmaddwd xm1, xm5\n paddd xm0, xm1\n paddd xm0, xm3\n.x_loop_ar1_inner:\n movd val0d, xm0\n psrldq xm0, 4\n imul val3d, cf3d\n add val3d, val0d\n sarx val3d, val3d, shiftd\n movsx val0d, byte [bufq+xq]\n add val3d, val0d\n cmp val3d, maxd\n cmovg val3d, maxd\n cmp val3d, mind\n cmovl val3d, mind\n mov byte [bufq+xq], val3b\n ; keep val3d in-place as left for next x iteration\n inc xq\n jz .x_loop_ar1_end\n test xq, 3\n jnz .x_loop_ar1_inner\n jmp .x_loop_ar1\n\n.x_loop_ar1_end:\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar1\n RET\n\n.ar2:\n DEFINE_ARGS buf, bufy, fg_data, uv, unused, shift\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n imul uvd, 25\n vpbroadcastw xm15, [base+round_vals-12+shiftq*2]\n pmovsxbw xm8, [fg_dataq+FGData.ar_coeffs_uv+uvq+0] ; cf0-7\n pmovsxbw xm9, [fg_dataq+FGData.ar_coeffs_uv+uvq+8] ; cf8-12\n pinsrw xm9, [base+pw_1], 5\n vpbroadcastw xm7, [base+hmul_bits+4]\n vpbroadcastd xm6, [base+pb_1]\n DEFINE_ARGS buf, bufy, fg_data, h, unused, x\n pshufd xm12, xm9, q0000\n pshufd xm13, xm9, q1111\n pshufd xm14, xm9, q2222\n pshufd xm11, xm8, q3333\n pshufd xm10, xm8, q2222\n pshufd xm9, xm8, q1111\n pshufd xm8, xm8, q0000\n sub bufq, 82*38+44-(82*3+41)\n add bufyq, 79+82*3\n mov hd, 35\n.y_loop_ar2:\n mov xq, -38\n\n.x_loop_ar2:\n pmovsxbw xm0, [bufq+xq-82*2-2] ; y=-2,x=[-2,+5]\n pmovsxbw xm1, [bufq+xq-82*1-2] ; y=-1,x=[-2,+5]\n psrldq xm2, xm0, 2 ; y=-2,x=[-1,+5]\n psrldq xm3, xm1, 2 ; y=-1,x=[-1,+5]\n psrldq xm4, xm1, 4 ; y=-1,x=[+0,+5]\n punpcklwd xm2, xm0, xm2\n punpcklwd xm3, xm4\n pmaddwd xm2, xm8\n pmaddwd xm3, xm11\n paddd xm2, xm3\n\n psrldq xm4, xm0, 4 ; y=-2,x=[+0,+5]\n psrldq xm5, xm0, 6 ; y=-2,x=[+1,+5]\n psrldq xm0, 8 ; y=-2,x=[+2,+5]\n punpcklwd xm4, xm5\n punpcklwd xm0, xm1\n psrldq xm3, xm1, 6 ; y=-1,x=[+1,+5]\n psrldq xm1, xm1, 8 ; y=-1,x=[+2,+5]\n punpcklwd xm3, xm1\n pmaddwd xm4, xm9\n pmaddwd xm0, xm10\n pmaddwd xm3, xm12\n paddd xm4, xm0\n paddd xm2, xm3\n paddd xm2, xm4\n\n movq xm0, [bufyq+xq*2]\n movq xm3, [bufyq+xq*2+82]\n pmaddubsw xm0, xm6, xm0\n pmaddubsw xm3, xm6, xm3\n paddw xm0, xm3\n pmulhrsw xm0, xm7\n punpcklwd xm0, xm15\n pmaddwd xm0, xm14\n paddd xm2, xm0\n\n movq xm0, [bufq+xq-2] ; y=0,x=[-2,+5]\n.x_loop_ar2_inner:\n pmovsxbw xm0, xm0\n pmaddwd xm3, xm0, xm13\n paddd xm3, xm2\n psrldq xm2, 4 ; shift top to next pixel\n psrad xm3, [fg_dataq+FGData.ar_coeff_shift]\n pslldq xm3, 2\n psrldq xm0, 2\n paddw xm3, xm0\n vpblendw xm0, xm3, 00000010b\n packsswb xm0, xm0\n pextrb [bufq+xq], xm0, 1\n inc xq\n jz .x_loop_ar2_end\n test xq, 3\n jnz .x_loop_ar2_inner\n jmp .x_loop_ar2\n\n.x_loop_ar2_end:\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar2\n RET\n\n.ar3:\n DEFINE_ARGS buf, bufy, fg_data, uv, unused, shift\n SUB rsp, 16*12\n%assign stack_size_padded (stack_size_padded+16*12)\n%assign stack_size (stack_size+16*12)\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n imul uvd, 25\n vpbroadcastw xm14, [base+round_vals-12+shiftq*2]\n pmovsxbw xm0, [fg_dataq+FGData.ar_coeffs_uv+uvq+ 0] ; cf0-7\n pmovsxbw xm1, [fg_dataq+FGData.ar_coeffs_uv+uvq+ 8] ; cf8-15\n pmovsxbw xm2, [fg_dataq+FGData.ar_coeffs_uv+uvq+16] ; cf16-23\n pmovsxbw xm5, [fg_dataq+FGData.ar_coeffs_uv+uvq+24] ; cf24 [luma]\n pshufd xm9, xm0, q1111\n pshufd xm10, xm0, q2222\n pshufd xm11, xm0, q3333\n pshufd xm0, xm0, q0000\n pshufd xm6, xm1, q1111\n pshufd xm7, xm1, q2222\n pshufd xm8, xm1, q3333\n pshufd xm1, xm1, q0000\n pshufd xm3, xm2, q1111\n pshufd xm4, xm2, q2222\n vpbroadcastw xm5, xm5\n vpblendw xm4, xm5, 10101010b ; interleave luma cf\n psrldq xm5, xm2, 10\n pshufd xm2, xm2, q0000\n pinsrw xm5, [base+round_vals+shiftq*2-10], 3\n pmovzxwd xm14, xm14\n mova [rsp+ 0*16], xm0\n mova [rsp+ 1*16], xm9\n mova [rsp+ 2*16], xm10\n mova [rsp+ 3*16], xm11\n mova [rsp+ 4*16], xm1\n mova [rsp+ 5*16], xm6\n mova [rsp+ 6*16], xm7\n mova [rsp+ 7*16], xm8\n mova [rsp+ 8*16], xm2\n mova [rsp+ 9*16], xm3\n mova [rsp+10*16], xm4\n mova [rsp+11*16], xm5\n vpbroadcastd xm13, [base+pb_1]\n vpbroadcastw xm15, [base+hmul_bits+4]\n DEFINE_ARGS buf, bufy, fg_data, h, unused, x\n sub bufq, 82*38+44-(82*3+41)\n add bufyq, 79+82*3\n mov hd, 35\n.y_loop_ar3:\n mov xq, -38\n\n.x_loop_ar3:\n movu xm0, [bufq+xq-82*3-3] ; y=-3,x=[-3,+12]\n movu xm1, [bufq+xq-82*2-3] ; y=-2,x=[-3,+12]\n movu xm2, [bufq+xq-82*1-3] ; y=-1,x=[-3,+12]\n pxor xm3, xm3\n pcmpgtb xm6, xm3, xm2\n pcmpgtb xm5, xm3, xm1\n pcmpgtb xm4, xm3, xm0\n punpckhbw xm3, xm0, xm4\n punpcklbw xm0, xm4\n punpckhbw xm4, xm1, xm5\n punpcklbw xm1, xm5\n punpckhbw xm5, xm2, xm6\n punpcklbw xm2, xm6\n\n psrldq xm6, xm0, 2\n psrldq xm7, xm0, 4\n psrldq xm8, xm0, 6\n psrldq xm9, xm0, 8\n palignr xm10, xm3, xm0, 10\n palignr xm11, xm3, xm0, 12\n\n punpcklwd xm0, xm6\n punpcklwd xm7, xm8\n punpcklwd xm9, xm10\n punpcklwd xm11, xm1\n pmaddwd xm0, [rsp+ 0*16]\n pmaddwd xm7, [rsp+ 1*16]\n pmaddwd xm9, [rsp+ 2*16]\n pmaddwd xm11, [rsp+ 3*16]\n paddd xm0, xm7\n paddd xm9, xm11\n paddd xm0, xm9\n\n psrldq xm6, xm1, 2\n psrldq xm7, xm1, 4\n psrldq xm8, xm1, 6\n psrldq xm9, xm1, 8\n palignr xm10, xm4, xm1, 10\n palignr xm11, xm4, xm1, 12\n psrldq xm12, xm2, 2\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm10, xm11\n punpcklwd xm12, xm2, xm12\n pmaddwd xm6, [rsp+ 4*16]\n pmaddwd xm8, [rsp+ 5*16]\n pmaddwd xm10, [rsp+ 6*16]\n pmaddwd xm12, [rsp+ 7*16]\n paddd xm6, xm8\n paddd xm10, xm12\n paddd xm6, xm10\n paddd xm0, xm6\n\n psrldq xm6, xm2, 4\n psrldq xm7, xm2, 6\n psrldq xm8, xm2, 8\n palignr xm9, xm5, xm2, 10\n palignr xm5, xm5, xm2, 12\n\n movq xm1, [bufyq+xq*2]\n movq xm2, [bufyq+xq*2+82]\n pmaddubsw xm1, xm13, xm1\n pmaddubsw xm2, xm13, xm2\n paddw xm1, xm2\n pmulhrsw xm1, xm15\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm5, xm1\n pmaddwd xm6, [rsp+ 8*16]\n pmaddwd xm8, [rsp+ 9*16]\n pmaddwd xm5, [rsp+10*16]\n paddd xm0, xm6\n paddd xm8, xm5\n paddd xm0, xm8\n paddd xm0, xm14\n\n movq xm1, [bufq+xq-3] ; y=0,x=[-3,+4]\n.x_loop_ar3_inner:\n pmovsxbw xm1, xm1\n pmaddwd xm2, xm1, [rsp+16*11]\n pshufd xm3, xm2, q1111\n paddd xm2, xm3 ; left+cur\n paddd xm2, xm0 ; add top\n psrldq xm0, 4\n psrad xm2, [fg_dataq+FGData.ar_coeff_shift]\n ; don't packssdw, we only care about one value\n pslldq xm2, 6\n vpblendw xm1, xm2, 1000b\n packsswb xm1, xm1\n pextrb [bufq+xq], xm1, 3\n psrldq xm1, 1\n inc xq\n jz .x_loop_ar3_end\n test xq, 3\n jnz .x_loop_ar3_inner\n jmp .x_loop_ar3\n\n.x_loop_ar3_end:\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar3\n RET\n\nINIT_YMM avx2\ncglobal fgy_32x32xn, 6, 13, 16, dst, src, stride, fg_data, w, scaling, grain_lut\n pcmpeqw m10, m10\n psrld m10, 24\n mov r7d, [fg_dataq+FGData.scaling_shift]\n lea r8, [pb_mask]\n%define base r8-pb_mask\n vpbroadcastw m11, [base+mul_bits+r7*2-14]\n mov r7d, [fg_dataq+FGData.clip_to_restricted_range]\n vpbroadcastw m12, [base+max+r7*4]\n vpbroadcastw m13, [base+min+r7*2]\n\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, sby, see, overlap\n\n mov overlapd, [fg_dataq+FGData.overlap_flag]\n movifnidn sbyd, sbym\n test sbyd, sbyd\n setnz r7b\n test r7b, overlapb\n jnz .vertical_overlap\n\n imul seed, sbyd, (173 << 24) | 37\n add seed, (105 << 24) | 178\n rol seed, 8\n movzx seed, seew\n xor seed, [fg_dataq+FGData.seed]\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n unused1, unused2, see, overlap\n\n lea src_bakq, [srcq+wq]\n neg wq\n sub dstq, srcq\n\n.loop_x:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, overlap\n\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 164\n lea offyq, [offyq+offxq*2+747] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, overlap\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n add srcq, strideq\n add grain_lutq, 82\n dec hd\n jg .loop_y\n\n add wq, 32\n jge .end\n lea srcq, [src_bakq+wq]\n test overlapd, overlapd\n jz .loop_x\n\n ; r8m = sbym\n movd xm15, [pb_27_17_17_27]\n cmp dword r8m, 0\n jne .loop_x_hv_overlap\n\n ; horizontal overlap (without vertical overlap)\n movd xm14, [pw_1024]\n.loop_x_h_overlap:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy\n\n lea left_offxyd, [offyd+32] ; previous column's offy*stride+offx\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 164\n lea offyq, [offyq+offxq*2+747] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y_h_overlap:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n movd xm4, [grain_lutq+left_offxyq]\n punpcklbw xm4, xm3\n pmaddubsw xm4, xm15, xm4\n pmulhrsw xm4, xm14\n packsswb xm4, xm4\n vpblendw xm4, xm3, 11111110b\n vpblendd m3, m4, 00001111b\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n add srcq, strideq\n add grain_lutq, 82\n dec hd\n jg .loop_y_h_overlap\n\n add wq, 32\n jge .end\n lea srcq, [src_bakq+wq]\n\n ; r8m = sbym\n cmp dword r8m, 0\n jne .loop_x_hv_overlap\n jmp .loop_x_h_overlap\n\n.end:\n RET\n\n.vertical_overlap:\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, sby, see, overlap\n\n movzx sbyd, sbyb\n imul seed, [fg_dataq+FGData.seed], 0x00010001\n imul r7d, sbyd, 173 * 0x00010001\n imul sbyd, 37 * 0x01000100\n add r7d, (105 << 16) | 188\n add sbyd, (178 << 24) | (141 << 8)\n and r7d, 0x00ff00ff\n and sbyd, 0xff00ff00\n xor seed, r7d\n xor seed, sbyd ; (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n unused1, unused2, see, overlap\n\n lea src_bakq, [srcq+wq]\n neg wq\n sub dstq, srcq\n\n vpbroadcastd m14, [pw_1024]\n.loop_x_v_overlap:\n vpbroadcastw m15, [pb_27_17_17_27]\n\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, overlap, top_offxy\n\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 164\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq*2+0x10001*747+32*82]\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, overlap, top_offxy\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y_v_overlap:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n movu m4, [grain_lutq+top_offxyq]\n punpckhbw m6, m4, m3\n punpcklbw m4, m3\n pmaddubsw m6, m15, m6\n pmaddubsw m4, m15, m4\n pmulhrsw m6, m14\n pmulhrsw m4, m14\n packsswb m3, m4, m6\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n vpbroadcastw m15, [pb_27_17_17_27+2] ; swap weights for second v-overlap line\n add srcq, strideq\n add grain_lutq, 82\n dec hw\n jz .end_y_v_overlap\n ; 2 lines get vertical overlap, then fall back to non-overlap code for\n ; remaining (up to) 30 lines\n xor hd, 0x10000\n test hd, 0x10000\n jnz .loop_y_v_overlap\n jmp .loop_y\n\n.end_y_v_overlap:\n add wq, 32\n jge .end_hv\n lea srcq, [src_bakq+wq]\n\n ; since fg_dataq.overlap is guaranteed to be set, we never jump\n ; back to .loop_x_v_overlap, and instead always fall-through to\n ; h+v overlap\n\n movd xm15, [pb_27_17_17_27]\n.loop_x_hv_overlap:\n vpbroadcastw m8, [pb_27_17_17_27]\n\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy, top_offxy, topleft_offxy\n\n lea topleft_offxyq, [top_offxyq+32]\n lea left_offxyq, [offyq+32]\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 164\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq*2+0x10001*747+32*82]\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy, top_offxy, topleft_offxy\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y_hv_overlap:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n ; FIXME it would be nice to have another register here to do 2 vpgatherdd's in parallel\n vpgatherdd m9, [scalingq+m4], m3\n pcmpeqw m3, m3\n vpgatherdd m4, [scalingq+m5], m3\n pcmpeqw m3, m3\n vpgatherdd m5, [scalingq+m6], m3\n pcmpeqw m3, m3\n vpgatherdd m6, [scalingq+m7], m3\n pand m9, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m9, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n movu m6, [grain_lutq+top_offxyq]\n movd xm4, [grain_lutq+left_offxyq]\n movd xm7, [grain_lutq+topleft_offxyq]\n ; do h interpolation first (so top | top/left -> top, left | cur -> cur)\n punpcklbw xm4, xm3\n punpcklbw xm7, xm6\n pmaddubsw xm4, xm15, xm4\n pmaddubsw xm7, xm15, xm7\n pmulhrsw xm4, xm14\n pmulhrsw xm7, xm14\n packsswb xm4, xm4\n packsswb xm7, xm7\n vpblendw xm4, xm3, 11111110b\n vpblendw xm7, xm6, 11111110b\n vpblendd m3, m4, 00001111b\n vpblendd m6, m7, 00001111b\n ; followed by v interpolation (top | cur -> cur)\n punpckhbw m7, m6, m3\n punpcklbw m6, m3\n pmaddubsw m7, m8, m7\n pmaddubsw m6, m8, m6\n pmulhrsw m7, m14\n pmulhrsw m6, m14\n packsswb m3, m6, m7\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m9\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n vpbroadcastw m8, [pb_27_17_17_27+2] ; swap weights for second v-overlap line\n add srcq, strideq\n add grain_lutq, 82\n dec hw\n jz .end_y_hv_overlap\n ; 2 lines get vertical overlap, then fall back to non-overlap code for\n ; remaining (up to) 30 lines\n xor hd, 0x10000\n test hd, 0x10000\n jnz .loop_y_hv_overlap\n jmp .loop_y_h_overlap\n\n.end_y_hv_overlap:\n add wq, 32\n lea srcq, [src_bakq+wq]\n jl .loop_x_hv_overlap\n\n.end_hv:\n RET\n\ncglobal fguv_32x32xn_i420, 6, 15, 16, dst, src, stride, fg_data, w, scaling, \\\n grain_lut, h, sby, luma, lstride, uv_pl, is_id\n pcmpeqw m10, m10\n psrld m10, 24\n mov r7d, [fg_dataq+FGData.scaling_shift]\n lea r8, [pb_mask]\n%define base r8-pb_mask\n vpbroadcastw m11, [base+mul_bits+r7*2-14]\n mov r7d, [fg_dataq+FGData.clip_to_restricted_range]\n mov r9d, dword is_idm\n vpbroadcastw m13, [base+min+r7*2]\n shlx r7d, r7d, r9d\n vpbroadcastw m12, [base+max+r7*2]\n\n cmp byte [fg_dataq+FGData.chroma_scaling_from_luma], 0\n jne .csfl\n\n%macro FGUV_32x32xN_LOOP 1 ; not-csfl\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, sby, see, overlap\n\n%if %1\n mov r7d, dword r11m\n vpbroadcastb m0, [fg_dataq+FGData.uv_mult+r7*4]\n vpbroadcastb m1, [fg_dataq+FGData.uv_luma_mult+r7*4]\n punpcklbw m14, m1, m0\n vpbroadcastw m15, [fg_dataq+FGData.uv_offset+r7*4]\n%else\n vpbroadcastd m14, [pw_1024]\n vpbroadcastd m15, [pb_23_22]\n%endif\n\n mov overlapd, [fg_dataq+FGData.overlap_flag]\n movifnidn sbyd, sbym\n test sbyd, sbyd\n setnz r7b\n test r7b, overlapb\n jnz %%vertical_overlap\n\n imul seed, sbyd, (173 << 24) | 37\n add seed, (105 << 24) | 178\n rol seed, 8\n movzx seed, seew\n xor seed, [fg_dataq+FGData.seed]\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n unused2, unused3, see, overlap, unused4, unused5, lstride\n\n mov lumaq, r9mp\n lea r12, [srcq+wq]\n lea r13, [dstq+wq]\n lea r14, [lumaq+wq*2]\n mov r11mp, r12\n mov r12mp, r13\n mov lstrideq, r10mp\n neg wq\n\n%%loop_x:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, overlap, unused1, unused2, lstride\n\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 82\n lea offyq, [offyq+offxq+498] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, overlap, unused1, unused2, lstride\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: luma_src as dword\n\n ; scaling[luma_src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma_source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n movu xm3, [grain_lutq+offxyq+ 0]\n vinserti128 m3, [grain_lutq+offxyq+82], 1\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[luma_src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n sub hb, 2\n jg %%loop_y\n\n add wq, 16\n jge %%end\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n test overlapd, overlapd\n jz %%loop_x\n\n ; r8m = sbym\n cmp dword r8m, 0\n jne %%loop_x_hv_overlap\n\n ; horizontal overlap (without vertical overlap)\n%%loop_x_h_overlap:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy, unused1, unused2, lstride\n\n lea left_offxyd, [offyd+16] ; previous column's offy*stride+offx\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 82\n lea offyq, [offyq+offxq+498] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy, unused1, unused2, lstride\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y_h_overlap:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: luma_src as dword\n\n ; scaling[luma_src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma_source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n%if %1\n vpbroadcastd m6, [pb_23_22] ; FIXME\n%endif\n movu xm3, [grain_lutq+offxyq+ 0]\n movd xm4, [grain_lutq+left_offxyq+ 0]\n vinserti128 m3, [grain_lutq+offxyq+82], 1\n vinserti128 m4, [grain_lutq+left_offxyq+82], 1\n punpcklbw m4, m3\n%if %1\n pmaddubsw m4, m6, m4\n pmulhrsw m4, [pw_1024]\n%else\n pmaddubsw m4, m15, m4\n pmulhrsw m4, m14\n%endif\n packsswb m4, m4\n pcmpeqw m6, m6 ; FIXME\n psrldq m6, 15 ; FIXME\n vpblendvb m3, m3, m4, m6\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[luma_src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n sub hb, 2\n jg %%loop_y_h_overlap\n\n add wq, 16\n jge %%end\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n\n ; r8m = sbym\n cmp dword r8m, 0\n jne %%loop_x_hv_overlap\n jmp %%loop_x_h_overlap\n\n%%end:\n RET\n\n%%vertical_overlap:\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, \\\n sby, see, overlap, unused1, unused2, lstride\n\n movzx sbyd, sbyb\n imul seed, [fg_dataq+FGData.seed], 0x00010001\n imul r7d, sbyd, 173 * 0x00010001\n imul sbyd, 37 * 0x01000100\n add r7d, (105 << 16) | 188\n add sbyd, (178 << 24) | (141 << 8)\n and r7d, 0x00ff00ff\n and sbyd, 0xff00ff00\n xor seed, r7d\n xor seed, sbyd ; (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n unused1, unused2, see, overlap, unused3, unused4, lstride\n\n mov lumaq, r9mp\n lea r12, [srcq+wq]\n lea r13, [dstq+wq]\n lea r14, [lumaq+wq*2]\n mov r11mp, r12\n mov r12mp, r13\n mov lstrideq, r10mp\n neg wq\n\n%%loop_x_v_overlap:\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, overlap, top_offxy, unused, lstride\n\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 82\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq+0x10001*498+16*82]\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, overlap, top_offxy, unused, lstride\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y_v_overlap:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: luma_src as dword\n\n ; scaling[luma_src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma_source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n%if %1\n vpbroadcastd m6, [pb_23_22]\n%endif\n movq xm3, [grain_lutq+offxyq]\n movq xm4, [grain_lutq+top_offxyq]\n vinserti128 m3, [grain_lutq+offxyq+8], 1\n vinserti128 m4, [grain_lutq+top_offxyq+8], 1\n punpcklbw m4, m3\n%if %1\n pmaddubsw m4, m6, m4\n pmulhrsw m4, [pw_1024]\n%else\n pmaddubsw m4, m15, m4\n pmulhrsw m4, m14\n%endif\n packsswb m4, m4\n vpermq m4, m4, q3120\n ; only interpolate first line, insert second line unmodified\n vinserti128 m3, m4, [grain_lutq+offxyq+82], 1\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[luma_src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n sub hb, 2\n jl %%end_y_v_overlap\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n jmp %%loop_y\n\n%%end_y_v_overlap:\n add wq, 16\n jge %%end_hv\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n\n ; since fg_dataq.overlap is guaranteed to be set, we never jump\n ; back to .loop_x_v_overlap, and instead always fall-through to\n ; h+v overlap\n\n%%loop_x_hv_overlap:\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy, top_offxy, topleft_offxy, lstride\n\n lea topleft_offxyq, [top_offxyq+16]\n lea left_offxyq, [offyq+16]\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 82\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq+0x10001*498+16*82]\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy, top_offxy, topleft_offxy, lstride\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y_hv_overlap:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m9, m9\n pcmpeqw m3, m3\n vpgatherdd m8, [scalingq+m4], m9\n vpgatherdd m4, [scalingq+m5], m3\n pcmpeqw m9, m9\n pcmpeqw m3, m3\n vpgatherdd m5, [scalingq+m6], m9\n vpgatherdd m6, [scalingq+m7], m3\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n%if %1\n vpbroadcastd m9, [pb_23_22]\n%endif\n movu xm3, [grain_lutq+offxyq]\n movq xm6, [grain_lutq+top_offxyq]\n vinserti128 m3, [grain_lutq+offxyq+82], 1\n vinserti128 m6, [grain_lutq+top_offxyq+8], 1\n movd xm4, [grain_lutq+left_offxyq]\n movd xm7, [grain_lutq+topleft_offxyq]\n vinserti128 m4, [grain_lutq+left_offxyq+82], 1\n ; do h interpolation first (so top | top/left -> top, left | cur -> cur)\n punpcklbw m4, m3\n punpcklbw xm7, xm6\n%if %1\n pmaddubsw m4, m9, m4\n pmaddubsw xm7, xm9, xm7\n pmulhrsw m4, [pw_1024]\n pmulhrsw xm7, [pw_1024]\n%else\n pmaddubsw m4, m15, m4\n pmaddubsw xm7, xm15, xm7\n pmulhrsw m4, m14\n pmulhrsw xm7, xm14\n%endif\n packsswb m4, m4\n packsswb xm7, xm7\n pcmpeqw m9, m9 ; this is kind of ugly\n psrldq m9, 15\n vpblendvb m3, m3, m4, m9\n shufpd m9, m9, m9, 1110b\n vpblendvb m6, m6, m7, m9\n vpermq m9, m3, q3120\n ; followed by v interpolation (top | cur -> cur)\n punpcklbw m6, m9\n%if %1\n vpbroadcastd m9, [pb_23_22]\n pmaddubsw m6, m9, m6\n pmulhrsw m6, [pw_1024]\n%else\n pmaddubsw m6, m15, m6\n pmulhrsw m6, m14\n%endif\n packsswb m6, m6\n vpermq m6, m6, q3120\n vpblendd m3, m3, m6, 00001111b\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n sub hb, 2\n jg %%loop_y_h_overlap\n\n%%end_y_hv_overlap:\n add wq, 16\n jge %%end_hv\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n jmp %%loop_x_hv_overlap\n\n%%end_hv:\n RET\n%endmacro\n\n FGUV_32x32xN_LOOP 1\n.csfl:\n FGUV_32x32xN_LOOP 0\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2019, VideoLAN and dav1d authors\n; Copyright © 2019, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 32\npw_1024: times 16 dw 1024\npb_mask: db 0, 0x80, 0x80, 0, 0x80, 0, 0, 0x80, 0x80, 0, 0, 0x80, 0, 0x80, 0x80, 0\nrnd_next_upperbit_mask: dw 0x100B, 0x2016, 0x402C, 0x8058\nbyte_blend: db 0, 0, 0, 0xff, 0, 0, 0, 0\npw_seed_xor: times 2 dw 0xb524\n times 2 dw 0x49d8\npd_m65536: dd ~0xffff\npb_23_22: times 2 db 23, 22\npb_1: times 4 db 1\nhmul_bits: dw 32768, 16384, 8192, 4096\nround: dw 2048, 1024, 512\nmul_bits: dw 256, 128, 64, 32, 16\nround_vals: dw 32, 64, 128, 256, 512\nmax: dw 255, 240, 235\nmin: dw 0, 16\npb_27_17_17_27: db 27, 17, 17, 27\n\n%macro JMP_TABLE 1-*\n %xdefine %1_table %%table\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .ar%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nJMP_TABLE generate_grain_y_avx2, 0, 1, 2, 3\nJMP_TABLE generate_grain_uv_420_avx2, 0, 1, 2, 3\n\nstruc FGData\n .seed: resd 1\n .num_y_points: resd 1\n .y_points: resb 14 * 2\n .chroma_scaling_from_luma: resd 1\n .num_uv_points: resd 2\n .uv_points: resb 2 * 10 * 2\n .scaling_shift: resd 1\n .ar_coeff_lag: resd 1\n .ar_coeffs_y: resb 24\n .ar_coeffs_uv: resb 2 * 26 ; includes padding\n .ar_coeff_shift: resd 1\n .grain_scale_shift: resd 1\n .uv_mult: resd 2\n .uv_luma_mult: resd 2\n .uv_offset: resd 2\n .overlap_flag: resd 1\n .clip_to_restricted_range: resd 1\nendstruc\n\ncextern gaussian_sequence\n\nSECTION .text\n\nINIT_XMM avx2\ncglobal generate_grain_y, 2, 9, 16, buf, fg_data\n lea r4, [pb_mask]\n%define base r4-pb_mask\n movq xm1, [base+rnd_next_upperbit_mask]\n movq xm4, [base+mul_bits]\n movq xm7, [base+hmul_bits]\n mov r2d, [fg_dataq+FGData.grain_scale_shift]\n vpbroadcastw xm8, [base+round+r2*2]\n mova xm5, [base+pb_mask]\n vpbroadcastw xm0, [fg_dataq+FGData.seed]\n vpbroadcastd xm9, [base+pd_m65536]\n mov r2, -73*82\n sub bufq, r2\n lea r3, [gaussian_sequence]\n.loop:\n pand xm2, xm0, xm1\n psrlw xm3, xm2, 10\n por xm2, xm3 ; bits 0xf, 0x1e, 0x3c and 0x78 are set\n pmullw xm2, xm4 ; bits 0x0f00 are set\n pshufb xm2, xm5, xm2 ; set 15th bit for next 4 seeds\n psllq xm6, xm2, 30\n por xm2, xm6\n psllq xm6, xm2, 15\n por xm2, xm6 ; aggregate each bit into next seed's high bit\n pmulhuw xm3, xm0, xm7\n por xm2, xm3 ; 4 next output seeds\n pshuflw xm0, xm2, q3333\n psrlw xm2, 5\n pmovzxwd xm3, xm2\n mova xm6, xm9\n vpgatherdd xm2, [r3+xm3*2], xm6\n pandn xm2, xm9, xm2\n packusdw xm2, xm2\n pmulhrsw xm2, xm8\n packsswb xm2, xm2\n movd [bufq+r2], xm2\n add r2, 4\n jl .loop\n\n ; auto-regression code\n movsxd r2, [fg_dataq+FGData.ar_coeff_lag]\n movsxd r2, [base+generate_grain_y_avx2_table+r2*4]\n lea r2, [r2+base+generate_grain_y_avx2_table]\n jmp r2\n\n.ar1:\n DEFINE_ARGS buf, fg_data, cf3, shift, val3, min, max, x, val0\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movsx cf3d, byte [fg_dataq+FGData.ar_coeffs_y+3]\n movd xm4, [fg_dataq+FGData.ar_coeffs_y]\n DEFINE_ARGS buf, h, cf3, shift, val3, min, max, x, val0\n pinsrb xm4, [pb_1], 3\n pmovsxbw xm4, xm4\n pshufd xm5, xm4, q1111\n pshufd xm4, xm4, q0000\n vpbroadcastw xm3, [base+round_vals+shiftq*2-12] ; rnd\n sub bufq, 82*73-(82*3+79)\n mov hd, 70\n mov mind, -128\n mov maxd, 127\n.y_loop_ar1:\n mov xq, -76\n movsx val3d, byte [bufq+xq-1]\n.x_loop_ar1:\n pmovsxbw xm0, [bufq+xq-82-1] ; top/left\n pmovsxbw xm2, [bufq+xq-82+0] ; top\n pmovsxbw xm1, [bufq+xq-82+1] ; top/right\n punpcklwd xm0, xm2\n punpcklwd xm1, xm3\n pmaddwd xm0, xm4\n pmaddwd xm1, xm5\n paddd xm0, xm1\n.x_loop_ar1_inner:\n movd val0d, xm0\n psrldq xm0, 4\n imul val3d, cf3d\n add val3d, val0d\n%if WIN64\n sarx val3d, val3d, shiftd\n%else\n sar val3d, shiftb\n%endif\n movsx val0d, byte [bufq+xq]\n add val3d, val0d\n cmp val3d, maxd\n cmovg val3d, maxd\n cmp val3d, mind\n cmovl val3d, mind\n mov byte [bufq+xq], val3b\n ; keep val3d in-place as left for next x iteration\n inc xq\n jz .x_loop_ar1_end\n test xq, 3\n jnz .x_loop_ar1_inner\n jmp .x_loop_ar1\n\n.x_loop_ar1_end:\n add bufq, 82\n dec hd\n jg .y_loop_ar1\n.ar0:\n RET\n\n.ar2:\n DEFINE_ARGS buf, fg_data, shift\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movd xm14, [base+hmul_bits-10+shiftq*2]\n movq xm15, [base+byte_blend+1]\n pmovsxbw xm8, [fg_dataq+FGData.ar_coeffs_y+0] ; cf0-7\n movd xm9, [fg_dataq+FGData.ar_coeffs_y+8] ; cf8-11\n pmovsxbw xm9, xm9\n DEFINE_ARGS buf, h, x\n pshufd xm12, xm9, q0000\n pshufd xm13, xm9, q1111\n pshufd xm11, xm8, q3333\n pshufd xm10, xm8, q2222\n pshufd xm9, xm8, q1111\n pshufd xm8, xm8, q0000\n sub bufq, 82*73-(82*3+79)\n mov hd, 70\n.y_loop_ar2:\n mov xq, -76\n\n.x_loop_ar2:\n pmovsxbw xm0, [bufq+xq-82*2-2] ; y=-2,x=[-2,+5]\n pmovsxbw xm1, [bufq+xq-82*1-2] ; y=-1,x=[-2,+5]\n psrldq xm2, xm0, 2 ; y=-2,x=[-1,+5]\n psrldq xm3, xm1, 2 ; y=-1,x=[-1,+5]\n psrldq xm4, xm1, 4 ; y=-1,x=[+0,+5]\n punpcklwd xm2, xm0, xm2\n punpcklwd xm3, xm4\n pmaddwd xm2, xm8\n pmaddwd xm3, xm11\n paddd xm2, xm3\n\n psrldq xm4, xm0, 4 ; y=-2,x=[+0,+5]\n psrldq xm5, xm0, 6 ; y=-2,x=[+1,+5]\n psrldq xm6, xm0, 8 ; y=-2,x=[+2,+5]\n punpcklwd xm4, xm5\n punpcklwd xm6, xm1\n psrldq xm7, xm1, 6 ; y=-1,x=[+1,+5]\n psrldq xm1, xm1, 8 ; y=-1,x=[+2,+5]\n punpcklwd xm7, xm1\n pmaddwd xm4, xm9\n pmaddwd xm6, xm10\n pmaddwd xm7, xm12\n paddd xm4, xm6\n paddd xm2, xm7\n paddd xm2, xm4\n\n movq xm0, [bufq+xq-2] ; y=0,x=[-2,+5]\n.x_loop_ar2_inner:\n pmovsxbw xm1, xm0\n pmaddwd xm3, xm1, xm13\n paddd xm3, xm2\n psrldq xm1, 4 ; y=0,x=0\n psrldq xm2, 4 ; shift top to next pixel\n psrad xm3, 5\n packssdw xm3, xm3\n pmulhrsw xm3, xm14\n paddw xm3, xm1\n packsswb xm3, xm3\n pextrb [bufq+xq], xm3, 0\n pslldq xm3, 2\n pand xm3, xm15\n pandn xm0, xm15, xm0\n por xm0, xm3\n psrldq xm0, 1\n inc xq\n jz .x_loop_ar2_end\n test xq, 3\n jnz .x_loop_ar2_inner\n jmp .x_loop_ar2\n\n.x_loop_ar2_end:\n add bufq, 82\n dec hd\n jg .y_loop_ar2\n RET\n\n.ar3:\n DEFINE_ARGS buf, fg_data, shift\n%if WIN64\n SUB rsp, 16*12\n%assign stack_size_padded (stack_size_padded+16*12)\n%assign stack_size (stack_size+16*12)\n%else\n ALLOC_STACK 16*12\n%endif\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movd xm14, [base+hmul_bits-10+shiftq*2]\n movq xm15, [base+byte_blend]\n pmovsxbw xm0, [fg_dataq+FGData.ar_coeffs_y+ 0] ; cf0-7\n pmovsxbw xm1, [fg_dataq+FGData.ar_coeffs_y+ 8] ; cf8-15\n pmovsxbw xm2, [fg_dataq+FGData.ar_coeffs_y+16] ; cf16-23\n pshufd xm9, xm0, q1111\n pshufd xm10, xm0, q2222\n pshufd xm11, xm0, q3333\n pshufd xm0, xm0, q0000\n pshufd xm6, xm1, q1111\n pshufd xm7, xm1, q2222\n pshufd xm8, xm1, q3333\n pshufd xm1, xm1, q0000\n pshufd xm3, xm2, q1111\n pshufd xm4, xm2, q2222\n psrldq xm5, xm2, 10\n pshufd xm2, xm2, q0000\n pinsrw xm5, [base+round_vals+shiftq*2-10], 3\n mova [rsp+ 0*16], xm0\n mova [rsp+ 1*16], xm9\n mova [rsp+ 2*16], xm10\n mova [rsp+ 3*16], xm11\n mova [rsp+ 4*16], xm1\n mova [rsp+ 5*16], xm6\n mova [rsp+ 6*16], xm7\n mova [rsp+ 7*16], xm8\n mova [rsp+ 8*16], xm2\n mova [rsp+ 9*16], xm3\n mova [rsp+10*16], xm4\n mova [rsp+11*16], xm5\n pxor xm13, xm13\n DEFINE_ARGS buf, h, x\n sub bufq, 82*73-(82*3+79)\n mov hd, 70\n.y_loop_ar3:\n mov xq, -76\n\n.x_loop_ar3:\n movu xm0, [bufq+xq-82*3-3] ; y=-3,x=[-3,+12]\n movu xm1, [bufq+xq-82*2-3] ; y=-2,x=[-3,+12]\n movu xm2, [bufq+xq-82*1-3] ; y=-1,x=[-3,+12]\n pxor xm3, xm3\n pcmpgtb xm6, xm3, xm2\n pcmpgtb xm5, xm3, xm1\n pcmpgtb xm4, xm3, xm0\n punpckhbw xm3, xm0, xm4\n punpcklbw xm0, xm4\n punpckhbw xm4, xm1, xm5\n punpcklbw xm1, xm5\n punpckhbw xm5, xm2, xm6\n punpcklbw xm2, xm6\n\n psrldq xm6, xm0, 2\n psrldq xm7, xm0, 4\n psrldq xm8, xm0, 6\n psrldq xm9, xm0, 8\n palignr xm10, xm3, xm0, 10\n palignr xm11, xm3, xm0, 12\n\n punpcklwd xm0, xm6\n punpcklwd xm7, xm8\n punpcklwd xm9, xm10\n punpcklwd xm11, xm1\n pmaddwd xm0, [rsp+ 0*16]\n pmaddwd xm7, [rsp+ 1*16]\n pmaddwd xm9, [rsp+ 2*16]\n pmaddwd xm11, [rsp+ 3*16]\n paddd xm0, xm7\n paddd xm9, xm11\n paddd xm0, xm9\n\n psrldq xm6, xm1, 2\n psrldq xm7, xm1, 4\n psrldq xm8, xm1, 6\n psrldq xm9, xm1, 8\n palignr xm10, xm4, xm1, 10\n palignr xm11, xm4, xm1, 12\n psrldq xm12, xm2, 2\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm10, xm11\n punpcklwd xm12, xm2, xm12\n pmaddwd xm6, [rsp+ 4*16]\n pmaddwd xm8, [rsp+ 5*16]\n pmaddwd xm10, [rsp+ 6*16]\n pmaddwd xm12, [rsp+ 7*16]\n paddd xm6, xm8\n paddd xm10, xm12\n paddd xm6, xm10\n paddd xm0, xm6\n\n psrldq xm6, xm2, 4\n psrldq xm7, xm2, 6\n psrldq xm8, xm2, 8\n palignr xm9, xm5, xm2, 10\n palignr xm5, xm5, xm2, 12\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm5, xm13\n pmaddwd xm6, [rsp+ 8*16]\n pmaddwd xm8, [rsp+ 9*16]\n pmaddwd xm5, [rsp+10*16]\n paddd xm0, xm6\n paddd xm8, xm5\n paddd xm0, xm8\n\n movq xm1, [bufq+xq-3] ; y=0,x=[-3,+4]\n.x_loop_ar3_inner:\n pmovsxbw xm2, xm1\n pmaddwd xm2, [rsp+16*11]\n pshufd xm3, xm2, q1111\n paddd xm2, xm3 ; left+cur\n paddd xm2, xm0 ; add top\n psrldq xm0, 4\n psrad xm2, 5\n packssdw xm2, xm2\n pmulhrsw xm2, xm14\n packsswb xm2, xm2\n pextrb [bufq+xq], xm2, 0\n pslldq xm2, 3\n pand xm2, xm15\n pandn xm1, xm15, xm1\n por xm1, xm2\n psrldq xm1, 1\n inc xq\n jz .x_loop_ar3_end\n test xq, 3\n jnz .x_loop_ar3_inner\n jmp .x_loop_ar3\n\n.x_loop_ar3_end:\n add bufq, 82\n dec hd\n jg .y_loop_ar3\n RET\n\nINIT_XMM avx2\ncglobal generate_grain_uv_420, 4, 10, 16, buf, bufy, fg_data, uv\n lea r4, [pb_mask]\n%define base r4-pb_mask\n movq xm1, [base+rnd_next_upperbit_mask]\n movq xm4, [base+mul_bits]\n movq xm7, [base+hmul_bits]\n mov r5d, [fg_dataq+FGData.grain_scale_shift]\n vpbroadcastw xm8, [base+round+r5*2]\n mova xm5, [base+pb_mask]\n vpbroadcastw xm0, [fg_dataq+FGData.seed]\n vpbroadcastw xm9, [base+pw_seed_xor+uvq*4]\n pxor xm0, xm9\n vpbroadcastd xm9, [base+pd_m65536]\n lea r6, [gaussian_sequence]\n mov r7d, 38\n add bufq, 44\n.loop_y:\n mov r5, -44\n.loop_x:\n pand xm2, xm0, xm1\n psrlw xm3, xm2, 10\n por xm2, xm3 ; bits 0xf, 0x1e, 0x3c and 0x78 are set\n pmullw xm2, xm4 ; bits 0x0f00 are set\n pshufb xm2, xm5, xm2 ; set 15th bit for next 4 seeds\n psllq xm6, xm2, 30\n por xm2, xm6\n psllq xm6, xm2, 15\n por xm2, xm6 ; aggregate each bit into next seed's high bit\n pmulhuw xm3, xm0, xm7\n por xm2, xm3 ; 4 next output seeds\n pshuflw xm0, xm2, q3333\n psrlw xm2, 5\n pmovzxwd xm3, xm2\n mova xm6, xm9\n vpgatherdd xm2, [r6+xm3*2], xm6\n pandn xm2, xm9, xm2\n packusdw xm2, xm2\n pmulhrsw xm2, xm8\n packsswb xm2, xm2\n movd [bufq+r5], xm2\n add r5, 4\n jl .loop_x\n add bufq, 82\n dec r7d\n jg .loop_y\n\n ; auto-regression code\n movsxd r5, [fg_dataq+FGData.ar_coeff_lag]\n movsxd r5, [base+generate_grain_uv_420_avx2_table+r5*4]\n lea r5, [r5+base+generate_grain_uv_420_avx2_table]\n jmp r5\n\n.ar0:\n INIT_YMM avx2\n DEFINE_ARGS buf, bufy, fg_data, uv, unused, shift\n imul uvd, 25\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movd xm4, [fg_dataq+FGData.ar_coeffs_uv+uvq]\n movd xm3, [base+hmul_bits+shiftq*2]\n DEFINE_ARGS buf, bufy, h\n pmovsxbw xm4, xm4\n vpbroadcastd m7, [pb_1]\n vpbroadcastw m6, [hmul_bits+4]\n vpbroadcastw m4, xm4\n vpbroadcastw m3, xm3\n sub bufq, 82*38+82-(82*3+41)\n add bufyq, 3+82*3\n mov hd, 35\n.y_loop_ar0:\n ; first 32 pixels\n movu xm8, [bufyq]\n movu xm9, [bufyq+82]\n movu xm10, [bufyq+16]\n movu xm11, [bufyq+82+16]\n vinserti128 m8, [bufyq+32], 1\n vinserti128 m9, [bufyq+82+32], 1\n vinserti128 m10, [bufyq+48], 1\n vinserti128 m11, [bufyq+82+48], 1\n pmaddubsw m8, m7, m8\n pmaddubsw m9, m7, m9\n pmaddubsw m10, m7, m10\n pmaddubsw m11, m7, m11\n paddw m8, m9\n paddw m10, m11\n pmulhrsw m8, m6\n pmulhrsw m10, m6\n pmullw m8, m4\n pmullw m10, m4\n pmulhrsw m8, m3\n pmulhrsw m10, m3\n packsswb m8, m10\n movu m0, [bufq]\n punpckhbw m1, m0, m8\n punpcklbw m0, m8\n pmaddubsw m1, m7, m1\n pmaddubsw m0, m7, m0\n packsswb m0, m1\n movu [bufq], m0\n\n ; last 6 pixels\n movu xm8, [bufyq+32*2]\n movu xm9, [bufyq+32*2+82]\n pmaddubsw xm8, xm7, xm8\n pmaddubsw xm9, xm7, xm9\n paddw xm8, xm9\n pmulhrsw xm8, xm6\n pmullw xm8, xm4\n pmulhrsw xm8, xm3\n packsswb xm8, xm8\n movq xm0, [bufq+32]\n punpcklbw xm8, xm0\n pmaddubsw xm8, xm7, xm8\n packsswb xm8, xm8\n vpblendw xm0, xm8, xm0, 1000b\n movq [bufq+32], xm0\n\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar0\n RET\n\n.ar1:\n INIT_XMM avx2\n DEFINE_ARGS buf, bufy, fg_data, uv, val3, cf3, min, max, x, shift\n imul uvd, 25\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n movsx cf3d, byte [fg_dataq+FGData.ar_coeffs_uv+uvq+3]\n movd xm4, [fg_dataq+FGData.ar_coeffs_uv+uvq]\n pinsrb xm4, [fg_dataq+FGData.ar_coeffs_uv+uvq+4], 3\n DEFINE_ARGS buf, bufy, h, val0, val3, cf3, min, max, x, shift\n pmovsxbw xm4, xm4\n pshufd xm5, xm4, q1111\n pshufd xm4, xm4, q0000\n pmovsxwd xm3, [base+round_vals+shiftq*2-12] ; rnd\n vpbroadcastd xm7, [pb_1]\n vpbroadcastw xm6, [hmul_bits+4]\n vpbroadcastd xm3, xm3\n sub bufq, 82*38+44-(82*3+41)\n add bufyq, 79+82*3\n mov hd, 35\n mov mind, -128\n mov maxd, 127\n.y_loop_ar1:\n mov xq, -38\n movsx val3d, byte [bufq+xq-1]\n.x_loop_ar1:\n pmovsxbw xm0, [bufq+xq-82-1] ; top/left\n movq xm8, [bufyq+xq*2]\n movq xm9, [bufyq+xq*2+82]\n psrldq xm2, xm0, 2 ; top\n psrldq xm1, xm0, 4 ; top/right\n pmaddubsw xm8, xm7, xm8\n pmaddubsw xm9, xm7, xm9\n paddw xm8, xm9\n pmulhrsw xm8, xm6\n punpcklwd xm0, xm2\n punpcklwd xm1, xm8\n pmaddwd xm0, xm4\n pmaddwd xm1, xm5\n paddd xm0, xm1\n paddd xm0, xm3\n.x_loop_ar1_inner:\n movd val0d, xm0\n psrldq xm0, 4\n imul val3d, cf3d\n add val3d, val0d\n sarx val3d, val3d, shiftd\n movsx val0d, byte [bufq+xq]\n add val3d, val0d\n cmp val3d, maxd\n cmovg val3d, maxd\n cmp val3d, mind\n cmovl val3d, mind\n mov byte [bufq+xq], val3b\n ; keep val3d in-place as left for next x iteration\n inc xq\n jz .x_loop_ar1_end\n test xq, 3\n jnz .x_loop_ar1_inner\n jmp .x_loop_ar1\n\n.x_loop_ar1_end:\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar1\n RET\n\n.ar2:\n DEFINE_ARGS buf, bufy, fg_data, uv, unused, shift\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n imul uvd, 25\n movd xm15, [base+hmul_bits-10+shiftq*2]\n pmovsxbw xm8, [fg_dataq+FGData.ar_coeffs_uv+uvq+0] ; cf0-7\n pmovsxbw xm9, [fg_dataq+FGData.ar_coeffs_uv+uvq+8] ; cf8-12\n vpbroadcastw xm7, [base+hmul_bits+4]\n vpbroadcastd xm6, [base+pb_1]\n DEFINE_ARGS buf, bufy, h, x\n pshufd xm12, xm9, q0000\n pshufd xm13, xm9, q1111\n pshufd xm14, xm9, q2222\n pxor xm10, xm10\n vpblendw xm14, xm10, 10101010b\n pshufd xm11, xm8, q3333\n pshufd xm10, xm8, q2222\n pshufd xm9, xm8, q1111\n pshufd xm8, xm8, q0000\n sub bufq, 82*38+44-(82*3+41)\n add bufyq, 79+82*3\n mov hd, 35\n.y_loop_ar2:\n mov xq, -38\n\n.x_loop_ar2:\n pmovsxbw xm0, [bufq+xq-82*2-2] ; y=-2,x=[-2,+5]\n pmovsxbw xm1, [bufq+xq-82*1-2] ; y=-1,x=[-2,+5]\n psrldq xm2, xm0, 2 ; y=-2,x=[-1,+5]\n psrldq xm3, xm1, 2 ; y=-1,x=[-1,+5]\n psrldq xm4, xm1, 4 ; y=-1,x=[+0,+5]\n punpcklwd xm2, xm0, xm2\n punpcklwd xm3, xm4\n pmaddwd xm2, xm8\n pmaddwd xm3, xm11\n paddd xm2, xm3\n\n psrldq xm4, xm0, 4 ; y=-2,x=[+0,+5]\n psrldq xm5, xm0, 6 ; y=-2,x=[+1,+5]\n psrldq xm0, 8 ; y=-2,x=[+2,+5]\n punpcklwd xm4, xm5\n punpcklwd xm0, xm1\n psrldq xm3, xm1, 6 ; y=-1,x=[+1,+5]\n psrldq xm1, xm1, 8 ; y=-1,x=[+2,+5]\n punpcklwd xm3, xm1\n pmaddwd xm4, xm9\n pmaddwd xm0, xm10\n pmaddwd xm3, xm12\n paddd xm4, xm0\n paddd xm2, xm3\n paddd xm2, xm4\n\n movq xm0, [bufyq+xq*2]\n movq xm3, [bufyq+xq*2+82]\n pmaddubsw xm0, xm6, xm0\n pmaddubsw xm3, xm6, xm3\n paddw xm0, xm3\n pmulhrsw xm0, xm7\n punpcklwd xm0, xm0\n pmaddwd xm0, xm14\n paddd xm2, xm0\n\n movq xm0, [bufq+xq-2] ; y=0,x=[-2,+5]\n.x_loop_ar2_inner:\n pmovsxbw xm0, xm0\n pmaddwd xm3, xm0, xm13\n paddd xm3, xm2\n psrldq xm2, 4 ; shift top to next pixel\n psrad xm3, 5\n packssdw xm3, xm3\n pmulhrsw xm3, xm15\n pslldq xm3, 2\n psrldq xm0, 2\n paddw xm3, xm0\n vpblendw xm0, xm3, 00000010b\n packsswb xm0, xm0\n pextrb [bufq+xq], xm0, 1\n inc xq\n jz .x_loop_ar2_end\n test xq, 3\n jnz .x_loop_ar2_inner\n jmp .x_loop_ar2\n\n.x_loop_ar2_end:\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar2\n RET\n\n.ar3:\n DEFINE_ARGS buf, bufy, fg_data, uv, unused, shift\n SUB rsp, 16*12\n%assign stack_size_padded (stack_size_padded+16*12)\n%assign stack_size (stack_size+16*12)\n mov shiftd, [fg_dataq+FGData.ar_coeff_shift]\n imul uvd, 25\n movd xm14, [base+hmul_bits-10+shiftq*2]\n pmovsxbw xm0, [fg_dataq+FGData.ar_coeffs_uv+uvq+ 0] ; cf0-7\n pmovsxbw xm1, [fg_dataq+FGData.ar_coeffs_uv+uvq+ 8] ; cf8-15\n pmovsxbw xm2, [fg_dataq+FGData.ar_coeffs_uv+uvq+16] ; cf16-23\n pmovsxbw xm5, [fg_dataq+FGData.ar_coeffs_uv+uvq+24] ; cf24 [luma]\n pshufd xm9, xm0, q1111\n pshufd xm10, xm0, q2222\n pshufd xm11, xm0, q3333\n pshufd xm0, xm0, q0000\n pshufd xm6, xm1, q1111\n pshufd xm7, xm1, q2222\n pshufd xm8, xm1, q3333\n pshufd xm1, xm1, q0000\n pshufd xm3, xm2, q1111\n pshufd xm4, xm2, q2222\n vpbroadcastw xm5, xm5\n vpblendw xm4, xm5, 10101010b ; interleave luma cf\n psrldq xm5, xm2, 10\n pshufd xm2, xm2, q0000\n pinsrw xm5, [base+round_vals+shiftq*2-10], 3\n mova [rsp+ 0*16], xm0\n mova [rsp+ 1*16], xm9\n mova [rsp+ 2*16], xm10\n mova [rsp+ 3*16], xm11\n mova [rsp+ 4*16], xm1\n mova [rsp+ 5*16], xm6\n mova [rsp+ 6*16], xm7\n mova [rsp+ 7*16], xm8\n mova [rsp+ 8*16], xm2\n mova [rsp+ 9*16], xm3\n mova [rsp+10*16], xm4\n mova [rsp+11*16], xm5\n vpbroadcastd xm13, [base+pb_1]\n vpbroadcastw xm15, [base+hmul_bits+4]\n DEFINE_ARGS buf, bufy, h, x\n sub bufq, 82*38+44-(82*3+41)\n add bufyq, 79+82*3\n mov hd, 35\n.y_loop_ar3:\n mov xq, -38\n\n.x_loop_ar3:\n movu xm0, [bufq+xq-82*3-3] ; y=-3,x=[-3,+12]\n movu xm1, [bufq+xq-82*2-3] ; y=-2,x=[-3,+12]\n movu xm2, [bufq+xq-82*1-3] ; y=-1,x=[-3,+12]\n pxor xm3, xm3\n pcmpgtb xm6, xm3, xm2\n pcmpgtb xm5, xm3, xm1\n pcmpgtb xm4, xm3, xm0\n punpckhbw xm3, xm0, xm4\n punpcklbw xm0, xm4\n punpckhbw xm4, xm1, xm5\n punpcklbw xm1, xm5\n punpckhbw xm5, xm2, xm6\n punpcklbw xm2, xm6\n\n psrldq xm6, xm0, 2\n psrldq xm7, xm0, 4\n psrldq xm8, xm0, 6\n psrldq xm9, xm0, 8\n palignr xm10, xm3, xm0, 10\n palignr xm11, xm3, xm0, 12\n\n punpcklwd xm0, xm6\n punpcklwd xm7, xm8\n punpcklwd xm9, xm10\n punpcklwd xm11, xm1\n pmaddwd xm0, [rsp+ 0*16]\n pmaddwd xm7, [rsp+ 1*16]\n pmaddwd xm9, [rsp+ 2*16]\n pmaddwd xm11, [rsp+ 3*16]\n paddd xm0, xm7\n paddd xm9, xm11\n paddd xm0, xm9\n\n psrldq xm6, xm1, 2\n psrldq xm7, xm1, 4\n psrldq xm8, xm1, 6\n psrldq xm9, xm1, 8\n palignr xm10, xm4, xm1, 10\n palignr xm11, xm4, xm1, 12\n psrldq xm12, xm2, 2\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm10, xm11\n punpcklwd xm12, xm2, xm12\n pmaddwd xm6, [rsp+ 4*16]\n pmaddwd xm8, [rsp+ 5*16]\n pmaddwd xm10, [rsp+ 6*16]\n pmaddwd xm12, [rsp+ 7*16]\n paddd xm6, xm8\n paddd xm10, xm12\n paddd xm6, xm10\n paddd xm0, xm6\n\n psrldq xm6, xm2, 4\n psrldq xm7, xm2, 6\n psrldq xm8, xm2, 8\n palignr xm9, xm5, xm2, 10\n palignr xm5, xm5, xm2, 12\n\n movq xm1, [bufyq+xq*2]\n movq xm2, [bufyq+xq*2+82]\n pmaddubsw xm1, xm13, xm1\n pmaddubsw xm2, xm13, xm2\n paddw xm1, xm2\n pmulhrsw xm1, xm15\n\n punpcklwd xm6, xm7\n punpcklwd xm8, xm9\n punpcklwd xm5, xm1\n pmaddwd xm6, [rsp+ 8*16]\n pmaddwd xm8, [rsp+ 9*16]\n pmaddwd xm5, [rsp+10*16]\n paddd xm0, xm6\n paddd xm8, xm5\n paddd xm0, xm8\n\n movq xm1, [bufq+xq-3] ; y=0,x=[-3,+4]\n.x_loop_ar3_inner:\n pmovsxbw xm1, xm1\n pmaddwd xm2, xm1, [rsp+16*11]\n pshufd xm3, xm2, q1111\n paddd xm2, xm3 ; left+cur\n paddd xm2, xm0 ; add top\n psrldq xm0, 4\n psrad xm2, 5\n packssdw xm2, xm2\n pmulhrsw xm2, xm14\n pslldq xm2, 6\n vpblendw xm1, xm2, 1000b\n packsswb xm1, xm1\n pextrb [bufq+xq], xm1, 3\n psrldq xm1, 1\n inc xq\n jz .x_loop_ar3_end\n test xq, 3\n jnz .x_loop_ar3_inner\n jmp .x_loop_ar3\n\n.x_loop_ar3_end:\n add bufq, 82\n add bufyq, 82*2\n dec hd\n jg .y_loop_ar3\n RET\n\nINIT_YMM avx2\ncglobal fgy_32x32xn, 6, 13, 16, dst, src, stride, fg_data, w, scaling, grain_lut\n pcmpeqw m10, m10\n psrld m10, 24\n mov r7d, [fg_dataq+FGData.scaling_shift]\n lea r8, [pb_mask]\n%define base r8-pb_mask\n vpbroadcastw m11, [base+mul_bits+r7*2-14]\n mov r7d, [fg_dataq+FGData.clip_to_restricted_range]\n vpbroadcastw m12, [base+max+r7*4]\n vpbroadcastw m13, [base+min+r7*2]\n\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, sby, see, overlap\n\n mov overlapd, [fg_dataq+FGData.overlap_flag]\n movifnidn sbyd, sbym\n test sbyd, sbyd\n setnz r7b\n test r7b, overlapb\n jnz .vertical_overlap\n\n imul seed, sbyd, (173 << 24) | 37\n add seed, (105 << 24) | 178\n rol seed, 8\n movzx seed, seew\n xor seed, [fg_dataq+FGData.seed]\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n unused1, unused2, see, overlap\n\n lea src_bakq, [srcq+wq]\n neg wq\n sub dstq, srcq\n\n.loop_x:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, overlap\n\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 164\n lea offyq, [offyq+offxq*2+747] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, overlap\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n add srcq, strideq\n add grain_lutq, 82\n dec hd\n jg .loop_y\n\n add wq, 32\n jge .end\n lea srcq, [src_bakq+wq]\n test overlapd, overlapd\n jz .loop_x\n\n ; r8m = sbym\n movd xm15, [pb_27_17_17_27]\n cmp dword r8m, 0\n jne .loop_x_hv_overlap\n\n ; horizontal overlap (without vertical overlap)\n movd xm14, [pw_1024]\n.loop_x_h_overlap:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy\n\n lea left_offxyd, [offyd+32] ; previous column's offy*stride+offx\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 164\n lea offyq, [offyq+offxq*2+747] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y_h_overlap:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n movd xm4, [grain_lutq+left_offxyq]\n punpcklbw xm4, xm3\n pmaddubsw xm4, xm15, xm4\n pmulhrsw xm4, xm14\n packsswb xm4, xm4\n vpblendw xm4, xm3, 11111110b\n vpblendd m3, m4, 00001111b\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n add srcq, strideq\n add grain_lutq, 82\n dec hd\n jg .loop_y_h_overlap\n\n add wq, 32\n jge .end\n lea srcq, [src_bakq+wq]\n\n ; r8m = sbym\n cmp dword r8m, 0\n jne .loop_x_hv_overlap\n jmp .loop_x_h_overlap\n\n.end:\n RET\n\n.vertical_overlap:\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, sby, see, overlap\n\n movzx sbyd, sbyb\n imul seed, [fg_dataq+FGData.seed], 0x00010001\n imul r7d, sbyd, 173 * 0x00010001\n imul sbyd, 37 * 0x01000100\n add r7d, (105 << 16) | 188\n add sbyd, (178 << 24) | (141 << 8)\n and r7d, 0x00ff00ff\n and sbyd, 0xff00ff00\n xor seed, r7d\n xor seed, sbyd ; (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n unused1, unused2, see, overlap\n\n lea src_bakq, [srcq+wq]\n neg wq\n sub dstq, srcq\n\n vpbroadcastd m14, [pw_1024]\n.loop_x_v_overlap:\n vpbroadcastw m15, [pb_27_17_17_27]\n\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, overlap, top_offxy\n\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 164\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq*2+0x10001*747+32*82]\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, overlap, top_offxy\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y_v_overlap:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n movu m4, [grain_lutq+top_offxyq]\n punpckhbw m6, m4, m3\n punpcklbw m4, m3\n pmaddubsw m6, m15, m6\n pmaddubsw m4, m15, m4\n pmulhrsw m6, m14\n pmulhrsw m4, m14\n packsswb m3, m4, m6\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n vpbroadcastw m15, [pb_27_17_17_27+2] ; swap weights for second v-overlap line\n add srcq, strideq\n add grain_lutq, 82\n dec hw\n jz .end_y_v_overlap\n ; 2 lines get vertical overlap, then fall back to non-overlap code for\n ; remaining (up to) 30 lines\n xor hd, 0x10000\n test hd, 0x10000\n jnz .loop_y_v_overlap\n jmp .loop_y\n\n.end_y_v_overlap:\n add wq, 32\n jge .end_hv\n lea srcq, [src_bakq+wq]\n\n ; since fg_dataq.overlap is guaranteed to be set, we never jump\n ; back to .loop_x_v_overlap, and instead always fall-through to\n ; h+v overlap\n\n movd xm15, [pb_27_17_17_27]\n.loop_x_hv_overlap:\n vpbroadcastw m8, [pb_27_17_17_27]\n\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy, top_offxy, topleft_offxy\n\n lea topleft_offxyq, [top_offxyq+32]\n lea left_offxyq, [offyq+32]\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 164\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq*2+0x10001*747+32*82]\n\n DEFINE_ARGS dst, src, stride, src_bak, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy, top_offxy, topleft_offxy\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n.loop_y_hv_overlap:\n ; src\n mova m0, [srcq]\n pxor m2, m2\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n punpckhwd m5, m0, m2\n punpcklwd m4, m0, m2\n punpckhwd m7, m1, m2\n punpcklwd m6, m1, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m3, m3\n ; FIXME it would be nice to have another register here to do 2 vpgatherdd's in parallel\n vpgatherdd m9, [scalingq+m4], m3\n pcmpeqw m3, m3\n vpgatherdd m4, [scalingq+m5], m3\n pcmpeqw m3, m3\n vpgatherdd m5, [scalingq+m6], m3\n pcmpeqw m3, m3\n vpgatherdd m6, [scalingq+m7], m3\n pand m9, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m9, m4\n packusdw m5, m6\n\n ; grain = grain_lut[offy+y][offx+x]\n movu m3, [grain_lutq+offxyq]\n movu m6, [grain_lutq+top_offxyq]\n movd xm4, [grain_lutq+left_offxyq]\n movd xm7, [grain_lutq+topleft_offxyq]\n ; do h interpolation first (so top | top/left -> top, left | cur -> cur)\n punpcklbw xm4, xm3\n punpcklbw xm7, xm6\n pmaddubsw xm4, xm15, xm4\n pmaddubsw xm7, xm15, xm7\n pmulhrsw xm4, xm14\n pmulhrsw xm7, xm14\n packsswb xm4, xm4\n packsswb xm7, xm7\n vpblendw xm4, xm3, 11111110b\n vpblendw xm7, xm6, 11111110b\n vpblendd m3, m4, 00001111b\n vpblendd m6, m7, 00001111b\n ; followed by v interpolation (top | cur -> cur)\n punpckhbw m7, m6, m3\n punpcklbw m6, m3\n pmaddubsw m7, m8, m7\n pmaddubsw m6, m8, m6\n pmulhrsw m7, m14\n pmulhrsw m6, m14\n packsswb m3, m6, m7\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m9\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq+srcq], m0\n\n vpbroadcastw m8, [pb_27_17_17_27+2] ; swap weights for second v-overlap line\n add srcq, strideq\n add grain_lutq, 82\n dec hw\n jz .end_y_hv_overlap\n ; 2 lines get vertical overlap, then fall back to non-overlap code for\n ; remaining (up to) 30 lines\n xor hd, 0x10000\n test hd, 0x10000\n jnz .loop_y_hv_overlap\n jmp .loop_y_h_overlap\n\n.end_y_hv_overlap:\n add wq, 32\n lea srcq, [src_bakq+wq]\n jl .loop_x_hv_overlap\n\n.end_hv:\n RET\n\ncglobal fguv_32x32xn_i420, 6, 15, 16, dst, src, stride, fg_data, w, scaling, \\\n grain_lut, h, sby, luma, lstride, uv_pl, is_id\n pcmpeqw m10, m10\n psrld m10, 24\n mov r7d, [fg_dataq+FGData.scaling_shift]\n lea r8, [pb_mask]\n%define base r8-pb_mask\n vpbroadcastw m11, [base+mul_bits+r7*2-14]\n mov r7d, [fg_dataq+FGData.clip_to_restricted_range]\n mov r9d, dword is_idm\n vpbroadcastw m13, [base+min+r7*2]\n shlx r7d, r7d, r9d\n vpbroadcastw m12, [base+max+r7*2]\n\n cmp byte [fg_dataq+FGData.chroma_scaling_from_luma], 0\n jne .csfl\n\n%macro FGUV_32x32xN_LOOP 1 ; not-csfl\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, sby, see, overlap\n\n%if %1\n mov r7d, dword r11m\n vpbroadcastb m0, [fg_dataq+FGData.uv_mult+r7*4]\n vpbroadcastb m1, [fg_dataq+FGData.uv_luma_mult+r7*4]\n punpcklbw m14, m1, m0\n vpbroadcastw m15, [fg_dataq+FGData.uv_offset+r7*4]\n%else\n vpbroadcastd m14, [pw_1024]\n vpbroadcastd m15, [pb_23_22]\n%endif\n\n mov overlapd, [fg_dataq+FGData.overlap_flag]\n movifnidn sbyd, sbym\n test sbyd, sbyd\n setnz r7b\n test r7b, overlapb\n jnz %%vertical_overlap\n\n imul seed, sbyd, (173 << 24) | 37\n add seed, (105 << 24) | 178\n rol seed, 8\n movzx seed, seew\n xor seed, [fg_dataq+FGData.seed]\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n unused2, unused3, see, overlap, unused4, unused5, lstride\n\n mov lumaq, r9mp\n lea r12, [srcq+wq]\n lea r13, [dstq+wq]\n lea r14, [lumaq+wq*2]\n mov r11mp, r12\n mov r12mp, r13\n mov lstrideq, r10mp\n neg wq\n\n%%loop_x:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, overlap, unused1, unused2, lstride\n\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 82\n lea offyq, [offyq+offxq+498] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, overlap, unused1, unused2, lstride\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: luma_src as dword\n\n ; scaling[luma_src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma_source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n movu xm3, [grain_lutq+offxyq+ 0]\n vinserti128 m3, [grain_lutq+offxyq+82], 1\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[luma_src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n sub hb, 2\n jg %%loop_y\n\n add wq, 16\n jge %%end\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n test overlapd, overlapd\n jz %%loop_x\n\n ; r8m = sbym\n cmp dword r8m, 0\n jne %%loop_x_hv_overlap\n\n ; horizontal overlap (without vertical overlap)\n%%loop_x_h_overlap:\n mov r6d, seed\n or seed, 0xEFF4\n shr r6d, 1\n test seeb, seeh\n lea seed, [r6+0x8000]\n cmovp seed, r6d ; updated seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy, unused1, unused2, lstride\n\n lea left_offxyd, [offyd+16] ; previous column's offy*stride+offx\n mov offxd, seed\n rorx offyd, seed, 8\n shr offxd, 12\n and offyd, 0xf\n imul offyd, 82\n lea offyq, [offyq+offxq+498] ; offy*stride+offx\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy, unused1, unused2, lstride\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y_h_overlap:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: luma_src as dword\n\n ; scaling[luma_src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma_source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n%if %1\n vpbroadcastd m6, [pb_23_22] ; FIXME\n%endif\n movu xm3, [grain_lutq+offxyq+ 0]\n movd xm4, [grain_lutq+left_offxyq+ 0]\n vinserti128 m3, [grain_lutq+offxyq+82], 1\n vinserti128 m4, [grain_lutq+left_offxyq+82], 1\n punpcklbw m4, m3\n%if %1\n pmaddubsw m4, m6, m4\n pmulhrsw m4, [pw_1024]\n%else\n pmaddubsw m4, m15, m4\n pmulhrsw m4, m14\n%endif\n packsswb m4, m4\n pcmpeqw m6, m6 ; FIXME\n psrldq m6, 15 ; FIXME\n vpblendvb m3, m3, m4, m6\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[luma_src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n sub hb, 2\n jg %%loop_y_h_overlap\n\n add wq, 16\n jge %%end\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n\n ; r8m = sbym\n cmp dword r8m, 0\n jne %%loop_x_hv_overlap\n jmp %%loop_x_h_overlap\n\n%%end:\n RET\n\n%%vertical_overlap:\n DEFINE_ARGS dst, src, stride, fg_data, w, scaling, grain_lut, unused, \\\n sby, see, overlap, unused1, unused2, lstride\n\n movzx sbyd, sbyb\n imul seed, [fg_dataq+FGData.seed], 0x00010001\n imul r7d, sbyd, 173 * 0x00010001\n imul sbyd, 37 * 0x01000100\n add r7d, (105 << 16) | 188\n add sbyd, (178 << 24) | (141 << 8)\n and r7d, 0x00ff00ff\n and sbyd, 0xff00ff00\n xor seed, r7d\n xor seed, sbyd ; (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n unused1, unused2, see, overlap, unused3, unused4, lstride\n\n mov lumaq, r9mp\n lea r12, [srcq+wq]\n lea r13, [dstq+wq]\n lea r14, [lumaq+wq*2]\n mov r11mp, r12\n mov r12mp, r13\n mov lstrideq, r10mp\n neg wq\n\n%%loop_x_v_overlap:\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, overlap, top_offxy, unused, lstride\n\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 82\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq+0x10001*498+16*82]\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, overlap, top_offxy, unused, lstride\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y_v_overlap:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: luma_src as dword\n\n ; scaling[luma_src]\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m8, [scalingq+m4], m3\n vpgatherdd m4, [scalingq+m5], m9\n pcmpeqw m3, m3\n pcmpeqw m9, m9\n vpgatherdd m5, [scalingq+m6], m3\n vpgatherdd m6, [scalingq+m7], m9\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma_source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n%if %1\n vpbroadcastd m6, [pb_23_22]\n%endif\n movq xm3, [grain_lutq+offxyq]\n movq xm4, [grain_lutq+top_offxyq]\n vinserti128 m3, [grain_lutq+offxyq+8], 1\n vinserti128 m4, [grain_lutq+top_offxyq+8], 1\n punpcklbw m4, m3\n%if %1\n pmaddubsw m4, m6, m4\n pmulhrsw m4, [pw_1024]\n%else\n pmaddubsw m4, m15, m4\n pmulhrsw m4, m14\n%endif\n packsswb m4, m4\n vpermq m4, m4, q3120\n ; only interpolate first line, insert second line unmodified\n vinserti128 m3, m4, [grain_lutq+offxyq+82], 1\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[luma_src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n sub hb, 2\n jl %%end_y_v_overlap\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n jmp %%loop_y\n\n%%end_y_v_overlap:\n add wq, 16\n jge %%end_hv\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n\n ; since fg_dataq.overlap is guaranteed to be set, we never jump\n ; back to .loop_x_v_overlap, and instead always fall-through to\n ; h+v overlap\n\n%%loop_x_hv_overlap:\n ; we assume from the block above that bits 8-15 of r7d are zero'ed\n mov r6d, seed\n or seed, 0xeff4eff4\n test seeb, seeh\n setp r7b ; parity of top_seed\n shr seed, 16\n shl r7d, 16\n test seeb, seeh\n setp r7b ; parity of cur_seed\n or r6d, 0x00010001\n xor r7d, r6d\n rorx seed, r7d, 1 ; updated (cur_seed << 16) | top_seed\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n offx, offy, see, left_offxy, top_offxy, topleft_offxy, lstride\n\n lea topleft_offxyq, [top_offxyq+16]\n lea left_offxyq, [offyq+16]\n rorx offyd, seed, 8\n rorx offxd, seed, 12\n and offyd, 0xf000f\n and offxd, 0xf000f\n imul offyd, 82\n ; offxy=offy*stride+offx, (cur_offxy << 16) | top_offxy\n lea offyq, [offyq+offxq+0x10001*498+16*82]\n\n DEFINE_ARGS dst, src, stride, luma, w, scaling, grain_lut, \\\n h, offxy, see, left_offxy, top_offxy, topleft_offxy, lstride\n\n movzx top_offxyd, offxyw\n shr offxyd, 16\n\n mov hd, hm\n mov grain_lutq, grain_lutmp\n%%loop_y_hv_overlap:\n ; src\n mova xm4, [lumaq+lstrideq*0+ 0]\n mova xm6, [lumaq+lstrideq*0+16]\n mova xm0, [srcq]\n vpbroadcastd m7, [pb_1]\n vinserti128 m4, [lumaq+lstrideq*2 +0], 1\n vinserti128 m6, [lumaq+lstrideq*2+16], 1\n vinserti128 m0, [srcq+strideq], 1\n pxor m2, m2\n pmaddubsw m4, m7\n pmaddubsw m6, m7\n pavgw m4, m2\n pavgw m6, m2\n\n%if %1\n packuswb m4, m6 ; luma\n punpckhbw m6, m4, m0\n punpcklbw m4, m0 ; { luma, chroma }\n pmaddubsw m6, m14\n pmaddubsw m4, m14\n psraw m6, 6\n psraw m4, 6\n paddw m6, m15\n paddw m4, m15\n packuswb m4, m6 ; pack+unpack = clip\n punpckhbw m6, m4, m2\n punpcklbw m4, m2\n%endif\n\n punpckhwd m5, m4, m2\n punpcklwd m4, m2\n punpckhwd m7, m6, m2\n punpcklwd m6, m2 ; m4-7: src as dword\n\n ; scaling[src]\n pcmpeqw m9, m9\n pcmpeqw m3, m3\n vpgatherdd m8, [scalingq+m4], m9\n vpgatherdd m4, [scalingq+m5], m3\n pcmpeqw m9, m9\n pcmpeqw m3, m3\n vpgatherdd m5, [scalingq+m6], m9\n vpgatherdd m6, [scalingq+m7], m3\n pand m8, m10\n pand m4, m10\n pand m5, m10\n pand m6, m10\n packusdw m8, m4\n packusdw m5, m6\n\n ; unpack chroma source\n punpckhbw m1, m0, m2\n punpcklbw m0, m2 ; m0-1: src as word\n\n ; grain = grain_lut[offy+y][offx+x]\n%if %1\n vpbroadcastd m9, [pb_23_22]\n%endif\n movu xm3, [grain_lutq+offxyq]\n movq xm6, [grain_lutq+top_offxyq]\n vinserti128 m3, [grain_lutq+offxyq+82], 1\n vinserti128 m6, [grain_lutq+top_offxyq+8], 1\n movd xm4, [grain_lutq+left_offxyq]\n movd xm7, [grain_lutq+topleft_offxyq]\n vinserti128 m4, [grain_lutq+left_offxyq+82], 1\n ; do h interpolation first (so top | top/left -> top, left | cur -> cur)\n punpcklbw m4, m3\n punpcklbw xm7, xm6\n%if %1\n pmaddubsw m4, m9, m4\n pmaddubsw xm7, xm9, xm7\n pmulhrsw m4, [pw_1024]\n pmulhrsw xm7, [pw_1024]\n%else\n pmaddubsw m4, m15, m4\n pmaddubsw xm7, xm15, xm7\n pmulhrsw m4, m14\n pmulhrsw xm7, xm14\n%endif\n packsswb m4, m4\n packsswb xm7, xm7\n pcmpeqw m9, m9 ; this is kind of ugly\n psrldq m9, 15\n vpblendvb m3, m3, m4, m9\n shufpd m9, m9, m9, 1110b\n vpblendvb m6, m6, m7, m9\n vpermq m9, m3, q3120\n ; followed by v interpolation (top | cur -> cur)\n punpcklbw m6, m9\n%if %1\n vpbroadcastd m9, [pb_23_22]\n pmaddubsw m6, m9, m6\n pmulhrsw m6, [pw_1024]\n%else\n pmaddubsw m6, m15, m6\n pmulhrsw m6, m14\n%endif\n packsswb m6, m6\n vpermq m6, m6, q3120\n vpblendd m3, m3, m6, 00001111b\n pcmpgtb m7, m2, m3\n punpcklbw m2, m3, m7\n punpckhbw m3, m7\n\n ; noise = round2(scaling[src] * grain, scaling_shift)\n pmullw m2, m8\n pmullw m3, m5\n pmulhrsw m2, m11\n pmulhrsw m3, m11\n\n ; dst = clip_pixel(src, noise)\n paddw m0, m2\n paddw m1, m3\n pmaxsw m0, m13\n pmaxsw m1, m13\n pminsw m0, m12\n pminsw m1, m12\n packuswb m0, m1\n mova [dstq], xm0\n vextracti128 [dstq+strideq], m0, 1\n\n lea srcq, [srcq+strideq*2]\n lea dstq, [dstq+strideq*2]\n lea lumaq, [lumaq+lstrideq*4]\n add grain_lutq, 82*2\n sub hb, 2\n jg %%loop_y_h_overlap\n\n%%end_y_hv_overlap:\n add wq, 16\n jge %%end_hv\n mov srcq, r11mp\n mov dstq, r12mp\n lea lumaq, [r14+wq*2]\n add srcq, wq\n add dstq, wq\n jmp %%loop_x_hv_overlap\n\n%%end_hv:\n RET\n%endmacro\n\n FGUV_32x32xN_LOOP 1\n.csfl:\n FGUV_32x32xN_LOOP 0\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":483,"cells":{"commit":{"kind":"string","value":"e1762480709d87bfe2c946e87d2532622d4179bd"},"subject":{"kind":"string","value":"x86: Add mc w_mask 4:4:4 AVX-512 (Ice Lake) asm"},"message":{"kind":"string","value":"x86: Add mc w_mask 4:4:4 AVX-512 (Ice Lake) asm\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/mc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nbidir_sctr_w4: dd 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\nwm_420_perm4: db 1, 3, 9, 11, 5, 7, 13, 15, 17, 19, 25, 27, 21, 23, 29, 31\n db 33, 35, 41, 43, 37, 39, 45, 47, 49, 51, 57, 59, 53, 55, 61, 63\n db 0, 2, 8, 10, 4, 6, 12, 14, 16, 18, 24, 26, 20, 22, 28, 30\n db 32, 34, 40, 42, 36, 38, 44, 46, 48, 50, 56, 58, 52, 54, 60, 62\nwm_420_perm8: db 1, 3, 17, 19, 5, 7, 21, 23, 9, 11, 25, 27, 13, 15, 29, 31\n db 33, 35, 49, 51, 37, 39, 53, 55, 41, 43, 57, 59, 45, 47, 61, 63\n db 0, 2, 16, 18, 4, 6, 20, 22, 8, 10, 24, 26, 12, 14, 28, 30\n db 32, 34, 48, 50, 36, 38, 52, 54, 40, 42, 56, 58, 44, 46, 60, 62\nwm_420_perm16: db 1, 3, 33, 35, 5, 7, 37, 39, 9, 11, 41, 43, 13, 15, 45, 47\n db 17, 19, 49, 51, 21, 23, 53, 55, 25, 27, 57, 59, 29, 31, 61, 63\n db 0, 2, 32, 34, 4, 6, 36, 38, 8, 10, 40, 42, 12, 14, 44, 46\n db 16, 18, 48, 50, 20, 22, 52, 54, 24, 26, 56, 58, 28, 30, 60, 62\nwm_420_mask: db 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63\n db 67, 71, 75, 79, 83, 87, 91, 95, 99,103,107,111,115,119,123,127\n db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\n db 65, 69, 73, 77, 81, 85, 89, 93, 97,101,105,109,113,117,121,125\nwm_422_mask: db 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62\n db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\n db 66, 70, 74, 78, 82, 86, 90, 94, 98,102,106,110,114,118,122,126\n db 65, 69, 73, 77, 81, 85, 89, 93, 97,101,105,109,113,117,121,125\nwm_444_mask: db 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31\n db 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63\n db 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30\n db 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\nspel_h_perm16a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\nspel_h_perm16b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 36, 37, 38, 39, 37, 38, 39, 40, 38, 39, 40, 41, 39, 40, 41, 42\n db 44, 45, 46, 47, 45, 46, 47, 48, 46, 47, 48, 49, 47, 48, 49, 50\nspel_h_perm16c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\n db 48, 49, 50, 51, 49, 50, 51, 52, 50, 51, 52, 53, 51, 52, 53, 54\nspel_h_perm32a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\nspel_h_perm32b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 20, 21, 22, 23, 21, 22, 23, 24, 22, 23, 24, 25, 23, 24, 25, 26\n db 28, 29, 30, 31, 29, 30, 31, 32, 30, 31, 32, 33, 31, 32, 33, 34\nspel_h_perm32c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\nspel_hv_perm4a: db 8, 9, 16, 17, 10, 11, 18, 19, 12, 13, 20, 21, 14, 15, 22, 23\n db 16, 17, 24, 25, 18, 19, 26, 27, 20, 21, 28, 29, 22, 23, 30, 31\nspel_hv_perm4b: db 24, 25, 32, 33, 26, 27, 34, 35, 28, 29, 36, 37, 30, 31, 38, 39\n db 32, 33, 40, 41, 34, 35, 42, 43, 36, 37, 44, 45, 38, 39, 46, 47\n db 40, 41, 48, 49, 42, 43, 50, 51, 44, 45, 52, 53, 46, 47, 54, 55\n db 48, 49, 56, 57, 50, 51, 58, 59, 52, 53, 60, 61, 54, 55, 62, 63\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_v_shuf4: db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\nwm_420_perm64: dq 0xfedcba9876543210\nwm_420_sign: dd 0x01020102, 0x01010101\nwm_422_sign: dd 0x80808080, 0x7f7f7f7f\nwm_sign_avx512: dd 0x40804080, 0xc0c0c0c0, 0x40404040\n\npw_m128 times 2 dw -128\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_2: dd 2\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\n%define pb_m64 (wm_sign_avx512+4)\n%define pb_64 (wm_sign_avx512+8)\n%define pb_127 (wm_422_sign +4)\n\ncextern mc_subpel_filters\ncextern mc_warp_filter\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx512icl, 7, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx512icl, 4, 8, 16, 32, 64, 128\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro PREP_8TAP_H 0\n %if cpuflag(avx512)\n vpermb m10, m5, m0\n vpermb m11, m5, m1\n vpermb m12, m6, m0\n vpermb m13, m6, m1\n vpermb m14, m7, m0\n vpermb m15, m7, m1\n mova m0, m4\n mova m2, m4\n mova m1, m4\n mova m3, m4\n vpdpbusd m0, m10, m8\n vpdpbusd m2, m12, m8\n vpdpbusd m1, m11, m8\n vpdpbusd m3, m13, m8\n vpdpbusd m0, m12, m9\n vpdpbusd m2, m14, m9\n vpdpbusd m1, m13, m9\n vpdpbusd m3, m15, m9\n packssdw m0, m2\n packssdw m1, m3\n psraw m0, 2\n psraw m1, 2\n mova [tmpq+ 0], m0\n mova [tmpq+64], m1\n %else\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n pmaddubsw m1, m8\n pmaddubsw m0, m2, m8\n pmaddubsw m2, m9\n pmaddubsw m3, m9\n paddw m1, m2\n paddw m0, m3\n phaddw m0, m1, m0\n pmulhrsw m0, m4\n %endif\n%endmacro\n\n%macro PREP_8TAP_V_W4 5 ; round, weights\n movd xm0, [srcq+strideq*0]\n vpbroadcastd ym1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd ym3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd ym1, ym1, ym0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd ym3, ym3, ym2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd ym0, [srcq+strideq*0]\n vpbroadcastd ym2, [srcq+strideq*1]\n vpblendd ym1, ym1, ym0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd ym0, [srcq+strideq*2]\n vbroadcasti128 ym5, [deint_shuf4]\n vpblendd ym3, ym3, ym2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd ym2, ym3, ym1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd ym3, ym3, ym1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw ym1, ym2, ym3 ; 01 12 23 34\n vpblendd ym3, ym3, ym0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw ym2, ym3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym3, [srcq+strideq*0]\n vpbroadcastd ym4, [srcq+strideq*1]\n vpblendd ym3, ym3, ym4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd ym3, ym3, ym0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd ym0, [srcq+strideq*2]\n vpblendd ym3, ym3, ym0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb ym3, ym5 ; 67 78 89 9a\n pmaddubsw ym4, ym1, ym%2\n vperm2i128 ym1, ym2, ym3, 0x21 ; 45 56 67 78\n pmaddubsw ym2, ym%3\n paddw ym4, ym2\n mova ym2, ym3\n pmaddubsw ym3, ym%5\n paddw ym3, ym4\n pmaddubsw ym4, ym1, ym%4\n paddw ym3, ym4\n pmulhrsw ym3, ym%1\n mova [tmpq], ym3\n%endmacro\n\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\n%macro PREP_8TAP 0\n %if WIN64\n DECLARE_REG_TMP 6, 4\n %else\n DECLARE_REG_TMP 6, 7\n %endif\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep%+SUFFIX]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n%if cpuflag(avx512)\n vpbroadcastd m4, [pd_2]\n%else\n vpbroadcastd m4, [pw_8192]\n vbroadcasti128 m5, [subpel_h_shufA]\n%endif\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n%if notcpuflag(avx512)\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n%endif\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n add wq, r7\n jmp wq\n.h_w4:\n%if cpuflag(avx512)\n mov r3d, 0x4\n kmovb k1, r3d\n vbroadcasti128 ym5, [subpel_h_shufA]\n%endif\n movzx mxd, mxb\n dec srcq\n vpbroadcastd ym6, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n%if cpuflag(avx512icl)\n mova ym0, ym4\n mova ym1, ym4\n movq xm2, [srcq+strideq*0]\n movq xm3, [srcq+strideq*1]\n vpbroadcastq ym2{k1}, [srcq+strideq*2]\n vpbroadcastq ym3{k1}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pshufb ym2, ym5\n pshufb ym3, ym5\n vpdpbusd ym0, ym2, ym6\n vpdpbusd ym1, ym3, ym6\n packssdw ym0, ym1\n psraw ym0, 2\n%else\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m6\n pmaddubsw m1, m6\n phaddw m0, m1\n pmulhrsw m0, m4\n%endif\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m5, [subpel_h_shufA]\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n lea stride3q, [strideq*3]\n%endif\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n%if cpuflag(avx512)\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n%endif\n lea srcq, [srcq+strideq*(mmsize/(8*2))]\n%if cpuflag(avx512icl)\n mova m10, m4\n mova m11, m4\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n vpdpbusd m10, m1, m8\n vpdpbusd m11, m2, m8\n vpdpbusd m10, m2, m9\n vpdpbusd m11, m3, m9\n packssdw m10, m11\n psraw m0, m10, 2\n%else\n PREP_8TAP_H\n%endif\n mova [tmpq], m0\n add tmpq, mmsize\n sub hd, mmsize/(8*2)\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm16a]\n mova m6, [spel_h_perm16b]\n mova m7, [spel_h_perm16c]\n lea stride3q, [strideq*3]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m0, [srcq+strideq*1], 1\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n PREP_8TAP_H\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n.h_w32_loop:\n movu m0, [srcq+strideq*0]\n movu m1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n add tmpq, 64*2\n sub hd, 2\n jg .h_w32_loop\n RET\n%else\n xor r6d, r6d\n jmp .h_start\n%endif\n.h_w64:\n%if cpuflag(avx512)\n xor r6d, r6d\n%else\n mov r6, -32*1\n%endif\n jmp .h_start\n.h_w128:\n%if cpuflag(avx512)\n mov r6, -64*1\n%else\n mov r6, -32*3\n%endif\n.h_start:\n%if cpuflag(avx512)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n%endif\n sub srcq, r6\n mov r5, r6\n.h_loop:\n%if cpuflag(avx512icl)\n movu m0, [srcq+r6+32*0]\n movu m1, [srcq+r6+32*1]\n PREP_8TAP_H\n%else\n movu xm0, [srcq+r6+8*0]\n vinserti128 ym0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 ym0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n add r6, mmsize\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n%if cpuflag(avx512)\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_v)]\n add wq, r7\n%endif\n lea myq, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n vpbroadcastd m7, [pw_8192]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n%if cpuflag(avx512)\n jmp wq\n%else\n cmp wd, 8\n jg .v_w16\n je .v_w8\n%endif\n.v_w4:\n%if cpuflag(avx512)\n AVX512_MM_PERMUTATION\n PREP_8TAP_V_W4 23, 24, 25, 26, 27\n AVX512_MM_PERMUTATION\n%else\n PREP_8TAP_V_W4 7, 8, 9, 10, 11\n%endif\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.v_w8:\n%if cpuflag(avx512)\n mov r3d, 0xf044\n kmovw k1, r3d\n kshiftrw k2, k1, 8\n movq xm0, [srcq+strideq*0]\n vpbroadcastq ym1, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vmovdqa64 ym0{k1}, ym1\n vmovdqa64 ym1{k1}, ym2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n punpcklbw ym0, ym1 ; 01 12 __ __\n punpcklbw m2, m3 ; 23 34 23 34\n punpcklbw m4, m5 ; 45 56 45 56\n vmovdqa64 m0{k2}, m2 ; 01 12 23 34\n vmovdqa64 m2{k2}, m4 ; 23 34 45 56\n.v_w8_loop:\n vpbroadcastq m1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n pmaddubsw m14, m0, m8\n pmaddubsw m15, m2, m9\n vpblendmq m0{k1}, m6, m1\n vpblendmq m2{k1}, m1, m3\n vpbroadcastq m6, [srcq+strideq*2]\n paddw m14, m15\n punpcklbw m2, m0, m2 ; 67 78 67 78\n vpblendmq m12{k1}, m3, m5\n vpblendmq m13{k1}, m5, m6\n vpblendmq m0{k2}, m4, m2 ; 45 56 67 78\n punpcklbw m4, m12, m13 ; 89 9a 89 9a\n vmovdqa64 m2{k2}, m4 ; 67 78 89 9a\n pmaddubsw m12, m0, m10\n pmaddubsw m13, m2, m11\n paddw m14, m12\n paddw m14, m13\n pmulhrsw m14, m7\n mova [tmpq], m14\n%else\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512)\n mov r3d, 0xf0\n kmovb k1, r3d\n vbroadcasti128 m0, [srcq+strideq*0]\n vbroadcasti128 m1, [srcq+strideq*1]\n vbroadcasti128 m2, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n vmovdqa64 m0{k1}, m1\n vmovdqa64 m1{k1}, m2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n shufpd m0, m2, 0xcc ; 0a_2a 0b_2b 1a_3a 1b_3b\n shufpd m1, m3, 0xcc ; 1a_3a 1b_3b 2a_4a 2b_4b\n shufpd m4, m4, 0x44 ; 4a_-- 4b_-- 5a_-- 5b_--\n shufpd m5, m5, 0x44 ; 5a_-- 5b_-- 6a_-- 6b_--\n punpckhbw m2, m0, m1 ; 23a 23b 34a 34b\n punpcklbw m0, m1 ; 01a 01b 12a 12b\n punpcklbw m4, m5 ; 45a 45b 56a 56b\n.v_w16_loop:\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m5, [srcq+strideq*0]\n vpblendmq m1{k1}, m6, m3\n vmovdqa64 m3{k1}, m5\n pmaddubsw m12, m0, m8\n pmaddubsw m13, m2, m8\n pmaddubsw m14, m2, m9\n pmaddubsw m15, m4, m9\n pmaddubsw m0, m4, m10\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n paddw m12, m14\n paddw m13, m15\n paddw m12, m0\n vmovdqa64 m5{k1}, m2\n vmovdqa64 m2{k1}, m6\n mova m0, m4\n shufpd m1, m5, 0xcc ; 6a_8a 6b_8b 7a_9a 7b_9b\n shufpd m3, m2, 0xcc ; 7a_9a 7b_9b 8a_Aa 8b_Ab\n punpcklbw m2, m1, m3 ; 67a 67b 78a 78b\n punpckhbw m4, m1, m3 ; 89a 89b 9Aa 9Ab\n pmaddubsw m14, m2, m10\n pmaddubsw m15, m2, m11\n paddw m13, m14\n paddw m12, m15\n pmaddubsw m14, m4, m11\n paddw m13, m14\n pmulhrsw m12, m7\n pmulhrsw m13, m7\n mova [tmpq+ 0], m12\n mova [tmpq+64], m13\n add tmpq, 64*2\n sub hd, 4\n jg .v_w16_loop\n%else\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n%endif\n RET\n%if cpuflag(avx512)\n.v_w32:\n mova m18, [bilin_v_perm64]\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n movu ym3, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym4, [srcq+strideq*0]\n movu ym5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym6, [srcq+strideq*0]\n vpermq m0, m18, m0\n vpermq m1, m18, m1\n vpermq m2, m18, m2\n vpermq m3, m18, m3\n vpermq m4, m18, m4\n vpermq m5, m18, m5\n vpermq m6, m18, m6\n punpcklbw m0, m1\n punpcklbw m1, m2\n punpcklbw m2, m3\n punpcklbw m3, m4\n punpcklbw m4, m5\n punpcklbw m5, m6\n.v_w32_loop:\n movu ym12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym13, [srcq+strideq*0]\n pmaddubsw m14, m0, m8\n pmaddubsw m16, m2, m9\n pmaddubsw m15, m1, m8\n pmaddubsw m17, m3, m9\n mova m0, m2\n mova m1, m3\n vpermq m12, m18, m12\n vpermq m13, m18, m13\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m4, m10\n pmaddubsw m17, m5, m10\n punpcklbw m6, m12\n punpcklbw m12, m13\n mova m2, m4\n mova m3, m5\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m6, m11\n pmaddubsw m17, m12, m11\n mova m4, m6\n mova m5, m12\n paddw m14, m16\n paddw m15, m17\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova m6, m13\n mova [tmpq+ 0], m14\n mova [tmpq+64], m15\n add tmpq, 64*2\n sub hd, 2\n jg .v_w32_loop\n vzeroupper\n RET\n.v_w64:\n mov r6d, hd\n mov wd, 64\n jmp .v_start\n.v_w128:\n lea r6d, [(1<<8)+hq]\n mov wd, 128\n.v_start:\n WIN64_SPILL_XMM 27\n mova m26, [bilin_v_perm64]\n mov r5, tmpq\n mov r7, srcq\n.v_loop0:\n vpermq m0, m26, [srcq+strideq*0]\n vpermq m1, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m2, m26, [srcq+strideq*0]\n vpermq m3, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m4, m26, [srcq+strideq*0]\n vpermq m5, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m6, m26, [srcq+strideq*0]\n punpckhbw m12, m0, m1\n punpcklbw m0, m1\n punpckhbw m13, m1, m2\n punpcklbw m1, m2\n punpckhbw m14, m2, m3\n punpcklbw m2, m3\n punpckhbw m15, m3, m4\n punpcklbw m3, m4\n punpckhbw m16, m4, m5\n punpcklbw m4, m5\n punpckhbw m17, m5, m6\n punpcklbw m5, m6\n.v_loop:\n vpermq m18, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m19, m26, [srcq+strideq*0]\n pmaddubsw m20, m0, m8\n pmaddubsw m21, m12, m8\n pmaddubsw m22, m1, m8\n pmaddubsw m23, m13, m8\n mova m0, m2\n mova m12, m14\n mova m1, m3\n mova m13, m15\n pmaddubsw m2, m9\n pmaddubsw m14, m9\n pmaddubsw m3, m9\n pmaddubsw m15, m9\n punpckhbw m24, m6, m18\n punpcklbw m6, m18\n paddw m20, m2\n paddw m21, m14\n paddw m22, m3\n paddw m23, m15\n mova m2, m4\n mova m14, m16\n mova m3, m5\n mova m15, m17\n pmaddubsw m4, m10\n pmaddubsw m16, m10\n pmaddubsw m5, m10\n pmaddubsw m17, m10\n punpckhbw m25, m18, m19\n punpcklbw m18, m19\n paddw m20, m4\n paddw m21, m16\n paddw m22, m5\n paddw m23, m17\n mova m4, m6\n mova m16, m24\n mova m5, m18\n mova m17, m25\n pmaddubsw m6, m11\n pmaddubsw m24, m11\n pmaddubsw m18, m11\n pmaddubsw m25, m11\n paddw m20, m6\n paddw m21, m24\n paddw m22, m18\n paddw m23, m25\n pmulhrsw m20, m7\n pmulhrsw m21, m7\n pmulhrsw m22, m7\n pmulhrsw m23, m7\n mova m6, m19\n mova [tmpq+wq*0+ 0], m20\n mova [tmpq+wq*0+64], m21\n mova [tmpq+wq*2+ 0], m22\n mova [tmpq+wq*2+64], m23\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_loop\n movzx hd, r6b\n add r5, 64*2\n add r7, 64\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_loop0\n%endif\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n %assign stack_size_padded 0\n WIN64_SPILL_XMM 16\n cmp wd, 4\n je .hv_w4\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n%if cpuflag(avx512)\n tzcnt wd, wd\n vpbroadcastd m8, [pd_2]\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_hv)]\n vpbroadcastd m9, [pd_32]\n add wq, r7\n%endif\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512)\n jmp wq\n%else\n jmp .hv_w8\n%endif\n.hv_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n%if cpuflag(avx512)\n mov r3d, 0x04\n kmovb k1, r3d\n kshiftlb k2, k1, 2\n kshiftlb k3, k1, 4\n vpbroadcastd m10, [pd_2]\n vbroadcasti128 m16, [subpel_h_shufA]\n%else\n mova m7, [subpel_h_shuf4]\n pmovzxbd m9, [deint_shuf4]\n vpbroadcastd m10, [pw_8192]\n%endif\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512icl)\n movq xm3, [srcq+strideq*0]\n vpbroadcastq ym2, [srcq+strideq*1]\n vpbroadcastq ym3{k1}, [srcq+strideq*2]\n vpbroadcastq m2{k2}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3{k2}, [srcq+strideq*0]\n vpbroadcastq m2{k3}, [srcq+strideq*1]\n vpbroadcastq m3{k3}, [srcq+strideq*2]\n mova m17, [spel_hv_perm4a]\n movu m18, [spel_hv_perm4b]\n mova m0, m10\n mova m1, m10\n pshufb m2, m16\n pshufb m3, m16\n vpdpbusd m0, m2, m8\n vpdpbusd m1, m3, m8\n packssdw m0, m1 ; _ 0 1 2 3 4 5 6\n psraw m0, 2\n vpermb m1, m17, m0 ; 01 12 23 34\n vpermb m2, m18, m0 ; 23 34 45 56\n.hv_w4_loop:\n movq xm3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movq xm4, [srcq+strideq*0]\n vpbroadcastq ym3{k1}, [srcq+strideq*1]\n vpbroadcastq ym4{k1}, [srcq+strideq*2]\n mova ym5, ym10\n mova ym6, ym10\n pshufb ym3, ym16\n pshufb ym4, ym16\n vpdpbusd ym5, ym3, ym8\n vpdpbusd ym6, ym4, ym8\n mova m7, m11\n packssdw ym5, ym6 ; 7 8 9 a _ _ _ _\n psraw ym5, 2\n valignq m0, m5, m0, 4 ; _ 4 5 6 7 8 9 a\n vpdpwssd m7, m1, m12\n vpdpwssd m7, m2, m13\n vpermb m1, m17, m0 ; 45 56 67 78\n vpermb m2, m18, m0 ; 67 78 89 9a\n vpdpwssd m7, m1, m14\n vpdpwssd m7, m2, m15\n psrad m7, 6\n vpmovdw [tmpq], m7\n%else\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7 ; 00 01 10 11 02 03 12 13\n pshufb m0, m7 ; 20 21 30 31 22 23 32 33\n pshufb m3, m7 ; 40 41 50 51 42 43 52 53\n pshufb m1, m7 ; 60 61 60 61 62 63 62 63\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0 ; 0a 1a 2a 3a 0b 1b 2b 3b\n phaddw m3, m1 ; 4a 5a 6a __ 4b 5b 6b __\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4 ; 1a 2a 3a 4a 1b 2b 3b 4b\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n%endif\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.hv_w8:\n%if cpuflag(avx512icl)\n WIN64_SPILL_XMM 24\n vbroadcasti128 m16, [subpel_h_shufA]\n vbroadcasti128 m17, [subpel_h_shufB]\n vbroadcasti128 m18, [subpel_h_shufC]\n vinserti128 ym0, [srcq+strideq*0], 1\n vinserti128 m0, [srcq+strideq*1], 2\n vinserti128 m0, [srcq+strideq*2], 3\n movu xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym1, [srcq+strideq*0], 1\n vinserti128 m1, [srcq+strideq*1], 2\n vinserti128 m1, [srcq+strideq*2], 3\n mova m2, m8\n mova m4, m8\n mova m3, m8\n mova m5, m8\n pshufb m20, m0, m16\n pshufb m21, m0, m17\n pshufb m22, m0, m18\n pshufb m23, m1, m16\n pshufb m6, m1, m17\n pshufb m7, m1, m18\n vpdpbusd m2, m20, m10\n vpdpbusd m4, m21, m10\n vpdpbusd m2, m21, m11\n vpdpbusd m4, m22, m11\n vpdpbusd m3, m23, m10\n vpdpbusd m5, m6, m10\n vpdpbusd m3, m6, m11\n vpdpbusd m5, m7, m11\n packssdw m2, m4\n packssdw m3, m5\n psraw m2, 2 ; _ 0 1 2\n psraw m3, 2 ; 3 4 5 6\n valignq m0, m3, m2, 2 ; 0 1 2 3\n valignq m1, m3, m2, 4 ; 1 2 3 4\n valignq m2, m3, m2, 6 ; 2 3 4 5\n punpcklwd m4, m0, m1 ; 01a 12a 23a 34a\n punpckhwd m5, m0, m1 ; 01b 12b 23b 34b\n punpcklwd m6, m2, m3 ; 23a 34a 45a 56a\n punpckhwd m7, m2, m3 ; 23b 34b 45b 56b\n.hv_w8_loop:\n movu xm19, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym19, [srcq+strideq*0], 1\n vinserti128 m19, [srcq+strideq*1], 2\n vinserti128 m19, [srcq+strideq*2], 3\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m4, m12\n vpdpwssd m21, m5, m12\n vpdpwssd m20, m6, m13\n vpdpwssd m21, m7, m13\n pshufb m0, m19, m16\n pshufb m1, m19, m17\n pshufb m2, m19, m18\n vpdpbusd m22, m0, m10\n vpdpbusd m23, m1, m10\n vpdpbusd m22, m1, m11\n vpdpbusd m23, m2, m11\n packssdw m22, m23\n psraw m22, 2 ; 7 8 9 A\n valignq m0, m22, m3, 2 ; 4 5 6 7\n valignq m1, m22, m3, 4 ; 5 6 7 8\n valignq m2, m22, m3, 6 ; 6 7 8 9\n mova m3, m22\n punpcklwd m4, m0, m1 ; 45a 56a 67a 78a\n punpckhwd m5, m0, m1 ; 45b 56b 67b 78b\n punpcklwd m6, m2, m3 ; 67a 78a 89a 9Aa\n punpckhwd m7, m2, m3 ; 67b 78b 89b 9Ab\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq], m20\n add tmpq, 64\n sub hd, 4\n jg .hv_w8_loop\n%else\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n%endif\n RET\n%if cpuflag(avx512icl)\n.hv_w16:\n mov wd, 16*2\n jmp .hv_start\n.hv_w32:\n mov wd, 32*2\n jmp .hv_start\n.hv_w64:\n mov wd, 64*2\n jmp .hv_start\n.hv_w128:\n mov wd, 128*2\n.hv_start:\n WIN64_SPILL_XMM 31\n mova m16, [spel_h_perm16a]\n mova m17, [spel_h_perm16b]\n mova m18, [spel_h_perm16c]\n lea r6d, [wq*8-16*2*8+hq]\n mov r5, tmpq\n mov r7, srcq\n.hv_loop0:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym1, [srcq+strideq*0]\n vinserti32x8 m1, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n vinserti32x8 m2, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym3, [srcq+strideq*0]\n mova m4, m8\n mova m5, m8\n mova m6, m8\n mova m7, m8\n vpermb m19, m16, m0\n vpermb m20, m17, m0\n vpermb m21, m18, m0\n vpermb m22, m16, m1\n vpermb m23, m17, m1\n vpermb m24, m18, m1\n vpermb m25, m16, m2\n vpermb m26, m17, m2\n vpermb m27, m18, m2\n vpermb ym28, ym16, ym3\n vpermb ym29, ym17, ym3\n vpermb ym30, ym18, ym3\n mova m0, m8\n mova m1, m8\n mova ym2, ym8\n mova ym3, ym8\n vpdpbusd m4, m19, m10\n vpdpbusd m5, m20, m10\n vpdpbusd m6, m22, m10\n vpdpbusd m7, m23, m10\n vpdpbusd m0, m25, m10\n vpdpbusd m1, m26, m10\n vpdpbusd ym2, ym28, ym10\n vpdpbusd ym3, ym29, ym10\n vpdpbusd m4, m20, m11\n vpdpbusd m5, m21, m11\n vpdpbusd m6, m23, m11\n vpdpbusd m7, m24, m11\n vpdpbusd m0, m26, m11\n vpdpbusd m1, m27, m11\n vpdpbusd ym2, ym29, ym11\n vpdpbusd ym3, ym30, ym11\n packssdw m4, m5\n packssdw m6, m7\n packssdw m0, m1\n packssdw ym2, ym3\n psraw m4, 2 ; 0a 0b 1a 1b\n psraw m6, 2 ; 2a 2b 3a 3b\n psraw m0, 2 ; 4a 4b 5a 5b\n psraw ym2, 2 ; 6a 6b __ __\n vshufi32x4 m5, m4, m6, q1032 ; 1a 1b 2a 2b\n vshufi32x4 m7, m6, m0, q1032 ; 3a 3b 4a 4b\n vshufi32x4 m1, m0, m2, q1032 ; 5a 5b 6a 6b\n punpcklwd m2, m4, m5 ; 01a 01c 12a 12c\n punpckhwd m3, m4, m5 ; 01b 01d 12b 12d\n punpcklwd m4, m6, m7 ; 23a 23c 34a 34c\n punpckhwd m5, m6, m7 ; 23b 23d 34b 34d\n punpcklwd m6, m0, m1 ; 45a 45c 56a 56c\n punpckhwd m7, m0, m1 ; 45b 45d 56b 56d\n.hv_loop:\n movu ym19, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti32x8 m19, [srcq+strideq*0], 1\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m2, m12\n vpdpwssd m21, m3, m12\n vpdpwssd m20, m4, m13\n vpdpwssd m21, m5, m13\n vpermb m24, m16, m19\n vpermb m25, m17, m19\n vpermb m26, m18, m19\n vpdpbusd m22, m24, m10\n vpdpbusd m23, m25, m10\n vpdpbusd m22, m25, m11\n vpdpbusd m23, m26, m11\n packssdw m22, m23\n psraw m22, 2 ; 7a 7b 8a 8b\n vshufi32x4 m0, m1, m22, q1032 ; 6a 6b 7a 7b\n mova m2, m4\n mova m3, m5\n mova m1, m22\n mova m4, m6\n mova m5, m7\n punpcklwd m6, m0, m1 ; 67a 67c 78a 78c\n punpckhwd m7, m0, m1 ; 67b 67d 78b 78d\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq+wq*0], ym20\n vextracti32x8 [tmpq+wq*1], m20, 1\n lea tmpq, [tmpq+wq*2]\n sub hd, 2\n jg .hv_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_loop0\n%endif\n RET\n%endmacro\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro WRAP_YMM 1+\n INIT_YMM cpuname\n %1\n INIT_ZMM cpuname\n%endmacro\n\n%macro BIDIR_FN 1 ; op\n%if mmsize == 64\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM %1 0\n vextracti32x4 xmm1, ym0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_ret:\n RET\n.w4_h16:\n vpbroadcastd m7, strided\n pmulld m7, [bidir_sctr_w4]\n %1 0\n kxnorw k1, k1, k1\n vpscatterdd [dstq+m7]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM %1 0\n vextracti128 xmm1, ym0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n %1 0\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq ], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w16:\n %1 0\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m7, [warp_8x8_shufA]\n.w32_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m7, [warp_8x8_shufA]\n.w64_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m7, [warp_8x8_shufA]\n.w128_loop:\n %1 0\n vpermq m6, m7, m0\n %1 2\n mova [dstq+64*0], m6\n %1_INC_PTR 4\n vpermq m6, m7, m0\n mova [dstq+64*1], m6\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n%else\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endif\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\n%macro AVG_FN 0\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-avg %+ SUFFIX %+ _table\n lea r6, [avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [base+pw_1024]\n add wq, r6\n BIDIR_FN AVG\n%endmacro\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\n%macro W_AVG_FN 0\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-w_avg %+ SUFFIX %+ _table\n lea r6, [w_avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [base+pw_2048]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n%endmacro\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n%if mmsize == 64\n vpermq m3, m8, [maskq+%1*32]\n%else\n vpermq m3, [maskq+%1*16], q3120\n%endif\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp2q, %1*mmsize\n add tmp1q, %1*mmsize\n%endmacro\n\n%macro MASK_FN 0\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-mask %+ SUFFIX %+ _table\n lea r7, [mask %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n%if mmsize == 64\n mova m8, [base+bilin_v_perm64]\n%endif\n vpbroadcastd m5, [base+pw_2048]\n add wq, r7\n BIDIR_FN MASK\n%endmacro MASK_FN\n\n%macro W_MASK 4-5 0 ; dst, mask, tmp_offset[1-2], 4:4:4\n mova m%1, [tmp1q+mmsize*%3]\n mova m1, [tmp2q+mmsize*%3]\n psubw m1, m%1\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m%1, m1\n mova m1, [tmp1q+mmsize*%4]\n mova m2, [tmp2q+mmsize*%4]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n%if cpuflag(avx512icl)\n vpshldw m%2, m3, 8\n psllw m3, m%2, 10\n%if %5\n psubb m%2, m5, m%2\n%endif\n%else\n psrlw m3, 8\n%if %5\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n%endif\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m%1, m7\n pmulhrsw m1, m7\n packuswb m%1, m1\n%endmacro\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovs r10, yq\n test yq, yq\n cmovs r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovs r10, xq\n test xq, xq\n cmovs r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovs bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovs topextq, r12\n cmp bottomextq, bhq\n cmovns bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovs rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovs leftextq, r12\n cmp rightextq, bwq\n cmovns rightextq, r2\n cmp leftextq, bwq\n cmovns leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\nINIT_YMM avx2\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m9, [base+deint_shuf4]\n vpbroadcastd m8, [base+wm_420_sign+r6*4] ; 258 - sign\n add wq, r7\n W_MASK 0, 4, 0, 1\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 0, 5, 2, 3\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 0, 5, 2, 3\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 0, 5, 2, 3\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32*0], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK 0, 4, -4, -3\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 0, 5, -2, -1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32*1], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n vpbroadcastd m8, [base+wm_422_sign+r6*4] ; 128 - sign\n add wq, r7\n mov maskq, maskmp\n W_MASK 0, 4, 0, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 0, 5, 2, 3\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 0, 4, 4, 5\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 0, 5, 6, 7\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m5, [base+pb_64]\n vpbroadcastd m7, [base+pw_2048]\n add wq, r7\n W_MASK 0, 4, 0, 1, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 0, 4, 2, 3, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 0, 4, 2, 3, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 0, 4, 2, 3, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 0, 4, 4, 5, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 0, 4, 6, 7, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\nINIT_ZMM avx512icl\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\ncglobal w_mask_420, 4, 8, 16, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx512icl_table\n lea r7, [w_mask_420_avx512icl_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m9, [base+pb_m64] ; -1 << 6\n mova ym10, [base+wm_420_mask+32]\n vpbroadcastd m8, [base+wm_sign_avx512+r6*8] ; (258 - sign) << 6\n add wq, r7\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n mova m5, [wm_420_perm4]\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM W_MASK 0, 4, 0, 1\n vinserti128 ym5, [wm_420_perm4+32], 1\n vpermb ym4, ym5, ym4\n vpdpbusd ym8, ym4, ym9\n vextracti128 xmm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_end:\n vpermb ym8, ym10, ym8\n movq [maskq], xm8\n RET\n.w4_h16:\n vpbroadcastd m11, strided\n pmulld m11, [bidir_sctr_w4]\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n vpdpbusd m8, m4, m9\n kxnorw k1, k1, k1\n vpermb m8, m10, m8\n mova [maskq], xm8\n vpscatterdd [dstq+m11]{k1}, m0\n RET\n.w8:\n mova m5, [wm_420_perm8]\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM W_MASK 0, 4, 0, 1\n vinserti128 ym5, [wm_420_perm8+32], 1\n vpermb ym4, ym5, ym4\n vpdpbusd ym8, ym4, ym9\n vpermb m8, m10, m8\n mova [maskq], xm8\n vextracti128 xmm1, ym0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 16\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n mova m1, m8\n vpdpbusd m1, m4, m9\n vpermb m1, m10, m1\n mova [maskq], xm1\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq+strideq*0], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16:\n mova m5, [wm_420_perm16]\n.w16_loop:\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n mova m1, m8\n vpdpbusd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m0, q3120\n mova [maskq], xm1\n add maskq, 16\n mova [dstq+strideq*0], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n lea dstq, [dstq+strideq*4]\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m5, [warp_8x8_shufA]\n.w32_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpbusd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n mova [maskq], xm1\n add maskq, 16\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m12, [wm_420_perm64] ; 0, 2, 4, 6, 8, 10, 12, 14\n psrlq m13, m12, 4 ; 1, 3, 5, 7, 9, 11, 13, 15\n.w64_loop:\n W_MASK 0, 4, 0, 2\n W_MASK 11, 5, 1, 3\n mova m2, m8\n vpdpbusd m2, m4, m9\n mova m3, m8\n vpdpbusd m3, m5, m9\n add tmp1q, 256\n add tmp2q, 256\n vpermt2b m2, m10, m3\n mova m1, m0\n vpermt2q m0, m12, m11\n vpermt2q m1, m13, m11\n mova [maskq], ym2\n add maskq, 32\n mova [dstq+strideq*0], m0\n mova [dstq+strideq*1], m1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m14, [wm_420_perm64]\n mova m10, [wm_420_mask]\n psrlq m15, m14, 4\n.w128_loop:\n W_MASK 0, 12, 0, 4\n W_MASK 11, 13, 1, 5\n mova m4, m8\n vpdpbusd m4, m12, m9\n mova m5, m8\n vpdpbusd m5, m13, m9\n mova m1, m0\n vpermt2q m0, m14, m11\n vpermt2q m1, m15, m11\n mova [dstq+strideq*0+64*0], m0\n mova [dstq+strideq*1+64*0], m1\n W_MASK 0, 12, 2, 6\n W_MASK 11, 13, 3, 7\n vprold m4, 16\n vprold m5, 16\n vpdpbusd m4, m12, m9\n vpdpbusd m5, m13, m9\n add tmp1q, 512\n add tmp2q, 512\n vpermt2b m4, m10, m5\n mova m1, m0\n vpermt2q m0, m14, m11\n vpermt2q m1, m15, m11\n mova [maskq], m4\n add maskq, 64\n mova [dstq+strideq*0+64*1], m0\n mova [dstq+strideq*1+64*1], m1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx512icl_table\n lea r7, [w_mask_422_avx512icl_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m9, [base+pw_m128]\n mova m10, [base+wm_422_mask]\n vpbroadcastd m11, [base+pb_127]\n add wq, r7\n vpbroadcastd m8, [base+wm_sign_avx512+4+r6*4]\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM W_MASK 0, 4, 0, 1\n movhps xm10, [wm_422_mask+16]\n vpdpwssd ym8, ym4, ym9\n vpermb ym8, ym10, ym8\n vextracti128 xmm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_end:\n pand xm8, xm11\n mova [maskq], xm8\n RET\n.w4_h16:\n vpbroadcastd m5, strided\n pmulld m5, [bidir_sctr_w4]\n W_MASK 0, 4, 0, 1\n vpdpwssd m8, m4, m9\n kxnorw k1, k1, k1\n vpermb m8, m10, m8\n pand ym8, ym11\n mova [maskq], ym8\n vpscatterdd [dstq+m5]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM W_MASK 0, 4, 0, 1\n movhps xm10, [wm_422_mask+16]\n vpdpwssd ym8, ym4, ym9\n vpermb ym8, ym10, ym8\n pand xm8, xm11\n mova [maskq], xm8\n vextracti128 xmm1, ym0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 32\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n vpermb m1, m10, m1\n pand ym1, ym11\n mova [maskq], ym1\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq+strideq*0], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 32\n lea dstq, [dstq+strideq*4]\n.w16:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n vpermb m1, m10, m1\n vpermq m0, m0, q3120\n pand ym1, ym11\n mova [maskq], ym1\n mova [dstq+strideq*0], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m5, [warp_8x8_shufA]\n.w32_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n pand ym1, ym11\n mova [maskq], ym1\n add maskq, 32\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m5, [warp_8x8_shufA]\n.w64_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n pand ym1, ym11\n mova [maskq], ym1\n add maskq, 32\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m13, [warp_8x8_shufA]\n.w128_loop:\n W_MASK 0, 4, 0, 1\n W_MASK 12, 5, 2, 3\n mova m2, m8\n vpdpwssd m2, m4, m9\n mova m3, m8\n vpdpwssd m3, m5, m9\n add tmp1q, 256\n add tmp2q, 256\n vpermt2b m2, m10, m3\n vpermq m0, m13, m0\n vpermq m1, m13, m12\n pand m2, m11\n mova [maskq], m2\n add maskq, 64\n mova [dstq+64*0], m0\n mova [dstq+64*1], m1\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 12, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx512icl_table\n lea r7, [w_mask_444_avx512icl_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m5, [base+pb_64]\n vpbroadcastd m7, [base+pw_2048]\n mova m8, [base+wm_444_mask]\n add wq, r7\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM W_MASK 0, 4, 0, 1, 1\n vinserti128 ym8, [wm_444_mask+32], 1\n vpermb ym4, ym8, ym4\n mova [maskq], ym4\n vextracti128 xmm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_end:\n RET\n.w4_h16:\n vpbroadcastd m9, strided\n pmulld m9, [bidir_sctr_w4]\n W_MASK 0, 4, 0, 1, 1\n vpermb m4, m8, m4\n kxnorw k1, k1, k1\n mova [maskq], m4\n vpscatterdd [dstq+m9]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM W_MASK 0, 4, 0, 1, 1\n vinserti128 ym8, [wm_444_mask+32], 1\n vpermb ym4, ym8, ym4\n mova [maskq], ym4\n vextracti128 xmm1, ym0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 64\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n W_MASK 0, 4, 0, 1, 1\n vpermb m4, m8, m4\n mova [maskq], m4\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq+strideq*0], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 64\n lea dstq, [dstq+strideq*4]\n.w16:\n W_MASK 0, 4, 0, 1, 1\n vpermb m4, m8, m4\n vpermq m0, m0, q3120\n mova [maskq], m4\n mova [dstq+strideq*0], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m9, [warp_8x8_shufA]\n.w32_loop:\n W_MASK 0, 4, 0, 1, 1\n vpermb m4, m8, m4\n add tmp1q, 128\n add tmp2q, 128\n vpermq m0, m9, m0\n mova [maskq], m4\n add maskq, 64\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m9, [warp_8x8_shufA]\n.w64_loop:\n W_MASK 0, 4, 0, 1, 1\n vpermb m4, m8, m4\n add tmp1q, 128\n add tmp2q, 128\n vpermq m0, m9, m0\n mova [maskq], m4\n add maskq, 64\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m11, [warp_8x8_shufA]\n.w128_loop:\n W_MASK 0, 4, 0, 1, 1\n W_MASK 10, 9, 2, 3, 1\n vpermb m4, m8, m4\n vpermb m9, m8, m9\n add tmp1q, 256\n add tmp2q, 256\n vpermq m0, m11, m0\n vpermq m10, m11, m10\n mova [maskq+64*0], m4\n mova [maskq+64*1], m9\n add maskq, 128\n mova [dstq+64*0], m0\n mova [dstq+64*1], m10\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nbidir_sctr_w4: dd 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\nwm_420_perm4: db 1, 3, 9, 11, 5, 7, 13, 15, 17, 19, 25, 27, 21, 23, 29, 31\n db 33, 35, 41, 43, 37, 39, 45, 47, 49, 51, 57, 59, 53, 55, 61, 63\n db 0, 2, 8, 10, 4, 6, 12, 14, 16, 18, 24, 26, 20, 22, 28, 30\n db 32, 34, 40, 42, 36, 38, 44, 46, 48, 50, 56, 58, 52, 54, 60, 62\nwm_420_perm8: db 1, 3, 17, 19, 5, 7, 21, 23, 9, 11, 25, 27, 13, 15, 29, 31\n db 33, 35, 49, 51, 37, 39, 53, 55, 41, 43, 57, 59, 45, 47, 61, 63\n db 0, 2, 16, 18, 4, 6, 20, 22, 8, 10, 24, 26, 12, 14, 28, 30\n db 32, 34, 48, 50, 36, 38, 52, 54, 40, 42, 56, 58, 44, 46, 60, 62\nwm_420_perm16: db 1, 3, 33, 35, 5, 7, 37, 39, 9, 11, 41, 43, 13, 15, 45, 47\n db 17, 19, 49, 51, 21, 23, 53, 55, 25, 27, 57, 59, 29, 31, 61, 63\n db 0, 2, 32, 34, 4, 6, 36, 38, 8, 10, 40, 42, 12, 14, 44, 46\n db 16, 18, 48, 50, 20, 22, 52, 54, 24, 26, 56, 58, 28, 30, 60, 62\nwm_420_mask: db 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63\n db 67, 71, 75, 79, 83, 87, 91, 95, 99,103,107,111,115,119,123,127\n db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\n db 65, 69, 73, 77, 81, 85, 89, 93, 97,101,105,109,113,117,121,125\nwm_422_mask: db 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62\n db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\n db 66, 70, 74, 78, 82, 86, 90, 94, 98,102,106,110,114,118,122,126\n db 65, 69, 73, 77, 81, 85, 89, 93, 97,101,105,109,113,117,121,125\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\nspel_h_perm16a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\nspel_h_perm16b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 36, 37, 38, 39, 37, 38, 39, 40, 38, 39, 40, 41, 39, 40, 41, 42\n db 44, 45, 46, 47, 45, 46, 47, 48, 46, 47, 48, 49, 47, 48, 49, 50\nspel_h_perm16c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\n db 48, 49, 50, 51, 49, 50, 51, 52, 50, 51, 52, 53, 51, 52, 53, 54\nspel_h_perm32a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\nspel_h_perm32b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 20, 21, 22, 23, 21, 22, 23, 24, 22, 23, 24, 25, 23, 24, 25, 26\n db 28, 29, 30, 31, 29, 30, 31, 32, 30, 31, 32, 33, 31, 32, 33, 34\nspel_h_perm32c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\nspel_hv_perm4a: db 8, 9, 16, 17, 10, 11, 18, 19, 12, 13, 20, 21, 14, 15, 22, 23\n db 16, 17, 24, 25, 18, 19, 26, 27, 20, 21, 28, 29, 22, 23, 30, 31\nspel_hv_perm4b: db 24, 25, 32, 33, 26, 27, 34, 35, 28, 29, 36, 37, 30, 31, 38, 39\n db 32, 33, 40, 41, 34, 35, 42, 43, 36, 37, 44, 45, 38, 39, 46, 47\n db 40, 41, 48, 49, 42, 43, 50, 51, 44, 45, 52, 53, 46, 47, 54, 55\n db 48, 49, 56, 57, 50, 51, 58, 59, 52, 53, 60, 61, 54, 55, 62, 63\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_v_shuf4: db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\nwm_420_perm64: dq 0xfedcba9876543210\nwm_420_sign: dd 0x01020102, 0x01010101\nwm_422_sign: dd 0x80808080, 0x7f7f7f7f\nwm_sign_avx512: dd 0x40804080, 0xc0c0c0c0, 0x40404040\n\npw_m128 times 2 dw -128\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_2: dd 2\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\n%define pb_m64 (wm_sign_avx512+4)\n%define pb_64 (wm_sign_avx512+8)\n%define pb_127 (wm_422_sign +4)\n\ncextern mc_subpel_filters\ncextern mc_warp_filter\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx512icl, 7, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx512icl, 4, 8, 16, 32, 64, 128\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro PREP_8TAP_H 0\n %if cpuflag(avx512)\n vpermb m10, m5, m0\n vpermb m11, m5, m1\n vpermb m12, m6, m0\n vpermb m13, m6, m1\n vpermb m14, m7, m0\n vpermb m15, m7, m1\n mova m0, m4\n mova m2, m4\n mova m1, m4\n mova m3, m4\n vpdpbusd m0, m10, m8\n vpdpbusd m2, m12, m8\n vpdpbusd m1, m11, m8\n vpdpbusd m3, m13, m8\n vpdpbusd m0, m12, m9\n vpdpbusd m2, m14, m9\n vpdpbusd m1, m13, m9\n vpdpbusd m3, m15, m9\n packssdw m0, m2\n packssdw m1, m3\n psraw m0, 2\n psraw m1, 2\n mova [tmpq+ 0], m0\n mova [tmpq+64], m1\n %else\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n pmaddubsw m1, m8\n pmaddubsw m0, m2, m8\n pmaddubsw m2, m9\n pmaddubsw m3, m9\n paddw m1, m2\n paddw m0, m3\n phaddw m0, m1, m0\n pmulhrsw m0, m4\n %endif\n%endmacro\n\n%macro PREP_8TAP_V_W4 5 ; round, weights\n movd xm0, [srcq+strideq*0]\n vpbroadcastd ym1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd ym3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd ym1, ym1, ym0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd ym3, ym3, ym2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd ym0, [srcq+strideq*0]\n vpbroadcastd ym2, [srcq+strideq*1]\n vpblendd ym1, ym1, ym0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd ym0, [srcq+strideq*2]\n vbroadcasti128 ym5, [deint_shuf4]\n vpblendd ym3, ym3, ym2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd ym2, ym3, ym1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd ym3, ym3, ym1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw ym1, ym2, ym3 ; 01 12 23 34\n vpblendd ym3, ym3, ym0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw ym2, ym3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym3, [srcq+strideq*0]\n vpbroadcastd ym4, [srcq+strideq*1]\n vpblendd ym3, ym3, ym4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd ym3, ym3, ym0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd ym0, [srcq+strideq*2]\n vpblendd ym3, ym3, ym0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb ym3, ym5 ; 67 78 89 9a\n pmaddubsw ym4, ym1, ym%2\n vperm2i128 ym1, ym2, ym3, 0x21 ; 45 56 67 78\n pmaddubsw ym2, ym%3\n paddw ym4, ym2\n mova ym2, ym3\n pmaddubsw ym3, ym%5\n paddw ym3, ym4\n pmaddubsw ym4, ym1, ym%4\n paddw ym3, ym4\n pmulhrsw ym3, ym%1\n mova [tmpq], ym3\n%endmacro\n\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\n%macro PREP_8TAP 0\n %if WIN64\n DECLARE_REG_TMP 6, 4\n %else\n DECLARE_REG_TMP 6, 7\n %endif\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep%+SUFFIX]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n%if cpuflag(avx512)\n vpbroadcastd m4, [pd_2]\n%else\n vpbroadcastd m4, [pw_8192]\n vbroadcasti128 m5, [subpel_h_shufA]\n%endif\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n%if notcpuflag(avx512)\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n%endif\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n add wq, r7\n jmp wq\n.h_w4:\n%if cpuflag(avx512)\n mov r3d, 0x4\n kmovb k1, r3d\n vbroadcasti128 ym5, [subpel_h_shufA]\n%endif\n movzx mxd, mxb\n dec srcq\n vpbroadcastd ym6, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n%if cpuflag(avx512icl)\n mova ym0, ym4\n mova ym1, ym4\n movq xm2, [srcq+strideq*0]\n movq xm3, [srcq+strideq*1]\n vpbroadcastq ym2{k1}, [srcq+strideq*2]\n vpbroadcastq ym3{k1}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pshufb ym2, ym5\n pshufb ym3, ym5\n vpdpbusd ym0, ym2, ym6\n vpdpbusd ym1, ym3, ym6\n packssdw ym0, ym1\n psraw ym0, 2\n%else\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m6\n pmaddubsw m1, m6\n phaddw m0, m1\n pmulhrsw m0, m4\n%endif\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m5, [subpel_h_shufA]\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n lea stride3q, [strideq*3]\n%endif\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n%if cpuflag(avx512)\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n%endif\n lea srcq, [srcq+strideq*(mmsize/(8*2))]\n%if cpuflag(avx512icl)\n mova m10, m4\n mova m11, m4\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n vpdpbusd m10, m1, m8\n vpdpbusd m11, m2, m8\n vpdpbusd m10, m2, m9\n vpdpbusd m11, m3, m9\n packssdw m10, m11\n psraw m0, m10, 2\n%else\n PREP_8TAP_H\n%endif\n mova [tmpq], m0\n add tmpq, mmsize\n sub hd, mmsize/(8*2)\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm16a]\n mova m6, [spel_h_perm16b]\n mova m7, [spel_h_perm16c]\n lea stride3q, [strideq*3]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m0, [srcq+strideq*1], 1\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n PREP_8TAP_H\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n.h_w32_loop:\n movu m0, [srcq+strideq*0]\n movu m1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n add tmpq, 64*2\n sub hd, 2\n jg .h_w32_loop\n RET\n%else\n xor r6d, r6d\n jmp .h_start\n%endif\n.h_w64:\n%if cpuflag(avx512)\n xor r6d, r6d\n%else\n mov r6, -32*1\n%endif\n jmp .h_start\n.h_w128:\n%if cpuflag(avx512)\n mov r6, -64*1\n%else\n mov r6, -32*3\n%endif\n.h_start:\n%if cpuflag(avx512)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n%endif\n sub srcq, r6\n mov r5, r6\n.h_loop:\n%if cpuflag(avx512icl)\n movu m0, [srcq+r6+32*0]\n movu m1, [srcq+r6+32*1]\n PREP_8TAP_H\n%else\n movu xm0, [srcq+r6+8*0]\n vinserti128 ym0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 ym0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n add r6, mmsize\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n%if cpuflag(avx512)\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_v)]\n add wq, r7\n%endif\n lea myq, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n vpbroadcastd m7, [pw_8192]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n%if cpuflag(avx512)\n jmp wq\n%else\n cmp wd, 8\n jg .v_w16\n je .v_w8\n%endif\n.v_w4:\n%if cpuflag(avx512)\n AVX512_MM_PERMUTATION\n PREP_8TAP_V_W4 23, 24, 25, 26, 27\n AVX512_MM_PERMUTATION\n%else\n PREP_8TAP_V_W4 7, 8, 9, 10, 11\n%endif\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.v_w8:\n%if cpuflag(avx512)\n mov r3d, 0xf044\n kmovw k1, r3d\n kshiftrw k2, k1, 8\n movq xm0, [srcq+strideq*0]\n vpbroadcastq ym1, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vmovdqa64 ym0{k1}, ym1\n vmovdqa64 ym1{k1}, ym2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n punpcklbw ym0, ym1 ; 01 12 __ __\n punpcklbw m2, m3 ; 23 34 23 34\n punpcklbw m4, m5 ; 45 56 45 56\n vmovdqa64 m0{k2}, m2 ; 01 12 23 34\n vmovdqa64 m2{k2}, m4 ; 23 34 45 56\n.v_w8_loop:\n vpbroadcastq m1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n pmaddubsw m14, m0, m8\n pmaddubsw m15, m2, m9\n vpblendmq m0{k1}, m6, m1\n vpblendmq m2{k1}, m1, m3\n vpbroadcastq m6, [srcq+strideq*2]\n paddw m14, m15\n punpcklbw m2, m0, m2 ; 67 78 67 78\n vpblendmq m12{k1}, m3, m5\n vpblendmq m13{k1}, m5, m6\n vpblendmq m0{k2}, m4, m2 ; 45 56 67 78\n punpcklbw m4, m12, m13 ; 89 9a 89 9a\n vmovdqa64 m2{k2}, m4 ; 67 78 89 9a\n pmaddubsw m12, m0, m10\n pmaddubsw m13, m2, m11\n paddw m14, m12\n paddw m14, m13\n pmulhrsw m14, m7\n mova [tmpq], m14\n%else\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512)\n mov r3d, 0xf0\n kmovb k1, r3d\n vbroadcasti128 m0, [srcq+strideq*0]\n vbroadcasti128 m1, [srcq+strideq*1]\n vbroadcasti128 m2, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n vmovdqa64 m0{k1}, m1\n vmovdqa64 m1{k1}, m2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n shufpd m0, m2, 0xcc ; 0a_2a 0b_2b 1a_3a 1b_3b\n shufpd m1, m3, 0xcc ; 1a_3a 1b_3b 2a_4a 2b_4b\n shufpd m4, m4, 0x44 ; 4a_-- 4b_-- 5a_-- 5b_--\n shufpd m5, m5, 0x44 ; 5a_-- 5b_-- 6a_-- 6b_--\n punpckhbw m2, m0, m1 ; 23a 23b 34a 34b\n punpcklbw m0, m1 ; 01a 01b 12a 12b\n punpcklbw m4, m5 ; 45a 45b 56a 56b\n.v_w16_loop:\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m5, [srcq+strideq*0]\n vpblendmq m1{k1}, m6, m3\n vmovdqa64 m3{k1}, m5\n pmaddubsw m12, m0, m8\n pmaddubsw m13, m2, m8\n pmaddubsw m14, m2, m9\n pmaddubsw m15, m4, m9\n pmaddubsw m0, m4, m10\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n paddw m12, m14\n paddw m13, m15\n paddw m12, m0\n vmovdqa64 m5{k1}, m2\n vmovdqa64 m2{k1}, m6\n mova m0, m4\n shufpd m1, m5, 0xcc ; 6a_8a 6b_8b 7a_9a 7b_9b\n shufpd m3, m2, 0xcc ; 7a_9a 7b_9b 8a_Aa 8b_Ab\n punpcklbw m2, m1, m3 ; 67a 67b 78a 78b\n punpckhbw m4, m1, m3 ; 89a 89b 9Aa 9Ab\n pmaddubsw m14, m2, m10\n pmaddubsw m15, m2, m11\n paddw m13, m14\n paddw m12, m15\n pmaddubsw m14, m4, m11\n paddw m13, m14\n pmulhrsw m12, m7\n pmulhrsw m13, m7\n mova [tmpq+ 0], m12\n mova [tmpq+64], m13\n add tmpq, 64*2\n sub hd, 4\n jg .v_w16_loop\n%else\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n%endif\n RET\n%if cpuflag(avx512)\n.v_w32:\n mova m18, [bilin_v_perm64]\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n movu ym3, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym4, [srcq+strideq*0]\n movu ym5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym6, [srcq+strideq*0]\n vpermq m0, m18, m0\n vpermq m1, m18, m1\n vpermq m2, m18, m2\n vpermq m3, m18, m3\n vpermq m4, m18, m4\n vpermq m5, m18, m5\n vpermq m6, m18, m6\n punpcklbw m0, m1\n punpcklbw m1, m2\n punpcklbw m2, m3\n punpcklbw m3, m4\n punpcklbw m4, m5\n punpcklbw m5, m6\n.v_w32_loop:\n movu ym12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym13, [srcq+strideq*0]\n pmaddubsw m14, m0, m8\n pmaddubsw m16, m2, m9\n pmaddubsw m15, m1, m8\n pmaddubsw m17, m3, m9\n mova m0, m2\n mova m1, m3\n vpermq m12, m18, m12\n vpermq m13, m18, m13\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m4, m10\n pmaddubsw m17, m5, m10\n punpcklbw m6, m12\n punpcklbw m12, m13\n mova m2, m4\n mova m3, m5\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m6, m11\n pmaddubsw m17, m12, m11\n mova m4, m6\n mova m5, m12\n paddw m14, m16\n paddw m15, m17\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova m6, m13\n mova [tmpq+ 0], m14\n mova [tmpq+64], m15\n add tmpq, 64*2\n sub hd, 2\n jg .v_w32_loop\n vzeroupper\n RET\n.v_w64:\n mov r6d, hd\n mov wd, 64\n jmp .v_start\n.v_w128:\n lea r6d, [(1<<8)+hq]\n mov wd, 128\n.v_start:\n WIN64_SPILL_XMM 27\n mova m26, [bilin_v_perm64]\n mov r5, tmpq\n mov r7, srcq\n.v_loop0:\n vpermq m0, m26, [srcq+strideq*0]\n vpermq m1, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m2, m26, [srcq+strideq*0]\n vpermq m3, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m4, m26, [srcq+strideq*0]\n vpermq m5, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m6, m26, [srcq+strideq*0]\n punpckhbw m12, m0, m1\n punpcklbw m0, m1\n punpckhbw m13, m1, m2\n punpcklbw m1, m2\n punpckhbw m14, m2, m3\n punpcklbw m2, m3\n punpckhbw m15, m3, m4\n punpcklbw m3, m4\n punpckhbw m16, m4, m5\n punpcklbw m4, m5\n punpckhbw m17, m5, m6\n punpcklbw m5, m6\n.v_loop:\n vpermq m18, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m19, m26, [srcq+strideq*0]\n pmaddubsw m20, m0, m8\n pmaddubsw m21, m12, m8\n pmaddubsw m22, m1, m8\n pmaddubsw m23, m13, m8\n mova m0, m2\n mova m12, m14\n mova m1, m3\n mova m13, m15\n pmaddubsw m2, m9\n pmaddubsw m14, m9\n pmaddubsw m3, m9\n pmaddubsw m15, m9\n punpckhbw m24, m6, m18\n punpcklbw m6, m18\n paddw m20, m2\n paddw m21, m14\n paddw m22, m3\n paddw m23, m15\n mova m2, m4\n mova m14, m16\n mova m3, m5\n mova m15, m17\n pmaddubsw m4, m10\n pmaddubsw m16, m10\n pmaddubsw m5, m10\n pmaddubsw m17, m10\n punpckhbw m25, m18, m19\n punpcklbw m18, m19\n paddw m20, m4\n paddw m21, m16\n paddw m22, m5\n paddw m23, m17\n mova m4, m6\n mova m16, m24\n mova m5, m18\n mova m17, m25\n pmaddubsw m6, m11\n pmaddubsw m24, m11\n pmaddubsw m18, m11\n pmaddubsw m25, m11\n paddw m20, m6\n paddw m21, m24\n paddw m22, m18\n paddw m23, m25\n pmulhrsw m20, m7\n pmulhrsw m21, m7\n pmulhrsw m22, m7\n pmulhrsw m23, m7\n mova m6, m19\n mova [tmpq+wq*0+ 0], m20\n mova [tmpq+wq*0+64], m21\n mova [tmpq+wq*2+ 0], m22\n mova [tmpq+wq*2+64], m23\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_loop\n movzx hd, r6b\n add r5, 64*2\n add r7, 64\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_loop0\n%endif\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n %assign stack_size_padded 0\n WIN64_SPILL_XMM 16\n cmp wd, 4\n je .hv_w4\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n%if cpuflag(avx512)\n tzcnt wd, wd\n vpbroadcastd m8, [pd_2]\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_hv)]\n vpbroadcastd m9, [pd_32]\n add wq, r7\n%endif\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512)\n jmp wq\n%else\n jmp .hv_w8\n%endif\n.hv_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n%if cpuflag(avx512)\n mov r3d, 0x04\n kmovb k1, r3d\n kshiftlb k2, k1, 2\n kshiftlb k3, k1, 4\n vpbroadcastd m10, [pd_2]\n vbroadcasti128 m16, [subpel_h_shufA]\n%else\n mova m7, [subpel_h_shuf4]\n pmovzxbd m9, [deint_shuf4]\n vpbroadcastd m10, [pw_8192]\n%endif\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512icl)\n movq xm3, [srcq+strideq*0]\n vpbroadcastq ym2, [srcq+strideq*1]\n vpbroadcastq ym3{k1}, [srcq+strideq*2]\n vpbroadcastq m2{k2}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3{k2}, [srcq+strideq*0]\n vpbroadcastq m2{k3}, [srcq+strideq*1]\n vpbroadcastq m3{k3}, [srcq+strideq*2]\n mova m17, [spel_hv_perm4a]\n movu m18, [spel_hv_perm4b]\n mova m0, m10\n mova m1, m10\n pshufb m2, m16\n pshufb m3, m16\n vpdpbusd m0, m2, m8\n vpdpbusd m1, m3, m8\n packssdw m0, m1 ; _ 0 1 2 3 4 5 6\n psraw m0, 2\n vpermb m1, m17, m0 ; 01 12 23 34\n vpermb m2, m18, m0 ; 23 34 45 56\n.hv_w4_loop:\n movq xm3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movq xm4, [srcq+strideq*0]\n vpbroadcastq ym3{k1}, [srcq+strideq*1]\n vpbroadcastq ym4{k1}, [srcq+strideq*2]\n mova ym5, ym10\n mova ym6, ym10\n pshufb ym3, ym16\n pshufb ym4, ym16\n vpdpbusd ym5, ym3, ym8\n vpdpbusd ym6, ym4, ym8\n mova m7, m11\n packssdw ym5, ym6 ; 7 8 9 a _ _ _ _\n psraw ym5, 2\n valignq m0, m5, m0, 4 ; _ 4 5 6 7 8 9 a\n vpdpwssd m7, m1, m12\n vpdpwssd m7, m2, m13\n vpermb m1, m17, m0 ; 45 56 67 78\n vpermb m2, m18, m0 ; 67 78 89 9a\n vpdpwssd m7, m1, m14\n vpdpwssd m7, m2, m15\n psrad m7, 6\n vpmovdw [tmpq], m7\n%else\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7 ; 00 01 10 11 02 03 12 13\n pshufb m0, m7 ; 20 21 30 31 22 23 32 33\n pshufb m3, m7 ; 40 41 50 51 42 43 52 53\n pshufb m1, m7 ; 60 61 60 61 62 63 62 63\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0 ; 0a 1a 2a 3a 0b 1b 2b 3b\n phaddw m3, m1 ; 4a 5a 6a __ 4b 5b 6b __\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4 ; 1a 2a 3a 4a 1b 2b 3b 4b\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n%endif\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.hv_w8:\n%if cpuflag(avx512icl)\n WIN64_SPILL_XMM 24\n vbroadcasti128 m16, [subpel_h_shufA]\n vbroadcasti128 m17, [subpel_h_shufB]\n vbroadcasti128 m18, [subpel_h_shufC]\n vinserti128 ym0, [srcq+strideq*0], 1\n vinserti128 m0, [srcq+strideq*1], 2\n vinserti128 m0, [srcq+strideq*2], 3\n movu xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym1, [srcq+strideq*0], 1\n vinserti128 m1, [srcq+strideq*1], 2\n vinserti128 m1, [srcq+strideq*2], 3\n mova m2, m8\n mova m4, m8\n mova m3, m8\n mova m5, m8\n pshufb m20, m0, m16\n pshufb m21, m0, m17\n pshufb m22, m0, m18\n pshufb m23, m1, m16\n pshufb m6, m1, m17\n pshufb m7, m1, m18\n vpdpbusd m2, m20, m10\n vpdpbusd m4, m21, m10\n vpdpbusd m2, m21, m11\n vpdpbusd m4, m22, m11\n vpdpbusd m3, m23, m10\n vpdpbusd m5, m6, m10\n vpdpbusd m3, m6, m11\n vpdpbusd m5, m7, m11\n packssdw m2, m4\n packssdw m3, m5\n psraw m2, 2 ; _ 0 1 2\n psraw m3, 2 ; 3 4 5 6\n valignq m0, m3, m2, 2 ; 0 1 2 3\n valignq m1, m3, m2, 4 ; 1 2 3 4\n valignq m2, m3, m2, 6 ; 2 3 4 5\n punpcklwd m4, m0, m1 ; 01a 12a 23a 34a\n punpckhwd m5, m0, m1 ; 01b 12b 23b 34b\n punpcklwd m6, m2, m3 ; 23a 34a 45a 56a\n punpckhwd m7, m2, m3 ; 23b 34b 45b 56b\n.hv_w8_loop:\n movu xm19, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym19, [srcq+strideq*0], 1\n vinserti128 m19, [srcq+strideq*1], 2\n vinserti128 m19, [srcq+strideq*2], 3\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m4, m12\n vpdpwssd m21, m5, m12\n vpdpwssd m20, m6, m13\n vpdpwssd m21, m7, m13\n pshufb m0, m19, m16\n pshufb m1, m19, m17\n pshufb m2, m19, m18\n vpdpbusd m22, m0, m10\n vpdpbusd m23, m1, m10\n vpdpbusd m22, m1, m11\n vpdpbusd m23, m2, m11\n packssdw m22, m23\n psraw m22, 2 ; 7 8 9 A\n valignq m0, m22, m3, 2 ; 4 5 6 7\n valignq m1, m22, m3, 4 ; 5 6 7 8\n valignq m2, m22, m3, 6 ; 6 7 8 9\n mova m3, m22\n punpcklwd m4, m0, m1 ; 45a 56a 67a 78a\n punpckhwd m5, m0, m1 ; 45b 56b 67b 78b\n punpcklwd m6, m2, m3 ; 67a 78a 89a 9Aa\n punpckhwd m7, m2, m3 ; 67b 78b 89b 9Ab\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq], m20\n add tmpq, 64\n sub hd, 4\n jg .hv_w8_loop\n%else\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n%endif\n RET\n%if cpuflag(avx512icl)\n.hv_w16:\n mov wd, 16*2\n jmp .hv_start\n.hv_w32:\n mov wd, 32*2\n jmp .hv_start\n.hv_w64:\n mov wd, 64*2\n jmp .hv_start\n.hv_w128:\n mov wd, 128*2\n.hv_start:\n WIN64_SPILL_XMM 31\n mova m16, [spel_h_perm16a]\n mova m17, [spel_h_perm16b]\n mova m18, [spel_h_perm16c]\n lea r6d, [wq*8-16*2*8+hq]\n mov r5, tmpq\n mov r7, srcq\n.hv_loop0:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym1, [srcq+strideq*0]\n vinserti32x8 m1, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n vinserti32x8 m2, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym3, [srcq+strideq*0]\n mova m4, m8\n mova m5, m8\n mova m6, m8\n mova m7, m8\n vpermb m19, m16, m0\n vpermb m20, m17, m0\n vpermb m21, m18, m0\n vpermb m22, m16, m1\n vpermb m23, m17, m1\n vpermb m24, m18, m1\n vpermb m25, m16, m2\n vpermb m26, m17, m2\n vpermb m27, m18, m2\n vpermb ym28, ym16, ym3\n vpermb ym29, ym17, ym3\n vpermb ym30, ym18, ym3\n mova m0, m8\n mova m1, m8\n mova ym2, ym8\n mova ym3, ym8\n vpdpbusd m4, m19, m10\n vpdpbusd m5, m20, m10\n vpdpbusd m6, m22, m10\n vpdpbusd m7, m23, m10\n vpdpbusd m0, m25, m10\n vpdpbusd m1, m26, m10\n vpdpbusd ym2, ym28, ym10\n vpdpbusd ym3, ym29, ym10\n vpdpbusd m4, m20, m11\n vpdpbusd m5, m21, m11\n vpdpbusd m6, m23, m11\n vpdpbusd m7, m24, m11\n vpdpbusd m0, m26, m11\n vpdpbusd m1, m27, m11\n vpdpbusd ym2, ym29, ym11\n vpdpbusd ym3, ym30, ym11\n packssdw m4, m5\n packssdw m6, m7\n packssdw m0, m1\n packssdw ym2, ym3\n psraw m4, 2 ; 0a 0b 1a 1b\n psraw m6, 2 ; 2a 2b 3a 3b\n psraw m0, 2 ; 4a 4b 5a 5b\n psraw ym2, 2 ; 6a 6b __ __\n vshufi32x4 m5, m4, m6, q1032 ; 1a 1b 2a 2b\n vshufi32x4 m7, m6, m0, q1032 ; 3a 3b 4a 4b\n vshufi32x4 m1, m0, m2, q1032 ; 5a 5b 6a 6b\n punpcklwd m2, m4, m5 ; 01a 01c 12a 12c\n punpckhwd m3, m4, m5 ; 01b 01d 12b 12d\n punpcklwd m4, m6, m7 ; 23a 23c 34a 34c\n punpckhwd m5, m6, m7 ; 23b 23d 34b 34d\n punpcklwd m6, m0, m1 ; 45a 45c 56a 56c\n punpckhwd m7, m0, m1 ; 45b 45d 56b 56d\n.hv_loop:\n movu ym19, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti32x8 m19, [srcq+strideq*0], 1\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m2, m12\n vpdpwssd m21, m3, m12\n vpdpwssd m20, m4, m13\n vpdpwssd m21, m5, m13\n vpermb m24, m16, m19\n vpermb m25, m17, m19\n vpermb m26, m18, m19\n vpdpbusd m22, m24, m10\n vpdpbusd m23, m25, m10\n vpdpbusd m22, m25, m11\n vpdpbusd m23, m26, m11\n packssdw m22, m23\n psraw m22, 2 ; 7a 7b 8a 8b\n vshufi32x4 m0, m1, m22, q1032 ; 6a 6b 7a 7b\n mova m2, m4\n mova m3, m5\n mova m1, m22\n mova m4, m6\n mova m5, m7\n punpcklwd m6, m0, m1 ; 67a 67c 78a 78c\n punpckhwd m7, m0, m1 ; 67b 67d 78b 78d\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq+wq*0], ym20\n vextracti32x8 [tmpq+wq*1], m20, 1\n lea tmpq, [tmpq+wq*2]\n sub hd, 2\n jg .hv_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_loop0\n%endif\n RET\n%endmacro\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro WRAP_YMM 1+\n INIT_YMM cpuname\n %1\n INIT_ZMM cpuname\n%endmacro\n\n%macro BIDIR_FN 1 ; op\n%if mmsize == 64\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM %1 0\n vextracti32x4 xmm1, ym0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_ret:\n RET\n.w4_h16:\n vpbroadcastd m7, strided\n pmulld m7, [bidir_sctr_w4]\n %1 0\n kxnorw k1, k1, k1\n vpscatterdd [dstq+m7]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM %1 0\n vextracti128 xmm1, ym0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n %1 0\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq ], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w16:\n %1 0\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m7, [warp_8x8_shufA]\n.w32_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m7, [warp_8x8_shufA]\n.w64_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m7, [warp_8x8_shufA]\n.w128_loop:\n %1 0\n vpermq m6, m7, m0\n %1 2\n mova [dstq+64*0], m6\n %1_INC_PTR 4\n vpermq m6, m7, m0\n mova [dstq+64*1], m6\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n%else\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endif\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\n%macro AVG_FN 0\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-avg %+ SUFFIX %+ _table\n lea r6, [avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [base+pw_1024]\n add wq, r6\n BIDIR_FN AVG\n%endmacro\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\n%macro W_AVG_FN 0\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-w_avg %+ SUFFIX %+ _table\n lea r6, [w_avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [base+pw_2048]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n%endmacro\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n%if mmsize == 64\n vpermq m3, m8, [maskq+%1*32]\n%else\n vpermq m3, [maskq+%1*16], q3120\n%endif\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp2q, %1*mmsize\n add tmp1q, %1*mmsize\n%endmacro\n\n%macro MASK_FN 0\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-mask %+ SUFFIX %+ _table\n lea r7, [mask %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n%if mmsize == 64\n mova m8, [base+bilin_v_perm64]\n%endif\n vpbroadcastd m5, [base+pw_2048]\n add wq, r7\n BIDIR_FN MASK\n%endmacro MASK_FN\n\n%macro W_MASK 4-5 0 ; dst, mask, tmp_offset[1-2], 4:4:4\n mova m%1, [tmp1q+mmsize*%3]\n mova m1, [tmp2q+mmsize*%3]\n psubw m1, m%1\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m%1, m1\n mova m1, [tmp1q+mmsize*%4]\n mova m2, [tmp2q+mmsize*%4]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n%if cpuflag(avx512icl)\n vpshldw m%2, m3, 8\n psllw m3, m%2, 10\n%else\n psrlw m3, 8\n%if %5\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n%endif\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m%1, m7\n pmulhrsw m1, m7\n packuswb m%1, m1\n%endmacro\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 0, 1, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 0, 4, 2, 3, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 0, 4, 2, 3, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 0, 4, 2, 3, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 0, 4, 4, 5, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 0, 4, 6, 7, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovs r10, yq\n test yq, yq\n cmovs r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovs r10, xq\n test xq, xq\n cmovs r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovs bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovs topextq, r12\n cmp bottomextq, bhq\n cmovns bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovs rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovs leftextq, r12\n cmp rightextq, bwq\n cmovns rightextq, r2\n cmp leftextq, bwq\n cmovns leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\nINIT_YMM avx2\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m9, [base+deint_shuf4]\n vpbroadcastd m8, [base+wm_420_sign+r6*4] ; 258 - sign\n add wq, r7\n W_MASK 0, 4, 0, 1\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 0, 5, 2, 3\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 0, 5, 2, 3\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 0, 5, 2, 3\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32*0], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK 0, 4, -4, -3\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 0, 5, -2, -1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32*1], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n vpbroadcastd m8, [base+wm_422_sign+r6*4] ; 128 - sign\n add wq, r7\n mov maskq, maskmp\n W_MASK 0, 4, 0, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 0, 5, 2, 3\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 0, 4, 4, 5\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 0, 5, 6, 7\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\nINIT_ZMM avx512icl\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\ncglobal w_mask_420, 4, 8, 16, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx512icl_table\n lea r7, [w_mask_420_avx512icl_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m9, [base+pb_m64] ; -1 << 6\n mova ym10, [base+wm_420_mask+32]\n vpbroadcastd m8, [base+wm_sign_avx512+r6*8] ; (258 - sign) << 6\n add wq, r7\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n mova m5, [wm_420_perm4]\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM W_MASK 0, 4, 0, 1\n vinserti128 ym5, [wm_420_perm4+32], 1\n vpermb ym4, ym5, ym4\n vpdpbusd ym8, ym4, ym9\n vextracti128 xmm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_end:\n vpermb ym8, ym10, ym8\n movq [maskq], xm8\n RET\n.w4_h16:\n vpbroadcastd m11, strided\n pmulld m11, [bidir_sctr_w4]\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n vpdpbusd m8, m4, m9\n kxnorw k1, k1, k1\n vpermb m8, m10, m8\n mova [maskq], xm8\n vpscatterdd [dstq+m11]{k1}, m0\n RET\n.w8:\n mova m5, [wm_420_perm8]\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM W_MASK 0, 4, 0, 1\n vinserti128 ym5, [wm_420_perm8+32], 1\n vpermb ym4, ym5, ym4\n vpdpbusd ym8, ym4, ym9\n vpermb m8, m10, m8\n mova [maskq], xm8\n vextracti128 xmm1, ym0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 16\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n mova m1, m8\n vpdpbusd m1, m4, m9\n vpermb m1, m10, m1\n mova [maskq], xm1\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq+strideq*0], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16:\n mova m5, [wm_420_perm16]\n.w16_loop:\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n mova m1, m8\n vpdpbusd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m0, q3120\n mova [maskq], xm1\n add maskq, 16\n mova [dstq+strideq*0], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n lea dstq, [dstq+strideq*4]\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m5, [warp_8x8_shufA]\n.w32_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpbusd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n mova [maskq], xm1\n add maskq, 16\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m12, [wm_420_perm64] ; 0, 2, 4, 6, 8, 10, 12, 14\n psrlq m13, m12, 4 ; 1, 3, 5, 7, 9, 11, 13, 15\n.w64_loop:\n W_MASK 0, 4, 0, 2\n W_MASK 11, 5, 1, 3\n mova m2, m8\n vpdpbusd m2, m4, m9\n mova m3, m8\n vpdpbusd m3, m5, m9\n add tmp1q, 256\n add tmp2q, 256\n vpermt2b m2, m10, m3\n mova m1, m0\n vpermt2q m0, m12, m11\n vpermt2q m1, m13, m11\n mova [maskq], ym2\n add maskq, 32\n mova [dstq+strideq*0], m0\n mova [dstq+strideq*1], m1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m14, [wm_420_perm64]\n mova m10, [wm_420_mask]\n psrlq m15, m14, 4\n.w128_loop:\n W_MASK 0, 12, 0, 4\n W_MASK 11, 13, 1, 5\n mova m4, m8\n vpdpbusd m4, m12, m9\n mova m5, m8\n vpdpbusd m5, m13, m9\n mova m1, m0\n vpermt2q m0, m14, m11\n vpermt2q m1, m15, m11\n mova [dstq+strideq*0+64*0], m0\n mova [dstq+strideq*1+64*0], m1\n W_MASK 0, 12, 2, 6\n W_MASK 11, 13, 3, 7\n vprold m4, 16\n vprold m5, 16\n vpdpbusd m4, m12, m9\n vpdpbusd m5, m13, m9\n add tmp1q, 512\n add tmp2q, 512\n vpermt2b m4, m10, m5\n mova m1, m0\n vpermt2q m0, m14, m11\n vpermt2q m1, m15, m11\n mova [maskq], m4\n add maskq, 64\n mova [dstq+strideq*0+64*1], m0\n mova [dstq+strideq*1+64*1], m1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx512icl_table\n lea r7, [w_mask_422_avx512icl_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m9, [base+pw_m128]\n mova m10, [base+wm_422_mask]\n vpbroadcastd m11, [base+pb_127]\n add wq, r7\n vpbroadcastd m8, [base+wm_sign_avx512+4+r6*4]\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM W_MASK 0, 4, 0, 1\n movhps xm10, [wm_422_mask+16]\n vpdpwssd ym8, ym4, ym9\n vpermb ym8, ym10, ym8\n vextracti128 xmm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_end:\n pand xm8, xm11\n mova [maskq], xm8\n RET\n.w4_h16:\n vpbroadcastd m5, strided\n pmulld m5, [bidir_sctr_w4]\n W_MASK 0, 4, 0, 1\n vpdpwssd m8, m4, m9\n kxnorw k1, k1, k1\n vpermb m8, m10, m8\n pand ym8, ym11\n mova [maskq], ym8\n vpscatterdd [dstq+m5]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM W_MASK 0, 4, 0, 1\n movhps xm10, [wm_422_mask+16]\n vpdpwssd ym8, ym4, ym9\n vpermb ym8, ym10, ym8\n pand xm8, xm11\n mova [maskq], xm8\n vextracti128 xmm1, ym0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 32\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n vpermb m1, m10, m1\n pand ym1, ym11\n mova [maskq], ym1\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq+strideq*0], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 32\n lea dstq, [dstq+strideq*4]\n.w16:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n vpermb m1, m10, m1\n vpermq m0, m0, q3120\n pand ym1, ym11\n mova [maskq], ym1\n mova [dstq+strideq*0], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m5, [warp_8x8_shufA]\n.w32_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n pand ym1, ym11\n mova [maskq], ym1\n add maskq, 32\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m5, [warp_8x8_shufA]\n.w64_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpwssd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n pand ym1, ym11\n mova [maskq], ym1\n add maskq, 32\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m13, [warp_8x8_shufA]\n.w128_loop:\n W_MASK 0, 4, 0, 1\n W_MASK 12, 5, 2, 3\n mova m2, m8\n vpdpwssd m2, m4, m9\n mova m3, m8\n vpdpwssd m3, m5, m9\n add tmp1q, 256\n add tmp2q, 256\n vpermt2b m2, m10, m3\n vpermq m0, m13, m0\n vpermq m1, m13, m12\n pand m2, m11\n mova [maskq], m2\n add maskq, 64\n mova [dstq+64*0], m0\n mova [dstq+64*1], m1\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":484,"cells":{"commit":{"kind":"string","value":"ce58d98b7b73c2d811a0baf88639b475591227ea"},"subject":{"kind":"string","value":"x86inc: save xmm_regs_used in spill_xmm for non-win64"},"message":{"kind":"string","value":"x86inc: save xmm_regs_used in spill_xmm for non-win64\n\nThis allows for AVX-512 code to issue vzeroupper automatically in RET,\nwhen not specified in cglobal but later on, along WIN64_SPILL_XMM.\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/ext/x86/x86inc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":";*****************************************************************************\n;* x86inc.asm: x264asm abstraction layer\n;*****************************************************************************\n;* Copyright (C) 2005-2019 x264 project\n;*\n;* Authors: Loren Merritt <lorenm@u.washington.edu>\n;* Henrik Gramner <henrik@gramner.com>\n;* Anton Mitrofanov <BugMaster@narod.ru>\n;* Fiona Glaser <fiona@x264.com>\n;*\n;* Permission to use, copy, modify, and/or distribute this software for any\n;* purpose with or without fee is hereby granted, provided that the above\n;* copyright notice and this permission notice appear in all copies.\n;*\n;* THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n;*****************************************************************************\n\n; This is a header file for the x264ASM assembly language, which uses\n; NASM/YASM syntax combined with a large number of macros to provide easy\n; abstraction between different calling conventions (x86_32, win64, linux64).\n; It also has various other useful features to simplify writing the kind of\n; DSP functions that are most often used in x264.\n\n; Unlike the rest of x264, this file is available under an ISC license, as it\n; has significant usefulness outside of x264 and we want it to be available\n; to the largest audience possible. Of course, if you modify it for your own\n; purposes to add a new feature, we strongly encourage contributing a patch\n; as this feature might be useful for others as well. Send patches or ideas\n; to x264-devel@videolan.org .\n\n%include \"config.asm\"\n\n%ifndef private_prefix\n %define private_prefix dav1d\n%endif\n\n%ifndef public_prefix\n %define public_prefix private_prefix\n%endif\n\n%ifndef STACK_ALIGNMENT\n %if ARCH_X86_64\n %define STACK_ALIGNMENT 16\n %else\n %define STACK_ALIGNMENT 4\n %endif\n%endif\n\n%define WIN64 0\n%define UNIX64 0\n%if ARCH_X86_64\n %ifidn __OUTPUT_FORMAT__,win32\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,win64\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,x64\n %define WIN64 1\n %else\n %define UNIX64 1\n %endif\n%endif\n\n%define FORMAT_ELF 0\n%define FORMAT_MACHO 0\n%ifidn __OUTPUT_FORMAT__,elf\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf32\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf64\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,macho\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho32\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho64\n %define FORMAT_MACHO 1\n%endif\n\n%ifdef PREFIX\n %define mangle(x) _ %+ x\n%else\n %define mangle(x) x\n%endif\n\n%macro SECTION_RODATA 0-1 16\n %ifidn __OUTPUT_FORMAT__,win32\n SECTION .rdata align=%1\n %elif WIN64\n SECTION .rdata align=%1\n %else\n SECTION .rodata align=%1\n %endif\n%endmacro\n\n%if ARCH_X86_64\n %define PIC 1 ; always use PIC on x86-64\n default rel\n%elifidn __OUTPUT_FORMAT__,win32\n %define PIC 0 ; PIC isn't used on 32-bit Windows\n%elifndef PIC\n %define PIC 0\n%endif\n\n%define HAVE_PRIVATE_EXTERN 1\n%ifdef __NASM_VER__\n %use smartalign\n %if __NASM_VERSION_ID__ < 0x020e0000 ; 2.14\n %define HAVE_PRIVATE_EXTERN 0\n %endif\n%endif\n\n; Macros to eliminate most code duplication between x86_32 and x86_64:\n; Currently this works only for leaf functions which load all their arguments\n; into registers at the start, and make no other use of the stack. Luckily that\n; covers most of x264's asm.\n\n; PROLOGUE:\n; %1 = number of arguments. loads them from stack if needed.\n; %2 = number of registers used. pushes callee-saved regs if needed.\n; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.\n; %4 = (optional) stack size to be allocated. The stack will be aligned before\n; allocating the specified stack size. If the required stack alignment is\n; larger than the known stack alignment the stack will be manually aligned\n; and an extra register will be allocated to hold the original stack\n; pointer (to not invalidate r0m etc.). To prevent the use of an extra\n; register as stack pointer, request a negative stack size.\n; %4+/%5+ = list of names to define to registers\n; PROLOGUE can also be invoked by adding the same options to cglobal\n\n; e.g.\n; cglobal foo, 2,3,7,0x40, dst, src, tmp\n; declares a function (foo) that automatically loads two arguments (dst and\n; src) into registers, uses one additional register (tmp) plus 7 vector\n; registers (m0-m6) and allocates 0x40 bytes of stack space.\n\n; TODO Some functions can use some args directly from the stack. If they're the\n; last args then you can just not declare them, but if they're in the middle\n; we need more flexible macro.\n\n; RET:\n; Pops anything that was pushed by PROLOGUE, and returns.\n\n; REP_RET:\n; Use this instead of RET if it's a branch target.\n\n; registers:\n; rN and rNq are the native-size register holding function argument N\n; rNd, rNw, rNb are dword, word, and byte size\n; rNh is the high 8 bits of the word size\n; rNm is the original location of arg N (a register or on the stack), dword\n; rNmp is native size\n\n%macro DECLARE_REG 2-3\n %define r%1q %2\n %define r%1d %2d\n %define r%1w %2w\n %define r%1b %2b\n %define r%1h %2h\n %define %2q %2\n %if %0 == 2\n %define r%1m %2d\n %define r%1mp %2\n %elif ARCH_X86_64 ; memory\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp qword r %+ %1 %+ m\n %else\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp dword r %+ %1 %+ m\n %endif\n %define r%1 %2\n%endmacro\n\n%macro DECLARE_REG_SIZE 3\n %define r%1q r%1\n %define e%1q r%1\n %define r%1d e%1\n %define e%1d e%1\n %define r%1w %1\n %define e%1w %1\n %define r%1h %3\n %define e%1h %3\n %define r%1b %2\n %define e%1b %2\n %if ARCH_X86_64 == 0\n %define r%1 e%1\n %endif\n%endmacro\n\nDECLARE_REG_SIZE ax, al, ah\nDECLARE_REG_SIZE bx, bl, bh\nDECLARE_REG_SIZE cx, cl, ch\nDECLARE_REG_SIZE dx, dl, dh\nDECLARE_REG_SIZE si, sil, null\nDECLARE_REG_SIZE di, dil, null\nDECLARE_REG_SIZE bp, bpl, null\n\n; t# defines for when per-arch register allocation is more complex than just function arguments\n\n%macro DECLARE_REG_TMP 1-*\n %assign %%i 0\n %rep %0\n CAT_XDEFINE t, %%i, r%1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n%endmacro\n\n%macro DECLARE_REG_TMP_SIZE 0-*\n %rep %0\n %define t%1q t%1 %+ q\n %define t%1d t%1 %+ d\n %define t%1w t%1 %+ w\n %define t%1h t%1 %+ h\n %define t%1b t%1 %+ b\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14\n\n%if ARCH_X86_64\n %define gprsize 8\n%else\n %define gprsize 4\n%endif\n\n%macro LEA 2\n%if ARCH_X86_64\n lea %1, [%2]\n%elif PIC\n call $+5 ; special-cased to not affect the RSB on most CPU:s\n pop %1\n add %1, (%2)-$+1\n%else\n mov %1, %2\n%endif\n%endmacro\n\n%macro PUSH 1\n push %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset+gprsize\n %endif\n%endmacro\n\n%macro POP 1\n pop %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset-gprsize\n %endif\n%endmacro\n\n%macro PUSH_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n PUSH r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro POP_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n pop r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro LOAD_IF_USED 1-*\n %rep %0\n %if %1 < num_args\n mov r%1, r %+ %1 %+ mp\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro SUB 2\n sub %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset+(%2)\n %endif\n%endmacro\n\n%macro ADD 2\n add %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset-(%2)\n %endif\n%endmacro\n\n%macro movifnidn 2\n %ifnidn %1, %2\n mov %1, %2\n %endif\n%endmacro\n\n%if ARCH_X86_64 == 0\n %define movsxd movifnidn\n%endif\n\n%macro movsxdifnidn 2\n %ifnidn %1, %2\n movsxd %1, %2\n %endif\n%endmacro\n\n%macro ASSERT 1\n %if (%1) == 0\n %error assertion ``%1'' failed\n %endif\n%endmacro\n\n%macro DEFINE_ARGS 0-*\n %ifdef n_arg_names\n %assign %%i 0\n %rep n_arg_names\n CAT_UNDEF arg_name %+ %%i, q\n CAT_UNDEF arg_name %+ %%i, d\n CAT_UNDEF arg_name %+ %%i, w\n CAT_UNDEF arg_name %+ %%i, h\n CAT_UNDEF arg_name %+ %%i, b\n CAT_UNDEF arg_name %+ %%i, m\n CAT_UNDEF arg_name %+ %%i, mp\n CAT_UNDEF arg_name, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n\n %xdefine %%stack_offset stack_offset\n %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine\n %assign %%i 0\n %rep %0\n %xdefine %1q r %+ %%i %+ q\n %xdefine %1d r %+ %%i %+ d\n %xdefine %1w r %+ %%i %+ w\n %xdefine %1h r %+ %%i %+ h\n %xdefine %1b r %+ %%i %+ b\n %xdefine %1m r %+ %%i %+ m\n %xdefine %1mp r %+ %%i %+ mp\n CAT_XDEFINE arg_name, %%i, %1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n %xdefine stack_offset %%stack_offset\n %assign n_arg_names %0\n%endmacro\n\n%define required_stack_alignment ((mmsize + 15) & ~15)\n%define vzeroupper_required (mmsize > 16 && (ARCH_X86_64 == 0 || xmm_regs_used > 16 || notcpuflag(avx512)))\n%define high_mm_regs (16*cpuflag(avx512))\n\n%macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)\n %ifnum %1\n %if %1 != 0\n %assign %%pad 0\n %assign stack_size %1\n %if stack_size < 0\n %assign stack_size -stack_size\n %endif\n %if WIN64\n %assign %%pad %%pad + 32 ; shadow space\n %if mmsize != 8\n %assign xmm_regs_used %2\n %if xmm_regs_used > 8\n %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers\n %endif\n %endif\n %endif\n %if required_stack_alignment <= STACK_ALIGNMENT\n ; maintain the current stack alignment\n %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %else\n %assign %%reg_num (regs_used - 1)\n %xdefine rstk r %+ %%reg_num\n ; align stack, and save original stack location directly above\n ; it, i.e. in [rsp+stack_size_padded], so we can restore the\n ; stack in a single instruction (i.e. mov rsp, rstk or mov\n ; rsp, [rsp+stack_size_padded])\n %if %1 < 0 ; need to store rsp on stack\n %xdefine rstkm [rsp + stack_size + %%pad]\n %assign %%pad %%pad + gprsize\n %else ; can keep rsp in rstk during whole function\n %xdefine rstkm rstk\n %endif\n %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))\n mov rstk, rsp\n and rsp, ~(required_stack_alignment-1)\n sub rsp, stack_size_padded\n movifnidn rstkm, rstk\n %endif\n WIN64_PUSH_XMM\n %endif\n %endif\n%endmacro\n\n%macro SETUP_STACK_POINTER 1\n %ifnum %1\n %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT\n %if %1 > 0\n ; Reserve an additional register for storing the original stack pointer, but avoid using\n ; eax/rax for this purpose since it can potentially get overwritten as a return value.\n %assign regs_used (regs_used + 1)\n %if ARCH_X86_64 && regs_used == 7\n %assign regs_used 8\n %elif ARCH_X86_64 == 0 && regs_used == 1\n %assign regs_used 2\n %endif\n %endif\n %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3\n ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)\n ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.\n %assign regs_used 5 + UNIX64 * 3\n %endif\n %endif\n %endif\n%endmacro\n\n%macro DEFINE_ARGS_INTERNAL 3+\n %ifnum %2\n DEFINE_ARGS %3\n %elif %1 == 4\n DEFINE_ARGS %2\n %elif %1 > 4\n DEFINE_ARGS %2, %3\n %endif\n%endmacro\n\n%if WIN64 ; Windows x64 ;=================================================\n\nDECLARE_REG 0, rcx\nDECLARE_REG 1, rdx\nDECLARE_REG 2, R8\nDECLARE_REG 3, R9\nDECLARE_REG 4, R10, 40\nDECLARE_REG 5, R11, 48\nDECLARE_REG 6, rax, 56\nDECLARE_REG 7, rdi, 64\nDECLARE_REG 8, rsi, 72\nDECLARE_REG 9, rbx, 80\nDECLARE_REG 10, rbp, 88\nDECLARE_REG 11, R14, 96\nDECLARE_REG 12, R15, 104\nDECLARE_REG 13, R12, 112\nDECLARE_REG 14, R13, 120\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4, %3\n %if mmsize != 8 && stack_size == 0\n WIN64_SPILL_XMM %3\n %endif\n LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%macro WIN64_PUSH_XMM 0\n ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.\n %if xmm_regs_used > 6 + high_mm_regs\n movaps [rstk + stack_offset + 8], xmm6\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps [rstk + stack_offset + 24], xmm7\n %endif\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i 8\n %rep %%xmm_regs_on_stack\n movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro WIN64_SPILL_XMM 1\n %assign xmm_regs_used %1\n ASSERT xmm_regs_used <= 16 + high_mm_regs\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.\n %assign %%pad %%xmm_regs_on_stack*16 + 32\n %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %endif\n WIN64_PUSH_XMM\n%endmacro\n\n%macro WIN64_RESTORE_XMM_INTERNAL 0\n %assign %%pad_size 0\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i xmm_regs_used - high_mm_regs\n %rep %%xmm_regs_on_stack\n %assign %%i %%i-1\n movaps xmm %+ %%i, [rsp + (%%i-8)*16 + stack_size + 32]\n %endrep\n %endif\n %if stack_size_padded > 0\n %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %assign %%pad_size stack_size_padded\n %endif\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps xmm7, [rsp + stack_offset - %%pad_size + 24]\n %endif\n %if xmm_regs_used > 6 + high_mm_regs\n movaps xmm6, [rsp + stack_offset - %%pad_size + 8]\n %endif\n%endmacro\n\n%macro WIN64_RESTORE_XMM 0\n WIN64_RESTORE_XMM_INTERNAL\n %assign stack_offset (stack_offset-stack_size_padded)\n %assign stack_size_padded 0\n %assign xmm_regs_used 0\n%endmacro\n\n%define has_epilogue regs_used > 7 || stack_size > 0 || vzeroupper_required || xmm_regs_used > 6+high_mm_regs\n\n%macro RET 0\n WIN64_RESTORE_XMM_INTERNAL\n POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%elif ARCH_X86_64 ; *nix x64 ;=============================================\n\nDECLARE_REG 0, rdi\nDECLARE_REG 1, rsi\nDECLARE_REG 2, rdx\nDECLARE_REG 3, rcx\nDECLARE_REG 4, R8\nDECLARE_REG 5, R9\nDECLARE_REG 6, rax, 8\nDECLARE_REG 7, R10, 16\nDECLARE_REG 8, R11, 24\nDECLARE_REG 9, rbx, 32\nDECLARE_REG 10, rbp, 40\nDECLARE_REG 11, R14, 48\nDECLARE_REG 12, R15, 56\nDECLARE_REG 13, R12, 64\nDECLARE_REG 14, R13, 72\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n %assign xmm_regs_used %3\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4\n LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 9 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 14, 13, 12, 11, 10, 9\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%else ; X86_32 ;==============================================================\n\nDECLARE_REG 0, eax, 4\nDECLARE_REG 1, ecx, 8\nDECLARE_REG 2, edx, 12\nDECLARE_REG 3, ebx, 16\nDECLARE_REG 4, esi, 20\nDECLARE_REG 5, edi, 24\nDECLARE_REG 6, ebp, 28\n%define rsp esp\n\n%macro DECLARE_ARG 1-*\n %rep %0\n %define r%1m [rstk + stack_offset + 4*%1 + 4]\n %define r%1mp dword r%1m\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14\n\n%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n %if num_args > 7\n %assign num_args 7\n %endif\n %if regs_used > 7\n %assign regs_used 7\n %endif\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 7\n PUSH_IF_USED 3, 4, 5, 6\n ALLOC_STACK %4\n LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 3 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 6, 5, 4, 3\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%endif ;======================================================================\n\n%if WIN64 == 0\n %macro WIN64_SPILL_XMM 1\n %assign xmm_regs_used %1\n %endmacro\n %macro WIN64_RESTORE_XMM 0\n %assign xmm_regs_used 0\n %endmacro\n %macro WIN64_PUSH_XMM 0\n %endmacro\n%endif\n\n; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either\n; a branch or a branch target. So switch to a 2-byte form of ret in that case.\n; We can automatically detect \"follows a branch\", but not a branch target.\n; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)\n%macro REP_RET 0\n %if has_epilogue || cpuflag(ssse3)\n RET\n %else\n rep ret\n %endif\n annotate_function_size\n%endmacro\n\n%define last_branch_adr $$\n%macro AUTO_REP_RET 0\n %if notcpuflag(ssse3)\n times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.\n %endif\n ret\n annotate_function_size\n%endmacro\n\n%macro BRANCH_INSTR 0-*\n %rep %0\n %macro %1 1-2 %1\n %2 %1\n %if notcpuflag(ssse3)\n %%branch_instr equ $\n %xdefine last_branch_adr %%branch_instr\n %endif\n %endmacro\n %rotate 1\n %endrep\n%endmacro\n\nBRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp\n\n%macro TAIL_CALL 1-2 1 ; callee, is_nonadjacent\n %if has_epilogue\n call %1\n RET\n %elif %2\n jmp %1\n %endif\n annotate_function_size\n%endmacro\n\n;=============================================================================\n; arch-independent part\n;=============================================================================\n\n%assign function_align 16\n\n; Begin a function.\n; Applies any symbol mangling needed for C linkage, and sets up a define such that\n; subsequent uses of the function name automatically refer to the mangled version.\n; Appends cpuflags to the function name if cpuflags has been specified.\n; The \"\" empty default parameter is a workaround for nasm, which fails if SUFFIX\n; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).\n%macro cglobal 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 1, %1 %+ SUFFIX, %2\n%endmacro\n%macro cvisible 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 0, %1 %+ SUFFIX, %2\n%endmacro\n%macro cglobal_internal 2-3+\n annotate_function_size\n %ifndef cglobaled_%2\n %if %1\n %xdefine %2 mangle(private_prefix %+ _ %+ %2)\n %else\n %xdefine %2 mangle(public_prefix %+ _ %+ %2)\n %endif\n %xdefine %2.skip_prologue %2 %+ .skip_prologue\n CAT_XDEFINE cglobaled_, %2, 1\n %endif\n %xdefine current_function %2\n %xdefine current_function_section __SECT__\n %if FORMAT_ELF\n %if %1\n global %2:function hidden\n %else\n global %2:function\n %endif\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN && %1\n global %2:private_extern\n %else\n global %2\n %endif\n align function_align\n %2:\n RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer\n %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required\n %assign stack_offset 0 ; stack pointer offset relative to the return address\n %assign stack_size 0 ; amount of stack space that can be freely used inside a function\n %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding\n %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64 and vzeroupper\n %ifnidn %3, \"\"\n PROLOGUE %3\n %endif\n%endmacro\n\n; Create a global symbol from a local label with the correct name mangling and type\n%macro cglobal_label 1\n %if FORMAT_ELF\n global current_function %+ %1:function hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global current_function %+ %1:private_extern\n %else\n global current_function %+ %1\n %endif\n %1:\n%endmacro\n\n%macro cextern 1\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n; like cextern, but without the prefix\n%macro cextern_naked 1\n %ifdef PREFIX\n %xdefine %1 mangle(%1)\n %endif\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n%macro const 1-2+\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n %if FORMAT_ELF\n global %1:data hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global %1:private_extern\n %else\n global %1\n %endif\n %1: %2\n%endmacro\n\n; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.\n%if FORMAT_ELF\n [SECTION .note.GNU-stack noalloc noexec nowrite progbits]\n%endif\n\n; Tell debuggers how large the function was.\n; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.\n; This is invoked by RET and similar macros, and also cglobal does it for the previous function,\n; but if the last function in a source file doesn't use any of the standard macros for its epilogue,\n; then its size might be unspecified.\n%macro annotate_function_size 0\n %ifdef __YASM_VER__\n %ifdef current_function\n %if FORMAT_ELF\n current_function_section\n %%ecf equ $\n size current_function %%ecf - current_function\n __SECT__\n %endif\n %endif\n %endif\n%endmacro\n\n; cpuflags\n\n%assign cpuflags_mmx (1<<0)\n%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx\n%assign cpuflags_3dnow (1<<2) | cpuflags_mmx\n%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow\n%assign cpuflags_sse (1<<4) | cpuflags_mmx2\n%assign cpuflags_sse2 (1<<5) | cpuflags_sse\n%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2\n%assign cpuflags_lzcnt (1<<7) | cpuflags_sse2\n%assign cpuflags_sse3 (1<<8) | cpuflags_sse2\n%assign cpuflags_ssse3 (1<<9) | cpuflags_sse3\n%assign cpuflags_sse4 (1<<10) | cpuflags_ssse3\n%assign cpuflags_sse42 (1<<11) | cpuflags_sse4\n%assign cpuflags_aesni (1<<12) | cpuflags_sse42\n%assign cpuflags_gfni (1<<13) | cpuflags_sse42\n%assign cpuflags_avx (1<<14) | cpuflags_sse42\n%assign cpuflags_xop (1<<15) | cpuflags_avx\n%assign cpuflags_fma4 (1<<16) | cpuflags_avx\n%assign cpuflags_fma3 (1<<17) | cpuflags_avx\n%assign cpuflags_bmi1 (1<<18) | cpuflags_avx|cpuflags_lzcnt\n%assign cpuflags_bmi2 (1<<19) | cpuflags_bmi1\n%assign cpuflags_avx2 (1<<20) | cpuflags_fma3|cpuflags_bmi2\n%assign cpuflags_avx512 (1<<21) | cpuflags_avx2 ; F, CD, BW, DQ, VL\n%assign cpuflags_avx512icl (1<<22) | cpuflags_avx512|cpuflags_gfni ; VNNI, IFMA, VBMI, VBMI2, VPOPCNTDQ, BITALG, VAES, VPCLMULQDQ\n\n%assign cpuflags_cache32 (1<<23)\n%assign cpuflags_cache64 (1<<24)\n%assign cpuflags_aligned (1<<25) ; not a cpu feature, but a function variant\n%assign cpuflags_atom (1<<26)\n\n; Returns a boolean value expressing whether or not the specified cpuflag is enabled.\n%define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)\n%define notcpuflag(x) (cpuflag(x) ^ 1)\n\n; Takes an arbitrary number of cpuflags from the above list.\n; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.\n; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.\n%macro INIT_CPUFLAGS 0-*\n %xdefine SUFFIX\n %undef cpuname\n %assign cpuflags 0\n\n %if %0 >= 1\n %rep %0\n %ifdef cpuname\n %xdefine cpuname cpuname %+ _%1\n %else\n %xdefine cpuname %1\n %endif\n %assign cpuflags cpuflags | cpuflags_%1\n %rotate 1\n %endrep\n %xdefine SUFFIX _ %+ cpuname\n\n %if cpuflag(avx)\n %assign avx_enabled 1\n %endif\n %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))\n %define mova movaps\n %define movu movups\n %define movnta movntps\n %endif\n %if cpuflag(aligned)\n %define movu mova\n %elif cpuflag(sse3) && notcpuflag(ssse3)\n %define movu lddqu\n %endif\n %endif\n\n %if ARCH_X86_64 || cpuflag(sse2)\n %ifdef __NASM_VER__\n ALIGNMODE p6\n %else\n CPU amdnop\n %endif\n %else\n %ifdef __NASM_VER__\n ALIGNMODE nop\n %else\n CPU basicnop\n %endif\n %endif\n%endmacro\n\n; Merge mmx, sse*, and avx*\n; m# is a simd register of the currently selected size\n; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#\n; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#\n; zm# is the corresponding zmm register if mmsize >= 64, otherwise the same as m#\n; (All 4 remain in sync through SWAP.)\n\n%macro CAT_XDEFINE 3\n %xdefine %1%2 %3\n%endmacro\n\n%macro CAT_UNDEF 2\n %undef %1%2\n%endmacro\n\n%macro DEFINE_MMREGS 1 ; mmtype\n %assign %%prev_mmregs 0\n %ifdef num_mmregs\n %assign %%prev_mmregs num_mmregs\n %endif\n\n %assign num_mmregs 8\n %if ARCH_X86_64 && mmsize >= 16\n %assign num_mmregs 16\n %if cpuflag(avx512) || mmsize == 64\n %assign num_mmregs 32\n %endif\n %endif\n\n %assign %%i 0\n %rep num_mmregs\n CAT_XDEFINE m, %%i, %1 %+ %%i\n CAT_XDEFINE nn%1, %%i, %%i\n %assign %%i %%i+1\n %endrep\n %if %%prev_mmregs > num_mmregs\n %rep %%prev_mmregs - num_mmregs\n CAT_UNDEF m, %%i\n CAT_UNDEF nn %+ mmtype, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n %xdefine mmtype %1\n%endmacro\n\n; Prefer registers 16-31 over 0-15 to avoid having to use vzeroupper\n%macro AVX512_MM_PERMUTATION 0-1 0 ; start_reg\n %if ARCH_X86_64 && cpuflag(avx512)\n %assign %%i %1\n %rep 16-%1\n %assign %%i_high %%i+16\n SWAP %%i, %%i_high\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro INIT_MMX 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_MMX %1\n %define mmsize 8\n %define mova movq\n %define movu movq\n %define movh movd\n %define movnta movntq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS mm\n%endmacro\n\n%macro INIT_XMM 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_XMM %1\n %define mmsize 16\n %define mova movdqa\n %define movu movdqu\n %define movh movq\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS xmm\n %if WIN64\n AVX512_MM_PERMUTATION 6 ; Swap callee-saved registers with volatile registers\n %endif\n%endmacro\n\n%macro INIT_YMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_YMM %1\n %define mmsize 32\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS ymm\n AVX512_MM_PERMUTATION\n%endmacro\n\n%macro INIT_ZMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_ZMM %1\n %define mmsize 64\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS zmm\n AVX512_MM_PERMUTATION\n%endmacro\n\nINIT_XMM\n\n%macro DECLARE_MMCAST 1\n %define mmmm%1 mm%1\n %define mmxmm%1 mm%1\n %define mmymm%1 mm%1\n %define mmzmm%1 mm%1\n %define xmmmm%1 mm%1\n %define xmmxmm%1 xmm%1\n %define xmmymm%1 xmm%1\n %define xmmzmm%1 xmm%1\n %define ymmmm%1 mm%1\n %define ymmxmm%1 xmm%1\n %define ymmymm%1 ymm%1\n %define ymmzmm%1 ymm%1\n %define zmmmm%1 mm%1\n %define zmmxmm%1 xmm%1\n %define zmmymm%1 ymm%1\n %define zmmzmm%1 zmm%1\n %define xm%1 xmm %+ m%1\n %define ym%1 ymm %+ m%1\n %define zm%1 zmm %+ m%1\n%endmacro\n\n%assign i 0\n%rep 32\n DECLARE_MMCAST i\n %assign i i+1\n%endrep\n\n; I often want to use macros that permute their arguments. e.g. there's no\n; efficient way to implement butterfly or transpose or dct without swapping some\n; arguments.\n;\n; I would like to not have to manually keep track of the permutations:\n; If I insert a permutation in the middle of a function, it should automatically\n; change everything that follows. For more complex macros I may also have multiple\n; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.\n;\n; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that\n; permutes its arguments. It's equivalent to exchanging the contents of the\n; registers, except that this way you exchange the register names instead, so it\n; doesn't cost any cycles.\n\n%macro PERMUTE 2-* ; takes a list of pairs to swap\n %rep %0/2\n %xdefine %%tmp%2 m%2\n %rotate 2\n %endrep\n %rep %0/2\n %xdefine m%1 %%tmp%2\n CAT_XDEFINE nn, m%1, %1\n %rotate 2\n %endrep\n%endmacro\n\n%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)\n %ifnum %1 ; SWAP 0, 1, ...\n SWAP_INTERNAL_NUM %1, %2\n %else ; SWAP m0, m1, ...\n SWAP_INTERNAL_NAME %1, %2\n %endif\n%endmacro\n\n%macro SWAP_INTERNAL_NUM 2-*\n %rep %0-1\n %xdefine %%tmp m%1\n %xdefine m%1 m%2\n %xdefine m%2 %%tmp\n CAT_XDEFINE nn, m%1, %1\n CAT_XDEFINE nn, m%2, %2\n %rotate 1\n %endrep\n%endmacro\n\n%macro SWAP_INTERNAL_NAME 2-*\n %xdefine %%args nn %+ %1\n %rep %0-1\n %xdefine %%args %%args, nn %+ %2\n %rotate 1\n %endrep\n SWAP_INTERNAL_NUM %%args\n%endmacro\n\n; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later\n; calls to that function will automatically load the permutation, so values can\n; be returned in mmregs.\n%macro SAVE_MM_PERMUTATION 0-1\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp m %+ %%i\n CAT_XDEFINE %%f, %%i, regnumof %+ %%tmp\n %assign %%i %%i+1\n %endrep\n%endmacro\n\n%macro LOAD_MM_PERMUTATION 0-1 ; name to load from\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %xdefine %%tmp %%f %+ 0\n %ifnum %%tmp\n RESET_MM_PERMUTATION\n AVX512_MM_PERMUTATION\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp %%f %+ %%i\n CAT_XDEFINE %%m, %%i, m %+ %%tmp\n %assign %%i %%i+1\n %endrep\n %rep num_mmregs\n %assign %%i %%i-1\n CAT_XDEFINE m, %%i, %%m %+ %%i\n CAT_XDEFINE nn, m %+ %%i, %%i\n %endrep\n %endif\n%endmacro\n\n; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't\n%macro call 1\n %ifid %1\n call_internal %1 %+ SUFFIX, %1\n %else\n call %1\n %endif\n%endmacro\n%macro call_internal 2\n %xdefine %%i %2\n %ifndef cglobaled_%2\n %ifdef cglobaled_%1\n %xdefine %%i %1\n %endif\n %endif\n call %%i\n LOAD_MM_PERMUTATION %%i\n%endmacro\n\n; Substitutions that reduce instruction size but are functionally equivalent\n%macro add 2\n %ifnum %2\n %if %2==128\n sub %1, -128\n %else\n add %1, %2\n %endif\n %else\n add %1, %2\n %endif\n%endmacro\n\n%macro sub 2\n %ifnum %2\n %if %2==128\n add %1, -128\n %else\n sub %1, %2\n %endif\n %else\n sub %1, %2\n %endif\n%endmacro\n\n;=============================================================================\n; AVX abstraction layer\n;=============================================================================\n\n%assign i 0\n%rep 32\n %if i < 8\n CAT_XDEFINE sizeofmm, i, 8\n CAT_XDEFINE regnumofmm, i, i\n %endif\n CAT_XDEFINE sizeofxmm, i, 16\n CAT_XDEFINE sizeofymm, i, 32\n CAT_XDEFINE sizeofzmm, i, 64\n CAT_XDEFINE regnumofxmm, i, i\n CAT_XDEFINE regnumofymm, i, i\n CAT_XDEFINE regnumofzmm, i, i\n %assign i i+1\n%endrep\n%undef i\n\n%macro CHECK_AVX_INSTR_EMU 3-*\n %xdefine %%opcode %1\n %xdefine %%dst %2\n %rep %0-2\n %ifidn %%dst, %3\n %error non-avx emulation of ``%%opcode'' is not supported\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n;%6+: operands\n%macro RUN_AVX_INSTR 6-9+\n %ifnum sizeof%7\n %assign __sizeofreg sizeof%7\n %elifnum sizeof%6\n %assign __sizeofreg sizeof%6\n %else\n %assign __sizeofreg mmsize\n %endif\n %assign __emulate_avx 0\n %if avx_enabled && __sizeofreg >= 16\n %xdefine __instr v%1\n %else\n %xdefine __instr %1\n %if %0 >= 8+%4\n %assign __emulate_avx 1\n %endif\n %endif\n %ifnidn %2, fnord\n %ifdef cpuname\n %if notcpuflag(%2)\n %error use of ``%1'' %2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 16 && notcpuflag(sse2)\n %error use of ``%1'' sse2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 32 && notcpuflag(avx2)\n %error use of ``%1'' avx2 instruction in cpuname function: current_function\n %elifidn %1, pextrw ; special case because the base instruction is mmx2,\n %ifnid %6 ; but sse4 is required for memory operands\n %if notcpuflag(sse4)\n %error use of ``%1'' sse4 instruction in cpuname function: current_function\n %endif\n %endif\n %endif\n %endif\n %endif\n\n %if __emulate_avx\n %xdefine __src1 %7\n %xdefine __src2 %8\n %if %5 && %4 == 0\n %ifnidn %6, %7\n %ifidn %6, %8\n %xdefine __src1 %8\n %xdefine __src2 %7\n %elifnnum sizeof%8\n ; 3-operand AVX instructions with a memory arg can only have it in src2,\n ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).\n ; So, if the instruction is commutative with a memory arg, swap them.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n %ifnidn %6, __src1\n %if %0 >= 9\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, __src2, %9\n %else\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, __src2\n %endif\n %if __sizeofreg == 8\n MOVQ %6, __src1\n %elif %3\n MOVAPS %6, __src1\n %else\n MOVDQA %6, __src1\n %endif\n %endif\n %if %0 >= 9\n %1 %6, __src2, %9\n %else\n %1 %6, __src2\n %endif\n %elif %0 >= 9\n __instr %6, %7, %8, %9\n %elif %0 == 8\n %if avx_enabled && %5\n %xdefine __src1 %7\n %xdefine __src2 %8\n %ifnum regnumof%7\n %ifnum regnumof%8\n %if regnumof%7 < 8 && regnumof%8 >= 8 && regnumof%8 < 16 && sizeof%8 <= 32\n ; Most VEX-encoded instructions require an additional byte to encode when\n ; src2 is a high register (e.g. m8..15). If the instruction is commutative\n ; we can swap src1 and src2 when doing so reduces the instruction length.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7, %8\n %endif\n %elif %0 == 7\n %if avx_enabled && %5\n %xdefine __src1 %6\n %xdefine __src2 %7\n %ifnum regnumof%6\n %ifnum regnumof%7\n %if regnumof%6 < 8 && regnumof%7 >= 8 && regnumof%7 < 16 && sizeof%7 <= 32\n %xdefine __src1 %7\n %xdefine __src2 %6\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7\n %endif\n %else\n __instr %6\n %endif\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n%macro AVX_INSTR 1-5 fnord, 0, 255, 0\n %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5\n %ifidn %2, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1\n %elifidn %3, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2\n %elifidn %4, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3\n %elifidn %5, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4\n %else\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5\n %endif\n %endmacro\n%endmacro\n\n; Instructions with both VEX/EVEX and legacy encodings\n; Non-destructive instructions are written without parameters\nAVX_INSTR addpd, sse2, 1, 0, 1\nAVX_INSTR addps, sse, 1, 0, 1\nAVX_INSTR addsd, sse2, 1, 0, 0\nAVX_INSTR addss, sse, 1, 0, 0\nAVX_INSTR addsubpd, sse3, 1, 0, 0\nAVX_INSTR addsubps, sse3, 1, 0, 0\nAVX_INSTR aesdec, aesni, 0, 0, 0\nAVX_INSTR aesdeclast, aesni, 0, 0, 0\nAVX_INSTR aesenc, aesni, 0, 0, 0\nAVX_INSTR aesenclast, aesni, 0, 0, 0\nAVX_INSTR aesimc, aesni\nAVX_INSTR aeskeygenassist, aesni\nAVX_INSTR andnpd, sse2, 1, 0, 0\nAVX_INSTR andnps, sse, 1, 0, 0\nAVX_INSTR andpd, sse2, 1, 0, 1\nAVX_INSTR andps, sse, 1, 0, 1\nAVX_INSTR blendpd, sse4, 1, 1, 0\nAVX_INSTR blendps, sse4, 1, 1, 0\nAVX_INSTR blendvpd, sse4 ; can't be emulated\nAVX_INSTR blendvps, sse4 ; can't be emulated\nAVX_INSTR cmpeqpd, sse2, 1, 0, 1\nAVX_INSTR cmpeqps, sse, 1, 0, 1\nAVX_INSTR cmpeqsd, sse2, 1, 0, 0\nAVX_INSTR cmpeqss, sse, 1, 0, 0\nAVX_INSTR cmplepd, sse2, 1, 0, 0\nAVX_INSTR cmpleps, sse, 1, 0, 0\nAVX_INSTR cmplesd, sse2, 1, 0, 0\nAVX_INSTR cmpless, sse, 1, 0, 0\nAVX_INSTR cmpltpd, sse2, 1, 0, 0\nAVX_INSTR cmpltps, sse, 1, 0, 0\nAVX_INSTR cmpltsd, sse2, 1, 0, 0\nAVX_INSTR cmpltss, sse, 1, 0, 0\nAVX_INSTR cmpneqpd, sse2, 1, 0, 1\nAVX_INSTR cmpneqps, sse, 1, 0, 1\nAVX_INSTR cmpneqsd, sse2, 1, 0, 0\nAVX_INSTR cmpneqss, sse, 1, 0, 0\nAVX_INSTR cmpnlepd, sse2, 1, 0, 0\nAVX_INSTR cmpnleps, sse, 1, 0, 0\nAVX_INSTR cmpnlesd, sse2, 1, 0, 0\nAVX_INSTR cmpnless, sse, 1, 0, 0\nAVX_INSTR cmpnltpd, sse2, 1, 0, 0\nAVX_INSTR cmpnltps, sse, 1, 0, 0\nAVX_INSTR cmpnltsd, sse2, 1, 0, 0\nAVX_INSTR cmpnltss, sse, 1, 0, 0\nAVX_INSTR cmpordpd, sse2 1, 0, 1\nAVX_INSTR cmpordps, sse 1, 0, 1\nAVX_INSTR cmpordsd, sse2 1, 0, 0\nAVX_INSTR cmpordss, sse 1, 0, 0\nAVX_INSTR cmppd, sse2, 1, 1, 0\nAVX_INSTR cmpps, sse, 1, 1, 0\nAVX_INSTR cmpsd, sse2, 1, 1, 0\nAVX_INSTR cmpss, sse, 1, 1, 0\nAVX_INSTR cmpunordpd, sse2, 1, 0, 1\nAVX_INSTR cmpunordps, sse, 1, 0, 1\nAVX_INSTR cmpunordsd, sse2, 1, 0, 0\nAVX_INSTR cmpunordss, sse, 1, 0, 0\nAVX_INSTR comisd, sse2, 1\nAVX_INSTR comiss, sse, 1\nAVX_INSTR cvtdq2pd, sse2, 1\nAVX_INSTR cvtdq2ps, sse2, 1\nAVX_INSTR cvtpd2dq, sse2, 1\nAVX_INSTR cvtpd2ps, sse2, 1\nAVX_INSTR cvtps2dq, sse2, 1\nAVX_INSTR cvtps2pd, sse2, 1\nAVX_INSTR cvtsd2si, sse2, 1\nAVX_INSTR cvtsd2ss, sse2, 1, 0, 0\nAVX_INSTR cvtsi2sd, sse2, 1, 0, 0\nAVX_INSTR cvtsi2ss, sse, 1, 0, 0\nAVX_INSTR cvtss2sd, sse2, 1, 0, 0\nAVX_INSTR cvtss2si, sse, 1\nAVX_INSTR cvttpd2dq, sse2, 1\nAVX_INSTR cvttps2dq, sse2, 1\nAVX_INSTR cvttsd2si, sse2, 1\nAVX_INSTR cvttss2si, sse, 1\nAVX_INSTR divpd, sse2, 1, 0, 0\nAVX_INSTR divps, sse, 1, 0, 0\nAVX_INSTR divsd, sse2, 1, 0, 0\nAVX_INSTR divss, sse, 1, 0, 0\nAVX_INSTR dppd, sse4, 1, 1, 0\nAVX_INSTR dpps, sse4, 1, 1, 0\nAVX_INSTR extractps, sse4, 1\nAVX_INSTR gf2p8affineinvqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8affineqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8mulb, gfni, 0, 0, 0\nAVX_INSTR haddpd, sse3, 1, 0, 0\nAVX_INSTR haddps, sse3, 1, 0, 0\nAVX_INSTR hsubpd, sse3, 1, 0, 0\nAVX_INSTR hsubps, sse3, 1, 0, 0\nAVX_INSTR insertps, sse4, 1, 1, 0\nAVX_INSTR lddqu, sse3\nAVX_INSTR ldmxcsr, sse, 1\nAVX_INSTR maskmovdqu, sse2\nAVX_INSTR maxpd, sse2, 1, 0, 1\nAVX_INSTR maxps, sse, 1, 0, 1\nAVX_INSTR maxsd, sse2, 1, 0, 0\nAVX_INSTR maxss, sse, 1, 0, 0\nAVX_INSTR minpd, sse2, 1, 0, 1\nAVX_INSTR minps, sse, 1, 0, 1\nAVX_INSTR minsd, sse2, 1, 0, 0\nAVX_INSTR minss, sse, 1, 0, 0\nAVX_INSTR movapd, sse2, 1\nAVX_INSTR movaps, sse, 1\nAVX_INSTR movd, mmx\nAVX_INSTR movddup, sse3, 1\nAVX_INSTR movdqa, sse2\nAVX_INSTR movdqu, sse2\nAVX_INSTR movhlps, sse, 1, 0, 0\nAVX_INSTR movhpd, sse2, 1, 0, 0\nAVX_INSTR movhps, sse, 1, 0, 0\nAVX_INSTR movlhps, sse, 1, 0, 0\nAVX_INSTR movlpd, sse2, 1, 0, 0\nAVX_INSTR movlps, sse, 1, 0, 0\nAVX_INSTR movmskpd, sse2, 1\nAVX_INSTR movmskps, sse, 1\nAVX_INSTR movntdq, sse2\nAVX_INSTR movntdqa, sse4\nAVX_INSTR movntpd, sse2, 1\nAVX_INSTR movntps, sse, 1\nAVX_INSTR movq, mmx\nAVX_INSTR movsd, sse2, 1, 0, 0\nAVX_INSTR movshdup, sse3, 1\nAVX_INSTR movsldup, sse3, 1\nAVX_INSTR movss, sse, 1, 0, 0\nAVX_INSTR movupd, sse2, 1\nAVX_INSTR movups, sse, 1\nAVX_INSTR mpsadbw, sse4, 0, 1, 0\nAVX_INSTR mulpd, sse2, 1, 0, 1\nAVX_INSTR mulps, sse, 1, 0, 1\nAVX_INSTR mulsd, sse2, 1, 0, 0\nAVX_INSTR mulss, sse, 1, 0, 0\nAVX_INSTR orpd, sse2, 1, 0, 1\nAVX_INSTR orps, sse, 1, 0, 1\nAVX_INSTR pabsb, ssse3\nAVX_INSTR pabsd, ssse3\nAVX_INSTR pabsw, ssse3\nAVX_INSTR packsswb, mmx, 0, 0, 0\nAVX_INSTR packssdw, mmx, 0, 0, 0\nAVX_INSTR packuswb, mmx, 0, 0, 0\nAVX_INSTR packusdw, sse4, 0, 0, 0\nAVX_INSTR paddb, mmx, 0, 0, 1\nAVX_INSTR paddw, mmx, 0, 0, 1\nAVX_INSTR paddd, mmx, 0, 0, 1\nAVX_INSTR paddq, sse2, 0, 0, 1\nAVX_INSTR paddsb, mmx, 0, 0, 1\nAVX_INSTR paddsw, mmx, 0, 0, 1\nAVX_INSTR paddusb, mmx, 0, 0, 1\nAVX_INSTR paddusw, mmx, 0, 0, 1\nAVX_INSTR palignr, ssse3, 0, 1, 0\nAVX_INSTR pand, mmx, 0, 0, 1\nAVX_INSTR pandn, mmx, 0, 0, 0\nAVX_INSTR pavgb, mmx2, 0, 0, 1\nAVX_INSTR pavgw, mmx2, 0, 0, 1\nAVX_INSTR pblendvb, sse4 ; can't be emulated\nAVX_INSTR pblendw, sse4, 0, 1, 0\nAVX_INSTR pclmulqdq, fnord, 0, 1, 0\nAVX_INSTR pclmulhqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmulhqlqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqlqdq, fnord, 0, 0, 0\nAVX_INSTR pcmpestri, sse42\nAVX_INSTR pcmpestrm, sse42\nAVX_INSTR pcmpistri, sse42\nAVX_INSTR pcmpistrm, sse42\nAVX_INSTR pcmpeqb, mmx, 0, 0, 1\nAVX_INSTR pcmpeqw, mmx, 0, 0, 1\nAVX_INSTR pcmpeqd, mmx, 0, 0, 1\nAVX_INSTR pcmpeqq, sse4, 0, 0, 1\nAVX_INSTR pcmpgtb, mmx, 0, 0, 0\nAVX_INSTR pcmpgtw, mmx, 0, 0, 0\nAVX_INSTR pcmpgtd, mmx, 0, 0, 0\nAVX_INSTR pcmpgtq, sse42, 0, 0, 0\nAVX_INSTR pextrb, sse4\nAVX_INSTR pextrd, sse4\nAVX_INSTR pextrq, sse4\nAVX_INSTR pextrw, mmx2\nAVX_INSTR phaddw, ssse3, 0, 0, 0\nAVX_INSTR phaddd, ssse3, 0, 0, 0\nAVX_INSTR phaddsw, ssse3, 0, 0, 0\nAVX_INSTR phminposuw, sse4\nAVX_INSTR phsubw, ssse3, 0, 0, 0\nAVX_INSTR phsubd, ssse3, 0, 0, 0\nAVX_INSTR phsubsw, ssse3, 0, 0, 0\nAVX_INSTR pinsrb, sse4, 0, 1, 0\nAVX_INSTR pinsrd, sse4, 0, 1, 0\nAVX_INSTR pinsrq, sse4, 0, 1, 0\nAVX_INSTR pinsrw, mmx2, 0, 1, 0\nAVX_INSTR pmaddwd, mmx, 0, 0, 1\nAVX_INSTR pmaddubsw, ssse3, 0, 0, 0\nAVX_INSTR pmaxsb, sse4, 0, 0, 1\nAVX_INSTR pmaxsw, mmx2, 0, 0, 1\nAVX_INSTR pmaxsd, sse4, 0, 0, 1\nAVX_INSTR pmaxub, mmx2, 0, 0, 1\nAVX_INSTR pmaxuw, sse4, 0, 0, 1\nAVX_INSTR pmaxud, sse4, 0, 0, 1\nAVX_INSTR pminsb, sse4, 0, 0, 1\nAVX_INSTR pminsw, mmx2, 0, 0, 1\nAVX_INSTR pminsd, sse4, 0, 0, 1\nAVX_INSTR pminub, mmx2, 0, 0, 1\nAVX_INSTR pminuw, sse4, 0, 0, 1\nAVX_INSTR pminud, sse4, 0, 0, 1\nAVX_INSTR pmovmskb, mmx2\nAVX_INSTR pmovsxbw, sse4\nAVX_INSTR pmovsxbd, sse4\nAVX_INSTR pmovsxbq, sse4\nAVX_INSTR pmovsxwd, sse4\nAVX_INSTR pmovsxwq, sse4\nAVX_INSTR pmovsxdq, sse4\nAVX_INSTR pmovzxbw, sse4\nAVX_INSTR pmovzxbd, sse4\nAVX_INSTR pmovzxbq, sse4\nAVX_INSTR pmovzxwd, sse4\nAVX_INSTR pmovzxwq, sse4\nAVX_INSTR pmovzxdq, sse4\nAVX_INSTR pmuldq, sse4, 0, 0, 1\nAVX_INSTR pmulhrsw, ssse3, 0, 0, 1\nAVX_INSTR pmulhuw, mmx2, 0, 0, 1\nAVX_INSTR pmulhw, mmx, 0, 0, 1\nAVX_INSTR pmullw, mmx, 0, 0, 1\nAVX_INSTR pmulld, sse4, 0, 0, 1\nAVX_INSTR pmuludq, sse2, 0, 0, 1\nAVX_INSTR por, mmx, 0, 0, 1\nAVX_INSTR psadbw, mmx2, 0, 0, 1\nAVX_INSTR pshufb, ssse3, 0, 0, 0\nAVX_INSTR pshufd, sse2\nAVX_INSTR pshufhw, sse2\nAVX_INSTR pshuflw, sse2\nAVX_INSTR psignb, ssse3, 0, 0, 0\nAVX_INSTR psignw, ssse3, 0, 0, 0\nAVX_INSTR psignd, ssse3, 0, 0, 0\nAVX_INSTR psllw, mmx, 0, 0, 0\nAVX_INSTR pslld, mmx, 0, 0, 0\nAVX_INSTR psllq, mmx, 0, 0, 0\nAVX_INSTR pslldq, sse2, 0, 0, 0\nAVX_INSTR psraw, mmx, 0, 0, 0\nAVX_INSTR psrad, mmx, 0, 0, 0\nAVX_INSTR psrlw, mmx, 0, 0, 0\nAVX_INSTR psrld, mmx, 0, 0, 0\nAVX_INSTR psrlq, mmx, 0, 0, 0\nAVX_INSTR psrldq, sse2, 0, 0, 0\nAVX_INSTR psubb, mmx, 0, 0, 0\nAVX_INSTR psubw, mmx, 0, 0, 0\nAVX_INSTR psubd, mmx, 0, 0, 0\nAVX_INSTR psubq, sse2, 0, 0, 0\nAVX_INSTR psubsb, mmx, 0, 0, 0\nAVX_INSTR psubsw, mmx, 0, 0, 0\nAVX_INSTR psubusb, mmx, 0, 0, 0\nAVX_INSTR psubusw, mmx, 0, 0, 0\nAVX_INSTR ptest, sse4\nAVX_INSTR punpckhbw, mmx, 0, 0, 0\nAVX_INSTR punpckhwd, mmx, 0, 0, 0\nAVX_INSTR punpckhdq, mmx, 0, 0, 0\nAVX_INSTR punpckhqdq, sse2, 0, 0, 0\nAVX_INSTR punpcklbw, mmx, 0, 0, 0\nAVX_INSTR punpcklwd, mmx, 0, 0, 0\nAVX_INSTR punpckldq, mmx, 0, 0, 0\nAVX_INSTR punpcklqdq, sse2, 0, 0, 0\nAVX_INSTR pxor, mmx, 0, 0, 1\nAVX_INSTR rcpps, sse, 1\nAVX_INSTR rcpss, sse, 1, 0, 0\nAVX_INSTR roundpd, sse4, 1\nAVX_INSTR roundps, sse4, 1\nAVX_INSTR roundsd, sse4, 1, 1, 0\nAVX_INSTR roundss, sse4, 1, 1, 0\nAVX_INSTR rsqrtps, sse, 1\nAVX_INSTR rsqrtss, sse, 1, 0, 0\nAVX_INSTR shufpd, sse2, 1, 1, 0\nAVX_INSTR shufps, sse, 1, 1, 0\nAVX_INSTR sqrtpd, sse2, 1\nAVX_INSTR sqrtps, sse, 1\nAVX_INSTR sqrtsd, sse2, 1, 0, 0\nAVX_INSTR sqrtss, sse, 1, 0, 0\nAVX_INSTR stmxcsr, sse, 1\nAVX_INSTR subpd, sse2, 1, 0, 0\nAVX_INSTR subps, sse, 1, 0, 0\nAVX_INSTR subsd, sse2, 1, 0, 0\nAVX_INSTR subss, sse, 1, 0, 0\nAVX_INSTR ucomisd, sse2, 1\nAVX_INSTR ucomiss, sse, 1\nAVX_INSTR unpckhpd, sse2, 1, 0, 0\nAVX_INSTR unpckhps, sse, 1, 0, 0\nAVX_INSTR unpcklpd, sse2, 1, 0, 0\nAVX_INSTR unpcklps, sse, 1, 0, 0\nAVX_INSTR xorpd, sse2, 1, 0, 1\nAVX_INSTR xorps, sse, 1, 0, 1\n\n; 3DNow instructions, for sharing code between AVX, SSE and 3DN\nAVX_INSTR pfadd, 3dnow, 1, 0, 1\nAVX_INSTR pfsub, 3dnow, 1, 0, 0\nAVX_INSTR pfmul, 3dnow, 1, 0, 1\n\n;%1 == instruction\n;%2 == minimal instruction set\n%macro GPR_INSTR 2\n %macro %1 2-5 fnord, %1, %2\n %ifdef cpuname\n %if notcpuflag(%5)\n %error use of ``%4'' %5 instruction in cpuname function: current_function\n %endif\n %endif\n %ifidn %3, fnord\n %4 %1, %2\n %else\n %4 %1, %2, %3\n %endif\n %endmacro\n%endmacro\n\nGPR_INSTR andn, bmi1\nGPR_INSTR bextr, bmi1\nGPR_INSTR blsi, bmi1\nGPR_INSTR blsmsk, bmi1\nGPR_INSTR bzhi, bmi2\nGPR_INSTR mulx, bmi2\nGPR_INSTR pdep, bmi2\nGPR_INSTR pext, bmi2\nGPR_INSTR popcnt, sse42\nGPR_INSTR rorx, bmi2\nGPR_INSTR sarx, bmi2\nGPR_INSTR shlx, bmi2\nGPR_INSTR shrx, bmi2\n\n; base-4 constants for shuffles\n%assign i 0\n%rep 256\n %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)\n %if j < 10\n CAT_XDEFINE q000, j, i\n %elif j < 100\n CAT_XDEFINE q00, j, i\n %elif j < 1000\n CAT_XDEFINE q0, j, i\n %else\n CAT_XDEFINE q, j, i\n %endif\n %assign i i+1\n%endrep\n%undef i\n%undef j\n\n%macro FMA_INSTR 3\n %macro %1 4-7 %1, %2, %3\n %if cpuflag(xop)\n v%5 %1, %2, %3, %4\n %elifnidn %1, %4\n %6 %1, %2, %3\n %7 %1, %4\n %else\n %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n%endmacro\n\nFMA_INSTR pmacsww, pmullw, paddw\nFMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation\nFMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation\nFMA_INSTR pmadcswd, pmaddwd, paddd\n\n; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.\n; FMA3 is only possible if dst is the same as one of the src registers.\n; Either src2 or src3 can be a memory operand.\n%macro FMA4_INSTR 2-*\n %push fma4_instr\n %xdefine %$prefix %1\n %rep %0 - 1\n %macro %$prefix%2 4-6 %$prefix, %2\n %if notcpuflag(fma3) && notcpuflag(fma4)\n %error use of ``%5%6'' fma instruction in cpuname function: current_function\n %elif cpuflag(fma4)\n v%5%6 %1, %2, %3, %4\n %elifidn %1, %2\n ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.\n %ifnum sizeof%3\n v%{5}213%6 %2, %3, %4\n %else\n v%{5}132%6 %2, %4, %3\n %endif\n %elifidn %1, %3\n v%{5}213%6 %3, %2, %4\n %elifidn %1, %4\n v%{5}231%6 %4, %2, %3\n %else\n %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n %rotate 1\n %endrep\n %pop\n%endmacro\n\nFMA4_INSTR fmadd, pd, ps, sd, ss\nFMA4_INSTR fmaddsub, pd, ps\nFMA4_INSTR fmsub, pd, ps, sd, ss\nFMA4_INSTR fmsubadd, pd, ps\nFMA4_INSTR fnmadd, pd, ps, sd, ss\nFMA4_INSTR fnmsub, pd, ps, sd, ss\n\n; Macros for converting VEX instructions to equivalent EVEX ones.\n%macro EVEX_INSTR 2-3 0 ; vex, evex, prefer_evex\n %macro %1 2-7 fnord, fnord, %1, %2, %3\n %ifidn %3, fnord\n %define %%args %1, %2\n %elifidn %4, fnord\n %define %%args %1, %2, %3\n %else\n %define %%args %1, %2, %3, %4\n %endif\n %assign %%evex_required cpuflag(avx512) & %7\n %ifnum regnumof%1\n %if regnumof%1 >= 16 || sizeof%1 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%2\n %if regnumof%2 >= 16 || sizeof%2 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%3\n %if regnumof%3 >= 16 || sizeof%3 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %if %%evex_required\n %6 %%args\n %else\n %5 %%args ; Prefer VEX over EVEX due to shorter instruction length\n %endif\n %endmacro\n%endmacro\n\nEVEX_INSTR vbroadcastf128, vbroadcastf32x4\nEVEX_INSTR vbroadcasti128, vbroadcasti32x4\nEVEX_INSTR vextractf128, vextractf32x4\nEVEX_INSTR vextracti128, vextracti32x4\nEVEX_INSTR vinsertf128, vinsertf32x4\nEVEX_INSTR vinserti128, vinserti32x4\nEVEX_INSTR vmovdqa, vmovdqa32\nEVEX_INSTR vmovdqu, vmovdqu32\nEVEX_INSTR vpand, vpandd\nEVEX_INSTR vpandn, vpandnd\nEVEX_INSTR vpor, vpord\nEVEX_INSTR vpxor, vpxord\nEVEX_INSTR vrcpps, vrcp14ps, 1 ; EVEX versions have higher precision\nEVEX_INSTR vrcpss, vrcp14ss, 1\nEVEX_INSTR vrsqrtps, vrsqrt14ps, 1\nEVEX_INSTR vrsqrtss, vrsqrt14ss, 1\n"},"old_contents":{"kind":"string","value":";*****************************************************************************\n;* x86inc.asm: x264asm abstraction layer\n;*****************************************************************************\n;* Copyright (C) 2005-2019 x264 project\n;*\n;* Authors: Loren Merritt <lorenm@u.washington.edu>\n;* Henrik Gramner <henrik@gramner.com>\n;* Anton Mitrofanov <BugMaster@narod.ru>\n;* Fiona Glaser <fiona@x264.com>\n;*\n;* Permission to use, copy, modify, and/or distribute this software for any\n;* purpose with or without fee is hereby granted, provided that the above\n;* copyright notice and this permission notice appear in all copies.\n;*\n;* THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n;*****************************************************************************\n\n; This is a header file for the x264ASM assembly language, which uses\n; NASM/YASM syntax combined with a large number of macros to provide easy\n; abstraction between different calling conventions (x86_32, win64, linux64).\n; It also has various other useful features to simplify writing the kind of\n; DSP functions that are most often used in x264.\n\n; Unlike the rest of x264, this file is available under an ISC license, as it\n; has significant usefulness outside of x264 and we want it to be available\n; to the largest audience possible. Of course, if you modify it for your own\n; purposes to add a new feature, we strongly encourage contributing a patch\n; as this feature might be useful for others as well. Send patches or ideas\n; to x264-devel@videolan.org .\n\n%include \"config.asm\"\n\n%ifndef private_prefix\n %define private_prefix dav1d\n%endif\n\n%ifndef public_prefix\n %define public_prefix private_prefix\n%endif\n\n%ifndef STACK_ALIGNMENT\n %if ARCH_X86_64\n %define STACK_ALIGNMENT 16\n %else\n %define STACK_ALIGNMENT 4\n %endif\n%endif\n\n%define WIN64 0\n%define UNIX64 0\n%if ARCH_X86_64\n %ifidn __OUTPUT_FORMAT__,win32\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,win64\n %define WIN64 1\n %elifidn __OUTPUT_FORMAT__,x64\n %define WIN64 1\n %else\n %define UNIX64 1\n %endif\n%endif\n\n%define FORMAT_ELF 0\n%define FORMAT_MACHO 0\n%ifidn __OUTPUT_FORMAT__,elf\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf32\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,elf64\n %define FORMAT_ELF 1\n%elifidn __OUTPUT_FORMAT__,macho\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho32\n %define FORMAT_MACHO 1\n%elifidn __OUTPUT_FORMAT__,macho64\n %define FORMAT_MACHO 1\n%endif\n\n%ifdef PREFIX\n %define mangle(x) _ %+ x\n%else\n %define mangle(x) x\n%endif\n\n%macro SECTION_RODATA 0-1 16\n %ifidn __OUTPUT_FORMAT__,win32\n SECTION .rdata align=%1\n %elif WIN64\n SECTION .rdata align=%1\n %else\n SECTION .rodata align=%1\n %endif\n%endmacro\n\n%if ARCH_X86_64\n %define PIC 1 ; always use PIC on x86-64\n default rel\n%elifidn __OUTPUT_FORMAT__,win32\n %define PIC 0 ; PIC isn't used on 32-bit Windows\n%elifndef PIC\n %define PIC 0\n%endif\n\n%define HAVE_PRIVATE_EXTERN 1\n%ifdef __NASM_VER__\n %use smartalign\n %if __NASM_VERSION_ID__ < 0x020e0000 ; 2.14\n %define HAVE_PRIVATE_EXTERN 0\n %endif\n%endif\n\n; Macros to eliminate most code duplication between x86_32 and x86_64:\n; Currently this works only for leaf functions which load all their arguments\n; into registers at the start, and make no other use of the stack. Luckily that\n; covers most of x264's asm.\n\n; PROLOGUE:\n; %1 = number of arguments. loads them from stack if needed.\n; %2 = number of registers used. pushes callee-saved regs if needed.\n; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.\n; %4 = (optional) stack size to be allocated. The stack will be aligned before\n; allocating the specified stack size. If the required stack alignment is\n; larger than the known stack alignment the stack will be manually aligned\n; and an extra register will be allocated to hold the original stack\n; pointer (to not invalidate r0m etc.). To prevent the use of an extra\n; register as stack pointer, request a negative stack size.\n; %4+/%5+ = list of names to define to registers\n; PROLOGUE can also be invoked by adding the same options to cglobal\n\n; e.g.\n; cglobal foo, 2,3,7,0x40, dst, src, tmp\n; declares a function (foo) that automatically loads two arguments (dst and\n; src) into registers, uses one additional register (tmp) plus 7 vector\n; registers (m0-m6) and allocates 0x40 bytes of stack space.\n\n; TODO Some functions can use some args directly from the stack. If they're the\n; last args then you can just not declare them, but if they're in the middle\n; we need more flexible macro.\n\n; RET:\n; Pops anything that was pushed by PROLOGUE, and returns.\n\n; REP_RET:\n; Use this instead of RET if it's a branch target.\n\n; registers:\n; rN and rNq are the native-size register holding function argument N\n; rNd, rNw, rNb are dword, word, and byte size\n; rNh is the high 8 bits of the word size\n; rNm is the original location of arg N (a register or on the stack), dword\n; rNmp is native size\n\n%macro DECLARE_REG 2-3\n %define r%1q %2\n %define r%1d %2d\n %define r%1w %2w\n %define r%1b %2b\n %define r%1h %2h\n %define %2q %2\n %if %0 == 2\n %define r%1m %2d\n %define r%1mp %2\n %elif ARCH_X86_64 ; memory\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp qword r %+ %1 %+ m\n %else\n %define r%1m [rstk + stack_offset + %3]\n %define r%1mp dword r %+ %1 %+ m\n %endif\n %define r%1 %2\n%endmacro\n\n%macro DECLARE_REG_SIZE 3\n %define r%1q r%1\n %define e%1q r%1\n %define r%1d e%1\n %define e%1d e%1\n %define r%1w %1\n %define e%1w %1\n %define r%1h %3\n %define e%1h %3\n %define r%1b %2\n %define e%1b %2\n %if ARCH_X86_64 == 0\n %define r%1 e%1\n %endif\n%endmacro\n\nDECLARE_REG_SIZE ax, al, ah\nDECLARE_REG_SIZE bx, bl, bh\nDECLARE_REG_SIZE cx, cl, ch\nDECLARE_REG_SIZE dx, dl, dh\nDECLARE_REG_SIZE si, sil, null\nDECLARE_REG_SIZE di, dil, null\nDECLARE_REG_SIZE bp, bpl, null\n\n; t# defines for when per-arch register allocation is more complex than just function arguments\n\n%macro DECLARE_REG_TMP 1-*\n %assign %%i 0\n %rep %0\n CAT_XDEFINE t, %%i, r%1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n%endmacro\n\n%macro DECLARE_REG_TMP_SIZE 0-*\n %rep %0\n %define t%1q t%1 %+ q\n %define t%1d t%1 %+ d\n %define t%1w t%1 %+ w\n %define t%1h t%1 %+ h\n %define t%1b t%1 %+ b\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14\n\n%if ARCH_X86_64\n %define gprsize 8\n%else\n %define gprsize 4\n%endif\n\n%macro LEA 2\n%if ARCH_X86_64\n lea %1, [%2]\n%elif PIC\n call $+5 ; special-cased to not affect the RSB on most CPU:s\n pop %1\n add %1, (%2)-$+1\n%else\n mov %1, %2\n%endif\n%endmacro\n\n%macro PUSH 1\n push %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset+gprsize\n %endif\n%endmacro\n\n%macro POP 1\n pop %1\n %ifidn rstk, rsp\n %assign stack_offset stack_offset-gprsize\n %endif\n%endmacro\n\n%macro PUSH_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n PUSH r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro POP_IF_USED 1-*\n %rep %0\n %if %1 < regs_used\n pop r%1\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro LOAD_IF_USED 1-*\n %rep %0\n %if %1 < num_args\n mov r%1, r %+ %1 %+ mp\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n%macro SUB 2\n sub %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset+(%2)\n %endif\n%endmacro\n\n%macro ADD 2\n add %1, %2\n %ifidn %1, rstk\n %assign stack_offset stack_offset-(%2)\n %endif\n%endmacro\n\n%macro movifnidn 2\n %ifnidn %1, %2\n mov %1, %2\n %endif\n%endmacro\n\n%if ARCH_X86_64 == 0\n %define movsxd movifnidn\n%endif\n\n%macro movsxdifnidn 2\n %ifnidn %1, %2\n movsxd %1, %2\n %endif\n%endmacro\n\n%macro ASSERT 1\n %if (%1) == 0\n %error assertion ``%1'' failed\n %endif\n%endmacro\n\n%macro DEFINE_ARGS 0-*\n %ifdef n_arg_names\n %assign %%i 0\n %rep n_arg_names\n CAT_UNDEF arg_name %+ %%i, q\n CAT_UNDEF arg_name %+ %%i, d\n CAT_UNDEF arg_name %+ %%i, w\n CAT_UNDEF arg_name %+ %%i, h\n CAT_UNDEF arg_name %+ %%i, b\n CAT_UNDEF arg_name %+ %%i, m\n CAT_UNDEF arg_name %+ %%i, mp\n CAT_UNDEF arg_name, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n\n %xdefine %%stack_offset stack_offset\n %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine\n %assign %%i 0\n %rep %0\n %xdefine %1q r %+ %%i %+ q\n %xdefine %1d r %+ %%i %+ d\n %xdefine %1w r %+ %%i %+ w\n %xdefine %1h r %+ %%i %+ h\n %xdefine %1b r %+ %%i %+ b\n %xdefine %1m r %+ %%i %+ m\n %xdefine %1mp r %+ %%i %+ mp\n CAT_XDEFINE arg_name, %%i, %1\n %assign %%i %%i+1\n %rotate 1\n %endrep\n %xdefine stack_offset %%stack_offset\n %assign n_arg_names %0\n%endmacro\n\n%define required_stack_alignment ((mmsize + 15) & ~15)\n%define vzeroupper_required (mmsize > 16 && (ARCH_X86_64 == 0 || xmm_regs_used > 16 || notcpuflag(avx512)))\n%define high_mm_regs (16*cpuflag(avx512))\n\n%macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)\n %ifnum %1\n %if %1 != 0\n %assign %%pad 0\n %assign stack_size %1\n %if stack_size < 0\n %assign stack_size -stack_size\n %endif\n %if WIN64\n %assign %%pad %%pad + 32 ; shadow space\n %if mmsize != 8\n %assign xmm_regs_used %2\n %if xmm_regs_used > 8\n %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers\n %endif\n %endif\n %endif\n %if required_stack_alignment <= STACK_ALIGNMENT\n ; maintain the current stack alignment\n %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %else\n %assign %%reg_num (regs_used - 1)\n %xdefine rstk r %+ %%reg_num\n ; align stack, and save original stack location directly above\n ; it, i.e. in [rsp+stack_size_padded], so we can restore the\n ; stack in a single instruction (i.e. mov rsp, rstk or mov\n ; rsp, [rsp+stack_size_padded])\n %if %1 < 0 ; need to store rsp on stack\n %xdefine rstkm [rsp + stack_size + %%pad]\n %assign %%pad %%pad + gprsize\n %else ; can keep rsp in rstk during whole function\n %xdefine rstkm rstk\n %endif\n %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))\n mov rstk, rsp\n and rsp, ~(required_stack_alignment-1)\n sub rsp, stack_size_padded\n movifnidn rstkm, rstk\n %endif\n WIN64_PUSH_XMM\n %endif\n %endif\n%endmacro\n\n%macro SETUP_STACK_POINTER 1\n %ifnum %1\n %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT\n %if %1 > 0\n ; Reserve an additional register for storing the original stack pointer, but avoid using\n ; eax/rax for this purpose since it can potentially get overwritten as a return value.\n %assign regs_used (regs_used + 1)\n %if ARCH_X86_64 && regs_used == 7\n %assign regs_used 8\n %elif ARCH_X86_64 == 0 && regs_used == 1\n %assign regs_used 2\n %endif\n %endif\n %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3\n ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)\n ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.\n %assign regs_used 5 + UNIX64 * 3\n %endif\n %endif\n %endif\n%endmacro\n\n%macro DEFINE_ARGS_INTERNAL 3+\n %ifnum %2\n DEFINE_ARGS %3\n %elif %1 == 4\n DEFINE_ARGS %2\n %elif %1 > 4\n DEFINE_ARGS %2, %3\n %endif\n%endmacro\n\n%if WIN64 ; Windows x64 ;=================================================\n\nDECLARE_REG 0, rcx\nDECLARE_REG 1, rdx\nDECLARE_REG 2, R8\nDECLARE_REG 3, R9\nDECLARE_REG 4, R10, 40\nDECLARE_REG 5, R11, 48\nDECLARE_REG 6, rax, 56\nDECLARE_REG 7, rdi, 64\nDECLARE_REG 8, rsi, 72\nDECLARE_REG 9, rbx, 80\nDECLARE_REG 10, rbp, 88\nDECLARE_REG 11, R14, 96\nDECLARE_REG 12, R15, 104\nDECLARE_REG 13, R12, 112\nDECLARE_REG 14, R13, 120\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4, %3\n %if mmsize != 8 && stack_size == 0\n WIN64_SPILL_XMM %3\n %endif\n LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%macro WIN64_PUSH_XMM 0\n ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.\n %if xmm_regs_used > 6 + high_mm_regs\n movaps [rstk + stack_offset + 8], xmm6\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps [rstk + stack_offset + 24], xmm7\n %endif\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i 8\n %rep %%xmm_regs_on_stack\n movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro WIN64_SPILL_XMM 1\n %assign xmm_regs_used %1\n ASSERT xmm_regs_used <= 16 + high_mm_regs\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.\n %assign %%pad %%xmm_regs_on_stack*16 + 32\n %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))\n SUB rsp, stack_size_padded\n %endif\n WIN64_PUSH_XMM\n%endmacro\n\n%macro WIN64_RESTORE_XMM_INTERNAL 0\n %assign %%pad_size 0\n %assign %%xmm_regs_on_stack xmm_regs_used - high_mm_regs - 8\n %if %%xmm_regs_on_stack > 0\n %assign %%i xmm_regs_used - high_mm_regs\n %rep %%xmm_regs_on_stack\n %assign %%i %%i-1\n movaps xmm %+ %%i, [rsp + (%%i-8)*16 + stack_size + 32]\n %endrep\n %endif\n %if stack_size_padded > 0\n %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %assign %%pad_size stack_size_padded\n %endif\n %endif\n %if xmm_regs_used > 7 + high_mm_regs\n movaps xmm7, [rsp + stack_offset - %%pad_size + 24]\n %endif\n %if xmm_regs_used > 6 + high_mm_regs\n movaps xmm6, [rsp + stack_offset - %%pad_size + 8]\n %endif\n%endmacro\n\n%macro WIN64_RESTORE_XMM 0\n WIN64_RESTORE_XMM_INTERNAL\n %assign stack_offset (stack_offset-stack_size_padded)\n %assign stack_size_padded 0\n %assign xmm_regs_used 0\n%endmacro\n\n%define has_epilogue regs_used > 7 || stack_size > 0 || vzeroupper_required || xmm_regs_used > 6+high_mm_regs\n\n%macro RET 0\n WIN64_RESTORE_XMM_INTERNAL\n POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%elif ARCH_X86_64 ; *nix x64 ;=============================================\n\nDECLARE_REG 0, rdi\nDECLARE_REG 1, rsi\nDECLARE_REG 2, rdx\nDECLARE_REG 3, rcx\nDECLARE_REG 4, R8\nDECLARE_REG 5, R9\nDECLARE_REG 6, rax, 8\nDECLARE_REG 7, R10, 16\nDECLARE_REG 8, R11, 24\nDECLARE_REG 9, rbx, 32\nDECLARE_REG 10, rbp, 40\nDECLARE_REG 11, R14, 48\nDECLARE_REG 12, R15, 56\nDECLARE_REG 13, R12, 64\nDECLARE_REG 14, R13, 72\n\n%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n %assign xmm_regs_used %3\n ASSERT regs_used >= num_args\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 15\n PUSH_IF_USED 9, 10, 11, 12, 13, 14\n ALLOC_STACK %4\n LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 9 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 14, 13, 12, 11, 10, 9\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%else ; X86_32 ;==============================================================\n\nDECLARE_REG 0, eax, 4\nDECLARE_REG 1, ecx, 8\nDECLARE_REG 2, edx, 12\nDECLARE_REG 3, ebx, 16\nDECLARE_REG 4, esi, 20\nDECLARE_REG 5, edi, 24\nDECLARE_REG 6, ebp, 28\n%define rsp esp\n\n%macro DECLARE_ARG 1-*\n %rep %0\n %define r%1m [rstk + stack_offset + 4*%1 + 4]\n %define r%1mp dword r%1m\n %rotate 1\n %endrep\n%endmacro\n\nDECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14\n\n%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...\n %assign num_args %1\n %assign regs_used %2\n ASSERT regs_used >= num_args\n %if num_args > 7\n %assign num_args 7\n %endif\n %if regs_used > 7\n %assign regs_used 7\n %endif\n SETUP_STACK_POINTER %4\n ASSERT regs_used <= 7\n PUSH_IF_USED 3, 4, 5, 6\n ALLOC_STACK %4\n LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6\n DEFINE_ARGS_INTERNAL %0, %4, %5\n%endmacro\n\n%define has_epilogue regs_used > 3 || stack_size > 0 || vzeroupper_required\n\n%macro RET 0\n %if stack_size_padded > 0\n %if required_stack_alignment > STACK_ALIGNMENT\n mov rsp, rstkm\n %else\n add rsp, stack_size_padded\n %endif\n %endif\n POP_IF_USED 6, 5, 4, 3\n %if vzeroupper_required\n vzeroupper\n %endif\n AUTO_REP_RET\n%endmacro\n\n%endif ;======================================================================\n\n%if WIN64 == 0\n %macro WIN64_SPILL_XMM 1\n %endmacro\n %macro WIN64_RESTORE_XMM 0\n %endmacro\n %macro WIN64_PUSH_XMM 0\n %endmacro\n%endif\n\n; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either\n; a branch or a branch target. So switch to a 2-byte form of ret in that case.\n; We can automatically detect \"follows a branch\", but not a branch target.\n; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)\n%macro REP_RET 0\n %if has_epilogue || cpuflag(ssse3)\n RET\n %else\n rep ret\n %endif\n annotate_function_size\n%endmacro\n\n%define last_branch_adr $$\n%macro AUTO_REP_RET 0\n %if notcpuflag(ssse3)\n times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.\n %endif\n ret\n annotate_function_size\n%endmacro\n\n%macro BRANCH_INSTR 0-*\n %rep %0\n %macro %1 1-2 %1\n %2 %1\n %if notcpuflag(ssse3)\n %%branch_instr equ $\n %xdefine last_branch_adr %%branch_instr\n %endif\n %endmacro\n %rotate 1\n %endrep\n%endmacro\n\nBRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp\n\n%macro TAIL_CALL 1-2 1 ; callee, is_nonadjacent\n %if has_epilogue\n call %1\n RET\n %elif %2\n jmp %1\n %endif\n annotate_function_size\n%endmacro\n\n;=============================================================================\n; arch-independent part\n;=============================================================================\n\n%assign function_align 16\n\n; Begin a function.\n; Applies any symbol mangling needed for C linkage, and sets up a define such that\n; subsequent uses of the function name automatically refer to the mangled version.\n; Appends cpuflags to the function name if cpuflags has been specified.\n; The \"\" empty default parameter is a workaround for nasm, which fails if SUFFIX\n; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).\n%macro cglobal 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 1, %1 %+ SUFFIX, %2\n%endmacro\n%macro cvisible 1-2+ \"\" ; name, [PROLOGUE args]\n cglobal_internal 0, %1 %+ SUFFIX, %2\n%endmacro\n%macro cglobal_internal 2-3+\n annotate_function_size\n %ifndef cglobaled_%2\n %if %1\n %xdefine %2 mangle(private_prefix %+ _ %+ %2)\n %else\n %xdefine %2 mangle(public_prefix %+ _ %+ %2)\n %endif\n %xdefine %2.skip_prologue %2 %+ .skip_prologue\n CAT_XDEFINE cglobaled_, %2, 1\n %endif\n %xdefine current_function %2\n %xdefine current_function_section __SECT__\n %if FORMAT_ELF\n %if %1\n global %2:function hidden\n %else\n global %2:function\n %endif\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN && %1\n global %2:private_extern\n %else\n global %2\n %endif\n align function_align\n %2:\n RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer\n %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required\n %assign stack_offset 0 ; stack pointer offset relative to the return address\n %assign stack_size 0 ; amount of stack space that can be freely used inside a function\n %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding\n %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64 and vzeroupper\n %ifnidn %3, \"\"\n PROLOGUE %3\n %endif\n%endmacro\n\n; Create a global symbol from a local label with the correct name mangling and type\n%macro cglobal_label 1\n %if FORMAT_ELF\n global current_function %+ %1:function hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global current_function %+ %1:private_extern\n %else\n global current_function %+ %1\n %endif\n %1:\n%endmacro\n\n%macro cextern 1\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n; like cextern, but without the prefix\n%macro cextern_naked 1\n %ifdef PREFIX\n %xdefine %1 mangle(%1)\n %endif\n CAT_XDEFINE cglobaled_, %1, 1\n extern %1\n%endmacro\n\n%macro const 1-2+\n %xdefine %1 mangle(private_prefix %+ _ %+ %1)\n %if FORMAT_ELF\n global %1:data hidden\n %elif FORMAT_MACHO && HAVE_PRIVATE_EXTERN\n global %1:private_extern\n %else\n global %1\n %endif\n %1: %2\n%endmacro\n\n; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.\n%if FORMAT_ELF\n [SECTION .note.GNU-stack noalloc noexec nowrite progbits]\n%endif\n\n; Tell debuggers how large the function was.\n; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.\n; This is invoked by RET and similar macros, and also cglobal does it for the previous function,\n; but if the last function in a source file doesn't use any of the standard macros for its epilogue,\n; then its size might be unspecified.\n%macro annotate_function_size 0\n %ifdef __YASM_VER__\n %ifdef current_function\n %if FORMAT_ELF\n current_function_section\n %%ecf equ $\n size current_function %%ecf - current_function\n __SECT__\n %endif\n %endif\n %endif\n%endmacro\n\n; cpuflags\n\n%assign cpuflags_mmx (1<<0)\n%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx\n%assign cpuflags_3dnow (1<<2) | cpuflags_mmx\n%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow\n%assign cpuflags_sse (1<<4) | cpuflags_mmx2\n%assign cpuflags_sse2 (1<<5) | cpuflags_sse\n%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2\n%assign cpuflags_lzcnt (1<<7) | cpuflags_sse2\n%assign cpuflags_sse3 (1<<8) | cpuflags_sse2\n%assign cpuflags_ssse3 (1<<9) | cpuflags_sse3\n%assign cpuflags_sse4 (1<<10) | cpuflags_ssse3\n%assign cpuflags_sse42 (1<<11) | cpuflags_sse4\n%assign cpuflags_aesni (1<<12) | cpuflags_sse42\n%assign cpuflags_gfni (1<<13) | cpuflags_sse42\n%assign cpuflags_avx (1<<14) | cpuflags_sse42\n%assign cpuflags_xop (1<<15) | cpuflags_avx\n%assign cpuflags_fma4 (1<<16) | cpuflags_avx\n%assign cpuflags_fma3 (1<<17) | cpuflags_avx\n%assign cpuflags_bmi1 (1<<18) | cpuflags_avx|cpuflags_lzcnt\n%assign cpuflags_bmi2 (1<<19) | cpuflags_bmi1\n%assign cpuflags_avx2 (1<<20) | cpuflags_fma3|cpuflags_bmi2\n%assign cpuflags_avx512 (1<<21) | cpuflags_avx2 ; F, CD, BW, DQ, VL\n%assign cpuflags_avx512icl (1<<22) | cpuflags_avx512|cpuflags_gfni ; VNNI, IFMA, VBMI, VBMI2, VPOPCNTDQ, BITALG, VAES, VPCLMULQDQ\n\n%assign cpuflags_cache32 (1<<23)\n%assign cpuflags_cache64 (1<<24)\n%assign cpuflags_aligned (1<<25) ; not a cpu feature, but a function variant\n%assign cpuflags_atom (1<<26)\n\n; Returns a boolean value expressing whether or not the specified cpuflag is enabled.\n%define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)\n%define notcpuflag(x) (cpuflag(x) ^ 1)\n\n; Takes an arbitrary number of cpuflags from the above list.\n; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.\n; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.\n%macro INIT_CPUFLAGS 0-*\n %xdefine SUFFIX\n %undef cpuname\n %assign cpuflags 0\n\n %if %0 >= 1\n %rep %0\n %ifdef cpuname\n %xdefine cpuname cpuname %+ _%1\n %else\n %xdefine cpuname %1\n %endif\n %assign cpuflags cpuflags | cpuflags_%1\n %rotate 1\n %endrep\n %xdefine SUFFIX _ %+ cpuname\n\n %if cpuflag(avx)\n %assign avx_enabled 1\n %endif\n %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))\n %define mova movaps\n %define movu movups\n %define movnta movntps\n %endif\n %if cpuflag(aligned)\n %define movu mova\n %elif cpuflag(sse3) && notcpuflag(ssse3)\n %define movu lddqu\n %endif\n %endif\n\n %if ARCH_X86_64 || cpuflag(sse2)\n %ifdef __NASM_VER__\n ALIGNMODE p6\n %else\n CPU amdnop\n %endif\n %else\n %ifdef __NASM_VER__\n ALIGNMODE nop\n %else\n CPU basicnop\n %endif\n %endif\n%endmacro\n\n; Merge mmx, sse*, and avx*\n; m# is a simd register of the currently selected size\n; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#\n; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#\n; zm# is the corresponding zmm register if mmsize >= 64, otherwise the same as m#\n; (All 4 remain in sync through SWAP.)\n\n%macro CAT_XDEFINE 3\n %xdefine %1%2 %3\n%endmacro\n\n%macro CAT_UNDEF 2\n %undef %1%2\n%endmacro\n\n%macro DEFINE_MMREGS 1 ; mmtype\n %assign %%prev_mmregs 0\n %ifdef num_mmregs\n %assign %%prev_mmregs num_mmregs\n %endif\n\n %assign num_mmregs 8\n %if ARCH_X86_64 && mmsize >= 16\n %assign num_mmregs 16\n %if cpuflag(avx512) || mmsize == 64\n %assign num_mmregs 32\n %endif\n %endif\n\n %assign %%i 0\n %rep num_mmregs\n CAT_XDEFINE m, %%i, %1 %+ %%i\n CAT_XDEFINE nn%1, %%i, %%i\n %assign %%i %%i+1\n %endrep\n %if %%prev_mmregs > num_mmregs\n %rep %%prev_mmregs - num_mmregs\n CAT_UNDEF m, %%i\n CAT_UNDEF nn %+ mmtype, %%i\n %assign %%i %%i+1\n %endrep\n %endif\n %xdefine mmtype %1\n%endmacro\n\n; Prefer registers 16-31 over 0-15 to avoid having to use vzeroupper\n%macro AVX512_MM_PERMUTATION 0-1 0 ; start_reg\n %if ARCH_X86_64 && cpuflag(avx512)\n %assign %%i %1\n %rep 16-%1\n %assign %%i_high %%i+16\n SWAP %%i, %%i_high\n %assign %%i %%i+1\n %endrep\n %endif\n%endmacro\n\n%macro INIT_MMX 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_MMX %1\n %define mmsize 8\n %define mova movq\n %define movu movq\n %define movh movd\n %define movnta movntq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS mm\n%endmacro\n\n%macro INIT_XMM 0-1+\n %assign avx_enabled 0\n %define RESET_MM_PERMUTATION INIT_XMM %1\n %define mmsize 16\n %define mova movdqa\n %define movu movdqu\n %define movh movq\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS xmm\n %if WIN64\n AVX512_MM_PERMUTATION 6 ; Swap callee-saved registers with volatile registers\n %endif\n%endmacro\n\n%macro INIT_YMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_YMM %1\n %define mmsize 32\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS ymm\n AVX512_MM_PERMUTATION\n%endmacro\n\n%macro INIT_ZMM 0-1+\n %assign avx_enabled 1\n %define RESET_MM_PERMUTATION INIT_ZMM %1\n %define mmsize 64\n %define mova movdqa\n %define movu movdqu\n %undef movh\n %define movnta movntdq\n INIT_CPUFLAGS %1\n DEFINE_MMREGS zmm\n AVX512_MM_PERMUTATION\n%endmacro\n\nINIT_XMM\n\n%macro DECLARE_MMCAST 1\n %define mmmm%1 mm%1\n %define mmxmm%1 mm%1\n %define mmymm%1 mm%1\n %define mmzmm%1 mm%1\n %define xmmmm%1 mm%1\n %define xmmxmm%1 xmm%1\n %define xmmymm%1 xmm%1\n %define xmmzmm%1 xmm%1\n %define ymmmm%1 mm%1\n %define ymmxmm%1 xmm%1\n %define ymmymm%1 ymm%1\n %define ymmzmm%1 ymm%1\n %define zmmmm%1 mm%1\n %define zmmxmm%1 xmm%1\n %define zmmymm%1 ymm%1\n %define zmmzmm%1 zmm%1\n %define xm%1 xmm %+ m%1\n %define ym%1 ymm %+ m%1\n %define zm%1 zmm %+ m%1\n%endmacro\n\n%assign i 0\n%rep 32\n DECLARE_MMCAST i\n %assign i i+1\n%endrep\n\n; I often want to use macros that permute their arguments. e.g. there's no\n; efficient way to implement butterfly or transpose or dct without swapping some\n; arguments.\n;\n; I would like to not have to manually keep track of the permutations:\n; If I insert a permutation in the middle of a function, it should automatically\n; change everything that follows. For more complex macros I may also have multiple\n; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.\n;\n; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that\n; permutes its arguments. It's equivalent to exchanging the contents of the\n; registers, except that this way you exchange the register names instead, so it\n; doesn't cost any cycles.\n\n%macro PERMUTE 2-* ; takes a list of pairs to swap\n %rep %0/2\n %xdefine %%tmp%2 m%2\n %rotate 2\n %endrep\n %rep %0/2\n %xdefine m%1 %%tmp%2\n CAT_XDEFINE nn, m%1, %1\n %rotate 2\n %endrep\n%endmacro\n\n%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)\n %ifnum %1 ; SWAP 0, 1, ...\n SWAP_INTERNAL_NUM %1, %2\n %else ; SWAP m0, m1, ...\n SWAP_INTERNAL_NAME %1, %2\n %endif\n%endmacro\n\n%macro SWAP_INTERNAL_NUM 2-*\n %rep %0-1\n %xdefine %%tmp m%1\n %xdefine m%1 m%2\n %xdefine m%2 %%tmp\n CAT_XDEFINE nn, m%1, %1\n CAT_XDEFINE nn, m%2, %2\n %rotate 1\n %endrep\n%endmacro\n\n%macro SWAP_INTERNAL_NAME 2-*\n %xdefine %%args nn %+ %1\n %rep %0-1\n %xdefine %%args %%args, nn %+ %2\n %rotate 1\n %endrep\n SWAP_INTERNAL_NUM %%args\n%endmacro\n\n; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later\n; calls to that function will automatically load the permutation, so values can\n; be returned in mmregs.\n%macro SAVE_MM_PERMUTATION 0-1\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp m %+ %%i\n CAT_XDEFINE %%f, %%i, regnumof %+ %%tmp\n %assign %%i %%i+1\n %endrep\n%endmacro\n\n%macro LOAD_MM_PERMUTATION 0-1 ; name to load from\n %if %0\n %xdefine %%f %1_m\n %else\n %xdefine %%f current_function %+ _m\n %endif\n %xdefine %%tmp %%f %+ 0\n %ifnum %%tmp\n RESET_MM_PERMUTATION\n AVX512_MM_PERMUTATION\n %assign %%i 0\n %rep num_mmregs\n %xdefine %%tmp %%f %+ %%i\n CAT_XDEFINE %%m, %%i, m %+ %%tmp\n %assign %%i %%i+1\n %endrep\n %rep num_mmregs\n %assign %%i %%i-1\n CAT_XDEFINE m, %%i, %%m %+ %%i\n CAT_XDEFINE nn, m %+ %%i, %%i\n %endrep\n %endif\n%endmacro\n\n; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't\n%macro call 1\n %ifid %1\n call_internal %1 %+ SUFFIX, %1\n %else\n call %1\n %endif\n%endmacro\n%macro call_internal 2\n %xdefine %%i %2\n %ifndef cglobaled_%2\n %ifdef cglobaled_%1\n %xdefine %%i %1\n %endif\n %endif\n call %%i\n LOAD_MM_PERMUTATION %%i\n%endmacro\n\n; Substitutions that reduce instruction size but are functionally equivalent\n%macro add 2\n %ifnum %2\n %if %2==128\n sub %1, -128\n %else\n add %1, %2\n %endif\n %else\n add %1, %2\n %endif\n%endmacro\n\n%macro sub 2\n %ifnum %2\n %if %2==128\n add %1, -128\n %else\n sub %1, %2\n %endif\n %else\n sub %1, %2\n %endif\n%endmacro\n\n;=============================================================================\n; AVX abstraction layer\n;=============================================================================\n\n%assign i 0\n%rep 32\n %if i < 8\n CAT_XDEFINE sizeofmm, i, 8\n CAT_XDEFINE regnumofmm, i, i\n %endif\n CAT_XDEFINE sizeofxmm, i, 16\n CAT_XDEFINE sizeofymm, i, 32\n CAT_XDEFINE sizeofzmm, i, 64\n CAT_XDEFINE regnumofxmm, i, i\n CAT_XDEFINE regnumofymm, i, i\n CAT_XDEFINE regnumofzmm, i, i\n %assign i i+1\n%endrep\n%undef i\n\n%macro CHECK_AVX_INSTR_EMU 3-*\n %xdefine %%opcode %1\n %xdefine %%dst %2\n %rep %0-2\n %ifidn %%dst, %3\n %error non-avx emulation of ``%%opcode'' is not supported\n %endif\n %rotate 1\n %endrep\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n;%6+: operands\n%macro RUN_AVX_INSTR 6-9+\n %ifnum sizeof%7\n %assign __sizeofreg sizeof%7\n %elifnum sizeof%6\n %assign __sizeofreg sizeof%6\n %else\n %assign __sizeofreg mmsize\n %endif\n %assign __emulate_avx 0\n %if avx_enabled && __sizeofreg >= 16\n %xdefine __instr v%1\n %else\n %xdefine __instr %1\n %if %0 >= 8+%4\n %assign __emulate_avx 1\n %endif\n %endif\n %ifnidn %2, fnord\n %ifdef cpuname\n %if notcpuflag(%2)\n %error use of ``%1'' %2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 16 && notcpuflag(sse2)\n %error use of ``%1'' sse2 instruction in cpuname function: current_function\n %elif %3 == 0 && __sizeofreg == 32 && notcpuflag(avx2)\n %error use of ``%1'' avx2 instruction in cpuname function: current_function\n %elifidn %1, pextrw ; special case because the base instruction is mmx2,\n %ifnid %6 ; but sse4 is required for memory operands\n %if notcpuflag(sse4)\n %error use of ``%1'' sse4 instruction in cpuname function: current_function\n %endif\n %endif\n %endif\n %endif\n %endif\n\n %if __emulate_avx\n %xdefine __src1 %7\n %xdefine __src2 %8\n %if %5 && %4 == 0\n %ifnidn %6, %7\n %ifidn %6, %8\n %xdefine __src1 %8\n %xdefine __src2 %7\n %elifnnum sizeof%8\n ; 3-operand AVX instructions with a memory arg can only have it in src2,\n ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).\n ; So, if the instruction is commutative with a memory arg, swap them.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n %ifnidn %6, __src1\n %if %0 >= 9\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, __src2, %9\n %else\n CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, __src2\n %endif\n %if __sizeofreg == 8\n MOVQ %6, __src1\n %elif %3\n MOVAPS %6, __src1\n %else\n MOVDQA %6, __src1\n %endif\n %endif\n %if %0 >= 9\n %1 %6, __src2, %9\n %else\n %1 %6, __src2\n %endif\n %elif %0 >= 9\n __instr %6, %7, %8, %9\n %elif %0 == 8\n %if avx_enabled && %5\n %xdefine __src1 %7\n %xdefine __src2 %8\n %ifnum regnumof%7\n %ifnum regnumof%8\n %if regnumof%7 < 8 && regnumof%8 >= 8 && regnumof%8 < 16 && sizeof%8 <= 32\n ; Most VEX-encoded instructions require an additional byte to encode when\n ; src2 is a high register (e.g. m8..15). If the instruction is commutative\n ; we can swap src1 and src2 when doing so reduces the instruction length.\n %xdefine __src1 %8\n %xdefine __src2 %7\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7, %8\n %endif\n %elif %0 == 7\n %if avx_enabled && %5\n %xdefine __src1 %6\n %xdefine __src2 %7\n %ifnum regnumof%6\n %ifnum regnumof%7\n %if regnumof%6 < 8 && regnumof%7 >= 8 && regnumof%7 < 16 && sizeof%7 <= 32\n %xdefine __src1 %7\n %xdefine __src2 %6\n %endif\n %endif\n %endif\n __instr %6, __src1, __src2\n %else\n __instr %6, %7\n %endif\n %else\n __instr %6\n %endif\n%endmacro\n\n;%1 == instruction\n;%2 == minimal instruction set\n;%3 == 1 if float, 0 if int\n;%4 == 1 if 4-operand emulation, 0 if 3-operand emulation, 255 otherwise (no emulation)\n;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not\n%macro AVX_INSTR 1-5 fnord, 0, 255, 0\n %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5\n %ifidn %2, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1\n %elifidn %3, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2\n %elifidn %4, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3\n %elifidn %5, fnord\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4\n %else\n RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5\n %endif\n %endmacro\n%endmacro\n\n; Instructions with both VEX/EVEX and legacy encodings\n; Non-destructive instructions are written without parameters\nAVX_INSTR addpd, sse2, 1, 0, 1\nAVX_INSTR addps, sse, 1, 0, 1\nAVX_INSTR addsd, sse2, 1, 0, 0\nAVX_INSTR addss, sse, 1, 0, 0\nAVX_INSTR addsubpd, sse3, 1, 0, 0\nAVX_INSTR addsubps, sse3, 1, 0, 0\nAVX_INSTR aesdec, aesni, 0, 0, 0\nAVX_INSTR aesdeclast, aesni, 0, 0, 0\nAVX_INSTR aesenc, aesni, 0, 0, 0\nAVX_INSTR aesenclast, aesni, 0, 0, 0\nAVX_INSTR aesimc, aesni\nAVX_INSTR aeskeygenassist, aesni\nAVX_INSTR andnpd, sse2, 1, 0, 0\nAVX_INSTR andnps, sse, 1, 0, 0\nAVX_INSTR andpd, sse2, 1, 0, 1\nAVX_INSTR andps, sse, 1, 0, 1\nAVX_INSTR blendpd, sse4, 1, 1, 0\nAVX_INSTR blendps, sse4, 1, 1, 0\nAVX_INSTR blendvpd, sse4 ; can't be emulated\nAVX_INSTR blendvps, sse4 ; can't be emulated\nAVX_INSTR cmpeqpd, sse2, 1, 0, 1\nAVX_INSTR cmpeqps, sse, 1, 0, 1\nAVX_INSTR cmpeqsd, sse2, 1, 0, 0\nAVX_INSTR cmpeqss, sse, 1, 0, 0\nAVX_INSTR cmplepd, sse2, 1, 0, 0\nAVX_INSTR cmpleps, sse, 1, 0, 0\nAVX_INSTR cmplesd, sse2, 1, 0, 0\nAVX_INSTR cmpless, sse, 1, 0, 0\nAVX_INSTR cmpltpd, sse2, 1, 0, 0\nAVX_INSTR cmpltps, sse, 1, 0, 0\nAVX_INSTR cmpltsd, sse2, 1, 0, 0\nAVX_INSTR cmpltss, sse, 1, 0, 0\nAVX_INSTR cmpneqpd, sse2, 1, 0, 1\nAVX_INSTR cmpneqps, sse, 1, 0, 1\nAVX_INSTR cmpneqsd, sse2, 1, 0, 0\nAVX_INSTR cmpneqss, sse, 1, 0, 0\nAVX_INSTR cmpnlepd, sse2, 1, 0, 0\nAVX_INSTR cmpnleps, sse, 1, 0, 0\nAVX_INSTR cmpnlesd, sse2, 1, 0, 0\nAVX_INSTR cmpnless, sse, 1, 0, 0\nAVX_INSTR cmpnltpd, sse2, 1, 0, 0\nAVX_INSTR cmpnltps, sse, 1, 0, 0\nAVX_INSTR cmpnltsd, sse2, 1, 0, 0\nAVX_INSTR cmpnltss, sse, 1, 0, 0\nAVX_INSTR cmpordpd, sse2 1, 0, 1\nAVX_INSTR cmpordps, sse 1, 0, 1\nAVX_INSTR cmpordsd, sse2 1, 0, 0\nAVX_INSTR cmpordss, sse 1, 0, 0\nAVX_INSTR cmppd, sse2, 1, 1, 0\nAVX_INSTR cmpps, sse, 1, 1, 0\nAVX_INSTR cmpsd, sse2, 1, 1, 0\nAVX_INSTR cmpss, sse, 1, 1, 0\nAVX_INSTR cmpunordpd, sse2, 1, 0, 1\nAVX_INSTR cmpunordps, sse, 1, 0, 1\nAVX_INSTR cmpunordsd, sse2, 1, 0, 0\nAVX_INSTR cmpunordss, sse, 1, 0, 0\nAVX_INSTR comisd, sse2, 1\nAVX_INSTR comiss, sse, 1\nAVX_INSTR cvtdq2pd, sse2, 1\nAVX_INSTR cvtdq2ps, sse2, 1\nAVX_INSTR cvtpd2dq, sse2, 1\nAVX_INSTR cvtpd2ps, sse2, 1\nAVX_INSTR cvtps2dq, sse2, 1\nAVX_INSTR cvtps2pd, sse2, 1\nAVX_INSTR cvtsd2si, sse2, 1\nAVX_INSTR cvtsd2ss, sse2, 1, 0, 0\nAVX_INSTR cvtsi2sd, sse2, 1, 0, 0\nAVX_INSTR cvtsi2ss, sse, 1, 0, 0\nAVX_INSTR cvtss2sd, sse2, 1, 0, 0\nAVX_INSTR cvtss2si, sse, 1\nAVX_INSTR cvttpd2dq, sse2, 1\nAVX_INSTR cvttps2dq, sse2, 1\nAVX_INSTR cvttsd2si, sse2, 1\nAVX_INSTR cvttss2si, sse, 1\nAVX_INSTR divpd, sse2, 1, 0, 0\nAVX_INSTR divps, sse, 1, 0, 0\nAVX_INSTR divsd, sse2, 1, 0, 0\nAVX_INSTR divss, sse, 1, 0, 0\nAVX_INSTR dppd, sse4, 1, 1, 0\nAVX_INSTR dpps, sse4, 1, 1, 0\nAVX_INSTR extractps, sse4, 1\nAVX_INSTR gf2p8affineinvqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8affineqb, gfni, 0, 1, 0\nAVX_INSTR gf2p8mulb, gfni, 0, 0, 0\nAVX_INSTR haddpd, sse3, 1, 0, 0\nAVX_INSTR haddps, sse3, 1, 0, 0\nAVX_INSTR hsubpd, sse3, 1, 0, 0\nAVX_INSTR hsubps, sse3, 1, 0, 0\nAVX_INSTR insertps, sse4, 1, 1, 0\nAVX_INSTR lddqu, sse3\nAVX_INSTR ldmxcsr, sse, 1\nAVX_INSTR maskmovdqu, sse2\nAVX_INSTR maxpd, sse2, 1, 0, 1\nAVX_INSTR maxps, sse, 1, 0, 1\nAVX_INSTR maxsd, sse2, 1, 0, 0\nAVX_INSTR maxss, sse, 1, 0, 0\nAVX_INSTR minpd, sse2, 1, 0, 1\nAVX_INSTR minps, sse, 1, 0, 1\nAVX_INSTR minsd, sse2, 1, 0, 0\nAVX_INSTR minss, sse, 1, 0, 0\nAVX_INSTR movapd, sse2, 1\nAVX_INSTR movaps, sse, 1\nAVX_INSTR movd, mmx\nAVX_INSTR movddup, sse3, 1\nAVX_INSTR movdqa, sse2\nAVX_INSTR movdqu, sse2\nAVX_INSTR movhlps, sse, 1, 0, 0\nAVX_INSTR movhpd, sse2, 1, 0, 0\nAVX_INSTR movhps, sse, 1, 0, 0\nAVX_INSTR movlhps, sse, 1, 0, 0\nAVX_INSTR movlpd, sse2, 1, 0, 0\nAVX_INSTR movlps, sse, 1, 0, 0\nAVX_INSTR movmskpd, sse2, 1\nAVX_INSTR movmskps, sse, 1\nAVX_INSTR movntdq, sse2\nAVX_INSTR movntdqa, sse4\nAVX_INSTR movntpd, sse2, 1\nAVX_INSTR movntps, sse, 1\nAVX_INSTR movq, mmx\nAVX_INSTR movsd, sse2, 1, 0, 0\nAVX_INSTR movshdup, sse3, 1\nAVX_INSTR movsldup, sse3, 1\nAVX_INSTR movss, sse, 1, 0, 0\nAVX_INSTR movupd, sse2, 1\nAVX_INSTR movups, sse, 1\nAVX_INSTR mpsadbw, sse4, 0, 1, 0\nAVX_INSTR mulpd, sse2, 1, 0, 1\nAVX_INSTR mulps, sse, 1, 0, 1\nAVX_INSTR mulsd, sse2, 1, 0, 0\nAVX_INSTR mulss, sse, 1, 0, 0\nAVX_INSTR orpd, sse2, 1, 0, 1\nAVX_INSTR orps, sse, 1, 0, 1\nAVX_INSTR pabsb, ssse3\nAVX_INSTR pabsd, ssse3\nAVX_INSTR pabsw, ssse3\nAVX_INSTR packsswb, mmx, 0, 0, 0\nAVX_INSTR packssdw, mmx, 0, 0, 0\nAVX_INSTR packuswb, mmx, 0, 0, 0\nAVX_INSTR packusdw, sse4, 0, 0, 0\nAVX_INSTR paddb, mmx, 0, 0, 1\nAVX_INSTR paddw, mmx, 0, 0, 1\nAVX_INSTR paddd, mmx, 0, 0, 1\nAVX_INSTR paddq, sse2, 0, 0, 1\nAVX_INSTR paddsb, mmx, 0, 0, 1\nAVX_INSTR paddsw, mmx, 0, 0, 1\nAVX_INSTR paddusb, mmx, 0, 0, 1\nAVX_INSTR paddusw, mmx, 0, 0, 1\nAVX_INSTR palignr, ssse3, 0, 1, 0\nAVX_INSTR pand, mmx, 0, 0, 1\nAVX_INSTR pandn, mmx, 0, 0, 0\nAVX_INSTR pavgb, mmx2, 0, 0, 1\nAVX_INSTR pavgw, mmx2, 0, 0, 1\nAVX_INSTR pblendvb, sse4 ; can't be emulated\nAVX_INSTR pblendw, sse4, 0, 1, 0\nAVX_INSTR pclmulqdq, fnord, 0, 1, 0\nAVX_INSTR pclmulhqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmulhqlqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqhqdq, fnord, 0, 0, 0\nAVX_INSTR pclmullqlqdq, fnord, 0, 0, 0\nAVX_INSTR pcmpestri, sse42\nAVX_INSTR pcmpestrm, sse42\nAVX_INSTR pcmpistri, sse42\nAVX_INSTR pcmpistrm, sse42\nAVX_INSTR pcmpeqb, mmx, 0, 0, 1\nAVX_INSTR pcmpeqw, mmx, 0, 0, 1\nAVX_INSTR pcmpeqd, mmx, 0, 0, 1\nAVX_INSTR pcmpeqq, sse4, 0, 0, 1\nAVX_INSTR pcmpgtb, mmx, 0, 0, 0\nAVX_INSTR pcmpgtw, mmx, 0, 0, 0\nAVX_INSTR pcmpgtd, mmx, 0, 0, 0\nAVX_INSTR pcmpgtq, sse42, 0, 0, 0\nAVX_INSTR pextrb, sse4\nAVX_INSTR pextrd, sse4\nAVX_INSTR pextrq, sse4\nAVX_INSTR pextrw, mmx2\nAVX_INSTR phaddw, ssse3, 0, 0, 0\nAVX_INSTR phaddd, ssse3, 0, 0, 0\nAVX_INSTR phaddsw, ssse3, 0, 0, 0\nAVX_INSTR phminposuw, sse4\nAVX_INSTR phsubw, ssse3, 0, 0, 0\nAVX_INSTR phsubd, ssse3, 0, 0, 0\nAVX_INSTR phsubsw, ssse3, 0, 0, 0\nAVX_INSTR pinsrb, sse4, 0, 1, 0\nAVX_INSTR pinsrd, sse4, 0, 1, 0\nAVX_INSTR pinsrq, sse4, 0, 1, 0\nAVX_INSTR pinsrw, mmx2, 0, 1, 0\nAVX_INSTR pmaddwd, mmx, 0, 0, 1\nAVX_INSTR pmaddubsw, ssse3, 0, 0, 0\nAVX_INSTR pmaxsb, sse4, 0, 0, 1\nAVX_INSTR pmaxsw, mmx2, 0, 0, 1\nAVX_INSTR pmaxsd, sse4, 0, 0, 1\nAVX_INSTR pmaxub, mmx2, 0, 0, 1\nAVX_INSTR pmaxuw, sse4, 0, 0, 1\nAVX_INSTR pmaxud, sse4, 0, 0, 1\nAVX_INSTR pminsb, sse4, 0, 0, 1\nAVX_INSTR pminsw, mmx2, 0, 0, 1\nAVX_INSTR pminsd, sse4, 0, 0, 1\nAVX_INSTR pminub, mmx2, 0, 0, 1\nAVX_INSTR pminuw, sse4, 0, 0, 1\nAVX_INSTR pminud, sse4, 0, 0, 1\nAVX_INSTR pmovmskb, mmx2\nAVX_INSTR pmovsxbw, sse4\nAVX_INSTR pmovsxbd, sse4\nAVX_INSTR pmovsxbq, sse4\nAVX_INSTR pmovsxwd, sse4\nAVX_INSTR pmovsxwq, sse4\nAVX_INSTR pmovsxdq, sse4\nAVX_INSTR pmovzxbw, sse4\nAVX_INSTR pmovzxbd, sse4\nAVX_INSTR pmovzxbq, sse4\nAVX_INSTR pmovzxwd, sse4\nAVX_INSTR pmovzxwq, sse4\nAVX_INSTR pmovzxdq, sse4\nAVX_INSTR pmuldq, sse4, 0, 0, 1\nAVX_INSTR pmulhrsw, ssse3, 0, 0, 1\nAVX_INSTR pmulhuw, mmx2, 0, 0, 1\nAVX_INSTR pmulhw, mmx, 0, 0, 1\nAVX_INSTR pmullw, mmx, 0, 0, 1\nAVX_INSTR pmulld, sse4, 0, 0, 1\nAVX_INSTR pmuludq, sse2, 0, 0, 1\nAVX_INSTR por, mmx, 0, 0, 1\nAVX_INSTR psadbw, mmx2, 0, 0, 1\nAVX_INSTR pshufb, ssse3, 0, 0, 0\nAVX_INSTR pshufd, sse2\nAVX_INSTR pshufhw, sse2\nAVX_INSTR pshuflw, sse2\nAVX_INSTR psignb, ssse3, 0, 0, 0\nAVX_INSTR psignw, ssse3, 0, 0, 0\nAVX_INSTR psignd, ssse3, 0, 0, 0\nAVX_INSTR psllw, mmx, 0, 0, 0\nAVX_INSTR pslld, mmx, 0, 0, 0\nAVX_INSTR psllq, mmx, 0, 0, 0\nAVX_INSTR pslldq, sse2, 0, 0, 0\nAVX_INSTR psraw, mmx, 0, 0, 0\nAVX_INSTR psrad, mmx, 0, 0, 0\nAVX_INSTR psrlw, mmx, 0, 0, 0\nAVX_INSTR psrld, mmx, 0, 0, 0\nAVX_INSTR psrlq, mmx, 0, 0, 0\nAVX_INSTR psrldq, sse2, 0, 0, 0\nAVX_INSTR psubb, mmx, 0, 0, 0\nAVX_INSTR psubw, mmx, 0, 0, 0\nAVX_INSTR psubd, mmx, 0, 0, 0\nAVX_INSTR psubq, sse2, 0, 0, 0\nAVX_INSTR psubsb, mmx, 0, 0, 0\nAVX_INSTR psubsw, mmx, 0, 0, 0\nAVX_INSTR psubusb, mmx, 0, 0, 0\nAVX_INSTR psubusw, mmx, 0, 0, 0\nAVX_INSTR ptest, sse4\nAVX_INSTR punpckhbw, mmx, 0, 0, 0\nAVX_INSTR punpckhwd, mmx, 0, 0, 0\nAVX_INSTR punpckhdq, mmx, 0, 0, 0\nAVX_INSTR punpckhqdq, sse2, 0, 0, 0\nAVX_INSTR punpcklbw, mmx, 0, 0, 0\nAVX_INSTR punpcklwd, mmx, 0, 0, 0\nAVX_INSTR punpckldq, mmx, 0, 0, 0\nAVX_INSTR punpcklqdq, sse2, 0, 0, 0\nAVX_INSTR pxor, mmx, 0, 0, 1\nAVX_INSTR rcpps, sse, 1\nAVX_INSTR rcpss, sse, 1, 0, 0\nAVX_INSTR roundpd, sse4, 1\nAVX_INSTR roundps, sse4, 1\nAVX_INSTR roundsd, sse4, 1, 1, 0\nAVX_INSTR roundss, sse4, 1, 1, 0\nAVX_INSTR rsqrtps, sse, 1\nAVX_INSTR rsqrtss, sse, 1, 0, 0\nAVX_INSTR shufpd, sse2, 1, 1, 0\nAVX_INSTR shufps, sse, 1, 1, 0\nAVX_INSTR sqrtpd, sse2, 1\nAVX_INSTR sqrtps, sse, 1\nAVX_INSTR sqrtsd, sse2, 1, 0, 0\nAVX_INSTR sqrtss, sse, 1, 0, 0\nAVX_INSTR stmxcsr, sse, 1\nAVX_INSTR subpd, sse2, 1, 0, 0\nAVX_INSTR subps, sse, 1, 0, 0\nAVX_INSTR subsd, sse2, 1, 0, 0\nAVX_INSTR subss, sse, 1, 0, 0\nAVX_INSTR ucomisd, sse2, 1\nAVX_INSTR ucomiss, sse, 1\nAVX_INSTR unpckhpd, sse2, 1, 0, 0\nAVX_INSTR unpckhps, sse, 1, 0, 0\nAVX_INSTR unpcklpd, sse2, 1, 0, 0\nAVX_INSTR unpcklps, sse, 1, 0, 0\nAVX_INSTR xorpd, sse2, 1, 0, 1\nAVX_INSTR xorps, sse, 1, 0, 1\n\n; 3DNow instructions, for sharing code between AVX, SSE and 3DN\nAVX_INSTR pfadd, 3dnow, 1, 0, 1\nAVX_INSTR pfsub, 3dnow, 1, 0, 0\nAVX_INSTR pfmul, 3dnow, 1, 0, 1\n\n;%1 == instruction\n;%2 == minimal instruction set\n%macro GPR_INSTR 2\n %macro %1 2-5 fnord, %1, %2\n %ifdef cpuname\n %if notcpuflag(%5)\n %error use of ``%4'' %5 instruction in cpuname function: current_function\n %endif\n %endif\n %ifidn %3, fnord\n %4 %1, %2\n %else\n %4 %1, %2, %3\n %endif\n %endmacro\n%endmacro\n\nGPR_INSTR andn, bmi1\nGPR_INSTR bextr, bmi1\nGPR_INSTR blsi, bmi1\nGPR_INSTR blsmsk, bmi1\nGPR_INSTR bzhi, bmi2\nGPR_INSTR mulx, bmi2\nGPR_INSTR pdep, bmi2\nGPR_INSTR pext, bmi2\nGPR_INSTR popcnt, sse42\nGPR_INSTR rorx, bmi2\nGPR_INSTR sarx, bmi2\nGPR_INSTR shlx, bmi2\nGPR_INSTR shrx, bmi2\n\n; base-4 constants for shuffles\n%assign i 0\n%rep 256\n %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)\n %if j < 10\n CAT_XDEFINE q000, j, i\n %elif j < 100\n CAT_XDEFINE q00, j, i\n %elif j < 1000\n CAT_XDEFINE q0, j, i\n %else\n CAT_XDEFINE q, j, i\n %endif\n %assign i i+1\n%endrep\n%undef i\n%undef j\n\n%macro FMA_INSTR 3\n %macro %1 4-7 %1, %2, %3\n %if cpuflag(xop)\n v%5 %1, %2, %3, %4\n %elifnidn %1, %4\n %6 %1, %2, %3\n %7 %1, %4\n %else\n %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n%endmacro\n\nFMA_INSTR pmacsww, pmullw, paddw\nFMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation\nFMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation\nFMA_INSTR pmadcswd, pmaddwd, paddd\n\n; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.\n; FMA3 is only possible if dst is the same as one of the src registers.\n; Either src2 or src3 can be a memory operand.\n%macro FMA4_INSTR 2-*\n %push fma4_instr\n %xdefine %$prefix %1\n %rep %0 - 1\n %macro %$prefix%2 4-6 %$prefix, %2\n %if notcpuflag(fma3) && notcpuflag(fma4)\n %error use of ``%5%6'' fma instruction in cpuname function: current_function\n %elif cpuflag(fma4)\n v%5%6 %1, %2, %3, %4\n %elifidn %1, %2\n ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.\n %ifnum sizeof%3\n v%{5}213%6 %2, %3, %4\n %else\n v%{5}132%6 %2, %4, %3\n %endif\n %elifidn %1, %3\n v%{5}213%6 %3, %2, %4\n %elifidn %1, %4\n v%{5}231%6 %4, %2, %3\n %else\n %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported\n %endif\n %endmacro\n %rotate 1\n %endrep\n %pop\n%endmacro\n\nFMA4_INSTR fmadd, pd, ps, sd, ss\nFMA4_INSTR fmaddsub, pd, ps\nFMA4_INSTR fmsub, pd, ps, sd, ss\nFMA4_INSTR fmsubadd, pd, ps\nFMA4_INSTR fnmadd, pd, ps, sd, ss\nFMA4_INSTR fnmsub, pd, ps, sd, ss\n\n; Macros for converting VEX instructions to equivalent EVEX ones.\n%macro EVEX_INSTR 2-3 0 ; vex, evex, prefer_evex\n %macro %1 2-7 fnord, fnord, %1, %2, %3\n %ifidn %3, fnord\n %define %%args %1, %2\n %elifidn %4, fnord\n %define %%args %1, %2, %3\n %else\n %define %%args %1, %2, %3, %4\n %endif\n %assign %%evex_required cpuflag(avx512) & %7\n %ifnum regnumof%1\n %if regnumof%1 >= 16 || sizeof%1 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%2\n %if regnumof%2 >= 16 || sizeof%2 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %ifnum regnumof%3\n %if regnumof%3 >= 16 || sizeof%3 > 32\n %assign %%evex_required 1\n %endif\n %endif\n %if %%evex_required\n %6 %%args\n %else\n %5 %%args ; Prefer VEX over EVEX due to shorter instruction length\n %endif\n %endmacro\n%endmacro\n\nEVEX_INSTR vbroadcastf128, vbroadcastf32x4\nEVEX_INSTR vbroadcasti128, vbroadcasti32x4\nEVEX_INSTR vextractf128, vextractf32x4\nEVEX_INSTR vextracti128, vextracti32x4\nEVEX_INSTR vinsertf128, vinsertf32x4\nEVEX_INSTR vinserti128, vinserti32x4\nEVEX_INSTR vmovdqa, vmovdqa32\nEVEX_INSTR vmovdqu, vmovdqu32\nEVEX_INSTR vpand, vpandd\nEVEX_INSTR vpandn, vpandnd\nEVEX_INSTR vpor, vpord\nEVEX_INSTR vpxor, vpxord\nEVEX_INSTR vrcpps, vrcp14ps, 1 ; EVEX versions have higher precision\nEVEX_INSTR vrcpss, vrcp14ss, 1\nEVEX_INSTR vrsqrtps, vrsqrt14ps, 1\nEVEX_INSTR vrsqrtss, vrsqrt14ss, 1\n"}}},{"rowIdx":485,"cells":{"commit":{"kind":"string","value":"c8118d72c1c9d83a8be630bd4d5312241fc87582"},"subject":{"kind":"string","value":"x86: Add mc w_mask 4:2:0 AVX-512 (Ice Lake) asm"},"message":{"kind":"string","value":"x86: Add mc w_mask 4:2:0 AVX-512 (Ice Lake) asm\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/mc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nbidir_sctr_w4: dd 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\nwm_420_perm4: db 1, 3, 9, 11, 5, 7, 13, 15, 17, 19, 25, 27, 21, 23, 29, 31\n db 33, 35, 41, 43, 37, 39, 45, 47, 49, 51, 57, 59, 53, 55, 61, 63\n db 0, 2, 8, 10, 4, 6, 12, 14, 16, 18, 24, 26, 20, 22, 28, 30\n db 32, 34, 40, 42, 36, 38, 44, 46, 48, 50, 56, 58, 52, 54, 60, 62\nwm_420_perm8: db 1, 3, 17, 19, 5, 7, 21, 23, 9, 11, 25, 27, 13, 15, 29, 31\n db 33, 35, 49, 51, 37, 39, 53, 55, 41, 43, 57, 59, 45, 47, 61, 63\n db 0, 2, 16, 18, 4, 6, 20, 22, 8, 10, 24, 26, 12, 14, 28, 30\n db 32, 34, 48, 50, 36, 38, 52, 54, 40, 42, 56, 58, 44, 46, 60, 62\nwm_420_perm16: db 1, 3, 33, 35, 5, 7, 37, 39, 9, 11, 41, 43, 13, 15, 45, 47\n db 17, 19, 49, 51, 21, 23, 53, 55, 25, 27, 57, 59, 29, 31, 61, 63\n db 0, 2, 32, 34, 4, 6, 36, 38, 8, 10, 40, 42, 12, 14, 44, 46\n db 16, 18, 48, 50, 20, 22, 52, 54, 24, 26, 56, 58, 28, 30, 60, 62\nwm_420_mask: db 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63\n db 67, 71, 75, 79, 83, 87, 91, 95, 99,103,107,111,115,119,123,127\n db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\n db 65, 69, 73, 77, 81, 85, 89, 93, 97,101,105,109,113,117,121,125\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\nspel_h_perm16a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\nspel_h_perm16b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 36, 37, 38, 39, 37, 38, 39, 40, 38, 39, 40, 41, 39, 40, 41, 42\n db 44, 45, 46, 47, 45, 46, 47, 48, 46, 47, 48, 49, 47, 48, 49, 50\nspel_h_perm16c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\n db 48, 49, 50, 51, 49, 50, 51, 52, 50, 51, 52, 53, 51, 52, 53, 54\nspel_h_perm32a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\nspel_h_perm32b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 20, 21, 22, 23, 21, 22, 23, 24, 22, 23, 24, 25, 23, 24, 25, 26\n db 28, 29, 30, 31, 29, 30, 31, 32, 30, 31, 32, 33, 31, 32, 33, 34\nspel_h_perm32c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\nspel_hv_perm4a: db 8, 9, 16, 17, 10, 11, 18, 19, 12, 13, 20, 21, 14, 15, 22, 23\n db 16, 17, 24, 25, 18, 19, 26, 27, 20, 21, 28, 29, 22, 23, 30, 31\nspel_hv_perm4b: db 24, 25, 32, 33, 26, 27, 34, 35, 28, 29, 36, 37, 30, 31, 38, 39\n db 32, 33, 40, 41, 34, 35, 42, 43, 36, 37, 44, 45, 38, 39, 46, 47\n db 40, 41, 48, 49, 42, 43, 50, 51, 44, 45, 52, 53, 46, 47, 54, 55\n db 48, 49, 56, 57, 50, 51, 58, 59, 52, 53, 60, 61, 54, 55, 62, 63\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_v_shuf4: db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\nwm_420_perm64: dq 0xfedcba9876543210\nwm_420_sign: dd 0x01020102, 0x01010101\nwm_sign_avx512: dd 0x40804080, 0x40404040\n\npb_m64: times 4 db -64\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_2: dd 2\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\ncextern mc_warp_filter\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx512icl, 7, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx512icl, 4, 8, 16, 32, 64, 128\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro PREP_8TAP_H 0\n %if cpuflag(avx512)\n vpermb m10, m5, m0\n vpermb m11, m5, m1\n vpermb m12, m6, m0\n vpermb m13, m6, m1\n vpermb m14, m7, m0\n vpermb m15, m7, m1\n mova m0, m4\n mova m2, m4\n mova m1, m4\n mova m3, m4\n vpdpbusd m0, m10, m8\n vpdpbusd m2, m12, m8\n vpdpbusd m1, m11, m8\n vpdpbusd m3, m13, m8\n vpdpbusd m0, m12, m9\n vpdpbusd m2, m14, m9\n vpdpbusd m1, m13, m9\n vpdpbusd m3, m15, m9\n packssdw m0, m2\n packssdw m1, m3\n psraw m0, 2\n psraw m1, 2\n mova [tmpq+ 0], m0\n mova [tmpq+64], m1\n %else\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n pmaddubsw m1, m8\n pmaddubsw m0, m2, m8\n pmaddubsw m2, m9\n pmaddubsw m3, m9\n paddw m1, m2\n paddw m0, m3\n phaddw m0, m1, m0\n pmulhrsw m0, m4\n %endif\n%endmacro\n\n%macro PREP_8TAP_V_W4 5 ; round, weights\n movd xm0, [srcq+strideq*0]\n vpbroadcastd ym1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd ym3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd ym1, ym1, ym0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd ym3, ym3, ym2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd ym0, [srcq+strideq*0]\n vpbroadcastd ym2, [srcq+strideq*1]\n vpblendd ym1, ym1, ym0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd ym0, [srcq+strideq*2]\n vbroadcasti128 ym5, [deint_shuf4]\n vpblendd ym3, ym3, ym2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd ym2, ym3, ym1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd ym3, ym3, ym1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw ym1, ym2, ym3 ; 01 12 23 34\n vpblendd ym3, ym3, ym0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw ym2, ym3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym3, [srcq+strideq*0]\n vpbroadcastd ym4, [srcq+strideq*1]\n vpblendd ym3, ym3, ym4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd ym3, ym3, ym0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd ym0, [srcq+strideq*2]\n vpblendd ym3, ym3, ym0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb ym3, ym5 ; 67 78 89 9a\n pmaddubsw ym4, ym1, ym%2\n vperm2i128 ym1, ym2, ym3, 0x21 ; 45 56 67 78\n pmaddubsw ym2, ym%3\n paddw ym4, ym2\n mova ym2, ym3\n pmaddubsw ym3, ym%5\n paddw ym3, ym4\n pmaddubsw ym4, ym1, ym%4\n paddw ym3, ym4\n pmulhrsw ym3, ym%1\n mova [tmpq], ym3\n%endmacro\n\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\n%macro PREP_8TAP 0\n %if WIN64\n DECLARE_REG_TMP 6, 4\n %else\n DECLARE_REG_TMP 6, 7\n %endif\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep%+SUFFIX]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n%if cpuflag(avx512)\n vpbroadcastd m4, [pd_2]\n%else\n vpbroadcastd m4, [pw_8192]\n vbroadcasti128 m5, [subpel_h_shufA]\n%endif\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n%if notcpuflag(avx512)\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n%endif\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n add wq, r7\n jmp wq\n.h_w4:\n%if cpuflag(avx512)\n mov r3d, 0x4\n kmovb k1, r3d\n vbroadcasti128 ym5, [subpel_h_shufA]\n%endif\n movzx mxd, mxb\n dec srcq\n vpbroadcastd ym6, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n%if cpuflag(avx512icl)\n mova ym0, ym4\n mova ym1, ym4\n movq xm2, [srcq+strideq*0]\n movq xm3, [srcq+strideq*1]\n vpbroadcastq ym2{k1}, [srcq+strideq*2]\n vpbroadcastq ym3{k1}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pshufb ym2, ym5\n pshufb ym3, ym5\n vpdpbusd ym0, ym2, ym6\n vpdpbusd ym1, ym3, ym6\n packssdw ym0, ym1\n psraw ym0, 2\n%else\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m6\n pmaddubsw m1, m6\n phaddw m0, m1\n pmulhrsw m0, m4\n%endif\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m5, [subpel_h_shufA]\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n lea stride3q, [strideq*3]\n%endif\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n%if cpuflag(avx512)\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n%endif\n lea srcq, [srcq+strideq*(mmsize/(8*2))]\n%if cpuflag(avx512icl)\n mova m10, m4\n mova m11, m4\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n vpdpbusd m10, m1, m8\n vpdpbusd m11, m2, m8\n vpdpbusd m10, m2, m9\n vpdpbusd m11, m3, m9\n packssdw m10, m11\n psraw m0, m10, 2\n%else\n PREP_8TAP_H\n%endif\n mova [tmpq], m0\n add tmpq, mmsize\n sub hd, mmsize/(8*2)\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm16a]\n mova m6, [spel_h_perm16b]\n mova m7, [spel_h_perm16c]\n lea stride3q, [strideq*3]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m0, [srcq+strideq*1], 1\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n PREP_8TAP_H\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n.h_w32_loop:\n movu m0, [srcq+strideq*0]\n movu m1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n add tmpq, 64*2\n sub hd, 2\n jg .h_w32_loop\n RET\n%else\n xor r6d, r6d\n jmp .h_start\n%endif\n.h_w64:\n%if cpuflag(avx512)\n xor r6d, r6d\n%else\n mov r6, -32*1\n%endif\n jmp .h_start\n.h_w128:\n%if cpuflag(avx512)\n mov r6, -64*1\n%else\n mov r6, -32*3\n%endif\n.h_start:\n%if cpuflag(avx512)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n%endif\n sub srcq, r6\n mov r5, r6\n.h_loop:\n%if cpuflag(avx512icl)\n movu m0, [srcq+r6+32*0]\n movu m1, [srcq+r6+32*1]\n PREP_8TAP_H\n%else\n movu xm0, [srcq+r6+8*0]\n vinserti128 ym0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 ym0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n add r6, mmsize\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n%if cpuflag(avx512)\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_v)]\n add wq, r7\n%endif\n lea myq, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n vpbroadcastd m7, [pw_8192]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n%if cpuflag(avx512)\n jmp wq\n%else\n cmp wd, 8\n jg .v_w16\n je .v_w8\n%endif\n.v_w4:\n%if cpuflag(avx512)\n AVX512_MM_PERMUTATION\n PREP_8TAP_V_W4 23, 24, 25, 26, 27\n AVX512_MM_PERMUTATION\n%else\n PREP_8TAP_V_W4 7, 8, 9, 10, 11\n%endif\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.v_w8:\n%if cpuflag(avx512)\n mov r3d, 0xf044\n kmovw k1, r3d\n kshiftrw k2, k1, 8\n movq xm0, [srcq+strideq*0]\n vpbroadcastq ym1, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vmovdqa64 ym0{k1}, ym1\n vmovdqa64 ym1{k1}, ym2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n punpcklbw ym0, ym1 ; 01 12 __ __\n punpcklbw m2, m3 ; 23 34 23 34\n punpcklbw m4, m5 ; 45 56 45 56\n vmovdqa64 m0{k2}, m2 ; 01 12 23 34\n vmovdqa64 m2{k2}, m4 ; 23 34 45 56\n.v_w8_loop:\n vpbroadcastq m1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n pmaddubsw m14, m0, m8\n pmaddubsw m15, m2, m9\n vpblendmq m0{k1}, m6, m1\n vpblendmq m2{k1}, m1, m3\n vpbroadcastq m6, [srcq+strideq*2]\n paddw m14, m15\n punpcklbw m2, m0, m2 ; 67 78 67 78\n vpblendmq m12{k1}, m3, m5\n vpblendmq m13{k1}, m5, m6\n vpblendmq m0{k2}, m4, m2 ; 45 56 67 78\n punpcklbw m4, m12, m13 ; 89 9a 89 9a\n vmovdqa64 m2{k2}, m4 ; 67 78 89 9a\n pmaddubsw m12, m0, m10\n pmaddubsw m13, m2, m11\n paddw m14, m12\n paddw m14, m13\n pmulhrsw m14, m7\n mova [tmpq], m14\n%else\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512)\n mov r3d, 0xf0\n kmovb k1, r3d\n vbroadcasti128 m0, [srcq+strideq*0]\n vbroadcasti128 m1, [srcq+strideq*1]\n vbroadcasti128 m2, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n vmovdqa64 m0{k1}, m1\n vmovdqa64 m1{k1}, m2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n shufpd m0, m2, 0xcc ; 0a_2a 0b_2b 1a_3a 1b_3b\n shufpd m1, m3, 0xcc ; 1a_3a 1b_3b 2a_4a 2b_4b\n shufpd m4, m4, 0x44 ; 4a_-- 4b_-- 5a_-- 5b_--\n shufpd m5, m5, 0x44 ; 5a_-- 5b_-- 6a_-- 6b_--\n punpckhbw m2, m0, m1 ; 23a 23b 34a 34b\n punpcklbw m0, m1 ; 01a 01b 12a 12b\n punpcklbw m4, m5 ; 45a 45b 56a 56b\n.v_w16_loop:\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m5, [srcq+strideq*0]\n vpblendmq m1{k1}, m6, m3\n vmovdqa64 m3{k1}, m5\n pmaddubsw m12, m0, m8\n pmaddubsw m13, m2, m8\n pmaddubsw m14, m2, m9\n pmaddubsw m15, m4, m9\n pmaddubsw m0, m4, m10\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n paddw m12, m14\n paddw m13, m15\n paddw m12, m0\n vmovdqa64 m5{k1}, m2\n vmovdqa64 m2{k1}, m6\n mova m0, m4\n shufpd m1, m5, 0xcc ; 6a_8a 6b_8b 7a_9a 7b_9b\n shufpd m3, m2, 0xcc ; 7a_9a 7b_9b 8a_Aa 8b_Ab\n punpcklbw m2, m1, m3 ; 67a 67b 78a 78b\n punpckhbw m4, m1, m3 ; 89a 89b 9Aa 9Ab\n pmaddubsw m14, m2, m10\n pmaddubsw m15, m2, m11\n paddw m13, m14\n paddw m12, m15\n pmaddubsw m14, m4, m11\n paddw m13, m14\n pmulhrsw m12, m7\n pmulhrsw m13, m7\n mova [tmpq+ 0], m12\n mova [tmpq+64], m13\n add tmpq, 64*2\n sub hd, 4\n jg .v_w16_loop\n%else\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n%endif\n RET\n%if cpuflag(avx512)\n.v_w32:\n mova m18, [bilin_v_perm64]\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n movu ym3, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym4, [srcq+strideq*0]\n movu ym5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym6, [srcq+strideq*0]\n vpermq m0, m18, m0\n vpermq m1, m18, m1\n vpermq m2, m18, m2\n vpermq m3, m18, m3\n vpermq m4, m18, m4\n vpermq m5, m18, m5\n vpermq m6, m18, m6\n punpcklbw m0, m1\n punpcklbw m1, m2\n punpcklbw m2, m3\n punpcklbw m3, m4\n punpcklbw m4, m5\n punpcklbw m5, m6\n.v_w32_loop:\n movu ym12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym13, [srcq+strideq*0]\n pmaddubsw m14, m0, m8\n pmaddubsw m16, m2, m9\n pmaddubsw m15, m1, m8\n pmaddubsw m17, m3, m9\n mova m0, m2\n mova m1, m3\n vpermq m12, m18, m12\n vpermq m13, m18, m13\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m4, m10\n pmaddubsw m17, m5, m10\n punpcklbw m6, m12\n punpcklbw m12, m13\n mova m2, m4\n mova m3, m5\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m6, m11\n pmaddubsw m17, m12, m11\n mova m4, m6\n mova m5, m12\n paddw m14, m16\n paddw m15, m17\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova m6, m13\n mova [tmpq+ 0], m14\n mova [tmpq+64], m15\n add tmpq, 64*2\n sub hd, 2\n jg .v_w32_loop\n vzeroupper\n RET\n.v_w64:\n mov r6d, hd\n mov wd, 64\n jmp .v_start\n.v_w128:\n lea r6d, [(1<<8)+hq]\n mov wd, 128\n.v_start:\n WIN64_SPILL_XMM 27\n mova m26, [bilin_v_perm64]\n mov r5, tmpq\n mov r7, srcq\n.v_loop0:\n vpermq m0, m26, [srcq+strideq*0]\n vpermq m1, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m2, m26, [srcq+strideq*0]\n vpermq m3, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m4, m26, [srcq+strideq*0]\n vpermq m5, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m6, m26, [srcq+strideq*0]\n punpckhbw m12, m0, m1\n punpcklbw m0, m1\n punpckhbw m13, m1, m2\n punpcklbw m1, m2\n punpckhbw m14, m2, m3\n punpcklbw m2, m3\n punpckhbw m15, m3, m4\n punpcklbw m3, m4\n punpckhbw m16, m4, m5\n punpcklbw m4, m5\n punpckhbw m17, m5, m6\n punpcklbw m5, m6\n.v_loop:\n vpermq m18, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m19, m26, [srcq+strideq*0]\n pmaddubsw m20, m0, m8\n pmaddubsw m21, m12, m8\n pmaddubsw m22, m1, m8\n pmaddubsw m23, m13, m8\n mova m0, m2\n mova m12, m14\n mova m1, m3\n mova m13, m15\n pmaddubsw m2, m9\n pmaddubsw m14, m9\n pmaddubsw m3, m9\n pmaddubsw m15, m9\n punpckhbw m24, m6, m18\n punpcklbw m6, m18\n paddw m20, m2\n paddw m21, m14\n paddw m22, m3\n paddw m23, m15\n mova m2, m4\n mova m14, m16\n mova m3, m5\n mova m15, m17\n pmaddubsw m4, m10\n pmaddubsw m16, m10\n pmaddubsw m5, m10\n pmaddubsw m17, m10\n punpckhbw m25, m18, m19\n punpcklbw m18, m19\n paddw m20, m4\n paddw m21, m16\n paddw m22, m5\n paddw m23, m17\n mova m4, m6\n mova m16, m24\n mova m5, m18\n mova m17, m25\n pmaddubsw m6, m11\n pmaddubsw m24, m11\n pmaddubsw m18, m11\n pmaddubsw m25, m11\n paddw m20, m6\n paddw m21, m24\n paddw m22, m18\n paddw m23, m25\n pmulhrsw m20, m7\n pmulhrsw m21, m7\n pmulhrsw m22, m7\n pmulhrsw m23, m7\n mova m6, m19\n mova [tmpq+wq*0+ 0], m20\n mova [tmpq+wq*0+64], m21\n mova [tmpq+wq*2+ 0], m22\n mova [tmpq+wq*2+64], m23\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_loop\n movzx hd, r6b\n add r5, 64*2\n add r7, 64\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_loop0\n%endif\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n %assign stack_size_padded 0\n WIN64_SPILL_XMM 16\n cmp wd, 4\n je .hv_w4\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n%if cpuflag(avx512)\n tzcnt wd, wd\n vpbroadcastd m8, [pd_2]\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_hv)]\n vpbroadcastd m9, [pd_32]\n add wq, r7\n%endif\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512)\n jmp wq\n%else\n jmp .hv_w8\n%endif\n.hv_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n%if cpuflag(avx512)\n mov r3d, 0x04\n kmovb k1, r3d\n kshiftlb k2, k1, 2\n kshiftlb k3, k1, 4\n vpbroadcastd m10, [pd_2]\n vbroadcasti128 m16, [subpel_h_shufA]\n%else\n mova m7, [subpel_h_shuf4]\n pmovzxbd m9, [deint_shuf4]\n vpbroadcastd m10, [pw_8192]\n%endif\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512icl)\n movq xm3, [srcq+strideq*0]\n vpbroadcastq ym2, [srcq+strideq*1]\n vpbroadcastq ym3{k1}, [srcq+strideq*2]\n vpbroadcastq m2{k2}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3{k2}, [srcq+strideq*0]\n vpbroadcastq m2{k3}, [srcq+strideq*1]\n vpbroadcastq m3{k3}, [srcq+strideq*2]\n mova m17, [spel_hv_perm4a]\n movu m18, [spel_hv_perm4b]\n mova m0, m10\n mova m1, m10\n pshufb m2, m16\n pshufb m3, m16\n vpdpbusd m0, m2, m8\n vpdpbusd m1, m3, m8\n packssdw m0, m1 ; _ 0 1 2 3 4 5 6\n psraw m0, 2\n vpermb m1, m17, m0 ; 01 12 23 34\n vpermb m2, m18, m0 ; 23 34 45 56\n.hv_w4_loop:\n movq xm3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movq xm4, [srcq+strideq*0]\n vpbroadcastq ym3{k1}, [srcq+strideq*1]\n vpbroadcastq ym4{k1}, [srcq+strideq*2]\n mova ym5, ym10\n mova ym6, ym10\n pshufb ym3, ym16\n pshufb ym4, ym16\n vpdpbusd ym5, ym3, ym8\n vpdpbusd ym6, ym4, ym8\n mova m7, m11\n packssdw ym5, ym6 ; 7 8 9 a _ _ _ _\n psraw ym5, 2\n valignq m0, m5, m0, 4 ; _ 4 5 6 7 8 9 a\n vpdpwssd m7, m1, m12\n vpdpwssd m7, m2, m13\n vpermb m1, m17, m0 ; 45 56 67 78\n vpermb m2, m18, m0 ; 67 78 89 9a\n vpdpwssd m7, m1, m14\n vpdpwssd m7, m2, m15\n psrad m7, 6\n vpmovdw [tmpq], m7\n%else\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7 ; 00 01 10 11 02 03 12 13\n pshufb m0, m7 ; 20 21 30 31 22 23 32 33\n pshufb m3, m7 ; 40 41 50 51 42 43 52 53\n pshufb m1, m7 ; 60 61 60 61 62 63 62 63\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0 ; 0a 1a 2a 3a 0b 1b 2b 3b\n phaddw m3, m1 ; 4a 5a 6a __ 4b 5b 6b __\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4 ; 1a 2a 3a 4a 1b 2b 3b 4b\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n%endif\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.hv_w8:\n%if cpuflag(avx512icl)\n WIN64_SPILL_XMM 24\n vbroadcasti128 m16, [subpel_h_shufA]\n vbroadcasti128 m17, [subpel_h_shufB]\n vbroadcasti128 m18, [subpel_h_shufC]\n vinserti128 ym0, [srcq+strideq*0], 1\n vinserti128 m0, [srcq+strideq*1], 2\n vinserti128 m0, [srcq+strideq*2], 3\n movu xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym1, [srcq+strideq*0], 1\n vinserti128 m1, [srcq+strideq*1], 2\n vinserti128 m1, [srcq+strideq*2], 3\n mova m2, m8\n mova m4, m8\n mova m3, m8\n mova m5, m8\n pshufb m20, m0, m16\n pshufb m21, m0, m17\n pshufb m22, m0, m18\n pshufb m23, m1, m16\n pshufb m6, m1, m17\n pshufb m7, m1, m18\n vpdpbusd m2, m20, m10\n vpdpbusd m4, m21, m10\n vpdpbusd m2, m21, m11\n vpdpbusd m4, m22, m11\n vpdpbusd m3, m23, m10\n vpdpbusd m5, m6, m10\n vpdpbusd m3, m6, m11\n vpdpbusd m5, m7, m11\n packssdw m2, m4\n packssdw m3, m5\n psraw m2, 2 ; _ 0 1 2\n psraw m3, 2 ; 3 4 5 6\n valignq m0, m3, m2, 2 ; 0 1 2 3\n valignq m1, m3, m2, 4 ; 1 2 3 4\n valignq m2, m3, m2, 6 ; 2 3 4 5\n punpcklwd m4, m0, m1 ; 01a 12a 23a 34a\n punpckhwd m5, m0, m1 ; 01b 12b 23b 34b\n punpcklwd m6, m2, m3 ; 23a 34a 45a 56a\n punpckhwd m7, m2, m3 ; 23b 34b 45b 56b\n.hv_w8_loop:\n movu xm19, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym19, [srcq+strideq*0], 1\n vinserti128 m19, [srcq+strideq*1], 2\n vinserti128 m19, [srcq+strideq*2], 3\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m4, m12\n vpdpwssd m21, m5, m12\n vpdpwssd m20, m6, m13\n vpdpwssd m21, m7, m13\n pshufb m0, m19, m16\n pshufb m1, m19, m17\n pshufb m2, m19, m18\n vpdpbusd m22, m0, m10\n vpdpbusd m23, m1, m10\n vpdpbusd m22, m1, m11\n vpdpbusd m23, m2, m11\n packssdw m22, m23\n psraw m22, 2 ; 7 8 9 A\n valignq m0, m22, m3, 2 ; 4 5 6 7\n valignq m1, m22, m3, 4 ; 5 6 7 8\n valignq m2, m22, m3, 6 ; 6 7 8 9\n mova m3, m22\n punpcklwd m4, m0, m1 ; 45a 56a 67a 78a\n punpckhwd m5, m0, m1 ; 45b 56b 67b 78b\n punpcklwd m6, m2, m3 ; 67a 78a 89a 9Aa\n punpckhwd m7, m2, m3 ; 67b 78b 89b 9Ab\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq], m20\n add tmpq, 64\n sub hd, 4\n jg .hv_w8_loop\n%else\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n%endif\n RET\n%if cpuflag(avx512icl)\n.hv_w16:\n mov wd, 16*2\n jmp .hv_start\n.hv_w32:\n mov wd, 32*2\n jmp .hv_start\n.hv_w64:\n mov wd, 64*2\n jmp .hv_start\n.hv_w128:\n mov wd, 128*2\n.hv_start:\n WIN64_SPILL_XMM 31\n mova m16, [spel_h_perm16a]\n mova m17, [spel_h_perm16b]\n mova m18, [spel_h_perm16c]\n lea r6d, [wq*8-16*2*8+hq]\n mov r5, tmpq\n mov r7, srcq\n.hv_loop0:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym1, [srcq+strideq*0]\n vinserti32x8 m1, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n vinserti32x8 m2, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym3, [srcq+strideq*0]\n mova m4, m8\n mova m5, m8\n mova m6, m8\n mova m7, m8\n vpermb m19, m16, m0\n vpermb m20, m17, m0\n vpermb m21, m18, m0\n vpermb m22, m16, m1\n vpermb m23, m17, m1\n vpermb m24, m18, m1\n vpermb m25, m16, m2\n vpermb m26, m17, m2\n vpermb m27, m18, m2\n vpermb ym28, ym16, ym3\n vpermb ym29, ym17, ym3\n vpermb ym30, ym18, ym3\n mova m0, m8\n mova m1, m8\n mova ym2, ym8\n mova ym3, ym8\n vpdpbusd m4, m19, m10\n vpdpbusd m5, m20, m10\n vpdpbusd m6, m22, m10\n vpdpbusd m7, m23, m10\n vpdpbusd m0, m25, m10\n vpdpbusd m1, m26, m10\n vpdpbusd ym2, ym28, ym10\n vpdpbusd ym3, ym29, ym10\n vpdpbusd m4, m20, m11\n vpdpbusd m5, m21, m11\n vpdpbusd m6, m23, m11\n vpdpbusd m7, m24, m11\n vpdpbusd m0, m26, m11\n vpdpbusd m1, m27, m11\n vpdpbusd ym2, ym29, ym11\n vpdpbusd ym3, ym30, ym11\n packssdw m4, m5\n packssdw m6, m7\n packssdw m0, m1\n packssdw ym2, ym3\n psraw m4, 2 ; 0a 0b 1a 1b\n psraw m6, 2 ; 2a 2b 3a 3b\n psraw m0, 2 ; 4a 4b 5a 5b\n psraw ym2, 2 ; 6a 6b __ __\n vshufi32x4 m5, m4, m6, q1032 ; 1a 1b 2a 2b\n vshufi32x4 m7, m6, m0, q1032 ; 3a 3b 4a 4b\n vshufi32x4 m1, m0, m2, q1032 ; 5a 5b 6a 6b\n punpcklwd m2, m4, m5 ; 01a 01c 12a 12c\n punpckhwd m3, m4, m5 ; 01b 01d 12b 12d\n punpcklwd m4, m6, m7 ; 23a 23c 34a 34c\n punpckhwd m5, m6, m7 ; 23b 23d 34b 34d\n punpcklwd m6, m0, m1 ; 45a 45c 56a 56c\n punpckhwd m7, m0, m1 ; 45b 45d 56b 56d\n.hv_loop:\n movu ym19, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti32x8 m19, [srcq+strideq*0], 1\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m2, m12\n vpdpwssd m21, m3, m12\n vpdpwssd m20, m4, m13\n vpdpwssd m21, m5, m13\n vpermb m24, m16, m19\n vpermb m25, m17, m19\n vpermb m26, m18, m19\n vpdpbusd m22, m24, m10\n vpdpbusd m23, m25, m10\n vpdpbusd m22, m25, m11\n vpdpbusd m23, m26, m11\n packssdw m22, m23\n psraw m22, 2 ; 7a 7b 8a 8b\n vshufi32x4 m0, m1, m22, q1032 ; 6a 6b 7a 7b\n mova m2, m4\n mova m3, m5\n mova m1, m22\n mova m4, m6\n mova m5, m7\n punpcklwd m6, m0, m1 ; 67a 67c 78a 78c\n punpckhwd m7, m0, m1 ; 67b 67d 78b 78d\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq+wq*0], ym20\n vextracti32x8 [tmpq+wq*1], m20, 1\n lea tmpq, [tmpq+wq*2]\n sub hd, 2\n jg .hv_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_loop0\n%endif\n RET\n%endmacro\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro WRAP_YMM 1+\n INIT_YMM cpuname\n %1\n INIT_ZMM cpuname\n%endmacro\n\n%macro BIDIR_FN 1 ; op\n%if mmsize == 64\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM %1 0\n vextracti32x4 xmm1, ym0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_ret:\n RET\n.w4_h16:\n vpbroadcastd m7, strided\n pmulld m7, [bidir_sctr_w4]\n %1 0\n kxnorw k1, k1, k1\n vpscatterdd [dstq+m7]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM %1 0\n vextracti128 xmm1, ym0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n %1 0\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq ], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w16:\n %1 0\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m7, [warp_8x8_shufA]\n.w32_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m7, [warp_8x8_shufA]\n.w64_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m7, [warp_8x8_shufA]\n.w128_loop:\n %1 0\n vpermq m6, m7, m0\n %1 2\n mova [dstq+64*0], m6\n %1_INC_PTR 4\n vpermq m6, m7, m0\n mova [dstq+64*1], m6\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n%else\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endif\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\n%macro AVG_FN 0\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-avg %+ SUFFIX %+ _table\n lea r6, [avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [base+pw_1024]\n add wq, r6\n BIDIR_FN AVG\n%endmacro\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\n%macro W_AVG_FN 0\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-w_avg %+ SUFFIX %+ _table\n lea r6, [w_avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [base+pw_2048]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n%endmacro\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n%if mmsize == 64\n vpermq m3, m8, [maskq+%1*32]\n%else\n vpermq m3, [maskq+%1*16], q3120\n%endif\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp2q, %1*mmsize\n add tmp1q, %1*mmsize\n%endmacro\n\n%macro MASK_FN 0\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-mask %+ SUFFIX %+ _table\n lea r7, [mask %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n%if mmsize == 64\n mova m8, [base+bilin_v_perm64]\n%endif\n vpbroadcastd m5, [base+pw_2048]\n add wq, r7\n BIDIR_FN MASK\n%endmacro MASK_FN\n\n%macro W_MASK 4-5 0 ; dst, mask, tmp_offset[1-2], 4:4:4\n mova m%1, [tmp1q+mmsize*%3]\n mova m1, [tmp2q+mmsize*%3]\n psubw m1, m%1\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m%1, m1\n mova m1, [tmp1q+mmsize*%4]\n mova m2, [tmp2q+mmsize*%4]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n%if cpuflag(avx512icl)\n vpshldw m%2, m3, 8\n psllw m3, m%2, 10\n%else\n psrlw m3, 8\n%if %5\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n%endif\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m%1, m7\n pmulhrsw m1, m7\n packuswb m%1, m1\n%endmacro\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4, 0, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 0, 5, 2, 3\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 0, 4, 4, 5\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 0, 5, 6, 7\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 0, 1, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 0, 4, 2, 3, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 0, 4, 2, 3, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 0, 1, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 0, 4, 2, 3, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 0, 4, 4, 5, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 0, 4, 6, 7, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovs r10, yq\n test yq, yq\n cmovs r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovs r10, xq\n test xq, xq\n cmovs r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovs bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovs topextq, r12\n cmp bottomextq, bhq\n cmovns bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovs rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovs leftextq, r12\n cmp rightextq, bwq\n cmovns rightextq, r2\n cmp leftextq, bwq\n cmovns leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\nINIT_YMM avx2\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m9, [base+deint_shuf4]\n vpbroadcastd m8, [base+wm_420_sign+r6*4] ; 258 - sign\n add wq, r7\n W_MASK 0, 4, 0, 1\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 0, 5, 2, 3\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 0, 5, 2, 3\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 0, 5, 2, 3\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4, 0, 1\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 0, 5, 2, 3\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32*0], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK 0, 4, -4, -3\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 0, 5, -2, -1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32*1], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\nINIT_ZMM avx512icl\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\ncglobal w_mask_420, 4, 8, 16, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx512icl_table\n lea r7, [w_mask_420_avx512icl_table]\n tzcnt wd, wm\n mov r6d, r7m ; sign\n movifnidn hd, hm\n movsxd wq, [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m9, [base+pb_m64] ; -1 << 6\n mova ym10, [base+wm_420_mask+32]\n vpbroadcastd m8, [base+wm_sign_avx512+r6*4] ; (258 - sign) << 6\n add wq, r7\n mov maskq, maskmp\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n mova m5, [wm_420_perm4]\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM W_MASK 0, 4, 0, 1\n vinserti128 ym5, [wm_420_perm4+32], 1\n vpermb ym4, ym5, ym4\n vpdpbusd ym8, ym4, ym9\n vextracti128 xmm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_end:\n vpermb ym8, ym10, ym8\n movq [maskq], xm8\n RET\n.w4_h16:\n vpbroadcastd m11, strided\n pmulld m11, [bidir_sctr_w4]\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n vpdpbusd m8, m4, m9\n kxnorw k1, k1, k1\n vpermb m8, m10, m8\n mova [maskq], xm8\n vpscatterdd [dstq+m11]{k1}, m0\n RET\n.w8:\n mova m5, [wm_420_perm8]\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM W_MASK 0, 4, 0, 1\n vinserti128 ym5, [wm_420_perm8+32], 1\n vpermb ym4, ym5, ym4\n vpdpbusd ym8, ym4, ym9\n vpermb m8, m10, m8\n mova [maskq], xm8\n vextracti128 xmm1, ym0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n add tmp1q, 128\n add tmp2q, 128\n add maskq, 16\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n mova m1, m8\n vpdpbusd m1, m4, m9\n vpermb m1, m10, m1\n mova [maskq], xm1\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq+strideq*0], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16:\n mova m5, [wm_420_perm16]\n.w16_loop:\n W_MASK 0, 4, 0, 1\n vpermb m4, m5, m4\n mova m1, m8\n vpdpbusd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m0, q3120\n mova [maskq], xm1\n add maskq, 16\n mova [dstq+strideq*0], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n lea dstq, [dstq+strideq*4]\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m5, [warp_8x8_shufA]\n.w32_loop:\n W_MASK 0, 4, 0, 1\n mova m1, m8\n vpdpbusd m1, m4, m9\n add tmp1q, 128\n add tmp2q, 128\n vpermb m1, m10, m1\n vpermq m0, m5, m0\n mova [maskq], xm1\n add maskq, 16\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m12, [wm_420_perm64] ; 0, 2, 4, 6, 8, 10, 12, 14\n psrlq m13, m12, 4 ; 1, 3, 5, 7, 9, 11, 13, 15\n.w64_loop:\n W_MASK 0, 4, 0, 2\n W_MASK 11, 5, 1, 3\n mova m2, m8\n vpdpbusd m2, m4, m9\n mova m3, m8\n vpdpbusd m3, m5, m9\n add tmp1q, 256\n add tmp2q, 256\n vpermt2b m2, m10, m3\n mova m1, m0\n vpermt2q m0, m12, m11\n vpermt2q m1, m13, m11\n mova [maskq], ym2\n add maskq, 32\n mova [dstq+strideq*0], m0\n mova [dstq+strideq*1], m1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m14, [wm_420_perm64]\n mova m10, [wm_420_mask]\n psrlq m15, m14, 4\n.w128_loop:\n W_MASK 0, 12, 0, 4\n W_MASK 11, 13, 1, 5\n mova m4, m8\n vpdpbusd m4, m12, m9\n mova m5, m8\n vpdpbusd m5, m13, m9\n mova m1, m0\n vpermt2q m0, m14, m11\n vpermt2q m1, m15, m11\n mova [dstq+strideq*0+64*0], m0\n mova [dstq+strideq*1+64*0], m1\n W_MASK 0, 12, 2, 6\n W_MASK 11, 13, 3, 7\n vprold m4, 16\n vprold m5, 16\n vpdpbusd m4, m12, m9\n vpdpbusd m5, m13, m9\n add tmp1q, 512\n add tmp2q, 512\n vpermt2b m4, m10, m5\n mova m1, m0\n vpermt2q m0, m14, m11\n vpermt2q m1, m15, m11\n mova [maskq], m4\n add maskq, 64\n mova [dstq+strideq*0+64*1], m0\n mova [dstq+strideq*1+64*1], m1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w128_loop\n RET\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nbidir_sctr_w4: dd 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\nspel_h_perm16a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\nspel_h_perm16b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 36, 37, 38, 39, 37, 38, 39, 40, 38, 39, 40, 41, 39, 40, 41, 42\n db 44, 45, 46, 47, 45, 46, 47, 48, 46, 47, 48, 49, 47, 48, 49, 50\nspel_h_perm16c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\n db 48, 49, 50, 51, 49, 50, 51, 52, 50, 51, 52, 53, 51, 52, 53, 54\nspel_h_perm32a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\nspel_h_perm32b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 20, 21, 22, 23, 21, 22, 23, 24, 22, 23, 24, 25, 23, 24, 25, 26\n db 28, 29, 30, 31, 29, 30, 31, 32, 30, 31, 32, 33, 31, 32, 33, 34\nspel_h_perm32c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\nspel_hv_perm4a: db 8, 9, 16, 17, 10, 11, 18, 19, 12, 13, 20, 21, 14, 15, 22, 23\n db 16, 17, 24, 25, 18, 19, 26, 27, 20, 21, 28, 29, 22, 23, 30, 31\nspel_hv_perm4b: db 24, 25, 32, 33, 26, 27, 34, 35, 28, 29, 36, 37, 30, 31, 38, 39\n db 32, 33, 40, 41, 34, 35, 42, 43, 36, 37, 44, 45, 38, 39, 46, 47\n db 40, 41, 48, 49, 42, 43, 50, 51, 44, 45, 52, 53, 46, 47, 54, 55\n db 48, 49, 56, 57, 50, 51, 58, 59, 52, 53, 60, 61, 54, 55, 62, 63\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_v_shuf4: db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_2: dd 2\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\ncextern mc_warp_filter\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx512icl, 7, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx512icl, 4, 8, 16, 32, 64, 128\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro PREP_8TAP_H 0\n %if cpuflag(avx512)\n vpermb m10, m5, m0\n vpermb m11, m5, m1\n vpermb m12, m6, m0\n vpermb m13, m6, m1\n vpermb m14, m7, m0\n vpermb m15, m7, m1\n mova m0, m4\n mova m2, m4\n mova m1, m4\n mova m3, m4\n vpdpbusd m0, m10, m8\n vpdpbusd m2, m12, m8\n vpdpbusd m1, m11, m8\n vpdpbusd m3, m13, m8\n vpdpbusd m0, m12, m9\n vpdpbusd m2, m14, m9\n vpdpbusd m1, m13, m9\n vpdpbusd m3, m15, m9\n packssdw m0, m2\n packssdw m1, m3\n psraw m0, 2\n psraw m1, 2\n mova [tmpq+ 0], m0\n mova [tmpq+64], m1\n %else\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n pmaddubsw m1, m8\n pmaddubsw m0, m2, m8\n pmaddubsw m2, m9\n pmaddubsw m3, m9\n paddw m1, m2\n paddw m0, m3\n phaddw m0, m1, m0\n pmulhrsw m0, m4\n %endif\n%endmacro\n\n%macro PREP_8TAP_V_W4 5 ; round, weights\n movd xm0, [srcq+strideq*0]\n vpbroadcastd ym1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd ym3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd ym1, ym1, ym0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd ym3, ym3, ym2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd ym0, [srcq+strideq*0]\n vpbroadcastd ym2, [srcq+strideq*1]\n vpblendd ym1, ym1, ym0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd ym0, [srcq+strideq*2]\n vbroadcasti128 ym5, [deint_shuf4]\n vpblendd ym3, ym3, ym2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd ym2, ym3, ym1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd ym3, ym3, ym1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw ym1, ym2, ym3 ; 01 12 23 34\n vpblendd ym3, ym3, ym0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw ym2, ym3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym3, [srcq+strideq*0]\n vpbroadcastd ym4, [srcq+strideq*1]\n vpblendd ym3, ym3, ym4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd ym3, ym3, ym0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd ym0, [srcq+strideq*2]\n vpblendd ym3, ym3, ym0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb ym3, ym5 ; 67 78 89 9a\n pmaddubsw ym4, ym1, ym%2\n vperm2i128 ym1, ym2, ym3, 0x21 ; 45 56 67 78\n pmaddubsw ym2, ym%3\n paddw ym4, ym2\n mova ym2, ym3\n pmaddubsw ym3, ym%5\n paddw ym3, ym4\n pmaddubsw ym4, ym1, ym%4\n paddw ym3, ym4\n pmulhrsw ym3, ym%1\n mova [tmpq], ym3\n%endmacro\n\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\n%macro PREP_8TAP 0\n %if WIN64\n DECLARE_REG_TMP 6, 4\n %else\n DECLARE_REG_TMP 6, 7\n %endif\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep%+SUFFIX]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n%if cpuflag(avx512)\n vpbroadcastd m4, [pd_2]\n%else\n vpbroadcastd m4, [pw_8192]\n vbroadcasti128 m5, [subpel_h_shufA]\n%endif\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n%if notcpuflag(avx512)\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n%endif\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n add wq, r7\n jmp wq\n.h_w4:\n%if cpuflag(avx512)\n mov r3d, 0x4\n kmovb k1, r3d\n vbroadcasti128 ym5, [subpel_h_shufA]\n%endif\n movzx mxd, mxb\n dec srcq\n vpbroadcastd ym6, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n%if cpuflag(avx512icl)\n mova ym0, ym4\n mova ym1, ym4\n movq xm2, [srcq+strideq*0]\n movq xm3, [srcq+strideq*1]\n vpbroadcastq ym2{k1}, [srcq+strideq*2]\n vpbroadcastq ym3{k1}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pshufb ym2, ym5\n pshufb ym3, ym5\n vpdpbusd ym0, ym2, ym6\n vpdpbusd ym1, ym3, ym6\n packssdw ym0, ym1\n psraw ym0, 2\n%else\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m6\n pmaddubsw m1, m6\n phaddw m0, m1\n pmulhrsw m0, m4\n%endif\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m5, [subpel_h_shufA]\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n lea stride3q, [strideq*3]\n%endif\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n%if cpuflag(avx512)\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n%endif\n lea srcq, [srcq+strideq*(mmsize/(8*2))]\n%if cpuflag(avx512icl)\n mova m10, m4\n mova m11, m4\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n vpdpbusd m10, m1, m8\n vpdpbusd m11, m2, m8\n vpdpbusd m10, m2, m9\n vpdpbusd m11, m3, m9\n packssdw m10, m11\n psraw m0, m10, 2\n%else\n PREP_8TAP_H\n%endif\n mova [tmpq], m0\n add tmpq, mmsize\n sub hd, mmsize/(8*2)\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm16a]\n mova m6, [spel_h_perm16b]\n mova m7, [spel_h_perm16c]\n lea stride3q, [strideq*3]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m0, [srcq+strideq*1], 1\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n PREP_8TAP_H\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n.h_w32_loop:\n movu m0, [srcq+strideq*0]\n movu m1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n add tmpq, 64*2\n sub hd, 2\n jg .h_w32_loop\n RET\n%else\n xor r6d, r6d\n jmp .h_start\n%endif\n.h_w64:\n%if cpuflag(avx512)\n xor r6d, r6d\n%else\n mov r6, -32*1\n%endif\n jmp .h_start\n.h_w128:\n%if cpuflag(avx512)\n mov r6, -64*1\n%else\n mov r6, -32*3\n%endif\n.h_start:\n%if cpuflag(avx512)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n%endif\n sub srcq, r6\n mov r5, r6\n.h_loop:\n%if cpuflag(avx512icl)\n movu m0, [srcq+r6+32*0]\n movu m1, [srcq+r6+32*1]\n PREP_8TAP_H\n%else\n movu xm0, [srcq+r6+8*0]\n vinserti128 ym0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 ym0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n add r6, mmsize\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n%if cpuflag(avx512)\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_v)]\n add wq, r7\n%endif\n lea myq, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n vpbroadcastd m7, [pw_8192]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n%if cpuflag(avx512)\n jmp wq\n%else\n cmp wd, 8\n jg .v_w16\n je .v_w8\n%endif\n.v_w4:\n%if cpuflag(avx512)\n AVX512_MM_PERMUTATION\n PREP_8TAP_V_W4 23, 24, 25, 26, 27\n AVX512_MM_PERMUTATION\n%else\n PREP_8TAP_V_W4 7, 8, 9, 10, 11\n%endif\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.v_w8:\n%if cpuflag(avx512)\n mov r3d, 0xf044\n kmovw k1, r3d\n kshiftrw k2, k1, 8\n movq xm0, [srcq+strideq*0]\n vpbroadcastq ym1, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vmovdqa64 ym0{k1}, ym1\n vmovdqa64 ym1{k1}, ym2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n punpcklbw ym0, ym1 ; 01 12 __ __\n punpcklbw m2, m3 ; 23 34 23 34\n punpcklbw m4, m5 ; 45 56 45 56\n vmovdqa64 m0{k2}, m2 ; 01 12 23 34\n vmovdqa64 m2{k2}, m4 ; 23 34 45 56\n.v_w8_loop:\n vpbroadcastq m1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n pmaddubsw m14, m0, m8\n pmaddubsw m15, m2, m9\n vpblendmq m0{k1}, m6, m1\n vpblendmq m2{k1}, m1, m3\n vpbroadcastq m6, [srcq+strideq*2]\n paddw m14, m15\n punpcklbw m2, m0, m2 ; 67 78 67 78\n vpblendmq m12{k1}, m3, m5\n vpblendmq m13{k1}, m5, m6\n vpblendmq m0{k2}, m4, m2 ; 45 56 67 78\n punpcklbw m4, m12, m13 ; 89 9a 89 9a\n vmovdqa64 m2{k2}, m4 ; 67 78 89 9a\n pmaddubsw m12, m0, m10\n pmaddubsw m13, m2, m11\n paddw m14, m12\n paddw m14, m13\n pmulhrsw m14, m7\n mova [tmpq], m14\n%else\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512)\n mov r3d, 0xf0\n kmovb k1, r3d\n vbroadcasti128 m0, [srcq+strideq*0]\n vbroadcasti128 m1, [srcq+strideq*1]\n vbroadcasti128 m2, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n vmovdqa64 m0{k1}, m1\n vmovdqa64 m1{k1}, m2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n shufpd m0, m2, 0xcc ; 0a_2a 0b_2b 1a_3a 1b_3b\n shufpd m1, m3, 0xcc ; 1a_3a 1b_3b 2a_4a 2b_4b\n shufpd m4, m4, 0x44 ; 4a_-- 4b_-- 5a_-- 5b_--\n shufpd m5, m5, 0x44 ; 5a_-- 5b_-- 6a_-- 6b_--\n punpckhbw m2, m0, m1 ; 23a 23b 34a 34b\n punpcklbw m0, m1 ; 01a 01b 12a 12b\n punpcklbw m4, m5 ; 45a 45b 56a 56b\n.v_w16_loop:\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m5, [srcq+strideq*0]\n vpblendmq m1{k1}, m6, m3\n vmovdqa64 m3{k1}, m5\n pmaddubsw m12, m0, m8\n pmaddubsw m13, m2, m8\n pmaddubsw m14, m2, m9\n pmaddubsw m15, m4, m9\n pmaddubsw m0, m4, m10\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n paddw m12, m14\n paddw m13, m15\n paddw m12, m0\n vmovdqa64 m5{k1}, m2\n vmovdqa64 m2{k1}, m6\n mova m0, m4\n shufpd m1, m5, 0xcc ; 6a_8a 6b_8b 7a_9a 7b_9b\n shufpd m3, m2, 0xcc ; 7a_9a 7b_9b 8a_Aa 8b_Ab\n punpcklbw m2, m1, m3 ; 67a 67b 78a 78b\n punpckhbw m4, m1, m3 ; 89a 89b 9Aa 9Ab\n pmaddubsw m14, m2, m10\n pmaddubsw m15, m2, m11\n paddw m13, m14\n paddw m12, m15\n pmaddubsw m14, m4, m11\n paddw m13, m14\n pmulhrsw m12, m7\n pmulhrsw m13, m7\n mova [tmpq+ 0], m12\n mova [tmpq+64], m13\n add tmpq, 64*2\n sub hd, 4\n jg .v_w16_loop\n%else\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n%endif\n RET\n%if cpuflag(avx512)\n.v_w32:\n mova m18, [bilin_v_perm64]\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n movu ym3, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym4, [srcq+strideq*0]\n movu ym5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym6, [srcq+strideq*0]\n vpermq m0, m18, m0\n vpermq m1, m18, m1\n vpermq m2, m18, m2\n vpermq m3, m18, m3\n vpermq m4, m18, m4\n vpermq m5, m18, m5\n vpermq m6, m18, m6\n punpcklbw m0, m1\n punpcklbw m1, m2\n punpcklbw m2, m3\n punpcklbw m3, m4\n punpcklbw m4, m5\n punpcklbw m5, m6\n.v_w32_loop:\n movu ym12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym13, [srcq+strideq*0]\n pmaddubsw m14, m0, m8\n pmaddubsw m16, m2, m9\n pmaddubsw m15, m1, m8\n pmaddubsw m17, m3, m9\n mova m0, m2\n mova m1, m3\n vpermq m12, m18, m12\n vpermq m13, m18, m13\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m4, m10\n pmaddubsw m17, m5, m10\n punpcklbw m6, m12\n punpcklbw m12, m13\n mova m2, m4\n mova m3, m5\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m6, m11\n pmaddubsw m17, m12, m11\n mova m4, m6\n mova m5, m12\n paddw m14, m16\n paddw m15, m17\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova m6, m13\n mova [tmpq+ 0], m14\n mova [tmpq+64], m15\n add tmpq, 64*2\n sub hd, 2\n jg .v_w32_loop\n vzeroupper\n RET\n.v_w64:\n mov r6d, hd\n mov wd, 64\n jmp .v_start\n.v_w128:\n lea r6d, [(1<<8)+hq]\n mov wd, 128\n.v_start:\n WIN64_SPILL_XMM 27\n mova m26, [bilin_v_perm64]\n mov r5, tmpq\n mov r7, srcq\n.v_loop0:\n vpermq m0, m26, [srcq+strideq*0]\n vpermq m1, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m2, m26, [srcq+strideq*0]\n vpermq m3, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m4, m26, [srcq+strideq*0]\n vpermq m5, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m6, m26, [srcq+strideq*0]\n punpckhbw m12, m0, m1\n punpcklbw m0, m1\n punpckhbw m13, m1, m2\n punpcklbw m1, m2\n punpckhbw m14, m2, m3\n punpcklbw m2, m3\n punpckhbw m15, m3, m4\n punpcklbw m3, m4\n punpckhbw m16, m4, m5\n punpcklbw m4, m5\n punpckhbw m17, m5, m6\n punpcklbw m5, m6\n.v_loop:\n vpermq m18, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m19, m26, [srcq+strideq*0]\n pmaddubsw m20, m0, m8\n pmaddubsw m21, m12, m8\n pmaddubsw m22, m1, m8\n pmaddubsw m23, m13, m8\n mova m0, m2\n mova m12, m14\n mova m1, m3\n mova m13, m15\n pmaddubsw m2, m9\n pmaddubsw m14, m9\n pmaddubsw m3, m9\n pmaddubsw m15, m9\n punpckhbw m24, m6, m18\n punpcklbw m6, m18\n paddw m20, m2\n paddw m21, m14\n paddw m22, m3\n paddw m23, m15\n mova m2, m4\n mova m14, m16\n mova m3, m5\n mova m15, m17\n pmaddubsw m4, m10\n pmaddubsw m16, m10\n pmaddubsw m5, m10\n pmaddubsw m17, m10\n punpckhbw m25, m18, m19\n punpcklbw m18, m19\n paddw m20, m4\n paddw m21, m16\n paddw m22, m5\n paddw m23, m17\n mova m4, m6\n mova m16, m24\n mova m5, m18\n mova m17, m25\n pmaddubsw m6, m11\n pmaddubsw m24, m11\n pmaddubsw m18, m11\n pmaddubsw m25, m11\n paddw m20, m6\n paddw m21, m24\n paddw m22, m18\n paddw m23, m25\n pmulhrsw m20, m7\n pmulhrsw m21, m7\n pmulhrsw m22, m7\n pmulhrsw m23, m7\n mova m6, m19\n mova [tmpq+wq*0+ 0], m20\n mova [tmpq+wq*0+64], m21\n mova [tmpq+wq*2+ 0], m22\n mova [tmpq+wq*2+64], m23\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_loop\n movzx hd, r6b\n add r5, 64*2\n add r7, 64\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_loop0\n%endif\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n %assign stack_size_padded 0\n WIN64_SPILL_XMM 16\n cmp wd, 4\n je .hv_w4\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n%if cpuflag(avx512)\n tzcnt wd, wd\n vpbroadcastd m8, [pd_2]\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_hv)]\n vpbroadcastd m9, [pd_32]\n add wq, r7\n%endif\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512)\n jmp wq\n%else\n jmp .hv_w8\n%endif\n.hv_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n%if cpuflag(avx512)\n mov r3d, 0x04\n kmovb k1, r3d\n kshiftlb k2, k1, 2\n kshiftlb k3, k1, 4\n vpbroadcastd m10, [pd_2]\n vbroadcasti128 m16, [subpel_h_shufA]\n%else\n mova m7, [subpel_h_shuf4]\n pmovzxbd m9, [deint_shuf4]\n vpbroadcastd m10, [pw_8192]\n%endif\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512icl)\n movq xm3, [srcq+strideq*0]\n vpbroadcastq ym2, [srcq+strideq*1]\n vpbroadcastq ym3{k1}, [srcq+strideq*2]\n vpbroadcastq m2{k2}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3{k2}, [srcq+strideq*0]\n vpbroadcastq m2{k3}, [srcq+strideq*1]\n vpbroadcastq m3{k3}, [srcq+strideq*2]\n mova m17, [spel_hv_perm4a]\n movu m18, [spel_hv_perm4b]\n mova m0, m10\n mova m1, m10\n pshufb m2, m16\n pshufb m3, m16\n vpdpbusd m0, m2, m8\n vpdpbusd m1, m3, m8\n packssdw m0, m1 ; _ 0 1 2 3 4 5 6\n psraw m0, 2\n vpermb m1, m17, m0 ; 01 12 23 34\n vpermb m2, m18, m0 ; 23 34 45 56\n.hv_w4_loop:\n movq xm3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movq xm4, [srcq+strideq*0]\n vpbroadcastq ym3{k1}, [srcq+strideq*1]\n vpbroadcastq ym4{k1}, [srcq+strideq*2]\n mova ym5, ym10\n mova ym6, ym10\n pshufb ym3, ym16\n pshufb ym4, ym16\n vpdpbusd ym5, ym3, ym8\n vpdpbusd ym6, ym4, ym8\n mova m7, m11\n packssdw ym5, ym6 ; 7 8 9 a _ _ _ _\n psraw ym5, 2\n valignq m0, m5, m0, 4 ; _ 4 5 6 7 8 9 a\n vpdpwssd m7, m1, m12\n vpdpwssd m7, m2, m13\n vpermb m1, m17, m0 ; 45 56 67 78\n vpermb m2, m18, m0 ; 67 78 89 9a\n vpdpwssd m7, m1, m14\n vpdpwssd m7, m2, m15\n psrad m7, 6\n vpmovdw [tmpq], m7\n%else\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7 ; 00 01 10 11 02 03 12 13\n pshufb m0, m7 ; 20 21 30 31 22 23 32 33\n pshufb m3, m7 ; 40 41 50 51 42 43 52 53\n pshufb m1, m7 ; 60 61 60 61 62 63 62 63\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0 ; 0a 1a 2a 3a 0b 1b 2b 3b\n phaddw m3, m1 ; 4a 5a 6a __ 4b 5b 6b __\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4 ; 1a 2a 3a 4a 1b 2b 3b 4b\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n%endif\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.hv_w8:\n%if cpuflag(avx512icl)\n WIN64_SPILL_XMM 24\n vbroadcasti128 m16, [subpel_h_shufA]\n vbroadcasti128 m17, [subpel_h_shufB]\n vbroadcasti128 m18, [subpel_h_shufC]\n vinserti128 ym0, [srcq+strideq*0], 1\n vinserti128 m0, [srcq+strideq*1], 2\n vinserti128 m0, [srcq+strideq*2], 3\n movu xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym1, [srcq+strideq*0], 1\n vinserti128 m1, [srcq+strideq*1], 2\n vinserti128 m1, [srcq+strideq*2], 3\n mova m2, m8\n mova m4, m8\n mova m3, m8\n mova m5, m8\n pshufb m20, m0, m16\n pshufb m21, m0, m17\n pshufb m22, m0, m18\n pshufb m23, m1, m16\n pshufb m6, m1, m17\n pshufb m7, m1, m18\n vpdpbusd m2, m20, m10\n vpdpbusd m4, m21, m10\n vpdpbusd m2, m21, m11\n vpdpbusd m4, m22, m11\n vpdpbusd m3, m23, m10\n vpdpbusd m5, m6, m10\n vpdpbusd m3, m6, m11\n vpdpbusd m5, m7, m11\n packssdw m2, m4\n packssdw m3, m5\n psraw m2, 2 ; _ 0 1 2\n psraw m3, 2 ; 3 4 5 6\n valignq m0, m3, m2, 2 ; 0 1 2 3\n valignq m1, m3, m2, 4 ; 1 2 3 4\n valignq m2, m3, m2, 6 ; 2 3 4 5\n punpcklwd m4, m0, m1 ; 01a 12a 23a 34a\n punpckhwd m5, m0, m1 ; 01b 12b 23b 34b\n punpcklwd m6, m2, m3 ; 23a 34a 45a 56a\n punpckhwd m7, m2, m3 ; 23b 34b 45b 56b\n.hv_w8_loop:\n movu xm19, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym19, [srcq+strideq*0], 1\n vinserti128 m19, [srcq+strideq*1], 2\n vinserti128 m19, [srcq+strideq*2], 3\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m4, m12\n vpdpwssd m21, m5, m12\n vpdpwssd m20, m6, m13\n vpdpwssd m21, m7, m13\n pshufb m0, m19, m16\n pshufb m1, m19, m17\n pshufb m2, m19, m18\n vpdpbusd m22, m0, m10\n vpdpbusd m23, m1, m10\n vpdpbusd m22, m1, m11\n vpdpbusd m23, m2, m11\n packssdw m22, m23\n psraw m22, 2 ; 7 8 9 A\n valignq m0, m22, m3, 2 ; 4 5 6 7\n valignq m1, m22, m3, 4 ; 5 6 7 8\n valignq m2, m22, m3, 6 ; 6 7 8 9\n mova m3, m22\n punpcklwd m4, m0, m1 ; 45a 56a 67a 78a\n punpckhwd m5, m0, m1 ; 45b 56b 67b 78b\n punpcklwd m6, m2, m3 ; 67a 78a 89a 9Aa\n punpckhwd m7, m2, m3 ; 67b 78b 89b 9Ab\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq], m20\n add tmpq, 64\n sub hd, 4\n jg .hv_w8_loop\n%else\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n%endif\n RET\n%if cpuflag(avx512icl)\n.hv_w16:\n mov wd, 16*2\n jmp .hv_start\n.hv_w32:\n mov wd, 32*2\n jmp .hv_start\n.hv_w64:\n mov wd, 64*2\n jmp .hv_start\n.hv_w128:\n mov wd, 128*2\n.hv_start:\n WIN64_SPILL_XMM 31\n mova m16, [spel_h_perm16a]\n mova m17, [spel_h_perm16b]\n mova m18, [spel_h_perm16c]\n lea r6d, [wq*8-16*2*8+hq]\n mov r5, tmpq\n mov r7, srcq\n.hv_loop0:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym1, [srcq+strideq*0]\n vinserti32x8 m1, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n vinserti32x8 m2, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym3, [srcq+strideq*0]\n mova m4, m8\n mova m5, m8\n mova m6, m8\n mova m7, m8\n vpermb m19, m16, m0\n vpermb m20, m17, m0\n vpermb m21, m18, m0\n vpermb m22, m16, m1\n vpermb m23, m17, m1\n vpermb m24, m18, m1\n vpermb m25, m16, m2\n vpermb m26, m17, m2\n vpermb m27, m18, m2\n vpermb ym28, ym16, ym3\n vpermb ym29, ym17, ym3\n vpermb ym30, ym18, ym3\n mova m0, m8\n mova m1, m8\n mova ym2, ym8\n mova ym3, ym8\n vpdpbusd m4, m19, m10\n vpdpbusd m5, m20, m10\n vpdpbusd m6, m22, m10\n vpdpbusd m7, m23, m10\n vpdpbusd m0, m25, m10\n vpdpbusd m1, m26, m10\n vpdpbusd ym2, ym28, ym10\n vpdpbusd ym3, ym29, ym10\n vpdpbusd m4, m20, m11\n vpdpbusd m5, m21, m11\n vpdpbusd m6, m23, m11\n vpdpbusd m7, m24, m11\n vpdpbusd m0, m26, m11\n vpdpbusd m1, m27, m11\n vpdpbusd ym2, ym29, ym11\n vpdpbusd ym3, ym30, ym11\n packssdw m4, m5\n packssdw m6, m7\n packssdw m0, m1\n packssdw ym2, ym3\n psraw m4, 2 ; 0a 0b 1a 1b\n psraw m6, 2 ; 2a 2b 3a 3b\n psraw m0, 2 ; 4a 4b 5a 5b\n psraw ym2, 2 ; 6a 6b __ __\n vshufi32x4 m5, m4, m6, q1032 ; 1a 1b 2a 2b\n vshufi32x4 m7, m6, m0, q1032 ; 3a 3b 4a 4b\n vshufi32x4 m1, m0, m2, q1032 ; 5a 5b 6a 6b\n punpcklwd m2, m4, m5 ; 01a 01c 12a 12c\n punpckhwd m3, m4, m5 ; 01b 01d 12b 12d\n punpcklwd m4, m6, m7 ; 23a 23c 34a 34c\n punpckhwd m5, m6, m7 ; 23b 23d 34b 34d\n punpcklwd m6, m0, m1 ; 45a 45c 56a 56c\n punpckhwd m7, m0, m1 ; 45b 45d 56b 56d\n.hv_loop:\n movu ym19, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti32x8 m19, [srcq+strideq*0], 1\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m2, m12\n vpdpwssd m21, m3, m12\n vpdpwssd m20, m4, m13\n vpdpwssd m21, m5, m13\n vpermb m24, m16, m19\n vpermb m25, m17, m19\n vpermb m26, m18, m19\n vpdpbusd m22, m24, m10\n vpdpbusd m23, m25, m10\n vpdpbusd m22, m25, m11\n vpdpbusd m23, m26, m11\n packssdw m22, m23\n psraw m22, 2 ; 7a 7b 8a 8b\n vshufi32x4 m0, m1, m22, q1032 ; 6a 6b 7a 7b\n mova m2, m4\n mova m3, m5\n mova m1, m22\n mova m4, m6\n mova m5, m7\n punpcklwd m6, m0, m1 ; 67a 67c 78a 78c\n punpckhwd m7, m0, m1 ; 67b 67d 78b 78d\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq+wq*0], ym20\n vextracti32x8 [tmpq+wq*1], m20, 1\n lea tmpq, [tmpq+wq*2]\n sub hd, 2\n jg .hv_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_loop0\n%endif\n RET\n%endmacro\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro WRAP_YMM 1+\n INIT_YMM cpuname\n %1\n INIT_ZMM cpuname\n%endmacro\n\n%macro BIDIR_FN 1 ; op\n%if mmsize == 64\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM %1 0\n vextracti32x4 xmm1, ym0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_ret:\n RET\n.w4_h16:\n vpbroadcastd m7, strided\n pmulld m7, [bidir_sctr_w4]\n %1 0\n kxnorw k1, k1, k1\n vpscatterdd [dstq+m7]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM %1 0\n vextracti128 xmm1, ym0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n %1 0\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq ], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w16:\n %1 0\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m7, [warp_8x8_shufA]\n.w32_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m7, [warp_8x8_shufA]\n.w64_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m7, [warp_8x8_shufA]\n.w128_loop:\n %1 0\n vpermq m6, m7, m0\n %1 2\n mova [dstq+64*0], m6\n %1_INC_PTR 4\n vpermq m6, m7, m0\n mova [dstq+64*1], m6\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n%else\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endif\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\n%macro AVG_FN 0\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-avg %+ SUFFIX %+ _table\n lea r6, [avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [base+pw_1024]\n add wq, r6\n BIDIR_FN AVG\n%endmacro\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\n%macro W_AVG_FN 0\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-w_avg %+ SUFFIX %+ _table\n lea r6, [w_avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [base+pw_2048]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n%endmacro\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n%if mmsize == 64\n vpermq m3, m8, [maskq+%1*32]\n%else\n vpermq m3, [maskq+%1*16], q3120\n%endif\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp2q, %1*mmsize\n add tmp1q, %1*mmsize\n%endmacro\n\n%macro MASK_FN 0\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-mask %+ SUFFIX %+ _table\n lea r7, [mask %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n%if mmsize == 64\n mova m8, [base+bilin_v_perm64]\n%endif\n vpbroadcastd m5, [base+pw_2048]\n add wq, r7\n BIDIR_FN MASK\n%endmacro MASK_FN\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovs r10, yq\n test yq, yq\n cmovs r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovs r10, xq\n test xq, xq\n cmovs r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovs bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovs topextq, r12\n cmp bottomextq, bhq\n cmovns bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovs rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovs leftextq, r12\n cmp rightextq, bwq\n cmovns rightextq, r2\n cmp leftextq, bwq\n cmovns leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\nINIT_YMM avx2\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\nINIT_ZMM avx512icl\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":486,"cells":{"commit":{"kind":"string","value":"ee51cf16781d93824ad4548c9daf745231322259"},"subject":{"kind":"string","value":"x86: replace \"mov hb, Xb\" by \"movzx hd, Xb\" in MC"},"message":{"kind":"string","value":"x86: replace \"mov hb, Xb\" by \"movzx hd, Xb\" in MC\n\nIt's a little easier for the CPU to simply overwrite a 32-bit reg rather\nthan writing it's low 8 bits while conserving bits 8 to 31.\nIn order to do that it actually fetches those bits, merge to a 32-bit\nvalue, and write that back to the 32-bit GPR.\n\nAs those are always cleared, perform a zero extend mov to dword instead.\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/mc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\ncextern mc_warp_filter\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\nINIT_ZMM avx512icl\nPREP_BILIN\n\nINIT_YMM avx2\nPREP_BILIN\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%if WIN64\nDECLARE_REG_TMP 6, 4\n%else\nDECLARE_REG_TMP 6, 7\n%endif\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vbroadcasti128 m5, [subpel_h_shufA]\n vpbroadcastd m4, [pw_8192]\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep_avx2+4]\n add wq, r7\n jmp wq\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m3, [r7+mxq*8+subpel_filters-prep_avx2+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n phaddw m0, m1\n pmulhrsw m0, m4\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PREP_8TAP_H 0\n pshufb m1, m0, m6\n pshufb m2, m0, m7\n pshufb m0, m5\n pmaddubsw m3, m1, m8\n pmaddubsw m1, m9\n pmaddubsw m2, m9\n pmaddubsw m0, m8\n paddw m2, m3\n paddw m0, m1\n phaddw m0, m2\n pmulhrsw m0, m4\n%endmacro\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n mov r5, r6\n.h_loop:\n movu xm0, [srcq+r6+8*0]\n vinserti128 m0, m0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 m0, m0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n add r6, 32\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n vpbroadcastd m7, [pw_8192]\n lea myq, [r7+myq*8+subpel_filters-prep_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n cmp wd, 8\n jg .v_w16\n je .v_w8\n.v_w4:\n movd xm0, [srcq+strideq*0]\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd m3, m3, m2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd m0, [srcq+strideq*0]\n vpbroadcastd m2, [srcq+strideq*1]\n vpblendd m1, m1, m0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd m0, [srcq+strideq*2]\n vbroadcasti128 m6, [deint_shuf4]\n vpblendd m3, m3, m2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd m2, m3, m1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd m3, m3, m1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw m1, m2, m3 ; 01 12 23 34\n vpblendd m3, m3, m0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw m2, m3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd m3, [srcq+strideq*0]\n vpbroadcastd m4, [srcq+strideq*1]\n vpblendd m3, m3, m4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd m3, m3, m0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd m0, [srcq+strideq*2]\n vpblendd m3, m3, m0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb m3, m6 ; 67 78 89 9a\n pmaddubsw m4, m1, m8\n vperm2i128 m1, m2, m3, 0x21 ; 45 56 67 78\n pmaddubsw m2, m9\n paddw m4, m2\n mova m2, m3\n pmaddubsw m3, m11\n paddw m3, m4\n pmaddubsw m4, m1, m10\n paddw m3, m4\n pmulhrsw m3, m7\n mova [tmpq], m3\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n mova m7, [subpel_h_shuf4]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+2]\n pmovzxbd m9, [deint_shuf4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m10, [pw_8192]\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7\n pshufb m0, m7\n pshufb m3, m7\n pshufb m1, m7\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro BIDIR_FN 1 ; op\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [pw_1024+r6-avg_avx2_table]\n add wq, r6\n BIDIR_FN AVG\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [w_avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [pw_2048+r6-w_avg_avx2_table]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n vpermq m3, [maskq+(%1+0)*(mmsize/2)], q3120\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n lea r7, [mask_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n vpbroadcastd m5, [pw_2048+r7-mask_avx2_table]\n add wq, r7\n BIDIR_FN MASK\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovl r10, yq\n test yq, yq\n cmovl r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovl r10, xq\n test xq, xq\n cmovl r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovl bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovl topextq, r12\n cmp bottomextq, bhq\n cmovge bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovl rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovl leftextq, r12\n cmp rightextq, bwq\n cmovge rightextq, r2\n cmp leftextq, bwq\n cmovge leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\ncextern mc_warp_filter\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n mov hb, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n mov hb, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n mov hb, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n mov hb, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\nINIT_ZMM avx512icl\nPREP_BILIN\n\nINIT_YMM avx2\nPREP_BILIN\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmovle myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%if WIN64\nDECLARE_REG_TMP 6, 4\n%else\nDECLARE_REG_TMP 6, 7\n%endif\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vbroadcasti128 m5, [subpel_h_shufA]\n vpbroadcastd m4, [pw_8192]\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep_avx2+4]\n add wq, r7\n jmp wq\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m3, [r7+mxq*8+subpel_filters-prep_avx2+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n phaddw m0, m1\n pmulhrsw m0, m4\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PREP_8TAP_H 0\n pshufb m1, m0, m6\n pshufb m2, m0, m7\n pshufb m0, m5\n pmaddubsw m3, m1, m8\n pmaddubsw m1, m9\n pmaddubsw m2, m9\n pmaddubsw m0, m8\n paddw m2, m3\n paddw m0, m1\n phaddw m0, m2\n pmulhrsw m0, m4\n%endmacro\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq], m0\n add tmpq, 32\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n mov r5, r6\n.h_loop:\n movu xm0, [srcq+r6+8*0]\n vinserti128 m0, m0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 m0, m0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n add tmpq, 64\n add r6, 32\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n vpbroadcastd m7, [pw_8192]\n lea myq, [r7+myq*8+subpel_filters-prep_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n cmp wd, 8\n jg .v_w16\n je .v_w8\n.v_w4:\n movd xm0, [srcq+strideq*0]\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd m3, m3, m2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd m0, [srcq+strideq*0]\n vpbroadcastd m2, [srcq+strideq*1]\n vpblendd m1, m1, m0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd m0, [srcq+strideq*2]\n vbroadcasti128 m6, [deint_shuf4]\n vpblendd m3, m3, m2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd m2, m3, m1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd m3, m3, m1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw m1, m2, m3 ; 01 12 23 34\n vpblendd m3, m3, m0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw m2, m3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd m3, [srcq+strideq*0]\n vpbroadcastd m4, [srcq+strideq*1]\n vpblendd m3, m3, m4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd m3, m3, m0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd m0, [srcq+strideq*2]\n vpblendd m3, m3, m0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb m3, m6 ; 67 78 89 9a\n pmaddubsw m4, m1, m8\n vperm2i128 m1, m2, m3, 0x21 ; 45 56 67 78\n pmaddubsw m2, m9\n paddw m4, m2\n mova m2, m3\n pmaddubsw m3, m11\n paddw m3, m4\n pmaddubsw m4, m1, m10\n paddw m3, m4\n pmulhrsw m3, m7\n mova [tmpq], m3\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n mov hb, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n mova m7, [subpel_h_shuf4]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep_avx2+2]\n pmovzxbd m9, [deint_shuf4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m10, [pw_8192]\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7\n pshufb m0, m7\n pshufb m3, m7\n pshufb m1, m7\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep_avx2+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep_avx2]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n mov hb, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro BIDIR_FN 1 ; op\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [pw_1024+r6-avg_avx2_table]\n add wq, r6\n BIDIR_FN AVG\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [w_avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [pw_2048+r6-w_avg_avx2_table]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n vpermq m3, [maskq+(%1+0)*(mmsize/2)], q3120\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n lea r7, [mask_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n vpbroadcastd m5, [pw_2048+r7-mask_avx2_table]\n add wq, r7\n BIDIR_FN MASK\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovl r10, yq\n test yq, yq\n cmovl r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovl r10, xq\n test xq, xq\n cmovl r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovl bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovl topextq, r12\n cmp bottomextq, bhq\n cmovge bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovl rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovl leftextq, r12\n cmp rightextq, bwq\n cmovge rightextq, r2\n cmp leftextq, bwq\n cmovge leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":487,"cells":{"commit":{"kind":"string","value":"13f1dd284e1fb64a188618daa9f01d1be3963bab"},"subject":{"kind":"string","value":"x86: Fix overflows in SSSE3 idct"},"message":{"kind":"string","value":"x86: Fix overflows in SSSE3 idct\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/itx_ssse3.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n\nSECTION_RODATA 16\n\ndeint_shuf: db 0, 1, 4, 5, 8, 9, 12, 13, 2, 3, 6, 7, 10, 11, 14, 15\n\ndeint_shuf1: db 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\ndeint_shuf2: db 8, 9, 0, 1, 10, 11, 2, 3, 12, 13, 4, 5, 14, 15, 6, 7\n\n%macro COEF_PAIR 2-3 0 ; !0 = m%1_m%2, 2 = no %2_%1\npw_%1_m%2: times 4 dw %1, -%2\n%if %3 != 2\npw_%2_%1: times 4 dw %2, %1\n%endif\n%if %3\npw_m%1_m%2: times 4 dw -%1, -%2\n%endif\n%endmacro\n\n;adst4\npw_1321_3803: times 4 dw 1321, 3803\npw_2482_m1321: times 4 dw 2482, -1321\npw_3344_2482: times 4 dw 3344, 2482\npw_3344_m3803: times 4 dw 3344, -3803\npw_3344_m3344: times 4 dw 3344, -3344\npw_0_3344 times 4 dw 0, 3344\npw_m6688_m3803: times 4 dw -6688, -3803\n\nCOEF_PAIR 2896, 2896\nCOEF_PAIR 1567, 3784\nCOEF_PAIR 799, 4017\nCOEF_PAIR 3406, 2276\nCOEF_PAIR 401, 4076\nCOEF_PAIR 1931, 3612\nCOEF_PAIR 3166, 2598\nCOEF_PAIR 3920, 1189\nCOEF_PAIR 3784, 1567, 1\nCOEF_PAIR 995, 3973\nCOEF_PAIR 1751, 3703\nCOEF_PAIR 3513, 2106\nCOEF_PAIR 3857, 1380\nCOEF_PAIR 4017, 799, 1\nCOEF_PAIR 201, 4091\nCOEF_PAIR 2440, 3290\nCOEF_PAIR 3035, 2751\nCOEF_PAIR 4052, 601\nCOEF_PAIR 2276, 3406, 1\nCOEF_PAIR 4076, 401, 2\nCOEF_PAIR 2598, 3166, 2\nCOEF_PAIR 3612, 1931, 2\nCOEF_PAIR 1189, 3920, 2\n\npd_2048: times 4 dd 2048\npw_2048: times 8 dw 2048\npw_m2048: times 8 dw -2048\npw_4096: times 8 dw 4096\npw_16384: times 8 dw 16384\npw_m16384: times 8 dw -16384\npw_1697x16: times 8 dw 1697*16\npw_1697x8: times 8 dw 1697*8\npw_2896x8: times 8 dw 2896*8\npw_3344x8: times 8 dw 3344*8\npw_8192: times 8 dw 8192\npw_m8192: times 8 dw -8192\npw_5: times 8 dw 5\npw_201x8: times 8 dw 201*8\npw_4091x8: times 8 dw 4091*8\npw_m2751x8: times 8 dw -2751*8\npw_3035x8: times 8 dw 3035*8\npw_1751x8: times 8 dw 1751*8\npw_3703x8: times 8 dw 3703*8\npw_m1380x8: times 8 dw -1380*8\npw_3857x8: times 8 dw 3857*8\npw_995x8: times 8 dw 995*8\npw_3973x8: times 8 dw 3973*8\npw_m2106x8: times 8 dw -2106*8\npw_3513x8: times 8 dw 3513*8\npw_2440x8: times 8 dw 2440*8\npw_3290x8: times 8 dw 3290*8\npw_m601x8: times 8 dw -601*8\npw_4052x8: times 8 dw 4052*8\n\npw_4095x8: times 8 dw 4095*8\npw_101x8: times 8 dw 101*8\npw_2967x8: times 8 dw 2967*8\npw_m2824x8: times 8 dw -2824*8\npw_3745x8: times 8 dw 3745*8\npw_1660x8: times 8 dw 1660*8\npw_3822x8: times 8 dw 3822*8\npw_m1474x8: times 8 dw -1474*8\npw_3996x8: times 8 dw 3996*8\npw_897x8: times 8 dw 897*8\npw_3461x8: times 8 dw 3461*8\npw_m2191x8: times 8 dw -2191*8\npw_3349x8: times 8 dw 3349*8\npw_2359x8: times 8 dw 2359*8\npw_4036x8: times 8 dw 4036*8\npw_m700x8: times 8 dw -700*8\npw_4065x8: times 8 dw 4065*8\npw_501x8: times 8 dw 501*8\npw_3229x8: times 8 dw 3229*8\npw_m2520x8: times 8 dw -2520*8\npw_3564x8: times 8 dw 3564*8\npw_2019x8: times 8 dw 2019*8\npw_3948x8: times 8 dw 3948*8\npw_m1092x8: times 8 dw -1092*8\npw_3889x8: times 8 dw 3889*8\npw_1285x8: times 8 dw 1285*8\npw_3659x8: times 8 dw 3659*8\npw_m1842x8: times 8 dw -1842*8\npw_3102x8: times 8 dw 3102*8\npw_2675x8: times 8 dw 2675*8\npw_4085x8: times 8 dw 4085*8\npw_m301x8: times 8 dw -301*8\n\niadst4_dconly1a: times 2 dw 10568, 19856, 26752, 30424\niadst4_dconly1b: times 2 dw 30424, 26752, 19856, 10568\niadst4_dconly2a: dw 10568, 10568, 10568, 10568, 19856, 19856, 19856, 19856\niadst4_dconly2b: dw 26752, 26752, 26752, 26752, 30424, 30424, 30424, 30424\n\nSECTION .text\n\n%macro REPX 2-*\n %xdefine %%f(x) %1\n%rep %0 - 1\n %rotate 1\n %%f(%1)\n%endrep\n%endmacro\n\n%define m(x) mangle(private_prefix %+ _ %+ x %+ SUFFIX)\n\n%if ARCH_X86_64\n%define o(x) x\n%else\n%define o(x) r5-$$+x ; PIC\n%endif\n\n%macro WRITE_4X4 9 ;src[1-2], tmp[1-3], row[1-4]\n lea r2, [dstq+strideq*2]\n%assign %%i 1\n%rotate 5\n%rep 4\n %if %1 & 2\n CAT_XDEFINE %%row_adr, %%i, r2 + strideq*(%1&1)\n %else\n CAT_XDEFINE %%row_adr, %%i, dstq + strideq*(%1&1)\n %endif\n %assign %%i %%i + 1\n %rotate 1\n%endrep\n\n movd m%3, [%%row_adr1] ;dst0\n movd m%5, [%%row_adr2] ;dst1\n punpckldq m%3, m%5 ;high: dst1 :low: dst0\n movd m%4, [%%row_adr3] ;dst2\n movd m%5, [%%row_adr4] ;dst3\n punpckldq m%4, m%5 ;high: dst3 :low: dst2\n\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n\n paddw m%3, m%1 ;high: dst1 + out1 ;low: dst0 + out0\n paddw m%4, m%2 ;high: dst3 + out3 ;low: dst2 + out2\n\n packuswb m%3, m%4 ;high->low: dst3 + out3, dst2 + out2, dst1 + out1, dst0 + out0\n\n movd [%%row_adr1], m%3 ;store dst0 + out0\n pshuflw m%4, m%3, q1032\n movd [%%row_adr2], m%4 ;store dst1 + out1\n punpckhqdq m%3, m%3\n movd [%%row_adr3], m%3 ;store dst2 + out2\n psrlq m%3, 32\n movd [%%row_adr4], m%3 ;store dst3 + out3\n%endmacro\n\n%macro ITX4_END 4-5 2048 ; row[1-4], rnd\n%if %5\n mova m2, [o(pw_%5)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n%endif\n\n WRITE_4X4 0, 1, 2, 3, 4, %1, %2, %3, %4\n ret\n%endmacro\n\n; flags: 1 = swap, 2: coef_regs, 4: no_pack\n%macro ITX_MUL2X_PACK 5-6 0 ; dst/src, tmp[1], rnd, coef[1-2], flags\n%if %6 & 2\n pmaddwd m%2, m%4, m%1\n pmaddwd m%1, m%5\n%elif %6 & 1\n pmaddwd m%2, m%1, [o(pw_%5_%4)]\n pmaddwd m%1, [o(pw_%4_m%5)]\n%else\n pmaddwd m%2, m%1, [o(pw_%4_m%5)]\n pmaddwd m%1, [o(pw_%5_%4)]\n%endif\n paddd m%2, m%3\n paddd m%1, m%3\n psrad m%2, 12\n psrad m%1, 12\n%if %6 & 4 == 0\n packssdw m%1, m%2\n%endif\n%endmacro\n\n%macro IDCT4_1D_PACKED 0-1 ;pw_2896x8\n mova m3, [o(pd_2048)]\n punpckhwd m2, m0, m1 ;unpacked in1 in3\n punpcklwd m0, m1 ;unpacked in0 in2\n ITX_MUL2X_PACK 2, 1, 3, 1567, 3784\n ITX_MUL2X_PACK 0, 1, 3, 2896, 2896\n psubsw m1, m0, m2 ;high: out2 ;low: out3\n paddsw m0, m2 ;high: out1 ;low: out0\n%endmacro\n\n%macro INV_TXFM_FN 5+ ; type1, type2, fast_thresh, size, xmm/stack\ncglobal inv_txfm_add_%1_%2_%4, 4, 6, %5, dst, stride, coeff, eob, tx2\n %undef cmp\n %define %%p1 m(i%1_%4_internal)\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n%if has_epilogue\n%if %3 > 0\n cmp eobd, %3\n jle %%end\n%elif %3 == 0\n test eobd, eobd\n jz %%end\n%endif\n lea tx2q, [o(m(i%2_%4_internal).pass2)]\n call %%p1\n RET\n%%end:\n%else\n lea tx2q, [o(m(i%2_%4_internal).pass2)]\n%if %3 > 0\n cmp eobd, %3\n jg %%p1\n%elif %3 == 0\n test eobd, eobd\n jnz %%p1\n%else\n times ((%%end - %%p1) >> 31) & 1 jmp %%p1\nALIGN function_align\n%%end:\n%endif\n%endif\n%endmacro\n\n%macro INV_TXFM_4X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x4, 6\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n TAIL_CALL m(iadst_4x4_internal).end\n%elifidn %1_%2, identity_dct\n mova m1, [coeffq+16*0]\n mova m2, [coeffq+16*1]\n punpcklwd m0, m1, m2\n punpckhwd m1, m2\n punpcklwd m0, m1\n punpcklqdq m0, m0\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end\n%elif %3 >= 0\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n%ifidn %1, dct\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%elifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%elifidn %1, flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd ;0\n%ifidn %2, dct\n%ifnidn %1, dct\n pmulhrsw m0, [o(pw_2896x8)]\n%else\n pmulhrsw m0, m1\n%endif\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end2\n%else ; adst / flipadst\n pmulhrsw m1, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n TAIL_CALL m(i%2_4x4_internal).end2\n%endif\n%endif\n%endmacro\n\nINIT_XMM ssse3\n\nINV_TXFM_4X4_FN dct, dct, 0\nINV_TXFM_4X4_FN dct, adst, 0\nINV_TXFM_4X4_FN dct, flipadst, 0\nINV_TXFM_4X4_FN dct, identity, 3\n\ncglobal idct_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0] ;high: in1 ;low: in0\n mova m1, [coeffq+16*1] ;high: in3 ;low in2\n\n IDCT4_1D_PACKED\n\n mova m2, [o(deint_shuf)]\n shufps m3, m0, m1, q1331\n shufps m0, m1, q0220\n pshufb m0, m2 ;high: in1 ;low: in0\n pshufb m1, m3, m2 ;high: in3 ;low :in2\n jmp tx2q\n\n.pass2:\n IDCT4_1D_PACKED\n\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2 ;memset(coeff, 0, sizeof(*coeff) * sh * sw);\n\n ITX4_END 0, 1, 3, 2\n\nINV_TXFM_4X4_FN adst, dct, 0\nINV_TXFM_4X4_FN adst, adst, 0\nINV_TXFM_4X4_FN adst, flipadst, 0\nINV_TXFM_4X4_FN adst, identity\n\ncglobal iadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call .main\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 0, 1, 2, 3\n\nALIGN function_align\n.main:\n punpcklwd m2, m0, m1 ;unpacked in0 in2\n punpckhwd m0, m1 ;unpacked in1 in3\n mova m3, m0\n pmaddwd m1, m2, [o(pw_3344_m3344)];3344 * in0 - 3344 * in2\n pmaddwd m0, [o(pw_0_3344)] ;3344 * in3\n paddd m1, m0 ;t2\n pmaddwd m0, m2, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m2, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m4, m3, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m3, [o(pw_3344_m3803)];3344 * in1 - 3803 * in3\n paddd m4, m0 ;t0 + t3\n pmaddwd m3, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m0, [o(pd_2048)]\n paddd m1, m0 ;t2 + 2048\n paddd m2, m0\n paddd m0, m4 ;t0 + t3 + 2048\n paddd m5, m2 ;t1 + t3 + 2048\n paddd m2, m4\n paddd m2, m3 ;t0 + t1 - t3 + 2048\n REPX {psrad x, 12}, m1, m0, m5, m2\n packssdw m0, m5 ;high: out1 ;low: out0\n packssdw m1, m2 ;high: out3 ;low: out3\n ret\n\nINV_TXFM_4X4_FN flipadst, dct, 0\nINV_TXFM_4X4_FN flipadst, adst, 0\nINV_TXFM_4X4_FN flipadst, flipadst, 0\nINV_TXFM_4X4_FN flipadst, identity\n\ncglobal iflipadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call m(iadst_4x4_internal).main\n punpcklwd m2, m1, m0\n punpckhwd m1, m0\n punpcklwd m0, m1, m2 ;high: in3 ;low :in2\n punpckhwd m1, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call m(iadst_4x4_internal).main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 3, 2, 1, 0\n\nINV_TXFM_4X4_FN identity, dct, 3\nINV_TXFM_4X4_FN identity, adst\nINV_TXFM_4X4_FN identity, flipadst\nINV_TXFM_4X4_FN identity, identity\n\ncglobal iidentity_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m0, m3\n pmulhrsw m3, m1\n paddsw m0, m2\n paddsw m1, m3\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddsw m0, m2\n paddsw m1, m3\n jmp m(iadst_4x4_internal).end\n\n%macro IWHT4_1D_PACKED 0\n punpckhqdq m3, m0, m1 ;low: in1 high: in3\n punpcklqdq m0, m1 ;low: in0 high: in2\n psubw m2, m0, m3 ;low: in0 - in1 high: in2 - in3\n paddw m0, m3 ;low: in0 + in1 high: in2 + in3\n punpckhqdq m2, m2 ;t2 t2\n punpcklqdq m0, m0 ;t0 t0\n psubw m1, m0, m2\n psraw m1, 1 ;t4 t4\n psubw m1, m3 ;low: t1/out2 high: t3/out1\n psubw m0, m1 ;high: out0\n paddw m2, m1 ;low: out3\n%endmacro\n\ncglobal inv_txfm_add_wht_wht_4x4, 3, 3, 4, dst, stride, coeff\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n psraw m0, 2\n psraw m1, 2\n\n IWHT4_1D_PACKED\n\n punpckhwd m0, m1\n punpcklwd m3, m1, m2\n punpckhdq m1, m0, m3\n punpckldq m0, m3\n\n IWHT4_1D_PACKED\n\n shufpd m0, m2, 0x01\n ITX4_END 0, 3, 2, 1, 0\n\n\n%macro IDCT8_1D_PACKED 0\n mova m6, [o(pd_2048)]\n punpckhwd m4, m0, m3 ;unpacked in1 in7\n punpcklwd m0, m2 ;unpacked in0 in4\n punpckhwd m2, m1 ;unpacked in5 in3\n punpcklwd m1, m3 ;unpacked in2 in6\n ITX_MUL2X_PACK 4, 3, 6, 799, 4017 ;low: t7a high: t4a\n ITX_MUL2X_PACK 2, 3, 6, 3406, 2276 ;low: t6a high: t5a\n ITX_MUL2X_PACK 1, 3, 6, 1567, 3784 ;low: t3 high: t2\n psubsw m3, m4, m2 ;low: t6a high: t5a\n paddsw m4, m2 ;low: t7 high: t4\n pshufb m3, [o(deint_shuf1)]\n ITX_MUL2X_PACK 0, 2, 6, 2896, 2896 ;low: t0 high: t1\n ITX_MUL2X_PACK 3, 2, 6, 2896, 2896 ;low: t6 high: t5\n psubsw m2, m0, m1 ;low: tmp3 high: tmp2\n paddsw m0, m1 ;low: tmp0 high: tmp1\n punpcklqdq m1, m4, m3 ;low: t7 high: t6\n punpckhqdq m4, m3 ;low: t4 high: t5\n psubsw m3, m0, m1 ;low: out7 high: out6\n paddsw m0, m1 ;low: out0 high: out1\n paddsw m1, m2, m4 ;low: out3 high: out2\n psubsw m2, m4 ;low: out4 high: out5\n%endmacro\n\n;dst1 = (src1 * coef1 - src2 * coef2 + rnd) >> 12\n;dst2 = (src1 * coef2 + src2 * coef1 + rnd) >> 12\n%macro ITX_MULSUB_2W 7-8 0 ; dst/src[1-2], tmp[1-2], rnd, coef[1-2], dst2_in_tmp1\n punpckhwd m%4, m%1, m%2\n punpcklwd m%1, m%2\n%if %7 < 8\n pmaddwd m%2, m%7, m%1\n pmaddwd m%3, m%7, m%4\n%else\n mova m%2, [o(pw_%7_%6)]\n%if %8\n pmaddwd m%3, m%1, m%2\n pmaddwd m%2, m%4\n%else\n pmaddwd m%3, m%4, m%2\n pmaddwd m%2, m%1\n%endif\n%endif\n paddd m%3, m%5\n paddd m%2, m%5\n psrad m%3, 12\n psrad m%2, 12\n%if %8\n packssdw m%3, m%2\n%else\n packssdw m%2, m%3 ;dst2\n%endif\n%if %7 < 8\n pmaddwd m%4, m%6\n pmaddwd m%1, m%6\n%elif %8\n mova m%2, [o(pw_%6_m%7)]\n pmaddwd m%4, m%2\n pmaddwd m%1, m%2\n%else\n mova m%3, [o(pw_%6_m%7)]\n pmaddwd m%4, m%3\n pmaddwd m%1, m%3\n%endif\n paddd m%4, m%5\n paddd m%1, m%5\n psrad m%4, 12\n psrad m%1, 12\n packssdw m%1, m%4 ;dst1\n%endmacro\n\n%macro IDCT4_1D 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %2, %4, %5, %6, %7, 1567, 3784, 1 ;t2, t3\n ITX_MULSUB_2W %1, %3, %4, %6, %7, 2896, 2896, 1 ;t1, t0\n psubsw m%3, m%1, m%2 ;out2\n paddsw m%2, m%1 ;out1\n paddsw m%1, m%5, m%4 ;out0\n psubsw m%4, m%5 ;out3\n%endmacro\n\n%macro WRITE_4X8 4 ;row[1-4]\n WRITE_4X4 0, 1, 4, 5, 6, %1, %2, %3, %4\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 2, 3, 4, 5, 6, %1, %2, %3, %4\n%endmacro\n\n%macro INV_4X8 0\n punpckhwd m4, m2, m3\n punpcklwd m2, m3\n punpckhwd m3, m0, m1\n punpcklwd m0, m1\n punpckhdq m1, m0, m2 ;low: in2 high: in3\n punpckldq m0, m2 ;low: in0 high: in1\n punpckldq m2, m3, m4 ;low: in4 high: in5\n punpckhdq m3, m4 ;low: in6 high: in7\n%endmacro\n\n%macro INV_TXFM_4X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x8, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_4096)]\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n movd m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n mova m2, [o(pw_2896x8)]\n punpckldq m0, m1\n pmulhrsw m0, m2\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n pmulhrsw m0, m2\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%endif\n%endif\n%endmacro\n\nINV_TXFM_4X8_FN dct, dct, 0\nINV_TXFM_4X8_FN dct, identity, 7\nINV_TXFM_4X8_FN dct, adst\nINV_TXFM_4X8_FN dct, flipadst\n\ncglobal idct_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(idct_8x4_internal).main\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n call .main\n shufps m1, m1, q1032\n shufps m3, m3, q1032\n mova m4, [o(pw_2048)]\n jmp m(iadst_4x8_internal).end2\n\nALIGN function_align\n.main:\n IDCT8_1D_PACKED\n ret\n\n\nINV_TXFM_4X8_FN adst, dct, 0\nINV_TXFM_4X8_FN adst, adst\nINV_TXFM_4X8_FN adst, flipadst\nINV_TXFM_4X8_FN adst, identity\n\ncglobal iadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n.pass1_end:\n INV_4X8\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call .main\n mova m4, [o(pw_2048)]\n pxor m5, m5\n psubw m5, m4\n\n.end:\n punpcklqdq m4, m5\n\n.end2:\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end3:\n pxor m5, m5\n mova [coeffq+16*0], m5\n mova [coeffq+16*1], m5\n mova [coeffq+16*2], m5\n mova [coeffq+16*3], m5\n\n.end4:\n WRITE_4X8 0, 1, 2, 3\n RET\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n punpckhwd m4, m3, m0 ;unpacked in7 in0\n punpckhwd m5, m2, m1 ;unpacked in5 in2\n punpcklwd m1, m2 ;unpacked in3 in4\n punpcklwd m0, m3 ;unpacked in1 in6\n ITX_MUL2X_PACK 4, 2, 6, 401, 4076 ;low: t0a high: t1a\n ITX_MUL2X_PACK 5, 2, 6, 1931, 3612 ;low: t2a high: t3a\n ITX_MUL2X_PACK 1, 2, 6, 3166, 2598 ;low: t4a high: t5a\n ITX_MUL2X_PACK 0, 2, 6, 3920, 1189 ;low: t6a high: t7a\n\n psubsw m3, m4, m1 ;low: t4 high: t5\n paddsw m4, m1 ;low: t0 high: t1\n psubsw m2, m5, m0 ;low: t6 high: t7\n paddsw m5, m0 ;low: t2 high: t3\n\n shufps m1, m3, m2, q1032\n punpckhwd m2, m1\n punpcklwd m3, m1\n ITX_MUL2X_PACK 3, 0, 6, 1567, 3784, 1 ;low: t5a high: t4a\n ITX_MUL2X_PACK 2, 0, 6, 3784, 1567 ;low: t7a high: t6a\n\n psubsw m1, m4, m5 ;low: t2 high: t3\n paddsw m4, m5 ;low: out0 high: -out7\n psubsw m5, m3, m2 ;low: t7 high: t6\n paddsw m3, m2 ;low: out6 high: -out1\n shufps m0, m4, m3, q3210 ;low: out0 high: -out1\n shufps m3, m4, q3210 ;low: out6 high: -out7\n\n mova m2, [o(pw_2896_m2896)]\n mova m7, [o(pw_2896_2896)]\n shufps m4, m1, m5, q1032 ;low: t3 high: t7\n shufps m1, m5, q3210 ;low: t2 high: t6\n punpcklwd m5, m1, m4\n punpckhwd m1, m4\n pmaddwd m4, m2, m1 ;-out5\n pmaddwd m2, m5 ; out4\n pmaddwd m1, m7 ; out2\n pmaddwd m5, m7 ;-out3\n REPX {paddd x, m6}, m4, m2, m1, m5\n REPX {psrad x, 12}, m4, m2, m1, m5\n packssdw m1, m5 ;low: out2 high: -out3\n packssdw m2, m4 ;low: out4 high: -out5\n ret\n\nINV_TXFM_4X8_FN flipadst, dct, 0\nINV_TXFM_4X8_FN flipadst, adst\nINV_TXFM_4X8_FN flipadst, flipadst\nINV_TXFM_4X8_FN flipadst, identity\n\ncglobal iflipadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n punpcklwd m4, m3, m2\n punpckhwd m3, m2\n punpcklwd m5, m1, m0\n punpckhwd m1, m0\n punpckldq m2, m3, m1 ;low: in4 high: in5\n punpckhdq m3, m1 ;low: in6 high: in7\n punpckldq m0, m4, m5 ;low: in0 high: in1\n punpckhdq m1, m4, m5 ;low: in2 high: in3\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n mova m4, m0\n mova m5, m1\n pshufd m0, m3, q1032\n pshufd m1, m2, q1032\n pshufd m2, m5, q1032\n pshufd m3, m4, q1032\n mova m5, [o(pw_2048)]\n pxor m4, m4\n psubw m4, m5\n jmp m(iadst_4x8_internal).end\n\nINV_TXFM_4X8_FN identity, dct, 3\nINV_TXFM_4X8_FN identity, adst\nINV_TXFM_4X8_FN identity, flipadst\nINV_TXFM_4X8_FN identity, identity\n\ncglobal iidentity_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddsw m0, m4\n paddsw m1, m5\n paddsw m2, m6\n paddsw m3, m7\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n mova m4, [o(pw_4096)]\n jmp m(iadst_4x8_internal).end2\n\n\n%macro WRITE_8X2 5 ;coefs[1-2], tmp[1-3]\n movq m%3, [dstq ]\n movq m%4, [dstq+strideq]\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n%ifnum %1\n paddw m%3, m%1\n%else\n paddw m%3, %1\n%endif\n%ifnum %2\n paddw m%4, m%2\n%else\n paddw m%4, %2\n%endif\n packuswb m%3, m%4\n movq [dstq ], m%3\n punpckhqdq m%3, m%3\n movq [dstq+strideq], m%3\n%endmacro\n\n%macro WRITE_8X4 7 ;coefs[1-4], tmp[1-3]\n WRITE_8X2 %1, %2, %5, %6, %7\n lea dstq, [dstq+strideq*2]\n WRITE_8X2 %3, %4, %5, %6, %7\n%endmacro\n\n%macro INV_TXFM_8X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m1, m0, [coeffq]\n pmulhrsw m1, m0\n pmulhrsw m0, m1, [o(pw_1697x8)]\n paddsw m1, m0\n pmulhrsw m1, [o(pw_2048)]\n punpcklwd m1, m1\n punpckhdq m2, m1, m1\n punpckldq m1, m1\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckldq m0, m1, m1\n punpckhdq m1, m1\n%elifidn %1_%2, identity_dct\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m5, m2, m3\n punpcklwd m2, m3\n punpcklwd m0, m4\n punpcklwd m2, m5\n punpcklqdq m0, m2\n mova m4, [o(pw_2896x8)]\n pmulhrsw m0, m4\n paddsw m0, m0\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n%ifidn %2, dct\n mova m2, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else ; adst / flipadst\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n%endif\n%endif\n TAIL_CALL m(iadst_8x4_internal).end2\n%endif\n%endmacro\n\nINV_TXFM_8X4_FN dct, dct, 0\nINV_TXFM_8X4_FN dct, adst, 0\nINV_TXFM_8X4_FN dct, flipadst, 0\nINV_TXFM_8X4_FN dct, identity, 3\n\ncglobal idct_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n call m(idct_4x8_internal).main\n\n mova m4, [o(deint_shuf1)]\n mova m5, [o(deint_shuf2)]\n pshufb m0, m4\n pshufb m1, m5\n pshufb m2, m4\n pshufb m3, m5\n punpckhdq m4, m0, m1\n punpckldq m0, m1\n punpckhdq m5, m2, m3\n punpckldq m2, m3\n punpckhqdq m1, m0, m2 ;in1\n punpcklqdq m0, m2 ;in0\n punpckhqdq m3, m4, m5 ;in3\n punpcklqdq m2 ,m4, m5 ;in2\n jmp tx2q\n\n.pass2:\n call .main\n jmp m(iadst_8x4_internal).end\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n IDCT4_1D 0, 1, 2, 3, 4, 5, 6\n ret\n\nINV_TXFM_8X4_FN adst, dct\nINV_TXFM_8X4_FN adst, adst\nINV_TXFM_8X4_FN adst, flipadst\nINV_TXFM_8X4_FN adst, identity\n\ncglobal iadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n pxor m5, m5\n psubsw m3, m5, m1\n psubsw m5, m4\n punpckhdq m4, m5, m3\n punpckldq m5, m3\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m5 ;in1\n punpcklwd m0, m5 ;in0\n punpcklwd m2, m3, m4 ;in2\n punpckhwd m3, m4 ;in3\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end2:\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n mova [coeffq+16*2], m6\n mova [coeffq+16*3], m6\n.end3:\n WRITE_8X4 0, 1, 2, 3, 4, 5, 6\n RET\n\nALIGN function_align\n.main:\n punpckhwd m6, m0, m2 ;unpacked in0 in2\n punpcklwd m0, m2 ;unpacked in0 in2\n punpckhwd m7, m1, m3 ;unpacked in1 in3\n punpcklwd m1, m3 ;unpacked in1 in3\n\n mova m2, [o(pw_3344_m3344)]\n mova m4, [o(pw_0_3344)]\n pmaddwd m3, m2, m6 ;3344 * in0 - 3344 * in2\n pmaddwd m5, m4, m7 ;3344 * in3\n pmaddwd m2, m0\n pmaddwd m4, m1\n paddd m3, m5\n paddd m2, m4\n mova m4, [o(pd_2048)]\n paddd m3, m4 ;t2 + 2048\n paddd m2, m4\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n\n pmaddwd m4, m0, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m0, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m3, m1, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m1, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m3, m4 ;t0 + t3\n\n pmaddwd m1, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m4, [o(pd_2048)]\n paddd m0, m4\n paddd m4, m3 ;t0 + t3 + 2048\n paddd m5, m0 ;t1 + t3 + 2048\n paddd m3, m0\n paddd m3, m1 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m3, 12 ;out3\n packssdw m0, m4, m5 ;low: out0 high: out1\n\n pmaddwd m4, m6, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m6, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m1, m7, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m7, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m1, m4 ;t0 + t3\n pmaddwd m7, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n\n mova m4, [o(pd_2048)]\n paddd m6, m4\n paddd m4, m1 ;t0 + t3 + 2048\n paddd m5, m6 ;t1 + t3 + 2048\n paddd m1, m6\n paddd m1, m7 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m1, 12 ;out3\n packssdw m3, m1 ;out3\n packssdw m4, m5 ;low: out0 high: out1\n\n punpckhqdq m1, m0, m4 ;out1\n punpcklqdq m0, m4 ;out0\n ret\n\nINV_TXFM_8X4_FN flipadst, dct\nINV_TXFM_8X4_FN flipadst, adst\nINV_TXFM_8X4_FN flipadst, flipadst\nINV_TXFM_8X4_FN flipadst, identity\n\ncglobal iflipadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m5, m3, m2\n punpcklwd m3, m2\n punpckhwd m2, m1, m0\n punpcklwd m1, m0\n\n pxor m0, m0\n psubsw m4, m0, m2\n psubsw m0, m5\n punpckhdq m2, m0, m4\n punpckldq m0, m4\n punpckhdq m4, m3, m1\n punpckldq m3, m1\n punpckhwd m1, m0, m3 ;in1\n punpcklwd m0, m3 ;in0\n punpckhwd m3, m2, m4 ;in3\n punpcklwd m2, m4 ;in2\n jmp tx2q\n\n.pass2:\n call m(iadst_8x4_internal).main\n mova m4, m0\n mova m5, m1\n mova m0, m3\n mova m1, m2\n mova m2, m5\n mova m3, m4\n jmp m(iadst_8x4_internal).end\n\nINV_TXFM_8X4_FN identity, dct, 7\nINV_TXFM_8X4_FN identity, adst\nINV_TXFM_8X4_FN identity, flipadst\nINV_TXFM_8X4_FN identity, identity\n\ncglobal iidentity_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n paddsw m0, m0\n paddsw m1, m1\n paddsw m2, m2\n paddsw m3, m3\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n punpckhdq m5, m4, m1\n punpckldq m4, m1\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m4 ;in1\n punpcklwd m0, m4 ;in0\n punpcklwd m2, m3, m5 ;in2\n punpckhwd m3, m5 ;in3\n jmp tx2q\n\n.pass2:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddsw m0, m4\n paddsw m1, m5\n paddsw m2, m6\n paddsw m3, m7\n jmp m(iadst_8x4_internal).end\n\n%macro INV_TXFM_8X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x8, 8, 16*4\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n mova m1, [o(pw_16384)]\n pmulhrsw m0, m1\n psrlw m1, 2\n pmulhrsw m0, m1\n punpckhwd m7, m0, m0\n punpcklwd m0, m0\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end2\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n TAIL_CALL m(iadst_8x4_internal).end3\n%elif %3 >= 0\n%ifidn %1, dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 3\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n.end:\n mov r3d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x8).end3)]\n.loop:\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n jmp tx2q\n.end3:\n RET\n%else ; identity\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpcklwd m0, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n punpcklwd m2, [coeffq+16*6]\n punpcklwd m3, [coeffq+16*7]\n punpcklwd m0, m2\n punpcklwd m1, m3\n punpcklwd m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n pxor m4, m4\n REPX {mova [coeffq+16*x], m4}, 0, 1, 2, 3, 4, 5, 6, 7\n jmp m(inv_txfm_add_dct_dct_8x8).end\n%endif\n%endif\n%endmacro\n\n%macro LOAD_8ROWS 2-3 0 ; src, stride, is_rect2\n%if %3\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [%1+%2*0]\n pmulhrsw m1, m7, [%1+%2*1]\n pmulhrsw m2, m7, [%1+%2*2]\n pmulhrsw m3, m7, [%1+%2*3]\n pmulhrsw m4, m7, [%1+%2*4]\n pmulhrsw m5, m7, [%1+%2*5]\n pmulhrsw m6, m7, [%1+%2*6]\n pmulhrsw m7, [%1+%2*7]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n mova m7, [%1+%2*7]\n%endif\n%endmacro\n\n%macro IDCT8_1D_ODDHALF 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %1, %4, %5, %6, %7, 799, 4017 ;t4a, t7a\n ITX_MULSUB_2W %3, %2, %5, %6, %7, 3406, 2276, 1 ;t5a, t6a\n psubsw m%2, m%4, m%5 ;t6a\n paddsw m%4, m%5 ;t7\n psubsw m%5, m%1, m%3 ;t5a\n paddsw m%1, m%3 ;t4\n ITX_MULSUB_2W %2, %5, %3, %6, %7, 2896, 2896, 1 ;t5, t6\n%endmacro\n\nINV_TXFM_8X8_FN dct, dct, 0\nINV_TXFM_8X8_FN dct, identity, 7\nINV_TXFM_8X8_FN dct, adst\nINV_TXFM_8X8_FN dct, flipadst\n\ncglobal idct_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.pass1_end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n\n.pass1_end3:\n punpcklwd m6, m1, m5 ;10 50 11 51 12 52 13 53\n punpckhwd m1, m5 ;14 54 15 55 16 56 17 57\n punpckhwd m5, m0, m4 ;04 44 05 45 06 46 07 47\n punpcklwd m0, m4 ;00 40 01 41 02 42 03 43\n punpckhwd m4, m3, m7 ;34 74 35 75 36 76 37 77\n punpcklwd m3, m7 ;30 70 31 71 32 72 33 73\n punpckhwd m7, m1, m4 ;16 36 56 76 17 37 57 77\n punpcklwd m1, m4 ;14 34 54 74 15 35 55 75\n punpckhwd m4, m6, m3 ;12 32 52 72 13 33 53 73\n punpcklwd m6, m3 ;10 30 50 70 11 31 51 71\n mova [rsp+gprsize+16*2], m6\n mova m6, [rsp+gprsize+16*1]\n punpckhwd m3, m2, m6 ;24 64 25 65 26 66 27 67\n punpcklwd m2, m6 ;20 60 21 61 22 62 23 63\n punpckhwd m6, m5, m3 ;06 26 46 66 07 27 47 67\n punpcklwd m5, m3 ;04 24 44 64 05 25 45 65\n punpckhwd m3, m0, m2 ;02 22 42 62 03 23 43 63\n punpcklwd m0, m2 ;00 20 40 60 01 21 41 61\n\n punpckhwd m2, m6, m7 ;07 17 27 37 47 57 67 77\n punpcklwd m6, m7 ;06 16 26 36 46 56 66 76\n mova [rsp+gprsize+16*0], m2\n punpcklwd m2, m3, m4 ;02 12 22 32 42 52 62 72\n punpckhwd m3, m4 ;03 13 23 33 43 53 63 73\n punpcklwd m4, m5, m1 ;04 14 24 34 44 54 64 74\n punpckhwd m5, m1 ;05 15 25 35 45 55 65 75\n mova m7, [rsp+gprsize+16*2]\n punpckhwd m1, m0, m7 ;01 11 21 31 41 51 61 71\n punpcklwd m0, m7 ;00 10 20 30 40 50 60 70\n mova m7, [rsp+gprsize+16*0]\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*0], m7\n\n.end3:\n WRITE_8X4 0, 1, 2, 3, 5, 6, 7\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 4, [rsp+gprsize+16*2], [rsp+gprsize+16*1], [rsp+gprsize+16*0], 5, 6, 7\n jmp tx2q\n\n.end4:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m1\n mova m7, [o(pd_2048)]\n IDCT4_1D 0, 2, 4, 6, 1, 3, 7\n mova m3, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m2\n mova m2, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m4\n mova m4, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m6\n IDCT8_1D_ODDHALF 3, 2, 5, 4, 1, 6, 7\n mova m6, [rsp+gprsize*2+16*0]\n psubsw m7, m0, m4 ;out7\n paddsw m0, m4 ;out0\n mova [rsp+gprsize*2+16*0], m7\n mova m1, [rsp+gprsize*2+16*2]\n psubsw m4, m6, m3 ;out4\n paddsw m3, m6 ;out3\n mova m7, [rsp+gprsize*2+16*1]\n psubsw m6, m1, m5 ;out6\n paddsw m1, m5 ;out1\n psubsw m5, m7, m2 ;out5\n paddsw m2, m7 ;out2\n ret\n\n\nINV_TXFM_8X8_FN adst, dct\nINV_TXFM_8X8_FN adst, adst\nINV_TXFM_8X8_FN adst, flipadst\nINV_TXFM_8X8_FN adst, identity\n\ncglobal iadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n call .main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).pass1_end2\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n call .main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).end2\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m4\n mova m7, [o(pd_2048)]\n ITX_MULSUB_2W 5, 2, 3, 4, 7, 1931, 3612 ;t3a, t2a\n ITX_MULSUB_2W 1, 6, 3, 4, 7, 3920, 1189 ;t7a, t6a\n paddsw m3, m2, m6 ;t2\n psubsw m2, m6 ;t6\n paddsw m4, m5, m1 ;t3\n psubsw m5, m1 ;t7\n ITX_MULSUB_2W 5, 2, 1, 6, 7, 3784, 1567 ;t6a, t7a\n\n mova m6, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m5\n mova m1, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m2\n mova m5, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m3\n ITX_MULSUB_2W 5, 0, 2, 3, 7, 401, 4076 ;t1a, t0a\n ITX_MULSUB_2W 1, 6, 2, 3, 7, 3166, 2598 ;t5a, t4a\n psubsw m2, m0, m6 ;t4\n paddsw m0, m6 ;t0\n paddsw m3, m5, m1 ;t1\n psubsw m5, m1 ;t5\n ITX_MULSUB_2W 2, 5, 1, 6, 7, 1567, 3784 ;t5a, t4a\n\n mova m7, [rsp+gprsize*2+16*0]\n paddsw m1, m3, m4 ;-out7\n psubsw m3, m4 ;t3\n mova [rsp+gprsize*2+16*0], m1\n psubsw m4, m0, m7 ;t2\n paddsw m0, m7 ;out0\n mova m6, [rsp+gprsize*2+16*2]\n mova m7, [rsp+gprsize*2+16*1]\n paddsw m1, m5, m6 ;-out1\n psubsw m5, m6 ;t6\n paddsw m6, m2, m7 ;out6\n psubsw m2, m7 ;t7\n ret\nALIGN function_align\n.main_pass1_end:\n mova [rsp+gprsize*2+16*1], m1\n mova [rsp+gprsize*2+16*2], m6\n punpckhwd m1, m4, m3\n punpcklwd m4, m3\n punpckhwd m7, m5, m2\n punpcklwd m5, m2\n mova m2, [o(pw_2896_2896)]\n mova m6, [o(pd_2048)]\n pmaddwd m3, m2, m7\n pmaddwd m2, m5\n paddd m3, m6\n paddd m2, m6\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n mova m3, [o(pw_2896_m2896)]\n pmaddwd m7, m3\n pmaddwd m5, m3\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m5, m7 ;-out5\n mova m3, [o(pw_2896_2896)]\n pmaddwd m7, m3, m1\n pmaddwd m3, m4\n paddd m7, m6\n paddd m3, m6\n psrad m7, 12\n psrad m3, 12\n packssdw m3, m7 ;-out3\n mova m7, [o(pw_2896_m2896)]\n pmaddwd m1, m7\n pmaddwd m4, m7\n paddd m1, m6\n paddd m4, m6\n psrad m1, 12\n psrad m4, 12\n packssdw m4, m1 ;-out5\n mova m1, [rsp+gprsize*2+16*1]\n mova m6, [rsp+gprsize*2+16*2]\n ret\nALIGN function_align\n.main_pass2_end:\n paddsw m7, m4, m3 ;t2 + t3\n psubsw m4, m3 ;t2 - t3\n paddsw m3, m5, m2 ;t6 + t7\n psubsw m5, m2 ;t6 - t7\n mova m2, [o(pw_2896x8)]\n pmulhrsw m4, m2 ;out4\n pmulhrsw m5, m2 ;-out5\n pmulhrsw m7, m2 ;-out3\n pmulhrsw m2, m3 ;out2\n mova m3, m7\n ret\n\nINV_TXFM_8X8_FN flipadst, dct\nINV_TXFM_8X8_FN flipadst, adst\nINV_TXFM_8X8_FN flipadst, flipadst\nINV_TXFM_8X8_FN flipadst, identity\n\ncglobal iflipadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_m16384)]\n\n.pass1_end1:\n pmulhrsw m1, m7\n mova [rsp+gprsize+16*1], m1\n mova m1, m6\n mova m6, m2\n pmulhrsw m2, m5, m7\n mova m5, m6\n mova m6, m4\n pmulhrsw m4, m3, m7\n mova m3, m6\n mova m6, m0\n mova m0, m7\n pxor m7, m7\n psubw m7, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*2], m2\n mova m2, m0\n pxor m0, m0\n psubw m0, m7\n mova m7, m2\n pmulhrsw m1, m0\n pmulhrsw m2, m5, m0\n mova [rsp+gprsize+16*1], m1\n mova m5, m4\n mova m1, m6\n pmulhrsw m4, m3, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n mova m3, m5\n mova [rsp+gprsize+16*0], m7\n jmp m(idct_8x8_internal).end3\n\nINV_TXFM_8X8_FN identity, dct, 7\nINV_TXFM_8X8_FN identity, adst\nINV_TXFM_8X8_FN identity, flipadst\nINV_TXFM_8X8_FN identity, identity\n\ncglobal iidentity_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.end:\n pmulhrsw m7, [o(pw_4096)]\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_4096)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).end3\n\n\n%macro INV_TXFM_4X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x16, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n mova m1, m0\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m1, [coeffq+16*1]\n mova m2, [o(pw_16384)]\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddsw m0, m0\n paddsw m1, m1\n paddsw m0, m2\n paddsw m1, m3\n pmulhrsw m0, m4\n pmulhrsw m4, m1\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhwd m6, m4, m4\n punpcklwd m4, m4\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckhdq m5, m4, m4\n punpckldq m4, m4\n punpckhdq m7, m6, m6\n punpckldq m6, m6\n mova [coeffq+16*4], m4\n TAIL_CALL m(iadst_4x16_internal).end2\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n punpckldq m0, m1\n pmulhrsw m1, m0, [o(pw_1697x8)]\n pcmpeqw m2, m2\n pcmpeqw m2, m0\n pxor m0, m2\n pavgw m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n pxor m1, m1\n REPX {mova [coeffq+32*x], m1}, 0, 1, 2, 3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, [o(pw_16384)]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mova m1, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%endif\n.end:\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n RET\n%endif\n%endmacro\n\nINV_TXFM_4X16_FN dct, dct, 0\nINV_TXFM_4X16_FN dct, identity, 15\nINV_TXFM_4X16_FN dct, adst\nINV_TXFM_4X16_FN dct, flipadst\n\ncglobal idct_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_4x8_internal).pass1)]\n\n.pass1:\n mova m0, [coeffq+16*1]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n push tx2q\n lea tx2q, [o(m(idct_4x16_internal).pass1_2)]\n jmp r3\n\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(m(idct_4x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n pop tx2q\n\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*7], m7\n jmp tx2q\n\n.pass2:\n call m(idct_16x4_internal).main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n\n.end1:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 3, 2\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 3, 2\n\n.end2:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nINV_TXFM_4X16_FN adst, dct, 0\nINV_TXFM_4X16_FN adst, adst\nINV_TXFM_4X16_FN adst, flipadst\nINV_TXFM_4X16_FN adst, identity\n\ncglobal iadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpcklqdq m6, m5, m4 ;low: -out5 high: -out7\n punpckhqdq m4, m5 ;low: out8 high: out10\n punpcklqdq m5, m7, m2 ;low: out4 high: out6\n punpckhqdq m2, m7 ;low: -out9 high: -out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpckhqdq m1, m6, m0 ;low: -out13 high: -out15\n punpcklqdq m0, m6 ;low: out0 high: out2\n punpckhqdq m6, m3, m2 ;low: out12 high: out14\n punpcklqdq m2, m3 ;low: -out1 high: -out3\n\n mova m7, [o(pw_2048)]\n\n.end1:\n REPX {pmulhrsw x, m7}, m0, m5, m4, m6\n pxor m3, m3\n psubw m3, m7\n mova m7, [coeffq+16*4]\n REPX {pmulhrsw x, m3}, m2, m7, m1\n pmulhrsw m3, [coeffq+16*5]\n mova [coeffq+16*7], m5\n\n punpckhqdq m5, m4, m7 ;low: out10 high: out11\n punpcklqdq m4, m7 ;low: out8 high: out9\n punpckhqdq m7, m6, m1 ;low: out14 high: out15\n punpcklqdq m6, m1 ;low: out12 high: out13\n punpckhqdq m1, m0, m2 ;low: out2 high: out3\n punpcklqdq m0, m2 ;low: out0 high: out1\n mova [coeffq+16*4], m4\n mova m4, [coeffq+16*7]\n punpcklqdq m2, m4, m3 ;low: out4 high: out5\n punpckhqdq m4, m3 ;low: out6 high: out7\n mova m3, m4\n\n.end2:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 2, 3\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 2, 3\n\n.end3:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\n\nINV_TXFM_4X16_FN flipadst, dct, 0\nINV_TXFM_4X16_FN flipadst, adst\nINV_TXFM_4X16_FN flipadst, flipadst\nINV_TXFM_4X16_FN flipadst, identity\n\ncglobal iflipadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpckhqdq m6, m5, m4 ;low: out5 high: out7\n punpcklqdq m4, m5 ;low: -out8 high: -out10\n punpckhqdq m5, m7, m2 ;low: -out4 high: -out6\n punpcklqdq m2, m7 ;low: out9 high: out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpcklqdq m1, m6, m0 ;low: out13 high: out15\n punpckhqdq m0, m6 ;low: -out0 high: -out2\n punpcklqdq m6, m3, m2 ;low: -out12 high: -out14\n punpckhqdq m2, m3 ;low: out1 high: out3\n\n mova m7, [o(pw_m2048)]\n jmp m(iadst_4x16_internal).end1\n\n\nINV_TXFM_4X16_FN identity, dct, 3\nINV_TXFM_4X16_FN identity, adst\nINV_TXFM_4X16_FN identity, flipadst\nINV_TXFM_4X16_FN identity, identity\n\n%macro IDTX16 3-4 ; src/dst, tmp, pw_1697x16, [pw_16394]\n pmulhrsw m%2, m%3, m%1\n%if %0 == 4 ; if downshifting by 1\n pmulhrsw m%2, m%4\n%else\n paddsw m%1, m%1\n%endif\n paddsw m%1, m%2\n%endmacro\n\ncglobal iidentity_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*1]\n mova m6, [o(pw_1697x8)]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n pcmpeqw m7, m7\n mov r3, tx2q\n lea tx2q, [o(.pass1_2)]\n.pass1:\n pmulhrsw m4, m6, m0\n pmulhrsw m5, m6, m1\n pavgw m4, m0\n pcmpeqw m0, m7\n pavgw m5, m1\n pcmpeqw m1, m7\n pandn m0, m4\n pmulhrsw m4, m6, m2\n pandn m1, m5\n pmulhrsw m5, m6, m3\n pavgw m4, m2\n pcmpeqw m2, m7\n pavgw m5, m3\n pcmpeqw m3, m7\n pandn m2, m4\n pandn m3, m5\n jmp m(iadst_4x8_internal).pass1_end\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(.pass1_end)]\n jmp .pass1\n.pass1_end:\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n jmp r3\n.pass2:\n mova m7, [o(pw_1697x16)]\n mova [coeffq+16*6], m6\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [coeffq+16*7]\n IDTX16 6, 7, 7\n mova [coeffq+16*7], m6\n mova m6, [coeffq+16*6]\n pmulhrsw m7, m6, [o(pw_1697x16)]\n paddsw m6, m6\n paddsw m6, m7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n jmp m(iadst_4x16_internal).end2\n\n\n%macro INV_TXFM_16X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m3, [coeffq]\n mova m0, [o(pw_16384)]\n pmulhrsw m3, m0\n psrlw m0, 3 ; pw_2048\n pmulhrsw m1, m3, [o(pw_1697x8)]\n paddsw m3, m1\n pmulhrsw m3, m0\n punpcklwd m3, m3\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_16384)]\n mova m6, [o(pw_2896x8)]\n mov r3d, 2\n psrlw m7, m5, 3 ; pw_2048\n.main_loop:\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpcklwd m0, m2\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*3]\n punpckhwd m3, m1, m2\n punpcklwd m1, m2\n punpcklwd m1, m3\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n pmulhrsw m1, m5\n paddsw m0, m1\n pmulhrsw m0, m6\n pmulhrsw m0, m7\n.end:\n pxor m3, m3\n mova [coeffq+16*0], m3\n mova [coeffq+16*1], m3\n mova [coeffq+16*2], m3\n mova [coeffq+16*3], m3\n add coeffq, 16*4\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%else\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n%ifidn %2, dct\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n mov r2d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x4).end)]\n.dconly:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n.dconly_loop:\n mova m1, [dstq]\n mova m3, [dstq+strideq]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq], m1\n mova [dstq+strideq], m3\n lea dstq, [dstq+strideq*2]\n dec r2d\n jg .dconly_loop\n jmp tx2q\n.end:\n RET\n%else ; adst / flipadst\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov [coeffq], eobd\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end3\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end3\n%endif\n%endif\n%endif\n%endmacro\n\n%macro LOAD_7ROWS 2 ;src, stride\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n%endmacro\n\n%macro SAVE_7ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n%endmacro\n\n%macro IDCT16_1D_PACKED_ODDHALF 7 ;src[1-4], tmp[1-3]\n punpckhwd m%5, m%4, m%1 ;packed in13 in3\n punpcklwd m%1, m%4 ;packed in1 in15\n punpcklwd m%4, m%3, m%2 ;packed in9 in7\n punpckhwd m%2, m%3 ;packed in5 in11\n mova m%7, [o(pd_2048)]\n ITX_MUL2X_PACK %1, %6, %7, 401, 4076, 1 ;low: t8a high: t15a\n ITX_MUL2X_PACK %4, %6, %7, 3166, 2598, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %2, %6, %7, 1931, 3612, 1 ;low: t10a high: t13a\n ITX_MUL2X_PACK %5, %6, %7, 3920, 1189, 1 ;low: t11a high: t12a\n psubsw m%6, m%1, m%4 ;low: t9 high: t14\n paddsw m%1, m%4 ;low: t8 high: t15\n psubsw m%4, m%5, m%2 ;low: t10 high: t13\n paddsw m%5, m%2 ;low: t11 high: t12\n mova m%2, [o(deint_shuf2)]\n pshufb m%6, m%2\n pshufb m%4, m%2\n ITX_MUL2X_PACK %6, %3, %7, 1567, 3784, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %4, %3, %7, m3784, 1567, 1 ;low: t10a high: t13a\n psubsw m%3, m%1, m%5 ;low: t11a high: t12a\n paddsw m%1, m%5 ;low: t8a high: t15a\n psubsw m%5, m%6, m%4 ;low: t10 high: t13\n paddsw m%6, m%4 ;low: t9 high: t14\n pshufb m%3, m%2\n pshufb m%5, m%2\n ITX_MUL2X_PACK %3, %2, %7, 2896, 2896, 4 ;t12, t11\n ITX_MUL2X_PACK %5, %4, %7, 2896, 2896, 4 ;t13a, t10a\n packssdw m%2, m%4 ;low: t11 high: t10a\n packssdw m%3, m%5 ;low: t12 high: t13a\n punpckhqdq m%4, m%1, m%6 ;low: t15a high: t14\n punpcklqdq m%1, m%6 ;low: t8a high: t9\n%endmacro\n\nINV_TXFM_16X4_FN dct, dct, 0\nINV_TXFM_16X4_FN dct, adst, 0\nINV_TXFM_16X4_FN dct, flipadst, 0\nINV_TXFM_16X4_FN dct, identity, 3\n\ncglobal idct_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n\n.pass1_end:\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpcklwd m2, m1, m3 ;packed out3, out7\n punpckhwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpcklwd m6, m5, m7 ;packed out11, out15\n punpckhwd m5, m7 ;packed out10, out14\n\n.pass1_end2:\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*6]\n mova [coeffq+16*6], m7\n\n.pass1_end3:\n punpckhwd m7, m3, m6 ;packed 9, 11, 13, 15 high\n punpcklwd m3, m6 ;packed 9, 10, 13, 15 low\n punpckhwd m6, m4, m5 ;packed 8, 10, 12, 14 high\n punpcklwd m4, m5 ;packed 8, 10, 12, 14 low\n punpckhwd m5, m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(1)\n punpcklwd m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(0)\n punpckhwd m3, m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(3)\n punpcklwd m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(2)\n mova [coeffq+16*7], m3\n mova m3, [coeffq+16*6]\n punpckhwd m7, m3, m2 ;packed 1, 3, 5, 7 high\n punpcklwd m3, m2 ;packed 1, 3, 5, 7 low\n punpckhwd m2, m0, m1 ;packed 0, 2, 4, 6 high\n punpcklwd m0, m1 ;packed 0, 2, 4, 6 low\n punpckhwd m1, m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(1)\n punpcklwd m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(0)\n punpckhwd m3, m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(3)\n punpcklwd m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(2)\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x4_internal).pass2)]\n\n.pass2_end:\n mova [coeffq+16*4], m4\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n lea r3, [dstq+8]\n call tx2q\n\n add coeffq, 16*4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mov dstq, r3\n jmp tx2q\n\nALIGN function_align\n.main:\n punpckhqdq m7, m0, m1 ;low:in1 high:in3\n punpcklqdq m0, m1\n punpcklqdq m1, m2, m3\n punpckhqdq m3, m2 ;low:in7 high:in5\n mova [coeffq+16*4], m7\n mova [coeffq+16*5], m3\n mova m7, [coeffq+16*7]\n punpcklqdq m2, m4, m5\n punpckhqdq m4, m5 ;low:in9 high:in11\n punpcklqdq m3, m6, m7\n punpckhqdq m7, m6 ;low:in15 high:in13\n mova [coeffq+16*6], m4\n IDCT8_1D_PACKED\n mova m6, [coeffq+16*4]\n mova m4, [coeffq+16*5]\n mova m5, [coeffq+16*6]\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*6], m3\n\n IDCT16_1D_PACKED_ODDHALF 6, 4, 5, 7, 1, 2, 3\n\n mova m1, [coeffq+16*4]\n psubsw m3, m0, m7 ;low:out15 high:out14\n paddsw m0, m7 ;low:out0 high:out1\n psubsw m7, m1, m5 ;low:out12 high:out13\n paddsw m1, m5 ;low:out3 high:out2\n mova [coeffq+16*7], m3\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*6]\n psubsw m5, m2, m4 ;low:out11 high:out10\n paddsw m2, m4 ;low:out4 high:out5\n psubsw m4, m3, m6 ;low:out8 high:out9\n paddsw m3, m6 ;low:out7 high:out6\n mova m6, m7\n ret\n\nINV_TXFM_16X4_FN adst, dct\nINV_TXFM_16X4_FN adst, adst\nINV_TXFM_16X4_FN adst, flipadst\nINV_TXFM_16X4_FN adst, identity\n\ncglobal iadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n call .main_pass1_end\n\n punpckhwd m6, m7, m0 ;packed -out11, -out15\n punpcklwd m0, m7 ;packed out0, out4\n punpcklwd m7, m3, m4 ;packed -out3, -out7\n punpckhwd m4, m3 ;packed out8, out12\n mova m1, [coeffq+16*6]\n punpcklwd m3, m1, m5 ;packed -out1, -out5\n punpckhwd m5, m1 ;packed out10, out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpckhwd m3, m2, m1 ;packed -out9, -out13\n punpcklwd m1, m2 ;packed out2, out6\n\n mova m7, [o(pw_16384)]\n\n.pass1_end:\n REPX {pmulhrsw x, m7}, m0, m1, m4, m5\n pxor m2, m2\n psubw m2, m7\n mova m7, [coeffq+16*6]\n REPX {pmulhrsw x, m2}, m7, m3, m6\n pmulhrsw m2, [coeffq+16*7]\n mova [coeffq+16*6], m7\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\nALIGN function_align\n.main:\n mova [coeffq+16*6], m0\n pshufd m0, m1, q1032\n pshufd m2, m2, q1032\n punpckhwd m1, m6, m0 ;packed in13, in2\n punpcklwd m0, m6 ;packed in3, in12\n punpckhwd m7, m5, m2 ;packed in11, in4\n punpcklwd m2, m5 ;packed in5, in10\n mova m6, [o(pd_2048)]\n ITX_MUL2X_PACK 1, 5, 6, 995, 3973 ;low:t2 high:t3\n ITX_MUL2X_PACK 7, 5, 6, 1751, 3703 ;low:t4 high:t5\n ITX_MUL2X_PACK 2, 5, 6, 3513, 2106 ;low:t10 high:t11\n ITX_MUL2X_PACK 0, 5, 6, 3857, 1380 ;low:t12 high:t13\n psubsw m5, m1, m2 ;low:t10a high:t11a\n paddsw m1, m2 ;low:t2a high:t3a\n psubsw m2, m7, m0 ;low:t12a high:t13a\n paddsw m7, m0 ;low:t4a high:t5a\n punpcklqdq m0, m5\n punpckhwd m0, m5 ;packed t10a, t11a\n punpcklqdq m5, m2\n punpckhwd m2, m5 ;packed t13a, t12a\n ITX_MUL2X_PACK 0, 5, 6, 3406, 2276 ;low:t10 high:t11\n ITX_MUL2X_PACK 2, 5, 6, 4017, 799, 1 ;low:t12 high:t13\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m7\n mova m1, [coeffq+16*6]\n mova m7, [coeffq+16*7]\n pshufd m1, m1, q1032\n pshufd m3, m3, q1032\n punpckhwd m5, m7, m1 ;packed in15, in0\n punpcklwd m1, m7 ;packed in1, in14\n punpckhwd m7, m4, m3 ;packed in9, in6\n punpcklwd m3, m4 ;packed in7, in8\n ITX_MUL2X_PACK 5, 4, 6, 201, 4091 ;low:t0 high:t1\n ITX_MUL2X_PACK 7, 4, 6, 2440, 3290 ;low:t6 high:t7\n ITX_MUL2X_PACK 3, 4, 6, 3035, 2751 ;low:t8 high:t9\n ITX_MUL2X_PACK 1, 4, 6, 4052, 601 ;low:t14 high:t15\n psubsw m4, m5, m3 ;low:t8a high:t9a\n paddsw m5, m3 ;low:t0a high:t1a\n psubsw m3, m7, m1 ;low:t14a high:t15a\n paddsw m7, m1 ;low:t6a high:t7a\n punpcklqdq m1, m4\n punpckhwd m1, m4 ;packed t8a, t9a\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t15a, t14a\n ITX_MUL2X_PACK 1, 4, 6, 799, 4017 ;low:t8 high:t9\n ITX_MUL2X_PACK 3, 4, 6, 2276, 3406, 1 ;low:t14 high:t15\n paddsw m4, m1, m2 ;low:t12a high:t13a\n psubsw m1, m2 ;low:t8a high:t9a\n psubsw m2, m0, m3 ;low:t14a high:t15a\n paddsw m0, m3 ;low:t10a high:t11a\n punpcklqdq m3, m1\n punpckhwd m3, m1 ;packed t12a, t13a\n punpcklqdq m1, m2\n punpckhwd m2, m1 ;packed t15a, t14a\n ITX_MUL2X_PACK 3, 1, 6, 1567, 3784 ;low:t12 high:t13\n ITX_MUL2X_PACK 2, 1, 6, 3784, 1567, 1 ;low:t14 high:t15\n psubsw m1, m3, m2 ;low:t14a high:t15a\n paddsw m3, m2 ;low:out2 high:-out13\n psubsw m2, m4, m0 ;low:t10 high:t11\n paddsw m0, m4 ;low:-out1 high:out14\n mova [coeffq+16*6], m0\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n psubsw m4, m5, m3 ;low:t4 high:t5\n paddsw m5, m3 ;low:t0 high:t1\n psubsw m3, m0, m7 ;low:t6 high:t7\n paddsw m0, m7 ;low:t2 high:t3\n punpcklqdq m7, m4\n punpckhwd m7, m4 ;packed t4, t5\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t7, t6\n ITX_MUL2X_PACK 7, 4, 6, 1567, 3784 ;low:t4a high:t5a\n ITX_MUL2X_PACK 3, 4, 6, 3784, 1567, 1 ;low:t6a high:t7a\n psubsw m4, m5, m0 ;low:t2a high:t3a\n paddsw m0, m5 ;low:out0 high:-out15\n psubsw m5, m7, m3 ;low:t6 high:t7\n paddsw m3, m7 ;low:-out3 high:out12\n ret\nALIGN function_align\n.main_pass1_end:\n mova m7, [o(deint_shuf1)]\n mova [coeffq+16*4], m0\n mova [coeffq+16*5], m3\n mova m0, [o(pw_2896_m2896)]\n mova m3, [o(pw_2896_2896)]\n pshufb m1, m7 ;t14a t15a\n pshufb m2, m7 ;t10 t11\n pshufb m4, m7 ;t2a t3a\n pshufb m5, m7 ;t6 t7\n pmaddwd m7, m0, m2\n pmaddwd m2, m3\n paddd m7, m6\n paddd m2, m6\n psrad m7, 12\n psrad m2, 12\n packssdw m2, m7 ;low:out6 high:-out9\n pmaddwd m7, m0, m4\n pmaddwd m4, m3\n paddd m7, m6\n paddd m4, m6\n psrad m7, 12\n psrad m4, 12\n packssdw m4, m7 ;low:-out7 high:out8\n pmaddwd m7, m3, m5\n pmaddwd m5, m0\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m7, m5 ;low:out4 high:-out11\n pmaddwd m5, m3, m1\n pmaddwd m1, m0\n paddd m5, m6\n paddd m1, m6\n psrad m5, 12\n psrad m1, 12\n packssdw m5, m1 ;low:-out5 high:out10\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n punpckhqdq m6, m2, m1 ;low:t11 high:t15a\n punpcklqdq m2, m1 ;low:t10 high:t14a\n psubsw m1, m2, m6\n paddsw m2, m6\n punpckhqdq m6, m4, m5 ;low:t3a high:t7\n punpcklqdq m4, m5 ;low:t2a high:t6\n psubsw m5, m4, m6\n paddsw m4, m6\n pmulhrsw m1, m7 ;low:-out9 high:out10\n pmulhrsw m2, m7 ;low:out6 high:-out5\n pmulhrsw m5, m7 ;low:out8 high:-out11\n pmulhrsw m4, m7 ;low:-out7 high:out4\n punpckhqdq m7, m4, m5 ;low:out4 high:-out11\n punpcklqdq m4, m5 ;low:-out7 high:out8\n punpckhqdq m5, m2, m1 ;low:-out5 high:out10\n punpcklqdq m2, m1 ;low:out6 high:-out9\n ret\n\n\nINV_TXFM_16X4_FN flipadst, dct\nINV_TXFM_16X4_FN flipadst, adst\nINV_TXFM_16X4_FN flipadst, flipadst\nINV_TXFM_16X4_FN flipadst, identity\n\ncglobal iflipadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass1_end\n\n punpcklwd m6, m7, m0 ;packed out11, out15\n punpckhwd m0, m7 ;packed -out0, -out4\n punpckhwd m7, m3, m4 ;packed out3, out7\n punpcklwd m4, m3 ;packed -out8, -out12\n mova m1, [coeffq+16*6]\n punpckhwd m3, m1, m5 ;packed out1, out5\n punpcklwd m5, m1 ;packed -out10, -out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpcklwd m3, m2, m1 ;packed out9, out13\n punpckhwd m1, m2 ;packed -out2, -out6\n\n mova m7, [o(pw_m16384)]\n jmp m(iadst_16x4_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\nINV_TXFM_16X4_FN identity, dct, 15\nINV_TXFM_16X4_FN identity, adst\nINV_TXFM_16X4_FN identity, flipadst\nINV_TXFM_16X4_FN identity, identity\n\ncglobal iidentity_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m1, [coeffq+16*6]\n mova m0, [coeffq+16*5]\n mova m2, [coeffq+16*7]\n mova m6, [o(pw_1697x16)]\n mova m7, [o(pw_16384)]\n pmulhrsw m4, m6, m1\n pmulhrsw m3, m6, m0\n pmulhrsw m5, m6, m2\n pmulhrsw m4, m7\n pmulhrsw m3, m7\n pmulhrsw m5, m7\n paddsw m1, m4\n paddsw m0, m3\n paddsw m5, m2\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mova m4, [coeffq+16*4]\n mova [coeffq+16*6], m1\n mova [coeffq+16*5], m0\n mova [coeffq+16*7], m5\n pmulhrsw m0, m6, m2\n pmulhrsw m1, m6, m3\n pmulhrsw m5, m6, m4\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n pmulhrsw m5, m7\n paddsw m2, m0\n paddsw m3, m1\n paddsw m4, m5\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pmulhrsw m5, m6, m0\n pmulhrsw m6, m1\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n paddsw m0, m5\n paddsw m1, m6\n mova m6, [coeffq+16*6]\n mova m5, [coeffq+16*5]\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpckhwd m2, m1, m3 ;packed out3, out7\n punpcklwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpckhwd m6, m5, m7 ;packed out11, out15\n punpcklwd m5, m7 ;packed out10, out14\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\n%macro SAVE_8ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n mova [%1+%2*7], m7\n%endmacro\n\n%macro INV_TXFM_8X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n psrlw m2, 3 ; pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mov r3d, 2\n.loop:\n mova m0, [o(pw_2896x8)]\n pmulhrsw m7, m0, [coeffq]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, m7, [o(pw_1697x16)]\n paddsw m7, m7\n paddsw m7, m0\n pmulhrsw m7, m1\n punpcklwd m0, m7, m7\n punpckhwd m7, m7\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end3\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n call m(iadst_8x4_internal).end3\n\n add coeffq, 16\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n add coeffq, 32*4\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m3, [coeffq+32*2]\n punpcklwd m3, [coeffq+32*3]\n mova m4, [o(pw_2896x8)]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m0, m2\n punpckldq m1, m3\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_identity_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%endif\n%endmacro\n\nINV_TXFM_8X16_FN dct, dct, 0\nINV_TXFM_8X16_FN dct, identity, 15\nINV_TXFM_8X16_FN dct, adst\nINV_TXFM_8X16_FN dct, flipadst\n\ncglobal idct_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_8x8_internal).pass1)]\n\n.pass1:\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov [rsp+gprsize+16*11], tx2q\n lea tx2q, [o(m(idct_8x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, [rsp+gprsize+16*11]\n jmp r3\n\n.pass2:\n lea tx2q, [o(m(idct_8x16_internal).end)]\n\n.pass2_pre:\n mova [coeffq+16*2 ], m1\n mova [coeffq+16*6 ], m3\n mova [coeffq+16*10], m5\n mova [coeffq+16*14], m7\n mova m1, m2\n mova m2, m4\n mova m3, m6\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n\n.pass2_main:\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+16*2 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*10]\n mova m3, [coeffq+16*14]\n mova m4, [coeffq+16*3 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*15]\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n ret\n\nINV_TXFM_8X16_FN adst, dct\nINV_TXFM_8X16_FN adst, adst\nINV_TXFM_8X16_FN adst, flipadst\nINV_TXFM_8X16_FN adst, identity\n\ncglobal iadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(iadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN flipadst, dct\nINV_TXFM_8X16_FN flipadst, adst\nINV_TXFM_8X16_FN flipadst, flipadst\nINV_TXFM_8X16_FN flipadst, identity\n\ncglobal iflipadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x16_internal).end)]\n lea r3, [dstq+strideq*8]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n jmp m(iflipadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN identity, dct, 7\nINV_TXFM_8X16_FN identity, adst\nINV_TXFM_8X16_FN identity, flipadst\nINV_TXFM_8X16_FN identity, identity\n\ncglobal iidentity_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_8x16_internal).pass1_end)]\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, r3\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m6\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*2], m5\n IDTX16 6, 5, 7\n mova m5, [rsp+gprsize+16*0]\n IDTX16 5, 7, 7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [rsp+gprsize+16*2]\n mova [rsp+gprsize+16*0], m5\n mova [rsp+gprsize+16*1], m6\n mova [rsp+gprsize+16*2], m7\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\n%macro INV_TXFM_16X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x8, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x8).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m7, [coeffq]\n mova m0, [o(pw_2896x8)]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 2 ; pw_4096\n pmulhrsw m7, m1\n punpcklwd m3, m7, m7\n punpckhwd m7, m7\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea r3, [dstq+strideq*4]\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n call m(iadst_8x4_internal).end2\n mov dstq, r3\n add coeffq, 16*4\n pshufd m0, m7, q0000\n pshufd m1, m7, q1111\n pshufd m2, m7, q2222\n pshufd m3, m7, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_2896x8)]\n mova m5, [o(pw_1697x16)]\n mova m6, [o(pw_16384)]\n psrlw m7, m6, 3 ; pw_2048\n mov r3d, 2\n.main_loop:\n mova m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n mova m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n punpckldq m0, m1\n mova m1, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n mova m2, [coeffq+16*6]\n punpcklwd m2, [coeffq+16*7]\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m1, m5, m0\n pmulhrsw m1, m6\n paddsw m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m7\n.end:\n pxor m1, m1\n REPX {mova [coeffq+16*x], m1}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16*8\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X8_FN dct, dct, 0\nINV_TXFM_16X8_FN dct, identity, 7\nINV_TXFM_16X8_FN dct, adst\nINV_TXFM_16X8_FN dct, flipadst\n\ncglobal idct_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*0, 32, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*1, 32, 1\n call .main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x8_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(idct_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).pass2_main\n\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n mova [rsp+gprsize*2+32*5], m5\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 0, 7, 2, 5, 6, 401, 4076 ;t8a, t15a\n ITX_MULSUB_2W 4, 3, 2, 5, 6, 3166, 2598 ;t9a, t14a\n psubsw m2, m0, m4 ;t9\n paddsw m0, m4 ;t8\n psubsw m4, m7, m3 ;t14\n paddsw m7, m3 ;t15\n ITX_MULSUB_2W 4, 2, 3, 5, 6, 1567, 3784 ;t9a, t14a\n mova m3, [rsp+gprsize*2+16*1]\n mova m5, [rsp+gprsize*2+32*5]\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+32*5], m4\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m7\n ITX_MULSUB_2W 3, 5, 7, 4, 6, 1931, 3612 ;t10a, t13a\n ITX_MULSUB_2W 2, 1, 7, 4, 6, 3920, 1189 ;t11a, t12a\n psubsw m4, m2, m3 ;t10\n paddsw m2, m3 ;t11\n psubsw m3, m1, m5 ;t13\n paddsw m1, m5 ;t12\n ITX_MULSUB_2W 3, 4, 7, 5, 6, m3784, 1567 ;t10a, t13a\n mova m7, [rsp+gprsize*2+32*5]\n psubsw m6, m0, m2 ;t11a\n paddsw m0, m2 ;t8a\n paddsw m2, m7, m3 ;t9\n psubsw m7, m3 ;t10\n mova m5, [rsp+gprsize*2+16*0]\n psubsw m3, m5, m0 ;out8\n paddsw m0, m5 ;out7\n mova [rsp+gprsize*2+32*5], m0\n mova m5, [rsp+gprsize*2+16*9]\n psubsw m0, m5, m2 ;out9\n paddsw m2, m5 ;out6\n mova [rsp+gprsize*2+16*0], m0\n mova [rsp+gprsize*2+16*9], m2\n mova m0, [rsp+gprsize*2+16*1]\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*1], m3\n psubsw m5, m0, m4 ;t13\n paddsw m0, m4 ;t14\n mova m3, [o(pd_2048)]\n psubsw m4, m2, m1 ;t12a\n paddsw m1, m2 ;t15a\n mova [rsp+gprsize*2+16*2], m1\n ITX_MULSUB_2W 5, 7, 1, 2, 3, 2896, 2896 ;t10a, t13a\n ITX_MULSUB_2W 4, 6, 1, 2, 3, 2896, 2896 ;t11, t12\n mova m3, [rsp+gprsize*2+16*8]\n psubsw m2, m3, m5 ;out10\n paddsw m3, m5 ;out5\n mova m5, [rsp+gprsize*2+16*7]\n mova [rsp+gprsize*2+16*8], m3\n psubsw m3, m5, m4 ;out11\n paddsw m5, m4 ;out4\n mova m4, [rsp+gprsize*2+16*6]\n mova [rsp+gprsize*2+16*7], m5\n paddsw m5, m4, m6 ;out3\n psubsw m4, m6 ;out12\n mova m6, [rsp+gprsize*2+16*5]\n mova [rsp+gprsize*2+16*6], m5\n psubsw m5, m6, m7 ;out13\n paddsw m6, m7 ;out2\n mova m7, [rsp+gprsize*2+16*4]\n mova [rsp+gprsize*2+16*5], m6\n psubsw m6, m7, m0 ;out14\n paddsw m7, m0 ;out1\n mova m1, [rsp+gprsize*2+16*2]\n mova m0, [rsp+gprsize*2+16*3]\n mova [rsp+gprsize*2+16*4], m7\n psubsw m7, m0, m1 ;out15\n paddsw m0, m1 ;out0\n mova [rsp+gprsize*2+16*3], m0\n mova m1, [rsp+gprsize*2+16*0]\n mova m0, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*0], m7\n ret\n\nINV_TXFM_16X8_FN adst, dct\nINV_TXFM_16X8_FN adst, adst\nINV_TXFM_16X8_FN adst, flipadst\nINV_TXFM_16X8_FN adst, identity\n\ncglobal iadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call .main\n call .main_pass1_end\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x8_internal).pass1_end)]\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).pass2_main\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m1\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 7, 0, 1, 2, 6, 995, 3973 ;t3, t2\n ITX_MULSUB_2W 3, 4, 1, 2, 6, 3513, 2106 ;t11, t10\n psubsw m1, m0, m4 ;t10a\n paddsw m0, m4 ;t2a\n psubsw m4, m7, m3 ;t11a\n paddsw m3, m7 ;t3a\n ITX_MULSUB_2W 1, 4, 7, 2, 6, 3406, 2276 ;t11, t10\n mova m2, [rsp+gprsize*2+16*0] ;in3\n mova m7, [rsp+gprsize*2+16*1] ;in4\n mova [rsp+gprsize*2+16*0], m1 ;t11\n mova [rsp+gprsize*2+16*1], m4 ;t10\n mova m1, [rsp+gprsize*2+16*2] ;in12\n mova [rsp+gprsize*2+16*2], m0 ;t2a\n ITX_MULSUB_2W 5, 7, 0, 4, 6, 1751, 3703 ;t5, t4\n ITX_MULSUB_2W 2, 1, 0, 4, 6, 3857, 1380 ;t13, t12\n psubsw m0, m7, m1 ;t12a\n paddsw m1, m7 ;t4a\n psubsw m4, m5, m2 ;t13a\n paddsw m5, m2 ;t5a\n ITX_MULSUB_2W 4, 0, 7, 2, 6, 4017, 799 ;t12, t13\n mova m2, [rsp+gprsize*2+16*8] ;in1\n mova m7, [rsp+gprsize*2+16*9] ;in14\n mova [rsp+gprsize*2+16*8], m4 ;t12\n mova [rsp+gprsize*2+16*9], m0 ;t13\n mova m4, [rsp+gprsize*2+16*4] ;in9\n mova m0, [rsp+gprsize*2+16*5] ;in6\n mova [rsp+gprsize*2+16*4], m1 ;t4a\n mova [rsp+gprsize*2+16*5], m5 ;t5a\n ITX_MULSUB_2W 2, 7, 1, 5, 6, 4052, 601 ;t15, t14\n ITX_MULSUB_2W 4, 0, 1, 5, 6, 2440, 3290 ;t7, t6\n psubsw m1, m0, m7 ;t14a\n paddsw m0, m7 ;t6a\n psubsw m5, m4, m2 ;t15a\n paddsw m4, m2 ;t7a\n ITX_MULSUB_2W 5, 1, 7, 2, 6, 2276, 3406 ;t14, t15\n mova m2, [rsp+gprsize*2+16*2] ;t2a\n mova [rsp+gprsize*2+16*2], m5 ;t14\n psubsw m7, m2, m0 ;t6\n paddsw m2, m0 ;t2\n psubsw m0, m3, m4 ;t7\n paddsw m3, m4 ;t3\n ITX_MULSUB_2W 0, 7, 4, 5, 6, 3784, 1567 ;t6a, t7a\n mova m4, [rsp+gprsize*2+16*7] ;in0\n mova m5, [rsp+gprsize*2+32*5] ;in15\n mova [rsp+gprsize*2+16*7], m3 ;t3\n mova [rsp+gprsize*2+32*5], m1 ;t15\n mova m1, [rsp+gprsize*2+16*6] ;in7\n mova m3, [rsp+gprsize*2+16*3] ;in8\n mova [rsp+gprsize*2+16*6], m7 ;t7a\n mova [rsp+gprsize*2+16*3], m0 ;t6a\n ITX_MULSUB_2W 5, 4, 0, 7, 6, 201, 4091 ;t1, t0\n ITX_MULSUB_2W 1, 3, 0, 7, 6, 3035, 2751 ;t9, t8\n psubsw m0, m4, m3 ;t8a\n paddsw m4, m3 ;t0a\n psubsw m3, m5, m1 ;t9a\n paddsw m5, m1 ;t1a\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 799, 4017 ;t9, t8\n mova m1, [rsp+gprsize*2+16*4] ;t4a\n mova m7, [rsp+gprsize*2+16*5] ;t5a\n mova [rsp+gprsize*2+16*4], m3 ;t8\n mova [rsp+gprsize*2+16*5], m0 ;t9\n psubsw m0, m4, m1 ;t4\n paddsw m4, m1 ;t0\n psubsw m3, m5, m7 ;t5\n paddsw m5, m7 ;t1\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 1567, 3784 ;t5a, t4a\n mova m7, [rsp+gprsize*2+16*3] ;t6a\n psubsw m1, m4, m2 ;t2a\n paddsw m4, m2 ;out0\n mova [rsp+gprsize*2+16*3], m4 ;out0\n mova m4, [rsp+gprsize*2+16*6] ;t7a\n psubsw m2, m3, m7 ;t6\n paddsw m3, m7 ;-out3\n mova [rsp+gprsize*2+16*6], m3 ;-out3\n psubsw m3, m0, m4 ;t7\n paddsw m0, m4 ;out12\n mova [rsp+gprsize*2+16*12], m3\n mova m3, [rsp+gprsize*2+16*7] ;t3\n mova [rsp+gprsize*2+16* 7], m2 ;out4\n psubsw m2, m5, m3 ;t3a\n paddsw m5, m3 ;-out15\n mova [rsp+gprsize*2+16*11], m2\n mova m2, [rsp+gprsize*2+32*5] ;t15\n mova [rsp+gprsize*2+16*10], m1 ;-out7\n mova m1, [rsp+gprsize*2+16*0] ;t11\n mova [rsp+gprsize*2+16*0 ], m5 ;-out15\n mova m3, [rsp+gprsize*2+16*1] ;t10\n mova [rsp+gprsize*2+16*1 ], m4 ;-out11\n mova m4, [rsp+gprsize*2+16*2] ;t14\n mova [rsp+gprsize*2+16*2 ], m0 ;out12\n psubsw m0, m3, m4 ;t14a\n paddsw m3, m4 ;t10a\n psubsw m5, m1, m2 ;t15a\n paddsw m1, m2 ;t11a\n ITX_MULSUB_2W 5, 0, 2, 4, 6, 3784, 1567 ;t14, t15\n mova m2, [rsp+gprsize*2+16*4] ;t8\n mova m4, [rsp+gprsize*2+16*5] ;t9\n mova [rsp+gprsize*2+16*4], m3 ;t10a\n mova [rsp+gprsize*2+16*5], m1 ;t11a\n mova m3, [rsp+gprsize*2+16*8] ;t12\n mova m1, [rsp+gprsize*2+16*9] ;t13\n mova [rsp+gprsize*2+16*8], m5 ;t14\n mova [rsp+gprsize*2+16*9], m0 ;t15\n psubsw m5, m2, m3 ;t12a\n paddsw m2, m3 ;t8a\n psubsw m0, m4, m1 ;t13a\n paddsw m4, m1 ;t9a\n ITX_MULSUB_2W 5, 0, 1, 3, 6, 1567, 3784 ;t13, t12\n mova m6, [rsp+gprsize*2+16*4] ;t10a\n mova m1, [rsp+gprsize*2+16*5] ;t11a\n psubsw m3, m2, m6 ;t10\n paddsw m2, m6 ;-out1\n paddsw m6, m4, m1 ;out14\n psubsw m4, m1 ;t11\n mova [rsp+gprsize*2+16*14], m4\n mova [rsp+gprsize*2+16* 4], m2 ;-out1\n mova m4, [rsp+gprsize*2+16*8] ;t14\n mova m2, [rsp+gprsize*2+16*9] ;t15\n mova [rsp+gprsize*2+16* 9], m3 ;out6\n psubsw m3, m0, m4 ;t14a\n paddsw m0, m4 ;out2\n psubsw m4, m5, m2 ;t15a\n paddsw m5, m2 ;-out13\n mova [rsp+gprsize*2+16* 5], m0 ;out2\n ret\nALIGN function_align\n.main_pass1_end:\n mova m0, [rsp+gprsize*2+16*14]\n mova [rsp+gprsize*2+16*14], m5\n mova [rsp+gprsize*2+16*15], m6\n mova m5, [o(pw_2896_2896)]\n mova m6, [o(pw_2896_m2896)]\n mova m7, [o(pd_2048)]\n punpcklwd m2, m3, m4\n punpckhwd m3, m4\n pmaddwd m4, m5, m2\n pmaddwd m2, m6\n pmaddwd m1, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m4, m2, m1, m3\n REPX {psrad x, 12}, m4, m1, m2, m3\n packssdw m4, m1 ;-out5\n packssdw m2, m3 ;out10\n mova [rsp+gprsize*2+16* 8], m4\n mova m3, [rsp+gprsize*2+16* 9]\n punpcklwd m1, m3, m0\n punpckhwd m3, m0\n pmaddwd m0, m5, m1\n pmaddwd m1, m6\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m0, m1, m4, m3\n REPX {psrad x, 12}, m0, m4, m1, m3\n packssdw m0, m4 ;out6\n packssdw m1, m3 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n mova m0, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n punpcklwd m3, m0, m4\n punpckhwd m0, m4\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n pmaddwd m5, m0\n pmaddwd m0, m6\n REPX {paddd x, m7}, m4, m3, m5, m0\n REPX {psrad x, 12}, m4, m5, m3, m0\n packssdw m4, m5 ;out4\n packssdw m3, m0 ;-out11\n mova [rsp+gprsize*2+16* 7], m4\n mova m4, [rsp+gprsize*2+16*10]\n mova m5, [rsp+gprsize*2+16*11]\n punpcklwd m0, m4, m5\n punpckhwd m4, m5\n pmaddwd m5, m0, [o(pw_2896_2896)]\n pmaddwd m0, m6\n pmaddwd m6, m4\n pmaddwd m4, [o(pw_2896_2896)]\n REPX {paddd x, m7}, m5, m0, m6, m4\n REPX {psrad x, 12}, m0, m6, m5, m4\n packssdw m0, m6 ;out8\n packssdw m5, m4 ;-out7\n mova [rsp+gprsize*2+16*10], m5\n mova m4, [rsp+gprsize*2+16* 2] ;out12\n mova m5, [rsp+gprsize*2+16*14] ;-out13\n mova m6, [rsp+gprsize*2+16*15] ;out14\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n mova m1, [rsp+gprsize*2+16* 9]\n mova m2, [rsp+gprsize*2+16*14]\n paddsw m0, m1, m2\n psubsw m1, m2\n pmulhrsw m0, m7 ;out6\n pmulhrsw m1, m7 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n psubsw m2, m3, m4\n paddsw m3, m4\n pmulhrsw m2, m7 ;out10\n pmulhrsw m3, m7 ;-out5\n mova [rsp+gprsize*2+16* 8], m3\n mova m3, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n paddsw m0, m3, m4\n psubsw m3, m4\n pmulhrsw m0, m7 ;out4\n pmulhrsw m3, m7 ;-out11\n mova [rsp+gprsize*2+16* 7], m0\n mova m0, [rsp+gprsize*2+16*10]\n paddsw m4, m0, [rsp+gprsize*2+16*11]\n psubsw m0, [rsp+gprsize*2+16*11]\n pmulhrsw m4, m7 ;-out7\n pmulhrsw m0, m7 ;out8\n mova [rsp+gprsize*2+16*10], m4\n mova m4, [rsp+gprsize*2+16*2 ] ;out12\n ret\n\nINV_TXFM_16X8_FN flipadst, dct\nINV_TXFM_16X8_FN flipadst, adst\nINV_TXFM_16X8_FN flipadst, flipadst\nINV_TXFM_16X8_FN flipadst, identity\n\ncglobal iflipadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x8_internal).pass1_end)]\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).pass2_main\n\n\nINV_TXFM_16X8_FN identity, dct, 15\nINV_TXFM_16X8_FN identity, adst\nINV_TXFM_16X8_FN identity, flipadst\nINV_TXFM_16X8_FN identity, identity\n\ncglobal iidentity_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*16\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x8_internal).pass1_end)]\n\n.pass1:\n mova m0, [o(pw_2896x8)]\n mova m2, [o(pw_1697x16)]\n mova m3, [o(pw_16384)]\n sub coeffq, 8*16\n REPX {pmulhrsw x, m0}, m4, m5, m6, m7\n pmulhrsw m1, m2, m4\n pmulhrsw m1, m3\n paddsw m1, m4 ; 1\n pmulhrsw m4, m2, m5\n pmulhrsw m4, m3\n paddsw m4, m5 ; 3\n pmulhrsw m5, m2, m6\n pmulhrsw m5, m3\n paddsw m5, m6 ; 5\n pmulhrsw m6, m2, m7\n pmulhrsw m6, m3\n paddsw m7, m6 ; 7\n pmulhrsw m6, m0, [coeffq+16*6]\n mova [rsp+gprsize+16*0], m4\n pmulhrsw m4, m2, m6\n pmulhrsw m4, m3\n paddsw m6, m4 ; 6\n pmulhrsw m4, m0, [coeffq+16*4]\n mova [rsp+gprsize+16*1], m6\n pmulhrsw m6, m2, m4\n pmulhrsw m6, m3\n paddsw m4, m6 ; 4\n pmulhrsw m6, m0, [coeffq+16*2]\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m2, m6\n pmulhrsw m2, m3\n paddsw m2, m6 ; 2\n pmulhrsw m6, m0, [o(pw_1697x16)]\n pmulhrsw m6, m3\n mova m3, [rsp+gprsize+16*0]\n paddsw m0, m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n mova [coeffq+16*1], m4\n mova [coeffq+16*3], m5\n mova [coeffq+16*5], m6\n mova [coeffq+16*7], m7\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mova [coeffq-16*7], m0\n mova [coeffq-16*5], m1\n mova [coeffq-16*3], m2\n mova [coeffq-16*1], m3\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea tx2q, [o(m(iidentity_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iidentity_8x8_internal).end\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iidentity_8x8_internal).end\n\n\n%macro INV_TXFM_16X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x16).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m2, m3, [coeffq+16*0]\n pmulhrsw m3, [coeffq+16*1]\n mova m0, [o(pw_8192)]\n mova m1, [o(pw_1697x16)]\n pshuflw m4, [o(deint_shuf)], q0000 ;pb_0_1\n punpcklwd m4, m4\n pcmpeqb m5, m5\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n paddb m5, m5 ;pb_m2\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n psrlw m0, 2 ;pw_2048\n pmulhrsw m7, m1, m2\n pmulhrsw m1, m3\n paddsw m2, m2\n paddsw m3, m3\n paddsw m2, m7\n paddsw m3, m1\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n mov r3d, 8\n.loop:\n mova m1, [dstq]\n pshufb m0, m2, m4\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq], m1\n mova m1, [dstq+strideq*8]\n pshufb m0, m3, m4\n psubb m4, m5 ; += 2\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq+strideq*8], m1\n add dstq, strideq\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_2896x8)]\n mova m6, [o(pw_2048)]\n xor eobd, eobd\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end)]\n lea r3, [dstq+8]\n mov [rsp+16*0], r3\n.main:\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n add coeffq, 32*4\n punpckldq m0, m1\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n psraw m1, 1\n pavgw m0, m1\n pmulhrsw m0, m5\n pmulhrsw m0, m6\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end1)]\n add coeffq, 32*4\n mov dstq, [rsp+16*0]\n jmp .main\n.end1:\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X16_FN dct, dct, 0\nINV_TXFM_16X16_FN dct, identity, 15\nINV_TXFM_16X16_FN dct, adst\nINV_TXFM_16X16_FN dct, flipadst\n\ncglobal idct_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_16x8_internal).main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(idct_16x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*4 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*12]\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n lea tx2q, [o(m(idct_8x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_main\n\n\n%macro ITX_16X16_ADST_LOAD_ODD_COEFS 0\n mova m0, [coeffq+16*1 ]\n mova m1, [coeffq+16*3 ]\n mova m2, [coeffq+16*29]\n mova m3, [coeffq+16*31]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*13]\n mova m1, [coeffq+16*15]\n mova m2, [coeffq+16*17]\n mova m3, [coeffq+16*19]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*5 ]\n mova m1, [coeffq+16*7 ]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*11]\n mova m4, [coeffq+16*21]\n mova m5, [coeffq+16*23]\n mova m6, [coeffq+16*25]\n mova m7, [coeffq+16*27]\n%endmacro\n\n%macro ITX_16X16_ADST_LOAD_EVEN_COEFS 0\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*2 ]\n mova m2, [coeffq+16*28]\n mova m3, [coeffq+16*30]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*12]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*16]\n mova m3, [coeffq+16*18]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m4, [coeffq+16*20]\n mova m5, [coeffq+16*22]\n mova m6, [coeffq+16*24]\n mova m7, [coeffq+16*26]\n%endmacro\n\nINV_TXFM_16X16_FN adst, dct\nINV_TXFM_16X16_FN adst, adst\nINV_TXFM_16X16_FN adst, flipadst\n\ncglobal iadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iadst_16x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_main\n\n\nINV_TXFM_16X16_FN flipadst, dct\nINV_TXFM_16X16_FN flipadst, adst\nINV_TXFM_16X16_FN flipadst, flipadst\n\ncglobal iflipadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*17, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS coeffq+16* 0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x16_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n\n lea tx2q, [o(m(iflipadst_16x16_internal).end2)]\n mov dstq, r3\n jmp m(iflipadst_8x16_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n\n%macro IDTX16B 3 ; src/dst, tmp, pw_1697x16\n pmulhrsw m%2, m%3, m%1\n psraw m%2, 1\n pavgw m%1, m%2\n%endmacro\n\nINV_TXFM_16X16_FN identity, dct, 15\nINV_TXFM_16X16_FN identity, identity\n\ncglobal iidentity_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*17\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end)]\n\n.pass1:\n mova m6, [o(pw_1697x16)]\n mova m7, [coeffq+32*6]\n mova m0, [coeffq+32*0]\n mova m1, [coeffq+32*1]\n mova m2, [coeffq+32*2]\n mova m3, [coeffq+32*3]\n mova m4, [coeffq+32*4]\n REPX {IDTX16B x, 5, 6}, 7, 0, 1, 2, 3, 4\n mova m5, [coeffq+32*5]\n mova [rsp+gprsize+16*1], m7\n IDTX16B 5, 7, 6\n mova m7, [coeffq+32*7]\n IDTX16B 7, 6, 6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end1)]\n jmp .pass1\n\n.pass1_end1:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 15*16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end2)]\n jmp .pass1\n\n.pass1_end2:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea r3, [dstq+8]\n lea tx2q, [o(m(iidentity_16x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m4\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 4, 7}, 5, 6, 0, 1, 2, 3\n mova m4, [o(pw_2048)]\n pmulhrsw m5, m4\n pmulhrsw m6, m4\n mova [rsp+gprsize+16*2], m5\n mova m5, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*1], m6\n IDTX16 5, 6, 7\n mova m6, [rsp+gprsize+16*0]\n IDTX16 6, 7, 7\n REPX {pmulhrsw x, m4}, m0, m1, m2, m3, m6\n pmulhrsw m4, m5\n mova [rsp+gprsize+16*0], m6\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end2)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n.end2:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n LOAD_8ROWS coeffq, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end3)]\n mov dstq, r3\n jmp .end\n\n.end3:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\ncglobal inv_txfm_add_dct_dct_8x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_8x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 2 ;pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x32).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n\n.end:\n RET\n\n\n\ncglobal idct_8x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n cmp eobd, 106\n jle .fast\n\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1:\n mova [rsp+gprsize+16*9 ], m0 ;in24\n mova [rsp+gprsize+16*10], m4 ;in28\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_1:\n mova [rsp+gprsize+16*7 ], m0 ;in16\n mova [rsp+gprsize+16*8 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n.fast:\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n mova [rsp+gprsize+16*5 ], m0 ;in8\n mova [rsp+gprsize+16*6 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n mova m1, m4 ;in4\n mova m2, [rsp+gprsize+16*5 ] ;in8\n mova m3, [rsp+gprsize+16*6 ] ;in12\n\n cmp eobd, 106\n jg .full\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n mova m0, [rsp+gprsize+16*11]\n mova m1, [rsp+gprsize+16*12]\n mova m2, [rsp+gprsize+16*13]\n mova m3, [rsp+gprsize+16*14]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call .main_fast\n jmp .pass2\n\n.full:\n mova m4, [rsp+gprsize+16*7 ] ;in16\n mova m5, [rsp+gprsize+16*8 ] ;in20\n mova m6, [rsp+gprsize+16*9 ] ;in24\n mova m7, [rsp+gprsize+16*10] ;in28\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n call .main\n\n.pass2:\n lea r3, [o(m(idct_8x32_internal).end6)]\n\n.end:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_8x32_internal).end2)]\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, \\\n 8, 9, 10, 11, 12, 13, 14, 15, \\\n 16, 17, 18, 19, 20, 21, 22, 23, \\\n 24, 25, 26, 27, 28, 29, 30, 31\n\n jmp tx2q\n\n.end2:\n lea tx2q, [o(m(idct_8x32_internal).end3)]\n jmp m(idct_8x8_internal).end\n\n.end3:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end4)]\n jmp m(idct_8x8_internal).end\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end5)]\n jmp m(idct_8x8_internal).end\n\n.end5:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n mov tx2q, r3\n jmp m(idct_8x8_internal).end\n\n.end6:\n ret\n\nALIGN function_align\n.main_veryfast:\n mova m0, [rsp+gprsize*2+16*19] ;in1\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t30,t31\n pmulhrsw m0, [o(pw_201x8)] ;t16,t17\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*34], m3 ;t31\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*20], m3 ;t17a\n mova [rsp+gprsize*2+16*33], m0 ;t30a\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m2, m1, [o(pw_3857x8)] ;t28,t29\n pmulhrsw m1, [o(pw_m1380x8)] ;t18,t19\n mova [rsp+gprsize*2+16*22], m1 ;t19\n mova [rsp+gprsize*2+16*31], m2 ;t28\n ITX_MULSUB_2W 2, 1, 0, 3, 7, m4017, 799 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*32], m1 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n pmulhrsw m3, m0, [o(pw_3973x8)] ;t26, t27\n pmulhrsw m0, [o(pw_995x8)] ;t20, t21\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*30], m3 ;t27\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m3 ;t21a\n mova [rsp+gprsize*2+16*29], m0 ;t26a\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pxor m0, m0\n mova m3, m0\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main_fast: ;bottom half is zero\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t31a\n pmulhrsw m0, [o(pw_201x8)] ;t16a\n pmulhrsw m2, m1, [o(pw_3035x8)] ;t30a\n pmulhrsw m1, [o(pw_m2751x8)] ;t17a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t17\n paddsw m0, m1 ;t16\n psubsw m5, m3, m2 ;t30\n paddsw m3, m2 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m3, m0, [o(pw_3703x8)]\n pmulhrsw m0, [o(pw_1751x8)]\n pmulhrsw m2, m1, [o(pw_3857x8)]\n pmulhrsw m1, [o(pw_m1380x8)]\n psubsw m4, m1, m0 ;t18\n paddsw m0, m1 ;t19\n psubsw m5, m2, m3 ;t29\n paddsw m3, m2 ;t28\n ITX_MULSUB_2W 5, 4, 1, 2, 7, m4017, 799 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m5 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m4 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n pmulhrsw m3, m0, [o(pw_3973x8)]\n pmulhrsw m0, [o(pw_995x8)]\n pmulhrsw m2, m1, [o(pw_3513x8)]\n pmulhrsw m1, [o(pw_m2106x8)]\n psubsw m4, m0, m1 ;t21\n paddsw m0, m1 ;t20\n psubsw m5, m3, m2 ;t26\n paddsw m3, m2 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pmulhrsw m3, m0, [o(pw_3290x8)]\n pmulhrsw m0, [o(pw_2440x8)]\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main:\n mova m7, [o(pd_2048)]\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n mova m2, [rsp+gprsize*2+16*33] ;in17\n mova m3, [rsp+gprsize*2+16*34] ;in31\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 201, 4091 ;t16a, t31a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3035, 2751 ;t17a, t30a\n psubsw m4, m0, m2 ;t17\n paddsw m0, m2 ;t16\n psubsw m5, m3, m1 ;t30\n paddsw m3, m1 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n mova m2, [rsp+gprsize*2+16*31] ;in25\n mova m3, [rsp+gprsize*2+16*32] ;in23\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 1751, 3703 ;t18a, t29a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3857, 1380 ;t19a, t28a\n psubsw m4, m2, m0 ;t18\n paddsw m0, m2 ;t19\n psubsw m5, m1, m3 ;t29\n paddsw m3, m1 ;t28\n ITX_MULSUB_2W 5, 4, 1, 2, 7, m4017, 799 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m5 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m4 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n mova m2, [rsp+gprsize*2+16*29] ;in21\n mova m3, [rsp+gprsize*2+16*30] ;in27\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 995, 3973 ;t20a, t27a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3513, 2106 ;t21a, t26a\n psubsw m4, m0, m2 ;t21\n paddsw m0, m2 ;t20\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m1, [rsp+gprsize*2+16*26] ;in3\n mova m2, [rsp+gprsize*2+16*27] ;in29\n mova m3, [rsp+gprsize*2+16*28] ;in19\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 2440, 3290 ;t22a, t25a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 4052, 601 ;t23a, t24a\n\n.main2:\n psubsw m4, m2, m0 ;t22\n paddsw m0, m2 ;t23\n psubsw m5, m1, m3 ;t25\n paddsw m3, m1 ;t24\n ITX_MULSUB_2W 5, 4, 1, 2, 7, m2276, 3406 ;t22a, t25a\n mova m2, [rsp+gprsize*2+16*24] ;t21a\n psubsw m1, m5, m2 ;t21\n paddsw m5, m2 ;t22\n mova [rsp+gprsize*2+16*25], m5 ;t22\n mova m2, [rsp+gprsize*2+16*29] ;t26a\n psubsw m5, m4, m2 ;t26\n paddsw m4, m2 ;t25\n mova [rsp+gprsize*2+16*28], m4 ;t25\n ITX_MULSUB_2W 5, 1, 2, 4, 7, m3784, 1567 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m1 ;t26a\n\n mova m1, [rsp+gprsize*2+16*23] ;t20\n mova m5, [rsp+gprsize*2+16*30] ;t27\n psubsw m2, m0, m1 ;t20a\n paddsw m0, m1 ;t23a\n psubsw m6, m3, m5 ;t27a\n paddsw m3, m5 ;t24a\n ITX_MULSUB_2W 6, 2, 1, 5, 7, m3784, 1567 ;t20, t27\n mova [rsp+gprsize*2+16*26], m0 ;t23a\n mova [rsp+gprsize*2+16*27], m3 ;t24a\n mova [rsp+gprsize*2+16*30], m2 ;t27\n\n mova m0, [rsp+gprsize*2+16*20] ;t17a\n mova m1, [rsp+gprsize*2+16*21] ;t18a\n mova m2, [rsp+gprsize*2+16*32] ;t29a\n mova m3, [rsp+gprsize*2+16*33] ;t30a\n psubsw m4, m0, m1 ;t18\n paddsw m0, m1 ;t17\n psubsw m5, m3, m2 ;t29\n paddsw m3, m2 ;t30\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t18a, t29a\n mova [rsp+gprsize*2+16*20], m0 ;t17\n mova [rsp+gprsize*2+16*21], m5 ;t18a\n mova [rsp+gprsize*2+16*32], m4 ;t29a\n mova [rsp+gprsize*2+16*33], m3 ;t30\n mova m0, [rsp+gprsize*2+16*19] ;t16\n mova m1, [rsp+gprsize*2+16*22] ;t19\n mova m2, [rsp+gprsize*2+16*31] ;t28\n mova m3, [rsp+gprsize*2+16*34] ;t31\n psubsw m4, m0, m1 ;t19a\n paddsw m0, m1 ;t16a\n psubsw m5, m3, m2 ;t28a\n paddsw m3, m2 ;t31a\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t19, t28\n mova m2, [rsp+gprsize*2+16*15] ;tmp12\n psubsw m1, m5, m6 ;t20a\n paddsw m5, m6 ;t19a\n psubsw m6, m2, m5 ;out19\n paddsw m2, m5 ;out12\n mova m5, [rsp+gprsize*2+16*30] ;t27\n mova [rsp+gprsize*2+16*22], m6 ;out19\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m6, m4, m5 ;t27a\n paddsw m4, m5 ;t28a\n ITX_MULSUB_2W 6, 1, 2, 5, 7, 2896, 2896 ;t20, t27\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp3\n psubsw m5, m2, m4 ;out28\n paddsw m2, m4 ;out3\n mova m4, [rsp+gprsize*2+16*14] ;tmp11\n mova [rsp+gprsize*2+16*31], m5 ;out28\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m5, m4, m6 ;out20\n paddsw m4, m6 ;out11\n mova m2, [rsp+gprsize*2+16*7 ] ;tmp4\n mova [rsp+gprsize*2+16*23], m5 ;out20\n mova [rsp+gprsize*2+16*14], m4 ;out11\n psubsw m5, m2, m1 ;out27\n paddsw m2, m1 ;out4\n mova m1, [rsp+gprsize*2+16*26] ;t23a\n mova m4, [rsp+gprsize*2+16*27] ;t24a\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*7 ], m2 ;out4\n psubsw m5, m0, m1 ;t23\n paddsw m0, m1 ;t16\n psubsw m2, m3, m4 ;t24\n paddsw m3, m4 ;t31\n ITX_MULSUB_2W 2, 5, 4, 6, 7, 2896, 2896 ;t23a, t24a\n mova m6, [rsp+gprsize*2+16*18] ;tmp15\n psubsw m4, m6, m0 ;out16\n paddsw m6, m0 ;out15\n mova m0, [rsp+gprsize*2+16*3 ] ;tmp0\n mova m1, [rsp+gprsize*2+16*11] ;tmp8\n mova [rsp+gprsize*2+16*18], m6 ;out15\n mova [rsp+gprsize*2+16*19], m4 ;out16\n psubsw m6, m0, m3 ;out31\n paddsw m0, m3 ;out0\n psubsw m4, m1, m2 ;out23\n paddsw m1, m2 ;out8\n mova m3, [rsp+gprsize*2+16*10] ;tmp7\n mova [rsp+gprsize*2+16*34], m6 ;out31\n mova [rsp+gprsize*2+16*11], m1 ;out8\n mova [rsp+gprsize*2+16*26], m4 ;out23\n paddsw m6, m3, m5 ;out7\n psubsw m3, m5 ;out24\n mova m1, [rsp+gprsize*2+16*20] ;t17\n mova m5, [rsp+gprsize*2+16*25] ;t22\n mova m2, [rsp+gprsize*2+16*17] ;tmp14\n mova [rsp+gprsize*2+16*27], m3 ;out24\n psubsw m4, m1, m5 ;t22a\n paddsw m1, m5 ;t17a\n psubsw m3, m2, m1 ;out17\n paddsw m2, m1 ;out14\n mova m5, [rsp+gprsize*2+16*28] ;t25\n mova m1, [rsp+gprsize*2+16*33] ;t30\n mova [rsp+gprsize*2+16*17], m2 ;out14\n mova [rsp+gprsize*2+16*20], m3 ;out17\n psubsw m2, m1, m5 ;t25a\n paddsw m1, m5 ;t30a\n ITX_MULSUB_2W 2, 4, 3, 5, 7, 2896, 2896 ;t22, t25\n mova m5, [rsp+gprsize*2+16*4 ] ;tmp1\n psubsw m3, m5, m1 ;out30\n paddsw m5, m1 ;out1\n mova m1, [rsp+gprsize*2+16*12] ;tmp9\n mova [rsp+gprsize*2+16*33], m3 ;out30\n mova [rsp+gprsize*2+16*4 ], m5 ;out1\n psubsw m3, m1, m2 ;out22\n paddsw m1, m2 ;out9\n mova m5, [rsp+gprsize*2+16*9 ] ;tmp6\n mova [rsp+gprsize*2+16*25], m3 ;out22\n mova [rsp+gprsize*2+16*12], m1 ;out9\n psubsw m3, m5, m4 ;out25\n paddsw m5, m4 ;out6\n mova m4, [rsp+gprsize*2+16*21] ;t18a\n mova m1, [rsp+gprsize*2+16*24] ;t21a\n mova m2, [rsp+gprsize*2+16*16] ;tmp13\n mova [rsp+gprsize*2+16*28], m3 ;out25\n mova [rsp+gprsize*2+16*9 ], m5 ;out6\n paddsw m3, m4, m1 ;t18\n psubsw m4, m1 ;t21\n psubsw m5, m2, m3 ;out18\n paddsw m2, m3 ;out13\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n mova m3, [rsp+gprsize*2+16*32] ;t29a\n mova [rsp+gprsize*2+16*21], m5 ;out18\n mova [rsp+gprsize*2+16*16], m2 ;out13\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t29\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 2896, 2896 ;t21a, t26a\n mova m2, [rsp+gprsize*2+16*5 ] ;tmp2\n psubsw m1, m2, m3 ;out29\n paddsw m2, m3 ;out2\n mova m3, [rsp+gprsize*2+16*13] ;tmp10\n mova [rsp+gprsize*2+16*32], m1 ;out29\n psubsw m7, m3, m5 ;out21\n paddsw m3, m5 ;out10\n mova m5, [rsp+gprsize*2+16*8 ] ;tmp5\n mova [rsp+gprsize*2+16*24], m7 ;out21\n mova [rsp+gprsize*2+16*13], m3 ;out10\n psubsw m1, m5, m4 ;out26\n paddsw m5, m4 ;out5\n mova m7, m6 ;out7\n mova m3, [rsp+gprsize*2+16*6 ] ;out3\n mova m4, [rsp+gprsize*2+16*7 ] ;out4\n mova [rsp+gprsize*2+16*29], m1 ;out26\n mova m6, [rsp+gprsize*2+16*9 ] ;out6\n mova m1, [rsp+gprsize*2+16*4 ] ;out1\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x8, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_32x8_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\ncglobal idct_32x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*1, 32\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n cmp eobd, 106\n jg .full\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n LOAD_8ROWS coeffq+16*17, 32\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass2:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x8_internal).end)]\n jmp m(idct_8x32_internal).end1\n\n.end:\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end1:\n lea r3, [dstq+8]\n lea tx2q, [o(m(idct_32x8_internal).end2)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end3:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end4)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end5:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end6)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end6:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end7:\n mov dstq, r3\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end8:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_8x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n.loop:\n LOAD_8ROWS coeffq+16*0, 64\n paddsw m6, [o(pw_5)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_5)]\n REPX {paddsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n call m(idct_8x8_internal).pass1_end3\n REPX {psraw x, 3 }, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16\n dec r3d\n jg .loop\n RET\n\ncglobal inv_txfm_add_identity_identity_32x8, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n.loop:\n LOAD_8ROWS coeffq+16*0, 16\n pmulhrsw m6, [o(pw_4096)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_4096)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n call m(idct_8x8_internal).pass1_end3\n\n mov [rsp+16*3], dstq\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n call m(idct_8x8_internal).end3\n\n add coeffq, 16*8\n mov dstq, [rsp+16*3]\n lea dstq, [dstq+8]\n dec r3d\n jg .loop\n jnc .loop\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_16x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x32).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\ncglobal idct_16x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n LOAD_8ROWS coeffq+16*1, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*5, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*33, 64 ;in8~in15\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n mova [coeffq+16*1 ], m0 ;in8\n mova [coeffq+16*5 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*32, 64 ;in0~in7\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n\n cmp eobd, 150\n jg .full\n\n mova m1, m4 ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [rsp+gprsize+16*11] ;in2\n mova m1, [rsp+gprsize+16*12] ;in6\n mova m2, [rsp+gprsize+16*13] ;in10\n mova m3, [rsp+gprsize+16*14] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n mova [coeffq+16*0 ], m0 ;in0\n mova [coeffq+16*4 ], m4 ;in4\n\n LOAD_8ROWS coeffq+16*2, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*6, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*34, 64 ;in16~in23\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n mova [coeffq+16*2 ], m0 ;in16\n mova [coeffq+16*6 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n LOAD_8ROWS coeffq+16*3, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*7, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS coeffq+16*35, 64 ;in24~in31\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n mova m6, m0 ;in24\n mova m7, m4 ;in28\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*4 ] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*6 ] ;in20\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main\n\n.pass2:\n mov [rsp+gprsize*1+16*35], eobd\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n lea r3, [o(m(idct_16x32_internal).end)]\n jmp m(idct_8x32_internal).end\n\n.end:\n mov dstq, [rsp+gprsize*2+16*35]\n mov eobd, [rsp+gprsize*1+16*35]\n add coeffq, 16*32\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*16] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*17] ;in12\n\n cmp eobd, 150\n jg .full1\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .end1\n\n.full1:\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*18] ;in20\n mova m6, [coeffq+16*3 ] ;in24\n mova m7, [coeffq+16*19] ;in26\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n mova m4, [coeffq+16*10] ;in18\n mova m5, [coeffq+16*26] ;in22\n mova m6, [coeffq+16*11] ;in26\n mova m7, [coeffq+16*27] ;in30\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n\n.end1:\n jmp m(idct_8x32_internal).pass2\n\n\n\ncglobal inv_txfm_add_dct_dct_32x16, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x16_internal)\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*11, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*19, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*27, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n add coeffq, 16\n lea r3, [o(m(idct_32x16_internal).pass1_end1)]\n.pass1:\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*2, 64, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n LOAD_8ROWS coeffq+16*34, 64, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass1_end:\n mova [rsp+gprsize+16*0 ], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+16*32, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*48, 32\n\n sub coeffq, 16\n lea r3, [o(m(idct_32x16_internal).end)]\n jmp .pass1\n\n.end:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_16x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 1\n mov r5, 2\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 278 ;if (eob > 278)\n cmovg r4, r5 ; iteration_count++\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n mov [rsp+gprsize+16*3], r4\n mov [rsp+gprsize*2+16*3], coeffq\n\n.loop:\n LOAD_8ROWS coeffq, 64, 1\n mova [rsp+16*1], m6\n pxor m6, m6\n REPX {mova [coeffq+64*x], m6}, 0, 1, 2, 3, 4, 5, 6, 7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*0], m2\n mova [rsp+16*1], m3\n mova [rsp+16*2], m4\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_16384)]\n REPX {IDTX16 x, 2, 3, 4}, 5, 6, 7, 0, 1\n mova m2, [o(pw_8192)]\n REPX {pmulhrsw x, m2}, m5, m6, m7, m0, m1\n mova m2, [rsp+16*0]\n mova [rsp+16*0], m7\n IDTX16 2, 7, 3, 4\n mova m7, [rsp+16*2]\n mova [rsp+16*2], m5\n IDTX16 7, 5, 3, 4\n mova m5, [rsp+16*1]\n mova [rsp+16*1], m6\n pmulhrsw m3, m5\n pmulhrsw m3, m4\n psrlw m4, 1 ; pw_8192\n paddsw m3, m5\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n pmulhrsw m4, m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n add coeffq, 16\n dec r3\n jg .loop\n mov coeffq, [rsp+gprsize*2+16*3]\n add coeffq, 64*8\n mov r3, [rsp+gprsize+16*3]\n xor dstq, dstq\n mov [rsp+gprsize+16*3], dstq\n mov dstq, [rsp+16*3]\n test r3, r3\n jnz .loop\n RET\n\n\ncglobal inv_txfm_add_identity_identity_32x16, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 12 ;0100b\n mov r5, 136 ;1000 1000b\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count+2\n mov r5, 34952 ;1000 1000 1000 1000b\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count += 4\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 32, 1\n REPX {paddsw x, x}, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*1], m5\n mova [rsp+16*2], m6\n mova m6, [o(pw_1697x16)]\n REPX {IDTX16 x, 5, 6}, 7, 0, 1, 2, 3, 4\n pmulhrsw m7, [o(pw_2048)]\n mova m5, [rsp+16*1]\n mova [rsp+16*0], m7\n IDTX16 5, 7, 6\n mova m7, [rsp+16*2]\n IDTX16 7, 6, 6\n mova m6, [o(pw_2048)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n mova [rsp+16*2], m5\n mova [rsp+16*1], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n pxor m7, m7\n REPX {mova [coeffq+32*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n.loop_end:\n add coeffq, 16\n shr r3, 2\n test r3, r3\n jz .ret\n test r3, 2\n jnz .loop\n mov r4, r3\n and r4, 1\n shl r4, 3\n add coeffq, r4\n add coeffq, 32*7\n mov dstq, [rsp+16*3]\n lea r4, [dstq+8]\n mov [rsp+16*3], r4\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_32x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*35], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*35], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*35]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n mova m0, [coeffq+256*0]\n mova m1, [coeffq+256*1]\n mova m2, [coeffq+256*2]\n mova m3, [coeffq+256*3]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+128*1]\n mova m1, [coeffq+128*3]\n mova m2, [coeffq+128*5]\n mova m3, [coeffq+128*7]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*35]\n mov r3, 4\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*35], r3\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*12]\n mova m2, [coeffq+16*20]\n mova m3, [coeffq+16*28]\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*13]\n mova m6, [coeffq+16*21]\n mova m7, [coeffq+16*29]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov eobd, [rsp+gprsize*1+16*35]\n test eobd, eobd\n jl .fast1\n\n.full1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n mova m4, [coeffq+16*2 ]\n mova m5, [coeffq+16*18]\n mova m6, [coeffq+16*3 ]\n mova m7, [coeffq+16*19]\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*22]\n mova m3, [coeffq+16*30]\n mova m4, [coeffq+16*7 ]\n mova m5, [coeffq+16*15]\n mova m6, [coeffq+16*23]\n mova m7, [coeffq+16*31]\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp tx2q\n\n.fast1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp tx2q\n\n.pass2_end:\n lea r3, [o(m(idct_32x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end\n\n.pass2_end1:\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg .pass2_loop\n\n ret\n\n\ncglobal inv_txfm_add_identity_identity_32x32, 4, 6, 8, 16*5, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 2\n mov r5, 4\n cmp eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n lea r3, [dstq+8]\n mov [rsp+gprsize*0+16*3], r3\n mov [rsp+gprsize*1+16*3], r4\n mov [rsp+gprsize*2+16*3], r4\n mov [rsp+gprsize*3+16*3], coeffq\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 64\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n pmulhrsw m7, [o(pw_8192)]\n mova [rsp+16*0], m7\n mova m7, [o(pw_8192)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+16*1], m6\n mova [rsp+16*2], m5\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n add coeffq, 16\n dec r3\n jg .loop\n\n mov r4, [rsp+gprsize*2+16*3]\n dec r4\n jle .ret\n\n mov dstq, [rsp+gprsize*0+16*3]\n mov coeffq, [rsp+gprsize*3+16*3]\n mov [rsp+gprsize*2+16*3], r4\n lea r3, [dstq+8]\n add coeffq, 64*8\n mov [rsp+gprsize*0+16*3], r3\n mov r3, [rsp+gprsize*1+16*3]\n mov [rsp+gprsize*3+16*3], coeffq\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_16x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x64).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\n\ncglobal idct_16x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 151\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*0, 64*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*1, 64*2\n call m(idct_16x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 2\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*67], r3\n mov eobd, [rsp+gprsize*1+16*67]\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n pxor m4, m4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n\n test eobd, eobd\n jl .fast\n\n.full:\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n mova m2, [coeffq+16*18]\n mova m3, [coeffq+16*19]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call .main\n jmp .end\n\n.fast:\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n\n call m(idct_8x32_internal).main_veryfast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n call .main_fast\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, r4\n jmp m(idct_8x32_internal).end2\n\n.end1:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n lea r3, [o(m(idct_16x64_internal).end2)]\n jmp m(idct_8x32_internal).end\n\n.end2:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n dec r3\n jg .pass2_loop\n ret\n\n\nALIGN function_align\n.main_fast:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t62,t63\n pmulhrsw m0, [o(pw_101x8)] ;t32,t33\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*66], m3 ;t63\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*36], m3 ;t33a\n mova [rsp+gprsize*2+16*65], m0 ;t62a\n\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60,t61\n pmulhrsw m1, [o(pw_m1474x8)] ;t34,t35\n mova [rsp+gprsize*2+16*38], m1 ;t35\n mova [rsp+gprsize*2+16*63], m2 ;t60\n ITX_MULSUB_2W 2, 1, 0, 3, 7, m4076, 401 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m2 ;t34a\n mova [rsp+gprsize*2+16*64], m1 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t58,t59\n pmulhrsw m0, [o(pw_897x8)] ;t36,t37\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*62], m3 ;t59\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56,t57\n pmulhrsw m1, [o(pw_m700x8)] ;t38,t39\n mova [rsp+gprsize*2+16*42], m1 ;t39\n mova [rsp+gprsize*2+16*59], m2 ;t56\n ITX_MULSUB_2W 2, 1, 0, 3, 7, m2598, 3166 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m2 ;t38a\n mova [rsp+gprsize*2+16*60], m1 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t54,t55\n pmulhrsw m0, [o(pw_501x8)] ;t40,t41\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*58], m3 ;t55\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*44], m3 ;t41a\n mova [rsp+gprsize*2+16*57], m0 ;t54a\n\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52,t53\n pmulhrsw m1, [o(pw_m1092x8)] ;t42,t43\n mova [rsp+gprsize*2+16*46], m1 ;t43\n mova [rsp+gprsize*2+16*55], m2 ;t52\n ITX_MULSUB_2W 2, 1, 0, 3, 7, m3612, 1931 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m2 ;t42a\n mova [rsp+gprsize*2+16*56], m1 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t50,t51\n pmulhrsw m0, [o(pw_1285x8)] ;t44,t45\n mova m6, m0\n mova [rsp+gprsize*2+16*54], m3 ;t51\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m3 ;t45a\n mova [rsp+gprsize*2+16*53], m0 ;t50a\n\n mova m0, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_4085x8)] ;t48,t49\n pmulhrsw m0, [o(pw_m301x8)] ;t46,t47\n mova m4, m3\n mova m5, m0\n\n jmp .main2\n\nALIGN function_align\n.main:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n mova m1, [rsp+gprsize*2+16*65] ;in31\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t63a\n pmulhrsw m0, [o(pw_101x8)] ;t32a\n pmulhrsw m2, m1, [o(pw_2967x8)] ;t62a\n pmulhrsw m1, [o(pw_m2824x8)] ;t33a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t33\n paddsw m0, m1 ;t32\n psubsw m5, m3, m2 ;t62\n paddsw m3, m2 ;t63\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*36], m5 ;t33a\n mova [rsp+gprsize*2+16*65], m4 ;t62a\n mova [rsp+gprsize*2+16*66], m3 ;t63\n\n mova m0, [rsp+gprsize*2+16*63] ;in17\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m3, m0, [o(pw_3745x8)] ;t61a\n pmulhrsw m0, [o(pw_1660x8)] ;t34a\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60a\n pmulhrsw m1, [o(pw_m1474x8)] ;t35a\n psubsw m4, m1, m0 ;t34\n paddsw m0, m1 ;t35\n psubsw m5, m2, m3 ;t61\n paddsw m3, m2 ;t60\n ITX_MULSUB_2W 5, 4, 1, 2, 7, m4076, 401 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m5 ;t34a\n mova [rsp+gprsize*2+16*38], m0 ;t35\n mova [rsp+gprsize*2+16*63], m3 ;t60\n mova [rsp+gprsize*2+16*64], m4 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n mova m1, [rsp+gprsize*2+16*61] ;in23\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t59a\n pmulhrsw m0, [o(pw_897x8)] ;t36a\n pmulhrsw m2, m1, [o(pw_3461x8)] ;t58a\n pmulhrsw m1, [o(pw_m2191x8)] ;t37a\n psubsw m4, m0, m1 ;t37\n paddsw m0, m1 ;t36\n psubsw m5, m3, m2 ;t58\n paddsw m3, m2 ;t59\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*40], m5 ;t37a\n mova [rsp+gprsize*2+16*61], m4 ;t58a\n mova [rsp+gprsize*2+16*62], m3 ;t59\n\n mova m0, [rsp+gprsize*2+16*59] ;in25\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m3, m0, [o(pw_3349x8)] ;t57a\n pmulhrsw m0, [o(pw_2359x8)] ;t38a\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56a\n pmulhrsw m1, [o(pw_m700x8)] ;t39a\n psubsw m4, m1, m0 ;t38\n paddsw m0, m1 ;t39\n psubsw m5, m2, m3 ;t57\n paddsw m3, m2 ;t56\n ITX_MULSUB_2W 5, 4, 1, 2, 7, m2598, 3166 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m5 ;t38a\n mova [rsp+gprsize*2+16*42], m0 ;t39\n mova [rsp+gprsize*2+16*59], m3 ;t56\n mova [rsp+gprsize*2+16*60], m4 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n mova m1, [rsp+gprsize*2+16*57] ;in27\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t55a\n pmulhrsw m0, [o(pw_501x8)] ;t40a\n pmulhrsw m2, m1, [o(pw_3229x8)] ;t54a\n pmulhrsw m1, [o(pw_m2520x8)] ;t41a\n psubsw m4, m0, m1 ;t41\n paddsw m0, m1 ;t40\n psubsw m5, m3, m2 ;t54\n paddsw m3, m2 ;t55\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*44], m5 ;t41a\n mova [rsp+gprsize*2+16*57], m4 ;t54a\n mova [rsp+gprsize*2+16*58], m3 ;t55\n\n mova m0, [rsp+gprsize*2+16*55] ;in21\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m3, m0, [o(pw_3564x8)] ;t53a\n pmulhrsw m0, [o(pw_2019x8)] ;t42a\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52a\n pmulhrsw m1, [o(pw_m1092x8)] ;t43a\n psubsw m4, m1, m0 ;t42\n paddsw m0, m1 ;t43\n psubsw m5, m2, m3 ;t53\n paddsw m3, m2 ;t52\n ITX_MULSUB_2W 5, 4, 1, 2, 7, m3612, 1931 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m5 ;t42a\n mova [rsp+gprsize*2+16*46], m0 ;t43\n mova [rsp+gprsize*2+16*55], m3 ;t52\n mova [rsp+gprsize*2+16*56], m4 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n mova m1, [rsp+gprsize*2+16*53] ;in19\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t51a\n pmulhrsw m0, [o(pw_1285x8)] ;t44a\n pmulhrsw m2, m1, [o(pw_3659x8)] ;t50a\n pmulhrsw m1, [o(pw_m1842x8)] ;t45a\n psubsw m4, m0, m1 ;t45\n paddsw m0, m1 ;t44\n psubsw m5, m3, m2 ;t50\n paddsw m3, m2 ;t51\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova m6, m0\n mova [rsp+gprsize*2+16*48], m5 ;t45a\n mova [rsp+gprsize*2+16*53], m4 ;t50a\n mova [rsp+gprsize*2+16*54], m3 ;t51\n\n mova m0, [rsp+gprsize*2+16*51] ;in29\n mova m1, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_3102x8)] ;t49a\n pmulhrsw m0, [o(pw_2675x8)] ;t46a\n pmulhrsw m2, m1, [o(pw_4085x8)] ;t48a\n pmulhrsw m1, [o(pw_m301x8)] ;t47a\n psubsw m5, m1, m0 ;t46\n paddsw m0, m1 ;t47\n psubsw m4, m2, m3 ;t49\n paddsw m3, m2 ;t48\n\nALIGN function_align\n.main2:\n ITX_MULSUB_2W 4, 5, 1, 2, 7, m1189, 3920 ;t46a, t49a\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m2, m0, m6 ;t44a\n paddsw m0, m6 ;t47a\n psubsw m6, m3, m1 ;t51a\n paddsw m3, m1 ;t48a\n mova [rsp+gprsize*2+16*50], m0 ;t47a\n mova [rsp+gprsize*2+16*51], m3 ;t48a\n ITX_MULSUB_2W 6, 2, 0, 3, 7, m2276, 3406 ;t44, t51\n mova [rsp+gprsize*2+16*47], m6 ;t44\n mova [rsp+gprsize*2+16*54], m2 ;t51\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m3, [rsp+gprsize*2+16*53] ;t50a\n psubsw m2, m4, m0 ;t45\n paddsw m4, m0 ;t46\n psubsw m6, m5, m3 ;t50\n paddsw m5, m3 ;t49\n ITX_MULSUB_2W 6, 2, 0, 3, 7, m2276, 3406 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m6 ;t45a\n mova [rsp+gprsize*2+16*49], m4 ;t46\n mova [rsp+gprsize*2+16*52], m5 ;t49\n mova [rsp+gprsize*2+16*53], m2 ;t50a\n\n mova m0, [rsp+gprsize*2+16*43] ;t40\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m3, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*58] ;t55\n psubsw m4, m0, m2 ;t43a\n paddsw m0, m2 ;t40a\n psubsw m5, m1, m3 ;t52a\n paddsw m1, m3 ;t55a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t43, t52\n mova [rsp+gprsize*2+16*43], m0 ;t40a\n mova [rsp+gprsize*2+16*46], m5 ;t43\n mova [rsp+gprsize*2+16*55], m4 ;t52\n mova [rsp+gprsize*2+16*58], m1 ;t55a\n\n mova m0, [rsp+gprsize*2+16*44] ;t41a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*57] ;t54a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t41\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t54\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t42a, t53a\n mova [rsp+gprsize*2+16*44], m0 ;t41\n mova [rsp+gprsize*2+16*45], m5 ;t42a\n mova [rsp+gprsize*2+16*56], m4 ;t53a\n mova [rsp+gprsize*2+16*57], m1 ;t54\n\n mova m0, [rsp+gprsize*2+16*41] ;t38a\n mova m2, [rsp+gprsize*2+16*40] ;t37a\n mova m3, [rsp+gprsize*2+16*61] ;t58a\n mova m1, [rsp+gprsize*2+16*60] ;t57a\n psubsw m4, m0, m2 ;t37\n paddsw m0, m2 ;t38\n psubsw m5, m1, m3 ;t58\n paddsw m1, m3 ;t57\n ITX_MULSUB_2W 5, 4, 2, 3, 7, m4017, 799 ;t37a, t58a\n mova [rsp+gprsize*2+16*41], m0 ;t38\n mova [rsp+gprsize*2+16*40], m5 ;t37a\n mova [rsp+gprsize*2+16*61], m4 ;t58a\n mova [rsp+gprsize*2+16*60], m1 ;t57\n\n mova m0, [rsp+gprsize*2+16*42] ;t39\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*59] ;t56\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t39a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t56a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, m4017, 799 ;t36, t59\n mova [rsp+gprsize*2+16*42], m0 ;t39a\n mova [rsp+gprsize*2+16*39], m5 ;t36\n mova [rsp+gprsize*2+16*62], m4 ;t59\n mova [rsp+gprsize*2+16*59], m1 ;t56a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m2, [rsp+gprsize*2+16*38] ;t35\n mova m3, [rsp+gprsize*2+16*63] ;t60\n mova m1, [rsp+gprsize*2+16*66] ;t63\n psubsw m4, m0, m2 ;t35a\n paddsw m0, m2 ;t32a\n psubsw m5, m1, m3 ;t60a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t35, t60\n mova [rsp+gprsize*2+16*35], m0 ;t32a\n mova [rsp+gprsize*2+16*38], m5 ;t35\n mova [rsp+gprsize*2+16*63], m4 ;t60\n mova [rsp+gprsize*2+16*66], m1 ;t63a\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m2, [rsp+gprsize*2+16*37] ;t34a\n mova m3, [rsp+gprsize*2+16*64] ;t61a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n psubsw m4, m0, m2 ;t34\n paddsw m0, m2 ;t33\n psubsw m5, m1, m3 ;t61\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t34a, t61a\n\n mova m2, [rsp+gprsize*2+16*41] ;t38\n mova m3, [rsp+gprsize*2+16*60] ;t57\n psubsw m6, m0, m2 ;t38a\n paddsw m0, m2 ;t33a\n psubsw m2, m1, m3 ;t57a\n paddsw m1, m3 ;t62a\n mova [rsp+gprsize*2+16*36], m0 ;t33a\n mova [rsp+gprsize*2+16*65], m1 ;t62a\n ITX_MULSUB_2W 2, 6, 0, 3, 7, 1567, 3784 ;t38, t57\n mova [rsp+gprsize*2+16*41], m2 ;t38\n mova [rsp+gprsize*2+16*60], m6 ;t57\n\n mova m2, [rsp+gprsize*2+16*40] ;t37\n mova m3, [rsp+gprsize*2+16*61] ;t58\n psubsw m0, m5, m2 ;t37\n paddsw m5, m2 ;t34\n psubsw m1, m4, m3 ;t58\n paddsw m4, m3 ;t61\n ITX_MULSUB_2W 1, 0, 2, 3, 7, 1567, 3784 ;t37a, t58a\n mova [rsp+gprsize*2+16*37], m5 ;t34\n mova [rsp+gprsize*2+16*64], m4 ;t61\n mova [rsp+gprsize*2+16*40], m1 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m0, [rsp+gprsize*2+16*38] ;t35\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*63] ;t60\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t35a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t60a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t36, t59\n mova [rsp+gprsize*2+16*38], m0 ;t35a\n mova [rsp+gprsize*2+16*39], m5 ;t36\n mova [rsp+gprsize*2+16*62], m4 ;t59\n mova [rsp+gprsize*2+16*63], m1 ;t60a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32a\n mova m2, [rsp+gprsize*2+16*42] ;t39a\n mova m3, [rsp+gprsize*2+16*59] ;t56a\n mova m1, [rsp+gprsize*2+16*66] ;t63a\n psubsw m4, m0, m2 ;t39\n paddsw m0, m2 ;t32\n psubsw m5, m1, m3 ;t56\n paddsw m1, m3 ;t63\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t39a, t56a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*42], m5 ;t39a\n mova [rsp+gprsize*2+16*59], m4 ;t56a\n mova [rsp+gprsize*2+16*66], m1 ;t63\n\n mova m0, [rsp+gprsize*2+16*50] ;t47a\n mova m2, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*51] ;t48a\n psubsw m4, m0, m2 ;t40\n paddsw m0, m2 ;t47\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t48\n ITX_MULSUB_2W 5, 4, 2, 3, 7, m3784, 1567 ;t40a, t55a\n mova [rsp+gprsize*2+16*50], m0 ;t47\n mova [rsp+gprsize*2+16*43], m5 ;t40a\n mova [rsp+gprsize*2+16*58], m4 ;t55a\n mova [rsp+gprsize*2+16*51], m1 ;t48\n\n mova m0, [rsp+gprsize*2+16*49] ;t46\n mova m2, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*52] ;t49\n psubsw m4, m0, m2 ;t41a\n paddsw m0, m2 ;t46a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t49a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, m3784, 1567 ;t41, t54\n mova [rsp+gprsize*2+16*49], m0 ;t46a\n mova [rsp+gprsize*2+16*44], m5 ;t41\n mova [rsp+gprsize*2+16*57], m4 ;t54\n mova [rsp+gprsize*2+16*52], m1 ;t49a\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*53] ;t50a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t45\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t50\n ITX_MULSUB_2W 5, 4, 2, 3, 7, m3784, 1567 ;t42a, t53a\n mova [rsp+gprsize*2+16*48], m0 ;t45\n mova [rsp+gprsize*2+16*45], m5 ;t42a\n mova [rsp+gprsize*2+16*56], m4 ;t53a\n mova [rsp+gprsize*2+16*53], m1 ;t50\n\n mova m0, [rsp+gprsize*2+16*47] ;t44\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m3, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m4, m0, m2 ;t43a\n paddsw m0, m2 ;t44a\n psubsw m5, m1, m3 ;t52a\n paddsw m1, m3 ;t51a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, m3784, 1567 ;t43, t52\n\n mova m2, [rsp+gprsize*2+16*38] ;t35a\n mova m3, [rsp+gprsize*2+16*31] ;tmp[28]\n psubsw m6, m2, m0 ;t44\n paddsw m2, m0 ;t35\n psubsw m0, m3, m2 ;out35\n paddsw m2, m3 ;out28\n mova m3, [rsp+gprsize*2+16*63] ;t60a\n mova [rsp+gprsize*2+16*38], m0 ;out35\n mova [rsp+gprsize*2+16*31], m2 ;out28\n psubsw m0, m3, m1 ;t51\n paddsw m3, m1 ;t60\n ITX_MULSUB_2W 0, 6, 1, 2, 7, 2896, 2896 ;t44a, t51a\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp[3]\n psubsw m1, m2, m3 ;out60\n paddsw m2, m3 ;out3\n mova m3, [rsp+gprsize*2+16*22] ;tmp[19]\n mova [rsp+gprsize*2+16*63], m1 ;out60\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m1, m3, m0 ;out44\n paddsw m3, m0 ;out19\n mova m2, [rsp+gprsize*2+16*15] ;tmp[12]\n\n mova m0, [rsp+gprsize*2+16*39] ;t36\n mova [rsp+gprsize*2+16*47], m1 ;out44\n mova [rsp+gprsize*2+16*22], m3 ;out19\n mova m1, [rsp+gprsize*2+16*62] ;t59\n psubsw m3, m2, m6 ;out51\n paddsw m2, m6 ;out12\n mova [rsp+gprsize*2+16*54], m3 ;out51\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m2, m0, m5 ;t43a\n paddsw m0, m5 ;t36a\n mova m5, [rsp+gprsize*2+16*30] ;tmp[27]\n psubsw m3, m1, m4 ;t52a\n paddsw m1, m4 ;t59a\n ITX_MULSUB_2W 3, 2, 4, 6, 7, 2896, 2896 ;t43, t52\n mova m4, [rsp+gprsize*2+16*7 ] ;tmp[4 ]\n psubsw m6, m5, m0 ;out36\n paddsw m5, m0 ;out27\n psubsw m0, m4, m1 ;out59\n paddsw m4, m1 ;out4\n mova [rsp+gprsize*2+16*39], m6 ;out36\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*62], m0 ;out59\n mova [rsp+gprsize*2+16*7 ], m4 ;out4\n mova m0, [rsp+gprsize*2+16*23] ;tmp[20]\n mova m5, [rsp+gprsize*2+16*14] ;tmp[11]\n psubsw m4, m0, m3 ;out43\n paddsw m0, m3 ;out20\n psubsw m6, m5, m2 ;out52\n paddsw m5, m2 ;out11\n mova [rsp+gprsize*2+16*46], m4 ;out43\n mova [rsp+gprsize*2+16*23], m0 ;out20\n mova [rsp+gprsize*2+16*55], m6 ;out52\n mova [rsp+gprsize*2+16*14], m5 ;out11\n\n mova m0, [rsp+gprsize*2+16*40] ;t37a\n mova m5, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*61] ;t58a\n mova m2, [rsp+gprsize*2+16*29] ;tmp[26]\n psubsw m4, m0, m5 ;t42\n paddsw m0, m5 ;t37\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t58\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t43, t52\n mova m3, [rsp+gprsize*2+16*8 ] ;tmp[5 ]\n psubsw m6, m2, m0 ;out37\n paddsw m2, m0 ;out26\n psubsw m0, m3, m1 ;out58\n paddsw m3, m1 ;out5\n mova [rsp+gprsize*2+16*40], m6 ;out37\n mova [rsp+gprsize*2+16*29], m2 ;out26\n mova [rsp+gprsize*2+16*61], m0 ;out58\n mova [rsp+gprsize*2+16*8 ], m3 ;out5\n mova m0, [rsp+gprsize*2+16*24] ;tmp[21]\n mova m1, [rsp+gprsize*2+16*13] ;tmp[10]\n psubsw m2, m0, m5 ;out42\n paddsw m0, m5 ;out21\n psubsw m3, m1, m4 ;out53\n paddsw m1, m4 ;out10\n mova [rsp+gprsize*2+16*45], m2 ;out42\n mova [rsp+gprsize*2+16*24], m0 ;out21\n mova [rsp+gprsize*2+16*56], m3 ;out53\n mova [rsp+gprsize*2+16*13], m1 ;out10\n\n mova m0, [rsp+gprsize*2+16*41] ;t38\n mova m5, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*60] ;t57\n mova m2, [rsp+gprsize*2+16*28] ;tmp[25]\n psubsw m4, m0, m5 ;t41a\n paddsw m0, m5 ;t38a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t57a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t41a, t54a\n mova m3, [rsp+gprsize*2+16*9 ] ;tmp[6 ]\n psubsw m6, m2, m0 ;out38\n paddsw m2, m0 ;out25\n psubsw m0, m3, m1 ;out57\n paddsw m3, m1 ;out6\n mova [rsp+gprsize*2+16*41], m6 ;out38\n mova [rsp+gprsize*2+16*28], m2 ;out25\n mova [rsp+gprsize*2+16*60], m0 ;out57\n mova [rsp+gprsize*2+16*9 ], m3 ;out6\n mova m0, [rsp+gprsize*2+16*25] ;tmp[22]\n mova m1, [rsp+gprsize*2+16*12] ;tmp[9 ]\n psubsw m2, m0, m5 ;out41\n paddsw m0, m5 ;out22\n psubsw m3, m1, m4 ;out54\n paddsw m1, m4 ;out9\n mova [rsp+gprsize*2+16*44], m2 ;out41\n mova [rsp+gprsize*2+16*25], m0 ;out22\n mova [rsp+gprsize*2+16*57], m3 ;out54\n mova [rsp+gprsize*2+16*12], m1 ;out9\n\n mova m0, [rsp+gprsize*2+16*42] ;t39a\n mova m5, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*59] ;t56a\n mova m2, [rsp+gprsize*2+16*27] ;tmp[24]\n psubsw m4, m0, m5 ;t40\n paddsw m0, m5 ;t39\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t56\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t40a, t55a\n mova m3, [rsp+gprsize*2+16*10] ;tmp[7 ]\n psubsw m6, m2, m0 ;out39\n paddsw m2, m0 ;out24\n psubsw m0, m3, m1 ;out56\n paddsw m3, m1 ;out7\n mova [rsp+gprsize*2+16*42], m6 ;out39\n mova [rsp+gprsize*2+16*27], m2 ;out24\n mova [rsp+gprsize*2+16*59], m0 ;out56\n mova [rsp+gprsize*2+16*10], m3 ;out7\n mova m0, [rsp+gprsize*2+16*26] ;tmp[23]\n mova m1, [rsp+gprsize*2+16*11] ;tmp[8 ]\n psubsw m2, m0, m5 ;out40\n paddsw m0, m5 ;out23\n psubsw m3, m1, m4 ;out55\n paddsw m1, m4 ;out8\n mova [rsp+gprsize*2+16*43], m2 ;out40\n mova [rsp+gprsize*2+16*26], m0 ;out23\n mova [rsp+gprsize*2+16*58], m3 ;out55\n mova [rsp+gprsize*2+16*11], m1 ;out8\n\n mova m0, [rsp+gprsize*2+16*37] ;t34\n mova m5, [rsp+gprsize*2+16*48] ;t45\n mova m3, [rsp+gprsize*2+16*53] ;t50\n mova m1, [rsp+gprsize*2+16*64] ;t61\n mova m2, [rsp+gprsize*2+16*32] ;tmp[29]\n psubsw m4, m0, m5 ;t45a\n paddsw m0, m5 ;t34a\n psubsw m5, m1, m3 ;t50a\n paddsw m1, m3 ;t61a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*5 ] ;tmp[2 ]\n psubsw m6, m2, m0 ;out34\n paddsw m2, m0 ;out29\n psubsw m0, m3, m1 ;out61\n paddsw m3, m1 ;out2\n mova [rsp+gprsize*2+16*37], m6 ;out34\n mova [rsp+gprsize*2+16*32], m2 ;out29\n mova [rsp+gprsize*2+16*64], m0 ;out61\n mova [rsp+gprsize*2+16*5 ], m3 ;out2\n mova m0, [rsp+gprsize*2+16*21] ;tmp[18]\n mova m1, [rsp+gprsize*2+16*16] ;tmp[13]\n psubsw m2, m0, m5 ;out45\n paddsw m0, m5 ;out18\n psubsw m3, m1, m4 ;out50\n paddsw m1, m4 ;out13\n mova [rsp+gprsize*2+16*48], m2 ;out45\n mova [rsp+gprsize*2+16*21], m0 ;out18\n mova [rsp+gprsize*2+16*53], m3 ;out50\n mova [rsp+gprsize*2+16*16], m1 ;out13\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m5, [rsp+gprsize*2+16*49] ;t46a\n mova m3, [rsp+gprsize*2+16*52] ;t49a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n mova m2, [rsp+gprsize*2+16*33] ;tmp[30]\n psubsw m4, m0, m5 ;t46\n paddsw m0, m5 ;t33\n psubsw m5, m1, m3 ;t49\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*4 ] ;tmp[1 ]\n psubsw m6, m2, m0 ;out33\n paddsw m2, m0 ;out30\n psubsw m0, m3, m1 ;out62\n paddsw m3, m1 ;out1\n mova [rsp+gprsize*2+16*36], m6 ;out33\n mova [rsp+gprsize*2+16*33], m2 ;out30\n mova [rsp+gprsize*2+16*65], m0 ;out62\n mova [rsp+gprsize*2+16*4 ], m3 ;out1\n mova m0, [rsp+gprsize*2+16*20] ;tmp[17]\n mova m1, [rsp+gprsize*2+16*17] ;tmp[14]\n psubsw m2, m0, m5 ;out46\n paddsw m0, m5 ;out17\n psubsw m3, m1, m4 ;out49\n paddsw m1, m4 ;out14\n mova [rsp+gprsize*2+16*49], m2 ;out46\n mova [rsp+gprsize*2+16*20], m0 ;out17\n mova [rsp+gprsize*2+16*52], m3 ;out49\n mova [rsp+gprsize*2+16*17], m1 ;out14\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m5, [rsp+gprsize*2+16*50] ;t47\n mova m3, [rsp+gprsize*2+16*51] ;t48\n mova m1, [rsp+gprsize*2+16*66] ;t63\n mova m2, [rsp+gprsize*2+16*34] ;tmp[31]\n psubsw m4, m0, m5 ;t47a\n paddsw m0, m5 ;t32a\n psubsw m5, m1, m3 ;t48a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t47, t48\n mova m3, [rsp+gprsize*2+16*3 ] ;tmp[0 ]\n psubsw m6, m2, m0 ;out32\n paddsw m2, m0 ;out31\n psubsw m0, m3, m1 ;out63\n paddsw m3, m1 ;out0\n mova [rsp+gprsize*2+16*35], m6 ;out32\n mova [rsp+gprsize*2+16*34], m2 ;out31\n mova [rsp+gprsize*2+16*66], m0 ;out63\n mova [rsp+gprsize*2+16*3 ], m3 ;out0\n mova m0, [rsp+gprsize*2+16*19] ;tmp[16]\n mova m1, [rsp+gprsize*2+16*18] ;tmp[15]\n psubsw m2, m0, m5 ;out47\n paddsw m0, m5 ;out16\n psubsw m3, m1, m4 ;out48\n paddsw m1, m4 ;out15\n mova [rsp+gprsize*2+16*50], m2 ;out47\n mova [rsp+gprsize*2+16*19], m0 ;out16\n mova [rsp+gprsize*2+16*51], m3 ;out48\n mova [rsp+gprsize*2+16*18], m1 ;out15\n ret\n\n\ncglobal inv_txfm_add_dct_dct_64x16, 4, 6, 8, 16*132, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x16_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x16).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m7, m7\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n mova m5, [dstq+16*2]\n mova m6, [dstq+16*3]\n punpckhbw m2, m1, m7\n punpcklbw m1, m7\n punpckhbw m4, m3, m7\n punpcklbw m3, m7\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n punpckhbw m2, m5, m7\n punpcklbw m5, m7\n punpckhbw m4, m6, m7\n punpcklbw m6, m7\n paddw m2, m0\n paddw m5, m0\n paddw m4, m0\n paddw m6, m0\n packuswb m5, m2\n packuswb m6, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n mova [dstq+16*2], m5\n mova [dstq+16*3], m6\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\n%macro LOAD_4ROWS 2-3 0 ;src, stride, is_rect2\n\n%if %3\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [%1+%2*0]\n pmulhrsw m1, m3, [%1+%2*1]\n pmulhrsw m2, m3, [%1+%2*2]\n pmulhrsw m3, [%1+%2*3]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n%endif\n%endmacro\n\n%macro LOAD_4ROWS_H 2 ;src, stride\n mova m4, [%1+%2*0]\n mova m5, [%1+%2*1]\n mova m6, [%1+%2*2]\n mova m7, [%1+%2*3]\n%endmacro\n\ncglobal idct_64x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mov r3d, 2\n mov [rsp+gprsize*2+16*67], dstq\n lea dstq, [rsp+gprsize+16*68]\n\n.pass1_loop:\n LOAD_4ROWS coeffq+32*0, 32*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+32*4, 32*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+32*2, 32*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+32*1, 32*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+32*17, 32*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+32*24, 32\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+32*24, 32\n\n add coeffq, 16\n add dstq, 16\n dec r3d\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*2+16*67]\n sub coeffq, 32\n mov r3d, 4\n\n.pass2_loop:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop\n\n mov r3d, 4\n lea coeffq, [rsp+gprsize+16*68]\n.pass2_loop2:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end2)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end3)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end3:\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop2\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x64).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n.end:\n RET\n\n\ncglobal idct_32x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*67]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n LOAD_4ROWS coeffq, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+128*1, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x32, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\n.end:\n RET\n\ncglobal idct_64x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*4+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8, 1\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*3+16*67]\n mov eobd, [rsp+gprsize*1+16*67]\n lea dstq, [dstq+32]\n mov [rsp+gprsize*1+16*35], eobd\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n.pass2_end:\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg m(idct_32x32_internal).pass2_loop\n\n.pass2_end2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x64, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\ncglobal idct_64x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*4+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*2+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea dstq, [dstq+32]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n jmp m(idct_16x64_internal).pass2_loop\n\n.pass2_end:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x64_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n\n dec r3\n jg m(idct_16x64_internal).pass2_loop\n\n.pass2_end2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, 4\n sub dstq, 72\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n\nSECTION_RODATA 16\n\ndeint_shuf: db 0, 1, 4, 5, 8, 9, 12, 13, 2, 3, 6, 7, 10, 11, 14, 15\n\ndeint_shuf1: db 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\ndeint_shuf2: db 8, 9, 0, 1, 10, 11, 2, 3, 12, 13, 4, 5, 14, 15, 6, 7\n\n%macro COEF_PAIR 2\npw_%1_m%2: times 4 dw %1, -%2\npw_%2_%1: times 4 dw %2, %1\n%endmacro\n\n;adst4\npw_1321_3803: times 4 dw 1321, 3803\npw_2482_m1321: times 4 dw 2482, -1321\npw_3344_2482: times 4 dw 3344, 2482\npw_3344_m3803: times 4 dw 3344, -3803\npw_3344_m3344: times 4 dw 3344, -3344\npw_0_3344 times 4 dw 0, 3344\npw_m6688_m3803: times 4 dw -6688, -3803\n\nCOEF_PAIR 2896, 2896\nCOEF_PAIR 1567, 3784\nCOEF_PAIR 799, 4017\nCOEF_PAIR 3406, 2276\nCOEF_PAIR 401, 4076\nCOEF_PAIR 1931, 3612\nCOEF_PAIR 3166, 2598\nCOEF_PAIR 3920, 1189\nCOEF_PAIR 3784, 1567\nCOEF_PAIR 995, 3973\nCOEF_PAIR 1751, 3703\nCOEF_PAIR 3513, 2106\nCOEF_PAIR 3857, 1380\nCOEF_PAIR 4017, 799\nCOEF_PAIR 201, 4091\nCOEF_PAIR 2440, 3290\nCOEF_PAIR 3035, 2751\nCOEF_PAIR 4052, 601\nCOEF_PAIR 2276, 3406\n\npd_2048: times 4 dd 2048\npw_2048: times 8 dw 2048\npw_m2048: times 8 dw -2048\npw_4096: times 8 dw 4096\npw_16384: times 8 dw 16384\npw_m16384: times 8 dw -16384\npw_1697x16: times 8 dw 1697*16\npw_1697x8: times 8 dw 1697*8\npw_2896x8: times 8 dw 2896*8\npw_3344x8: times 8 dw 3344*8\npw_8192: times 8 dw 8192\npw_m8192: times 8 dw -8192\npw_5: times 8 dw 5\npw_201x8: times 8 dw 201*8\npw_4091x8: times 8 dw 4091*8\npw_m2751x8: times 8 dw -2751*8\npw_3035x8: times 8 dw 3035*8\npw_1751x8: times 8 dw 1751*8\npw_3703x8: times 8 dw 3703*8\npw_m1380x8: times 8 dw -1380*8\npw_3857x8: times 8 dw 3857*8\npw_995x8: times 8 dw 995*8\npw_3973x8: times 8 dw 3973*8\npw_m2106x8: times 8 dw -2106*8\npw_3513x8: times 8 dw 3513*8\npw_2440x8: times 8 dw 2440*8\npw_3290x8: times 8 dw 3290*8\npw_m601x8: times 8 dw -601*8\npw_4052x8: times 8 dw 4052*8\n\npw_4095x8: times 8 dw 4095*8\npw_101x8: times 8 dw 101*8\npw_2967x8: times 8 dw 2967*8\npw_m2824x8: times 8 dw -2824*8\npw_3745x8: times 8 dw 3745*8\npw_1660x8: times 8 dw 1660*8\npw_3822x8: times 8 dw 3822*8\npw_m1474x8: times 8 dw -1474*8\npw_3996x8: times 8 dw 3996*8\npw_897x8: times 8 dw 897*8\npw_3461x8: times 8 dw 3461*8\npw_m2191x8: times 8 dw -2191*8\npw_3349x8: times 8 dw 3349*8\npw_2359x8: times 8 dw 2359*8\npw_4036x8: times 8 dw 4036*8\npw_m700x8: times 8 dw -700*8\npw_4065x8: times 8 dw 4065*8\npw_501x8: times 8 dw 501*8\npw_3229x8: times 8 dw 3229*8\npw_m2520x8: times 8 dw -2520*8\npw_3564x8: times 8 dw 3564*8\npw_2019x8: times 8 dw 2019*8\npw_3948x8: times 8 dw 3948*8\npw_m1092x8: times 8 dw -1092*8\npw_3889x8: times 8 dw 3889*8\npw_1285x8: times 8 dw 1285*8\npw_3659x8: times 8 dw 3659*8\npw_m1842x8: times 8 dw -1842*8\npw_3102x8: times 8 dw 3102*8\npw_2675x8: times 8 dw 2675*8\npw_4085x8: times 8 dw 4085*8\npw_m301x8: times 8 dw -301*8\n\niadst4_dconly1a: times 2 dw 10568, 19856, 26752, 30424\niadst4_dconly1b: times 2 dw 30424, 26752, 19856, 10568\niadst4_dconly2a: dw 10568, 10568, 10568, 10568, 19856, 19856, 19856, 19856\niadst4_dconly2b: dw 26752, 26752, 26752, 26752, 30424, 30424, 30424, 30424\n\nSECTION .text\n\n%macro REPX 2-*\n %xdefine %%f(x) %1\n%rep %0 - 1\n %rotate 1\n %%f(%1)\n%endrep\n%endmacro\n\n%define m(x) mangle(private_prefix %+ _ %+ x %+ SUFFIX)\n\n%if ARCH_X86_64\n%define o(x) x\n%else\n%define o(x) r5-$$+x ; PIC\n%endif\n\n%macro WRITE_4X4 9 ;src[1-2], tmp[1-3], row[1-4]\n lea r2, [dstq+strideq*2]\n%assign %%i 1\n%rotate 5\n%rep 4\n %if %1 & 2\n CAT_XDEFINE %%row_adr, %%i, r2 + strideq*(%1&1)\n %else\n CAT_XDEFINE %%row_adr, %%i, dstq + strideq*(%1&1)\n %endif\n %assign %%i %%i + 1\n %rotate 1\n%endrep\n\n movd m%3, [%%row_adr1] ;dst0\n movd m%5, [%%row_adr2] ;dst1\n punpckldq m%3, m%5 ;high: dst1 :low: dst0\n movd m%4, [%%row_adr3] ;dst2\n movd m%5, [%%row_adr4] ;dst3\n punpckldq m%4, m%5 ;high: dst3 :low: dst2\n\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n\n paddw m%3, m%1 ;high: dst1 + out1 ;low: dst0 + out0\n paddw m%4, m%2 ;high: dst3 + out3 ;low: dst2 + out2\n\n packuswb m%3, m%4 ;high->low: dst3 + out3, dst2 + out2, dst1 + out1, dst0 + out0\n\n movd [%%row_adr1], m%3 ;store dst0 + out0\n pshuflw m%4, m%3, q1032\n movd [%%row_adr2], m%4 ;store dst1 + out1\n punpckhqdq m%3, m%3\n movd [%%row_adr3], m%3 ;store dst2 + out2\n psrlq m%3, 32\n movd [%%row_adr4], m%3 ;store dst3 + out3\n%endmacro\n\n%macro ITX4_END 4-5 2048 ; row[1-4], rnd\n%if %5\n mova m2, [o(pw_%5)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n%endif\n\n WRITE_4X4 0, 1, 2, 3, 4, %1, %2, %3, %4\n ret\n%endmacro\n\n; flags: 1 = swap, 2: coef_regs, 4: no_pack\n%macro ITX_MUL2X_PACK 5-6 0 ; dst/src, tmp[1], rnd, coef[1-2], flags\n%if %6 & 2\n pmaddwd m%2, m%4, m%1\n pmaddwd m%1, m%5\n%elif %6 & 1\n pmaddwd m%2, m%1, [o(pw_%5_%4)]\n pmaddwd m%1, [o(pw_%4_m%5)]\n%else\n pmaddwd m%2, m%1, [o(pw_%4_m%5)]\n pmaddwd m%1, [o(pw_%5_%4)]\n%endif\n paddd m%2, m%3\n paddd m%1, m%3\n psrad m%2, 12\n psrad m%1, 12\n%if %6 & 4 == 0\n packssdw m%1, m%2\n%endif\n%endmacro\n\n%macro IDCT4_1D_PACKED 0-1 ;pw_2896x8\n mova m3, [o(pd_2048)]\n punpckhwd m2, m0, m1 ;unpacked in1 in3\n punpcklwd m0, m1 ;unpacked in0 in2\n ITX_MUL2X_PACK 2, 1, 3, 1567, 3784\n ITX_MUL2X_PACK 0, 1, 3, 2896, 2896\n psubsw m1, m0, m2 ;high: out2 ;low: out3\n paddsw m0, m2 ;high: out1 ;low: out0\n%endmacro\n\n%macro INV_TXFM_FN 5+ ; type1, type2, fast_thresh, size, xmm/stack\ncglobal inv_txfm_add_%1_%2_%4, 4, 6, %5, dst, stride, coeff, eob, tx2\n %undef cmp\n %define %%p1 m(i%1_%4_internal)\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n%if has_epilogue\n%if %3 > 0\n cmp eobd, %3\n jle %%end\n%elif %3 == 0\n test eobd, eobd\n jz %%end\n%endif\n lea tx2q, [o(m(i%2_%4_internal).pass2)]\n call %%p1\n RET\n%%end:\n%else\n lea tx2q, [o(m(i%2_%4_internal).pass2)]\n%if %3 > 0\n cmp eobd, %3\n jg %%p1\n%elif %3 == 0\n test eobd, eobd\n jnz %%p1\n%else\n times ((%%end - %%p1) >> 31) & 1 jmp %%p1\nALIGN function_align\n%%end:\n%endif\n%endif\n%endmacro\n\n%macro INV_TXFM_4X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x4, 6\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n TAIL_CALL m(iadst_4x4_internal).end\n%elifidn %1_%2, identity_dct\n mova m1, [coeffq+16*0]\n mova m2, [coeffq+16*1]\n punpcklwd m0, m1, m2\n punpckhwd m1, m2\n punpcklwd m0, m1\n punpcklqdq m0, m0\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end\n%elif %3 >= 0\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n%ifidn %1, dct\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%elifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%elifidn %1, flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd ;0\n%ifidn %2, dct\n%ifnidn %1, dct\n pmulhrsw m0, [o(pw_2896x8)]\n%else\n pmulhrsw m0, m1\n%endif\n mova m1, m0\n TAIL_CALL m(iadst_4x4_internal).end2\n%else ; adst / flipadst\n pmulhrsw m1, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n TAIL_CALL m(i%2_4x4_internal).end2\n%endif\n%endif\n%endmacro\n\nINIT_XMM ssse3\n\nINV_TXFM_4X4_FN dct, dct, 0\nINV_TXFM_4X4_FN dct, adst, 0\nINV_TXFM_4X4_FN dct, flipadst, 0\nINV_TXFM_4X4_FN dct, identity, 3\n\ncglobal idct_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0] ;high: in1 ;low: in0\n mova m1, [coeffq+16*1] ;high: in3 ;low in2\n\n IDCT4_1D_PACKED\n\n mova m2, [o(deint_shuf)]\n shufps m3, m0, m1, q1331\n shufps m0, m1, q0220\n pshufb m0, m2 ;high: in1 ;low: in0\n pshufb m1, m3, m2 ;high: in3 ;low :in2\n jmp tx2q\n\n.pass2:\n IDCT4_1D_PACKED\n\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2 ;memset(coeff, 0, sizeof(*coeff) * sh * sw);\n\n ITX4_END 0, 1, 3, 2\n\nINV_TXFM_4X4_FN adst, dct, 0\nINV_TXFM_4X4_FN adst, adst, 0\nINV_TXFM_4X4_FN adst, flipadst, 0\nINV_TXFM_4X4_FN adst, identity\n\ncglobal iadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call .main\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 0, 1, 2, 3\n\nALIGN function_align\n.main:\n punpcklwd m2, m0, m1 ;unpacked in0 in2\n punpckhwd m0, m1 ;unpacked in1 in3\n mova m3, m0\n pmaddwd m1, m2, [o(pw_3344_m3344)];3344 * in0 - 3344 * in2\n pmaddwd m0, [o(pw_0_3344)] ;3344 * in3\n paddd m1, m0 ;t2\n pmaddwd m0, m2, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m2, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m4, m3, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m3, [o(pw_3344_m3803)];3344 * in1 - 3803 * in3\n paddd m4, m0 ;t0 + t3\n pmaddwd m3, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m0, [o(pd_2048)]\n paddd m1, m0 ;t2 + 2048\n paddd m2, m0\n paddd m0, m4 ;t0 + t3 + 2048\n paddd m5, m2 ;t1 + t3 + 2048\n paddd m2, m4\n paddd m2, m3 ;t0 + t1 - t3 + 2048\n REPX {psrad x, 12}, m1, m0, m5, m2\n packssdw m0, m5 ;high: out1 ;low: out0\n packssdw m1, m2 ;high: out3 ;low: out3\n ret\n\nINV_TXFM_4X4_FN flipadst, dct, 0\nINV_TXFM_4X4_FN flipadst, adst, 0\nINV_TXFM_4X4_FN flipadst, flipadst, 0\nINV_TXFM_4X4_FN flipadst, identity\n\ncglobal iflipadst_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n call m(iadst_4x4_internal).main\n punpcklwd m2, m1, m0\n punpckhwd m1, m0\n punpcklwd m0, m1, m2 ;high: in3 ;low :in2\n punpckhwd m1, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n call m(iadst_4x4_internal).main\n\n.end:\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n\n.end2:\n ITX4_END 3, 2, 1, 0\n\nINV_TXFM_4X4_FN identity, dct, 3\nINV_TXFM_4X4_FN identity, adst\nINV_TXFM_4X4_FN identity, flipadst\nINV_TXFM_4X4_FN identity, identity\n\ncglobal iidentity_4x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m0, m3\n pmulhrsw m3, m1\n paddsw m0, m2\n paddsw m1, m3\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m0, m2 ;high: in3 ;low :in2\n punpcklwd m0, m2 ;high: in1 ;low: in0\n jmp tx2q\n\n.pass2:\n mova m3, [o(pw_1697x8)]\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddsw m0, m2\n paddsw m1, m3\n jmp m(iadst_4x4_internal).end\n\n%macro IWHT4_1D_PACKED 0\n punpckhqdq m3, m0, m1 ;low: in1 high: in3\n punpcklqdq m0, m1 ;low: in0 high: in2\n psubw m2, m0, m3 ;low: in0 - in1 high: in2 - in3\n paddw m0, m3 ;low: in0 + in1 high: in2 + in3\n punpckhqdq m2, m2 ;t2 t2\n punpcklqdq m0, m0 ;t0 t0\n psubw m1, m0, m2\n psraw m1, 1 ;t4 t4\n psubw m1, m3 ;low: t1/out2 high: t3/out1\n psubw m0, m1 ;high: out0\n paddw m2, m1 ;low: out3\n%endmacro\n\ncglobal inv_txfm_add_wht_wht_4x4, 3, 3, 4, dst, stride, coeff\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pxor m2, m2\n mova [coeffq+16*0], m2\n mova [coeffq+16*1], m2\n psraw m0, 2\n psraw m1, 2\n\n IWHT4_1D_PACKED\n\n punpckhwd m0, m1\n punpcklwd m3, m1, m2\n punpckhdq m1, m0, m3\n punpckldq m0, m3\n\n IWHT4_1D_PACKED\n\n shufpd m0, m2, 0x01\n ITX4_END 0, 3, 2, 1, 0\n\n\n%macro IDCT8_1D_PACKED 0\n mova m6, [o(pd_2048)]\n punpckhwd m4, m0, m3 ;unpacked in1 in7\n punpcklwd m0, m2 ;unpacked in0 in4\n punpckhwd m2, m1 ;unpacked in5 in3\n punpcklwd m1, m3 ;unpacked in2 in6\n ITX_MUL2X_PACK 4, 3, 6, 799, 4017 ;low: t7a high: t4a\n ITX_MUL2X_PACK 2, 3, 6, 3406, 2276 ;low: t6a high: t5a\n ITX_MUL2X_PACK 1, 3, 6, 1567, 3784 ;low: t3 high: t2\n psubsw m3, m4, m2 ;low: t6a high: t5a\n paddsw m4, m2 ;low: t7 high: t4\n pshufb m3, [o(deint_shuf1)]\n ITX_MUL2X_PACK 0, 2, 6, 2896, 2896 ;low: t0 high: t1\n ITX_MUL2X_PACK 3, 2, 6, 2896, 2896 ;low: t6 high: t5\n psubsw m2, m0, m1 ;low: tmp3 high: tmp2\n paddsw m0, m1 ;low: tmp0 high: tmp1\n punpcklqdq m1, m4, m3 ;low: t7 high: t6\n punpckhqdq m4, m3 ;low: t4 high: t5\n psubsw m3, m0, m1 ;low: out7 high: out6\n paddsw m0, m1 ;low: out0 high: out1\n paddsw m1, m2, m4 ;low: out3 high: out2\n psubsw m2, m4 ;low: out4 high: out5\n%endmacro\n\n;dst1 = (src1 * coef1 - src2 * coef2 + rnd) >> 12\n;dst2 = (src1 * coef2 + src2 * coef1 + rnd) >> 12\n%macro ITX_MULSUB_2W 7-8 0 ; dst/src[1-2], tmp[1-2], rnd, coef[1-2], dst2_in_tmp1\n punpckhwd m%4, m%1, m%2\n punpcklwd m%1, m%2\n%if %7 < 8\n pmaddwd m%2, m%7, m%1\n pmaddwd m%3, m%7, m%4\n%else\n mova m%2, [o(pw_%7_%6)]\n%if %8\n pmaddwd m%3, m%1, m%2\n pmaddwd m%2, m%4\n%else\n pmaddwd m%3, m%4, m%2\n pmaddwd m%2, m%1\n%endif\n%endif\n paddd m%3, m%5\n paddd m%2, m%5\n psrad m%3, 12\n psrad m%2, 12\n%if %8\n packssdw m%3, m%2\n%else\n packssdw m%2, m%3 ;dst2\n%endif\n%if %7 < 8\n pmaddwd m%4, m%6\n pmaddwd m%1, m%6\n%elif %8\n mova m%2, [o(pw_%6_m%7)]\n pmaddwd m%4, m%2\n pmaddwd m%1, m%2\n%else\n mova m%3, [o(pw_%6_m%7)]\n pmaddwd m%4, m%3\n pmaddwd m%1, m%3\n%endif\n paddd m%4, m%5\n paddd m%1, m%5\n psrad m%4, 12\n psrad m%1, 12\n packssdw m%1, m%4 ;dst1\n%endmacro\n\n%macro IDCT4_1D 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %2, %4, %5, %6, %7, 1567, 3784, 1 ;t2, t3\n ITX_MULSUB_2W %1, %3, %4, %6, %7, 2896, 2896, 1 ;t1, t0\n psubsw m%3, m%1, m%2 ;out2\n paddsw m%2, m%1 ;out1\n paddsw m%1, m%5, m%4 ;out0\n psubsw m%4, m%5 ;out3\n%endmacro\n\n%macro WRITE_4X8 4 ;row[1-4]\n WRITE_4X4 0, 1, 4, 5, 6, %1, %2, %3, %4\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 2, 3, 4, 5, 6, %1, %2, %3, %4\n%endmacro\n\n%macro INV_4X8 0\n punpckhwd m4, m2, m3\n punpcklwd m2, m3\n punpckhwd m3, m0, m1\n punpcklwd m0, m1\n punpckhdq m1, m0, m2 ;low: in2 high: in3\n punpckldq m0, m2 ;low: in0 high: in1\n punpckldq m2, m3, m4 ;low: in4 high: in5\n punpckhdq m3, m4 ;low: in6 high: in7\n%endmacro\n\n%macro INV_TXFM_4X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x8, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_4096)]\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n movd m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n mova m2, [o(pw_2896x8)]\n punpckldq m0, m1\n pmulhrsw m0, m2\n pmulhrsw m1, m0, [o(pw_1697x8)]\n paddsw m0, m1\n pmulhrsw m0, m2\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n TAIL_CALL m(iadst_4x8_internal).end4\n%endif\n%endif\n%endmacro\n\nINV_TXFM_4X8_FN dct, dct, 0\nINV_TXFM_4X8_FN dct, identity, 7\nINV_TXFM_4X8_FN dct, adst\nINV_TXFM_4X8_FN dct, flipadst\n\ncglobal idct_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(idct_8x4_internal).main\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n call .main\n shufps m1, m1, q1032\n shufps m3, m3, q1032\n mova m4, [o(pw_2048)]\n jmp m(iadst_4x8_internal).end2\n\nALIGN function_align\n.main:\n IDCT8_1D_PACKED\n ret\n\n\nINV_TXFM_4X8_FN adst, dct, 0\nINV_TXFM_4X8_FN adst, adst\nINV_TXFM_4X8_FN adst, flipadst\nINV_TXFM_4X8_FN adst, identity\n\ncglobal iadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n.pass1_end:\n INV_4X8\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call .main\n mova m4, [o(pw_2048)]\n pxor m5, m5\n psubw m5, m4\n\n.end:\n punpcklqdq m4, m5\n\n.end2:\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end3:\n pxor m5, m5\n mova [coeffq+16*0], m5\n mova [coeffq+16*1], m5\n mova [coeffq+16*2], m5\n mova [coeffq+16*3], m5\n\n.end4:\n WRITE_4X8 0, 1, 2, 3\n RET\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n punpckhwd m4, m3, m0 ;unpacked in7 in0\n punpckhwd m5, m2, m1 ;unpacked in5 in2\n punpcklwd m1, m2 ;unpacked in3 in4\n punpcklwd m0, m3 ;unpacked in1 in6\n ITX_MUL2X_PACK 4, 2, 6, 401, 4076 ;low: t0a high: t1a\n ITX_MUL2X_PACK 5, 2, 6, 1931, 3612 ;low: t2a high: t3a\n ITX_MUL2X_PACK 1, 2, 6, 3166, 2598 ;low: t4a high: t5a\n ITX_MUL2X_PACK 0, 2, 6, 3920, 1189 ;low: t6a high: t7a\n\n psubsw m3, m4, m1 ;low: t4 high: t5\n paddsw m4, m1 ;low: t0 high: t1\n psubsw m2, m5, m0 ;low: t6 high: t7\n paddsw m5, m0 ;low: t2 high: t3\n\n shufps m1, m3, m2, q1032\n punpckhwd m2, m1\n punpcklwd m3, m1\n ITX_MUL2X_PACK 3, 0, 6, 1567, 3784, 1 ;low: t5a high: t4a\n ITX_MUL2X_PACK 2, 0, 6, 3784, 1567 ;low: t7a high: t6a\n\n psubsw m1, m4, m5 ;low: t2 high: t3\n paddsw m4, m5 ;low: out0 high: -out7\n psubsw m5, m3, m2 ;low: t7 high: t6\n paddsw m3, m2 ;low: out6 high: -out1\n shufps m0, m4, m3, q3210 ;low: out0 high: -out1\n shufps m3, m4, q3210 ;low: out6 high: -out7\n\n mova m2, [o(pw_2896_m2896)]\n mova m7, [o(pw_2896_2896)]\n shufps m4, m1, m5, q1032 ;low: t3 high: t7\n shufps m1, m5, q3210 ;low: t2 high: t6\n punpcklwd m5, m1, m4\n punpckhwd m1, m4\n pmaddwd m4, m2, m1 ;-out5\n pmaddwd m2, m5 ; out4\n pmaddwd m1, m7 ; out2\n pmaddwd m5, m7 ;-out3\n REPX {paddd x, m6}, m4, m2, m1, m5\n REPX {psrad x, 12}, m4, m2, m1, m5\n packssdw m1, m5 ;low: out2 high: -out3\n packssdw m2, m4 ;low: out4 high: -out5\n ret\n\nINV_TXFM_4X8_FN flipadst, dct, 0\nINV_TXFM_4X8_FN flipadst, adst\nINV_TXFM_4X8_FN flipadst, flipadst\nINV_TXFM_4X8_FN flipadst, identity\n\ncglobal iflipadst_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n call m(iadst_8x4_internal).main\n\n punpcklwd m4, m3, m2\n punpckhwd m3, m2\n punpcklwd m5, m1, m0\n punpckhwd m1, m0\n punpckldq m2, m3, m1 ;low: in4 high: in5\n punpckhdq m3, m1 ;low: in6 high: in7\n punpckldq m0, m4, m5 ;low: in0 high: in1\n punpckhdq m1, m4, m5 ;low: in2 high: in3\n jmp tx2q\n\n.pass2:\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n mova m4, m0\n mova m5, m1\n pshufd m0, m3, q1032\n pshufd m1, m2, q1032\n pshufd m2, m5, q1032\n pshufd m3, m4, q1032\n mova m5, [o(pw_2048)]\n pxor m4, m4\n psubw m4, m5\n jmp m(iadst_4x8_internal).end\n\nINV_TXFM_4X8_FN identity, dct, 3\nINV_TXFM_4X8_FN identity, adst\nINV_TXFM_4X8_FN identity, flipadst\nINV_TXFM_4X8_FN identity, identity\n\ncglobal iidentity_4x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n.pass1:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddsw m0, m4\n paddsw m1, m5\n paddsw m2, m6\n paddsw m3, m7\n jmp m(iadst_4x8_internal).pass1_end\n\n.pass2:\n mova m4, [o(pw_4096)]\n jmp m(iadst_4x8_internal).end2\n\n\n%macro WRITE_8X2 5 ;coefs[1-2], tmp[1-3]\n movq m%3, [dstq ]\n movq m%4, [dstq+strideq]\n pxor m%5, m%5\n punpcklbw m%3, m%5 ;extend byte to word\n punpcklbw m%4, m%5 ;extend byte to word\n%ifnum %1\n paddw m%3, m%1\n%else\n paddw m%3, %1\n%endif\n%ifnum %2\n paddw m%4, m%2\n%else\n paddw m%4, %2\n%endif\n packuswb m%3, m%4\n movq [dstq ], m%3\n punpckhqdq m%3, m%3\n movq [dstq+strideq], m%3\n%endmacro\n\n%macro WRITE_8X4 7 ;coefs[1-4], tmp[1-3]\n WRITE_8X2 %1, %2, %5, %6, %7\n lea dstq, [dstq+strideq*2]\n WRITE_8X2 %3, %4, %5, %6, %7\n%endmacro\n\n%macro INV_TXFM_8X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m1, m0, [coeffq]\n pmulhrsw m1, m0\n pmulhrsw m0, m1, [o(pw_1697x8)]\n paddsw m1, m0\n pmulhrsw m1, [o(pw_2048)]\n punpcklwd m1, m1\n punpckhdq m2, m1, m1\n punpckldq m1, m1\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckldq m0, m1, m1\n punpckhdq m1, m1\n%elifidn %1_%2, identity_dct\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m5, m2, m3\n punpcklwd m2, m3\n punpcklwd m0, m4\n punpcklwd m2, m5\n punpcklqdq m0, m2\n mova m4, [o(pw_2896x8)]\n pmulhrsw m0, m4\n paddsw m0, m0\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else\n pshuflw m0, [coeffq], q0000\n punpcklqdq m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n pmulhrsw m0, m1\n%ifidn %2, dct\n mova m2, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mova m1, m0\n mova m2, m0\n mova m3, m0\n%else ; adst / flipadst\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n%endif\n%endif\n TAIL_CALL m(iadst_8x4_internal).end2\n%endif\n%endmacro\n\nINV_TXFM_8X4_FN dct, dct, 0\nINV_TXFM_8X4_FN dct, adst, 0\nINV_TXFM_8X4_FN dct, flipadst, 0\nINV_TXFM_8X4_FN dct, identity, 3\n\ncglobal idct_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n call m(idct_4x8_internal).main\n\n mova m4, [o(deint_shuf1)]\n mova m5, [o(deint_shuf2)]\n pshufb m0, m4\n pshufb m1, m5\n pshufb m2, m4\n pshufb m3, m5\n punpckhdq m4, m0, m1\n punpckldq m0, m1\n punpckhdq m5, m2, m3\n punpckldq m2, m3\n punpckhqdq m1, m0, m2 ;in1\n punpcklqdq m0, m2 ;in0\n punpckhqdq m3, m4, m5 ;in3\n punpcklqdq m2 ,m4, m5 ;in2\n jmp tx2q\n\n.pass2:\n call .main\n jmp m(iadst_8x4_internal).end\n\nALIGN function_align\n.main:\n mova m6, [o(pd_2048)]\n IDCT4_1D 0, 1, 2, 3, 4, 5, 6\n ret\n\nINV_TXFM_8X4_FN adst, dct\nINV_TXFM_8X4_FN adst, adst\nINV_TXFM_8X4_FN adst, flipadst\nINV_TXFM_8X4_FN adst, identity\n\ncglobal iadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n pxor m5, m5\n psubsw m3, m5, m1\n psubsw m5, m4\n punpckhdq m4, m5, m3\n punpckldq m5, m3\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m5 ;in1\n punpcklwd m0, m5 ;in0\n punpcklwd m2, m3, m4 ;in2\n punpckhwd m3, m4 ;in3\n jmp tx2q\n\n.pass2:\n call .main\n\n.end:\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m4\n pmulhrsw m1, m4\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n\n.end2:\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n mova [coeffq+16*2], m6\n mova [coeffq+16*3], m6\n.end3:\n WRITE_8X4 0, 1, 2, 3, 4, 5, 6\n RET\n\nALIGN function_align\n.main:\n punpckhwd m6, m0, m2 ;unpacked in0 in2\n punpcklwd m0, m2 ;unpacked in0 in2\n punpckhwd m7, m1, m3 ;unpacked in1 in3\n punpcklwd m1, m3 ;unpacked in1 in3\n\n mova m2, [o(pw_3344_m3344)]\n mova m4, [o(pw_0_3344)]\n pmaddwd m3, m2, m6 ;3344 * in0 - 3344 * in2\n pmaddwd m5, m4, m7 ;3344 * in3\n pmaddwd m2, m0\n pmaddwd m4, m1\n paddd m3, m5\n paddd m2, m4\n mova m4, [o(pd_2048)]\n paddd m3, m4 ;t2 + 2048\n paddd m2, m4\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n\n pmaddwd m4, m0, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m0, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m3, m1, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m1, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m3, m4 ;t0 + t3\n\n pmaddwd m1, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n mova m4, [o(pd_2048)]\n paddd m0, m4\n paddd m4, m3 ;t0 + t3 + 2048\n paddd m5, m0 ;t1 + t3 + 2048\n paddd m3, m0\n paddd m3, m1 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m3, 12 ;out3\n packssdw m0, m4, m5 ;low: out0 high: out1\n\n pmaddwd m4, m6, [o(pw_1321_3803)] ;1321 * in0 + 3803 * in2\n pmaddwd m6, [o(pw_2482_m1321)] ;2482 * in0 - 1321 * in2\n pmaddwd m1, m7, [o(pw_3344_2482)] ;3344 * in1 + 2482 * in3\n pmaddwd m5, m7, [o(pw_3344_m3803)] ;3344 * in1 - 3803 * in3\n paddd m1, m4 ;t0 + t3\n pmaddwd m7, [o(pw_m6688_m3803)] ;-2 * 3344 * in1 - 3803 * in3\n\n mova m4, [o(pd_2048)]\n paddd m6, m4\n paddd m4, m1 ;t0 + t3 + 2048\n paddd m5, m6 ;t1 + t3 + 2048\n paddd m1, m6\n paddd m1, m7 ;t0 + t1 - t3 + 2048\n\n psrad m4, 12 ;out0\n psrad m5, 12 ;out1\n psrad m1, 12 ;out3\n packssdw m3, m1 ;out3\n packssdw m4, m5 ;low: out0 high: out1\n\n punpckhqdq m1, m0, m4 ;out1\n punpcklqdq m0, m4 ;out0\n ret\n\nINV_TXFM_8X4_FN flipadst, dct\nINV_TXFM_8X4_FN flipadst, adst\nINV_TXFM_8X4_FN flipadst, flipadst\nINV_TXFM_8X4_FN flipadst, identity\n\ncglobal iflipadst_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n\n shufps m0, m0, q1032\n shufps m1, m1, q1032\n call m(iadst_4x8_internal).main\n\n punpckhwd m5, m3, m2\n punpcklwd m3, m2\n punpckhwd m2, m1, m0\n punpcklwd m1, m0\n\n pxor m0, m0\n psubsw m4, m0, m2\n psubsw m0, m5\n punpckhdq m2, m0, m4\n punpckldq m0, m4\n punpckhdq m4, m3, m1\n punpckldq m3, m1\n punpckhwd m1, m0, m3 ;in1\n punpcklwd m0, m3 ;in0\n punpckhwd m3, m2, m4 ;in3\n punpcklwd m2, m4 ;in2\n jmp tx2q\n\n.pass2:\n call m(iadst_8x4_internal).main\n mova m4, m0\n mova m5, m1\n mova m0, m3\n mova m1, m2\n mova m2, m5\n mova m3, m4\n jmp m(iadst_8x4_internal).end\n\nINV_TXFM_8X4_FN identity, dct, 7\nINV_TXFM_8X4_FN identity, adst\nINV_TXFM_8X4_FN identity, flipadst\nINV_TXFM_8X4_FN identity, identity\n\ncglobal iidentity_8x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [coeffq+16*0]\n pmulhrsw m1, m3, [coeffq+16*1]\n pmulhrsw m2, m3, [coeffq+16*2]\n pmulhrsw m3, [coeffq+16*3]\n paddsw m0, m0\n paddsw m1, m1\n paddsw m2, m2\n paddsw m3, m3\n\n punpckhwd m4, m0, m1\n punpcklwd m0, m1\n punpckhwd m1, m2, m3\n punpcklwd m2, m3\n punpckhdq m5, m4, m1\n punpckldq m4, m1\n punpckhdq m3, m0, m2\n punpckldq m0, m2\n punpckhwd m1, m0, m4 ;in1\n punpcklwd m0, m4 ;in0\n punpcklwd m2, m3, m5 ;in2\n punpckhwd m3, m5 ;in3\n jmp tx2q\n\n.pass2:\n mova m7, [o(pw_1697x8)]\n pmulhrsw m4, m7, m0\n pmulhrsw m5, m7, m1\n pmulhrsw m6, m7, m2\n pmulhrsw m7, m3\n paddsw m0, m4\n paddsw m1, m5\n paddsw m2, m6\n paddsw m3, m7\n jmp m(iadst_8x4_internal).end\n\n%macro INV_TXFM_8X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x8, 8, 16*4\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n pmulhrsw m0, [coeffq]\n mova m1, [o(pw_16384)]\n pmulhrsw m0, m1\n psrlw m1, 2\n pmulhrsw m0, m1\n punpckhwd m7, m0, m0\n punpcklwd m0, m0\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end2\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n TAIL_CALL m(iadst_8x4_internal).end3\n%elif %3 >= 0\n%ifidn %1, dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 3\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n.end:\n mov r3d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x8).end3)]\n.loop:\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n jmp tx2q\n.end3:\n RET\n%else ; identity\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n punpcklwd m0, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n punpcklwd m2, [coeffq+16*6]\n punpcklwd m3, [coeffq+16*7]\n punpcklwd m0, m2\n punpcklwd m1, m3\n punpcklwd m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n pxor m4, m4\n REPX {mova [coeffq+16*x], m4}, 0, 1, 2, 3, 4, 5, 6, 7\n jmp m(inv_txfm_add_dct_dct_8x8).end\n%endif\n%endif\n%endmacro\n\n%macro LOAD_8ROWS 2-3 0 ; src, stride, is_rect2\n%if %3\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [%1+%2*0]\n pmulhrsw m1, m7, [%1+%2*1]\n pmulhrsw m2, m7, [%1+%2*2]\n pmulhrsw m3, m7, [%1+%2*3]\n pmulhrsw m4, m7, [%1+%2*4]\n pmulhrsw m5, m7, [%1+%2*5]\n pmulhrsw m6, m7, [%1+%2*6]\n pmulhrsw m7, [%1+%2*7]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n mova m7, [%1+%2*7]\n%endif\n%endmacro\n\n%macro IDCT8_1D_ODDHALF 7 ; src[1-4], tmp[1-2], pd_2048\n ITX_MULSUB_2W %1, %4, %5, %6, %7, 799, 4017 ;t4a, t7a\n ITX_MULSUB_2W %3, %2, %5, %6, %7, 3406, 2276, 1 ;t5a, t6a\n psubsw m%2, m%4, m%5 ;t6a\n paddsw m%4, m%5 ;t7\n psubsw m%5, m%1, m%3 ;t5a\n paddsw m%1, m%3 ;t4\n ITX_MULSUB_2W %2, %5, %3, %6, %7, 2896, 2896, 1 ;t5, t6\n%endmacro\n\nINV_TXFM_8X8_FN dct, dct, 0\nINV_TXFM_8X8_FN dct, identity, 7\nINV_TXFM_8X8_FN dct, adst\nINV_TXFM_8X8_FN dct, flipadst\n\ncglobal idct_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.pass1_end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n\n.pass1_end3:\n punpcklwd m6, m1, m5 ;10 50 11 51 12 52 13 53\n punpckhwd m1, m5 ;14 54 15 55 16 56 17 57\n punpckhwd m5, m0, m4 ;04 44 05 45 06 46 07 47\n punpcklwd m0, m4 ;00 40 01 41 02 42 03 43\n punpckhwd m4, m3, m7 ;34 74 35 75 36 76 37 77\n punpcklwd m3, m7 ;30 70 31 71 32 72 33 73\n punpckhwd m7, m1, m4 ;16 36 56 76 17 37 57 77\n punpcklwd m1, m4 ;14 34 54 74 15 35 55 75\n punpckhwd m4, m6, m3 ;12 32 52 72 13 33 53 73\n punpcklwd m6, m3 ;10 30 50 70 11 31 51 71\n mova [rsp+gprsize+16*2], m6\n mova m6, [rsp+gprsize+16*1]\n punpckhwd m3, m2, m6 ;24 64 25 65 26 66 27 67\n punpcklwd m2, m6 ;20 60 21 61 22 62 23 63\n punpckhwd m6, m5, m3 ;06 26 46 66 07 27 47 67\n punpcklwd m5, m3 ;04 24 44 64 05 25 45 65\n punpckhwd m3, m0, m2 ;02 22 42 62 03 23 43 63\n punpcklwd m0, m2 ;00 20 40 60 01 21 41 61\n\n punpckhwd m2, m6, m7 ;07 17 27 37 47 57 67 77\n punpcklwd m6, m7 ;06 16 26 36 46 56 66 76\n mova [rsp+gprsize+16*0], m2\n punpcklwd m2, m3, m4 ;02 12 22 32 42 52 62 72\n punpckhwd m3, m4 ;03 13 23 33 43 53 63 73\n punpcklwd m4, m5, m1 ;04 14 24 34 44 54 64 74\n punpckhwd m5, m1 ;05 15 25 35 45 55 65 75\n mova m7, [rsp+gprsize+16*2]\n punpckhwd m1, m0, m7 ;01 11 21 31 41 51 61 71\n punpcklwd m0, m7 ;00 10 20 30 40 50 60 70\n mova m7, [rsp+gprsize+16*0]\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n\n.end2:\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, [rsp+gprsize+16*0]\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*0], m7\n\n.end3:\n WRITE_8X4 0, 1, 2, 3, 5, 6, 7\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 4, [rsp+gprsize+16*2], [rsp+gprsize+16*1], [rsp+gprsize+16*0], 5, 6, 7\n jmp tx2q\n\n.end4:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m1\n mova m7, [o(pd_2048)]\n IDCT4_1D 0, 2, 4, 6, 1, 3, 7\n mova m3, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m2\n mova m2, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m4\n mova m4, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m6\n IDCT8_1D_ODDHALF 3, 2, 5, 4, 1, 6, 7\n mova m6, [rsp+gprsize*2+16*0]\n psubsw m7, m0, m4 ;out7\n paddsw m0, m4 ;out0\n mova [rsp+gprsize*2+16*0], m7\n mova m1, [rsp+gprsize*2+16*2]\n psubsw m4, m6, m3 ;out4\n paddsw m3, m6 ;out3\n mova m7, [rsp+gprsize*2+16*1]\n psubsw m6, m1, m5 ;out6\n paddsw m1, m5 ;out1\n psubsw m5, m7, m2 ;out5\n paddsw m2, m7 ;out2\n ret\n\n\nINV_TXFM_8X8_FN adst, dct\nINV_TXFM_8X8_FN adst, adst\nINV_TXFM_8X8_FN adst, flipadst\nINV_TXFM_8X8_FN adst, identity\n\ncglobal iadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call .main\n call .main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_16384)]\n\n.pass1_end1:\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).pass1_end2\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call .main\n call .main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*1], m6\n pxor m6, m6\n psubw m6, m7\n mova m7, m6\n jmp m(idct_8x8_internal).end2\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m7\n mova [rsp+gprsize*2+16*1], m3\n mova [rsp+gprsize*2+16*2], m4\n mova m7, [o(pd_2048)]\n ITX_MULSUB_2W 5, 2, 3, 4, 7, 1931, 3612 ;t3a, t2a\n ITX_MULSUB_2W 1, 6, 3, 4, 7, 3920, 1189 ;t7a, t6a\n paddsw m3, m2, m6 ;t2\n psubsw m2, m6 ;t6\n paddsw m4, m5, m1 ;t3\n psubsw m5, m1 ;t7\n ITX_MULSUB_2W 5, 2, 1, 6, 7, 3784, 1567 ;t6a, t7a\n\n mova m6, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m5\n mova m1, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*1], m2\n mova m5, [rsp+gprsize*2+16*0]\n mova [rsp+gprsize*2+16*0], m3\n ITX_MULSUB_2W 5, 0, 2, 3, 7, 401, 4076 ;t1a, t0a\n ITX_MULSUB_2W 1, 6, 2, 3, 7, 3166, 2598 ;t5a, t4a\n psubsw m2, m0, m6 ;t4\n paddsw m0, m6 ;t0\n paddsw m3, m5, m1 ;t1\n psubsw m5, m1 ;t5\n ITX_MULSUB_2W 2, 5, 1, 6, 7, 1567, 3784 ;t5a, t4a\n\n mova m7, [rsp+gprsize*2+16*0]\n paddsw m1, m3, m4 ;-out7\n psubsw m3, m4 ;t3\n mova [rsp+gprsize*2+16*0], m1\n psubsw m4, m0, m7 ;t2\n paddsw m0, m7 ;out0\n mova m6, [rsp+gprsize*2+16*2]\n mova m7, [rsp+gprsize*2+16*1]\n paddsw m1, m5, m6 ;-out1\n psubsw m5, m6 ;t6\n paddsw m6, m2, m7 ;out6\n psubsw m2, m7 ;t7\n ret\nALIGN function_align\n.main_pass1_end:\n mova [rsp+gprsize*2+16*1], m1\n mova [rsp+gprsize*2+16*2], m6\n punpckhwd m1, m4, m3\n punpcklwd m4, m3\n punpckhwd m7, m5, m2\n punpcklwd m5, m2\n mova m2, [o(pw_2896_2896)]\n mova m6, [o(pd_2048)]\n pmaddwd m3, m2, m7\n pmaddwd m2, m5\n paddd m3, m6\n paddd m2, m6\n psrad m3, 12\n psrad m2, 12\n packssdw m2, m3 ;out2\n mova m3, [o(pw_2896_m2896)]\n pmaddwd m7, m3\n pmaddwd m5, m3\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m5, m7 ;-out5\n mova m3, [o(pw_2896_2896)]\n pmaddwd m7, m3, m1\n pmaddwd m3, m4\n paddd m7, m6\n paddd m3, m6\n psrad m7, 12\n psrad m3, 12\n packssdw m3, m7 ;-out3\n mova m7, [o(pw_2896_m2896)]\n pmaddwd m1, m7\n pmaddwd m4, m7\n paddd m1, m6\n paddd m4, m6\n psrad m1, 12\n psrad m4, 12\n packssdw m4, m1 ;-out5\n mova m1, [rsp+gprsize*2+16*1]\n mova m6, [rsp+gprsize*2+16*2]\n ret\nALIGN function_align\n.main_pass2_end:\n paddsw m7, m4, m3 ;t2 + t3\n psubsw m4, m3 ;t2 - t3\n paddsw m3, m5, m2 ;t6 + t7\n psubsw m5, m2 ;t6 - t7\n mova m2, [o(pw_2896x8)]\n pmulhrsw m4, m2 ;out4\n pmulhrsw m5, m2 ;-out5\n pmulhrsw m7, m2 ;-out3\n pmulhrsw m2, m3 ;out2\n mova m3, m7\n ret\n\nINV_TXFM_8X8_FN flipadst, dct\nINV_TXFM_8X8_FN flipadst, adst\nINV_TXFM_8X8_FN flipadst, flipadst\nINV_TXFM_8X8_FN flipadst, identity\n\ncglobal iflipadst_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n\n.pass1:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass1_end\n\n.pass1_end:\n mova m7, [o(pw_m16384)]\n\n.pass1_end1:\n pmulhrsw m1, m7\n mova [rsp+gprsize+16*1], m1\n mova m1, m6\n mova m6, m2\n pmulhrsw m2, m5, m7\n mova m5, m6\n mova m6, m4\n pmulhrsw m4, m3, m7\n mova m3, m6\n mova m6, m0\n mova m0, m7\n pxor m7, m7\n psubw m7, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n REPX {pmulhrsw x, m7}, m1, m3, m5\n pmulhrsw m7, m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.pass2_main:\n call m(iadst_8x8_internal).main\n call m(iadst_8x8_internal).main_pass2_end\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m2, m4, m6\n mova [rsp+gprsize+16*2], m2\n mova m2, m0\n pxor m0, m0\n psubw m0, m7\n mova m7, m2\n pmulhrsw m1, m0\n pmulhrsw m2, m5, m0\n mova [rsp+gprsize+16*1], m1\n mova m5, m4\n mova m1, m6\n pmulhrsw m4, m3, m0\n pmulhrsw m0, [rsp+gprsize+16*0]\n mova m3, m5\n mova [rsp+gprsize+16*0], m7\n jmp m(idct_8x8_internal).end3\n\nINV_TXFM_8X8_FN identity, dct, 7\nINV_TXFM_8X8_FN identity, adst\nINV_TXFM_8X8_FN identity, flipadst\nINV_TXFM_8X8_FN identity, identity\n\ncglobal iidentity_8x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq, 16\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\nALIGN function_align\n.pass2:\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n\n.end:\n pmulhrsw m7, [o(pw_4096)]\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_4096)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+gprsize+16*2], m5\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).end3\n\n\n%macro INV_TXFM_4X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 4x16, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m0, [o(pw_2896x8)]\n mova m1, m0\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m1, [coeffq+16*1]\n mova m2, [o(pw_16384)]\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_2048)]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n pmulhrsw m2, m3, m0\n pmulhrsw m3, m1\n paddsw m0, m0\n paddsw m1, m1\n paddsw m0, m2\n paddsw m1, m3\n pmulhrsw m0, m4\n pmulhrsw m4, m1\n punpckhwd m2, m0, m0\n punpcklwd m0, m0\n punpckhwd m6, m4, m4\n punpcklwd m4, m4\n punpckhdq m1, m0, m0\n punpckldq m0, m0\n punpckhdq m3, m2, m2\n punpckldq m2, m2\n punpckhdq m5, m4, m4\n punpckldq m4, m4\n punpckhdq m7, m6, m6\n punpckldq m6, m6\n mova [coeffq+16*4], m4\n TAIL_CALL m(iadst_4x16_internal).end2\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n punpckldq m0, m1\n pmulhrsw m1, m0, [o(pw_1697x8)]\n pcmpeqw m2, m2\n pcmpeqw m2, m0\n pxor m0, m2\n pavgw m0, m1\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, [o(pw_2048)]\n punpcklqdq m0, m0\n pxor m1, m1\n REPX {mova [coeffq+32*x], m1}, 0, 1, 2, 3\n%elifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n pmulhrsw m0, [o(pw_16384)]\n pmulhrsw m0, m1\n pmulhrsw m0, [o(pw_2048)]\n%else ; adst_dct / flipadst_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n%ifidn %1, adst\n pmulhrsw m0, [o(iadst4_dconly1a)]\n%else ; flipadst\n pmulhrsw m0, [o(iadst4_dconly1b)]\n%endif\n mova m1, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, [o(pw_2896x8)]\n pmulhrsw m0, m1\n%endif\n.end:\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n lea dstq, [dstq+strideq*4]\n WRITE_4X4 0, 0, 1, 2, 3, 0, 1, 2, 3\n RET\n%endif\n%endmacro\n\nINV_TXFM_4X16_FN dct, dct, 0\nINV_TXFM_4X16_FN dct, identity, 15\nINV_TXFM_4X16_FN dct, adst\nINV_TXFM_4X16_FN dct, flipadst\n\ncglobal idct_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_4x8_internal).pass1)]\n\n.pass1:\n mova m0, [coeffq+16*1]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n push tx2q\n lea tx2q, [o(m(idct_4x16_internal).pass1_2)]\n jmp r3\n\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(m(idct_4x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n pop tx2q\n\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*7], m7\n jmp tx2q\n\n.pass2:\n call m(idct_16x4_internal).main\n\n.end:\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n\n.end1:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 3, 2\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 3, 2\n\n.end2:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\nINV_TXFM_4X16_FN adst, dct, 0\nINV_TXFM_4X16_FN adst, adst\nINV_TXFM_4X16_FN adst, flipadst\nINV_TXFM_4X16_FN adst, identity\n\ncglobal iadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpcklqdq m6, m5, m4 ;low: -out5 high: -out7\n punpckhqdq m4, m5 ;low: out8 high: out10\n punpcklqdq m5, m7, m2 ;low: out4 high: out6\n punpckhqdq m2, m7 ;low: -out9 high: -out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpckhqdq m1, m6, m0 ;low: -out13 high: -out15\n punpcklqdq m0, m6 ;low: out0 high: out2\n punpckhqdq m6, m3, m2 ;low: out12 high: out14\n punpcklqdq m2, m3 ;low: -out1 high: -out3\n\n mova m7, [o(pw_2048)]\n\n.end1:\n REPX {pmulhrsw x, m7}, m0, m5, m4, m6\n pxor m3, m3\n psubw m3, m7\n mova m7, [coeffq+16*4]\n REPX {pmulhrsw x, m3}, m2, m7, m1\n pmulhrsw m3, [coeffq+16*5]\n mova [coeffq+16*7], m5\n\n punpckhqdq m5, m4, m7 ;low: out10 high: out11\n punpcklqdq m4, m7 ;low: out8 high: out9\n punpckhqdq m7, m6, m1 ;low: out14 high: out15\n punpcklqdq m6, m1 ;low: out12 high: out13\n punpckhqdq m1, m0, m2 ;low: out2 high: out3\n punpcklqdq m0, m2 ;low: out0 high: out1\n mova [coeffq+16*4], m4\n mova m4, [coeffq+16*7]\n punpcklqdq m2, m4, m3 ;low: out4 high: out5\n punpckhqdq m4, m3 ;low: out6 high: out7\n mova m3, m4\n\n.end2:\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n mov r3, coeffq\n WRITE_4X8 0, 1, 2, 3\n\n mova m0, [r3+16*4]\n mova m1, [r3+16*5]\n mova m2, [r3+16*6]\n mova m3, m7\n lea dstq, [dstq+strideq*4]\n WRITE_4X8 0, 1, 2, 3\n\n.end3:\n pxor m7, m7\n REPX {mova [r3+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n ret\n\n\nINV_TXFM_4X16_FN flipadst, dct, 0\nINV_TXFM_4X16_FN flipadst, adst\nINV_TXFM_4X16_FN flipadst, flipadst\nINV_TXFM_4X16_FN flipadst, identity\n\ncglobal iflipadst_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_4x8_internal).pass1)]\n jmp m(idct_4x16_internal).pass1\n\n.pass2:\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass2_end\n\n punpckhqdq m6, m5, m4 ;low: out5 high: out7\n punpcklqdq m4, m5 ;low: -out8 high: -out10\n punpckhqdq m5, m7, m2 ;low: -out4 high: -out6\n punpcklqdq m2, m7 ;low: out9 high: out11\n mova [coeffq+16*4], m2\n mova [coeffq+16*5], m6\n mova m2, [coeffq+16*6]\n mova m6, [coeffq+16*7]\n punpcklqdq m1, m6, m0 ;low: out13 high: out15\n punpckhqdq m0, m6 ;low: -out0 high: -out2\n punpcklqdq m6, m3, m2 ;low: -out12 high: -out14\n punpckhqdq m2, m3 ;low: out1 high: out3\n\n mova m7, [o(pw_m2048)]\n jmp m(iadst_4x16_internal).end1\n\n\nINV_TXFM_4X16_FN identity, dct, 3\nINV_TXFM_4X16_FN identity, adst\nINV_TXFM_4X16_FN identity, flipadst\nINV_TXFM_4X16_FN identity, identity\n\n%macro IDTX16 3-4 ; src/dst, tmp, pw_1697x16, [pw_16394]\n pmulhrsw m%2, m%3, m%1\n%if %0 == 4 ; if downshifting by 1\n pmulhrsw m%2, m%4\n%else\n paddsw m%1, m%1\n%endif\n paddsw m%1, m%2\n%endmacro\n\ncglobal iidentity_4x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m0, [coeffq+16*1]\n mova m6, [o(pw_1697x8)]\n mova m1, [coeffq+16*3]\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*7]\n pcmpeqw m7, m7\n mov r3, tx2q\n lea tx2q, [o(.pass1_2)]\n.pass1:\n pmulhrsw m4, m6, m0\n pmulhrsw m5, m6, m1\n pavgw m4, m0\n pcmpeqw m0, m7\n pavgw m5, m1\n pcmpeqw m1, m7\n pandn m0, m4\n pmulhrsw m4, m6, m2\n pandn m1, m5\n pmulhrsw m5, m6, m3\n pavgw m4, m2\n pcmpeqw m2, m7\n pavgw m5, m3\n pcmpeqw m3, m7\n pandn m2, m4\n pandn m3, m5\n jmp m(iadst_4x8_internal).pass1_end\n.pass1_2:\n mova [coeffq+16*1], m0\n mova [coeffq+16*3], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*4]\n mova m3, [coeffq+16*6]\n lea tx2q, [o(.pass1_end)]\n jmp .pass1\n.pass1_end:\n mova m4, [coeffq+16*1]\n mova m5, [coeffq+16*3]\n mova m6, [coeffq+16*5]\n jmp r3\n.pass2:\n mova m7, [o(pw_1697x16)]\n mova [coeffq+16*6], m6\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [coeffq+16*7]\n IDTX16 6, 7, 7\n mova [coeffq+16*7], m6\n mova m6, [coeffq+16*6]\n pmulhrsw m7, m6, [o(pw_1697x16)]\n paddsw m6, m6\n paddsw m6, m7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*7]\n mova [coeffq+16*4], m4\n jmp m(iadst_4x16_internal).end2\n\n\n%macro INV_TXFM_16X4_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x4, 8\n%if %3 >= 0\n%ifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m3, [coeffq]\n mova m0, [o(pw_16384)]\n pmulhrsw m3, m0\n psrlw m0, 3 ; pw_2048\n pmulhrsw m1, m3, [o(pw_1697x8)]\n paddsw m3, m1\n pmulhrsw m3, m0\n punpcklwd m3, m3\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_16384)]\n mova m6, [o(pw_2896x8)]\n mov r3d, 2\n psrlw m7, m5, 3 ; pw_2048\n.main_loop:\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n punpckhwd m2, m0, m1\n punpcklwd m0, m1\n punpcklwd m0, m2\n mova m1, [coeffq+16*2]\n mova m2, [coeffq+16*3]\n punpckhwd m3, m1, m2\n punpcklwd m1, m2\n punpcklwd m1, m3\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n pmulhrsw m1, m5\n paddsw m0, m1\n pmulhrsw m0, m6\n pmulhrsw m0, m7\n.end:\n pxor m3, m3\n mova [coeffq+16*0], m3\n mova [coeffq+16*1], m3\n mova [coeffq+16*2], m3\n mova [coeffq+16*3], m3\n add coeffq, 16*4\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%else\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n%ifidn %2, dct\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n mov r2d, 2\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x4).end)]\n.dconly:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n.dconly_loop:\n mova m1, [dstq]\n mova m3, [dstq+strideq]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq], m1\n mova [dstq+strideq], m3\n lea dstq, [dstq+strideq*2]\n dec r2d\n jg .dconly_loop\n jmp tx2q\n.end:\n RET\n%else ; adst / flipadst\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov [coeffq], eobd\n pmulhrsw m2, m0, [o(iadst4_dconly2b)]\n pmulhrsw m0, [o(iadst4_dconly2a)]\n mova m1, [o(pw_2048)]\n pmulhrsw m0, m1\n pmulhrsw m2, m1\n%ifidn %2, adst\n punpckhqdq m1, m0, m0\n punpcklqdq m0, m0\n punpckhqdq m3, m2, m2\n punpcklqdq m2, m2\n%else ; flipadst\n mova m3, m0\n punpckhqdq m0, m2, m2\n punpcklqdq m1, m2, m2\n punpckhqdq m2, m3, m3\n punpcklqdq m3, m3\n%endif\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end3\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end3\n%endif\n%endif\n%endif\n%endmacro\n\n%macro LOAD_7ROWS 2 ;src, stride\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n mova m4, [%1+%2*4]\n mova m5, [%1+%2*5]\n mova m6, [%1+%2*6]\n%endmacro\n\n%macro SAVE_7ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n%endmacro\n\n%macro IDCT16_1D_PACKED_ODDHALF 7 ;src[1-4], tmp[1-3]\n punpckhwd m%5, m%4, m%1 ;packed in13 in3\n punpcklwd m%1, m%4 ;packed in1 in15\n punpcklwd m%4, m%3, m%2 ;packed in9 in7\n punpckhwd m%2, m%3 ;packed in5 in11\n mova m%7, [o(pd_2048)]\n ITX_MUL2X_PACK %1, %6, %7, 401, 4076, 1 ;low: t8a high: t15a\n ITX_MUL2X_PACK %4, %6, %7, 3166, 2598, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %2, %6, %7, 1931, 3612, 1 ;low: t10a high: t13a\n ITX_MUL2X_PACK %5, %6, %7, 3920, 1189, 1 ;low: t11a high: t12a\n psubsw m%6, m%1, m%4 ;low: t9 high: t14\n paddsw m%1, m%4 ;low: t8 high: t15\n psubsw m%3, m%5, m%2 ;low: t10 high: t13\n paddsw m%5, m%2 ;low: t11 high: t12\n mova m%2, [o(deint_shuf2)]\n pshufb m%6, m%2\n pshufb m%3, [o(deint_shuf1)]\n pxor m%4, m%4\n psubw m%4, m%3 ;packed -t10 -t13\n ITX_MUL2X_PACK %6, %3, %7, 1567, 3784, 1 ;low: t9a high: t14a\n ITX_MUL2X_PACK %4, %3, %7, 3784, 1567 ;low: t10a high: t13a\n psubsw m%3, m%1, m%5 ;low: t11a high: t12a\n paddsw m%1, m%5 ;low: t8a high: t15a\n psubsw m%5, m%6, m%4 ;low: t10 high: t13\n paddsw m%6, m%4 ;low: t9 high: t14\n pshufb m%3, m%2\n pshufb m%5, m%2\n ITX_MUL2X_PACK %3, %2, %7, 2896, 2896, 4 ;t12, t11\n ITX_MUL2X_PACK %5, %4, %7, 2896, 2896, 4 ;t13a, t10a\n packssdw m%2, m%4 ;low: t11 high: t10a\n packssdw m%3, m%5 ;low: t12 high: t13a\n punpckhqdq m%4, m%1, m%6 ;low: t15a high: t14\n punpcklqdq m%1, m%6 ;low: t8a high: t9\n%endmacro\n\nINV_TXFM_16X4_FN dct, dct, 0\nINV_TXFM_16X4_FN dct, adst, 0\nINV_TXFM_16X4_FN dct, flipadst, 0\nINV_TXFM_16X4_FN dct, identity, 3\n\ncglobal idct_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n\n.pass1_end:\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpcklwd m2, m1, m3 ;packed out3, out7\n punpckhwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpcklwd m6, m5, m7 ;packed out11, out15\n punpckhwd m5, m7 ;packed out10, out14\n\n.pass1_end2:\n mova m7, [o(pw_16384)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [coeffq+16*6]\n mova [coeffq+16*6], m7\n\n.pass1_end3:\n punpckhwd m7, m3, m6 ;packed 9, 11, 13, 15 high\n punpcklwd m3, m6 ;packed 9, 10, 13, 15 low\n punpckhwd m6, m4, m5 ;packed 8, 10, 12, 14 high\n punpcklwd m4, m5 ;packed 8, 10, 12, 14 low\n punpckhwd m5, m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(1)\n punpcklwd m4, m3 ;8, 9, 10, 11, 12, 13, 14, 15(0)\n punpckhwd m3, m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(3)\n punpcklwd m6, m7 ;8, 9, 10, 11, 12, 13, 14, 15(2)\n mova [coeffq+16*7], m3\n mova m3, [coeffq+16*6]\n punpckhwd m7, m3, m2 ;packed 1, 3, 5, 7 high\n punpcklwd m3, m2 ;packed 1, 3, 5, 7 low\n punpckhwd m2, m0, m1 ;packed 0, 2, 4, 6 high\n punpcklwd m0, m1 ;packed 0, 2, 4, 6 low\n punpckhwd m1, m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(1)\n punpcklwd m0, m3 ;0, 1, 2, 3, 4, 5, 6, 7(0)\n punpckhwd m3, m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(3)\n punpcklwd m2, m7 ;0, 1, 2, 3, 4, 5, 6, 7(2)\n jmp tx2q\n\n.pass2:\n lea tx2q, [o(m(idct_8x4_internal).pass2)]\n\n.pass2_end:\n mova [coeffq+16*4], m4\n mova [coeffq+16*5], m5\n mova [coeffq+16*6], m6\n lea r3, [dstq+8]\n call tx2q\n\n add coeffq, 16*4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mov dstq, r3\n jmp tx2q\n\nALIGN function_align\n.main:\n punpckhqdq m7, m0, m1 ;low:in1 high:in3\n punpcklqdq m0, m1\n punpcklqdq m1, m2, m3\n punpckhqdq m3, m2 ;low:in7 high:in5\n mova [coeffq+16*4], m7\n mova [coeffq+16*5], m3\n mova m7, [coeffq+16*7]\n punpcklqdq m2, m4, m5\n punpckhqdq m4, m5 ;low:in9 high:in11\n punpcklqdq m3, m6, m7\n punpckhqdq m7, m6 ;low:in15 high:in13\n mova [coeffq+16*6], m4\n IDCT8_1D_PACKED\n mova m6, [coeffq+16*4]\n mova m4, [coeffq+16*5]\n mova m5, [coeffq+16*6]\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m2\n mova [coeffq+16*6], m3\n\n IDCT16_1D_PACKED_ODDHALF 6, 4, 5, 7, 1, 2, 3\n\n mova m1, [coeffq+16*4]\n psubsw m3, m0, m7 ;low:out15 high:out14\n paddsw m0, m7 ;low:out0 high:out1\n psubsw m7, m1, m5 ;low:out12 high:out13\n paddsw m1, m5 ;low:out3 high:out2\n mova [coeffq+16*7], m3\n mova m2, [coeffq+16*5]\n mova m3, [coeffq+16*6]\n psubsw m5, m2, m4 ;low:out11 high:out10\n paddsw m2, m4 ;low:out4 high:out5\n psubsw m4, m3, m6 ;low:out8 high:out9\n paddsw m3, m6 ;low:out7 high:out6\n mova m6, m7\n ret\n\nINV_TXFM_16X4_FN adst, dct\nINV_TXFM_16X4_FN adst, adst\nINV_TXFM_16X4_FN adst, flipadst\nINV_TXFM_16X4_FN adst, identity\n\ncglobal iadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call .main\n call .main_pass1_end\n\n punpckhwd m6, m7, m0 ;packed -out11, -out15\n punpcklwd m0, m7 ;packed out0, out4\n punpcklwd m7, m3, m4 ;packed -out3, -out7\n punpckhwd m4, m3 ;packed out8, out12\n mova m1, [coeffq+16*6]\n punpcklwd m3, m1, m5 ;packed -out1, -out5\n punpckhwd m5, m1 ;packed out10, out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpckhwd m3, m2, m1 ;packed -out9, -out13\n punpcklwd m1, m2 ;packed out2, out6\n\n mova m7, [o(pw_16384)]\n\n.pass1_end:\n REPX {pmulhrsw x, m7}, m0, m1, m4, m5\n pxor m2, m2\n psubw m2, m7\n mova m7, [coeffq+16*6]\n REPX {pmulhrsw x, m2}, m7, m3, m6\n pmulhrsw m2, [coeffq+16*7]\n mova [coeffq+16*6], m7\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\nALIGN function_align\n.main:\n mova [coeffq+16*6], m0\n pshufd m0, m1, q1032\n pshufd m2, m2, q1032\n punpckhwd m1, m6, m0 ;packed in13, in2\n punpcklwd m0, m6 ;packed in3, in12\n punpckhwd m7, m5, m2 ;packed in11, in4\n punpcklwd m2, m5 ;packed in5, in10\n mova m6, [o(pd_2048)]\n ITX_MUL2X_PACK 1, 5, 6, 995, 3973 ;low:t2 high:t3\n ITX_MUL2X_PACK 7, 5, 6, 1751, 3703 ;low:t4 high:t5\n ITX_MUL2X_PACK 2, 5, 6, 3513, 2106 ;low:t10 high:t11\n ITX_MUL2X_PACK 0, 5, 6, 3857, 1380 ;low:t12 high:t13\n psubsw m5, m1, m2 ;low:t10a high:t11a\n paddsw m1, m2 ;low:t2a high:t3a\n psubsw m2, m7, m0 ;low:t12a high:t13a\n paddsw m7, m0 ;low:t4a high:t5a\n punpcklqdq m0, m5\n punpckhwd m0, m5 ;packed t10a, t11a\n punpcklqdq m5, m2\n punpckhwd m2, m5 ;packed t13a, t12a\n ITX_MUL2X_PACK 0, 5, 6, 3406, 2276 ;low:t10 high:t11\n ITX_MUL2X_PACK 2, 5, 6, 4017, 799, 1 ;low:t12 high:t13\n mova [coeffq+16*4], m1\n mova [coeffq+16*5], m7\n mova m1, [coeffq+16*6]\n mova m7, [coeffq+16*7]\n pshufd m1, m1, q1032\n pshufd m3, m3, q1032\n punpckhwd m5, m7, m1 ;packed in15, in0\n punpcklwd m1, m7 ;packed in1, in14\n punpckhwd m7, m4, m3 ;packed in9, in6\n punpcklwd m3, m4 ;packed in7, in8\n ITX_MUL2X_PACK 5, 4, 6, 201, 4091 ;low:t0 high:t1\n ITX_MUL2X_PACK 7, 4, 6, 2440, 3290 ;low:t6 high:t7\n ITX_MUL2X_PACK 3, 4, 6, 3035, 2751 ;low:t8 high:t9\n ITX_MUL2X_PACK 1, 4, 6, 4052, 601 ;low:t14 high:t15\n psubsw m4, m5, m3 ;low:t8a high:t9a\n paddsw m5, m3 ;low:t0a high:t1a\n psubsw m3, m7, m1 ;low:t14a high:t15a\n paddsw m7, m1 ;low:t6a high:t7a\n punpcklqdq m1, m4\n punpckhwd m1, m4 ;packed t8a, t9a\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t15a, t14a\n ITX_MUL2X_PACK 1, 4, 6, 799, 4017 ;low:t8 high:t9\n ITX_MUL2X_PACK 3, 4, 6, 2276, 3406, 1 ;low:t14 high:t15\n paddsw m4, m1, m2 ;low:t12a high:t13a\n psubsw m1, m2 ;low:t8a high:t9a\n psubsw m2, m0, m3 ;low:t14a high:t15a\n paddsw m0, m3 ;low:t10a high:t11a\n punpcklqdq m3, m1\n punpckhwd m3, m1 ;packed t12a, t13a\n punpcklqdq m1, m2\n punpckhwd m2, m1 ;packed t15a, t14a\n ITX_MUL2X_PACK 3, 1, 6, 1567, 3784 ;low:t12 high:t13\n ITX_MUL2X_PACK 2, 1, 6, 3784, 1567, 1 ;low:t14 high:t15\n psubsw m1, m3, m2 ;low:t14a high:t15a\n paddsw m3, m2 ;low:out2 high:-out13\n psubsw m2, m4, m0 ;low:t10 high:t11\n paddsw m0, m4 ;low:-out1 high:out14\n mova [coeffq+16*6], m0\n mova [coeffq+16*7], m3\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n psubsw m4, m5, m3 ;low:t4 high:t5\n paddsw m5, m3 ;low:t0 high:t1\n psubsw m3, m0, m7 ;low:t6 high:t7\n paddsw m0, m7 ;low:t2 high:t3\n punpcklqdq m7, m4\n punpckhwd m7, m4 ;packed t4, t5\n punpcklqdq m4, m3\n punpckhwd m3, m4 ;packed t7, t6\n ITX_MUL2X_PACK 7, 4, 6, 1567, 3784 ;low:t4a high:t5a\n ITX_MUL2X_PACK 3, 4, 6, 3784, 1567, 1 ;low:t6a high:t7a\n psubsw m4, m5, m0 ;low:t2a high:t3a\n paddsw m0, m5 ;low:out0 high:-out15\n psubsw m5, m7, m3 ;low:t6 high:t7\n paddsw m3, m7 ;low:-out3 high:out12\n ret\nALIGN function_align\n.main_pass1_end:\n mova m7, [o(deint_shuf1)]\n mova [coeffq+16*4], m0\n mova [coeffq+16*5], m3\n mova m0, [o(pw_2896_m2896)]\n mova m3, [o(pw_2896_2896)]\n pshufb m1, m7 ;t14a t15a\n pshufb m2, m7 ;t10 t11\n pshufb m4, m7 ;t2a t3a\n pshufb m5, m7 ;t6 t7\n pmaddwd m7, m0, m2\n pmaddwd m2, m3\n paddd m7, m6\n paddd m2, m6\n psrad m7, 12\n psrad m2, 12\n packssdw m2, m7 ;low:out6 high:-out9\n pmaddwd m7, m0, m4\n pmaddwd m4, m3\n paddd m7, m6\n paddd m4, m6\n psrad m7, 12\n psrad m4, 12\n packssdw m4, m7 ;low:-out7 high:out8\n pmaddwd m7, m3, m5\n pmaddwd m5, m0\n paddd m7, m6\n paddd m5, m6\n psrad m7, 12\n psrad m5, 12\n packssdw m7, m5 ;low:out4 high:-out11\n pmaddwd m5, m3, m1\n pmaddwd m1, m0\n paddd m5, m6\n paddd m1, m6\n psrad m5, 12\n psrad m1, 12\n packssdw m5, m1 ;low:-out5 high:out10\n mova m0, [coeffq+16*4]\n mova m3, [coeffq+16*5]\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n punpckhqdq m6, m2, m1 ;low:t11 high:t15a\n punpcklqdq m2, m1 ;low:t10 high:t14a\n psubsw m1, m2, m6\n paddsw m2, m6\n punpckhqdq m6, m4, m5 ;low:t3a high:t7\n punpcklqdq m4, m5 ;low:t2a high:t6\n psubsw m5, m4, m6\n paddsw m4, m6\n pmulhrsw m1, m7 ;low:-out9 high:out10\n pmulhrsw m2, m7 ;low:out6 high:-out5\n pmulhrsw m5, m7 ;low:out8 high:-out11\n pmulhrsw m4, m7 ;low:-out7 high:out4\n punpckhqdq m7, m4, m5 ;low:out4 high:-out11\n punpcklqdq m4, m5 ;low:-out7 high:out8\n punpckhqdq m5, m2, m1 ;low:-out5 high:out10\n punpcklqdq m2, m1 ;low:out6 high:-out9\n ret\n\n\nINV_TXFM_16X4_FN flipadst, dct\nINV_TXFM_16X4_FN flipadst, adst\nINV_TXFM_16X4_FN flipadst, flipadst\nINV_TXFM_16X4_FN flipadst, identity\n\ncglobal iflipadst_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_7ROWS coeffq, 16\n call m(iadst_16x4_internal).main\n call m(iadst_16x4_internal).main_pass1_end\n\n punpcklwd m6, m7, m0 ;packed out11, out15\n punpckhwd m0, m7 ;packed -out0, -out4\n punpckhwd m7, m3, m4 ;packed out3, out7\n punpcklwd m4, m3 ;packed -out8, -out12\n mova m1, [coeffq+16*6]\n punpckhwd m3, m1, m5 ;packed out1, out5\n punpcklwd m5, m1 ;packed -out10, -out14\n mova m1, [coeffq+16*7]\n mova [coeffq+16*6], m3\n mova [coeffq+16*7], m7\n punpcklwd m3, m2, m1 ;packed out9, out13\n punpckhwd m1, m2 ;packed -out2, -out6\n\n mova m7, [o(pw_m16384)]\n jmp m(iadst_16x4_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\nINV_TXFM_16X4_FN identity, dct, 15\nINV_TXFM_16X4_FN identity, adst\nINV_TXFM_16X4_FN identity, flipadst\nINV_TXFM_16X4_FN identity, identity\n\ncglobal iidentity_16x4_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m1, [coeffq+16*6]\n mova m0, [coeffq+16*5]\n mova m2, [coeffq+16*7]\n mova m6, [o(pw_1697x16)]\n mova m7, [o(pw_16384)]\n pmulhrsw m4, m6, m1\n pmulhrsw m3, m6, m0\n pmulhrsw m5, m6, m2\n pmulhrsw m4, m7\n pmulhrsw m3, m7\n pmulhrsw m5, m7\n paddsw m1, m4\n paddsw m0, m3\n paddsw m5, m2\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n mova m4, [coeffq+16*4]\n mova [coeffq+16*6], m1\n mova [coeffq+16*5], m0\n mova [coeffq+16*7], m5\n pmulhrsw m0, m6, m2\n pmulhrsw m1, m6, m3\n pmulhrsw m5, m6, m4\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n pmulhrsw m5, m7\n paddsw m2, m0\n paddsw m3, m1\n paddsw m4, m5\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n pmulhrsw m5, m6, m0\n pmulhrsw m6, m1\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n paddsw m0, m5\n paddsw m1, m6\n mova m6, [coeffq+16*6]\n mova m5, [coeffq+16*5]\n punpckhwd m7, m0, m2 ;packed out1, out5\n punpcklwd m0, m2 ;packed out0, out4\n punpckhwd m2, m1, m3 ;packed out3, out7\n punpcklwd m1, m3 ;packed out2, out6\n mova [coeffq+16*6], m7\n mova m7, [coeffq+16*7]\n punpckhwd m3, m4, m6 ;packed out9, out13\n punpcklwd m4, m6 ;packed out8, out12\n punpckhwd m6, m5, m7 ;packed out11, out15\n punpcklwd m5, m7 ;packed out10, out14\n jmp m(idct_16x4_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x4_internal).pass2)]\n jmp m(idct_16x4_internal).pass2_end\n\n\n%macro SAVE_8ROWS 2 ;src, stride\n mova [%1+%2*0], m0\n mova [%1+%2*1], m1\n mova [%1+%2*2], m2\n mova [%1+%2*3], m3\n mova [%1+%2*4], m4\n mova [%1+%2*5], m5\n mova [%1+%2*6], m6\n mova [%1+%2*7], m7\n%endmacro\n\n%macro INV_TXFM_8X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 8x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n pshuflw m0, [coeffq], q0000\n punpcklwd m0, m0\n mova m1, [o(pw_2896x8)]\n pmulhrsw m0, m1\n mova m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n psrlw m2, 3 ; pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mov r3d, 2\n.loop:\n mova m0, [o(pw_2896x8)]\n pmulhrsw m7, m0, [coeffq]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 3 ; pw_2048\n pmulhrsw m0, m7, [o(pw_1697x16)]\n paddsw m7, m7\n paddsw m7, m0\n pmulhrsw m7, m1\n punpcklwd m0, m7, m7\n punpckhwd m7, m7\n pshufd m3, m0, q3333\n pshufd m2, m0, q2222\n pshufd m1, m0, q1111\n pshufd m0, m0, q0000\n call m(iadst_8x4_internal).end3\n pshufd m3, m7, q3333\n pshufd m2, m7, q2222\n pshufd m1, m7, q1111\n pshufd m0, m7, q0000\n lea dstq, [dstq+strideq*2]\n call m(iadst_8x4_internal).end3\n\n add coeffq, 16\n lea dstq, [dstq+strideq*2]\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n add coeffq, 32*4\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m3, [coeffq+32*2]\n punpcklwd m3, [coeffq+32*3]\n mova m4, [o(pw_2896x8)]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m0, m2\n punpckldq m1, m3\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m4\n pmulhrsw m0, [o(pw_2048)]\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n lea tx2q, [o(m(inv_txfm_add_identity_dct_8x16).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n RET\n%endif\n%endmacro\n\nINV_TXFM_8X16_FN dct, dct, 0\nINV_TXFM_8X16_FN dct, identity, 15\nINV_TXFM_8X16_FN dct, adst\nINV_TXFM_8X16_FN dct, flipadst\n\ncglobal idct_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(idct_8x8_internal).pass1)]\n\n.pass1:\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov [rsp+gprsize+16*11], tx2q\n lea tx2q, [o(m(idct_8x16_internal).pass1_end)]\n jmp r3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, [rsp+gprsize+16*11]\n jmp r3\n\n.pass2:\n lea tx2q, [o(m(idct_8x16_internal).end)]\n\n.pass2_pre:\n mova [coeffq+16*2 ], m1\n mova [coeffq+16*6 ], m3\n mova [coeffq+16*10], m5\n mova [coeffq+16*14], m7\n mova m1, m2\n mova m2, m4\n mova m3, m6\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n\n.pass2_main:\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+16*2 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*10]\n mova m3, [coeffq+16*14]\n mova m4, [coeffq+16*3 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*15]\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n ret\n\nINV_TXFM_8X16_FN adst, dct\nINV_TXFM_8X16_FN adst, adst\nINV_TXFM_8X16_FN adst, flipadst\nINV_TXFM_8X16_FN adst, identity\n\ncglobal iadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n\n mov r3, dstq\n lea dstq, [dstq+strideq*8]\n jmp m(iadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN flipadst, dct\nINV_TXFM_8X16_FN flipadst, adst\nINV_TXFM_8X16_FN flipadst, flipadst\nINV_TXFM_8X16_FN flipadst, identity\n\ncglobal iflipadst_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n lea r3, [o(m(iflipadst_8x8_internal).pass1)]\n jmp m(idct_8x16_internal).pass1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_8x16_internal).end)]\n lea r3, [dstq+strideq*8]\n\n.pass2_pre:\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n mova m0, m2\n mova m1, m3\n mova m2, m4\n mova m3, m5\n\n.pass2_main:\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*3 ]\n mova m6, [coeffq+16*13]\n mova m7, [coeffq+16*15]\n mova [rsp+gprsize+16*3], m4\n mova [rsp+gprsize+16*4], m5\n mova [rsp+gprsize+16*9], m6\n mova [rsp+gprsize+32*5], m7\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*7 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*11]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass2_end\n jmp m(iflipadst_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).end\n\n\nINV_TXFM_8X16_FN identity, dct, 7\nINV_TXFM_8X16_FN identity, adst\nINV_TXFM_8X16_FN identity, flipadst\nINV_TXFM_8X16_FN identity, identity\n\ncglobal iidentity_8x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 32, 1\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_8x16_internal).pass1_end)]\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32, 1\n mov tx2q, r3\n mova [rsp+gprsize+16*1], m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass2:\n lea tx2q, [o(m(iidentity_8x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m6\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 6, 7}, 0, 1, 2, 3, 4, 5\n mova m6, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*2], m5\n IDTX16 6, 5, 7\n mova m5, [rsp+gprsize+16*0]\n IDTX16 5, 7, 7\n mova m7, [o(pw_2048)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n pmulhrsw m7, [rsp+gprsize+16*2]\n mova [rsp+gprsize+16*0], m5\n mova [rsp+gprsize+16*1], m6\n mova [rsp+gprsize+16*2], m7\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\n%macro INV_TXFM_16X8_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x8, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 4\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x8).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m7, [coeffq]\n mova m0, [o(pw_2896x8)]\n mova m1, [o(pw_16384)]\n pxor m2, m2\n mova [coeffq], m2\n pmulhrsw m7, m0\n pmulhrsw m7, m0\n pmulhrsw m7, m1\n psrlw m1, 2 ; pw_4096\n pmulhrsw m7, m1\n punpcklwd m3, m7, m7\n punpckhwd m7, m7\n pshufd m0, m3, q0000\n pshufd m1, m3, q1111\n pshufd m2, m3, q2222\n pshufd m3, m3, q3333\n lea r3, [dstq+strideq*4]\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n call m(iadst_8x4_internal).end2\n mov dstq, r3\n add coeffq, 16*4\n pshufd m0, m7, q0000\n pshufd m1, m7, q1111\n pshufd m2, m7, q2222\n pshufd m3, m7, q3333\n lea tx2q, [dstq+8]\n call m(iadst_8x4_internal).end2\n add coeffq, 16*4\n mov dstq, tx2q\n TAIL_CALL m(iadst_8x4_internal).end2\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_2896x8)]\n mova m5, [o(pw_1697x16)]\n mova m6, [o(pw_16384)]\n psrlw m7, m6, 3 ; pw_2048\n mov r3d, 2\n.main_loop:\n mova m0, [coeffq+16*0]\n punpcklwd m0, [coeffq+16*1]\n mova m1, [coeffq+16*2]\n punpcklwd m1, [coeffq+16*3]\n punpckldq m0, m1\n mova m1, [coeffq+16*4]\n punpcklwd m1, [coeffq+16*5]\n mova m2, [coeffq+16*6]\n punpcklwd m2, [coeffq+16*7]\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m0, m4\n pmulhrsw m1, m5, m0\n pmulhrsw m1, m6\n paddsw m0, m1\n pmulhrsw m0, m4\n pmulhrsw m0, m7\n.end:\n pxor m1, m1\n REPX {mova [coeffq+16*x], m1}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16*8\n lea tx2q, [dstq+8]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n lea dstq, [dstq+strideq*2]\n WRITE_8X4 0, 0, 0, 0, 1, 2, 3\n mov dstq, tx2q\n dec r3d\n jg .main_loop\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X8_FN dct, dct, 0\nINV_TXFM_16X8_FN dct, identity, 7\nINV_TXFM_16X8_FN dct, adst\nINV_TXFM_16X8_FN dct, flipadst\n\ncglobal idct_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*0, 32, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*1, 32, 1\n call .main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x8_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(idct_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).pass2_main\n\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n mova [rsp+gprsize*2+32*5], m5\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 0, 7, 2, 5, 6, 401, 4076 ;t8a, t15a\n ITX_MULSUB_2W 4, 3, 2, 5, 6, 3166, 2598 ;t9a, t14a\n psubsw m2, m0, m4 ;t9\n paddsw m0, m4 ;t8\n psubsw m4, m7, m3 ;t14\n paddsw m7, m3 ;t15\n ITX_MULSUB_2W 4, 2, 3, 5, 6, 1567, 3784 ;t9a, t14a\n mova m3, [rsp+gprsize*2+16*1]\n mova m5, [rsp+gprsize*2+32*5]\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+32*5], m4\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*2], m7\n ITX_MULSUB_2W 3, 5, 7, 4, 6, 1931, 3612 ;t10a, t13a\n ITX_MULSUB_2W 2, 1, 7, 4, 6, 3920, 1189 ;t11a, t12a\n pxor m4, m4\n psubsw m7, m2, m3 ;t10\n paddsw m2, m3 ;t11\n psubsw m3, m1, m5 ;t13\n paddsw m1, m5 ;t12\n psubw m4, m7\n ITX_MULSUB_2W 4, 3, 7, 5, 6, 1567, 3784 ;t10a, t13a\n mova m7, [rsp+gprsize*2+32*5]\n psubsw m6, m0, m2 ;t11a\n paddsw m0, m2 ;t8a\n paddsw m2, m7, m4 ;t9\n psubsw m7, m4 ;t10\n mova m5, [rsp+gprsize*2+16*0]\n psubsw m4, m5, m0 ;out8\n paddsw m0, m5 ;out7\n mova [rsp+gprsize*2+32*5], m0\n mova m5, [rsp+gprsize*2+16*9]\n psubsw m0, m5, m2 ;out9\n paddsw m2, m5 ;out6\n mova [rsp+gprsize*2+16*0], m0\n mova [rsp+gprsize*2+16*9], m2\n mova m0, [rsp+gprsize*2+16*1]\n mova m2, [rsp+gprsize*2+16*2]\n mova [rsp+gprsize*2+16*1], m4\n psubsw m5, m0, m3 ;t13\n paddsw m0, m3 ;t14\n mova m3, [o(pd_2048)]\n psubsw m4, m2, m1 ;t12a\n paddsw m1, m2 ;t15a\n mova [rsp+gprsize*2+16*2], m1\n ITX_MULSUB_2W 5, 7, 1, 2, 3, 2896, 2896 ;t10a, t13a\n ITX_MULSUB_2W 4, 6, 1, 2, 3, 2896, 2896 ;t11, t12\n mova m3, [rsp+gprsize*2+16*8]\n psubsw m2, m3, m5 ;out10\n paddsw m3, m5 ;out5\n mova m5, [rsp+gprsize*2+16*7]\n mova [rsp+gprsize*2+16*8], m3\n psubsw m3, m5, m4 ;out11\n paddsw m5, m4 ;out4\n mova m4, [rsp+gprsize*2+16*6]\n mova [rsp+gprsize*2+16*7], m5\n paddsw m5, m4, m6 ;out3\n psubsw m4, m6 ;out12\n mova m6, [rsp+gprsize*2+16*5]\n mova [rsp+gprsize*2+16*6], m5\n psubsw m5, m6, m7 ;out13\n paddsw m6, m7 ;out2\n mova m7, [rsp+gprsize*2+16*4]\n mova [rsp+gprsize*2+16*5], m6\n psubsw m6, m7, m0 ;out14\n paddsw m7, m0 ;out1\n mova m1, [rsp+gprsize*2+16*2]\n mova m0, [rsp+gprsize*2+16*3]\n mova [rsp+gprsize*2+16*4], m7\n psubsw m7, m0, m1 ;out15\n paddsw m0, m1 ;out0\n mova [rsp+gprsize*2+16*3], m0\n mova m1, [rsp+gprsize*2+16*0]\n mova m0, [rsp+gprsize*2+16*1]\n mova [rsp+gprsize*2+16*0], m7\n ret\n\nINV_TXFM_16X8_FN adst, dct\nINV_TXFM_16X8_FN adst, adst\nINV_TXFM_16X8_FN adst, flipadst\nINV_TXFM_16X8_FN adst, identity\n\ncglobal iadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call .main\n call .main_pass1_end\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x8_internal).pass1_end)]\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iadst_8x8_internal).pass2_main\n\nALIGN function_align\n.main:\n mova [rsp+gprsize*2+16*0], m1\n mova [rsp+gprsize*2+16*1], m2\n mova [rsp+gprsize*2+16*2], m6\n\n mova m6, [o(pd_2048)]\n ITX_MULSUB_2W 7, 0, 1, 2, 6, 995, 3973 ;t3, t2\n ITX_MULSUB_2W 3, 4, 1, 2, 6, 3513, 2106 ;t11, t10\n psubsw m1, m0, m4 ;t10a\n paddsw m0, m4 ;t2a\n psubsw m4, m7, m3 ;t11a\n paddsw m3, m7 ;t3a\n ITX_MULSUB_2W 1, 4, 7, 2, 6, 3406, 2276 ;t11, t10\n mova m2, [rsp+gprsize*2+16*0] ;in3\n mova m7, [rsp+gprsize*2+16*1] ;in4\n mova [rsp+gprsize*2+16*0], m1 ;t11\n mova [rsp+gprsize*2+16*1], m4 ;t10\n mova m1, [rsp+gprsize*2+16*2] ;in12\n mova [rsp+gprsize*2+16*2], m0 ;t2a\n ITX_MULSUB_2W 5, 7, 0, 4, 6, 1751, 3703 ;t5, t4\n ITX_MULSUB_2W 2, 1, 0, 4, 6, 3857, 1380 ;t13, t12\n psubsw m0, m7, m1 ;t12a\n paddsw m1, m7 ;t4a\n psubsw m4, m5, m2 ;t13a\n paddsw m5, m2 ;t5a\n ITX_MULSUB_2W 4, 0, 7, 2, 6, 4017, 799 ;t12, t13\n mova m2, [rsp+gprsize*2+16*8] ;in1\n mova m7, [rsp+gprsize*2+16*9] ;in14\n mova [rsp+gprsize*2+16*8], m4 ;t12\n mova [rsp+gprsize*2+16*9], m0 ;t13\n mova m4, [rsp+gprsize*2+16*4] ;in9\n mova m0, [rsp+gprsize*2+16*5] ;in6\n mova [rsp+gprsize*2+16*4], m1 ;t4a\n mova [rsp+gprsize*2+16*5], m5 ;t5a\n ITX_MULSUB_2W 2, 7, 1, 5, 6, 4052, 601 ;t15, t14\n ITX_MULSUB_2W 4, 0, 1, 5, 6, 2440, 3290 ;t7, t6\n psubsw m1, m0, m7 ;t14a\n paddsw m0, m7 ;t6a\n psubsw m5, m4, m2 ;t15a\n paddsw m4, m2 ;t7a\n ITX_MULSUB_2W 5, 1, 7, 2, 6, 2276, 3406 ;t14, t15\n mova m2, [rsp+gprsize*2+16*2] ;t2a\n mova [rsp+gprsize*2+16*2], m5 ;t14\n psubsw m7, m2, m0 ;t6\n paddsw m2, m0 ;t2\n psubsw m0, m3, m4 ;t7\n paddsw m3, m4 ;t3\n ITX_MULSUB_2W 0, 7, 4, 5, 6, 3784, 1567 ;t6a, t7a\n mova m4, [rsp+gprsize*2+16*7] ;in0\n mova m5, [rsp+gprsize*2+32*5] ;in15\n mova [rsp+gprsize*2+16*7], m3 ;t3\n mova [rsp+gprsize*2+32*5], m1 ;t15\n mova m1, [rsp+gprsize*2+16*6] ;in7\n mova m3, [rsp+gprsize*2+16*3] ;in8\n mova [rsp+gprsize*2+16*6], m7 ;t7a\n mova [rsp+gprsize*2+16*3], m0 ;t6a\n ITX_MULSUB_2W 5, 4, 0, 7, 6, 201, 4091 ;t1, t0\n ITX_MULSUB_2W 1, 3, 0, 7, 6, 3035, 2751 ;t9, t8\n psubsw m0, m4, m3 ;t8a\n paddsw m4, m3 ;t0a\n psubsw m3, m5, m1 ;t9a\n paddsw m5, m1 ;t1a\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 799, 4017 ;t9, t8\n mova m1, [rsp+gprsize*2+16*4] ;t4a\n mova m7, [rsp+gprsize*2+16*5] ;t5a\n mova [rsp+gprsize*2+16*4], m3 ;t8\n mova [rsp+gprsize*2+16*5], m0 ;t9\n psubsw m0, m4, m1 ;t4\n paddsw m4, m1 ;t0\n psubsw m3, m5, m7 ;t5\n paddsw m5, m7 ;t1\n ITX_MULSUB_2W 0, 3, 1, 7, 6, 1567, 3784 ;t5a, t4a\n mova m7, [rsp+gprsize*2+16*3] ;t6a\n psubsw m1, m4, m2 ;t2a\n paddsw m4, m2 ;out0\n mova [rsp+gprsize*2+16*3], m4 ;out0\n mova m4, [rsp+gprsize*2+16*6] ;t7a\n psubsw m2, m3, m7 ;t6\n paddsw m3, m7 ;-out3\n mova [rsp+gprsize*2+16*6], m3 ;-out3\n psubsw m3, m0, m4 ;t7\n paddsw m0, m4 ;out12\n mova [rsp+gprsize*2+16*12], m3\n mova m3, [rsp+gprsize*2+16*7] ;t3\n mova [rsp+gprsize*2+16* 7], m2 ;out4\n psubsw m2, m5, m3 ;t3a\n paddsw m5, m3 ;-out15\n mova [rsp+gprsize*2+16*11], m2\n mova m2, [rsp+gprsize*2+32*5] ;t15\n mova [rsp+gprsize*2+16*10], m1 ;-out7\n mova m1, [rsp+gprsize*2+16*0] ;t11\n mova [rsp+gprsize*2+16*0 ], m5 ;-out15\n mova m3, [rsp+gprsize*2+16*1] ;t10\n mova [rsp+gprsize*2+16*1 ], m4 ;-out11\n mova m4, [rsp+gprsize*2+16*2] ;t14\n mova [rsp+gprsize*2+16*2 ], m0 ;out12\n psubsw m0, m3, m4 ;t14a\n paddsw m3, m4 ;t10a\n psubsw m5, m1, m2 ;t15a\n paddsw m1, m2 ;t11a\n ITX_MULSUB_2W 5, 0, 2, 4, 6, 3784, 1567 ;t14, t15\n mova m2, [rsp+gprsize*2+16*4] ;t8\n mova m4, [rsp+gprsize*2+16*5] ;t9\n mova [rsp+gprsize*2+16*4], m3 ;t10a\n mova [rsp+gprsize*2+16*5], m1 ;t11a\n mova m3, [rsp+gprsize*2+16*8] ;t12\n mova m1, [rsp+gprsize*2+16*9] ;t13\n mova [rsp+gprsize*2+16*8], m5 ;t14\n mova [rsp+gprsize*2+16*9], m0 ;t15\n psubsw m5, m2, m3 ;t12a\n paddsw m2, m3 ;t8a\n psubsw m0, m4, m1 ;t13a\n paddsw m4, m1 ;t9a\n ITX_MULSUB_2W 5, 0, 1, 3, 6, 1567, 3784 ;t13, t12\n mova m6, [rsp+gprsize*2+16*4] ;t10a\n mova m1, [rsp+gprsize*2+16*5] ;t11a\n psubsw m3, m2, m6 ;t10\n paddsw m2, m6 ;-out1\n paddsw m6, m4, m1 ;out14\n psubsw m4, m1 ;t11\n mova [rsp+gprsize*2+16*14], m4\n mova [rsp+gprsize*2+16* 4], m2 ;-out1\n mova m4, [rsp+gprsize*2+16*8] ;t14\n mova m2, [rsp+gprsize*2+16*9] ;t15\n mova [rsp+gprsize*2+16* 9], m3 ;out6\n psubsw m3, m0, m4 ;t14a\n paddsw m0, m4 ;out2\n psubsw m4, m5, m2 ;t15a\n paddsw m5, m2 ;-out13\n mova [rsp+gprsize*2+16* 5], m0 ;out2\n ret\nALIGN function_align\n.main_pass1_end:\n mova m0, [rsp+gprsize*2+16*14]\n mova [rsp+gprsize*2+16*14], m5\n mova [rsp+gprsize*2+16*15], m6\n mova m5, [o(pw_2896_2896)]\n mova m6, [o(pw_2896_m2896)]\n mova m7, [o(pd_2048)]\n punpcklwd m2, m3, m4\n punpckhwd m3, m4\n pmaddwd m4, m5, m2\n pmaddwd m2, m6\n pmaddwd m1, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m4, m2, m1, m3\n REPX {psrad x, 12}, m4, m1, m2, m3\n packssdw m4, m1 ;-out5\n packssdw m2, m3 ;out10\n mova [rsp+gprsize*2+16* 8], m4\n mova m3, [rsp+gprsize*2+16* 9]\n punpcklwd m1, m3, m0\n punpckhwd m3, m0\n pmaddwd m0, m5, m1\n pmaddwd m1, m6\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n REPX {paddd x, m7}, m0, m1, m4, m3\n REPX {psrad x, 12}, m0, m4, m1, m3\n packssdw m0, m4 ;out6\n packssdw m1, m3 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n mova m0, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n punpcklwd m3, m0, m4\n punpckhwd m0, m4\n pmaddwd m4, m5, m3\n pmaddwd m3, m6\n pmaddwd m5, m0\n pmaddwd m0, m6\n REPX {paddd x, m7}, m4, m3, m5, m0\n REPX {psrad x, 12}, m4, m5, m3, m0\n packssdw m4, m5 ;out4\n packssdw m3, m0 ;-out11\n mova [rsp+gprsize*2+16* 7], m4\n mova m4, [rsp+gprsize*2+16*10]\n mova m5, [rsp+gprsize*2+16*11]\n punpcklwd m0, m4, m5\n punpckhwd m4, m5\n pmaddwd m5, m0, [o(pw_2896_2896)]\n pmaddwd m0, m6\n pmaddwd m6, m4\n pmaddwd m4, [o(pw_2896_2896)]\n REPX {paddd x, m7}, m5, m0, m6, m4\n REPX {psrad x, 12}, m0, m6, m5, m4\n packssdw m0, m6 ;out8\n packssdw m5, m4 ;-out7\n mova [rsp+gprsize*2+16*10], m5\n mova m4, [rsp+gprsize*2+16* 2] ;out12\n mova m5, [rsp+gprsize*2+16*14] ;-out13\n mova m6, [rsp+gprsize*2+16*15] ;out14\n ret\nALIGN function_align\n.main_pass2_end:\n mova m7, [o(pw_2896x8)]\n mova m1, [rsp+gprsize*2+16* 9]\n mova m2, [rsp+gprsize*2+16*14]\n paddsw m0, m1, m2\n psubsw m1, m2\n pmulhrsw m0, m7 ;out6\n pmulhrsw m1, m7 ;-out9\n mova [rsp+gprsize*2+16* 9], m0\n psubsw m2, m3, m4\n paddsw m3, m4\n pmulhrsw m2, m7 ;out10\n pmulhrsw m3, m7 ;-out5\n mova [rsp+gprsize*2+16* 8], m3\n mova m3, [rsp+gprsize*2+16* 7]\n mova m4, [rsp+gprsize*2+16*12]\n paddsw m0, m3, m4\n psubsw m3, m4\n pmulhrsw m0, m7 ;out4\n pmulhrsw m3, m7 ;-out11\n mova [rsp+gprsize*2+16* 7], m0\n mova m0, [rsp+gprsize*2+16*10]\n paddsw m4, m0, [rsp+gprsize*2+16*11]\n psubsw m0, [rsp+gprsize*2+16*11]\n pmulhrsw m4, m7 ;-out7\n pmulhrsw m0, m7 ;out8\n mova [rsp+gprsize*2+16*10], m4\n mova m4, [rsp+gprsize*2+16*2 ] ;out12\n ret\n\nINV_TXFM_16X8_FN flipadst, dct\nINV_TXFM_16X8_FN flipadst, adst\nINV_TXFM_16X8_FN flipadst, flipadst\nINV_TXFM_16X8_FN flipadst, identity\n\ncglobal iflipadst_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mova m7, [o(pw_2896x8)]\n pmulhrsw m0, m7, [coeffq+16*0 ]\n pmulhrsw m1, m7, [coeffq+16*1 ]\n pmulhrsw m2, m7, [coeffq+16*14]\n pmulhrsw m3, m7, [coeffq+16*15]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n pmulhrsw m0, m7, [coeffq+16*6 ]\n pmulhrsw m1, m7, [coeffq+16*7 ]\n pmulhrsw m2, m7, [coeffq+16*8 ]\n pmulhrsw m3, m7, [coeffq+16*9 ]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n pmulhrsw m0, m7, [coeffq+16*2 ]\n pmulhrsw m1, m7, [coeffq+16*3 ]\n pmulhrsw m2, m7, [coeffq+16*4 ]\n pmulhrsw m3, m7, [coeffq+16*5 ]\n pmulhrsw m4, m7, [coeffq+16*10]\n pmulhrsw m5, m7, [coeffq+16*11]\n pmulhrsw m6, m7, [coeffq+16*12]\n pmulhrsw m7, [coeffq+16*13]\n\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x8_internal).pass1_end)]\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n jmp m(iflipadst_8x8_internal).pass1_end\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x8_internal).pass2_main\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iflipadst_8x8_internal).pass2_main\n\n\nINV_TXFM_16X8_FN identity, dct, 15\nINV_TXFM_16X8_FN identity, adst\nINV_TXFM_16X8_FN identity, flipadst\nINV_TXFM_16X8_FN identity, identity\n\ncglobal iidentity_16x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*16\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x8_internal).pass1_end)]\n\n.pass1:\n mova m0, [o(pw_2896x8)]\n mova m2, [o(pw_1697x16)]\n mova m3, [o(pw_16384)]\n sub coeffq, 8*16\n REPX {pmulhrsw x, m0}, m4, m5, m6, m7\n pmulhrsw m1, m2, m4\n pmulhrsw m1, m3\n paddsw m1, m4 ; 1\n pmulhrsw m4, m2, m5\n pmulhrsw m4, m3\n paddsw m4, m5 ; 3\n pmulhrsw m5, m2, m6\n pmulhrsw m5, m3\n paddsw m5, m6 ; 5\n pmulhrsw m6, m2, m7\n pmulhrsw m6, m3\n paddsw m7, m6 ; 7\n pmulhrsw m6, m0, [coeffq+16*6]\n mova [rsp+gprsize+16*0], m4\n pmulhrsw m4, m2, m6\n pmulhrsw m4, m3\n paddsw m6, m4 ; 6\n pmulhrsw m4, m0, [coeffq+16*4]\n mova [rsp+gprsize+16*1], m6\n pmulhrsw m6, m2, m4\n pmulhrsw m6, m3\n paddsw m4, m6 ; 4\n pmulhrsw m6, m0, [coeffq+16*2]\n pmulhrsw m0, [coeffq+16*0]\n pmulhrsw m2, m6\n pmulhrsw m2, m3\n paddsw m2, m6 ; 2\n pmulhrsw m6, m0, [o(pw_1697x16)]\n pmulhrsw m6, m3\n mova m3, [rsp+gprsize+16*0]\n paddsw m0, m6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n mova [coeffq+16*1], m4\n mova [coeffq+16*3], m5\n mova [coeffq+16*5], m6\n mova [coeffq+16*7], m7\n mova m4, [coeffq-16*7]\n mova m5, [coeffq-16*5]\n mova m6, [coeffq-16*3]\n mova m7, [coeffq-16*1]\n mova [coeffq-16*7], m0\n mova [coeffq-16*5], m1\n mova [coeffq-16*3], m2\n mova [coeffq-16*1], m3\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea tx2q, [o(m(iidentity_16x8_internal).end)]\n lea r3, [dstq+8]\n jmp m(iidentity_8x8_internal).end\n\n.end:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n mov dstq, r3\n jmp m(iidentity_8x8_internal).end\n\n\n%macro INV_TXFM_16X16_FN 2-3 -1 ; type1, type2, fast_thresh\n INV_TXFM_FN %1, %2, %3, 16x16, 8, 16*16\n%ifidn %1_%2, dct_dct\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x16).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n.end:\n RET\n%elifidn %1_%2, dct_identity\n mova m3, [o(pw_2896x8)]\n pmulhrsw m2, m3, [coeffq+16*0]\n pmulhrsw m3, [coeffq+16*1]\n mova m0, [o(pw_8192)]\n mova m1, [o(pw_1697x16)]\n pshuflw m4, [o(deint_shuf)], q0000 ;pb_0_1\n punpcklwd m4, m4\n pcmpeqb m5, m5\n pxor m6, m6\n mova [coeffq+16*0], m6\n mova [coeffq+16*1], m6\n paddb m5, m5 ;pb_m2\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n psrlw m0, 2 ;pw_2048\n pmulhrsw m7, m1, m2\n pmulhrsw m1, m3\n paddsw m2, m2\n paddsw m3, m3\n paddsw m2, m7\n paddsw m3, m1\n pmulhrsw m2, m0\n pmulhrsw m3, m0\n mov r3d, 8\n.loop:\n mova m1, [dstq]\n pshufb m0, m2, m4\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq], m1\n mova m1, [dstq+strideq*8]\n pshufb m0, m3, m4\n psubb m4, m5 ; += 2\n punpckhbw m7, m1, m6\n punpcklbw m1, m6\n paddw m7, m0\n paddw m1, m0\n packuswb m1, m7\n mova [dstq+strideq*8], m1\n add dstq, strideq\n dec r3d\n jg .loop\n RET\n%elifidn %1_%2, identity_dct\n mova m4, [o(pw_1697x16)]\n mova m5, [o(pw_2896x8)]\n mova m6, [o(pw_2048)]\n xor eobd, eobd\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end)]\n lea r3, [dstq+8]\n mov [rsp+16*0], r3\n.main:\n movd m0, [coeffq+32*0]\n punpcklwd m0, [coeffq+32*1]\n movd m1, [coeffq+32*2]\n punpcklwd m1, [coeffq+32*3]\n add coeffq, 32*4\n punpckldq m0, m1\n movd m1, [coeffq+32*0]\n punpcklwd m1, [coeffq+32*1]\n movd m2, [coeffq+32*2]\n punpcklwd m2, [coeffq+32*3]\n xor eobd, eobd\n mov [coeffq-32*4], eobd\n mov [coeffq-32*3], eobd\n mov [coeffq-32*2], eobd\n mov [coeffq-32*1], eobd\n punpckldq m1, m2\n punpcklqdq m0, m1\n pmulhrsw m1, m4, m0\n psraw m1, 1\n pavgw m0, m1\n pmulhrsw m0, m5\n pmulhrsw m0, m6\n mov [coeffq+32*0], eobd\n mov [coeffq+32*1], eobd\n mov [coeffq+32*2], eobd\n mov [coeffq+32*3], eobd\n mov r3d, 4\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n.end:\n lea tx2q, [o(m(inv_txfm_add_identity_dct_16x16).end1)]\n add coeffq, 32*4\n mov dstq, [rsp+16*0]\n jmp .main\n.end1:\n RET\n%endif\n%endmacro\n\nINV_TXFM_16X16_FN dct, dct, 0\nINV_TXFM_16X16_FN dct, identity, 15\nINV_TXFM_16X16_FN dct, adst\nINV_TXFM_16X16_FN dct, flipadst\n\ncglobal idct_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_16x8_internal).main\n mov r3, tx2q\n lea tx2q, [o(m(idct_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(idct_16x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*4 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*12]\n mova m4, [coeffq+16*1 ]\n mova m5, [coeffq+16*5 ]\n mova m6, [coeffq+16*9 ]\n mova m7, [coeffq+16*13]\n lea tx2q, [o(m(idct_8x16_internal).end)]\n jmp m(idct_8x16_internal).pass2_main\n\n\n%macro ITX_16X16_ADST_LOAD_ODD_COEFS 0\n mova m0, [coeffq+16*1 ]\n mova m1, [coeffq+16*3 ]\n mova m2, [coeffq+16*29]\n mova m3, [coeffq+16*31]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*13]\n mova m1, [coeffq+16*15]\n mova m2, [coeffq+16*17]\n mova m3, [coeffq+16*19]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*5 ]\n mova m1, [coeffq+16*7 ]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*11]\n mova m4, [coeffq+16*21]\n mova m5, [coeffq+16*23]\n mova m6, [coeffq+16*25]\n mova m7, [coeffq+16*27]\n%endmacro\n\n%macro ITX_16X16_ADST_LOAD_EVEN_COEFS 0\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*2 ]\n mova m2, [coeffq+16*28]\n mova m3, [coeffq+16*30]\n mova [rsp+gprsize+16*7], m0\n mova [rsp+gprsize+16*8], m1\n mova [rsp+gprsize+16*9], m2\n mova [rsp+gprsize+32*5], m3\n mova m0, [coeffq+16*12]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*16]\n mova m3, [coeffq+16*18]\n mova [rsp+gprsize+16*3], m2\n mova [rsp+gprsize+16*4], m3\n mova [rsp+gprsize+16*5], m0\n mova [rsp+gprsize+16*6], m1\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m4, [coeffq+16*20]\n mova m5, [coeffq+16*22]\n mova m6, [coeffq+16*24]\n mova m7, [coeffq+16*26]\n%endmacro\n\nINV_TXFM_16X16_FN adst, dct\nINV_TXFM_16X16_FN adst, adst\nINV_TXFM_16X16_FN adst, flipadst\n\ncglobal iadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*17, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*1, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n lea tx2q, [o(m(iadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_8192)]\n jmp m(iadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iadst_16x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iadst_16x16_internal).end1)]\n mov dstq, r3\n lea r3, [dstq+8]\n jmp m(iadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n mov dstq, r3\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n lea tx2q, [o(m(iadst_8x16_internal).end)]\n jmp m(iadst_8x16_internal).pass2_main\n\n\nINV_TXFM_16X16_FN flipadst, dct\nINV_TXFM_16X16_FN flipadst, adst\nINV_TXFM_16X16_FN flipadst, flipadst\n\ncglobal iflipadst_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n ITX_16X16_ADST_LOAD_ODD_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mov r3, tx2q\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*1, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end1)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*17, 32\n ITX_16X16_ADST_LOAD_EVEN_COEFS\n call m(iadst_16x8_internal).main\n call m(iadst_16x8_internal).main_pass1_end\n\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).pass1_end2)]\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS coeffq+16* 0, 32\n mova [rsp+gprsize+16*0], m7\n mov tx2q, r3\n mova m7, [o(pw_m8192)]\n jmp m(iflipadst_8x8_internal).pass1_end1\n\n.pass2:\n lea tx2q, [o(m(iflipadst_16x16_internal).end)]\n lea r3, [dstq+8]\n jmp m(iflipadst_8x16_internal).pass2_pre\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(iflipadst_16x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n\n mova m4, [coeffq+16*0 ]\n mova m5, [coeffq+16*2 ]\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*6 ]\n mova m2, [coeffq+16*8 ]\n mova m3, [coeffq+16*10]\n mova m6, [coeffq+16*12]\n mova m7, [coeffq+16*14]\n mova [rsp+gprsize+16*7], m4\n mova [rsp+gprsize+16*8], m5\n mova [rsp+gprsize+16*5], m6\n mova [rsp+gprsize+16*6], m7\n\n lea tx2q, [o(m(iflipadst_16x16_internal).end2)]\n mov dstq, r3\n jmp m(iflipadst_8x16_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp m(iflipadst_8x8_internal).end\n\n\n%macro IDTX16B 3 ; src/dst, tmp, pw_1697x16\n pmulhrsw m%2, m%3, m%1\n psraw m%2, 1\n pavgw m%1, m%2\n%endmacro\n\nINV_TXFM_16X16_FN identity, dct, 15\nINV_TXFM_16X16_FN identity, identity\n\ncglobal iidentity_16x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n add coeffq, 16*17\n mov r3, tx2q\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end)]\n\n.pass1:\n mova m6, [o(pw_1697x16)]\n mova m7, [coeffq+32*6]\n mova m0, [coeffq+32*0]\n mova m1, [coeffq+32*1]\n mova m2, [coeffq+32*2]\n mova m3, [coeffq+32*3]\n mova m4, [coeffq+32*4]\n REPX {IDTX16B x, 5, 6}, 7, 0, 1, 2, 3, 4\n mova m5, [coeffq+32*5]\n mova [rsp+gprsize+16*1], m7\n IDTX16B 5, 7, 6\n mova m7, [coeffq+32*7]\n IDTX16B 7, 6, 6\n jmp m(idct_8x8_internal).pass1_end3\n\n.pass1_end:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end1)]\n jmp .pass1\n\n.pass1_end1:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 15*16\n lea tx2q, [o(m(iidentity_16x16_internal).pass1_end2)]\n jmp .pass1\n\n.pass1_end2:\n SAVE_8ROWS coeffq, 32\n sub coeffq, 16\n mov tx2q, r3\n jmp .pass1\n\n.pass2:\n lea r3, [dstq+8]\n lea tx2q, [o(m(iidentity_16x16_internal).end1)]\n\n.end:\n mova [rsp+gprsize+16*0], m7\n mova [rsp+gprsize+16*1], m4\n mova m7, [o(pw_1697x16)]\n REPX {IDTX16 x, 4, 7}, 5, 6, 0, 1, 2, 3\n mova m4, [o(pw_2048)]\n pmulhrsw m5, m4\n pmulhrsw m6, m4\n mova [rsp+gprsize+16*2], m5\n mova m5, [rsp+gprsize+16*1]\n mova [rsp+gprsize+16*1], m6\n IDTX16 5, 6, 7\n mova m6, [rsp+gprsize+16*0]\n IDTX16 6, 7, 7\n REPX {pmulhrsw x, m4}, m0, m1, m2, m3, m6\n pmulhrsw m4, m5\n mova [rsp+gprsize+16*0], m6\n jmp m(idct_8x8_internal).end3\n\n.end1:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end2)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n.end2:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 32*8\n LOAD_8ROWS coeffq, 32\n lea tx2q, [o(m(iidentity_16x16_internal).end3)]\n mov dstq, r3\n jmp .end\n\n.end3:\n LOAD_8ROWS coeffq+16*1, 32\n lea tx2q, [o(m(idct_8x16_internal).end1)]\n lea dstq, [dstq+strideq*2]\n jmp .end\n\n\ncglobal inv_txfm_add_dct_dct_8x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_8x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n pmulhrsw m0, m2\n psrlw m2, 2 ;pw_2048\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_8x32).end)]\n jmp m(inv_txfm_add_dct_dct_8x8).loop\n\n.end:\n RET\n\n\n\ncglobal idct_8x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n cmp eobd, 106\n jle .fast\n\n LOAD_8ROWS coeffq+16*3, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1:\n mova [rsp+gprsize+16*9 ], m0 ;in24\n mova [rsp+gprsize+16*10], m4 ;in28\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_1:\n mova [rsp+gprsize+16*7 ], m0 ;in16\n mova [rsp+gprsize+16*8 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n.fast:\n LOAD_8ROWS coeffq+16*1, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n mova [rsp+gprsize+16*5 ], m0 ;in8\n mova [rsp+gprsize+16*6 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_8x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n mova m1, m4 ;in4\n mova m2, [rsp+gprsize+16*5 ] ;in8\n mova m3, [rsp+gprsize+16*6 ] ;in12\n\n cmp eobd, 106\n jg .full\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n mova m0, [rsp+gprsize+16*11]\n mova m1, [rsp+gprsize+16*12]\n mova m2, [rsp+gprsize+16*13]\n mova m3, [rsp+gprsize+16*14]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call .main_fast\n jmp .pass2\n\n.full:\n mova m4, [rsp+gprsize+16*7 ] ;in16\n mova m5, [rsp+gprsize+16*8 ] ;in20\n mova m6, [rsp+gprsize+16*9 ] ;in24\n mova m7, [rsp+gprsize+16*10] ;in28\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n call .main\n\n.pass2:\n lea r3, [o(m(idct_8x32_internal).end6)]\n\n.end:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_8x32_internal).end2)]\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, \\\n 8, 9, 10, 11, 12, 13, 14, 15, \\\n 16, 17, 18, 19, 20, 21, 22, 23, \\\n 24, 25, 26, 27, 28, 29, 30, 31\n\n jmp tx2q\n\n.end2:\n lea tx2q, [o(m(idct_8x32_internal).end3)]\n jmp m(idct_8x8_internal).end\n\n.end3:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end4)]\n jmp m(idct_8x8_internal).end\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n lea tx2q, [o(m(idct_8x32_internal).end5)]\n jmp m(idct_8x8_internal).end\n\n.end5:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea dstq, [dstq+strideq*2]\n mov tx2q, r3\n jmp m(idct_8x8_internal).end\n\n.end6:\n ret\n\nALIGN function_align\n.main_veryfast:\n mova m0, [rsp+gprsize*2+16*19] ;in1\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t30,t31\n pmulhrsw m0, [o(pw_201x8)] ;t16,t17\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*34], m3 ;t31\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*20], m3 ;t17a\n mova [rsp+gprsize*2+16*33], m0 ;t30a\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m2, m1, [o(pw_3857x8)] ;t28,t29\n pmulhrsw m1, [o(pw_m1380x8)] ;t18,t19\n mova [rsp+gprsize*2+16*22], m1 ;t19\n mova [rsp+gprsize*2+16*31], m2 ;t28\n pxor m0, m0\n psubw m0, m1\n ITX_MULSUB_2W 0, 2, 1, 3, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m0 ;t18a\n mova [rsp+gprsize*2+16*32], m2 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n pmulhrsw m3, m0, [o(pw_3973x8)] ;t26, t27\n pmulhrsw m0, [o(pw_995x8)] ;t20, t21\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*30], m3 ;t27\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m3 ;t21a\n mova [rsp+gprsize*2+16*29], m0 ;t26a\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pxor m0, m0\n mova m3, m0\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main_fast: ;bottom half is zero\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n pmulhrsw m3, m0, [o(pw_4091x8)] ;t31a\n pmulhrsw m0, [o(pw_201x8)] ;t16a\n pmulhrsw m2, m1, [o(pw_3035x8)] ;t30a\n pmulhrsw m1, [o(pw_m2751x8)] ;t17a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t17\n paddsw m0, m1 ;t16\n psubsw m5, m3, m2 ;t30\n paddsw m3, m2 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n pmulhrsw m3, m0, [o(pw_3703x8)]\n pmulhrsw m0, [o(pw_1751x8)]\n pmulhrsw m2, m1, [o(pw_3857x8)]\n pmulhrsw m1, [o(pw_m1380x8)]\n psubsw m4, m1, m0 ;t18\n paddsw m0, m1 ;t19\n psubsw m5, m2, m3 ;t29\n paddsw m3, m2 ;t28\n pxor m2, m2\n psubw m2, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m5 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n pmulhrsw m3, m0, [o(pw_3973x8)]\n pmulhrsw m0, [o(pw_995x8)]\n pmulhrsw m2, m1, [o(pw_3513x8)]\n pmulhrsw m1, [o(pw_m2106x8)]\n psubsw m4, m0, m1 ;t21\n paddsw m0, m1 ;t20\n psubsw m5, m3, m2 ;t26\n paddsw m3, m2 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m2, [rsp+gprsize*2+16*26] ;in3\n pmulhrsw m3, m0, [o(pw_3290x8)]\n pmulhrsw m0, [o(pw_2440x8)]\n pmulhrsw m1, m2, [o(pw_4052x8)]\n pmulhrsw m2, [o(pw_m601x8)]\n jmp .main2\n\nALIGN function_align\n.main:\n mova m7, [o(pd_2048)]\n mova m0, [rsp+gprsize*2+16*19] ;in1\n mova m1, [rsp+gprsize*2+16*20] ;in15\n mova m2, [rsp+gprsize*2+16*33] ;in17\n mova m3, [rsp+gprsize*2+16*34] ;in31\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 201, 4091 ;t16a, t31a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3035, 2751 ;t17a, t30a\n psubsw m4, m0, m2 ;t17\n paddsw m0, m2 ;t16\n psubsw m5, m3, m1 ;t30\n paddsw m3, m1 ;t31\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 799, 4017 ;t17a, t30a\n mova [rsp+gprsize*2+16*19], m0 ;t16\n mova [rsp+gprsize*2+16*20], m5 ;t17a\n mova [rsp+gprsize*2+16*33], m4 ;t30a\n mova [rsp+gprsize*2+16*34], m3 ;t31\n mova m0, [rsp+gprsize*2+16*21] ;in9\n mova m1, [rsp+gprsize*2+16*22] ;in7\n mova m2, [rsp+gprsize*2+16*31] ;in25\n mova m3, [rsp+gprsize*2+16*32] ;in23\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 1751, 3703 ;t18a, t29a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3857, 1380 ;t19a, t28a\n psubsw m4, m2, m0 ;t18\n paddsw m0, m2 ;t19\n psubsw m5, m1, m3 ;t29\n paddsw m3, m1 ;t28\n pxor m2, m2\n psubw m2, m4 ;-t18\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 799, 4017 ;t18a, t29a\n mova [rsp+gprsize*2+16*21], m2 ;t18a\n mova [rsp+gprsize*2+16*22], m0 ;t19\n mova [rsp+gprsize*2+16*31], m3 ;t28\n mova [rsp+gprsize*2+16*32], m5 ;t29a\n mova m0, [rsp+gprsize*2+16*23] ;in5\n mova m1, [rsp+gprsize*2+16*24] ;in11\n mova m2, [rsp+gprsize*2+16*29] ;in21\n mova m3, [rsp+gprsize*2+16*30] ;in27\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 995, 3973 ;t20a, t27a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 3513, 2106 ;t21a, t26a\n psubsw m4, m0, m2 ;t21\n paddsw m0, m2 ;t20\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t27\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3406, 2276 ;t21a, t26a\n mova [rsp+gprsize*2+16*23], m0 ;t20\n mova [rsp+gprsize*2+16*24], m5 ;t21a\n mova [rsp+gprsize*2+16*29], m4 ;t26a\n mova [rsp+gprsize*2+16*30], m3 ;t27\n mova m0, [rsp+gprsize*2+16*25] ;in13\n mova m1, [rsp+gprsize*2+16*26] ;in3\n mova m2, [rsp+gprsize*2+16*27] ;in29\n mova m3, [rsp+gprsize*2+16*28] ;in19\n ITX_MULSUB_2W 0, 3, 4, 5, 7, 2440, 3290 ;t22a, t25a\n ITX_MULSUB_2W 2, 1, 4, 5, 7, 4052, 601 ;t23a, t24a\n\n.main2:\n psubsw m4, m2, m0 ;t22\n paddsw m0, m2 ;t23\n psubsw m5, m1, m3 ;t25\n paddsw m3, m1 ;t24\n pxor m6, m6\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 3406, 2276 ;t22a, t25a\n\n mova m4, [rsp+gprsize*2+16*24] ;t21a\n psubsw m1, m2, m4 ;t21\n paddsw m2, m4 ;t22\n psubw m4, m6, m1 ;-t21\n mova [rsp+gprsize*2+16*25], m2 ;t22\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n psubsw m2, m5, m1 ;t26\n paddsw m5, m1 ;t25\n mova [rsp+gprsize*2+16*28], m5 ;t25\n ITX_MULSUB_2W 4, 2, 1, 5, 7, 1567, 3784 ;t21a, t26a\n mova [rsp+gprsize*2+16*24], m4 ;t21a\n mova [rsp+gprsize*2+16*29], m2 ;t26a\n\n mova m1, [rsp+gprsize*2+16*23] ;t20\n mova m5, [rsp+gprsize*2+16*30] ;t27\n psubsw m2, m0, m1 ;t20a\n paddsw m0, m1 ;t23a\n psubsw m4, m3, m5 ;t27a\n paddsw m3, m5 ;t24a\n psubw m6, m2 ;-t20a\n ITX_MULSUB_2W 6, 4, 1, 5, 7, 1567, 3784 ;t20, t27\n mova [rsp+gprsize*2+16*26], m0 ;t23a\n mova [rsp+gprsize*2+16*27], m3 ;t24a\n mova [rsp+gprsize*2+16*30], m4 ;t27\n\n mova m0, [rsp+gprsize*2+16*20] ;t17a\n mova m1, [rsp+gprsize*2+16*21] ;t18a\n mova m2, [rsp+gprsize*2+16*32] ;t29a\n mova m3, [rsp+gprsize*2+16*33] ;t30a\n psubsw m4, m0, m1 ;t18\n paddsw m0, m1 ;t17\n psubsw m5, m3, m2 ;t29\n paddsw m3, m2 ;t30\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t18a, t29a\n mova [rsp+gprsize*2+16*20], m0 ;t17\n mova [rsp+gprsize*2+16*21], m5 ;t18a\n mova [rsp+gprsize*2+16*32], m4 ;t29a\n mova [rsp+gprsize*2+16*33], m3 ;t30\n mova m0, [rsp+gprsize*2+16*19] ;t16\n mova m1, [rsp+gprsize*2+16*22] ;t19\n mova m2, [rsp+gprsize*2+16*31] ;t28\n mova m3, [rsp+gprsize*2+16*34] ;t31\n psubsw m4, m0, m1 ;t19a\n paddsw m0, m1 ;t16a\n psubsw m5, m3, m2 ;t28a\n paddsw m3, m2 ;t31a\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1567, 3784 ;t19, t28\n mova m2, [rsp+gprsize*2+16*15] ;tmp12\n psubsw m1, m5, m6 ;t20a\n paddsw m5, m6 ;t19a\n psubsw m6, m2, m5 ;out19\n paddsw m2, m5 ;out12\n mova m5, [rsp+gprsize*2+16*30] ;t27\n mova [rsp+gprsize*2+16*22], m6 ;out19\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m6, m4, m5 ;t27a\n paddsw m4, m5 ;t28a\n ITX_MULSUB_2W 6, 1, 2, 5, 7, 2896, 2896 ;t20, t27\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp3\n psubsw m5, m2, m4 ;out28\n paddsw m2, m4 ;out3\n mova m4, [rsp+gprsize*2+16*14] ;tmp11\n mova [rsp+gprsize*2+16*31], m5 ;out28\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m5, m4, m6 ;out20\n paddsw m4, m6 ;out11\n mova m2, [rsp+gprsize*2+16*7 ] ;tmp4\n mova [rsp+gprsize*2+16*23], m5 ;out20\n mova [rsp+gprsize*2+16*14], m4 ;out11\n psubsw m5, m2, m1 ;out27\n paddsw m2, m1 ;out4\n mova m1, [rsp+gprsize*2+16*26] ;t23a\n mova m4, [rsp+gprsize*2+16*27] ;t24a\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*7 ], m2 ;out4\n psubsw m5, m0, m1 ;t23\n paddsw m0, m1 ;t16\n psubsw m2, m3, m4 ;t24\n paddsw m3, m4 ;t31\n ITX_MULSUB_2W 2, 5, 4, 6, 7, 2896, 2896 ;t23a, t24a\n mova m6, [rsp+gprsize*2+16*18] ;tmp15\n psubsw m4, m6, m0 ;out16\n paddsw m6, m0 ;out15\n mova m0, [rsp+gprsize*2+16*3 ] ;tmp0\n mova m1, [rsp+gprsize*2+16*11] ;tmp8\n mova [rsp+gprsize*2+16*18], m6 ;out15\n mova [rsp+gprsize*2+16*19], m4 ;out16\n psubsw m6, m0, m3 ;out31\n paddsw m0, m3 ;out0\n psubsw m4, m1, m2 ;out23\n paddsw m1, m2 ;out8\n mova m3, [rsp+gprsize*2+16*10] ;tmp7\n mova [rsp+gprsize*2+16*34], m6 ;out31\n mova [rsp+gprsize*2+16*11], m1 ;out8\n mova [rsp+gprsize*2+16*26], m4 ;out23\n paddsw m6, m3, m5 ;out7\n psubsw m3, m5 ;out24\n mova m1, [rsp+gprsize*2+16*20] ;t17\n mova m5, [rsp+gprsize*2+16*25] ;t22\n mova m2, [rsp+gprsize*2+16*17] ;tmp14\n mova [rsp+gprsize*2+16*27], m3 ;out24\n psubsw m4, m1, m5 ;t22a\n paddsw m1, m5 ;t17a\n psubsw m3, m2, m1 ;out17\n paddsw m2, m1 ;out14\n mova m5, [rsp+gprsize*2+16*28] ;t25\n mova m1, [rsp+gprsize*2+16*33] ;t30\n mova [rsp+gprsize*2+16*17], m2 ;out14\n mova [rsp+gprsize*2+16*20], m3 ;out17\n psubsw m2, m1, m5 ;t25a\n paddsw m1, m5 ;t30a\n ITX_MULSUB_2W 2, 4, 3, 5, 7, 2896, 2896 ;t22, t25\n mova m5, [rsp+gprsize*2+16*4 ] ;tmp1\n psubsw m3, m5, m1 ;out30\n paddsw m5, m1 ;out1\n mova m1, [rsp+gprsize*2+16*12] ;tmp9\n mova [rsp+gprsize*2+16*33], m3 ;out30\n mova [rsp+gprsize*2+16*4 ], m5 ;out1\n psubsw m3, m1, m2 ;out22\n paddsw m1, m2 ;out9\n mova m5, [rsp+gprsize*2+16*9 ] ;tmp6\n mova [rsp+gprsize*2+16*25], m3 ;out22\n mova [rsp+gprsize*2+16*12], m1 ;out9\n psubsw m3, m5, m4 ;out25\n paddsw m5, m4 ;out6\n mova m4, [rsp+gprsize*2+16*21] ;t18a\n mova m1, [rsp+gprsize*2+16*24] ;t21a\n mova m2, [rsp+gprsize*2+16*16] ;tmp13\n mova [rsp+gprsize*2+16*28], m3 ;out25\n mova [rsp+gprsize*2+16*9 ], m5 ;out6\n paddsw m3, m4, m1 ;t18\n psubsw m4, m1 ;t21\n psubsw m5, m2, m3 ;out18\n paddsw m2, m3 ;out13\n mova m1, [rsp+gprsize*2+16*29] ;t26a\n mova m3, [rsp+gprsize*2+16*32] ;t29a\n mova [rsp+gprsize*2+16*21], m5 ;out18\n mova [rsp+gprsize*2+16*16], m2 ;out13\n psubsw m5, m3, m1 ;t26\n paddsw m3, m1 ;t29\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 2896, 2896 ;t21a, t26a\n mova m2, [rsp+gprsize*2+16*5 ] ;tmp2\n psubsw m1, m2, m3 ;out29\n paddsw m2, m3 ;out2\n mova m3, [rsp+gprsize*2+16*13] ;tmp10\n mova [rsp+gprsize*2+16*32], m1 ;out29\n psubsw m7, m3, m5 ;out21\n paddsw m3, m5 ;out10\n mova m5, [rsp+gprsize*2+16*8 ] ;tmp5\n mova [rsp+gprsize*2+16*24], m7 ;out21\n mova [rsp+gprsize*2+16*13], m3 ;out10\n psubsw m1, m5, m4 ;out26\n paddsw m5, m4 ;out5\n mova m7, m6 ;out7\n mova m3, [rsp+gprsize*2+16*6 ] ;out3\n mova m4, [rsp+gprsize*2+16*7 ] ;out4\n mova [rsp+gprsize*2+16*29], m1 ;out26\n mova m6, [rsp+gprsize*2+16*9 ] ;out6\n mova m1, [rsp+gprsize*2+16*4 ] ;out1\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x8, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_32x8_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 8\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m5, m5\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n punpckhbw m2, m1, m5\n punpcklbw m1, m5\n punpckhbw m4, m3, m5\n punpcklbw m3, m5\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\ncglobal idct_32x8_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n LOAD_8ROWS coeffq+16*0, 64\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*2, 64\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*1, 32\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n cmp eobd, 106\n jg .full\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n LOAD_8ROWS coeffq+16*17, 32\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass2:\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x8_internal).end)]\n jmp m(idct_8x32_internal).end1\n\n.end:\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end1:\n lea r3, [dstq+8]\n lea tx2q, [o(m(idct_32x8_internal).end2)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end3:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end4)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end4:\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end5:\n mov dstq, r3\n lea r3, [r3+8]\n lea tx2q, [o(m(idct_32x8_internal).end6)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end6:\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x8_internal).end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.end7:\n mov dstq, r3\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n jmp m(idct_8x8_internal).pass2_main\n\n.end8:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_8x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n.loop:\n LOAD_8ROWS coeffq+16*0, 64\n paddsw m6, [o(pw_5)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_5)]\n REPX {paddsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n call m(idct_8x8_internal).pass1_end3\n REPX {psraw x, 3 }, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n add coeffq, 16\n dec r3d\n jg .loop\n RET\n\ncglobal inv_txfm_add_identity_identity_32x8, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n mov r5d, 4\n mov tx2d, 2\n cmp eobd, 106\n cmovg tx2d, r5d\n mov r3d, tx2d\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n.loop:\n LOAD_8ROWS coeffq+16*0, 16\n pmulhrsw m6, [o(pw_4096)]\n mova [rsp+16*1], m6\n mova m6, [o(pw_4096)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n lea tx2q, [o(m(idct_32x8_internal).end8)]\n call m(idct_8x8_internal).pass1_end3\n\n mov [rsp+16*3], dstq\n mova [rsp+16*2], m5\n mova [rsp+16*1], m6\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_8x8_internal).end4)]\n call m(idct_8x8_internal).end3\n\n add coeffq, 16*8\n mov dstq, [rsp+16*3]\n lea dstq, [dstq+8]\n dec r3d\n jg .loop\n jnc .loop\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n call m(idct_16x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r2d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x32).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\ncglobal idct_16x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n LOAD_8ROWS coeffq+16*1, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*5, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+16*33, 64 ;in8~in15\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n mova [coeffq+16*1 ], m0 ;in8\n mova [coeffq+16*5 ], m4 ;in12\n mova [rsp+gprsize+16*13], m2 ;in10\n mova [rsp+gprsize+16*14], m6 ;in14\n mova [rsp+gprsize+16*21], m1 ;in9\n mova [rsp+gprsize+16*24], m3 ;in11\n mova [rsp+gprsize+16*25], m5 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*32, 64 ;in0~in7\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n mova [rsp+gprsize+16*11], m2 ;in2\n mova [rsp+gprsize+16*12], m6 ;in6\n mova [rsp+gprsize+16*19], m1 ;in1\n mova [rsp+gprsize+16*26], m3 ;in3\n mova [rsp+gprsize+16*23], m5 ;in5\n mova [rsp+gprsize+16*22], m7 ;in7\n\n cmp eobd, 150\n jg .full\n\n mova m1, m4 ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [rsp+gprsize+16*11] ;in2\n mova m1, [rsp+gprsize+16*12] ;in6\n mova m2, [rsp+gprsize+16*13] ;in10\n mova m3, [rsp+gprsize+16*14] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .pass2\n\n.full:\n mova [coeffq+16*0 ], m0 ;in0\n mova [coeffq+16*4 ], m4 ;in4\n\n LOAD_8ROWS coeffq+16*2, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*6, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*34, 64 ;in16~in23\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n mova [coeffq+16*2 ], m0 ;in16\n mova [coeffq+16*6 ], m4 ;in20\n mova [rsp+gprsize+16*15], m2 ;in18\n mova [rsp+gprsize+16*16], m6 ;in22\n mova [rsp+gprsize+16*33], m1 ;in17\n mova [rsp+gprsize+16*28], m3 ;in19\n mova [rsp+gprsize+16*29], m5 ;in21\n mova [rsp+gprsize+16*32], m7 ;in23\n\n LOAD_8ROWS coeffq+16*3, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+16*7, 128, 1\n call m(idct_16x8_internal).main\n lea tx2q, [o(m(idct_16x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS coeffq+16*35, 64 ;in24~in31\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_16x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n mova [rsp+gprsize+16*17], m2 ;in26\n mova [rsp+gprsize+16*18], m6 ;in30\n mova [rsp+gprsize+16*31], m1 ;in25\n mova [rsp+gprsize+16*30], m3 ;in27\n mova [rsp+gprsize+16*27], m5 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n mova m6, m0 ;in24\n mova m7, m4 ;in28\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*4 ] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*5 ] ;in12\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*6 ] ;in20\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3 , 16\n LOAD_8ROWS rsp+gprsize+16*11, 16\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main\n\n.pass2:\n mov [rsp+gprsize*1+16*35], eobd\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n lea r3, [o(m(idct_16x32_internal).end)]\n jmp m(idct_8x32_internal).end\n\n.end:\n mov dstq, [rsp+gprsize*2+16*35]\n mov eobd, [rsp+gprsize*1+16*35]\n add coeffq, 16*32\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mova m0, [coeffq+16*0 ] ;in0\n mova m1, [coeffq+16*16] ;in4\n mova m2, [coeffq+16*1 ] ;in8\n mova m3, [coeffq+16*17] ;in12\n\n cmp eobd, 150\n jg .full1\n\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp .end1\n\n.full1:\n mova m4, [coeffq+16*2 ] ;in16\n mova m5, [coeffq+16*18] ;in20\n mova m6, [coeffq+16*3 ] ;in24\n mova m7, [coeffq+16*19] ;in26\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ] ;in2\n mova m1, [coeffq+16*24] ;in6\n mova m2, [coeffq+16*9 ] ;in10\n mova m3, [coeffq+16*25] ;in14\n mova m4, [coeffq+16*10] ;in18\n mova m5, [coeffq+16*26] ;in22\n mova m6, [coeffq+16*11] ;in26\n mova m7, [coeffq+16*27] ;in30\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n\n.end1:\n jmp m(idct_8x32_internal).pass2\n\n\n\ncglobal inv_txfm_add_dct_dct_32x16, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x16_internal)\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*11, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*19, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n\n add coeffq, 16*16\n lea dstq, [r3+8]\n LOAD_8ROWS rsp+16*27, 16\n mova [rsp+16*0], m7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end\n call m(idct_8x16_internal).pass2\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n add coeffq, 16\n lea r3, [o(m(idct_32x16_internal).pass1_end1)]\n.pass1:\n LOAD_8ROWS coeffq+16*0, 128, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+16*4, 128, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+16*2, 64, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n LOAD_8ROWS coeffq+16*34, 64, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n call m(idct_8x32_internal).main\n\n.pass1_end:\n mova [rsp+gprsize+16*0 ], m7\n mov tx2q, r3\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+16*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+16*16, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+16*32, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0 ], m7\n lea tx2q, [o(m(idct_32x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+16*48, 32\n\n sub coeffq, 16\n lea r3, [o(m(idct_32x16_internal).end)]\n jmp .pass1\n\n.end:\n ret\n\n\ncglobal inv_txfm_add_identity_identity_16x32, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 1\n mov r5, 2\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count++\n inc r5\n cmp eobd, 278 ;if (eob > 278)\n cmovg r4, r5 ; iteration_count++\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n mov [rsp+gprsize+16*3], r4\n mov [rsp+gprsize*2+16*3], coeffq\n\n.loop:\n LOAD_8ROWS coeffq, 64, 1\n mova [rsp+16*1], m6\n pxor m6, m6\n REPX {mova [coeffq+64*x], m6}, 0, 1, 2, 3, 4, 5, 6, 7\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*0], m2\n mova [rsp+16*1], m3\n mova [rsp+16*2], m4\n mova m3, [o(pw_1697x16)]\n mova m4, [o(pw_16384)]\n REPX {IDTX16 x, 2, 3, 4}, 5, 6, 7, 0, 1\n mova m2, [o(pw_8192)]\n REPX {pmulhrsw x, m2}, m5, m6, m7, m0, m1\n mova m2, [rsp+16*0]\n mova [rsp+16*0], m7\n IDTX16 2, 7, 3, 4\n mova m7, [rsp+16*2]\n mova [rsp+16*2], m5\n IDTX16 7, 5, 3, 4\n mova m5, [rsp+16*1]\n mova [rsp+16*1], m6\n pmulhrsw m3, m5\n pmulhrsw m3, m4\n psrlw m4, 1 ; pw_8192\n paddsw m3, m5\n pmulhrsw m2, m4\n pmulhrsw m3, m4\n pmulhrsw m4, m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n add coeffq, 16\n dec r3\n jg .loop\n mov coeffq, [rsp+gprsize*2+16*3]\n add coeffq, 64*8\n mov r3, [rsp+gprsize+16*3]\n xor dstq, dstq\n mov [rsp+gprsize+16*3], dstq\n mov dstq, [rsp+16*3]\n test r3, r3\n jnz .loop\n RET\n\n\ncglobal inv_txfm_add_identity_identity_32x16, 4, 6, 8, 16*4, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 12 ;0100b\n mov r5, 136 ;1000 1000b\n cmp eobd, 43 ;if (eob > 43)\n cmovg r4, r5 ; iteration_count+2\n mov r5, 34952 ;1000 1000 1000 1000b\n cmp eobd, 150 ;if (eob > 150)\n cmovg r4, r5 ; iteration_count += 4\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n lea r3, [dstq+8]\n mov [rsp+16*3], r3\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 32, 1\n REPX {paddsw x, x}, m0, m1, m2, m3, m4, m5, m6, m7\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n mova [rsp+16*1], m5\n mova [rsp+16*2], m6\n mova m6, [o(pw_1697x16)]\n REPX {IDTX16 x, 5, 6}, 7, 0, 1, 2, 3, 4\n pmulhrsw m7, [o(pw_2048)]\n mova m5, [rsp+16*1]\n mova [rsp+16*0], m7\n IDTX16 5, 7, 6\n mova m7, [rsp+16*2]\n IDTX16 7, 6, 6\n mova m6, [o(pw_2048)]\n REPX {pmulhrsw x, m6}, m0, m1, m2, m3, m4, m5, m7\n mova [rsp+16*2], m5\n mova [rsp+16*1], m7\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n pxor m7, m7\n REPX {mova [coeffq+32*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n.loop_end:\n add coeffq, 16\n shr r3, 2\n test r3, r3\n jz .ret\n test r3, 2\n jnz .loop\n mov r4, r3\n and r4, 1\n shl r4, 3\n add coeffq, r4\n add coeffq, 32*7\n mov dstq, [rsp+16*3]\n lea r4, [dstq+8]\n mov [rsp+16*3], r4\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_32x32, 4, 6, 8, 16*36, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x8).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n\ncglobal idct_32x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*35], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*35], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*35]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n mova m0, [coeffq+256*0]\n mova m1, [coeffq+256*1]\n mova m2, [coeffq+256*2]\n mova m3, [coeffq+256*3]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n mova m0, [coeffq+128*1]\n mova m1, [coeffq+128*3]\n mova m2, [coeffq+128*5]\n mova m3, [coeffq+128*7]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_32x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*35]\n mov r3, 4\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*35], r3\n lea r3, [dstq+8]\n mov [rsp+gprsize*2+16*35], r3\n\n mova m0, [coeffq+16*4 ]\n mova m1, [coeffq+16*12]\n mova m2, [coeffq+16*20]\n mova m3, [coeffq+16*28]\n mova m4, [coeffq+16*5 ]\n mova m5, [coeffq+16*13]\n mova m6, [coeffq+16*21]\n mova m7, [coeffq+16*29]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov eobd, [rsp+gprsize*1+16*35]\n test eobd, eobd\n jl .fast1\n\n.full1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n mova m4, [coeffq+16*2 ]\n mova m5, [coeffq+16*18]\n mova m6, [coeffq+16*3 ]\n mova m7, [coeffq+16*19]\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*6 ]\n mova m1, [coeffq+16*14]\n mova m2, [coeffq+16*22]\n mova m3, [coeffq+16*30]\n mova m4, [coeffq+16*7 ]\n mova m5, [coeffq+16*15]\n mova m6, [coeffq+16*23]\n mova m7, [coeffq+16*31]\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp tx2q\n\n.fast1:\n mova m0, [coeffq+16*0 ]\n mova m1, [coeffq+16*16]\n mova m2, [coeffq+16*1 ]\n mova m3, [coeffq+16*17]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n jmp tx2q\n\n.pass2_end:\n lea r3, [o(m(idct_32x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end\n\n.pass2_end1:\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg .pass2_loop\n\n ret\n\n\ncglobal inv_txfm_add_identity_identity_32x32, 4, 6, 8, 16*5, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r4, 2\n mov r5, 4\n cmp eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n lea r3, [dstq+8]\n mov [rsp+gprsize*0+16*3], r3\n mov [rsp+gprsize*1+16*3], r4\n mov [rsp+gprsize*2+16*3], r4\n mov [rsp+gprsize*3+16*3], coeffq\n mov r3, r4\n\n.loop:\n LOAD_8ROWS coeffq, 64\n mova [rsp+16*1], m6\n lea tx2q, [o(m(idct_32x16_internal).end)]\n call m(idct_8x8_internal).pass1_end3\n pmulhrsw m7, [o(pw_8192)]\n mova [rsp+16*0], m7\n mova m7, [o(pw_8192)]\n REPX {pmulhrsw x, m7}, m0, m1, m2, m3, m4, m5, m6\n mova [rsp+16*1], m6\n mova [rsp+16*2], m5\n call m(idct_8x8_internal).end3\n lea dstq, [dstq+strideq*2]\n\n pxor m7, m7\n REPX {mova [coeffq+64*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7\n\n add coeffq, 16\n dec r3\n jg .loop\n\n mov r4, [rsp+gprsize*2+16*3]\n dec r4\n jle .ret\n\n mov dstq, [rsp+gprsize*0+16*3]\n mov coeffq, [rsp+gprsize*3+16*3]\n mov [rsp+gprsize*2+16*3], r4\n lea r3, [dstq+8]\n add coeffq, 64*8\n mov [rsp+gprsize*0+16*3], r3\n mov r3, [rsp+gprsize*1+16*3]\n mov [rsp+gprsize*3+16*3], coeffq\n jmp .loop\n\n.ret:\n RET\n\n\ncglobal inv_txfm_add_dct_dct_16x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_16x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r2d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_16x64).end)]\n jmp m(inv_txfm_add_dct_dct_16x4).dconly\n\n.end:\n RET\n\n\ncglobal idct_16x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 151\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*0, 64*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*1, 64*2\n call m(idct_16x8_internal).main\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_16x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 2\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n.pass2_loop:\n mov [rsp+gprsize*3+16*67], r3\n mov eobd, [rsp+gprsize*1+16*67]\n\n mova m0, [coeffq+16*4 ] ;in1\n mova m1, [coeffq+16*12] ;in3\n mova m2, [coeffq+16*20] ;in5\n mova m3, [coeffq+16*28] ;in7\n mova m4, [coeffq+16*5 ] ;in9\n mova m5, [coeffq+16*13] ;in11\n mova m6, [coeffq+16*21] ;in13\n mova m7, [coeffq+16*29] ;in15\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n pxor m4, m4\n mova m0, [coeffq+16*0]\n mova m1, [coeffq+16*1]\n\n test eobd, eobd\n jl .fast\n\n.full:\n mova m2, [coeffq+16*2]\n mova m3, [coeffq+16*3]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n mova m2, [coeffq+16*18]\n mova m3, [coeffq+16*19]\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova m4, [coeffq+16*10]\n mova m5, [coeffq+16*26]\n mova m6, [coeffq+16*11]\n mova m7, [coeffq+16*27]\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n mova m0, [coeffq+16*6 ] ;in17\n mova m1, [coeffq+16*14] ;in19\n mova m2, [coeffq+16*22] ;in21\n mova m3, [coeffq+16*30] ;in23\n mova m4, [coeffq+16*7 ] ;in25\n mova m5, [coeffq+16*15] ;in27\n mova m6, [coeffq+16*23] ;in29\n mova m7, [coeffq+16*31] ;in31\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call .main\n jmp .end\n\n.fast:\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n mova m0, [coeffq+16*16]\n mova m1, [coeffq+16*17]\n\n REPX {mova x, m4}, m2, m3, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n mova m0, [coeffq+16*8 ]\n mova m1, [coeffq+16*24]\n mova m2, [coeffq+16*9 ]\n mova m3, [coeffq+16*25]\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n\n call m(idct_8x32_internal).main_veryfast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n call .main_fast\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mov r3, r4\n jmp m(idct_8x32_internal).end2\n\n.end1:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n lea r3, [o(m(idct_16x64_internal).end2)]\n jmp m(idct_8x32_internal).end\n\n.end2:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n\n dec r3\n jg .pass2_loop\n ret\n\n\nALIGN function_align\n.main_fast:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t62,t63\n pmulhrsw m0, [o(pw_101x8)] ;t32,t33\n mova m7, [o(pd_2048)]\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*66], m3 ;t63\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*36], m3 ;t33a\n mova [rsp+gprsize*2+16*65], m0 ;t62a\n\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60,t61\n pmulhrsw m1, [o(pw_m1474x8)] ;t34,t35\n mova [rsp+gprsize*2+16*38], m1 ;t35\n mova [rsp+gprsize*2+16*63], m2 ;t60\n pxor m6, m6\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 401, 4076 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m3 ;t34a\n mova [rsp+gprsize*2+16*64], m2 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t58,t59\n pmulhrsw m0, [o(pw_897x8)] ;t36,t37\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*62], m3 ;t59\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56,t57\n pmulhrsw m1, [o(pw_m700x8)] ;t38,t39\n mova [rsp+gprsize*2+16*42], m1 ;t39\n mova [rsp+gprsize*2+16*59], m2 ;t56\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 3166, 2598 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m3 ;t38a\n mova [rsp+gprsize*2+16*60], m2 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t54,t55\n pmulhrsw m0, [o(pw_501x8)] ;t40,t41\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*58], m3 ;t55\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*44], m3 ;t41a\n mova [rsp+gprsize*2+16*57], m0 ;t54a\n\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52,t53\n pmulhrsw m1, [o(pw_m1092x8)] ;t42,t43\n mova [rsp+gprsize*2+16*46], m1 ;t43\n mova [rsp+gprsize*2+16*55], m2 ;t52\n psubw m3, m6, m1\n ITX_MULSUB_2W 3, 2, 0, 1, 7, 1931, 3612 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m3 ;t42a\n mova [rsp+gprsize*2+16*56], m2 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t50,t51\n pmulhrsw m0, [o(pw_1285x8)] ;t44,t45\n mova m6, m0\n mova [rsp+gprsize*2+16*54], m3 ;t51\n ITX_MULSUB_2W 3, 0, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m3 ;t45a\n mova [rsp+gprsize*2+16*53], m0 ;t50a\n\n mova m0, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_4085x8)] ;t48,t49\n pmulhrsw m0, [o(pw_m301x8)] ;t46,t47\n mova m4, m3\n mova m5, m0\n\n jmp .main2\n\nALIGN function_align\n.main:\n mova m0, [rsp+gprsize*2+16*35] ;in1\n mova m1, [rsp+gprsize*2+16*65] ;in31\n pmulhrsw m3, m0, [o(pw_4095x8)] ;t63a\n pmulhrsw m0, [o(pw_101x8)] ;t32a\n pmulhrsw m2, m1, [o(pw_2967x8)] ;t62a\n pmulhrsw m1, [o(pw_m2824x8)] ;t33a\n mova m7, [o(pd_2048)]\n psubsw m4, m0, m1 ;t33\n paddsw m0, m1 ;t32\n psubsw m5, m3, m2 ;t62\n paddsw m3, m2 ;t63\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 401, 4076 ;t33a, t62a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*36], m5 ;t33a\n mova [rsp+gprsize*2+16*65], m4 ;t62a\n mova [rsp+gprsize*2+16*66], m3 ;t63\n\n mova m0, [rsp+gprsize*2+16*63] ;in17\n mova m1, [rsp+gprsize*2+16*37] ;in15\n pmulhrsw m3, m0, [o(pw_3745x8)] ;t61a\n pmulhrsw m0, [o(pw_1660x8)] ;t34a\n pmulhrsw m2, m1, [o(pw_3822x8)] ;t60a\n pmulhrsw m1, [o(pw_m1474x8)] ;t35a\n psubsw m4, m1, m0 ;t34\n paddsw m0, m1 ;t35\n psubsw m5, m2, m3 ;t61\n paddsw m3, m2 ;t60\n pxor m6, m6\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 401, 4076 ;t34a, t61a\n mova [rsp+gprsize*2+16*37], m2 ;t34a\n mova [rsp+gprsize*2+16*38], m0 ;t35\n mova [rsp+gprsize*2+16*63], m3 ;t60\n mova [rsp+gprsize*2+16*64], m5 ;t61a\n\n mova m0, [rsp+gprsize*2+16*39] ;in9\n mova m1, [rsp+gprsize*2+16*61] ;in23\n pmulhrsw m3, m0, [o(pw_3996x8)] ;t59a\n pmulhrsw m0, [o(pw_897x8)] ;t36a\n pmulhrsw m2, m1, [o(pw_3461x8)] ;t58a\n pmulhrsw m1, [o(pw_m2191x8)] ;t37a\n psubsw m4, m0, m1 ;t37\n paddsw m0, m1 ;t36\n psubsw m5, m3, m2 ;t58\n paddsw m3, m2 ;t59\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3166, 2598 ;t37a, t58a\n mova [rsp+gprsize*2+16*39], m0 ;t36\n mova [rsp+gprsize*2+16*40], m5 ;t37a\n mova [rsp+gprsize*2+16*61], m4 ;t58a\n mova [rsp+gprsize*2+16*62], m3 ;t59\n\n mova m0, [rsp+gprsize*2+16*59] ;in25\n mova m1, [rsp+gprsize*2+16*41] ;in7\n pmulhrsw m3, m0, [o(pw_3349x8)] ;t57a\n pmulhrsw m0, [o(pw_2359x8)] ;t38a\n pmulhrsw m2, m1, [o(pw_4036x8)] ;t56a\n pmulhrsw m1, [o(pw_m700x8)] ;t39a\n psubsw m4, m1, m0 ;t38\n paddsw m0, m1 ;t39\n psubsw m5, m2, m3 ;t57\n paddsw m3, m2 ;t56\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 3166, 2598 ;t38a, t57a\n mova [rsp+gprsize*2+16*41], m2 ;t38a\n mova [rsp+gprsize*2+16*42], m0 ;t39\n mova [rsp+gprsize*2+16*59], m3 ;t56\n mova [rsp+gprsize*2+16*60], m5 ;t57a\n\n mova m0, [rsp+gprsize*2+16*43] ;in5\n mova m1, [rsp+gprsize*2+16*57] ;in27\n pmulhrsw m3, m0, [o(pw_4065x8)] ;t55a\n pmulhrsw m0, [o(pw_501x8)] ;t40a\n pmulhrsw m2, m1, [o(pw_3229x8)] ;t54a\n pmulhrsw m1, [o(pw_m2520x8)] ;t41a\n psubsw m4, m0, m1 ;t41\n paddsw m0, m1 ;t40\n psubsw m5, m3, m2 ;t54\n paddsw m3, m2 ;t55\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 1931, 3612 ;t41a, t54a\n mova [rsp+gprsize*2+16*43], m0 ;t40\n mova [rsp+gprsize*2+16*44], m5 ;t41a\n mova [rsp+gprsize*2+16*57], m4 ;t54a\n mova [rsp+gprsize*2+16*58], m3 ;t55\n\n mova m0, [rsp+gprsize*2+16*55] ;in21\n mova m1, [rsp+gprsize*2+16*45] ;in11\n pmulhrsw m3, m0, [o(pw_3564x8)] ;t53a\n pmulhrsw m0, [o(pw_2019x8)] ;t42a\n pmulhrsw m2, m1, [o(pw_3948x8)] ;t52a\n pmulhrsw m1, [o(pw_m1092x8)] ;t43a\n psubsw m4, m1, m0 ;t42\n paddsw m0, m1 ;t43\n psubsw m5, m2, m3 ;t53\n paddsw m3, m2 ;t52\n psubw m2, m6, m4\n ITX_MULSUB_2W 2, 5, 1, 4, 7, 1931, 3612 ;t42a, t53a\n mova [rsp+gprsize*2+16*45], m2 ;t42a\n mova [rsp+gprsize*2+16*46], m0 ;t43\n mova [rsp+gprsize*2+16*55], m3 ;t52\n mova [rsp+gprsize*2+16*56], m5 ;t53a\n\n mova m0, [rsp+gprsize*2+16*47] ;in13\n mova m1, [rsp+gprsize*2+16*53] ;in19\n pmulhrsw m3, m0, [o(pw_3889x8)] ;t51a\n pmulhrsw m0, [o(pw_1285x8)] ;t44a\n pmulhrsw m2, m1, [o(pw_3659x8)] ;t50a\n pmulhrsw m1, [o(pw_m1842x8)] ;t45a\n psubsw m4, m0, m1 ;t45\n paddsw m0, m1 ;t44\n psubsw m5, m3, m2 ;t50\n paddsw m3, m2 ;t51\n ITX_MULSUB_2W 5, 4, 1, 2, 7, 3920, 1189 ;t45a, t50a\n mova m6, m0\n mova [rsp+gprsize*2+16*48], m5 ;t45a\n mova [rsp+gprsize*2+16*53], m4 ;t50a\n mova [rsp+gprsize*2+16*54], m3 ;t51\n\n mova m0, [rsp+gprsize*2+16*51] ;in29\n mova m1, [rsp+gprsize*2+16*49] ;in3\n pmulhrsw m3, m0, [o(pw_3102x8)] ;t49a\n pmulhrsw m0, [o(pw_2675x8)] ;t46a\n pmulhrsw m2, m1, [o(pw_4085x8)] ;t48a\n pmulhrsw m1, [o(pw_m301x8)] ;t47a\n psubsw m5, m1, m0 ;t46\n paddsw m0, m1 ;t47\n psubsw m4, m2, m3 ;t49\n paddsw m3, m2 ;t48\n\nALIGN function_align\n.main2:\n pxor m2, m2\n psubw m2, m5\n ITX_MULSUB_2W 2, 4, 1, 5, 7, 3920, 1189 ;t46a, t49a\n\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m5, m0, m6 ;t44a\n paddsw m0, m6 ;t47a\n psubsw m6, m3, m1 ;t51a\n paddsw m3, m1 ;t48a\n mova [rsp+gprsize*2+16*50], m0 ;t47a\n mova [rsp+gprsize*2+16*51], m3 ;t48a\n pxor m1, m1\n psubw m3, m1, m5\n ITX_MULSUB_2W 3, 6, 0, 5, 7, 3406, 2276 ;t44, t51\n mova [rsp+gprsize*2+16*47], m3 ;t44\n mova [rsp+gprsize*2+16*54], m6 ;t51\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m3, [rsp+gprsize*2+16*53] ;t50a\n psubsw m5, m2, m0 ;t45\n paddsw m2, m0 ;t46\n psubsw m6, m4, m3 ;t50\n paddsw m4, m3 ;t49\n psubw m1, m5\n ITX_MULSUB_2W 1, 6, 0, 3, 7, 3406, 2276 ;t45a, t50a\n mova [rsp+gprsize*2+16*48], m1 ;t45a\n mova [rsp+gprsize*2+16*49], m2 ;t46\n mova [rsp+gprsize*2+16*52], m4 ;t49\n mova [rsp+gprsize*2+16*53], m6 ;t50a\n\n mova m0, [rsp+gprsize*2+16*43] ;t40\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m3, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*58] ;t55\n psubsw m4, m0, m2 ;t43a\n paddsw m0, m2 ;t40a\n psubsw m5, m1, m3 ;t52a\n paddsw m1, m3 ;t55a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t43, t52\n mova [rsp+gprsize*2+16*43], m0 ;t40a\n mova [rsp+gprsize*2+16*46], m5 ;t43\n mova [rsp+gprsize*2+16*55], m4 ;t52\n mova [rsp+gprsize*2+16*58], m1 ;t55a\n\n mova m0, [rsp+gprsize*2+16*44] ;t41a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*57] ;t54a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t41\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t54\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 3406, 2276 ;t42a, t53a\n mova [rsp+gprsize*2+16*44], m0 ;t41\n mova [rsp+gprsize*2+16*45], m5 ;t42a\n mova [rsp+gprsize*2+16*56], m4 ;t53a\n mova [rsp+gprsize*2+16*57], m1 ;t54\n\n mova m0, [rsp+gprsize*2+16*41] ;t38a\n mova m2, [rsp+gprsize*2+16*40] ;t37a\n mova m3, [rsp+gprsize*2+16*61] ;t58a\n mova m1, [rsp+gprsize*2+16*60] ;t57a\n psubsw m4, m0, m2 ;t37\n paddsw m0, m2 ;t38\n psubsw m5, m1, m3 ;t58\n paddsw m1, m3 ;t57\n pxor m6, m6\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 799, 4017 ;t37a, t58a\n mova [rsp+gprsize*2+16*41], m0 ;t38\n mova [rsp+gprsize*2+16*40], m3 ;t37a\n mova [rsp+gprsize*2+16*61], m5 ;t58a\n mova [rsp+gprsize*2+16*60], m1 ;t57\n\n mova m0, [rsp+gprsize*2+16*42] ;t39\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*59] ;t56\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t39a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t56a\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 799, 4017 ;t36, t59\n mova [rsp+gprsize*2+16*42], m0 ;t39a\n mova [rsp+gprsize*2+16*39], m3 ;t36\n mova [rsp+gprsize*2+16*62], m5 ;t59\n mova [rsp+gprsize*2+16*59], m1 ;t56a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m2, [rsp+gprsize*2+16*38] ;t35\n mova m3, [rsp+gprsize*2+16*63] ;t60\n mova m1, [rsp+gprsize*2+16*66] ;t63\n psubsw m4, m0, m2 ;t35a\n paddsw m0, m2 ;t32a\n psubsw m5, m1, m3 ;t60a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t35, t60\n mova [rsp+gprsize*2+16*35], m0 ;t32a\n mova [rsp+gprsize*2+16*38], m5 ;t35\n mova [rsp+gprsize*2+16*63], m4 ;t60\n mova [rsp+gprsize*2+16*66], m1 ;t63a\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m2, [rsp+gprsize*2+16*37] ;t34a\n mova m3, [rsp+gprsize*2+16*64] ;t61a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n psubsw m4, m0, m2 ;t34\n paddsw m0, m2 ;t33\n psubsw m5, m1, m3 ;t61\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 799, 4017 ;t34a, t61a\n\n mova m2, [rsp+gprsize*2+16*41] ;t38\n mova m3, [rsp+gprsize*2+16*60] ;t57\n psubsw m6, m0, m2 ;t38a\n paddsw m0, m2 ;t33a\n psubsw m2, m1, m3 ;t57a\n paddsw m1, m3 ;t62a\n mova [rsp+gprsize*2+16*36], m0 ;t33a\n mova [rsp+gprsize*2+16*65], m1 ;t62a\n ITX_MULSUB_2W 2, 6, 0, 3, 7, 1567, 3784 ;t38, t57\n mova [rsp+gprsize*2+16*41], m2 ;t38\n mova [rsp+gprsize*2+16*60], m6 ;t57\n\n mova m2, [rsp+gprsize*2+16*40] ;t37\n mova m3, [rsp+gprsize*2+16*61] ;t58\n psubsw m0, m5, m2 ;t37\n paddsw m5, m2 ;t34\n psubsw m1, m4, m3 ;t58\n paddsw m4, m3 ;t61\n ITX_MULSUB_2W 1, 0, 2, 3, 7, 1567, 3784 ;t37a, t58a\n mova [rsp+gprsize*2+16*37], m5 ;t34\n mova [rsp+gprsize*2+16*64], m4 ;t61\n mova [rsp+gprsize*2+16*40], m1 ;t37a\n mova [rsp+gprsize*2+16*61], m0 ;t58a\n\n mova m0, [rsp+gprsize*2+16*38] ;t35\n mova m2, [rsp+gprsize*2+16*39] ;t36\n mova m3, [rsp+gprsize*2+16*62] ;t59\n mova m1, [rsp+gprsize*2+16*63] ;t60\n psubsw m4, m0, m2 ;t36a\n paddsw m0, m2 ;t35a\n psubsw m5, m1, m3 ;t59a\n paddsw m1, m3 ;t60a\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t36, t59\n mova [rsp+gprsize*2+16*38], m0 ;t35a\n mova [rsp+gprsize*2+16*39], m5 ;t36\n mova [rsp+gprsize*2+16*62], m4 ;t59\n mova [rsp+gprsize*2+16*63], m1 ;t60a\n\n mova m0, [rsp+gprsize*2+16*35] ;t32a\n mova m2, [rsp+gprsize*2+16*42] ;t39a\n mova m3, [rsp+gprsize*2+16*59] ;t56a\n mova m1, [rsp+gprsize*2+16*66] ;t63a\n psubsw m4, m0, m2 ;t39\n paddsw m0, m2 ;t32\n psubsw m5, m1, m3 ;t56\n paddsw m1, m3 ;t63\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t39a, t56a\n mova [rsp+gprsize*2+16*35], m0 ;t32\n mova [rsp+gprsize*2+16*42], m5 ;t39a\n mova [rsp+gprsize*2+16*59], m4 ;t56a\n mova [rsp+gprsize*2+16*66], m1 ;t63\n\n mova m0, [rsp+gprsize*2+16*50] ;t47a\n mova m2, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*51] ;t48a\n psubsw m4, m0, m2 ;t40\n paddsw m0, m2 ;t47\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t48\n pxor m6, m6\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t40a, t55a\n mova [rsp+gprsize*2+16*50], m0 ;t47\n mova [rsp+gprsize*2+16*43], m3 ;t40a\n mova [rsp+gprsize*2+16*58], m5 ;t55a\n mova [rsp+gprsize*2+16*51], m1 ;t48\n\n mova m0, [rsp+gprsize*2+16*49] ;t46\n mova m2, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*52] ;t49\n psubsw m4, m0, m2 ;t41a\n paddsw m0, m2 ;t46a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t49a\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t41, t54\n mova [rsp+gprsize*2+16*49], m0 ;t46a\n mova [rsp+gprsize*2+16*44], m3 ;t41\n mova [rsp+gprsize*2+16*57], m5 ;t54\n mova [rsp+gprsize*2+16*52], m1 ;t49a\n\n mova m0, [rsp+gprsize*2+16*48] ;t45a\n mova m2, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*53] ;t50a\n psubsw m4, m0, m2 ;t42\n paddsw m0, m2 ;t45\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t50\n psubw m3, m6, m4\n ITX_MULSUB_2W 3, 5, 2, 4, 7, 1567, 3784 ;t42a, t53a\n mova [rsp+gprsize*2+16*48], m0 ;t45\n mova [rsp+gprsize*2+16*45], m3 ;t42a\n mova [rsp+gprsize*2+16*56], m5 ;t53a\n mova [rsp+gprsize*2+16*53], m1 ;t50\n\n mova m0, [rsp+gprsize*2+16*47] ;t44\n mova m2, [rsp+gprsize*2+16*46] ;t43\n mova m5, [rsp+gprsize*2+16*55] ;t52\n mova m1, [rsp+gprsize*2+16*54] ;t51\n psubsw m3, m0, m2 ;t43a\n paddsw m0, m2 ;t44a\n psubsw m4, m1, m5 ;t52a\n paddsw m1, m5 ;t51a\n psubw m5, m6, m3\n ITX_MULSUB_2W 5, 4, 2, 3, 7, 1567, 3784 ;t43, t52\n\n mova m2, [rsp+gprsize*2+16*38] ;t35a\n mova m3, [rsp+gprsize*2+16*31] ;tmp[28]\n psubsw m6, m2, m0 ;t44\n paddsw m2, m0 ;t35\n psubsw m0, m3, m2 ;out35\n paddsw m2, m3 ;out28\n mova m3, [rsp+gprsize*2+16*63] ;t60a\n mova [rsp+gprsize*2+16*38], m0 ;out35\n mova [rsp+gprsize*2+16*31], m2 ;out28\n psubsw m0, m3, m1 ;t51\n paddsw m3, m1 ;t60\n ITX_MULSUB_2W 0, 6, 1, 2, 7, 2896, 2896 ;t44a, t51a\n mova m2, [rsp+gprsize*2+16*6 ] ;tmp[3]\n psubsw m1, m2, m3 ;out60\n paddsw m2, m3 ;out3\n mova m3, [rsp+gprsize*2+16*22] ;tmp[19]\n mova [rsp+gprsize*2+16*63], m1 ;out60\n mova [rsp+gprsize*2+16*6 ], m2 ;out3\n psubsw m1, m3, m0 ;out44\n paddsw m3, m0 ;out19\n mova m2, [rsp+gprsize*2+16*15] ;tmp[12]\n\n mova m0, [rsp+gprsize*2+16*39] ;t36\n mova [rsp+gprsize*2+16*47], m1 ;out44\n mova [rsp+gprsize*2+16*22], m3 ;out19\n mova m1, [rsp+gprsize*2+16*62] ;t59\n psubsw m3, m2, m6 ;out51\n paddsw m2, m6 ;out12\n mova [rsp+gprsize*2+16*54], m3 ;out51\n mova [rsp+gprsize*2+16*15], m2 ;out12\n psubsw m2, m0, m5 ;t43a\n paddsw m0, m5 ;t36a\n mova m5, [rsp+gprsize*2+16*30] ;tmp[27]\n psubsw m3, m1, m4 ;t52a\n paddsw m1, m4 ;t59a\n ITX_MULSUB_2W 3, 2, 4, 6, 7, 2896, 2896 ;t43, t52\n mova m4, [rsp+gprsize*2+16*7 ] ;tmp[4 ]\n psubsw m6, m5, m0 ;out36\n paddsw m5, m0 ;out27\n psubsw m0, m4, m1 ;out59\n paddsw m4, m1 ;out4\n mova [rsp+gprsize*2+16*39], m6 ;out36\n mova [rsp+gprsize*2+16*30], m5 ;out27\n mova [rsp+gprsize*2+16*62], m0 ;out59\n mova [rsp+gprsize*2+16*7 ], m4 ;out4\n mova m0, [rsp+gprsize*2+16*23] ;tmp[20]\n mova m5, [rsp+gprsize*2+16*14] ;tmp[11]\n psubsw m4, m0, m3 ;out43\n paddsw m0, m3 ;out20\n psubsw m6, m5, m2 ;out52\n paddsw m5, m2 ;out11\n mova [rsp+gprsize*2+16*46], m4 ;out43\n mova [rsp+gprsize*2+16*23], m0 ;out20\n mova [rsp+gprsize*2+16*55], m6 ;out52\n mova [rsp+gprsize*2+16*14], m5 ;out11\n\n mova m0, [rsp+gprsize*2+16*40] ;t37a\n mova m5, [rsp+gprsize*2+16*45] ;t42a\n mova m3, [rsp+gprsize*2+16*56] ;t53a\n mova m1, [rsp+gprsize*2+16*61] ;t58a\n mova m2, [rsp+gprsize*2+16*29] ;tmp[26]\n psubsw m4, m0, m5 ;t42\n paddsw m0, m5 ;t37\n psubsw m5, m1, m3 ;t53\n paddsw m1, m3 ;t58\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t43, t52\n mova m3, [rsp+gprsize*2+16*8 ] ;tmp[5 ]\n psubsw m6, m2, m0 ;out37\n paddsw m2, m0 ;out26\n psubsw m0, m3, m1 ;out58\n paddsw m3, m1 ;out5\n mova [rsp+gprsize*2+16*40], m6 ;out37\n mova [rsp+gprsize*2+16*29], m2 ;out26\n mova [rsp+gprsize*2+16*61], m0 ;out58\n mova [rsp+gprsize*2+16*8 ], m3 ;out5\n mova m0, [rsp+gprsize*2+16*24] ;tmp[21]\n mova m1, [rsp+gprsize*2+16*13] ;tmp[10]\n psubsw m2, m0, m5 ;out42\n paddsw m0, m5 ;out21\n psubsw m3, m1, m4 ;out53\n paddsw m1, m4 ;out10\n mova [rsp+gprsize*2+16*45], m2 ;out42\n mova [rsp+gprsize*2+16*24], m0 ;out21\n mova [rsp+gprsize*2+16*56], m3 ;out53\n mova [rsp+gprsize*2+16*13], m1 ;out10\n\n mova m0, [rsp+gprsize*2+16*41] ;t38\n mova m5, [rsp+gprsize*2+16*44] ;t41\n mova m3, [rsp+gprsize*2+16*57] ;t54\n mova m1, [rsp+gprsize*2+16*60] ;t57\n mova m2, [rsp+gprsize*2+16*28] ;tmp[25]\n psubsw m4, m0, m5 ;t41a\n paddsw m0, m5 ;t38a\n psubsw m5, m1, m3 ;t54a\n paddsw m1, m3 ;t57a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t41a, t54a\n mova m3, [rsp+gprsize*2+16*9 ] ;tmp[6 ]\n psubsw m6, m2, m0 ;out38\n paddsw m2, m0 ;out25\n psubsw m0, m3, m1 ;out57\n paddsw m3, m1 ;out6\n mova [rsp+gprsize*2+16*41], m6 ;out38\n mova [rsp+gprsize*2+16*28], m2 ;out25\n mova [rsp+gprsize*2+16*60], m0 ;out57\n mova [rsp+gprsize*2+16*9 ], m3 ;out6\n mova m0, [rsp+gprsize*2+16*25] ;tmp[22]\n mova m1, [rsp+gprsize*2+16*12] ;tmp[9 ]\n psubsw m2, m0, m5 ;out41\n paddsw m0, m5 ;out22\n psubsw m3, m1, m4 ;out54\n paddsw m1, m4 ;out9\n mova [rsp+gprsize*2+16*44], m2 ;out41\n mova [rsp+gprsize*2+16*25], m0 ;out22\n mova [rsp+gprsize*2+16*57], m3 ;out54\n mova [rsp+gprsize*2+16*12], m1 ;out9\n\n mova m0, [rsp+gprsize*2+16*42] ;t39a\n mova m5, [rsp+gprsize*2+16*43] ;t40a\n mova m3, [rsp+gprsize*2+16*58] ;t55a\n mova m1, [rsp+gprsize*2+16*59] ;t56a\n mova m2, [rsp+gprsize*2+16*27] ;tmp[24]\n psubsw m4, m0, m5 ;t40\n paddsw m0, m5 ;t39\n psubsw m5, m1, m3 ;t55\n paddsw m1, m3 ;t56\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t40a, t55a\n mova m3, [rsp+gprsize*2+16*10] ;tmp[7 ]\n psubsw m6, m2, m0 ;out39\n paddsw m2, m0 ;out24\n psubsw m0, m3, m1 ;out56\n paddsw m3, m1 ;out7\n mova [rsp+gprsize*2+16*42], m6 ;out39\n mova [rsp+gprsize*2+16*27], m2 ;out24\n mova [rsp+gprsize*2+16*59], m0 ;out56\n mova [rsp+gprsize*2+16*10], m3 ;out7\n mova m0, [rsp+gprsize*2+16*26] ;tmp[23]\n mova m1, [rsp+gprsize*2+16*11] ;tmp[8 ]\n psubsw m2, m0, m5 ;out40\n paddsw m0, m5 ;out23\n psubsw m3, m1, m4 ;out55\n paddsw m1, m4 ;out8\n mova [rsp+gprsize*2+16*43], m2 ;out40\n mova [rsp+gprsize*2+16*26], m0 ;out23\n mova [rsp+gprsize*2+16*58], m3 ;out55\n mova [rsp+gprsize*2+16*11], m1 ;out8\n\n mova m0, [rsp+gprsize*2+16*37] ;t34\n mova m5, [rsp+gprsize*2+16*48] ;t45\n mova m3, [rsp+gprsize*2+16*53] ;t50\n mova m1, [rsp+gprsize*2+16*64] ;t61\n mova m2, [rsp+gprsize*2+16*32] ;tmp[29]\n psubsw m4, m0, m5 ;t45a\n paddsw m0, m5 ;t34a\n psubsw m5, m1, m3 ;t50a\n paddsw m1, m3 ;t61a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*5 ] ;tmp[2 ]\n psubsw m6, m2, m0 ;out34\n paddsw m2, m0 ;out29\n psubsw m0, m3, m1 ;out61\n paddsw m3, m1 ;out2\n mova [rsp+gprsize*2+16*37], m6 ;out34\n mova [rsp+gprsize*2+16*32], m2 ;out29\n mova [rsp+gprsize*2+16*64], m0 ;out61\n mova [rsp+gprsize*2+16*5 ], m3 ;out2\n mova m0, [rsp+gprsize*2+16*21] ;tmp[18]\n mova m1, [rsp+gprsize*2+16*16] ;tmp[13]\n psubsw m2, m0, m5 ;out45\n paddsw m0, m5 ;out18\n psubsw m3, m1, m4 ;out50\n paddsw m1, m4 ;out13\n mova [rsp+gprsize*2+16*48], m2 ;out45\n mova [rsp+gprsize*2+16*21], m0 ;out18\n mova [rsp+gprsize*2+16*53], m3 ;out50\n mova [rsp+gprsize*2+16*16], m1 ;out13\n\n mova m0, [rsp+gprsize*2+16*36] ;t33a\n mova m5, [rsp+gprsize*2+16*49] ;t46a\n mova m3, [rsp+gprsize*2+16*52] ;t49a\n mova m1, [rsp+gprsize*2+16*65] ;t62a\n mova m2, [rsp+gprsize*2+16*33] ;tmp[30]\n psubsw m4, m0, m5 ;t46\n paddsw m0, m5 ;t33\n psubsw m5, m1, m3 ;t49\n paddsw m1, m3 ;t62\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t45, t50\n mova m3, [rsp+gprsize*2+16*4 ] ;tmp[1 ]\n psubsw m6, m2, m0 ;out33\n paddsw m2, m0 ;out30\n psubsw m0, m3, m1 ;out62\n paddsw m3, m1 ;out1\n mova [rsp+gprsize*2+16*36], m6 ;out33\n mova [rsp+gprsize*2+16*33], m2 ;out30\n mova [rsp+gprsize*2+16*65], m0 ;out62\n mova [rsp+gprsize*2+16*4 ], m3 ;out1\n mova m0, [rsp+gprsize*2+16*20] ;tmp[17]\n mova m1, [rsp+gprsize*2+16*17] ;tmp[14]\n psubsw m2, m0, m5 ;out46\n paddsw m0, m5 ;out17\n psubsw m3, m1, m4 ;out49\n paddsw m1, m4 ;out14\n mova [rsp+gprsize*2+16*49], m2 ;out46\n mova [rsp+gprsize*2+16*20], m0 ;out17\n mova [rsp+gprsize*2+16*52], m3 ;out49\n mova [rsp+gprsize*2+16*17], m1 ;out14\n\n mova m0, [rsp+gprsize*2+16*35] ;t32\n mova m5, [rsp+gprsize*2+16*50] ;t47\n mova m3, [rsp+gprsize*2+16*51] ;t48\n mova m1, [rsp+gprsize*2+16*66] ;t63\n mova m2, [rsp+gprsize*2+16*34] ;tmp[31]\n psubsw m4, m0, m5 ;t47a\n paddsw m0, m5 ;t32a\n psubsw m5, m1, m3 ;t48a\n paddsw m1, m3 ;t63a\n ITX_MULSUB_2W 5, 4, 3, 6, 7, 2896, 2896 ;t47, t48\n mova m3, [rsp+gprsize*2+16*3 ] ;tmp[0 ]\n psubsw m6, m2, m0 ;out32\n paddsw m2, m0 ;out31\n psubsw m0, m3, m1 ;out63\n paddsw m3, m1 ;out0\n mova [rsp+gprsize*2+16*35], m6 ;out32\n mova [rsp+gprsize*2+16*34], m2 ;out31\n mova [rsp+gprsize*2+16*66], m0 ;out63\n mova [rsp+gprsize*2+16*3 ], m3 ;out0\n mova m0, [rsp+gprsize*2+16*19] ;tmp[16]\n mova m1, [rsp+gprsize*2+16*18] ;tmp[15]\n psubsw m2, m0, m5 ;out47\n paddsw m0, m5 ;out16\n psubsw m3, m1, m4 ;out48\n paddsw m1, m4 ;out15\n mova [rsp+gprsize*2+16*50], m2 ;out47\n mova [rsp+gprsize*2+16*19], m0 ;out16\n mova [rsp+gprsize*2+16*51], m3 ;out48\n mova [rsp+gprsize*2+16*18], m1 ;out15\n ret\n\n\ncglobal inv_txfm_add_dct_dct_64x16, 4, 6, 8, 16*132, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x16_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 16\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x16).end)]\n\n.body:\n pmulhrsw m0, m2\n movd m2, [o(pw_2048)] ;intentionally rip-relative\n pmulhrsw m0, m1\n pmulhrsw m0, m2\n pshuflw m0, m0, q0000\n punpcklwd m0, m0\n pxor m7, m7\n\n.loop:\n mova m1, [dstq+16*0]\n mova m3, [dstq+16*1]\n mova m5, [dstq+16*2]\n mova m6, [dstq+16*3]\n punpckhbw m2, m1, m7\n punpcklbw m1, m7\n punpckhbw m4, m3, m7\n punpcklbw m3, m7\n paddw m2, m0\n paddw m1, m0\n paddw m4, m0\n paddw m3, m0\n packuswb m1, m2\n packuswb m3, m4\n punpckhbw m2, m5, m7\n punpcklbw m5, m7\n punpckhbw m4, m6, m7\n punpcklbw m6, m7\n paddw m2, m0\n paddw m5, m0\n paddw m4, m0\n paddw m6, m0\n packuswb m5, m2\n packuswb m6, m4\n mova [dstq+16*0], m1\n mova [dstq+16*1], m3\n mova [dstq+16*2], m5\n mova [dstq+16*3], m6\n add dstq, strideq\n dec r3d\n jg .loop\n jmp tx2q\n\n.end:\n RET\n\n\n%macro LOAD_4ROWS 2-3 0 ;src, stride, is_rect2\n\n%if %3\n mova m3, [o(pw_2896x8)]\n pmulhrsw m0, m3, [%1+%2*0]\n pmulhrsw m1, m3, [%1+%2*1]\n pmulhrsw m2, m3, [%1+%2*2]\n pmulhrsw m3, [%1+%2*3]\n%else\n mova m0, [%1+%2*0]\n mova m1, [%1+%2*1]\n mova m2, [%1+%2*2]\n mova m3, [%1+%2*3]\n%endif\n%endmacro\n\n%macro LOAD_4ROWS_H 2 ;src, stride\n mova m4, [%1+%2*0]\n mova m5, [%1+%2*1]\n mova m6, [%1+%2*2]\n mova m7, [%1+%2*3]\n%endmacro\n\ncglobal idct_64x16_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n mov r3d, 2\n mov [rsp+gprsize*2+16*67], dstq\n lea dstq, [rsp+gprsize+16*68]\n\n.pass1_loop:\n LOAD_4ROWS coeffq+32*0, 32*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+32*4, 32*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+32*2, 32*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+32*1, 32*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+32*17, 32*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+32*24, 32\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+32*0, 32\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+32*8, 32\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+32*16, 32\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x16_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+32*24, 32\n\n add coeffq, 16\n add dstq, 16\n dec r3d\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*2+16*67]\n sub coeffq, 32\n mov r3d, 4\n\n.pass2_loop:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end1)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end1:\n pxor m7, m7\n REPX {mova [coeffq+16*x], m7}, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop\n\n mov r3d, 4\n lea coeffq, [rsp+gprsize+16*68]\n.pass2_loop2:\n mov [rsp+gprsize*1+16*67], r3d\n\n LOAD_4ROWS coeffq+16*0, 32*2\n LOAD_4ROWS_H coeffq+16*1, 32*2\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+16*2, 32*2\n LOAD_4ROWS_H coeffq+16*3, 32*2\n call m(idct_16x8_internal).main\n\n mov r3, dstq\n lea tx2q, [o(m(idct_64x16_internal).end2)]\n lea dstq, [dstq+strideq*8]\n jmp m(idct_8x8_internal).end\n\n.end2:\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x16_internal).end3)]\n mov dstq, r3\n jmp m(idct_8x8_internal).end\n\n.end3:\n\n add coeffq, 16*16\n mov r3d, [rsp+gprsize*1+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n add dstq, 8\n mov [rsp+gprsize*2+16*67], dstq\n dec r3d\n jg .pass2_loop2\n ret\n\n\ncglobal inv_txfm_add_dct_dct_32x64, 4, 6, 8, 16*68, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_32x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n mov [coeffq], eobd\n pmulhrsw m0, m1\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_32x64).end)]\n jmp m(inv_txfm_add_dct_dct_32x8).body\n\n.end:\n RET\n\n\ncglobal idct_32x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n\n.pass1_loop:\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*19], m0 ;in1\n mova [rsp+gprsize+16*26], m1 ;in3\n mova [rsp+gprsize+16*23], m2 ;in5\n mova [rsp+gprsize+16*22], m3 ;in7\n mova [rsp+gprsize+16*21], m4 ;in9\n mova [rsp+gprsize+16*24], m5 ;in11\n mova [rsp+gprsize+16*25], m6 ;in13\n mova [rsp+gprsize+16*20], m7 ;in15\n\n mov tx2d, [rsp+gprsize*1+16*67]\n test tx2d, tx2d\n jl .fast\n\n.full:\n LOAD_8ROWS coeffq+64*0, 64*4, 1\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*33], m0 ;in17\n mova [rsp+gprsize+16*28], m1 ;in19\n mova [rsp+gprsize+16*29], m2 ;in21\n mova [rsp+gprsize+16*32], m3 ;in23\n mova [rsp+gprsize+16*31], m4 ;in25\n mova [rsp+gprsize+16*30], m5 ;in27\n mova [rsp+gprsize+16*27], m6 ;in29\n mova [rsp+gprsize+16*34], m7 ;in31\n\n call m(idct_8x32_internal).main\n jmp .pass1_end\n\n.fast:\n LOAD_4ROWS coeffq, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n\n SAVE_7ROWS rsp+gprsize+16*3, 16\n LOAD_4ROWS coeffq+128*1, 256, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n call m(idct_8x32_internal).main_fast\n\n.pass1_end:\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_32x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS coeffq+64*24, 64\n\n add coeffq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*2+16*67]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x32, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x32_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_16384)]\n pmulhrsw m0, m1\n mov [coeffq], eobd\n mov r3d, 32\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\n.end:\n RET\n\ncglobal idct_64x32_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*2+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*4+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8, 1\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8, 1\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4, 1\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2, 1\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2, 1\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n lea tx2q, [o(m(idct_64x32_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*3+16*67]\n mov eobd, [rsp+gprsize*1+16*67]\n lea dstq, [dstq+32]\n mov [rsp+gprsize*1+16*35], eobd\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n.pass2_end:\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x32_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n lea tx2q, [o(m(idct_64x32_internal).pass2_end)]\n add coeffq, 16*32\n mov dstq, [rsp+gprsize*2+16*35]\n mov r3, [rsp+gprsize*3+16*35]\n dec r3\n jg m(idct_32x32_internal).pass2_loop\n\n.pass2_end2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea tx2q, [o(m(idct_32x32_internal).pass2_end)]\n mov r3, 4\n jmp m(idct_32x32_internal).pass2_loop\n\n\ncglobal inv_txfm_add_dct_dct_64x64, 4, 6, 8, 16*197, dst, stride, coeff, eob, tx2\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n test eobd, eobd\n jz .dconly\n\n call m(idct_64x64_internal)\n RET\n\n.dconly:\n movd m1, [o(pw_2896x8)]\n pmulhrsw m0, m1, [coeffq]\n movd m2, [o(pw_8192)]\n mov [coeffq], eobd\n mov r3d, 64\n lea tx2q, [o(m(inv_txfm_add_dct_dct_64x32).end)]\n jmp m(inv_txfm_add_dct_dct_64x16).body\n\ncglobal idct_64x64_internal, 0, 0, 0, dst, stride, coeff, eob, tx2\n %undef cmp\n\n mov r5, 4\n mov r4, 2\n sub eobd, 136\n cmovge r4, r5\n\n%if ARCH_X86_32\n LEA r5, $$\n%endif\n\n mov [rsp+gprsize*1+16*67], eobd\n mov r3, r4\n mov [rsp+gprsize*4+16*67], coeffq\n mov [rsp+gprsize*3+16*67], dstq\n lea dstq, [rsp+gprsize+16*69]\n mov [rsp+gprsize*2+16*67], dstq\n\n.pass1_loop:\n LOAD_4ROWS coeffq+64*0, 64*8\n pxor m4, m4\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_8x8_internal).main\n SAVE_7ROWS rsp+gprsize+16*3, 16\n\n pxor m4, m4\n LOAD_4ROWS coeffq+64*4, 64*8\n\n REPX {mova x, m4}, m5, m6, m7\n call m(idct_16x8_internal).main\n mova m7, [rsp+gprsize+16*0]\n SAVE_8ROWS rsp+gprsize+16*11, 16\n\n LOAD_8ROWS coeffq+64*2, 64*4\n mova [rsp+gprsize+16*19], m0\n mova [rsp+gprsize+16*26], m1\n mova [rsp+gprsize+16*23], m2\n mova [rsp+gprsize+16*22], m3\n mova [rsp+gprsize+16*21], m4\n mova [rsp+gprsize+16*24], m5\n mova [rsp+gprsize+16*25], m6\n mova [rsp+gprsize+16*20], m7\n\n call m(idct_8x32_internal).main_fast\n SAVE_8ROWS rsp+gprsize+16*3, 16\n\n LOAD_8ROWS coeffq+64*1, 64*2\n mova [rsp+gprsize+16*35], m0 ;in1\n mova [rsp+gprsize+16*49], m1 ;in3\n mova [rsp+gprsize+16*43], m2 ;in5\n mova [rsp+gprsize+16*41], m3 ;in7\n mova [rsp+gprsize+16*39], m4 ;in9\n mova [rsp+gprsize+16*45], m5 ;in11\n mova [rsp+gprsize+16*47], m6 ;in13\n mova [rsp+gprsize+16*37], m7 ;in15\n\n LOAD_8ROWS coeffq+64*17, 64*2\n mova [rsp+gprsize+16*63], m0 ;in17\n mova [rsp+gprsize+16*53], m1 ;in19\n mova [rsp+gprsize+16*55], m2 ;in21\n mova [rsp+gprsize+16*61], m3 ;in23\n mova [rsp+gprsize+16*59], m4 ;in25\n mova [rsp+gprsize+16*57], m5 ;in27\n mova [rsp+gprsize+16*51], m6 ;in29\n mova [rsp+gprsize+16*65], m7 ;in31\n\n call m(idct_16x64_internal).main\n\n LOAD_8ROWS rsp+gprsize+16*3, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end:\n SAVE_8ROWS coeffq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*11, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end1)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end1:\n SAVE_8ROWS coeffq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*19, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end2)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end2:\n SAVE_8ROWS coeffq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*27, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end3)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end3:\n SAVE_8ROWS coeffq+64*24, 64\n LOAD_8ROWS rsp+gprsize+16*35, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end4)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end4:\n SAVE_8ROWS dstq+64*0, 64\n LOAD_8ROWS rsp+gprsize+16*43, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end5)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end5:\n SAVE_8ROWS dstq+64*8, 64\n LOAD_8ROWS rsp+gprsize+16*51, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end6)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end6:\n SAVE_8ROWS dstq+64*16, 64\n LOAD_8ROWS rsp+gprsize+16*59, 16\n mova [rsp+gprsize+16*0], m7\n mova m7, [o(pw_8192)]\n lea tx2q, [o(m(idct_64x64_internal).pass1_end7)]\n jmp m(idct_8x8_internal).pass1_end1\n\n.pass1_end7:\n SAVE_8ROWS dstq+64*24, 64\n\n add coeffq, 16\n add dstq, 16\n dec r3\n jg .pass1_loop\n\n.pass2:\n mov dstq, [rsp+gprsize*3+16*67]\n mov coeffq, [rsp+gprsize*2+16*67]\n lea dstq, [dstq+32]\n mov r3, 4\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n jmp m(idct_16x64_internal).pass2_loop\n\n.pass2_end:\n LOAD_8ROWS rsp+gprsize+16*35, 16\n lea dstq, [dstq+strideq*2]\n add rsp, 16*32\n mova [rsp+gprsize+16*0], m7\n lea r3, [o(m(idct_64x64_internal).pass2_end1)]\n jmp m(idct_8x32_internal).end2\n\n.pass2_end1:\n add coeffq, 16*32\n sub rsp, 16*32\n\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, [rsp+gprsize*3+16*67]\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_64x64_internal).pass2_end)]\n\n dec r3\n jg m(idct_16x64_internal).pass2_loop\n\n.pass2_end2:\n mov coeffq, [rsp+gprsize*4+16*67]\n mov dstq, [rsp+gprsize*2+16*67]\n mov r3, 4\n sub dstq, 72\n lea r4, [dstq+8]\n mov [rsp+gprsize*2+16*67], r4\n lea r4, [o(m(idct_16x64_internal).end1)]\n jmp m(idct_16x64_internal).pass2_loop\n"}}},{"rowIdx":488,"cells":{"commit":{"kind":"string","value":"92edd252bd8dd99c43ad3965817bd409881fbce0"},"subject":{"kind":"string","value":"x86: Add mc avg/w_avg/mask AVX-512 (Ice Lake) asm"},"message":{"kind":"string","value":"x86: Add mc avg/w_avg/mask AVX-512 (Ice Lake) asm\n"},"repos":{"kind":"string","value":"xiph/rav1e,xiph/rav1e,xiph/rav1e"},"file_path":{"kind":"string","value":"src/x86/mc.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583503017,"string":"1,583,503,017"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nbidir_sctr_w4: dd 0, 1, 8, 9, 2, 3, 10, 11, 4, 5, 12, 13, 6, 7, 14, 15\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\nspel_h_perm16a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\nspel_h_perm16b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 36, 37, 38, 39, 37, 38, 39, 40, 38, 39, 40, 41, 39, 40, 41, 42\n db 44, 45, 46, 47, 45, 46, 47, 48, 46, 47, 48, 49, 47, 48, 49, 50\nspel_h_perm16c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\n db 48, 49, 50, 51, 49, 50, 51, 52, 50, 51, 52, 53, 51, 52, 53, 54\nspel_h_perm32a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\nspel_h_perm32b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 20, 21, 22, 23, 21, 22, 23, 24, 22, 23, 24, 25, 23, 24, 25, 26\n db 28, 29, 30, 31, 29, 30, 31, 32, 30, 31, 32, 33, 31, 32, 33, 34\nspel_h_perm32c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\nspel_hv_perm4a: db 8, 9, 16, 17, 10, 11, 18, 19, 12, 13, 20, 21, 14, 15, 22, 23\n db 16, 17, 24, 25, 18, 19, 26, 27, 20, 21, 28, 29, 22, 23, 30, 31\nspel_hv_perm4b: db 24, 25, 32, 33, 26, 27, 34, 35, 28, 29, 36, 37, 30, 31, 38, 39\n db 32, 33, 40, 41, 34, 35, 42, 43, 36, 37, 44, 45, 38, 39, 46, 47\n db 40, 41, 48, 49, 42, 43, 50, 51, 44, 45, 52, 53, 46, 47, 54, 55\n db 48, 49, 56, 57, 50, 51, 58, 59, 52, 53, 60, 61, 54, 55, 62, 63\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_v_shuf4: db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_2: dd 2\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\ncextern mc_warp_filter\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx512icl, 7, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx512icl, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx512icl, 4, 8, 16, 32, 64, 128\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro PREP_8TAP_H 0\n %if cpuflag(avx512)\n vpermb m10, m5, m0\n vpermb m11, m5, m1\n vpermb m12, m6, m0\n vpermb m13, m6, m1\n vpermb m14, m7, m0\n vpermb m15, m7, m1\n mova m0, m4\n mova m2, m4\n mova m1, m4\n mova m3, m4\n vpdpbusd m0, m10, m8\n vpdpbusd m2, m12, m8\n vpdpbusd m1, m11, m8\n vpdpbusd m3, m13, m8\n vpdpbusd m0, m12, m9\n vpdpbusd m2, m14, m9\n vpdpbusd m1, m13, m9\n vpdpbusd m3, m15, m9\n packssdw m0, m2\n packssdw m1, m3\n psraw m0, 2\n psraw m1, 2\n mova [tmpq+ 0], m0\n mova [tmpq+64], m1\n %else\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n pmaddubsw m1, m8\n pmaddubsw m0, m2, m8\n pmaddubsw m2, m9\n pmaddubsw m3, m9\n paddw m1, m2\n paddw m0, m3\n phaddw m0, m1, m0\n pmulhrsw m0, m4\n %endif\n%endmacro\n\n%macro PREP_8TAP_V_W4 5 ; round, weights\n movd xm0, [srcq+strideq*0]\n vpbroadcastd ym1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd ym3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd ym1, ym1, ym0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd ym3, ym3, ym2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd ym0, [srcq+strideq*0]\n vpbroadcastd ym2, [srcq+strideq*1]\n vpblendd ym1, ym1, ym0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd ym0, [srcq+strideq*2]\n vbroadcasti128 ym5, [deint_shuf4]\n vpblendd ym3, ym3, ym2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd ym2, ym3, ym1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd ym3, ym3, ym1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw ym1, ym2, ym3 ; 01 12 23 34\n vpblendd ym3, ym3, ym0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw ym2, ym3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym3, [srcq+strideq*0]\n vpbroadcastd ym4, [srcq+strideq*1]\n vpblendd ym3, ym3, ym4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd ym3, ym3, ym0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd ym0, [srcq+strideq*2]\n vpblendd ym3, ym3, ym0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb ym3, ym5 ; 67 78 89 9a\n pmaddubsw ym4, ym1, ym%2\n vperm2i128 ym1, ym2, ym3, 0x21 ; 45 56 67 78\n pmaddubsw ym2, ym%3\n paddw ym4, ym2\n mova ym2, ym3\n pmaddubsw ym3, ym%5\n paddw ym3, ym4\n pmaddubsw ym4, ym1, ym%4\n paddw ym3, ym4\n pmulhrsw ym3, ym%1\n mova [tmpq], ym3\n%endmacro\n\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\n%macro PREP_8TAP 0\n %if WIN64\n DECLARE_REG_TMP 6, 4\n %else\n DECLARE_REG_TMP 6, 7\n %endif\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep%+SUFFIX]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n%if cpuflag(avx512)\n vpbroadcastd m4, [pd_2]\n%else\n vpbroadcastd m4, [pw_8192]\n vbroadcasti128 m5, [subpel_h_shufA]\n%endif\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n%if notcpuflag(avx512)\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n%endif\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n add wq, r7\n jmp wq\n.h_w4:\n%if cpuflag(avx512)\n mov r3d, 0x4\n kmovb k1, r3d\n vbroadcasti128 ym5, [subpel_h_shufA]\n%endif\n movzx mxd, mxb\n dec srcq\n vpbroadcastd ym6, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n%if cpuflag(avx512icl)\n mova ym0, ym4\n mova ym1, ym4\n movq xm2, [srcq+strideq*0]\n movq xm3, [srcq+strideq*1]\n vpbroadcastq ym2{k1}, [srcq+strideq*2]\n vpbroadcastq ym3{k1}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pshufb ym2, ym5\n pshufb ym3, ym5\n vpdpbusd ym0, ym2, ym6\n vpdpbusd ym1, ym3, ym6\n packssdw ym0, ym1\n psraw ym0, 2\n%else\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m6\n pmaddubsw m1, m6\n phaddw m0, m1\n pmulhrsw m0, m4\n%endif\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m5, [subpel_h_shufA]\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n lea stride3q, [strideq*3]\n%endif\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n%if cpuflag(avx512)\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n%endif\n lea srcq, [srcq+strideq*(mmsize/(8*2))]\n%if cpuflag(avx512icl)\n mova m10, m4\n mova m11, m4\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n vpdpbusd m10, m1, m8\n vpdpbusd m11, m2, m8\n vpdpbusd m10, m2, m9\n vpdpbusd m11, m3, m9\n packssdw m10, m11\n psraw m0, m10, 2\n%else\n PREP_8TAP_H\n%endif\n mova [tmpq], m0\n add tmpq, mmsize\n sub hd, mmsize/(8*2)\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm16a]\n mova m6, [spel_h_perm16b]\n mova m7, [spel_h_perm16c]\n lea stride3q, [strideq*3]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m0, [srcq+strideq*1], 1\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n PREP_8TAP_H\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n.h_w32_loop:\n movu m0, [srcq+strideq*0]\n movu m1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n add tmpq, 64*2\n sub hd, 2\n jg .h_w32_loop\n RET\n%else\n xor r6d, r6d\n jmp .h_start\n%endif\n.h_w64:\n%if cpuflag(avx512)\n xor r6d, r6d\n%else\n mov r6, -32*1\n%endif\n jmp .h_start\n.h_w128:\n%if cpuflag(avx512)\n mov r6, -64*1\n%else\n mov r6, -32*3\n%endif\n.h_start:\n%if cpuflag(avx512)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n%endif\n sub srcq, r6\n mov r5, r6\n.h_loop:\n%if cpuflag(avx512icl)\n movu m0, [srcq+r6+32*0]\n movu m1, [srcq+r6+32*1]\n PREP_8TAP_H\n%else\n movu xm0, [srcq+r6+8*0]\n vinserti128 ym0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 ym0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n add r6, mmsize\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n%if cpuflag(avx512)\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_v)]\n add wq, r7\n%endif\n lea myq, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n vpbroadcastd m7, [pw_8192]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n%if cpuflag(avx512)\n jmp wq\n%else\n cmp wd, 8\n jg .v_w16\n je .v_w8\n%endif\n.v_w4:\n%if cpuflag(avx512)\n AVX512_MM_PERMUTATION\n PREP_8TAP_V_W4 23, 24, 25, 26, 27\n AVX512_MM_PERMUTATION\n%else\n PREP_8TAP_V_W4 7, 8, 9, 10, 11\n%endif\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.v_w8:\n%if cpuflag(avx512)\n mov r3d, 0xf044\n kmovw k1, r3d\n kshiftrw k2, k1, 8\n movq xm0, [srcq+strideq*0]\n vpbroadcastq ym1, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vmovdqa64 ym0{k1}, ym1\n vmovdqa64 ym1{k1}, ym2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n punpcklbw ym0, ym1 ; 01 12 __ __\n punpcklbw m2, m3 ; 23 34 23 34\n punpcklbw m4, m5 ; 45 56 45 56\n vmovdqa64 m0{k2}, m2 ; 01 12 23 34\n vmovdqa64 m2{k2}, m4 ; 23 34 45 56\n.v_w8_loop:\n vpbroadcastq m1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n pmaddubsw m14, m0, m8\n pmaddubsw m15, m2, m9\n vpblendmq m0{k1}, m6, m1\n vpblendmq m2{k1}, m1, m3\n vpbroadcastq m6, [srcq+strideq*2]\n paddw m14, m15\n punpcklbw m2, m0, m2 ; 67 78 67 78\n vpblendmq m12{k1}, m3, m5\n vpblendmq m13{k1}, m5, m6\n vpblendmq m0{k2}, m4, m2 ; 45 56 67 78\n punpcklbw m4, m12, m13 ; 89 9a 89 9a\n vmovdqa64 m2{k2}, m4 ; 67 78 89 9a\n pmaddubsw m12, m0, m10\n pmaddubsw m13, m2, m11\n paddw m14, m12\n paddw m14, m13\n pmulhrsw m14, m7\n mova [tmpq], m14\n%else\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512)\n mov r3d, 0xf0\n kmovb k1, r3d\n vbroadcasti128 m0, [srcq+strideq*0]\n vbroadcasti128 m1, [srcq+strideq*1]\n vbroadcasti128 m2, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n vmovdqa64 m0{k1}, m1\n vmovdqa64 m1{k1}, m2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n shufpd m0, m2, 0xcc ; 0a_2a 0b_2b 1a_3a 1b_3b\n shufpd m1, m3, 0xcc ; 1a_3a 1b_3b 2a_4a 2b_4b\n shufpd m4, m4, 0x44 ; 4a_-- 4b_-- 5a_-- 5b_--\n shufpd m5, m5, 0x44 ; 5a_-- 5b_-- 6a_-- 6b_--\n punpckhbw m2, m0, m1 ; 23a 23b 34a 34b\n punpcklbw m0, m1 ; 01a 01b 12a 12b\n punpcklbw m4, m5 ; 45a 45b 56a 56b\n.v_w16_loop:\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m5, [srcq+strideq*0]\n vpblendmq m1{k1}, m6, m3\n vmovdqa64 m3{k1}, m5\n pmaddubsw m12, m0, m8\n pmaddubsw m13, m2, m8\n pmaddubsw m14, m2, m9\n pmaddubsw m15, m4, m9\n pmaddubsw m0, m4, m10\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n paddw m12, m14\n paddw m13, m15\n paddw m12, m0\n vmovdqa64 m5{k1}, m2\n vmovdqa64 m2{k1}, m6\n mova m0, m4\n shufpd m1, m5, 0xcc ; 6a_8a 6b_8b 7a_9a 7b_9b\n shufpd m3, m2, 0xcc ; 7a_9a 7b_9b 8a_Aa 8b_Ab\n punpcklbw m2, m1, m3 ; 67a 67b 78a 78b\n punpckhbw m4, m1, m3 ; 89a 89b 9Aa 9Ab\n pmaddubsw m14, m2, m10\n pmaddubsw m15, m2, m11\n paddw m13, m14\n paddw m12, m15\n pmaddubsw m14, m4, m11\n paddw m13, m14\n pmulhrsw m12, m7\n pmulhrsw m13, m7\n mova [tmpq+ 0], m12\n mova [tmpq+64], m13\n add tmpq, 64*2\n sub hd, 4\n jg .v_w16_loop\n%else\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n%endif\n RET\n%if cpuflag(avx512)\n.v_w32:\n mova m18, [bilin_v_perm64]\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n movu ym3, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym4, [srcq+strideq*0]\n movu ym5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym6, [srcq+strideq*0]\n vpermq m0, m18, m0\n vpermq m1, m18, m1\n vpermq m2, m18, m2\n vpermq m3, m18, m3\n vpermq m4, m18, m4\n vpermq m5, m18, m5\n vpermq m6, m18, m6\n punpcklbw m0, m1\n punpcklbw m1, m2\n punpcklbw m2, m3\n punpcklbw m3, m4\n punpcklbw m4, m5\n punpcklbw m5, m6\n.v_w32_loop:\n movu ym12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym13, [srcq+strideq*0]\n pmaddubsw m14, m0, m8\n pmaddubsw m16, m2, m9\n pmaddubsw m15, m1, m8\n pmaddubsw m17, m3, m9\n mova m0, m2\n mova m1, m3\n vpermq m12, m18, m12\n vpermq m13, m18, m13\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m4, m10\n pmaddubsw m17, m5, m10\n punpcklbw m6, m12\n punpcklbw m12, m13\n mova m2, m4\n mova m3, m5\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m6, m11\n pmaddubsw m17, m12, m11\n mova m4, m6\n mova m5, m12\n paddw m14, m16\n paddw m15, m17\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova m6, m13\n mova [tmpq+ 0], m14\n mova [tmpq+64], m15\n add tmpq, 64*2\n sub hd, 2\n jg .v_w32_loop\n vzeroupper\n RET\n.v_w64:\n mov r6d, hd\n mov wd, 64\n jmp .v_start\n.v_w128:\n lea r6d, [(1<<8)+hq]\n mov wd, 128\n.v_start:\n WIN64_SPILL_XMM 27\n mova m26, [bilin_v_perm64]\n mov r5, tmpq\n mov r7, srcq\n.v_loop0:\n vpermq m0, m26, [srcq+strideq*0]\n vpermq m1, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m2, m26, [srcq+strideq*0]\n vpermq m3, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m4, m26, [srcq+strideq*0]\n vpermq m5, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m6, m26, [srcq+strideq*0]\n punpckhbw m12, m0, m1\n punpcklbw m0, m1\n punpckhbw m13, m1, m2\n punpcklbw m1, m2\n punpckhbw m14, m2, m3\n punpcklbw m2, m3\n punpckhbw m15, m3, m4\n punpcklbw m3, m4\n punpckhbw m16, m4, m5\n punpcklbw m4, m5\n punpckhbw m17, m5, m6\n punpcklbw m5, m6\n.v_loop:\n vpermq m18, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m19, m26, [srcq+strideq*0]\n pmaddubsw m20, m0, m8\n pmaddubsw m21, m12, m8\n pmaddubsw m22, m1, m8\n pmaddubsw m23, m13, m8\n mova m0, m2\n mova m12, m14\n mova m1, m3\n mova m13, m15\n pmaddubsw m2, m9\n pmaddubsw m14, m9\n pmaddubsw m3, m9\n pmaddubsw m15, m9\n punpckhbw m24, m6, m18\n punpcklbw m6, m18\n paddw m20, m2\n paddw m21, m14\n paddw m22, m3\n paddw m23, m15\n mova m2, m4\n mova m14, m16\n mova m3, m5\n mova m15, m17\n pmaddubsw m4, m10\n pmaddubsw m16, m10\n pmaddubsw m5, m10\n pmaddubsw m17, m10\n punpckhbw m25, m18, m19\n punpcklbw m18, m19\n paddw m20, m4\n paddw m21, m16\n paddw m22, m5\n paddw m23, m17\n mova m4, m6\n mova m16, m24\n mova m5, m18\n mova m17, m25\n pmaddubsw m6, m11\n pmaddubsw m24, m11\n pmaddubsw m18, m11\n pmaddubsw m25, m11\n paddw m20, m6\n paddw m21, m24\n paddw m22, m18\n paddw m23, m25\n pmulhrsw m20, m7\n pmulhrsw m21, m7\n pmulhrsw m22, m7\n pmulhrsw m23, m7\n mova m6, m19\n mova [tmpq+wq*0+ 0], m20\n mova [tmpq+wq*0+64], m21\n mova [tmpq+wq*2+ 0], m22\n mova [tmpq+wq*2+64], m23\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_loop\n movzx hd, r6b\n add r5, 64*2\n add r7, 64\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_loop0\n%endif\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n %assign stack_size_padded 0\n WIN64_SPILL_XMM 16\n cmp wd, 4\n je .hv_w4\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n%if cpuflag(avx512)\n tzcnt wd, wd\n vpbroadcastd m8, [pd_2]\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_hv)]\n vpbroadcastd m9, [pd_32]\n add wq, r7\n%endif\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512)\n jmp wq\n%else\n jmp .hv_w8\n%endif\n.hv_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n%if cpuflag(avx512)\n mov r3d, 0x04\n kmovb k1, r3d\n kshiftlb k2, k1, 2\n kshiftlb k3, k1, 4\n vpbroadcastd m10, [pd_2]\n vbroadcasti128 m16, [subpel_h_shufA]\n%else\n mova m7, [subpel_h_shuf4]\n pmovzxbd m9, [deint_shuf4]\n vpbroadcastd m10, [pw_8192]\n%endif\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512icl)\n movq xm3, [srcq+strideq*0]\n vpbroadcastq ym2, [srcq+strideq*1]\n vpbroadcastq ym3{k1}, [srcq+strideq*2]\n vpbroadcastq m2{k2}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3{k2}, [srcq+strideq*0]\n vpbroadcastq m2{k3}, [srcq+strideq*1]\n vpbroadcastq m3{k3}, [srcq+strideq*2]\n mova m17, [spel_hv_perm4a]\n movu m18, [spel_hv_perm4b]\n mova m0, m10\n mova m1, m10\n pshufb m2, m16\n pshufb m3, m16\n vpdpbusd m0, m2, m8\n vpdpbusd m1, m3, m8\n packssdw m0, m1 ; _ 0 1 2 3 4 5 6\n psraw m0, 2\n vpermb m1, m17, m0 ; 01 12 23 34\n vpermb m2, m18, m0 ; 23 34 45 56\n.hv_w4_loop:\n movq xm3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movq xm4, [srcq+strideq*0]\n vpbroadcastq ym3{k1}, [srcq+strideq*1]\n vpbroadcastq ym4{k1}, [srcq+strideq*2]\n mova ym5, ym10\n mova ym6, ym10\n pshufb ym3, ym16\n pshufb ym4, ym16\n vpdpbusd ym5, ym3, ym8\n vpdpbusd ym6, ym4, ym8\n mova m7, m11\n packssdw ym5, ym6 ; 7 8 9 a _ _ _ _\n psraw ym5, 2\n valignq m0, m5, m0, 4 ; _ 4 5 6 7 8 9 a\n vpdpwssd m7, m1, m12\n vpdpwssd m7, m2, m13\n vpermb m1, m17, m0 ; 45 56 67 78\n vpermb m2, m18, m0 ; 67 78 89 9a\n vpdpwssd m7, m1, m14\n vpdpwssd m7, m2, m15\n psrad m7, 6\n vpmovdw [tmpq], m7\n%else\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7 ; 00 01 10 11 02 03 12 13\n pshufb m0, m7 ; 20 21 30 31 22 23 32 33\n pshufb m3, m7 ; 40 41 50 51 42 43 52 53\n pshufb m1, m7 ; 60 61 60 61 62 63 62 63\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0 ; 0a 1a 2a 3a 0b 1b 2b 3b\n phaddw m3, m1 ; 4a 5a 6a __ 4b 5b 6b __\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4 ; 1a 2a 3a 4a 1b 2b 3b 4b\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n%endif\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.hv_w8:\n%if cpuflag(avx512icl)\n WIN64_SPILL_XMM 24\n vbroadcasti128 m16, [subpel_h_shufA]\n vbroadcasti128 m17, [subpel_h_shufB]\n vbroadcasti128 m18, [subpel_h_shufC]\n vinserti128 ym0, [srcq+strideq*0], 1\n vinserti128 m0, [srcq+strideq*1], 2\n vinserti128 m0, [srcq+strideq*2], 3\n movu xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym1, [srcq+strideq*0], 1\n vinserti128 m1, [srcq+strideq*1], 2\n vinserti128 m1, [srcq+strideq*2], 3\n mova m2, m8\n mova m4, m8\n mova m3, m8\n mova m5, m8\n pshufb m20, m0, m16\n pshufb m21, m0, m17\n pshufb m22, m0, m18\n pshufb m23, m1, m16\n pshufb m6, m1, m17\n pshufb m7, m1, m18\n vpdpbusd m2, m20, m10\n vpdpbusd m4, m21, m10\n vpdpbusd m2, m21, m11\n vpdpbusd m4, m22, m11\n vpdpbusd m3, m23, m10\n vpdpbusd m5, m6, m10\n vpdpbusd m3, m6, m11\n vpdpbusd m5, m7, m11\n packssdw m2, m4\n packssdw m3, m5\n psraw m2, 2 ; _ 0 1 2\n psraw m3, 2 ; 3 4 5 6\n valignq m0, m3, m2, 2 ; 0 1 2 3\n valignq m1, m3, m2, 4 ; 1 2 3 4\n valignq m2, m3, m2, 6 ; 2 3 4 5\n punpcklwd m4, m0, m1 ; 01a 12a 23a 34a\n punpckhwd m5, m0, m1 ; 01b 12b 23b 34b\n punpcklwd m6, m2, m3 ; 23a 34a 45a 56a\n punpckhwd m7, m2, m3 ; 23b 34b 45b 56b\n.hv_w8_loop:\n movu xm19, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym19, [srcq+strideq*0], 1\n vinserti128 m19, [srcq+strideq*1], 2\n vinserti128 m19, [srcq+strideq*2], 3\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m4, m12\n vpdpwssd m21, m5, m12\n vpdpwssd m20, m6, m13\n vpdpwssd m21, m7, m13\n pshufb m0, m19, m16\n pshufb m1, m19, m17\n pshufb m2, m19, m18\n vpdpbusd m22, m0, m10\n vpdpbusd m23, m1, m10\n vpdpbusd m22, m1, m11\n vpdpbusd m23, m2, m11\n packssdw m22, m23\n psraw m22, 2 ; 7 8 9 A\n valignq m0, m22, m3, 2 ; 4 5 6 7\n valignq m1, m22, m3, 4 ; 5 6 7 8\n valignq m2, m22, m3, 6 ; 6 7 8 9\n mova m3, m22\n punpcklwd m4, m0, m1 ; 45a 56a 67a 78a\n punpckhwd m5, m0, m1 ; 45b 56b 67b 78b\n punpcklwd m6, m2, m3 ; 67a 78a 89a 9Aa\n punpckhwd m7, m2, m3 ; 67b 78b 89b 9Ab\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq], m20\n add tmpq, 64\n sub hd, 4\n jg .hv_w8_loop\n%else\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n%endif\n RET\n%if cpuflag(avx512icl)\n.hv_w16:\n mov wd, 16*2\n jmp .hv_start\n.hv_w32:\n mov wd, 32*2\n jmp .hv_start\n.hv_w64:\n mov wd, 64*2\n jmp .hv_start\n.hv_w128:\n mov wd, 128*2\n.hv_start:\n WIN64_SPILL_XMM 31\n mova m16, [spel_h_perm16a]\n mova m17, [spel_h_perm16b]\n mova m18, [spel_h_perm16c]\n lea r6d, [wq*8-16*2*8+hq]\n mov r5, tmpq\n mov r7, srcq\n.hv_loop0:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym1, [srcq+strideq*0]\n vinserti32x8 m1, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n vinserti32x8 m2, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym3, [srcq+strideq*0]\n mova m4, m8\n mova m5, m8\n mova m6, m8\n mova m7, m8\n vpermb m19, m16, m0\n vpermb m20, m17, m0\n vpermb m21, m18, m0\n vpermb m22, m16, m1\n vpermb m23, m17, m1\n vpermb m24, m18, m1\n vpermb m25, m16, m2\n vpermb m26, m17, m2\n vpermb m27, m18, m2\n vpermb ym28, ym16, ym3\n vpermb ym29, ym17, ym3\n vpermb ym30, ym18, ym3\n mova m0, m8\n mova m1, m8\n mova ym2, ym8\n mova ym3, ym8\n vpdpbusd m4, m19, m10\n vpdpbusd m5, m20, m10\n vpdpbusd m6, m22, m10\n vpdpbusd m7, m23, m10\n vpdpbusd m0, m25, m10\n vpdpbusd m1, m26, m10\n vpdpbusd ym2, ym28, ym10\n vpdpbusd ym3, ym29, ym10\n vpdpbusd m4, m20, m11\n vpdpbusd m5, m21, m11\n vpdpbusd m6, m23, m11\n vpdpbusd m7, m24, m11\n vpdpbusd m0, m26, m11\n vpdpbusd m1, m27, m11\n vpdpbusd ym2, ym29, ym11\n vpdpbusd ym3, ym30, ym11\n packssdw m4, m5\n packssdw m6, m7\n packssdw m0, m1\n packssdw ym2, ym3\n psraw m4, 2 ; 0a 0b 1a 1b\n psraw m6, 2 ; 2a 2b 3a 3b\n psraw m0, 2 ; 4a 4b 5a 5b\n psraw ym2, 2 ; 6a 6b __ __\n vshufi32x4 m5, m4, m6, q1032 ; 1a 1b 2a 2b\n vshufi32x4 m7, m6, m0, q1032 ; 3a 3b 4a 4b\n vshufi32x4 m1, m0, m2, q1032 ; 5a 5b 6a 6b\n punpcklwd m2, m4, m5 ; 01a 01c 12a 12c\n punpckhwd m3, m4, m5 ; 01b 01d 12b 12d\n punpcklwd m4, m6, m7 ; 23a 23c 34a 34c\n punpckhwd m5, m6, m7 ; 23b 23d 34b 34d\n punpcklwd m6, m0, m1 ; 45a 45c 56a 56c\n punpckhwd m7, m0, m1 ; 45b 45d 56b 56d\n.hv_loop:\n movu ym19, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti32x8 m19, [srcq+strideq*0], 1\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m2, m12\n vpdpwssd m21, m3, m12\n vpdpwssd m20, m4, m13\n vpdpwssd m21, m5, m13\n vpermb m24, m16, m19\n vpermb m25, m17, m19\n vpermb m26, m18, m19\n vpdpbusd m22, m24, m10\n vpdpbusd m23, m25, m10\n vpdpbusd m22, m25, m11\n vpdpbusd m23, m26, m11\n packssdw m22, m23\n psraw m22, 2 ; 7a 7b 8a 8b\n vshufi32x4 m0, m1, m22, q1032 ; 6a 6b 7a 7b\n mova m2, m4\n mova m3, m5\n mova m1, m22\n mova m4, m6\n mova m5, m7\n punpcklwd m6, m0, m1 ; 67a 67c 78a 78c\n punpckhwd m7, m0, m1 ; 67b 67d 78b 78d\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq+wq*0], ym20\n vextracti32x8 [tmpq+wq*1], m20, 1\n lea tmpq, [tmpq+wq*2]\n sub hd, 2\n jg .hv_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_loop0\n%endif\n RET\n%endmacro\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro WRAP_YMM 1+\n INIT_YMM cpuname\n %1\n INIT_ZMM cpuname\n%endmacro\n\n%macro BIDIR_FN 1 ; op\n%if mmsize == 64\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n cmp hd, 8\n jg .w4_h16\n WRAP_YMM %1 0\n vextracti32x4 xmm1, ym0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xmm1\n pextrd [dstq+stride3q ], xmm1, 1\n jl .w4_ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xmm1, 2\n pextrd [dstq+stride3q ], xmm1, 3\n.w4_ret:\n RET\n.w4_h16:\n vpbroadcastd m7, strided\n pmulld m7, [bidir_sctr_w4]\n %1 0\n kxnorw k1, k1, k1\n vpscatterdd [dstq+m7]{k1}, m0\n RET\n.w8:\n cmp hd, 4\n jne .w8_h8\n WRAP_YMM %1 0\n vextracti128 xmm1, ym0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xmm1\n RET\n.w8_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w8_h8:\n %1 0\n vextracti32x4 xmm1, ym0, 1\n vextracti32x4 xmm2, m0, 2\n vextracti32x4 xmm3, m0, 3\n movq [dstq ], xm0\n movq [dstq+strideq*1], xmm1\n movq [dstq+strideq*2], xmm2\n movq [dstq+stride3q ], xmm3\n lea dstq, [dstq+strideq*4]\n movhps [dstq ], xm0\n movhps [dstq+strideq*1], xmm1\n movhps [dstq+strideq*2], xmm2\n movhps [dstq+stride3q ], xmm3\n sub hd, 8\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 2\n lea dstq, [dstq+strideq*4]\n.w16:\n %1 0\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti32x4 [dstq+strideq*1], m0, 2\n vextracti32x4 [dstq+strideq*2], ym0, 1\n vextracti32x4 [dstq+stride3q ], m0, 3\n sub hd, 4\n jg .w16_loop\n RET\n.w32:\n pmovzxbq m7, [warp_8x8_shufA]\n.w32_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq+strideq*0], ym0\n vextracti32x8 [dstq+strideq*1], m0, 1\n lea dstq, [dstq+strideq*2]\n sub hd, 2\n jg .w32_loop\n RET\n.w64:\n pmovzxbq m7, [warp_8x8_shufA]\n.w64_loop:\n %1 0\n %1_INC_PTR 2\n vpermq m0, m7, m0\n mova [dstq], m0\n add dstq, strideq\n dec hd\n jg .w64_loop\n RET\n.w128:\n pmovzxbq m7, [warp_8x8_shufA]\n.w128_loop:\n %1 0\n vpermq m6, m7, m0\n %1 2\n mova [dstq+64*0], m6\n %1_INC_PTR 4\n vpermq m6, m7, m0\n mova [dstq+64*1], m6\n add dstq, strideq\n dec hd\n jg .w128_loop\n RET\n%else\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endif\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\n%macro AVG_FN 0\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-avg %+ SUFFIX %+ _table\n lea r6, [avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [base+pw_1024]\n add wq, r6\n BIDIR_FN AVG\n%endmacro\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\n%macro W_AVG_FN 0\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n%define base r6-w_avg %+ SUFFIX %+ _table\n lea r6, [w_avg %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [base+pw_2048]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n%endmacro\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n%if mmsize == 64\n vpermq m3, m8, [maskq+%1*32]\n%else\n vpermq m3, [maskq+%1*16], q3120\n%endif\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp2q, %1*mmsize\n add tmp1q, %1*mmsize\n%endmacro\n\n%macro MASK_FN 0\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-mask %+ SUFFIX %+ _table\n lea r7, [mask %+ SUFFIX %+ _table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n%if mmsize == 64\n mova m8, [base+bilin_v_perm64]\n%endif\n vpbroadcastd m5, [base+pw_2048]\n add wq, r7\n BIDIR_FN MASK\n%endmacro MASK_FN\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovs r10, yq\n test yq, yq\n cmovs r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovs r10, xq\n test xq, xq\n cmovs r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovs bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovs topextq, r12\n cmp bottomextq, bhq\n cmovns bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovs rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovs leftextq, r12\n cmp rightextq, bwq\n cmovns rightextq, r2\n cmp leftextq, bwq\n cmovns leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\nINIT_YMM avx2\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\nINIT_ZMM avx512icl\nPREP_BILIN\nPREP_8TAP\nAVG_FN\nW_AVG_FN\nMASK_FN\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\nSECTION_RODATA 64\n\n; dav1d_obmc_masks[] with 64-x interleaved\nobmc_masks: db 0, 0, 0, 0\n ; 2\n db 45, 19, 64, 0\n ; 4\n db 39, 25, 50, 14, 59, 5, 64, 0\n ; 8\n db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0\n ; 16\n db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10\n db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0\n ; 32\n db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20\n db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9\n db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2\n db 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0, 64, 0\n\nbilin_h_perm16: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 33, 32, 34, 33, 35, 34, 36, 35, 37, 36, 38, 37, 39, 38, 40, 39\n db 41, 40, 42, 41, 43, 42, 44, 43, 45, 44, 46, 45, 47, 46, 48, 47\nbilin_h_perm32: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\n db 9, 8, 10, 9, 11, 10, 12, 11, 13, 12, 14, 13, 15, 14, 16, 15\n db 17, 16, 18, 17, 19, 18, 20, 19, 21, 20, 22, 21, 23, 22, 24, 23\n db 25, 24, 26, 25, 27, 26, 28, 27, 29, 28, 30, 29, 31, 30, 32, 31\nbilin_v_perm8: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 32, 80, 33, 81, 34, 82, 35, 83, 36, 84, 37, 85, 38, 86, 39, 87\n db 64, 32, 65, 33, 66, 34, 67, 35, 68, 36, 69, 37, 70, 38, 71, 39\nbilin_v_perm16: db 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7\n db 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15\n db 64, 16, 65, 17, 66, 18, 67, 19, 68, 20, 69, 21, 70, 22, 71, 23\n db 72, 24, 73, 25, 74, 26, 75, 27, 76, 28, 77, 29, 78, 30, 79, 31\nbilin_v_perm32: db 64, 0, 65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7\n db 72, 8, 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15\n db 80, 16, 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23\n db 88, 24, 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31\nbilin_v_perm64: dq 0, 4, 1, 5, 2, 6, 3, 7\nspel_h_perm16a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\nspel_h_perm16b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 36, 37, 38, 39, 37, 38, 39, 40, 38, 39, 40, 41, 39, 40, 41, 42\n db 44, 45, 46, 47, 45, 46, 47, 48, 46, 47, 48, 49, 47, 48, 49, 50\nspel_h_perm16c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 40, 41, 42, 43, 41, 42, 43, 44, 42, 43, 44, 45, 43, 44, 45, 46\n db 48, 49, 50, 51, 49, 50, 51, 52, 50, 51, 52, 53, 51, 52, 53, 54\nspel_h_perm32a: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\n db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\nspel_h_perm32b: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\n db 12, 13, 14, 15, 13, 14, 15, 16, 14, 15, 16, 17, 15, 16, 17, 18\n db 20, 21, 22, 23, 21, 22, 23, 24, 22, 23, 24, 25, 23, 24, 25, 26\n db 28, 29, 30, 31, 29, 30, 31, 32, 30, 31, 32, 33, 31, 32, 33, 34\nspel_h_perm32c: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\n db 16, 17, 18, 19, 17, 18, 19, 20, 18, 19, 20, 21, 19, 20, 21, 22\n db 24, 25, 26, 27, 25, 26, 27, 28, 26, 27, 28, 29, 27, 28, 29, 30\n db 32, 33, 34, 35, 33, 34, 35, 36, 34, 35, 36, 37, 35, 36, 37, 38\nspel_hv_perm4a: db 8, 9, 16, 17, 10, 11, 18, 19, 12, 13, 20, 21, 14, 15, 22, 23\n db 16, 17, 24, 25, 18, 19, 26, 27, 20, 21, 28, 29, 22, 23, 30, 31\nspel_hv_perm4b: db 24, 25, 32, 33, 26, 27, 34, 35, 28, 29, 36, 37, 30, 31, 38, 39\n db 32, 33, 40, 41, 34, 35, 42, 43, 36, 37, 44, 45, 38, 39, 46, 47\n db 40, 41, 48, 49, 42, 43, 50, 51, 44, 45, 52, 53, 46, 47, 54, 55\n db 48, 49, 56, 57, 50, 51, 58, 59, 52, 53, 60, 61, 54, 55, 62, 63\n\nwarp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8\n db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12\nwarp_8x8_shufB: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10\n db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14\nsubpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12\n db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6\nsubpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10\nsubpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14\nsubpel_v_shuf4: db 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15\nbilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11\nbilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7\nbilin_v_shuf4: db 4, 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7\ndeint_shuf4: db 0, 4, 1, 5, 2, 6, 3, 7, 4, 8, 5, 9, 6, 10, 7, 11\nblend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3\n\npb_64: times 4 db 64\npw_34: times 2 dw 34\npw_258: times 2 dw 258\npw_512: times 2 dw 512\npw_1024: times 2 dw 1024\npw_2048: times 2 dw 2048\npw_6903: times 2 dw 6903\npw_8192: times 2 dw 8192\npd_2: dd 2\npd_32: dd 32\npd_512: dd 512\npd_32768: dd 32768\n\ncextern mc_subpel_filters\n%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)\n\n%macro BIDIR_JMP_TABLE 1-*\n %xdefine %1_table (%%table - 2*%2)\n %xdefine %%base %1_table\n %xdefine %%prefix mangle(private_prefix %+ _%1)\n %%table:\n %rep %0 - 1\n dd %%prefix %+ .w%2 - %%base\n %rotate 1\n %endrep\n%endmacro\n\nBIDIR_JMP_TABLE avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_avg_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE mask_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_420_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_422_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE w_mask_444_avx2, 4, 8, 16, 32, 64, 128\nBIDIR_JMP_TABLE blend_avx2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_v_avx2, 2, 4, 8, 16, 32\nBIDIR_JMP_TABLE blend_h_avx2, 2, 4, 8, 16, 32, 32, 32\n\n%macro BASE_JMP_TABLE 3-*\n %xdefine %1_%2_table (%%table - %3)\n %xdefine %%base %1_%2\n %%table:\n %rep %0 - 2\n dw %%base %+ _w%3 - %%base\n %rotate 1\n %endrep\n%endmacro\n\n%xdefine put_avx2 mangle(private_prefix %+ _put_bilin_avx2.put)\n%xdefine prep_avx2 mangle(private_prefix %+ _prep_bilin_avx2.prep)\n%xdefine prep_avx512icl mangle(private_prefix %+ _prep_bilin_avx512icl.prep)\n\nBASE_JMP_TABLE put, avx2, 2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx2, 4, 8, 16, 32, 64, 128\nBASE_JMP_TABLE prep, avx512icl, 4, 8, 16, 32, 64, 128\n\n%macro HV_JMP_TABLE 5-*\n %xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)\n %xdefine %%base %1_%3\n %assign %%types %4\n %if %%types & 1\n %xdefine %1_%2_h_%3_table (%%h - %5)\n %%h:\n %rep %0 - 4\n dw %%prefix %+ .h_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 2\n %xdefine %1_%2_v_%3_table (%%v - %5)\n %%v:\n %rep %0 - 4\n dw %%prefix %+ .v_w%5 - %%base\n %rotate 1\n %endrep\n %rotate 4\n %endif\n %if %%types & 4\n %xdefine %1_%2_hv_%3_table (%%hv - %5)\n %%hv:\n %rep %0 - 4\n dw %%prefix %+ .hv_w%5 - %%base\n %rotate 1\n %endrep\n %endif\n%endmacro\n\nHV_JMP_TABLE put, 8tap, avx2, 3, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx2, 1, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, 8tap, avx512icl, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE put, bilin, avx2, 7, 2, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx2, 7, 4, 8, 16, 32, 64, 128\nHV_JMP_TABLE prep, bilin, avx512icl, 7, 4, 8, 16, 32, 64, 128\n\n%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX\n\ncextern mc_warp_filter\n\nSECTION .text\n\nINIT_XMM avx2\nDECLARE_REG_TMP 4, 6, 7\ncglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy\n movifnidn mxyd, r6m ; mx\n lea t2, [put_avx2]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r7m ; my\n test mxyd, mxyd\n jnz .v\n.put:\n movzx wd, word [t2+wq*2+table_offset(put,)]\n add wq, t2\n jmp wq\n.put_w2:\n movzx t0d, word [srcq+ssq*0]\n movzx t1d, word [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0w\n mov [dstq+dsq*1], t1w\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w2\n RET\n.put_w4:\n mov t0d, [srcq+ssq*0]\n mov t1d, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0d\n mov [dstq+dsq*1], t1d\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w4\n RET\n.put_w8:\n mov t0, [srcq+ssq*0]\n mov t1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mov [dstq+dsq*0], t0\n mov [dstq+dsq*1], t1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w8\n RET\n.put_w16:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w16\n RET\nINIT_YMM avx2\n.put_w32:\n movu m0, [srcq+ssq*0]\n movu m1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0], m0\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w32\n RET\n.put_w64:\n movu m0, [srcq+ssq*0+32*0]\n movu m1, [srcq+ssq*0+32*1]\n movu m2, [srcq+ssq*1+32*0]\n movu m3, [srcq+ssq*1+32*1]\n lea srcq, [srcq+ssq*2]\n mova [dstq+dsq*0+32*0], m0\n mova [dstq+dsq*0+32*1], m1\n mova [dstq+dsq*1+32*0], m2\n mova [dstq+dsq*1+32*1], m3\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .put_w64\n RET\n.put_w128:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n movu m2, [srcq+32*2]\n movu m3, [srcq+32*3]\n add srcq, ssq\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n mova [dstq+32*2], m2\n mova [dstq+32*3], m3\n add dstq, dsq\n dec hd\n jg .put_w128\n RET\n.h:\n ; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4\n ; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4\n imul mxyd, 0xff01\n vbroadcasti128 m4, [bilin_h_shuf8]\n add mxyd, 16 << 8\n movd xm5, mxyd\n mov mxyd, r7m ; my\n vpbroadcastw m5, xm5\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_h)]\n vpbroadcastd m3, [pw_2048]\n add wq, t2\n jmp wq\n.h_w2:\n movd xm0, [srcq+ssq*0]\n pinsrd xm0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2\n RET\n.h_w4:\n mova xm4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n pmulhrsw xm0, xm3\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n movu xm0, [srcq+ssq*0]\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pshufb xm1, xm4\n pmaddubsw xm0, xm5\n pmaddubsw xm1, xm5\n pmulhrsw xm0, xm3\n pmulhrsw xm1, xm3\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n add srcq, ssq\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .h_w32\n RET\n.h_w64:\n movu m0, [srcq+8*0]\n movu m1, [srcq+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n movu m1, [srcq+8*4]\n movu m2, [srcq+8*5]\n add srcq, ssq\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmulhrsw m1, m3\n pmulhrsw m2, m3\n packuswb m1, m2\n mova [dstq+32*0], m0\n mova [dstq+32*1], m1\n add dstq, dsq\n dec hd\n jg .h_w64\n RET\n.h_w128:\n mov t1, -32*3\n.h_w128_loop:\n movu m0, [srcq+t1+32*3+8*0]\n movu m1, [srcq+t1+32*3+8*1]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmulhrsw m0, m3\n pmulhrsw m1, m3\n packuswb m0, m1\n mova [dstq+t1+32*3], m0\n add t1, 32\n jle .h_w128_loop\n add srcq, ssq\n add dstq, dsq\n dec hd\n jg .h_w128\n RET\n.v:\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_v)]\n imul mxyd, 0xff01\n vpbroadcastd m5, [pw_2048]\n add mxyd, 16 << 8\n add wq, t2\n movd xm4, mxyd\n vpbroadcastw m4, xm4\n jmp wq\n.v_w2:\n movd xm0, [srcq+ssq*0]\n.v_w2_loop:\n pinsrw xm1, xm0, [srcq+ssq*1], 1 ; 0 1\n lea srcq, [srcq+ssq*2]\n pinsrw xm0, xm1, [srcq+ssq*0], 0 ; 2 1\n pshuflw xm1, xm1, q2301 ; 1 0\n punpcklbw xm1, xm0, xm1\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 1\n pextrw [dstq+dsq*1], xm1, 0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm0, [srcq+ssq*0]\n.v_w4_loop:\n vpbroadcastd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm2, xm1, xm0, 0x01 ; 0 1\n vpbroadcastd xm0, [srcq+ssq*0]\n vpblendd xm1, xm1, xm0, 0x02 ; 1 2\n punpcklbw xm1, xm2\n pmaddubsw xm1, xm4\n pmulhrsw xm1, xm5\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm0, [srcq+ssq*0]\n.v_w8_loop:\n movq xm3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw xm1, xm3, xm0\n movq xm0, [srcq+ssq*0]\n punpcklbw xm2, xm0, xm3\n pmaddubsw xm1, xm4\n pmaddubsw xm2, xm4\n pmulhrsw xm1, xm5\n pmulhrsw xm2, xm5\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n movu xm0, [srcq+ssq*0]\n.v_w16_loop:\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m3, m2, m0, 0x0f ; 0 1\n vbroadcasti128 m0, [srcq+ssq*0]\n vpblendd m2, m2, m0, 0xf0 ; 1 2\n punpcklbw m1, m2, m3\n punpckhbw m2, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n RET\n.v_w32:\n%macro PUT_BILIN_V_W32 0\n movu m0, [srcq+ssq*0]\n%%loop:\n movu m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n punpcklbw m1, m3, m0\n punpckhbw m2, m3, m0\n movu m0, [srcq+ssq*0]\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*0], m1\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m1, m4\n pmaddubsw m2, m4\n pmulhrsw m1, m5\n pmulhrsw m2, m5\n packuswb m1, m2\n mova [dstq+dsq*1], m1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg %%loop\n%endmacro\n PUT_BILIN_V_W32\n RET\n.v_w64:\n movu m0, [srcq+32*0]\n movu m1, [srcq+32*1]\n.v_w64_loop:\n add srcq, ssq\n movu m3, [srcq+32*0]\n punpcklbw m2, m3, m0\n punpckhbw m0, m3, m0\n pmaddubsw m2, m4\n pmaddubsw m0, m4\n pmulhrsw m2, m5\n pmulhrsw m0, m5\n packuswb m2, m0\n mova m0, m3\n movu m3, [srcq+32*1]\n mova [dstq+32*0], m2\n punpcklbw m2, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m2, m4\n pmaddubsw m1, m4\n pmulhrsw m2, m5\n pmulhrsw m1, m5\n packuswb m2, m1\n mova m1, m3\n mova [dstq+32*1], m2\n add dstq, dsq\n dec hd\n jg .v_w64_loop\n RET\n.v_w128:\n mov t0, dstq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop:\n PUT_BILIN_V_W32\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8\n ; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4\n movzx wd, word [t2+wq*2+table_offset(put, _bilin_hv)]\n WIN64_SPILL_XMM 8\n shl mxyd, 11 ; can't shift by 12 due to signed overflow\n vpbroadcastd m7, [pw_2048]\n movd xm6, mxyd\n add wq, t2\n vpbroadcastw m6, xm6\n jmp wq\n.hv_w2:\n vpbroadcastd xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w2_loop:\n movd xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pinsrd xm1, [srcq+ssq*0], 1\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 _ 2 _\n shufps xm2, xm0, xm1, q1032 ; 0 _ 1 _\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n pextrw [dstq+dsq*0], xm1, 0\n pextrw [dstq+dsq*1], xm1, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova xm4, [bilin_h_shuf4]\n movddup xm0, [srcq+ssq*0]\n pshufb xm0, xm4\n pmaddubsw xm0, xm5\n.hv_w4_loop:\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movhps xm1, [srcq+ssq*0]\n pshufb xm1, xm4\n pmaddubsw xm1, xm5 ; 1 2\n shufps xm2, xm0, xm1, q1032 ; 0 1\n mova xm0, xm1\n psubw xm1, xm2\n paddw xm1, xm1\n pmulhw xm1, xm6\n paddw xm1, xm2\n pmulhrsw xm1, xm7\n packuswb xm1, xm1\n movd [dstq+dsq*0], xm1\n pextrd [dstq+dsq*1], xm1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n vbroadcasti128 m0, [srcq+ssq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m1, m1, [srcq+ssq*0], 1\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m2, m0, m1, 0x21 ; 0 1\n mova m0, m1\n psubw m1, m2\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m2\n pmulhrsw m1, m7\n vextracti128 xm2, m1, 1\n packuswb xm1, xm2\n movq [dstq+dsq*0], xm1\n movhps [dstq+dsq*1], xm1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n RET\n.hv_w16:\n movu m0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w16_loop:\n movu xm2, [srcq+ssq*1+8*0]\n vinserti128 m2, m2, [srcq+ssq*1+8*1], 1\n lea srcq, [srcq+ssq*2]\n movu xm3, [srcq+ssq*0+8*0]\n vinserti128 m3, m3, [srcq+ssq*0+8*1], 1\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m2, m5\n psubw m1, m2, m0\n paddw m1, m1\n pmulhw m1, m6\n paddw m1, m0\n pmaddubsw m0, m3, m5\n psubw m3, m0, m2\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m2\n pmulhrsw m1, m7\n pmulhrsw m3, m7\n packuswb m1, m3\n vpermq m1, m1, q3120\n mova [dstq+dsq*0], xm1\n vextracti128 [dstq+dsq*1], m1, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w16_loop\n RET\n.hv_w32:\n xor t2d, t2d\n.hv_w32gt:\n mov t0, dstq\n mov t1, srcq\n%if WIN64\n movaps r4m, xmm8\n%endif\n.hv_w32_loop0:\n movu m0, [srcq+8*0]\n vinserti128 m0, m0, [srcq+8*2], 1\n movu m1, [srcq+8*1]\n vinserti128 m1, m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, ssq\n movu xm2, [srcq+8*1]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m1\n mova m1, m2\n pmulhrsw m8, m3, m7\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*2], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n paddw m3, m3\n pmulhw m3, m6\n paddw m3, m0\n mova m0, m2\n pmulhrsw m3, m7\n packuswb m3, m8\n mova [dstq], m3\n add dstq, dsq\n dec hd\n jg .hv_w32_loop\n movzx hd, t2b\n add t0, 32\n add t1, 32\n mov dstq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w32_loop0\n%if WIN64\n movaps xmm8, r4m\n%endif\n RET\n.hv_w64:\n lea t2d, [hq+(1<<8)]\n jmp .hv_w32gt\n.hv_w128:\n lea t2d, [hq+(3<<8)]\n jmp .hv_w32gt\n\n%macro PREP_BILIN 0\nDECLARE_REG_TMP 3, 5, 6\ncglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3\n movifnidn mxyd, r5m ; mx\n lea t2, [prep%+SUFFIX]\n tzcnt wd, wm\n movifnidn hd, hm\n test mxyd, mxyd\n jnz .h\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .v\n.prep:\n movzx wd, word [t2+wq*2+table_offset(prep,)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.prep_w4:\n movd xm0, [srcq+strideq*0]\n pinsrd xm0, [srcq+strideq*1], 1\n pinsrd xm0, [srcq+strideq*2], 2\n pinsrd xm0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pmovzxbw ym0, xm0\n psllw ym0, 4\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .prep_w4\n RET\n.prep_w8:\n movq xm0, [srcq+strideq*0]\n%if cpuflag(avx512)\n movq xm1, [srcq+strideq*1]\n vinserti128 ym0, [srcq+strideq*2], 1\n vinserti128 ym1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n punpcklqdq ym0, ym1\n pmovzxbw m0, ym0\n psllw m0, 4\n mova [tmpq], m0\n%else\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmovzxbw m0, xm0\n pmovzxbw m1, xm1\n psllw m0, 4\n psllw m1, 4\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .prep_w8\n RET\n.prep_w16:\n%if cpuflag(avx512)\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 ym1, [srcq+stride3q ], 1\n pmovzxbw m0, ym0\n pmovzxbw m1, ym1\n%else\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n%endif\n lea srcq, [srcq+strideq*4]\n psllw m0, 4\n psllw m1, 4\n%if notcpuflag(avx512)\n psllw m2, 4\n psllw m3, 4\n%endif\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n%if notcpuflag(avx512)\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .prep_w16\n RET\n.prep_w32:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0]\n pmovzxbw m1, [srcq+strideq*1]\n pmovzxbw m2, [srcq+strideq*2]\n pmovzxbw m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n pmovzxbw m0, [srcq+strideq*0+16*0]\n pmovzxbw m1, [srcq+strideq*0+16*1]\n pmovzxbw m2, [srcq+strideq*1+16*0]\n pmovzxbw m3, [srcq+strideq*1+16*1]\n lea srcq, [srcq+strideq*2]\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .prep_w32\n RET\n.prep_w64:\n%if cpuflag(avx512)\n pmovzxbw m0, [srcq+strideq*0+32*0]\n pmovzxbw m1, [srcq+strideq*0+32*1]\n pmovzxbw m2, [srcq+strideq*1+32*0]\n pmovzxbw m3, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n pmovzxbw m0, [srcq+16*0]\n pmovzxbw m1, [srcq+16*1]\n pmovzxbw m2, [srcq+16*2]\n pmovzxbw m3, [srcq+16*3]\n add srcq, strideq\n%endif\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .prep_w64\n RET\n.prep_w128:\n pmovzxbw m0, [srcq+(mmsize/2)*0]\n pmovzxbw m1, [srcq+(mmsize/2)*1]\n pmovzxbw m2, [srcq+(mmsize/2)*2]\n pmovzxbw m3, [srcq+(mmsize/2)*3]\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n pmovzxbw m0, [srcq+16*4]\n pmovzxbw m1, [srcq+16*5]\n pmovzxbw m2, [srcq+16*6]\n pmovzxbw m3, [srcq+16*7]\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n psllw m0, 4\n psllw m1, 4\n psllw m2, 4\n psllw m3, 4\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .prep_w128\n RET\n.h:\n ; 16 * src[x] + (mx * (src[x + 1] - src[x]))\n ; = (16 - mx) * src[x] + mx * src[x + 1]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n%if cpuflag(avx512)\n vpbroadcastw m5, mxyd\n%else\n movd xm5, mxyd\n vbroadcasti128 m4, [bilin_h_shuf8]\n vpbroadcastw m5, xm5\n%endif\n mov mxyd, r6m ; my\n test mxyd, mxyd\n jnz .hv\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.h_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n.h_w4_loop:\n movq xm0, [srcq+strideq*0]\n movhps xm0, [srcq+strideq*1]\n movq xm1, [srcq+strideq*2]\n movhps xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, xm1, 1\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pmaddubsw m0, m5\n mova [tmpq+64*0], m0\n%else\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 m0, [srcq+strideq*1], 1\n movu xm1, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpermb m0, m4, m0\n vpermb m1, m4, m1\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n mova [tmpq+64*0], m0\n mova [tmpq+64*1], m1\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n movu xm2, [srcq+strideq*2+8*0]\n vinserti128 m2, [srcq+strideq*2+8*1], 1\n movu xm3, [srcq+stride3q +8*0]\n vinserti128 m3, [srcq+stride3q +8*1], 1\n lea srcq, [srcq+strideq*4]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+32*0], m0\n mova [tmpq+32*1], m1\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m3\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w32_loop:\n vpermb m0, m4, [srcq+strideq*0]\n vpermb m1, m4, [srcq+strideq*1]\n vpermb m2, m4, [srcq+strideq*2]\n vpermb m3, m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n%else\n.h_w32_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n movu xm1, [srcq+strideq*0+8*2]\n vinserti128 m1, [srcq+strideq*0+8*3], 1\n movu xm2, [srcq+strideq*1+8*0]\n vinserti128 m2, [srcq+strideq*1+8*1], 1\n movu xm3, [srcq+strideq*1+8*2]\n vinserti128 m3, [srcq+strideq*1+8*3], 1\n lea srcq, [srcq+strideq*2]\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n sub hd, mmsize*4/(32*2)\n jg .h_w32_loop\n RET\n.h_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w64_loop:\n vpermb m0, m4, [srcq+strideq*0+32*0]\n vpermb m1, m4, [srcq+strideq*0+32*1]\n vpermb m2, m4, [srcq+strideq*1+32*0]\n vpermb m3, m4, [srcq+strideq*1+32*1]\n lea srcq, [srcq+strideq*2]\n%else\n.h_w64_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n add srcq, strideq\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n add tmpq, mmsize*4\n%if cpuflag(avx512)\n sub hd, 2\n%else\n dec hd\n%endif\n jg .h_w64_loop\n RET\n.h_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n.h_w128_loop:\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n%else\n.h_w128_loop:\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n movu xm2, [srcq+8*4]\n vinserti128 m2, [srcq+8*5], 1\n movu xm3, [srcq+8*6]\n vinserti128 m3, [srcq+8*7], 1\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n%endif\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq+mmsize*0], m0\n mova [tmpq+mmsize*1], m1\n mova [tmpq+mmsize*2], m2\n mova [tmpq+mmsize*3], m3\n%if notcpuflag(avx512)\n movu xm0, [srcq+8* 8]\n vinserti128 m0, [srcq+8* 9], 1\n movu xm1, [srcq+8*10]\n vinserti128 m1, [srcq+8*11], 1\n movu xm2, [srcq+8*12]\n vinserti128 m2, [srcq+8*13], 1\n movu xm3, [srcq+8*14]\n vinserti128 m3, [srcq+8*15], 1\n%endif\n add tmpq, 32*8\n add srcq, strideq\n%if notcpuflag(avx512)\n pshufb m0, m4\n pshufb m1, m4\n pshufb m2, m4\n pshufb m3, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n mova [tmpq-32*4], m0\n mova [tmpq-32*3], m1\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n dec hd\n jg .h_w128_loop\n RET\n.v:\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]\n imul mxyd, 0xff01\n add mxyd, 16 << 8\n add wq, t2\n lea stride3q, [strideq*3]\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n jmp wq\n.v_w4:\n%if cpuflag(avx512)\n vpbroadcastd xm0, [srcq+strideq*0]\n mov r3d, 0x29\n vbroadcasti128 ym3, [bilin_v_shuf4]\n kmovb k1, r3d\n.v_w4_loop:\n vpblendmd xm1{k1}, xm0, [srcq+strideq*1] {1to4} ; __01 ____\n vpbroadcastd ym2, [srcq+strideq*2]\n vpbroadcastd ym2{k1}, [srcq+stride3q ] ; __2_ 23__\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym0, [srcq+strideq*0]\n punpckhqdq ym2{k1}, ym1, ym0 ; 012_ 234_\n pshufb ym2, ym3\n%else\n movd xm0, [srcq+strideq*0]\n.v_w4_loop:\n vpbroadcastd m1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x05 ; 0 2 2 2\n vpbroadcastd m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x0f ; 1 1 3 3\n vpblendd m2, m1, m0, 0xa0 ; 0 2 2 4\n vpblendd m1, m1, m3, 0xaa ; 0 1 2 3\n vpblendd m2, m2, m3, 0x55 ; 1 2 3 4\n punpcklbw m2, m1\n%endif\n pmaddubsw ym2, ym6\n mova [tmpq], ym2\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n RET\n.v_w8:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm8]\n vbroadcasti128 ym0, [srcq+strideq*0]\n%else\n movq xm0, [srcq+strideq*0]\n%endif\n.v_w8_loop:\n%if cpuflag(avx512icl)\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpbroadcastq ym0, [srcq+strideq*2]\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 ym0, [srcq+strideq*0], 0\n vpermt2b m1, m5, m0\n pmaddubsw m1, m6\n mova [tmpq], m1\n%else\n vpbroadcastq m1, [srcq+strideq*2]\n vpbroadcastq m2, [srcq+strideq*1]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m0, 0x03 ; 0 2 2 2\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m3, m3, m2, 0x33 ; 1 3 1 3\n vpblendd m2, m1, m3, 0x0f ; 1 3 2 2\n vpblendd m1, m1, m3, 0xf0 ; 0 2 1 3\n vpblendd m2, m2, m0, 0xc0 ; 1 3 2 4\n punpcklbw m3, m2, m1\n punpckhbw m2, m1\n pmaddubsw m3, m6\n pmaddubsw m2, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm16]\n movu xm0, [srcq+strideq*0]\n.v_w16_loop:\n movu xm2, [srcq+strideq*2]\n vinserti128 ym1, ym0, [srcq+strideq*1], 1\n vpermt2b m1, m5, m2\n vinserti128 ym2, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n movu xm0, [srcq+strideq*0]\n vpermt2b m2, m5, m0\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n%else\n vbroadcasti128 m0, [srcq+strideq*0]\n.v_w16_loop:\n vbroadcasti128 m1, [srcq+strideq*2]\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n shufpd m4, m0, m1, 0x0c ; 0 2 ; 0l2l 0h2h\n vbroadcasti128 m0, [srcq+strideq*0]\n shufpd m2, m2, m3, 0x0c ; 1 3 ; 1l3l 1h3h\n shufpd m1, m1, m0, 0x0c ; 2 4 ; 2l4l 2h4h\n punpcklbw m3, m2, m4\n punpcklbw m5, m1, m2\n punpckhbw m1, m2\n punpckhbw m2, m4\n pmaddubsw m3, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m1, m6\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m5\n mova [tmpq+32*2], m2\n mova [tmpq+32*3], m1\n%endif\n add tmpq, 32*4\n sub hd, 4\n jg .v_w16_loop\n RET\n.v_w32:\n%if cpuflag(avx512icl)\n mova m5, [bilin_v_perm32]\n movu ym0, [srcq+strideq*0]\n.v_w32_loop:\n movu ym2, [srcq+strideq*1]\n movu ym3, [srcq+strideq*2]\n movu ym4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpermt2b m0, m5, m2\n vpermt2b m2, m5, m3\n vpermt2b m3, m5, m4\n pmaddubsw m1, m0, m6\n movu ym0, [srcq+strideq*0]\n vpermt2b m4, m5, m0\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m4\n add tmpq, 64*4\n%else\n vpermq ym0, [srcq+strideq*0], q3120\n.v_w32_loop:\n vpermq ym1, [srcq+strideq*1], q3120\n vpermq ym2, [srcq+strideq*2], q3120\n vpermq ym3, [srcq+stride3q ], q3120\n lea srcq, [srcq+strideq*4]\n punpcklbw m4, m1, m0\n punpckhbw m5, m1, m0\n vpermq ym0, [srcq+strideq*0], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], ym4\n mova [tmpq+32*1], ym5\n punpcklbw m4, m2, m1\n punpckhbw m5, m2, m1\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], ym4\n mova [tmpq+32*3], ym5\n add tmpq, 32*8\n punpcklbw m4, m3, m2\n punpckhbw m5, m3, m2\n punpcklbw m1, m0, m3\n punpckhbw m2, m0, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m1, m6\n pmaddubsw m2, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m1\n mova [tmpq-32*1], m2\n%endif\n sub hd, 4\n jg .v_w32_loop\n RET\n.v_w64:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0]\n.v_w64_loop:\n vpermq m1, m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m1, m0\n punpckhbw m2, m1, m0\n vpermq m0, m5, [srcq+strideq*0]\n punpcklbw m3, m0, m1\n punpckhbw m1, m0, m1\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m1, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m2\n mova [tmpq+64*2], m3\n mova [tmpq+64*3], m1\n add tmpq, 64*4\n%else\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n.v_w64_loop:\n vpermq m2, [srcq+strideq*1+32*0], q3120\n vpermq m3, [srcq+strideq*1+32*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m5, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m4\n mova [tmpq+32*1], m5\n punpcklbw m4, m3, m1\n punpckhbw m5, m3, m1\n vpermq m0, [srcq+strideq*0+32*0], q3120\n vpermq m1, [srcq+strideq*0+32*1], q3120\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*2], m4\n mova [tmpq+32*3], m5\n add tmpq, 32*8\n punpcklbw m4, m0, m2\n punpckhbw m5, m0, m2\n punpcklbw m2, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n mova [tmpq-32*4], m4\n mova [tmpq-32*3], m5\n mova [tmpq-32*2], m2\n mova [tmpq-32*1], m3\n%endif\n sub hd, 2\n jg .v_w64_loop\n RET\n.v_w128:\n%if cpuflag(avx512)\n mova m5, [bilin_v_perm64]\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n.v_w128_loop:\n vpermq m2, m5, [srcq+strideq*1+ 0]\n vpermq m3, m5, [srcq+strideq*1+64]\n lea srcq, [srcq+strideq*2]\n punpcklbw m4, m2, m0\n punpckhbw m0, m2, m0\n pmaddubsw m4, m6\n pmaddubsw m0, m6\n mova [tmpq+64*0], m4\n mova [tmpq+64*1], m0\n punpcklbw m4, m3, m1\n punpckhbw m1, m3, m1\n pmaddubsw m4, m6\n pmaddubsw m1, m6\n mova [tmpq+64*2], m4\n mova [tmpq+64*3], m1\n vpermq m0, m5, [srcq+strideq*0+ 0]\n vpermq m1, m5, [srcq+strideq*0+64]\n punpcklbw m4, m0, m2\n punpckhbw m2, m0, m2\n pmaddubsw m4, m6\n pmaddubsw m2, m6\n mova [tmpq+64*4], m4\n mova [tmpq+64*5], m2\n punpcklbw m4, m1, m3\n punpckhbw m3, m1, m3\n pmaddubsw m4, m6\n pmaddubsw m3, m6\n mova [tmpq+64*6], m4\n mova [tmpq+64*7], m3\n add tmpq, 64*8\n sub hd, 2\n jg .v_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.v_w128_loop0:\n vpermq m0, [srcq+strideq*0], q3120\n.v_w128_loop:\n vpermq m1, [srcq+strideq*1], q3120\n lea srcq, [srcq+strideq*2]\n punpcklbw m2, m1, m0\n punpckhbw m3, m1, m0\n vpermq m0, [srcq+strideq*0], q3120\n punpcklbw m4, m0, m1\n punpckhbw m5, m0, m1\n pmaddubsw m2, m6\n pmaddubsw m3, m6\n pmaddubsw m4, m6\n pmaddubsw m5, m6\n mova [tmpq+32*0], m2\n mova [tmpq+32*1], m3\n mova [tmpq+32*8], m4\n mova [tmpq+32*9], m5\n add tmpq, 32*16\n sub hd, 2\n jg .v_w128_loop\n movzx hd, t2b\n add t0, 64\n add t1, 32\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .v_w128_loop0\n%endif\n RET\n.hv:\n ; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4\n ; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 7\n movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]\n shl mxyd, 11\n%if cpuflag(avx512)\n vpbroadcastw m6, mxyd\n%else\n movd xm6, mxyd\n vpbroadcastw m6, xm6\n%endif\n add wq, t2\n lea stride3q, [strideq*3]\n jmp wq\n.hv_w4:\n vbroadcasti128 ym4, [bilin_h_shuf4]\n vpbroadcastq ym0, [srcq+strideq*0]\n pshufb ym0, ym4\n pmaddubsw ym0, ym5\n.hv_w4_loop:\n movq xm1, [srcq+strideq*1]\n movhps xm1, [srcq+strideq*2]\n movq xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movhps xm2, [srcq+strideq*0]\n vinserti128 ym1, xm2, 1\n pshufb ym1, ym4\n pmaddubsw ym1, ym5 ; 1 2 3 4\n%if cpuflag(avx512)\n valignq ym2, ym1, ym0, 3 ; 0 1 2 3\n%else\n vpblendd ym2, ym1, ym0, 0xc0\n vpermq ym2, ym2, q2103 ; 0 1 2 3\n%endif\n mova ym0, ym1\n psubw ym1, ym2\n pmulhrsw ym1, ym6\n paddw ym1, ym2\n mova [tmpq], ym1\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n RET\n.hv_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m4, [bilin_h_shuf8]\n%endif\n vbroadcasti128 m0, [srcq+strideq*0]\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w8_loop:\n movu xm1, [srcq+strideq*1]\n%if cpuflag(avx512)\n vinserti128 ym1, [srcq+strideq*2], 1\n vinserti128 m1, [srcq+stride3q ], 2\n lea srcq, [srcq+strideq*4]\n vinserti128 m1, [srcq+strideq*0], 3\n pshufb m1, m4\n pmaddubsw m1, m5 ; 1 2 3 4\n valignq m2, m1, m0, 6 ; 0 1 2 3\n mova m0, m1\n psubw m1, m2\n pmulhrsw m1, m6\n paddw m1, m2\n mova [tmpq], m1\n%else\n vinserti128 m1, m1, [srcq+strideq*2], 1\n movu xm2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 m2, m2, [srcq+strideq*0], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5 ; 1 2\n vperm2i128 m3, m0, m1, 0x21 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vperm2i128 m2, m1, m0, 0x21 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+32*0], m1\n mova [tmpq+32*1], m3\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .hv_w8_loop\n RET\n.hv_w16:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm16]\n vbroadcasti32x8 m0, [srcq+strideq*0]\n vpermb m0, m4, m0\n%else\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n%endif\n pmaddubsw m0, m5\n.hv_w16_loop:\n%if cpuflag(avx512icl)\n movu ym1, [srcq+strideq*1]\n vinserti32x8 m1, [srcq+strideq*2], 1\n movu ym2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti32x8 m2, [srcq+strideq*0], 1\n vpermb m1, m4, m1\n vpermb m2, m4, m2\n pmaddubsw m1, m5 ; 1 2\n vshufi32x4 m3, m0, m1, q1032 ; 0 1\n pmaddubsw m0, m2, m5 ; 3 4\n vshufi32x4 m2, m1, m0, q1032 ; 2 3\n psubw m1, m3\n pmulhrsw m1, m6\n paddw m1, m3\n psubw m3, m0, m2\n pmulhrsw m3, m6\n paddw m3, m2\n mova [tmpq+64*0], m1\n mova [tmpq+64*1], m3\n%else\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*1], m2\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .hv_w16_loop\n RET\n.hv_w32:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+strideq*0]\n pmaddubsw m0, m5\n.hv_w32_loop:\n vpermb m1, m4, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermb m2, m4, [srcq+strideq*0]\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+64*0], m3\n mova [tmpq+64*1], m2\n add tmpq, 64*2\n sub hd, 2\n%else\n movu xm0, [srcq+8*0]\n vinserti128 m0, [srcq+8*1], 1\n movu xm1, [srcq+8*2]\n vinserti128 m1, [srcq+8*3], 1\n pshufb m0, m4\n pshufb m1, m4\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w32_loop:\n add srcq, strideq\n movu xm2, [srcq+8*0]\n vinserti128 m2, m2, [srcq+8*1], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m0\n pmulhrsw m3, m6\n paddw m3, m0\n mova m0, m2\n mova [tmpq+ 0], m3\n movu xm2, [srcq+8*2]\n vinserti128 m2, m2, [srcq+8*3], 1\n pshufb m2, m4\n pmaddubsw m2, m5\n psubw m3, m2, m1\n pmulhrsw m3, m6\n paddw m3, m1\n mova m1, m2\n mova [tmpq+32], m3\n add tmpq, 32*2\n dec hd\n%endif\n jg .hv_w32_loop\n RET\n.hv_w64:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n.hv_w64_loop:\n add srcq, strideq\n vpermb m2, m4, [srcq+32*0]\n vpermb m3, m4, [srcq+32*1]\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n psubw m7, m2, m0\n psubw m8, m3, m1\n pmulhrsw m7, m6\n pmulhrsw m8, m6\n paddw m7, m0\n paddw m8, m1\n mova [tmpq+ 0], m7\n mova [tmpq+64], m8\n mova m0, m2\n mova m1, m3\n add tmpq, 64*2\n dec hd\n jg .hv_w64_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(3<<8)]\n.hv_w64_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w64_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n add tmpq, 32*8\n mova [tmpq-32*4], m2\n sub hd, 2\n jg .hv_w64_loop\n movzx hd, t2b\n add t0, 32\n add t1, 16\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w64_loop0\n%endif\n RET\n.hv_w128:\n%if cpuflag(avx512icl)\n mova m4, [bilin_h_perm32]\n vpermb m0, m4, [srcq+32*0]\n vpermb m1, m4, [srcq+32*1]\n vpermb m2, m4, [srcq+32*2]\n vpermb m3, m4, [srcq+32*3]\n pmaddubsw m0, m5\n pmaddubsw m1, m5\n pmaddubsw m2, m5\n pmaddubsw m3, m5\n.hv_w128_loop:\n add srcq, strideq\n vpermb m7, m4, [srcq+32*0]\n vpermb m8, m4, [srcq+32*1]\n vpermb m9, m4, [srcq+32*2]\n vpermb m10, m4, [srcq+32*3]\n pmaddubsw m7, m5\n pmaddubsw m8, m5\n pmaddubsw m9, m5\n pmaddubsw m10, m5\n psubw m11, m7, m0\n psubw m12, m8, m1\n psubw m13, m9, m2\n psubw m14, m10, m3\n pmulhrsw m11, m6\n pmulhrsw m12, m6\n pmulhrsw m13, m6\n pmulhrsw m14, m6\n paddw m11, m0\n paddw m12, m1\n paddw m13, m2\n paddw m14, m3\n mova [tmpq+64*0], m11\n mova [tmpq+64*1], m12\n mova [tmpq+64*2], m13\n mova [tmpq+64*3], m14\n mova m0, m7\n mova m1, m8\n mova m2, m9\n mova m3, m10\n add tmpq, 64*4\n dec hd\n jg .hv_w128_loop\n%else\n mov t0, tmpq\n mov t1, srcq\n lea t2d, [hq+(7<<8)]\n.hv_w128_loop0:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, m0, [srcq+strideq*0+8*1], 1\n pshufb m0, m4\n pmaddubsw m0, m5\n.hv_w128_loop:\n movu xm1, [srcq+strideq*1+8*0]\n vinserti128 m1, m1, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n movu xm2, [srcq+strideq*0+8*0]\n vinserti128 m2, m2, [srcq+strideq*0+8*1], 1\n pshufb m1, m4\n pshufb m2, m4\n pmaddubsw m1, m5\n psubw m3, m1, m0\n pmulhrsw m3, m6\n paddw m3, m0\n pmaddubsw m0, m2, m5\n psubw m2, m0, m1\n pmulhrsw m2, m6\n paddw m2, m1\n mova [tmpq+32*0], m3\n mova [tmpq+32*8], m2\n add tmpq, 32*16\n sub hd, 2\n jg .hv_w128_loop\n movzx hd, t2b\n add t0, mmsize\n add t1, mmsize/2\n mov tmpq, t0\n mov srcq, t1\n sub t2d, 1<<8\n jg .hv_w128_loop0\n%endif\n RET\n%endmacro\n\n; int8_t subpel_filters[5][15][8]\n%assign FILTER_REGULAR (0*15 << 16) | 3*15\n%assign FILTER_SMOOTH (1*15 << 16) | 4*15\n%assign FILTER_SHARP (2*15 << 16) | 3*15\n\n%if WIN64\nDECLARE_REG_TMP 4, 5\n%else\nDECLARE_REG_TMP 7, 8\n%endif\n%macro PUT_8TAP_FN 3 ; type, type_h, type_v\ncglobal put_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)\n%endif\n%endmacro\n\nPUT_8TAP_FN regular, REGULAR, REGULAR\nPUT_8TAP_FN regular_sharp, REGULAR, SHARP\nPUT_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPUT_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPUT_8TAP_FN smooth, SMOOTH, SMOOTH\nPUT_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPUT_8TAP_FN sharp_regular, SHARP, REGULAR\nPUT_8TAP_FN sharp, SHARP, SHARP\nPUT_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal put_8tap, 4, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r8, [put_avx2]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r8+wq*2+table_offset(put,)]\n add wq, r8\n lea r6, [ssq*3]\n lea r7, [dsq*3]\n%if WIN64\n pop r8\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n vpbroadcastd m5, [pw_34] ; 2 + (8 << 2)\n WIN64_SPILL_XMM 11\n cmp wd, 4\n jl .h_w2\n vbroadcasti128 m6, [subpel_h_shufA]\n je .h_w4\n tzcnt wd, wd\n vbroadcasti128 m7, [subpel_h_shufB]\n vbroadcasti128 m8, [subpel_h_shufC]\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r8+wq*2+table_offset(put, _8tap_h)]\n vpbroadcastd m9, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+4]\n add wq, r8\n jmp wq\n.h_w2:\n movzx mxd, mxb\n dec srcq\n mova xm4, [subpel_h_shuf4]\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w2_loop:\n movq xm0, [srcq+ssq*0]\n movhps xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm4\n pmaddubsw xm0, xm3\n phaddw xm0, xm0\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w2_loop\n RET\n.h_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd xm3, [r8+mxq*8+subpel_filters-put_avx2+2]\n.h_w4_loop:\n movq xm0, [srcq+ssq*0]\n movq xm1, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm0, xm6\n pshufb xm1, xm6\n pmaddubsw xm0, xm3\n pmaddubsw xm1, xm3\n phaddw xm0, xm1\n paddw xm0, xm5\n psraw xm0, 6\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w4_loop\n RET\n.h_w8:\n%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]\n pshufb m%2, m%1, m7\n pshufb m%3, m%1, m8\n pshufb m%1, m6\n pmaddubsw m%4, m%2, m9\n pmaddubsw m%2, m10\n pmaddubsw m%3, m10\n pmaddubsw m%1, m9\n paddw m%3, m%4\n paddw m%1, m%2\n phaddw m%1, m%3\n paddw m%1, m5\n psraw m%1, 6\n%endmacro\n movu xm0, [srcq+ssq*0]\n vinserti128 m0, m0, [srcq+ssq*1], 1\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 0, 1, 2, 3\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w8\n RET\n.h_w16:\n movu xm0, [srcq+ssq*0+8*0]\n vinserti128 m0, m0, [srcq+ssq*1+8*0], 1\n movu xm1, [srcq+ssq*0+8*1]\n vinserti128 m1, m1, [srcq+ssq*1+8*1], 1\n PUT_8TAP_H 0, 2, 3, 4\n lea srcq, [srcq+ssq*2]\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .h_w16\n RET\n.h_w32:\n xor r6d, r6d\n jmp .h_start\n.h_w64:\n mov r6, -32*1\n jmp .h_start\n.h_w128:\n mov r6, -32*3\n.h_start:\n sub srcq, r6\n sub dstq, r6\n mov r4, r6\n.h_loop:\n movu m0, [srcq+r6+8*0]\n movu m1, [srcq+r6+8*1]\n PUT_8TAP_H 0, 2, 3, 4\n PUT_8TAP_H 1, 2, 3, 4\n packuswb m0, m1\n mova [dstq+r6], m0\n add r6, 32\n jle .h_loop\n add srcq, ssq\n add dstq, dsq\n mov r6, r4\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n tzcnt r6d, wd\n movzx r6d, word [r8+r6*2+table_offset(put, _8tap_v)]\n vpbroadcastd m7, [pw_512]\n lea myq, [r8+myq*8+subpel_filters-put_avx2]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n add r6, r8\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n jmp r6\n.v_w2:\n movd xm2, [srcq+ssq*0]\n pinsrw xm2, [srcq+ssq*1], 2\n pinsrw xm2, [srcq+ssq*2], 4\n pinsrw xm2, [srcq+ss3q ], 6 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w2_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 2\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w2_loop\n RET\n.v_w4:\n movd xm2, [srcq+ssq*0]\n pinsrd xm2, [srcq+ssq*1], 1\n pinsrd xm2, [srcq+ssq*2], 2\n pinsrd xm2, [srcq+ss3q ], 3 ; 0 1 2 3\n lea srcq, [srcq+ssq*4]\n movd xm3, [srcq+ssq*0]\n vpbroadcastd xm1, [srcq+ssq*1]\n vpbroadcastd xm0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd xm3, xm3, xm1, 0x02 ; 4 5\n vpblendd xm1, xm1, xm0, 0x02 ; 5 6\n palignr xm4, xm3, xm2, 4 ; 1 2 3 4\n punpcklbw xm3, xm1 ; 45 56\n punpcklbw xm1, xm2, xm4 ; 01 12\n punpckhbw xm2, xm4 ; 23 34\n.v_w4_loop:\n pmaddubsw xm5, xm1, xm8 ; a0 b0\n mova xm1, xm2\n pmaddubsw xm2, xm9 ; a1 b1\n paddw xm5, xm2\n mova xm2, xm3\n pmaddubsw xm3, xm10 ; a2 b2\n paddw xm5, xm3\n vpbroadcastd xm4, [srcq+ssq*0]\n vpblendd xm3, xm0, xm4, 0x02 ; 6 7\n vpbroadcastd xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd xm4, xm4, xm0, 0x02 ; 7 8\n punpcklbw xm3, xm4 ; 67 78\n pmaddubsw xm4, xm3, xm11 ; a3 b3\n paddw xm5, xm4\n pmulhrsw xm5, xm7\n packuswb xm5, xm5\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w4_loop\n RET\n.v_w8:\n movq xm1, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m2, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m6, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n pmaddubsw m5, m1, m8 ; a0 b0\n mova m1, m2\n pmaddubsw m2, m9 ; a1 b1\n paddw m5, m2\n mova m2, m3\n pmaddubsw m3, m10 ; a2 b2\n paddw m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 67 78\n pmaddubsw m4, m3, m11 ; a3 b3\n paddw m5, m4\n pmulhrsw m5, m7\n vextracti128 xm4, m5, 1\n packuswb xm5, xm4\n movq [dstq+dsq*0], xm5\n movhps [dstq+dsq*1], xm5\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w8_loop\n RET\n.v_w16:\n.v_w32:\n.v_w64:\n.v_w128:\n lea r6d, [wq-16]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+ssq*0]\n vbroadcasti128 m5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m0, [srcq+ssq*1]\n vbroadcasti128 m6, [srcq+ssq*0]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m1, [srcq+ssq*0]\n vbroadcasti128 m2, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m3, [srcq+ssq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vbroadcasti128 m13, [srcq+ssq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n packuswb m14, m15\n vpermq m14, m14, q3120\n mova [dstq+dsq*0], xm14\n vextracti128 [dstq+dsq*1], m14, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r4, 16\n add r7, 16\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n cmp wd, 4\n jg .hv_w8\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m7, [r8+mxq*8+subpel_filters-put_avx2+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m8, [pw_8192]\n vpbroadcastd m9, [pd_512]\n pshufd m10, m0, q0000\n pshufd m11, m0, q1111\n pshufd m12, m0, q2222\n pshufd m13, m0, q3333\n cmp wd, 4\n je .hv_w4\n vbroadcasti128 m6, [subpel_h_shuf4]\n movq xm2, [srcq+ssq*0]\n movhps xm2, [srcq+ssq*1]\n movq xm0, [srcq+ssq*2]\n movhps xm0, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m2, m2, m3, 0x30\n vpblendd m0, m0, m1, 0x30\n vpblendd m2, m2, m4, 0xc0\n pshufb m2, m6\n pshufb m0, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n phaddw m2, m0\n pmulhrsw m2, m8\n vextracti128 xm3, m2, 1\n palignr xm4, xm3, xm2, 4\n punpcklwd xm1, xm2, xm4 ; 01 12\n punpckhwd xm2, xm4 ; 23 34\n pshufd xm0, xm3, q2121\n punpcklwd xm3, xm0 ; 45 56\n.hv_w2_loop:\n pmaddwd xm5, xm1, xm10 ; a0 b0\n mova xm1, xm2\n pmaddwd xm2, xm11 ; a1 b1\n paddd xm5, xm2\n mova xm2, xm3\n pmaddwd xm3, xm12 ; a2 b2\n paddd xm5, xm3\n movq xm4, [srcq+ssq*0]\n movhps xm4, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n pshufb xm4, xm6\n pmaddubsw xm4, xm7\n phaddw xm4, xm4\n pmulhrsw xm4, xm8\n palignr xm3, xm4, xm0, 12\n mova xm0, xm4\n punpcklwd xm3, xm0 ; 67 78\n pmaddwd xm4, xm3, xm13 ; a3 b3\n paddd xm5, xm9\n paddd xm5, xm4\n psrad xm5, 10\n packssdw xm5, xm5\n packuswb xm5, xm5\n pextrw [dstq+dsq*0], xm5, 0\n pextrw [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w2_loop\n RET\n.hv_w4:\n mova m6, [subpel_h_shuf4]\n vpbroadcastq m2, [srcq+ssq*0]\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m0, [srcq+ssq*2]\n vpbroadcastq m5, [srcq+ss3q ]\n lea srcq, [srcq+ssq*4]\n vpbroadcastq m3, [srcq+ssq*0]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpbroadcastq m4, [srcq+ssq*1]\n vpbroadcastq m1, [srcq+ssq*2]\n add srcq, ss3q\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m4, 0xcc ; 4 5\n pshufb m2, m6\n pshufb m0, m6\n pshufb m3, m6\n pshufb m1, m6\n pmaddubsw m2, m7\n pmaddubsw m0, m7\n pmaddubsw m3, m7\n pmaddubsw m1, m7\n phaddw m2, m0\n phaddw m3, m1\n pmulhrsw m2, m8\n pmulhrsw m3, m8\n palignr m4, m3, m2, 4\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m10 ; a0 b0\n mova m1, m2\n pmaddwd m2, m11 ; a1 b1\n paddd m5, m2\n mova m2, m3\n pmaddwd m3, m12 ; a2 b2\n paddd m5, m3\n vpbroadcastq m4, [srcq+ssq*0]\n vpbroadcastq m3, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m3, 0xcc ; 7 8\n pshufb m4, m6\n pmaddubsw m4, m7\n phaddw m4, m4\n pmulhrsw m4, m8\n palignr m3, m4, m0, 12\n mova m0, m4\n punpcklwd m3, m0 ; 67 78\n pmaddwd m4, m3, m13 ; a3 b3\n paddd m5, m9\n paddd m5, m4\n psrad m5, 10\n vextracti128 xm4, m5, 1\n packssdw xm5, xm4\n packuswb xm5, xm5\n pshuflw xm5, xm5, q3120\n movd [dstq+dsq*0], xm5\n pextrd [dstq+dsq*1], xm5, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w4_loop\n RET\n.hv_w8:\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r8+mxq*8+subpel_filters-put_avx2+0]\n vpbroadcastd m11, [r8+mxq*8+subpel_filters-put_avx2+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 6\n cmovs myd, mxd\n vpbroadcastq m0, [r8+myq*8+subpel_filters-put_avx2]\n lea ss3q, [ssq*3]\n sub srcq, ss3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n lea r6d, [wq-8]\n mov r4, dstq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+ssq*0]\n movu xm5, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n movu xm6, [srcq+ssq*0]\n vbroadcasti128 m0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+ssq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+ssq*1], 1 ; 2 5\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 3 6\n%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]\n pshufb %3, %1, %6\n pshufb %4, %1, %7\n pshufb %1, %5\n pmaddubsw %2, %3, m10\n pmaddubsw %4, m11\n pmaddubsw %3, m11\n pmaddubsw %1, m10\n paddw %2, %4\n paddw %1, %3\n phaddw %1, %2\n%endmacro\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 r6m, m0, 1 ; not enough registers\n movu xm0, [srcq+ssq*1]\n lea srcq, [srcq+ssq*2]\n vinserti128 m0, m0, [srcq+ssq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_512]\n vbroadcasti128 m6, r6m\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 10\n psrad m7, 10\n packssdw m8, m7\n vextracti128 xm7, m8, 1\n packuswb xm8, xm7\n pshufd xm7, xm8, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r4, 8\n add r7, 8\n mov dstq, r4\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n RET\n\n%macro PREP_8TAP_H 0\n %if cpuflag(avx512)\n vpermb m10, m5, m0\n vpermb m11, m5, m1\n vpermb m12, m6, m0\n vpermb m13, m6, m1\n vpermb m14, m7, m0\n vpermb m15, m7, m1\n mova m0, m4\n mova m2, m4\n mova m1, m4\n mova m3, m4\n vpdpbusd m0, m10, m8\n vpdpbusd m2, m12, m8\n vpdpbusd m1, m11, m8\n vpdpbusd m3, m13, m8\n vpdpbusd m0, m12, m9\n vpdpbusd m2, m14, m9\n vpdpbusd m1, m13, m9\n vpdpbusd m3, m15, m9\n packssdw m0, m2\n packssdw m1, m3\n psraw m0, 2\n psraw m1, 2\n mova [tmpq+ 0], m0\n mova [tmpq+64], m1\n %else\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n pmaddubsw m1, m8\n pmaddubsw m0, m2, m8\n pmaddubsw m2, m9\n pmaddubsw m3, m9\n paddw m1, m2\n paddw m0, m3\n phaddw m0, m1, m0\n pmulhrsw m0, m4\n %endif\n%endmacro\n\n%macro PREP_8TAP_V_W4 5 ; round, weights\n movd xm0, [srcq+strideq*0]\n vpbroadcastd ym1, [srcq+strideq*2]\n vpbroadcastd xm2, [srcq+strideq*1]\n vpbroadcastd ym3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd ym1, ym1, ym0, 0x01 ; 0 2 2 _ 2 _ _ _\n vpblendd ym3, ym3, ym2, 0x03 ; 1 1 3 3 3 3 _ _\n vpbroadcastd ym0, [srcq+strideq*0]\n vpbroadcastd ym2, [srcq+strideq*1]\n vpblendd ym1, ym1, ym0, 0x68 ; 0 2 2 4 2 4 4 _\n vpbroadcastd ym0, [srcq+strideq*2]\n vbroadcasti128 ym5, [deint_shuf4]\n vpblendd ym3, ym3, ym2, 0xc0 ; 1 1 3 3 3 3 5 5\n vpblendd ym2, ym3, ym1, 0x55 ; 0 1 2 3 2 3 4 5\n vpblendd ym3, ym3, ym1, 0xaa ; 1 2 3 4 3 4 5 _\n punpcklbw ym1, ym2, ym3 ; 01 12 23 34\n vpblendd ym3, ym3, ym0, 0x80 ; 1 2 3 4 3 4 5 6\n punpckhbw ym2, ym3 ; 23 34 45 56\n.v_w4_loop:\n pinsrd xm0, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n vpbroadcastd ym3, [srcq+strideq*0]\n vpbroadcastd ym4, [srcq+strideq*1]\n vpblendd ym3, ym3, ym4, 0x20 ; _ _ 8 _ 8 9 _ _\n vpblendd ym3, ym3, ym0, 0x03 ; 6 7 8 _ 8 9 _ _\n vpbroadcastd ym0, [srcq+strideq*2]\n vpblendd ym3, ym3, ym0, 0x40 ; 6 7 8 _ 8 9 a _\n pshufb ym3, ym5 ; 67 78 89 9a\n pmaddubsw ym4, ym1, ym%2\n vperm2i128 ym1, ym2, ym3, 0x21 ; 45 56 67 78\n pmaddubsw ym2, ym%3\n paddw ym4, ym2\n mova ym2, ym3\n pmaddubsw ym3, ym%5\n paddw ym3, ym4\n pmaddubsw ym4, ym1, ym%4\n paddw ym3, ym4\n pmulhrsw ym3, ym%1\n mova [tmpq], ym3\n%endmacro\n\n%macro PREP_8TAP_FN 3 ; type, type_h, type_v\ncglobal prep_8tap_%1\n mov t0d, FILTER_%2\n mov t1d, FILTER_%3\n%ifnidn %1, sharp_smooth ; skip the jump in the last filter\n jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)\n%endif\n%endmacro\n\n%macro PREP_8TAP 0\n %if WIN64\n DECLARE_REG_TMP 6, 4\n %else\n DECLARE_REG_TMP 6, 7\n %endif\nPREP_8TAP_FN regular, REGULAR, REGULAR\nPREP_8TAP_FN regular_sharp, REGULAR, SHARP\nPREP_8TAP_FN regular_smooth, REGULAR, SMOOTH\nPREP_8TAP_FN smooth_regular, SMOOTH, REGULAR\nPREP_8TAP_FN smooth, SMOOTH, SMOOTH\nPREP_8TAP_FN smooth_sharp, SMOOTH, SHARP\nPREP_8TAP_FN sharp_regular, SHARP, REGULAR\nPREP_8TAP_FN sharp, SHARP, SHARP\nPREP_8TAP_FN sharp_smooth, SHARP, SMOOTH\n\ncglobal prep_8tap, 3, 8, 0, tmp, src, stride, w, h, mx, my, stride3\n imul mxd, mxm, 0x010101\n add mxd, t0d ; 8tap_h, mx, 4tap_h\n imul myd, mym, 0x010101\n add myd, t1d ; 8tap_v, my, 4tap_v\n lea r7, [prep%+SUFFIX]\n movsxd wq, wm\n movifnidn hd, hm\n test mxd, 0xf00\n jnz .h\n test myd, 0xf00\n jnz .v\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep,)]\n add wq, r7\n lea r6, [strideq*3]\n%if WIN64\n pop r7\n%endif\n jmp wq\n.h:\n test myd, 0xf00\n jnz .hv\n%if cpuflag(avx512)\n vpbroadcastd m4, [pd_2]\n%else\n vpbroadcastd m4, [pw_8192]\n vbroadcasti128 m5, [subpel_h_shufA]\n%endif\n WIN64_SPILL_XMM 10\n cmp wd, 4\n je .h_w4\n tzcnt wd, wd\n%if notcpuflag(avx512)\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n%endif\n shr mxd, 16\n sub srcq, 3\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_h)]\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m9, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n add wq, r7\n jmp wq\n.h_w4:\n%if cpuflag(avx512)\n mov r3d, 0x4\n kmovb k1, r3d\n vbroadcasti128 ym5, [subpel_h_shufA]\n%endif\n movzx mxd, mxb\n dec srcq\n vpbroadcastd ym6, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n lea stride3q, [strideq*3]\n.h_w4_loop:\n%if cpuflag(avx512icl)\n mova ym0, ym4\n mova ym1, ym4\n movq xm2, [srcq+strideq*0]\n movq xm3, [srcq+strideq*1]\n vpbroadcastq ym2{k1}, [srcq+strideq*2]\n vpbroadcastq ym3{k1}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pshufb ym2, ym5\n pshufb ym3, ym5\n vpdpbusd ym0, ym2, ym6\n vpdpbusd ym1, ym3, ym6\n packssdw ym0, ym1\n psraw ym0, 2\n%else\n movq xm0, [srcq+strideq*0]\n vpbroadcastq m2, [srcq+strideq*2]\n movq xm1, [srcq+strideq*1]\n vpblendd m0, m0, m2, 0xf0\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpblendd m1, m1, m2, 0xf0\n pshufb m0, m5\n pshufb m1, m5\n pmaddubsw m0, m6\n pmaddubsw m1, m6\n phaddw m0, m1\n pmulhrsw m0, m4\n%endif\n mova [tmpq], ym0\n add tmpq, 32\n sub hd, 4\n jg .h_w4_loop\n RET\n.h_w8:\n%if cpuflag(avx512)\n vbroadcasti128 m5, [subpel_h_shufA]\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n lea stride3q, [strideq*3]\n%endif\n.h_w8_loop:\n movu xm0, [srcq+strideq*0]\n vinserti128 ym0, [srcq+strideq*1], 1\n%if cpuflag(avx512)\n vinserti128 m0, [srcq+strideq*2], 2\n vinserti128 m0, [srcq+stride3q ], 3\n%endif\n lea srcq, [srcq+strideq*(mmsize/(8*2))]\n%if cpuflag(avx512icl)\n mova m10, m4\n mova m11, m4\n pshufb m1, m0, m5\n pshufb m2, m0, m6\n pshufb m3, m0, m7\n vpdpbusd m10, m1, m8\n vpdpbusd m11, m2, m8\n vpdpbusd m10, m2, m9\n vpdpbusd m11, m3, m9\n packssdw m10, m11\n psraw m0, m10, 2\n%else\n PREP_8TAP_H\n%endif\n mova [tmpq], m0\n add tmpq, mmsize\n sub hd, mmsize/(8*2)\n jg .h_w8_loop\n RET\n.h_w16:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm16a]\n mova m6, [spel_h_perm16b]\n mova m7, [spel_h_perm16c]\n lea stride3q, [strideq*3]\n.h_w16_loop:\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*2]\n vinserti32x8 m0, [srcq+strideq*1], 1\n vinserti32x8 m1, [srcq+stride3q ], 1\n lea srcq, [srcq+strideq*4]\n PREP_8TAP_H\n%else\n.h_w16_loop:\n movu xm0, [srcq+strideq*0+8*0]\n vinserti128 m0, [srcq+strideq*0+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+strideq*1+8*0]\n vinserti128 m0, m0, [srcq+strideq*1+8*1], 1\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n sub hd, mmsize*2/(16*2)\n jg .h_w16_loop\n RET\n.h_w32:\n%if cpuflag(avx512icl)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n.h_w32_loop:\n movu m0, [srcq+strideq*0]\n movu m1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n PREP_8TAP_H\n add tmpq, 64*2\n sub hd, 2\n jg .h_w32_loop\n RET\n%else\n xor r6d, r6d\n jmp .h_start\n%endif\n.h_w64:\n%if cpuflag(avx512)\n xor r6d, r6d\n%else\n mov r6, -32*1\n%endif\n jmp .h_start\n.h_w128:\n%if cpuflag(avx512)\n mov r6, -64*1\n%else\n mov r6, -32*3\n%endif\n.h_start:\n%if cpuflag(avx512)\n mova m5, [spel_h_perm32a]\n mova m6, [spel_h_perm32b]\n mova m7, [spel_h_perm32c]\n%endif\n sub srcq, r6\n mov r5, r6\n.h_loop:\n%if cpuflag(avx512icl)\n movu m0, [srcq+r6+32*0]\n movu m1, [srcq+r6+32*1]\n PREP_8TAP_H\n%else\n movu xm0, [srcq+r6+8*0]\n vinserti128 ym0, [srcq+r6+8*1], 1\n PREP_8TAP_H\n mova [tmpq+32*0], m0\n movu xm0, [srcq+r6+8*2]\n vinserti128 ym0, [srcq+r6+8*3], 1\n PREP_8TAP_H\n mova [tmpq+32*1], m0\n%endif\n add tmpq, mmsize*2\n add r6, mmsize\n jle .h_loop\n add srcq, strideq\n mov r6, r5\n dec hd\n jg .h_loop\n RET\n.v:\n %assign stack_offset stack_offset - stack_size_padded\n WIN64_SPILL_XMM 16\n movzx mxd, myb ; Select 4-tap/8-tap filter multipliers.\n shr myd, 16 ; Note that the code is 8-tap only, having\n cmp hd, 4 ; a separate 4-tap code path for (4|8|16)x4\n cmove myd, mxd ; had a negligible effect on performance.\n ; TODO: Would a 6-tap code path be worth it?\n%if cpuflag(avx512)\n tzcnt wd, wd\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_v)]\n add wq, r7\n%endif\n lea myq, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n vpbroadcastd m7, [pw_8192]\n vpbroadcastw m8, [myq+0]\n vpbroadcastw m9, [myq+2]\n vpbroadcastw m10, [myq+4]\n vpbroadcastw m11, [myq+6]\n%if cpuflag(avx512)\n jmp wq\n%else\n cmp wd, 8\n jg .v_w16\n je .v_w8\n%endif\n.v_w4:\n%if cpuflag(avx512)\n AVX512_MM_PERMUTATION\n PREP_8TAP_V_W4 23, 24, 25, 26, 27\n AVX512_MM_PERMUTATION\n%else\n PREP_8TAP_V_W4 7, 8, 9, 10, 11\n%endif\n add tmpq, 32\n sub hd, 4\n jg .v_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.v_w8:\n%if cpuflag(avx512)\n mov r3d, 0xf044\n kmovw k1, r3d\n kshiftrw k2, k1, 8\n movq xm0, [srcq+strideq*0]\n vpbroadcastq ym1, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vmovdqa64 ym0{k1}, ym1\n vmovdqa64 ym1{k1}, ym2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n punpcklbw ym0, ym1 ; 01 12 __ __\n punpcklbw m2, m3 ; 23 34 23 34\n punpcklbw m4, m5 ; 45 56 45 56\n vmovdqa64 m0{k2}, m2 ; 01 12 23 34\n vmovdqa64 m2{k2}, m4 ; 23 34 45 56\n.v_w8_loop:\n vpbroadcastq m1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n pmaddubsw m14, m0, m8\n pmaddubsw m15, m2, m9\n vpblendmq m0{k1}, m6, m1\n vpblendmq m2{k1}, m1, m3\n vpbroadcastq m6, [srcq+strideq*2]\n paddw m14, m15\n punpcklbw m2, m0, m2 ; 67 78 67 78\n vpblendmq m12{k1}, m3, m5\n vpblendmq m13{k1}, m5, m6\n vpblendmq m0{k2}, m4, m2 ; 45 56 67 78\n punpcklbw m4, m12, m13 ; 89 9a 89 9a\n vmovdqa64 m2{k2}, m4 ; 67 78 89 9a\n pmaddubsw m12, m0, m10\n pmaddubsw m13, m2, m11\n paddw m14, m12\n paddw m14, m13\n pmulhrsw m14, m7\n mova [tmpq], m14\n%else\n movq xm1, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m2, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m1, m1, m4, 0x30\n vpblendd m4, m4, m2, 0x30\n punpcklbw m1, m4 ; 01 12\n vpblendd m2, m2, m5, 0x30\n vpblendd m5, m5, m3, 0x30\n punpcklbw m2, m5 ; 23 34\n vpblendd m3, m3, m6, 0x30\n vpblendd m6, m6, m0, 0x30\n punpcklbw m3, m6 ; 45 56\n.v_w8_loop:\n vpbroadcastq m4, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n pmaddubsw m5, m2, m9 ; a1\n pmaddubsw m6, m2, m8 ; b0\n vpblendd m2, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*0]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m2, m4 ; 67 78\n pmaddubsw m1, m8 ; a0\n pmaddubsw m4, m3, m9 ; b1\n paddw m5, m1\n mova m1, m3\n pmaddubsw m3, m10 ; a2\n paddw m6, m4\n paddw m5, m3\n vpbroadcastq m4, [srcq+strideq*1]\n vpblendd m3, m0, m4, 0x30\n vpbroadcastq m0, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0x30\n punpcklbw m3, m4 ; 89 9a\n pmaddubsw m4, m2, m11 ; a3\n paddw m5, m4\n pmaddubsw m4, m2, m10 ; b2\n paddw m6, m4\n pmaddubsw m4, m3, m11 ; b3\n paddw m6, m4\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n mova [tmpq+32*0], m5\n mova [tmpq+32*1], m6\n%endif\n add tmpq, 32*2\n sub hd, 4\n jg .v_w8_loop\n RET\n.v_w16:\n%if cpuflag(avx512)\n mov r3d, 0xf0\n kmovb k1, r3d\n vbroadcasti128 m0, [srcq+strideq*0]\n vbroadcasti128 m1, [srcq+strideq*1]\n vbroadcasti128 m2, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n vmovdqa64 m0{k1}, m1\n vmovdqa64 m1{k1}, m2\n vmovdqa64 m2{k1}, m3\n vmovdqa64 m3{k1}, m4\n vmovdqa64 m4{k1}, m5\n vmovdqa64 m5{k1}, m6\n shufpd m0, m2, 0xcc ; 0a_2a 0b_2b 1a_3a 1b_3b\n shufpd m1, m3, 0xcc ; 1a_3a 1b_3b 2a_4a 2b_4b\n shufpd m4, m4, 0x44 ; 4a_-- 4b_-- 5a_-- 5b_--\n shufpd m5, m5, 0x44 ; 5a_-- 5b_-- 6a_-- 6b_--\n punpckhbw m2, m0, m1 ; 23a 23b 34a 34b\n punpcklbw m0, m1 ; 01a 01b 12a 12b\n punpcklbw m4, m5 ; 45a 45b 56a 56b\n.v_w16_loop:\n vbroadcasti128 m3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vbroadcasti128 m5, [srcq+strideq*0]\n vpblendmq m1{k1}, m6, m3\n vmovdqa64 m3{k1}, m5\n pmaddubsw m12, m0, m8\n pmaddubsw m13, m2, m8\n pmaddubsw m14, m2, m9\n pmaddubsw m15, m4, m9\n pmaddubsw m0, m4, m10\n vbroadcasti128 m2, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*2]\n paddw m12, m14\n paddw m13, m15\n paddw m12, m0\n vmovdqa64 m5{k1}, m2\n vmovdqa64 m2{k1}, m6\n mova m0, m4\n shufpd m1, m5, 0xcc ; 6a_8a 6b_8b 7a_9a 7b_9b\n shufpd m3, m2, 0xcc ; 7a_9a 7b_9b 8a_Aa 8b_Ab\n punpcklbw m2, m1, m3 ; 67a 67b 78a 78b\n punpckhbw m4, m1, m3 ; 89a 89b 9Aa 9Ab\n pmaddubsw m14, m2, m10\n pmaddubsw m15, m2, m11\n paddw m13, m14\n paddw m12, m15\n pmaddubsw m14, m4, m11\n paddw m13, m14\n pmulhrsw m12, m7\n pmulhrsw m13, m7\n mova [tmpq+ 0], m12\n mova [tmpq+64], m13\n add tmpq, 64*2\n sub hd, 4\n jg .v_w16_loop\n%else\n lea r6d, [wq-16]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 4\n mov r6b, hb\n.v_w16_loop0:\n vbroadcasti128 m4, [srcq+strideq*0]\n vbroadcasti128 m5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m0, [srcq+strideq*1]\n vbroadcasti128 m6, [srcq+strideq*0]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m1, [srcq+strideq*0]\n vbroadcasti128 m2, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m3, [srcq+strideq*0]\n shufpd m4, m4, m0, 0x0c\n shufpd m5, m5, m1, 0x0c\n punpcklbw m1, m4, m5 ; 01\n punpckhbw m4, m5 ; 34\n shufpd m6, m6, m2, 0x0c\n punpcklbw m2, m5, m6 ; 12\n punpckhbw m5, m6 ; 45\n shufpd m0, m0, m3, 0x0c\n punpcklbw m3, m6, m0 ; 23\n punpckhbw m6, m0 ; 56\n.v_w16_loop:\n vbroadcasti128 m12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vbroadcasti128 m13, [srcq+strideq*0]\n pmaddubsw m14, m1, m8 ; a0\n pmaddubsw m15, m2, m8 ; b0\n mova m1, m3\n mova m2, m4\n pmaddubsw m3, m9 ; a1\n pmaddubsw m4, m9 ; b1\n paddw m14, m3\n paddw m15, m4\n mova m3, m5\n mova m4, m6\n pmaddubsw m5, m10 ; a2\n pmaddubsw m6, m10 ; b2\n paddw m14, m5\n paddw m15, m6\n shufpd m6, m0, m12, 0x0d\n shufpd m0, m12, m13, 0x0c\n punpcklbw m5, m6, m0 ; 67\n punpckhbw m6, m0 ; 78\n pmaddubsw m12, m5, m11 ; a3\n pmaddubsw m13, m6, m11 ; b3\n paddw m14, m12\n paddw m15, m13\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova [tmpq+wq*0], m14\n mova [tmpq+wq*2], m15\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_w16_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_w16_loop0\n%endif\n RET\n%if cpuflag(avx512)\n.v_w32:\n mova m18, [bilin_v_perm64]\n movu ym0, [srcq+strideq*0]\n movu ym1, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n movu ym3, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym4, [srcq+strideq*0]\n movu ym5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym6, [srcq+strideq*0]\n vpermq m0, m18, m0\n vpermq m1, m18, m1\n vpermq m2, m18, m2\n vpermq m3, m18, m3\n vpermq m4, m18, m4\n vpermq m5, m18, m5\n vpermq m6, m18, m6\n punpcklbw m0, m1\n punpcklbw m1, m2\n punpcklbw m2, m3\n punpcklbw m3, m4\n punpcklbw m4, m5\n punpcklbw m5, m6\n.v_w32_loop:\n movu ym12, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu ym13, [srcq+strideq*0]\n pmaddubsw m14, m0, m8\n pmaddubsw m16, m2, m9\n pmaddubsw m15, m1, m8\n pmaddubsw m17, m3, m9\n mova m0, m2\n mova m1, m3\n vpermq m12, m18, m12\n vpermq m13, m18, m13\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m4, m10\n pmaddubsw m17, m5, m10\n punpcklbw m6, m12\n punpcklbw m12, m13\n mova m2, m4\n mova m3, m5\n paddw m14, m16\n paddw m15, m17\n pmaddubsw m16, m6, m11\n pmaddubsw m17, m12, m11\n mova m4, m6\n mova m5, m12\n paddw m14, m16\n paddw m15, m17\n pmulhrsw m14, m7\n pmulhrsw m15, m7\n mova m6, m13\n mova [tmpq+ 0], m14\n mova [tmpq+64], m15\n add tmpq, 64*2\n sub hd, 2\n jg .v_w32_loop\n vzeroupper\n RET\n.v_w64:\n mov r6d, hd\n mov wd, 64\n jmp .v_start\n.v_w128:\n lea r6d, [(1<<8)+hq]\n mov wd, 128\n.v_start:\n WIN64_SPILL_XMM 27\n mova m26, [bilin_v_perm64]\n mov r5, tmpq\n mov r7, srcq\n.v_loop0:\n vpermq m0, m26, [srcq+strideq*0]\n vpermq m1, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m2, m26, [srcq+strideq*0]\n vpermq m3, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m4, m26, [srcq+strideq*0]\n vpermq m5, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m6, m26, [srcq+strideq*0]\n punpckhbw m12, m0, m1\n punpcklbw m0, m1\n punpckhbw m13, m1, m2\n punpcklbw m1, m2\n punpckhbw m14, m2, m3\n punpcklbw m2, m3\n punpckhbw m15, m3, m4\n punpcklbw m3, m4\n punpckhbw m16, m4, m5\n punpcklbw m4, m5\n punpckhbw m17, m5, m6\n punpcklbw m5, m6\n.v_loop:\n vpermq m18, m26, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpermq m19, m26, [srcq+strideq*0]\n pmaddubsw m20, m0, m8\n pmaddubsw m21, m12, m8\n pmaddubsw m22, m1, m8\n pmaddubsw m23, m13, m8\n mova m0, m2\n mova m12, m14\n mova m1, m3\n mova m13, m15\n pmaddubsw m2, m9\n pmaddubsw m14, m9\n pmaddubsw m3, m9\n pmaddubsw m15, m9\n punpckhbw m24, m6, m18\n punpcklbw m6, m18\n paddw m20, m2\n paddw m21, m14\n paddw m22, m3\n paddw m23, m15\n mova m2, m4\n mova m14, m16\n mova m3, m5\n mova m15, m17\n pmaddubsw m4, m10\n pmaddubsw m16, m10\n pmaddubsw m5, m10\n pmaddubsw m17, m10\n punpckhbw m25, m18, m19\n punpcklbw m18, m19\n paddw m20, m4\n paddw m21, m16\n paddw m22, m5\n paddw m23, m17\n mova m4, m6\n mova m16, m24\n mova m5, m18\n mova m17, m25\n pmaddubsw m6, m11\n pmaddubsw m24, m11\n pmaddubsw m18, m11\n pmaddubsw m25, m11\n paddw m20, m6\n paddw m21, m24\n paddw m22, m18\n paddw m23, m25\n pmulhrsw m20, m7\n pmulhrsw m21, m7\n pmulhrsw m22, m7\n pmulhrsw m23, m7\n mova m6, m19\n mova [tmpq+wq*0+ 0], m20\n mova [tmpq+wq*0+64], m21\n mova [tmpq+wq*2+ 0], m22\n mova [tmpq+wq*2+64], m23\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .v_loop\n movzx hd, r6b\n add r5, 64*2\n add r7, 64\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .v_loop0\n%endif\n RET\n.hv:\n %assign stack_offset stack_offset - stack_size_padded\n %assign stack_size_padded 0\n WIN64_SPILL_XMM 16\n cmp wd, 4\n je .hv_w4\n shr mxd, 16\n sub srcq, 3\n vpbroadcastd m10, [r7+mxq*8+subpel_filters-prep%+SUFFIX+0]\n vpbroadcastd m11, [r7+mxq*8+subpel_filters-prep%+SUFFIX+4]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n%if cpuflag(avx512)\n tzcnt wd, wd\n vpbroadcastd m8, [pd_2]\n movzx wd, word [r7+wq*2+table_offset(prep, _8tap_hv)]\n vpbroadcastd m9, [pd_32]\n add wq, r7\n%endif\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512)\n jmp wq\n%else\n jmp .hv_w8\n%endif\n.hv_w4:\n movzx mxd, mxb\n dec srcq\n vpbroadcastd m8, [r7+mxq*8+subpel_filters-prep%+SUFFIX+2]\n movzx mxd, myb\n shr myd, 16\n cmp hd, 4\n cmove myd, mxd\n vpbroadcastq m0, [r7+myq*8+subpel_filters-prep%+SUFFIX]\n lea stride3q, [strideq*3]\n sub srcq, stride3q\n%if cpuflag(avx512)\n mov r3d, 0x04\n kmovb k1, r3d\n kshiftlb k2, k1, 2\n kshiftlb k3, k1, 4\n vpbroadcastd m10, [pd_2]\n vbroadcasti128 m16, [subpel_h_shufA]\n%else\n mova m7, [subpel_h_shuf4]\n pmovzxbd m9, [deint_shuf4]\n vpbroadcastd m10, [pw_8192]\n%endif\n punpcklbw m0, m0\n psraw m0, 8 ; sign-extend\n vpbroadcastd m11, [pd_32]\n pshufd m12, m0, q0000\n pshufd m13, m0, q1111\n pshufd m14, m0, q2222\n pshufd m15, m0, q3333\n%if cpuflag(avx512icl)\n movq xm3, [srcq+strideq*0]\n vpbroadcastq ym2, [srcq+strideq*1]\n vpbroadcastq ym3{k1}, [srcq+strideq*2]\n vpbroadcastq m2{k2}, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3{k2}, [srcq+strideq*0]\n vpbroadcastq m2{k3}, [srcq+strideq*1]\n vpbroadcastq m3{k3}, [srcq+strideq*2]\n mova m17, [spel_hv_perm4a]\n movu m18, [spel_hv_perm4b]\n mova m0, m10\n mova m1, m10\n pshufb m2, m16\n pshufb m3, m16\n vpdpbusd m0, m2, m8\n vpdpbusd m1, m3, m8\n packssdw m0, m1 ; _ 0 1 2 3 4 5 6\n psraw m0, 2\n vpermb m1, m17, m0 ; 01 12 23 34\n vpermb m2, m18, m0 ; 23 34 45 56\n.hv_w4_loop:\n movq xm3, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n movq xm4, [srcq+strideq*0]\n vpbroadcastq ym3{k1}, [srcq+strideq*1]\n vpbroadcastq ym4{k1}, [srcq+strideq*2]\n mova ym5, ym10\n mova ym6, ym10\n pshufb ym3, ym16\n pshufb ym4, ym16\n vpdpbusd ym5, ym3, ym8\n vpdpbusd ym6, ym4, ym8\n mova m7, m11\n packssdw ym5, ym6 ; 7 8 9 a _ _ _ _\n psraw ym5, 2\n valignq m0, m5, m0, 4 ; _ 4 5 6 7 8 9 a\n vpdpwssd m7, m1, m12\n vpdpwssd m7, m2, m13\n vpermb m1, m17, m0 ; 45 56 67 78\n vpermb m2, m18, m0 ; 67 78 89 9a\n vpdpwssd m7, m1, m14\n vpdpwssd m7, m2, m15\n psrad m7, 6\n vpmovdw [tmpq], m7\n%else\n vpbroadcastq m2, [srcq+strideq*0]\n vpbroadcastq m4, [srcq+strideq*1]\n vpbroadcastq m0, [srcq+strideq*2]\n vpbroadcastq m5, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m3, [srcq+strideq*0]\n vpbroadcastq m6, [srcq+strideq*1]\n vpbroadcastq m1, [srcq+strideq*2]\n vpblendd m2, m2, m4, 0xcc ; 0 1\n vpblendd m0, m0, m5, 0xcc ; 2 3\n vpblendd m3, m3, m6, 0xcc ; 4 5\n pshufb m2, m7 ; 00 01 10 11 02 03 12 13\n pshufb m0, m7 ; 20 21 30 31 22 23 32 33\n pshufb m3, m7 ; 40 41 50 51 42 43 52 53\n pshufb m1, m7 ; 60 61 60 61 62 63 62 63\n pmaddubsw m2, m8\n pmaddubsw m0, m8\n pmaddubsw m3, m8\n pmaddubsw m1, m8\n phaddw m2, m0 ; 0a 1a 2a 3a 0b 1b 2b 3b\n phaddw m3, m1 ; 4a 5a 6a __ 4b 5b 6b __\n pmulhrsw m2, m10\n pmulhrsw m3, m10\n palignr m4, m3, m2, 4 ; 1a 2a 3a 4a 1b 2b 3b 4b\n punpcklwd m1, m2, m4 ; 01 12\n punpckhwd m2, m4 ; 23 34\n pshufd m0, m3, q2121\n punpcklwd m3, m0 ; 45 56\n.hv_w4_loop:\n pmaddwd m5, m1, m12 ; a0 b0\n pmaddwd m6, m2, m12 ; c0 d0\n pmaddwd m2, m13 ; a1 b1\n pmaddwd m4, m3, m13 ; c1 d1\n mova m1, m3\n pmaddwd m3, m14 ; a2 b2\n paddd m5, m2\n vpbroadcastq m2, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n paddd m6, m4\n paddd m5, m3\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m3, [srcq+strideq*1]\n vpblendd m2, m2, m4, 0xcc\n vpbroadcastq m4, [srcq+strideq*2]\n vpblendd m3, m3, m4, 0xcc\n pshufb m2, m7\n pshufb m3, m7\n pmaddubsw m2, m8\n pmaddubsw m3, m8\n phaddw m2, m3\n pmulhrsw m2, m10\n palignr m3, m2, m0, 12\n mova m0, m2\n punpcklwd m2, m3, m0 ; 67 78\n punpckhwd m3, m0 ; 89 9a\n pmaddwd m4, m2, m14 ; c2 d2\n paddd m6, m11\n paddd m5, m11\n paddd m6, m4\n pmaddwd m4, m2, m15 ; a3 b3\n paddd m5, m4\n pmaddwd m4, m3, m15 ; c3 d3\n paddd m6, m4\n psrad m5, 6\n psrad m6, 6\n packssdw m5, m6\n vpermd m5, m9, m5\n mova [tmpq], m5\n%endif\n add tmpq, 32\n sub hd, 4\n jg .hv_w4_loop\n%if cpuflag(avx512)\n vzeroupper\n%endif\n RET\n.hv_w8:\n%if cpuflag(avx512icl)\n WIN64_SPILL_XMM 24\n vbroadcasti128 m16, [subpel_h_shufA]\n vbroadcasti128 m17, [subpel_h_shufB]\n vbroadcasti128 m18, [subpel_h_shufC]\n vinserti128 ym0, [srcq+strideq*0], 1\n vinserti128 m0, [srcq+strideq*1], 2\n vinserti128 m0, [srcq+strideq*2], 3\n movu xm1, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym1, [srcq+strideq*0], 1\n vinserti128 m1, [srcq+strideq*1], 2\n vinserti128 m1, [srcq+strideq*2], 3\n mova m2, m8\n mova m4, m8\n mova m3, m8\n mova m5, m8\n pshufb m20, m0, m16\n pshufb m21, m0, m17\n pshufb m22, m0, m18\n pshufb m23, m1, m16\n pshufb m6, m1, m17\n pshufb m7, m1, m18\n vpdpbusd m2, m20, m10\n vpdpbusd m4, m21, m10\n vpdpbusd m2, m21, m11\n vpdpbusd m4, m22, m11\n vpdpbusd m3, m23, m10\n vpdpbusd m5, m6, m10\n vpdpbusd m3, m6, m11\n vpdpbusd m5, m7, m11\n packssdw m2, m4\n packssdw m3, m5\n psraw m2, 2 ; _ 0 1 2\n psraw m3, 2 ; 3 4 5 6\n valignq m0, m3, m2, 2 ; 0 1 2 3\n valignq m1, m3, m2, 4 ; 1 2 3 4\n valignq m2, m3, m2, 6 ; 2 3 4 5\n punpcklwd m4, m0, m1 ; 01a 12a 23a 34a\n punpckhwd m5, m0, m1 ; 01b 12b 23b 34b\n punpcklwd m6, m2, m3 ; 23a 34a 45a 56a\n punpckhwd m7, m2, m3 ; 23b 34b 45b 56b\n.hv_w8_loop:\n movu xm19, [srcq+stride3q ]\n lea srcq, [srcq+strideq*4]\n vinserti128 ym19, [srcq+strideq*0], 1\n vinserti128 m19, [srcq+strideq*1], 2\n vinserti128 m19, [srcq+strideq*2], 3\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m4, m12\n vpdpwssd m21, m5, m12\n vpdpwssd m20, m6, m13\n vpdpwssd m21, m7, m13\n pshufb m0, m19, m16\n pshufb m1, m19, m17\n pshufb m2, m19, m18\n vpdpbusd m22, m0, m10\n vpdpbusd m23, m1, m10\n vpdpbusd m22, m1, m11\n vpdpbusd m23, m2, m11\n packssdw m22, m23\n psraw m22, 2 ; 7 8 9 A\n valignq m0, m22, m3, 2 ; 4 5 6 7\n valignq m1, m22, m3, 4 ; 5 6 7 8\n valignq m2, m22, m3, 6 ; 6 7 8 9\n mova m3, m22\n punpcklwd m4, m0, m1 ; 45a 56a 67a 78a\n punpckhwd m5, m0, m1 ; 45b 56b 67b 78b\n punpcklwd m6, m2, m3 ; 67a 78a 89a 9Aa\n punpckhwd m7, m2, m3 ; 67b 78b 89b 9Ab\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq], m20\n add tmpq, 64\n sub hd, 4\n jg .hv_w8_loop\n%else\n lea r6d, [wq-8]\n mov r5, tmpq\n mov r7, srcq\n shl r6d, 5\n mov r6b, hb\n.hv_w8_loop0:\n vbroadcasti128 m7, [subpel_h_shufA]\n vbroadcasti128 m8, [subpel_h_shufB]\n vbroadcasti128 m9, [subpel_h_shufC]\n movu xm4, [srcq+strideq*0]\n movu xm5, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n movu xm6, [srcq+strideq*0]\n vbroadcasti128 m0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vpblendd m4, m4, m0, 0xf0 ; 0 3\n vinserti128 m5, m5, [srcq+strideq*0], 1 ; 1 4\n vinserti128 m6, m6, [srcq+strideq*1], 1 ; 2 5\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 3 6\n HV_H_W8 m4, m1, m2, m3, m7, m8, m9\n HV_H_W8 m5, m1, m2, m3, m7, m8, m9\n HV_H_W8 m6, m1, m2, m3, m7, m8, m9\n HV_H_W8 m0, m1, m2, m3, m7, m8, m9\n vpbroadcastd m7, [pw_8192]\n vpermq m4, m4, q3120\n vpermq m5, m5, q3120\n vpermq m6, m6, q3120\n pmulhrsw m0, m7\n pmulhrsw m4, m7\n pmulhrsw m5, m7\n pmulhrsw m6, m7\n vpermq m7, m0, q3120\n punpcklwd m1, m4, m5 ; 01\n punpckhwd m4, m5 ; 34\n punpcklwd m2, m5, m6 ; 12\n punpckhwd m5, m6 ; 45\n punpcklwd m3, m6, m7 ; 23\n punpckhwd m6, m7 ; 56\n.hv_w8_loop:\n vextracti128 [tmpq], m0, 1 ; not enough registers\n movu xm0, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti128 m0, m0, [srcq+strideq*0], 1 ; 7 8\n pmaddwd m8, m1, m12 ; a0\n pmaddwd m9, m2, m12 ; b0\n mova m1, m3\n mova m2, m4\n pmaddwd m3, m13 ; a1\n pmaddwd m4, m13 ; b1\n paddd m8, m3\n paddd m9, m4\n mova m3, m5\n mova m4, m6\n pmaddwd m5, m14 ; a2\n pmaddwd m6, m14 ; b2\n paddd m8, m5\n paddd m9, m6\n vbroadcasti128 m6, [subpel_h_shufB]\n vbroadcasti128 m7, [subpel_h_shufC]\n vbroadcasti128 m5, [subpel_h_shufA]\n HV_H_W8 m0, m5, m6, m7, m5, m6, m7\n vpbroadcastd m5, [pw_8192]\n vpbroadcastd m7, [pd_32]\n vbroadcasti128 m6, [tmpq]\n pmulhrsw m0, m5\n paddd m8, m7\n paddd m9, m7\n vpermq m7, m0, q3120 ; 7 8\n shufpd m6, m6, m7, 0x04 ; 6 7\n punpcklwd m5, m6, m7 ; 67\n punpckhwd m6, m7 ; 78\n pmaddwd m7, m5, m15 ; a3\n paddd m8, m7\n pmaddwd m7, m6, m15 ; b3\n paddd m7, m9\n psrad m8, 6\n psrad m7, 6\n packssdw m8, m7\n vpermq m7, m8, q3120\n mova [tmpq+wq*0], xm7\n vextracti128 [tmpq+wq*2], m7, 1\n lea tmpq, [tmpq+wq*4]\n sub hd, 2\n jg .hv_w8_loop\n movzx hd, r6b\n add r5, 16\n add r7, 8\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_w8_loop0\n%endif\n RET\n%if cpuflag(avx512icl)\n.hv_w16:\n mov wd, 16*2\n jmp .hv_start\n.hv_w32:\n mov wd, 32*2\n jmp .hv_start\n.hv_w64:\n mov wd, 64*2\n jmp .hv_start\n.hv_w128:\n mov wd, 128*2\n.hv_start:\n WIN64_SPILL_XMM 31\n mova m16, [spel_h_perm16a]\n mova m17, [spel_h_perm16b]\n mova m18, [spel_h_perm16c]\n lea r6d, [wq*8-16*2*8+hq]\n mov r5, tmpq\n mov r7, srcq\n.hv_loop0:\n movu ym0, [srcq+strideq*0]\n vinserti32x8 m0, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym1, [srcq+strideq*0]\n vinserti32x8 m1, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym2, [srcq+strideq*0]\n vinserti32x8 m2, [srcq+strideq*1], 1\n lea srcq, [srcq+strideq*2]\n movu ym3, [srcq+strideq*0]\n mova m4, m8\n mova m5, m8\n mova m6, m8\n mova m7, m8\n vpermb m19, m16, m0\n vpermb m20, m17, m0\n vpermb m21, m18, m0\n vpermb m22, m16, m1\n vpermb m23, m17, m1\n vpermb m24, m18, m1\n vpermb m25, m16, m2\n vpermb m26, m17, m2\n vpermb m27, m18, m2\n vpermb ym28, ym16, ym3\n vpermb ym29, ym17, ym3\n vpermb ym30, ym18, ym3\n mova m0, m8\n mova m1, m8\n mova ym2, ym8\n mova ym3, ym8\n vpdpbusd m4, m19, m10\n vpdpbusd m5, m20, m10\n vpdpbusd m6, m22, m10\n vpdpbusd m7, m23, m10\n vpdpbusd m0, m25, m10\n vpdpbusd m1, m26, m10\n vpdpbusd ym2, ym28, ym10\n vpdpbusd ym3, ym29, ym10\n vpdpbusd m4, m20, m11\n vpdpbusd m5, m21, m11\n vpdpbusd m6, m23, m11\n vpdpbusd m7, m24, m11\n vpdpbusd m0, m26, m11\n vpdpbusd m1, m27, m11\n vpdpbusd ym2, ym29, ym11\n vpdpbusd ym3, ym30, ym11\n packssdw m4, m5\n packssdw m6, m7\n packssdw m0, m1\n packssdw ym2, ym3\n psraw m4, 2 ; 0a 0b 1a 1b\n psraw m6, 2 ; 2a 2b 3a 3b\n psraw m0, 2 ; 4a 4b 5a 5b\n psraw ym2, 2 ; 6a 6b __ __\n vshufi32x4 m5, m4, m6, q1032 ; 1a 1b 2a 2b\n vshufi32x4 m7, m6, m0, q1032 ; 3a 3b 4a 4b\n vshufi32x4 m1, m0, m2, q1032 ; 5a 5b 6a 6b\n punpcklwd m2, m4, m5 ; 01a 01c 12a 12c\n punpckhwd m3, m4, m5 ; 01b 01d 12b 12d\n punpcklwd m4, m6, m7 ; 23a 23c 34a 34c\n punpckhwd m5, m6, m7 ; 23b 23d 34b 34d\n punpcklwd m6, m0, m1 ; 45a 45c 56a 56c\n punpckhwd m7, m0, m1 ; 45b 45d 56b 56d\n.hv_loop:\n movu ym19, [srcq+strideq*1]\n lea srcq, [srcq+strideq*2]\n vinserti32x8 m19, [srcq+strideq*0], 1\n mova m20, m9\n mova m21, m9\n mova m22, m8\n mova m23, m8\n vpdpwssd m20, m2, m12\n vpdpwssd m21, m3, m12\n vpdpwssd m20, m4, m13\n vpdpwssd m21, m5, m13\n vpermb m24, m16, m19\n vpermb m25, m17, m19\n vpermb m26, m18, m19\n vpdpbusd m22, m24, m10\n vpdpbusd m23, m25, m10\n vpdpbusd m22, m25, m11\n vpdpbusd m23, m26, m11\n packssdw m22, m23\n psraw m22, 2 ; 7a 7b 8a 8b\n vshufi32x4 m0, m1, m22, q1032 ; 6a 6b 7a 7b\n mova m2, m4\n mova m3, m5\n mova m1, m22\n mova m4, m6\n mova m5, m7\n punpcklwd m6, m0, m1 ; 67a 67c 78a 78c\n punpckhwd m7, m0, m1 ; 67b 67d 78b 78d\n vpdpwssd m20, m4, m14\n vpdpwssd m21, m5, m14\n vpdpwssd m20, m6, m15\n vpdpwssd m21, m7, m15\n psrad m20, 6\n psrad m21, 6\n packssdw m20, m21\n mova [tmpq+wq*0], ym20\n vextracti32x8 [tmpq+wq*1], m20, 1\n lea tmpq, [tmpq+wq*2]\n sub hd, 2\n jg .hv_loop\n movzx hd, r6b\n add r5, 32\n add r7, 16\n mov tmpq, r5\n mov srcq, r7\n sub r6d, 1<<8\n jg .hv_loop0\n%endif\n RET\n%endmacro\n\n%macro WARP_V 5 ; dst, 02, 46, 13, 57\n ; Can be done using gathers, but that's terribly slow on many CPU:s\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm8, [filterq+myq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1 ; a e\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+deltaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; b f\n lea tmp1d, [myq+deltaq*4]\n lea tmp2d, [myq+deltaq*1]\n shr myd, 10\n shr tmp1d, 10\n movq xm9, [filterq+myq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1 ; c g\n lea tmp1d, [tmp2q+deltaq*4]\n lea myd, [tmp2q+gammaq] ; my += gamma\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklwd m8, m0\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1 ; d h\n punpcklwd m0, m9, m0\n punpckldq m9, m8, m0\n punpckhdq m0, m8, m0\n punpcklbw m8, m11, m9 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8\n punpckhbw m9, m11, m9 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8\n pmaddwd m%2, m8\n pmaddwd m9, m%3\n punpcklbw m8, m11, m0 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8\n punpckhbw m0, m11, m0 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8\n pmaddwd m8, m%4\n pmaddwd m0, m%5\n paddd m%2, m9\n paddd m0, m8\n paddd m%1, m0, m%2\n%endmacro\n\ncglobal warp_affine_8x8t, 0, 14, 0, tmp, ts\n%if WIN64\n sub rsp, 0xa0\n%endif\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main\n.loop:\n psrad m7, 13\n psrad m0, 13\n packssdw m7, m0\n pmulhrsw m7, m14 ; (x + (1 << 6)) >> 7\n vpermq m7, m7, q3120\n mova [tmpq+tsq*0], xm7\n vextracti128 [tmpq+tsq*2], m7, 1\n dec r4d\n jz mangle(private_prefix %+ _warp_affine_8x8_avx2).end\n call mangle(private_prefix %+ _warp_affine_8x8_avx2).main2\n lea tmpq, [tmpq+tsq*4]\n jmp .loop\n\ncglobal warp_affine_8x8, 0, 14, 0, dst, ds, src, ss, abcd, mx, tmp2, alpha, \\\n beta, filter, tmp1, delta, my, gamma\n%if WIN64\n sub rsp, 0xa0\n %assign xmm_regs_used 16\n %assign stack_size_padded 0xa0\n %assign stack_offset stack_offset+stack_size_padded\n%endif\n call .main\n jmp .start\n.loop:\n call .main2\n lea dstq, [dstq+dsq*2]\n.start:\n psrad m7, 18\n psrad m0, 18\n packusdw m7, m0\n pavgw m7, m11 ; (x + (1 << 10)) >> 11\n vextracti128 xm0, m7, 1\n packuswb xm7, xm0\n pshufd xm7, xm7, q3120\n movq [dstq+dsq*0], xm7\n movhps [dstq+dsq*1], xm7\n dec r4d\n jg .loop\n.end:\n RET\nALIGN function_align\n.main:\n ; Stack args offset by one (r4m -> r5m etc.) due to call\n%if WIN64\n mov abcdq, r5m\n mov mxd, r6m\n movaps [rsp+stack_offset+0x10], xmm6\n movaps [rsp+stack_offset+0x20], xmm7\n movaps [rsp+0x28], xmm8\n movaps [rsp+0x38], xmm9\n movaps [rsp+0x48], xmm10\n movaps [rsp+0x58], xmm11\n movaps [rsp+0x68], xmm12\n movaps [rsp+0x78], xmm13\n movaps [rsp+0x88], xmm14\n movaps [rsp+0x98], xmm15\n%endif\n movsx alphad, word [abcdq+2*0]\n movsx betad, word [abcdq+2*1]\n mova m12, [warp_8x8_shufA]\n mova m13, [warp_8x8_shufB]\n vpbroadcastd m14, [pw_8192]\n vpbroadcastd m15, [pd_32768]\n pxor m11, m11\n lea filterq, [mc_warp_filter]\n lea tmp1q, [ssq*3+3]\n add mxd, 512+(64<<10)\n lea tmp2d, [alphaq*3]\n sub srcq, tmp1q ; src -= src_stride*3 + 3\n sub betad, tmp2d ; beta -= alpha*3\n mov myd, r7m\n call .h\n psrld m1, m0, 16\n call .h\n psrld m4, m0, 16\n call .h\n pblendw m1, m0, 0xaa ; 02\n call .h\n pblendw m4, m0, 0xaa ; 13\n call .h\n psrld m2, m1, 16\n pblendw m2, m0, 0xaa ; 24\n call .h\n psrld m5, m4, 16\n pblendw m5, m0, 0xaa ; 35\n call .h\n psrld m3, m2, 16\n pblendw m3, m0, 0xaa ; 46\n movsx deltad, word [abcdq+2*2]\n movsx gammad, word [abcdq+2*3]\n add myd, 512+(64<<10)\n mov r4d, 4\n lea tmp1d, [deltaq*3]\n sub gammad, tmp1d ; gamma -= delta*3\n.main2:\n call .h\n psrld m6, m5, 16\n pblendw m6, m0, 0xaa ; 57\n WARP_V 7, 1, 3, 4, 6\n call .h\n mova m1, m2\n mova m2, m3\n psrld m3, 16\n pblendw m3, m0, 0xaa ; 68\n WARP_V 0, 4, 6, 1, 3\n mova m4, m5\n mova m5, m6\n ret\nALIGN function_align\n.h:\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n vbroadcasti128 m10, [srcq]\n shr mxd, 10\n shr tmp1d, 10\n movq xm8, [filterq+mxq *8]\n vinserti128 m8, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+alphaq*1]\n shr tmp2d, 10\n shr tmp1d, 10\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n lea tmp1d, [mxq+alphaq*4]\n lea tmp2d, [mxq+alphaq*1]\n shr mxd, 10\n shr tmp1d, 10\n movq xm9, [filterq+mxq *8]\n vinserti128 m9, [filterq+tmp1q*8], 1\n lea tmp1d, [tmp2q+alphaq*4]\n lea mxd, [tmp2q+betaq] ; mx += beta\n shr tmp2d, 10\n shr tmp1d, 10\n punpcklqdq m8, m0 ; 0 1 4 5\n movq xm0, [filterq+tmp2q*8]\n vinserti128 m0, [filterq+tmp1q*8], 1\n punpcklqdq m9, m0 ; 2 3 6 7\n pshufb m0, m10, m12\n pmaddubsw m0, m8\n pshufb m10, m13\n pmaddubsw m10, m9\n add srcq, ssq\n phaddw m0, m10\n pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13\n paddd m0, m15 ; rounded 14-bit result in upper 16 bits of dword\n ret\n\n%macro BIDIR_FN 1 ; op\n %1 0\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 4\n je .ret\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n cmp hd, 8\n je .ret\n %1 2\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n.ret:\n RET\n.w8_loop:\n %1_INC_PTR 2\n %1 0\n lea dstq, [dstq+strideq*4]\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*4]\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n %1_INC_PTR 4\n %1 0\n lea dstq, [dstq+strideq*2]\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+strideq*1], m0\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n %1_INC_PTR 4\n %1 0\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n %1 0\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n %1 2\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n %1_INC_PTR 8\n %1 -4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n %1 -2\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n dec hd\n jg .w128_loop\n RET\n%endmacro\n\n%macro AVG 1 ; src_offset\n mova m0, [tmp1q+(%1+0)*mmsize]\n paddw m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n paddw m1, [tmp2q+(%1+1)*mmsize]\n pmulhrsw m0, m2\n pmulhrsw m1, m2\n packuswb m0, m1\n%endmacro\n\n%macro AVG_INC_PTR 1\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m2, [pw_1024+r6-avg_avx2_table]\n add wq, r6\n BIDIR_FN AVG\n\n%macro W_AVG 1 ; src_offset\n ; (a * weight + b * (16 - weight) + 128) >> 8\n ; = ((a - b) * weight + (b << 4) + 128) >> 8\n ; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4\n ; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4\n mova m0, [tmp1q+(%1+0)*mmsize]\n psubw m2, m0, [tmp2q+(%1+0)*mmsize]\n mova m1, [tmp1q+(%1+1)*mmsize]\n psubw m3, m1, [tmp2q+(%1+1)*mmsize]\n pmulhw m2, m4\n pmulhw m3, m4\n paddw m0, m2\n paddw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%define W_AVG_INC_PTR AVG_INC_PTR\n\ncglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3\n lea r6, [w_avg_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n vpbroadcastw m4, r6m ; weight\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m5, [pw_2048+r6-w_avg_avx2_table]\n psllw m4, 12 ; (weight-16) << 12 when interpreted as signed\n add wq, r6\n cmp dword r6m, 7\n jg .weight_gt7\n mov r6, tmp1q\n pxor m0, m0\n mov tmp1q, tmp2q\n psubw m4, m0, m4 ; -weight\n mov tmp2q, r6\n.weight_gt7:\n BIDIR_FN W_AVG\n\n%macro MASK 1 ; src_offset\n ; (a * m + b * (64 - m) + 512) >> 10\n ; = ((a - b) * m + (b << 6) + 512) >> 10\n ; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4\n vpermq m3, [maskq+(%1+0)*(mmsize/2)], q3120\n mova m0, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0, [tmp1q+(%1+0)*mmsize]\n psubb m3, m4, m3\n paddw m1, m1 ; (b - a) << 1\n paddb m3, m3\n punpcklbw m2, m4, m3 ; -m << 9\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1, [tmp1q+(%1+1)*mmsize]\n paddw m2, m2\n punpckhbw m3, m4, m3\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n%endmacro\n\n%macro MASK_INC_PTR 1\n add maskq, %1*mmsize/2\n add tmp1q, %1*mmsize\n add tmp2q, %1*mmsize\n%endmacro\n\ncglobal mask, 4, 8, 6, dst, stride, tmp1, tmp2, w, h, mask, stride3\n lea r7, [mask_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n pxor m4, m4\n vpbroadcastd m5, [pw_2048+r7-mask_avx2_table]\n add wq, r7\n BIDIR_FN MASK\n\n%macro W_MASK 2-3 0 ; src_offset, mask_out, 4:4:4\n mova m0, [tmp1q+(%1+0)*mmsize]\n mova m1, [tmp2q+(%1+0)*mmsize]\n psubw m1, m0\n pabsw m%2, m1\n psubusw m%2, m6, m%2\n psrlw m%2, 8 ; 64 - m\n psllw m2, m%2, 10\n pmulhw m1, m2\n paddw m0, m1\n mova m1, [tmp1q+(%1+1)*mmsize]\n mova m2, [tmp2q+(%1+1)*mmsize]\n psubw m2, m1\n pabsw m3, m2\n psubusw m3, m6, m3\n psrlw m3, 8\n%if %3\n packuswb m%2, m3\n psubb m%2, m5, m%2\n vpermq m%2, m%2, q3120\n%else\n phaddw m%2, m3\n%endif\n psllw m3, 10\n pmulhw m2, m3\n paddw m1, m2\n pmulhrsw m0, m7\n pmulhrsw m1, m7\n packuswb m0, m1\n%endmacro\n\ncglobal w_mask_420, 4, 8, 14, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_420_avx2_table\n lea r7, [w_mask_420_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n movd xm8, [base+pw_258] ; 64 * 4 + 2\n pmovzxbd m9, [base+deint_shuf4]\n psubw xm8, xm0\n add wq, r7\n vpbroadcastw m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm0, m4, 1\n vpblendd xm1, xm4, xm0, 0x05\n vpblendd xm4, xm4, xm0, 0x0a\n pshufd xm1, xm1, q2301\n psubw xm4, xm8, xm4\n psubw xm4, xm1\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [maskq], xm4\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n phaddd m4, m5\n vextracti128 xm1, m0, 1\n psubw m4, m8, m4\n psrlw m4, 2\n vpermd m4, m9, m4\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n movd [dstq ], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq ], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], xm4\n RET\n.w8_loop:\n add tmp1q, 2*32\n add tmp2q, 2*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 8\n.w8:\n vextracti128 xm2, m4, 1\n vextracti128 xm1, m0, 1\n psubw xm4, xm8, xm4\n psubw xm4, xm2\n psrlw xm4, 2\n packuswb xm4, xm4\n movq [dstq ], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n movq [maskq], xm4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w16:\n vpermq m0, m0, q3120\n mova [dstq ], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n punpckhqdq m1, m4, m5\n punpcklqdq m4, m5\n psubw m1, m8, m1\n psubw m1, m4\n psrlw m1, 2\n vpermq m0, m0, q3120\n packuswb m1, m1\n vpermd m1, m9, m1\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], xm1\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 16\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n psubw m4, m8, m4\n psubw m4, m5\n psrlw m4, 2\n vpermq m0, m0, q3120\n packuswb m4, m4\n vpermd m4, m9, m4\n mova [dstq+strideq*1], m0\n mova [maskq], xm4\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n dec hd\n.w64_loop:\n add tmp1q, 4*32\n add tmp2q, 4*32\n W_MASK 0, 4\n add dstq, strideq\n.w64:\n vpermq m0, m0, q3120\n mova [dstq], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+32], m0\n test hd, 1\n jz .w64_loop_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n add maskq, 32\n dec hd\n jg .w64_loop\n RET\n.w128_loop_even:\n psubw m12, m8, m4\n psubw m13, m8, m5\n dec hd\n.w128_loop:\n W_MASK 0, 4\n add dstq, strideq\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+0*32], m0\n W_MASK 2, 5\n vpermq m0, m0, q3120\n mova [dstq+1*32], m0\n add tmp1q, 8*32\n add tmp2q, 8*32\n test hd, 1\n jz .w128_even\n psubw m4, m10, m4\n psubw m5, m11, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq], m4\n jmp .w128_odd\n.w128_even:\n psubw m10, m8, m4\n psubw m11, m8, m5\n.w128_odd:\n W_MASK -4, 4\n vpermq m0, m0, q3120\n mova [dstq+2*32], m0\n W_MASK -2, 5\n vpermq m0, m0, q3120\n mova [dstq+3*32], m0\n test hd, 1\n jz .w128_loop_even\n psubw m4, m12, m4\n psubw m5, m13, m5\n psrlw m4, 2\n psrlw m5, 2\n packuswb m4, m5\n vpermd m4, m9, m4\n mova [maskq+32], m4\n add maskq, 64\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_422, 4, 8, 11, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_422_avx2_table\n lea r7, [w_mask_422_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movd xm0, r7m ; sign\n pxor m9, m9\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n pmovzxbd m10, [base+deint_shuf4]\n add wq, r7\n psrlw xm8, xm7, 4 ; pw_128\n psubb xm8, xm0\n vpbroadcastb m8, xm8\n W_MASK 0, 4\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n jg .w4_h16\n.w4_end:\n vextracti128 xm5, m4, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n mova [maskq], xm5\n RET\n.w4_h16:\n W_MASK 2, 5\n lea dstq, [dstq+strideq*4]\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermd m5, m10, m5\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq], m5\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 16\n.w8:\n vextracti128 xm5, m4, 1\n vextracti128 xm1, m0, 1\n packuswb xm4, xm5\n psubb xm5, xm8, xm4\n pavgb xm5, xm9\n pshufd xm5, xm5, q3120\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], xm5\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*2], xm0\n vextracti128 [dstq+stride3q ], m0, 1\n mova [maskq], m5\n sub hd, 4\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+strideq*1], m0\n mova [maskq], m5\n sub hd, 2\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq], m5\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4\n add dstq, strideq\n add maskq, 32*2\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n W_MASK 2, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*1], m0\n mova [maskq+32*0], m5\n W_MASK 4, 4\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n W_MASK 6, 5\n packuswb m4, m5\n psubb m5, m8, m4\n pavgb m5, m9\n vpermq m0, m0, q3120\n vpermd m5, m10, m5\n mova [dstq+32*3], m0\n mova [maskq+32*1], m5\n dec hd\n jg .w128_loop\n RET\n\ncglobal w_mask_444, 4, 8, 8, dst, stride, tmp1, tmp2, w, h, mask, stride3\n%define base r7-w_mask_444_avx2_table\n lea r7, [w_mask_444_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n mov maskq, maskmp\n movsxd wq, dword [r7+wq*4]\n vpbroadcastd m6, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8\n vpbroadcastd m7, [base+pw_2048]\n vpbroadcastd m5, [base+pb_64]\n add wq, r7\n W_MASK 0, 4, 1\n lea stride3q, [strideq*3]\n jmp wq\n.w4:\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n mova [maskq+32*0], m4\n cmp hd, 8\n jl .w4_end\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n je .w4_end\n W_MASK 2, 4, 1\n lea dstq, [dstq+strideq*4]\n vextracti128 xm1, m0, 1\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n movd [dstq+strideq*2], xm1\n pextrd [dstq+stride3q ], xm1, 1\n lea dstq, [dstq+strideq*4]\n pextrd [dstq+strideq*0], xm0, 2\n pextrd [dstq+strideq*1], xm0, 3\n pextrd [dstq+strideq*2], xm1, 2\n pextrd [dstq+stride3q ], xm1, 3\n mova [maskq+32*1], m4\n.w4_end:\n RET\n.w8_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*4]\n add maskq, 32\n.w8:\n vextracti128 xm1, m0, 1\n movq [dstq+strideq*0], xm0\n movq [dstq+strideq*1], xm1\n movhps [dstq+strideq*2], xm0\n movhps [dstq+stride3q ], xm1\n mova [maskq], m4\n sub hd, 4\n jg .w8_loop\n RET\n.w16_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n lea dstq, [dstq+strideq*2]\n add maskq, 32\n.w16:\n vpermq m0, m0, q3120\n mova [dstq+strideq*0], xm0\n vextracti128 [dstq+strideq*1], m0, 1\n mova [maskq], m4\n sub hd, 2\n jg .w16_loop\n RET\n.w32_loop:\n add tmp1q, 32*2\n add tmp2q, 32*2\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32\n.w32:\n vpermq m0, m0, q3120\n mova [dstq], m0\n mova [maskq], m4\n dec hd\n jg .w32_loop\n RET\n.w64_loop:\n add tmp1q, 32*4\n add tmp2q, 32*4\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*2\n.w64:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n dec hd\n jg .w64_loop\n RET\n.w128_loop:\n add tmp1q, 32*8\n add tmp2q, 32*8\n W_MASK 0, 4, 1\n add dstq, strideq\n add maskq, 32*4\n.w128:\n vpermq m0, m0, q3120\n mova [dstq+32*0], m0\n mova [maskq+32*0], m4\n W_MASK 2, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*1], m0\n mova [maskq+32*1], m4\n W_MASK 4, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*2], m0\n mova [maskq+32*2], m4\n W_MASK 6, 4, 1\n vpermq m0, m0, q3120\n mova [dstq+32*3], m0\n mova [maskq+32*3], m4\n dec hd\n jg .w128_loop\n RET\n\ncglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask\n%define base r6-blend_avx2_table\n lea r6, [blend_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movifnidn maskq, maskmp\n movsxd wq, dword [r6+wq*4]\n vpbroadcastd m4, [base+pb_64]\n vpbroadcastd m5, [base+pw_512]\n add wq, r6\n lea r6, [dsq*3]\n jmp wq\n.w4:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n vpbroadcastd xm1, [dstq+dsq*2]\n pinsrd xm1, [dstq+r6 ], 3\n mova xm6, [maskq]\n psubb xm3, xm4, xm6\n punpcklbw xm2, xm3, xm6\n punpckhbw xm3, xm6\n mova xm6, [tmpq]\n add maskq, 4*4\n add tmpq, 4*4\n punpcklbw xm0, xm6\n punpckhbw xm1, xm6\n pmaddubsw xm0, xm2\n pmaddubsw xm1, xm3\n pmulhrsw xm0, xm5\n pmulhrsw xm1, xm5\n packuswb xm0, xm1\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n pextrd [dstq+dsq*2], xm0, 2\n pextrd [dstq+r6 ], xm0, 3\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w4\n RET\nALIGN function_align\n.w8:\n movq xm1, [dstq+dsq*0]\n movhps xm1, [dstq+dsq*1]\n vpbroadcastq m2, [dstq+dsq*2]\n vpbroadcastq m3, [dstq+r6 ]\n mova m0, [maskq]\n mova m6, [tmpq]\n add maskq, 8*4\n add tmpq, 8*4\n vpblendd m1, m2, 0x30\n vpblendd m1, m3, 0xc0\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n vextracti128 xm1, m0, 1\n movq [dstq+dsq*0], xm0\n movhps [dstq+dsq*1], xm0\n movq [dstq+dsq*2], xm1\n movhps [dstq+r6 ], xm1\n lea dstq, [dstq+dsq*4]\n sub hd, 4\n jg .w8\n RET\nALIGN function_align\n.w16:\n mova m0, [maskq]\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n mova m6, [tmpq]\n add maskq, 16*2\n add tmpq, 16*2\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16\n RET\nALIGN function_align\n.w32:\n mova m0, [maskq]\n mova m1, [dstq]\n mova m6, [tmpq]\n add maskq, 32\n add tmpq, 32\n psubb m3, m4, m0\n punpcklbw m2, m3, m0\n punpckhbw m3, m0\n punpcklbw m0, m1, m6\n punpckhbw m1, m6\n pmaddubsw m0, m2\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32\n RET\n\ncglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_v_avx2_table\n lea r5, [blend_v_avx2_table]\n tzcnt wd, wm\n movifnidn hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n add maskq, obmc_masks-blend_v_avx2_table\n jmp wq\n.w2:\n vpbroadcastd xm2, [maskq+2*2]\n.w2_s0_loop:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w2_s0_loop\n RET\nALIGN function_align\n.w4:\n vpbroadcastq xm2, [maskq+4*2]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movq xm1, [tmpq]\n add tmpq, 4*2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [maskq+8*2]\n.w8_loop:\n vpbroadcastq m2, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m2, 0x30\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n punpcklbw m0, m1\n pmaddubsw m0, m4\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m3, [maskq+16*2]\n vbroadcasti128 m4, [maskq+16*3]\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n mova m2, [tmpq]\n add tmpq, 16*2\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n sub hd, 2\n jg .w16_loop\n RET\nALIGN function_align\n.w32:\n mova xm3, [maskq+16*4]\n vinserti128 m3, [maskq+16*6], 1\n mova xm4, [maskq+16*5]\n vinserti128 m4, [maskq+16*7], 1\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m4\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, dsq\n dec hd\n jg .w32_loop\n RET\n\ncglobal blend_h, 4, 7, 6, dst, ds, tmp, w, h, mask\n%define base r5-blend_h_avx2_table\n lea r5, [blend_h_avx2_table]\n mov r6d, wd\n tzcnt wd, wd\n mov hd, hm\n movsxd wq, dword [r5+wq*4]\n vpbroadcastd m5, [base+pw_512]\n add wq, r5\n lea maskq, [base+obmc_masks+hq*2]\n lea hd, [hq*3]\n shr hd, 2 ; h * 3/4\n lea maskq, [maskq+hq*2]\n neg hq\n jmp wq\n.w2:\n movd xm0, [dstq+dsq*0]\n pinsrw xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movd xm1, [tmpq]\n add tmpq, 2*2\n punpcklwd xm2, xm2\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n pextrw [dstq+dsq*0], xm0, 0\n pextrw [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w2\n RET\nALIGN function_align\n.w4:\n mova xm3, [blend_shuf]\n.w4_loop:\n movd xm0, [dstq+dsq*0]\n pinsrd xm0, [dstq+dsq*1], 1\n movd xm2, [maskq+hq*2]\n movq xm1, [tmpq]\n add tmpq, 4*2\n pshufb xm2, xm3\n punpcklbw xm0, xm1\n pmaddubsw xm0, xm2\n pmulhrsw xm0, xm5\n packuswb xm0, xm0\n movd [dstq+dsq*0], xm0\n pextrd [dstq+dsq*1], xm0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w4_loop\n RET\nALIGN function_align\n.w8:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x03\n.w8_loop:\n vpbroadcastq m1, [dstq+dsq*0]\n movq xm0, [dstq+dsq*1]\n vpblendd m0, m1, 0x30\n vpbroadcastd m3, [maskq+hq*2]\n movq xm1, [tmpq+8*1]\n vinserti128 m1, [tmpq+8*0], 1\n add tmpq, 8*2\n pshufb m3, m4\n punpcklbw m0, m1\n pmaddubsw m0, m3\n pmulhrsw m0, m5\n vextracti128 xm1, m0, 1\n packuswb xm0, xm1\n movhps [dstq+dsq*0], xm0\n movq [dstq+dsq*1], xm0\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w8_loop\n RET\nALIGN function_align\n.w16:\n vbroadcasti128 m4, [blend_shuf]\n shufpd m4, m4, 0x0c\n.w16_loop:\n mova xm1, [dstq+dsq*0]\n vinserti128 m1, [dstq+dsq*1], 1\n vpbroadcastd m3, [maskq+hq*2]\n mova m2, [tmpq]\n add tmpq, 16*2\n pshufb m3, m4\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq+dsq*0], xm0\n vextracti128 [dstq+dsq*1], m0, 1\n lea dstq, [dstq+dsq*2]\n add hq, 2\n jl .w16_loop\n RET\nALIGN function_align\n.w32: ; w32/w64/w128\n sub dsq, r6\n.w32_loop0:\n vpbroadcastw m3, [maskq+hq*2]\n mov wd, r6d\n.w32_loop:\n mova m1, [dstq]\n mova m2, [tmpq]\n add tmpq, 32\n punpcklbw m0, m1, m2\n punpckhbw m1, m2\n pmaddubsw m0, m3\n pmaddubsw m1, m3\n pmulhrsw m0, m5\n pmulhrsw m1, m5\n packuswb m0, m1\n mova [dstq], m0\n add dstq, 32\n sub wd, 32\n jg .w32_loop\n add dstq, dsq\n inc hq\n jl .w32_loop0\n RET\n\ncglobal emu_edge, 10, 13, 1, bw, bh, iw, ih, x, y, dst, dstride, src, sstride, \\\n bottomext, rightext\n ; we assume that the buffer (stride) is larger than width, so we can\n ; safely overwrite by a few bytes\n\n ; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)\n xor r12d, r12d\n lea r10, [ihq-1]\n cmp yq, ihq\n cmovs r10, yq\n test yq, yq\n cmovs r10, r12\n imul r10, sstrideq\n add srcq, r10\n\n ; ref += iclip(x, 0, iw - 1)\n lea r10, [iwq-1]\n cmp xq, iwq\n cmovs r10, xq\n test xq, xq\n cmovs r10, r12\n add srcq, r10\n\n ; bottom_ext = iclip(y + bh - ih, 0, bh - 1)\n lea bottomextq, [yq+bhq]\n sub bottomextq, ihq\n lea r3, [bhq-1]\n cmovs bottomextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, x, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; top_ext = iclip(-y, 0, bh - 1)\n neg topextq\n cmovs topextq, r12\n cmp bottomextq, bhq\n cmovns bottomextq, r3\n cmp topextq, bhq\n cmovg topextq, r3\n\n ; right_ext = iclip(x + bw - iw, 0, bw - 1)\n lea rightextq, [xq+bwq]\n sub rightextq, iwq\n lea r2, [bwq-1]\n cmovs rightextq, r12\n\n DEFINE_ARGS bw, bh, iw, ih, leftext, topext, dst, dstride, src, sstride, \\\n bottomext, rightext\n\n ; left_ext = iclip(-x, 0, bw - 1)\n neg leftextq\n cmovs leftextq, r12\n cmp rightextq, bwq\n cmovns rightextq, r2\n cmp leftextq, bwq\n cmovns leftextq, r2\n\n DEFINE_ARGS bw, centerh, centerw, dummy, leftext, topext, \\\n dst, dstride, src, sstride, bottomext, rightext\n\n ; center_h = bh - top_ext - bottom_ext\n lea r3, [bottomextq+topextq]\n sub centerhq, r3\n\n ; blk += top_ext * PXSTRIDE(dst_stride)\n mov r2, topextq\n imul r2, dstrideq\n add dstq, r2\n mov r9m, dstq\n\n ; center_w = bw - left_ext - right_ext\n mov centerwq, bwq\n lea r3, [rightextq+leftextq]\n sub centerwq, r3\n\n%macro v_loop 3 ; need_left_ext, need_right_ext, suffix\n.v_loop_%3:\n%if %1\n test leftextq, leftextq\n jz .body_%3\n\n ; left extension\n xor r3, r3\n vpbroadcastb m0, [srcq]\n.left_loop_%3:\n mova [dstq+r3], m0\n add r3, 32\n cmp r3, leftextq\n jl .left_loop_%3\n\n ; body\n.body_%3:\n lea r12, [dstq+leftextq]\n%endif\n xor r3, r3\n.body_loop_%3:\n movu m0, [srcq+r3]\n%if %1\n movu [r12+r3], m0\n%else\n movu [dstq+r3], m0\n%endif\n add r3, 32\n cmp r3, centerwq\n jl .body_loop_%3\n\n%if %2\n ; right extension\n test rightextq, rightextq\n jz .body_loop_end_%3\n%if %1\n add r12, centerwq\n%else\n lea r12, [dstq+centerwq]\n%endif\n xor r3, r3\n vpbroadcastb m0, [srcq+centerwq-1]\n.right_loop_%3:\n movu [r12+r3], m0\n add r3, 32\n cmp r3, rightextq\n jl .right_loop_%3\n\n.body_loop_end_%3:\n%endif\n add dstq, dstrideq\n add srcq, sstrideq\n dec centerhq\n jg .v_loop_%3\n%endmacro\n\n test leftextq, leftextq\n jnz .need_left_ext\n test rightextq, rightextq\n jnz .need_right_ext\n v_loop 0, 0, 0\n jmp .body_done\n\n.need_left_ext:\n test rightextq, rightextq\n jnz .need_left_right_ext\n v_loop 1, 0, 1\n jmp .body_done\n\n.need_left_right_ext:\n v_loop 1, 1, 2\n jmp .body_done\n\n.need_right_ext:\n v_loop 0, 1, 3\n\n.body_done:\n ; bottom edge extension\n test bottomextq, bottomextq\n jz .top\n mov srcq, dstq\n sub srcq, dstrideq\n xor r1, r1\n.bottom_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, bottomextq\n.bottom_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .bottom_y_loop\n add r1, 32\n cmp r1, bwq\n jl .bottom_x_loop\n\n.top:\n ; top edge extension\n test topextq, topextq\n jz .end\n mov srcq, r9m\n mov dstq, dstm\n xor r1, r1\n.top_x_loop:\n mova m0, [srcq+r1]\n lea r3, [dstq+r1]\n mov r4, topextq\n.top_y_loop:\n mova [r3], m0\n add r3, dstrideq\n dec r4\n jg .top_y_loop\n add r1, 32\n cmp r1, bwq\n jl .top_x_loop\n\n.end:\n RET\n\nINIT_YMM avx2\nPREP_BILIN\nPREP_8TAP\n\nINIT_ZMM avx512icl\nPREP_BILIN\nPREP_8TAP\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":489,"cells":{"commit":{"kind":"string","value":"3a6a55d8d5883cf094bc3a140e568420014bbf47"},"subject":{"kind":"string","value":"x86: Fix crash in AVX2 cdef_filter with <32-byte stack alignment"},"message":{"kind":"string","value":"x86: Fix crash in AVX2 cdef_filter with <32-byte stack alignment\n"},"repos":{"kind":"string","value":"videolan/dav1d,videolan/dav1d"},"file_path":{"kind":"string","value":"src/x86/cdef.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1583359545,"string":"1,583,359,545"},"new_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\n%macro DUP4 1-*\n %rep %0\n times 4 db %1\n %rotate 1\n %endrep\n%endmacro\n\n%macro DIRS 16 ; cdef_directions[]\n %rep 4 + 16 + 4 ; 6 7 0 1 2 3 4 5 6 7 0 1\n ; masking away unused bits allows us to use a single vpaddd {1to16}\n ; instruction instead of having to do vpbroadcastd + paddb\n db %13 & 0x3f, -%13 & 0x3f\n %rotate 1\n %endrep\n%endmacro\n\n%macro JMP_TABLE 2-*\n %xdefine %1_jmptable %%table\n %xdefine %%base mangle(private_prefix %+ _%1_avx2)\n %%table:\n %rep %0 - 1\n dd %%base %+ .%2 - %%table\n %rotate 1\n %endrep\n%endmacro\n\n%macro CDEF_FILTER_JMP_TABLE 1\nJMP_TABLE cdef_filter_%1, \\\n d6k0, d6k1, d7k0, d7k1, \\\n d0k0, d0k1, d1k0, d1k1, d2k0, d2k1, d3k0, d3k1, \\\n d4k0, d4k1, d5k0, d5k1, d6k0, d6k1, d7k0, d7k1, \\\n d0k0, d0k1, d1k0, d1k1\n%endmacro\n\nSECTION_RODATA 64\n\nlut_perm_4x4: db 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79\n db 16, 17, 0, 1, 2, 3, 4, 5, 18, 19, 8, 9, 10, 11, 12, 13\n db 20, 21, 80, 81, 82, 83, 84, 85, 22, 23, 32, 33, 34, 35, 36, 37\n db 98, 99,100,101,102,103,104,105, 50, 51, 52, 53, 54, 55, 56, 57\nedge_mask: dq 0x00003c3c3c3c0000, 0x00003f3f3f3f0000 ; 0000, 0001\n dq 0x0000fcfcfcfc0000, 0x0000ffffffff0000 ; 0010, 0011\n dq 0x00003c3c3c3c3c3c, 0x00003f3f3f3f3f3f ; 0100, 0101\n dq 0x0000fcfcfcfcfcfc, 0x0000ffffffffffff ; 0110, 0111\n dq 0x3c3c3c3c3c3c0000, 0x3f3f3f3f3f3f0000 ; 1000, 1001\n dq 0xfcfcfcfcfcfc0000, 0xffffffffffff0000 ; 1010, 1011\n dq 0x3c3c3c3c3c3c3c3c, 0x3f3f3f3f3f3f3f3f ; 1100, 1101\n dq 0xfcfcfcfcfcfcfcfc, 0xffffffffffffffff ; 1110, 1111\npx_idx: DUP4 18, 19, 20, 21, 26, 27, 28, 29, 34, 35, 36, 37, 42, 43, 44, 45\ncdef_dirs: DIRS -7,-14, 1, -6, 1, 2, 1, 10, 9, 18, 8, 17, 8, 16, 8, 15\ngf_shr: dq 0x0102040810204080, 0x0102040810204080 ; >> 0, >> 0\n dq 0x0204081020408000, 0x0408102040800000 ; >> 1, >> 2\n dq 0x0810204080000000, 0x1020408000000000 ; >> 3, >> 4\n dq 0x2040800000000000, 0x4080000000000000 ; >> 5, >> 6\nend_perm: db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\npri_tap: db 64, 64, 32, 32, 48, 48, 48, 48 ; left-shifted by 4\nsec_tap: db 32, 32, 16, 16\npd_268435568: dd 268435568\nblend_4x4: dd 0x00, 0x80, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00\n dd 0x80, 0x00, 0x00\nblend_4x8_0: dd 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80\nblend_4x8_1: dd 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80\n dd 0x00, 0x00\nblend_4x8_2: dd 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080\n dd 0x0000\nblend_4x8_3: dd 0x0000, 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080\n dd 0x0000, 0x0000\nblend_8x8_0: dq 0x00, 0x00, 0x80, 0x80, 0x80, 0x80\nblend_8x8_1: dq 0x0000, 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x0000, 0x0000\npd_47130256: dd 4, 7, 1, 3, 0, 2, 5, 6\ndiv_table: dd 840, 420, 280, 210, 168, 140, 120, 105, 420, 210, 140, 105\nshufw_6543210x:db 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1, 14, 15\nshufb_lohi: db 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15\npw_128: times 2 dw 128\npw_2048: times 2 dw 2048\ntap_table: ; masks for 8 bit shifts\n db 0xFF, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01\n ; weights\n db 4, 2, 3, 3, 2, 1\n db -1 * 16 + 1, -2 * 16 + 2\n db 0 * 16 + 1, -1 * 16 + 2\n db 0 * 16 + 1, 0 * 16 + 2\n db 0 * 16 + 1, 1 * 16 + 2\n db 1 * 16 + 1, 2 * 16 + 2\n db 1 * 16 + 0, 2 * 16 + 1\n db 1 * 16 + 0, 2 * 16 + 0\n db 1 * 16 + 0, 2 * 16 - 1\n ; the last 6 are repeats of the first 6 so we don't need to & 7\n db -1 * 16 + 1, -2 * 16 + 2\n db 0 * 16 + 1, -1 * 16 + 2\n db 0 * 16 + 1, 0 * 16 + 2\n db 0 * 16 + 1, 1 * 16 + 2\n db 1 * 16 + 1, 2 * 16 + 2\n db 1 * 16 + 0, 2 * 16 + 1\n\nCDEF_FILTER_JMP_TABLE 4x4\nCDEF_FILTER_JMP_TABLE 4x8\nCDEF_FILTER_JMP_TABLE 8x8\n\nSECTION .text\n\n%macro PREP_REGS 2 ; w, h\n ; off1/2/3[k] [6 total] from [tapq+12+(dir+0/2/6)*2+k]\n mov dird, r6m\n lea tableq, [cdef_filter_%1x%2_jmptable]\n lea dirq, [tableq+dirq*2*4]\n%if %1 == 4\n %if %2 == 4\n DEFINE_ARGS dst, stride, left, top, pri, sec, \\\n table, dir, dirjmp, dst4, stride3, k\n %else\n DEFINE_ARGS dst, stride, left, top, pri, sec, \\\n table, dir, dirjmp, dst4, dst8, stride3, k\n lea dst8q, [dstq+strideq*8]\n %endif\n%else\n DEFINE_ARGS dst, stride, h, top1, pri, sec, \\\n table, dir, dirjmp, top2, dst4, stride3, k\n mov hq, -8\n lea top1q, [top1q+strideq*0]\n lea top2q, [top1q+strideq*1]\n%endif\n lea dst4q, [dstq+strideq*4]\n%if %1 == 4\n lea stride3q, [strideq*3]\n%endif\n%endmacro\n\n%macro LOAD_BLOCK 2-3 0 ; w, h, init_min_max\n mov kd, 1\n pxor m15, m15 ; sum\n%if %2 == 8\n pxor m12, m12\n %if %1 == 4\n movd xm4, [dstq +strideq*0]\n movd xm6, [dstq +strideq*1]\n movd xm5, [dstq +strideq*2]\n movd xm7, [dstq +stride3q ]\n vinserti128 m4, [dst4q+strideq*0], 1\n vinserti128 m6, [dst4q+strideq*1], 1\n vinserti128 m5, [dst4q+strideq*2], 1\n vinserti128 m7, [dst4q+stride3q ], 1\n punpckldq m4, m6\n punpckldq m5, m7\n %else\n movq xm4, [dstq+strideq*0]\n movq xm5, [dstq+strideq*1]\n vinserti128 m4, [dstq+strideq*2], 1\n vinserti128 m5, [dstq+stride3q ], 1\n %endif\n punpcklqdq m4, m5\n%else\n movd xm4, [dstq+strideq*0]\n movd xm5, [dstq+strideq*1]\n vinserti128 m4, [dstq+strideq*2], 1\n vinserti128 m5, [dstq+stride3q ], 1\n punpckldq m4, m5\n%endif\n%if %3 == 1\n mova m7, m4 ; min\n mova m8, m4 ; max\n%endif\n%endmacro\n\n%macro ACCUMULATE_TAP_BYTE 7-8 0 ; tap_offset, shift, mask, strength\n ; mul_tap, w, h, clip\n ; load p0/p1\n movsxd dirjmpq, [dirq+kq*4+%1*2*4]\n add dirjmpq, tableq\n call dirjmpq\n\n%if %8 == 1\n pmaxub m7, m5\n pminub m8, m5\n pmaxub m7, m6\n pminub m8, m6\n%endif\n\n ; accumulate sum[m15] over p0/p1\n%if %7 == 4\n punpcklbw m5, m6\n punpcklbw m6, m4, m4\n psubusb m9, m5, m6\n psubusb m5, m6, m5\n por m9, m5 ; abs_diff_p01(p01 - px)\n pcmpeqb m5, m9\n por m5, %5\n psignb m6, %5, m5\n psrlw m5, m9, %2 ; emulate 8-bit shift\n pand m5, %3\n psubusb m5, %4, m5\n pminub m5, m9\n pmaddubsw m5, m6\n paddw m15, m5\n%else\n psubusb m9, m5, m4\n psubusb m5, m4, m5\n psubusb m11, m6, m4\n psubusb m6, m4, m6\n por m9, m5 ; abs_diff_p0(p0 - px)\n por m11, m6 ; abs_diff_p1(p1 - px)\n pcmpeqb m5, m9\n pcmpeqb m6, m11\n punpckhbw m10, m9, m11\n punpcklbw m9, m11\n por m5, %5\n por m11, m6, %5\n punpckhbw m6, m5, m11\n punpcklbw m5, m11\n psignb m11, %5, m6\n psrlw m6, m10, %2 ; emulate 8-bit shift\n pand m6, %3\n psubusb m6, %4, m6\n pminub m6, m10\n pmaddubsw m6, m11\n paddw m12, m6\n psignb m11, %5, m5\n psrlw m5, m9, %2 ; emulate 8-bit shift\n pand m5, %3\n psubusb m5, %4, m5\n pminub m5, m9\n pmaddubsw m5, m11\n paddw m15, m5\n%endif\n%endmacro\n\n%macro ADJUST_PIXEL 4-5 0 ; w, h, zero, pw_2048, clip\n%if %2 == 4\n %if %5 == 1\n punpcklbw m4, %3\n %endif\n pcmpgtw %3, m15\n paddw m15, %3\n pmulhrsw m15, %4\n %if %5 == 0\n packsswb m15, m15\n paddb m4, m15\n %else\n paddw m4, m15\n packuswb m4, m4 ; clip px in [0x0,0xff]\n pminub m4, m7\n pmaxub m4, m8\n %endif\n vextracti128 xm5, m4, 1\n movd [dstq+strideq*0], xm4\n movd [dstq+strideq*2], xm5\n pextrd [dstq+strideq*1], xm4, 1\n pextrd [dstq+stride3q ], xm5, 1\n%else\n pcmpgtw m6, %3, m12\n pcmpgtw m5, %3, m15\n paddw m12, m6\n paddw m15, m5\n %if %5 == 1\n punpckhbw m5, m4, %3\n punpcklbw m4, %3\n %endif\n pmulhrsw m12, %4\n pmulhrsw m15, %4\n %if %5 == 0\n packsswb m15, m12\n paddb m4, m15\n %else\n paddw m5, m12\n paddw m4, m15\n packuswb m4, m5 ; clip px in [0x0,0xff]\n pminub m4, m7\n pmaxub m4, m8\n %endif\n vextracti128 xm5, m4, 1\n %if %1 == 4\n movd [dstq +strideq*0], xm4\n movd [dst4q+strideq*0], xm5\n pextrd [dstq +strideq*1], xm4, 1\n pextrd [dst4q+strideq*1], xm5, 1\n pextrd [dstq +strideq*2], xm4, 2\n pextrd [dst4q+strideq*2], xm5, 2\n pextrd [dstq +stride3q ], xm4, 3\n pextrd [dst4q+stride3q ], xm5, 3\n %else\n movq [dstq+strideq*0], xm4\n movq [dstq+strideq*2], xm5\n movhps [dstq+strideq*1], xm4\n movhps [dstq+stride3q ], xm5\n %endif\n%endif\n%endmacro\n\n%macro BORDER_PREP_REGS 2 ; w, h\n ; off1/2/3[k] [6 total] from [tapq+12+(dir+0/2/6)*2+k]\n mov dird, r6m\n lea dirq, [tableq+dirq*2+14]\n%if %1*%2*2/mmsize > 1\n %if %1 == 4\n DEFINE_ARGS dst, stride, dir, stk, pri, sec, stride3, h, off, k\n %else\n DEFINE_ARGS dst, stride, dir, stk, pri, sec, h, off, k\n %endif\n mov hd, %1*%2*2/mmsize\n%else\n DEFINE_ARGS dst, stride, dir, stk, pri, sec, stride3, off, k\n%endif\n lea stkq, [px]\n pxor m11, m11\n%endmacro\n\n%macro BORDER_LOAD_BLOCK 2-3 0 ; w, h, init_min_max\n mov kd, 1\n%if %1 == 4\n movq xm4, [stkq+32*0]\n movhps xm4, [stkq+32*1]\n movq xm5, [stkq+32*2]\n movhps xm5, [stkq+32*3]\n vinserti128 m4, xm5, 1\n%else\n mova xm4, [stkq+32*0] ; px\n vinserti128 m4, [stkq+32*1], 1\n%endif\n pxor m15, m15 ; sum\n%if %3 == 1\n mova m7, m4 ; max\n mova m8, m4 ; min\n%endif\n%endmacro\n\n%macro ACCUMULATE_TAP_WORD 6-7 0 ; tap_offset, shift, mask, strength\n ; mul_tap, w, clip\n ; load p0/p1\n movsx offq, byte [dirq+kq+%1] ; off1\n%if %6 == 4\n movq xm5, [stkq+offq*2+32*0] ; p0\n movq xm6, [stkq+offq*2+32*2]\n movhps xm5, [stkq+offq*2+32*1]\n movhps xm6, [stkq+offq*2+32*3]\n vinserti128 m5, xm6, 1\n%else\n movu xm5, [stkq+offq*2+32*0] ; p0\n vinserti128 m5, [stkq+offq*2+32*1], 1\n%endif\n neg offq ; -off1\n%if %6 == 4\n movq xm6, [stkq+offq*2+32*0] ; p1\n movq xm9, [stkq+offq*2+32*2]\n movhps xm6, [stkq+offq*2+32*1]\n movhps xm9, [stkq+offq*2+32*3]\n vinserti128 m6, xm9, 1\n%else\n movu xm6, [stkq+offq*2+32*0] ; p1\n vinserti128 m6, [stkq+offq*2+32*1], 1\n%endif\n%if %7 == 1\n ; out of bounds values are set to a value that is a both a large unsigned\n ; value and a negative signed value.\n ; use signed max and unsigned min to remove them\n pmaxsw m7, m5 ; max after p0\n pminuw m8, m5 ; min after p0\n pmaxsw m7, m6 ; max after p1\n pminuw m8, m6 ; min after p1\n%endif\n\n ; accumulate sum[m15] over p0/p1\n ; calculate difference before converting\n psubw m5, m4 ; diff_p0(p0 - px)\n psubw m6, m4 ; diff_p1(p1 - px)\n\n ; convert to 8-bits with signed saturation\n ; saturating to large diffs has no impact on the results\n packsswb m5, m6\n\n ; group into pairs so we can accumulate using maddubsw\n pshufb m5, m12\n pabsb m9, m5\n psignb m10, %5, m5\n psrlw m5, m9, %2 ; emulate 8-bit shift\n pand m5, %3\n psubusb m5, %4, m5\n\n ; use unsigned min since abs diff can equal 0x80\n pminub m5, m9\n pmaddubsw m5, m10\n paddw m15, m5\n%endmacro\n\n%macro BORDER_ADJUST_PIXEL 2-3 0 ; w, pw_2048, clip\n pcmpgtw m9, m11, m15\n paddw m15, m9\n pmulhrsw m15, %2\n paddw m4, m15\n%if %3 == 1\n pminsw m4, m7\n pmaxsw m4, m8\n%endif\n packuswb m4, m4\n vextracti128 xm5, m4, 1\n%if %1 == 4\n movd [dstq+strideq*0], xm4\n pextrd [dstq+strideq*1], xm4, 1\n movd [dstq+strideq*2], xm5\n pextrd [dstq+stride3q], xm5, 1\n%else\n movq [dstq+strideq*0], xm4\n movq [dstq+strideq*1], xm5\n%endif\n%endmacro\n\n%macro CDEF_FILTER 2 ; w, h\nINIT_YMM avx2\ncglobal cdef_filter_%1x%2, 4, 9, 0, dst, stride, left, top, \\\n pri, sec, dir, damping, edge\n%assign stack_offset_entry stack_offset\n mov edged, edgem\n cmp edged, 0xf\n jne .border_block\n\n PUSH r9\n PUSH r10\n PUSH r11\n%if %2 == 4\n %assign regs_used 12\n %if STACK_ALIGNMENT < 32\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n %endif\n ALLOC_STACK 0x60, 16\n pmovzxbw xm0, [leftq+1]\n vpermq m0, m0, q0110\n psrldq m1, m0, 4\n vpalignr m2, m0, m0, 12\n movu [rsp+0x10], m0\n movu [rsp+0x28], m1\n movu [rsp+0x40], m2\n%elif %1 == 4\n PUSH r12\n %assign regs_used 13\n %if STACK_ALIGNMENT < 32\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n %endif\n ALLOC_STACK 8*2+%1*%2*1, 16\n pmovzxwd m0, [leftq]\n mova [rsp+0x10], m0\n%else\n PUSH r12\n PUSH r13\n %assign regs_used 14\n %if STACK_ALIGNMENT < 32\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n %endif\n ALLOC_STACK 8*2+%1*%2*2+32, 16\n lea r11, [strideq*3]\n movu xm4, [dstq+strideq*2]\n pmovzxwq m0, [leftq+0]\n pmovzxwq m1, [leftq+8]\n vinserti128 m4, [dstq+r11], 1\n pmovzxbd m2, [leftq+1]\n pmovzxbd m3, [leftq+9]\n mova [rsp+0x10], m0\n mova [rsp+0x30], m1\n mova [rsp+0x50], m2\n mova [rsp+0x70], m3\n mova [rsp+0x90], m4\n%endif\n\n DEFINE_ARGS dst, stride, left, top, pri, secdmp, zero, pridmp, damping\n mov dampingd, r7m\n xor zerod, zerod\n movifnidn prid, prim\n sub dampingd, 31\n movifnidn secdmpd, secdmpm\n or prid, 0\n jz .sec_only\n movd xm0, prid\n lzcnt pridmpd, prid\n add pridmpd, dampingd\n cmovs pridmpd, zerod\n mov [rsp+0], pridmpq ; pri_shift\n or secdmpd, 0\n jz .pri_only\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n\n DEFINE_ARGS dst, stride, left, top, pri, secdmp, table, pridmp\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, left, top, pri, sec, table, dir\n vpbroadcastb m0, xm0 ; pri_strength\n vpbroadcastb m1, xm1 ; sec_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n lea secq, [tableq+12] ; sec_taps\n\n PREP_REGS %1, %2\n%if %1*%2 > mmsize\n.v_loop:\n%endif\n LOAD_BLOCK %1, %2, 1\n.k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_BYTE 2, [rsp+0], m13, m0, m2, %1, %2, 1 ; dir + 0\n ACCUMULATE_TAP_BYTE 4, [rsp+8], m14, m1, m3, %1, %2, 1 ; dir + 2\n ACCUMULATE_TAP_BYTE 0, [rsp+8], m14, m1, m3, %1, %2, 1 ; dir - 2\n dec kq\n jge .k_loop\n\n vpbroadcastd m10, [pw_2048]\n pxor m9, m9\n ADJUST_PIXEL %1, %2, m9, m10, 1\n%if %1*%2 > mmsize\n mov dstq, dst4q\n lea top1q, [rsp+0x90]\n lea top2q, [rsp+0xA0]\n lea dst4q, [dst4q+strideq*4]\n add hq, 4\n jl .v_loop\n%endif\n RET\n\n.pri_only:\n DEFINE_ARGS dst, stride, left, top, pri, _, table, pridmp\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, left, top, pri, _, table, dir\n vpbroadcastb m0, xm0 ; pri_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n PREP_REGS %1, %2\n vpbroadcastd m3, [pw_2048]\n pxor m1, m1\n%if %1*%2 > mmsize\n.pri_v_loop:\n%endif\n LOAD_BLOCK %1, %2\n.pri_k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n ACCUMULATE_TAP_BYTE 2, [rsp+0], m13, m0, m2, %1, %2 ; dir + 0\n dec kq\n jge .pri_k_loop\n ADJUST_PIXEL %1, %2, m1, m3\n%if %1*%2 > mmsize\n mov dstq, dst4q\n lea top1q, [rsp+0x90]\n lea top2q, [rsp+0xA0]\n lea dst4q, [dst4q+strideq*4]\n add hq, 4\n jl .pri_v_loop\n%endif\n RET\n\n.sec_only:\n DEFINE_ARGS dst, stride, left, top, _, secdmp, zero, _, damping\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n DEFINE_ARGS dst, stride, left, top, _, secdmp, table\n lea tableq, [tap_table]\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, left, top, _, sec, table, dir\n vpbroadcastb m1, xm1 ; sec_strength\n lea secq, [tableq+12] ; sec_taps\n PREP_REGS %1, %2\n vpbroadcastd m2, [pw_2048]\n pxor m0, m0\n%if %1*%2 > mmsize\n.sec_v_loop:\n%endif\n LOAD_BLOCK %1, %2\n.sec_k_loop:\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_BYTE 4, [rsp+8], m14, m1, m3, %1, %2 ; dir + 2\n ACCUMULATE_TAP_BYTE 0, [rsp+8], m14, m1, m3, %1, %2 ; dir - 2\n dec kq\n jge .sec_k_loop\n ADJUST_PIXEL %1, %2, m0, m2\n%if %1*%2 > mmsize\n mov dstq, dst4q\n lea top1q, [rsp+0x90]\n lea top2q, [rsp+0xA0]\n lea dst4q, [dst4q+strideq*4]\n add hq, 4\n jl .sec_v_loop\n%endif\n RET\n\n.d0k0:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m6, [dstq+strideq*1-1]\n vpbroadcastq m10, [dstq+strideq*2-1]\n movd xm5, [topq+strideq*1+1]\n movd xm9, [dstq+strideq*0+1]\n psrldq m11, m6, 2\n psrldq m12, m10, 2\n vinserti128 m6, [dstq+stride3q -1], 1\n vinserti128 m10, [dstq+strideq*4-1], 1\n vpblendd m5, m11, 0x10\n vpblendd m9, m12, 0x10\n movu m11, [blend_4x4+16]\n punpckldq m6, m10\n punpckldq m5, m9\n vpblendvb m6, [rsp+gprsize+0x28], m11\n %else\n movd xm5, [topq +strideq*1+1]\n movq xm6, [dstq +strideq*1-1]\n movq xm10, [dstq +stride3q -1]\n movq xm11, [dst4q+strideq*1-1]\n pinsrd xm5, [dstq +strideq*0+1], 1\n movhps xm6, [dstq +strideq*2-1]\n movhps xm10, [dst4q+strideq*0-1]\n movhps xm11, [dst4q+strideq*2-1]\n psrldq xm9, xm6, 2\n shufps xm5, xm9, q2010 ; -1 +0 +1 +2\n shufps xm6, xm10, q2020 ; +1 +2 +3 +4\n psrldq xm9, xm11, 2\n psrldq xm10, 2\n shufps xm10, xm9, q2020 ; +3 +4 +5 +6\n movd xm9, [dst4q+stride3q -1]\n pinsrd xm9, [dst4q+strideq*4-1], 1\n shufps xm11, xm9, q1020 ; +5 +6 +7 +8\n pmovzxbw m9, [leftq+3]\n vinserti128 m6, xm11, 1\n movu m11, [blend_4x8_0+4]\n vinserti128 m5, xm10, 1\n vpblendvb m6, m9, m11\n %endif\n%else\n lea r13, [blend_8x8_0+16]\n movq xm5, [top2q +1]\n vbroadcasti128 m10, [dstq+strideq*1-1]\n vbroadcasti128 m11, [dstq+strideq*2-1]\n movhps xm5, [dstq+strideq*0+1]\n vinserti128 m6, m10, [dstq+stride3q -1], 1\n vinserti128 m9, m11, [dstq+strideq*4-1], 1\n psrldq m10, 2\n psrldq m11, 2\n punpcklqdq m6, m9\n movu m9, [r13+hq*2*1+16*1]\n punpcklqdq m10, m11\n vpblendd m5, m10, 0xF0\n vpblendvb m6, [rsp+gprsize+80+hq*8+64+8*1], m9\n%endif\n ret\n.d1k0:\n.d2k0:\n.d3k0:\n%if %1 == 4\n %if %2 == 4\n movq xm6, [dstq+strideq*0-1]\n movq xm9, [dstq+strideq*1-1]\n vinserti128 m6, [dstq+strideq*2-1], 1\n vinserti128 m9, [dstq+stride3q -1], 1\n movu m11, [rsp+gprsize+0x10]\n pcmpeqd m12, m12\n psrldq m5, m6, 2\n psrldq m10, m9, 2\n psrld m12, 24\n punpckldq m6, m9\n punpckldq m5, m10\n vpblendvb m6, m11, m12\n %else\n movq xm6, [dstq +strideq*0-1]\n movq xm9, [dstq +strideq*2-1]\n movhps xm6, [dstq +strideq*1-1]\n movhps xm9, [dstq +stride3q -1]\n movq xm10, [dst4q+strideq*0-1]\n movhps xm10, [dst4q+strideq*1-1]\n psrldq xm5, xm6, 2\n psrldq xm11, xm9, 2\n shufps xm5, xm11, q2020\n movq xm11, [dst4q+strideq*2-1]\n movhps xm11, [dst4q+stride3q -1]\n shufps xm6, xm9, q2020\n shufps xm9, xm10, xm11, q2020\n vinserti128 m6, xm9, 1\n pmovzxbw m9, [leftq+1]\n psrldq xm10, 2\n psrldq xm11, 2\n shufps xm10, xm11, q2020\n vpbroadcastd m11, [blend_4x8_0+4]\n vinserti128 m5, xm10, 1\n vpblendvb m6, m9, m11\n %endif\n%else\n movu xm5, [dstq+strideq*0-1]\n movu xm9, [dstq+strideq*1-1]\n vinserti128 m5, [dstq+strideq*2-1], 1\n vinserti128 m9, [dstq+stride3q -1], 1\n mova m10, [blend_8x8_0+16]\n punpcklqdq m6, m5, m9\n vpblendvb m6, [rsp+gprsize+80+hq*8+64], m10\n psrldq m5, 2\n psrldq m9, 2\n punpcklqdq m5, m9\n%endif\n ret\n.d4k0:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m10, [dstq+strideq*1-1]\n vpbroadcastq m11, [dstq+strideq*2-1]\n movd xm6, [topq+strideq*1-1]\n movd xm9, [dstq+strideq*0-1]\n psrldq m5, m10, 2\n psrldq m12, m11, 2\n vpblendd m6, m10, 0x10\n vpblendd m9, m11, 0x10\n movu m10, [blend_4x4]\n vinserti128 m5, [dstq+stride3q +1], 1\n vinserti128 m12, [dstq+strideq*4+1], 1\n punpckldq m6, m9\n punpckldq m5, m12\n vpblendvb m6, [rsp+gprsize+0x40], m10\n %else\n movd xm6, [topq +strideq*1-1]\n movq xm9, [dstq +strideq*1-1]\n movq xm10, [dstq +stride3q -1]\n movq xm11, [dst4q+strideq*1-1]\n pinsrd xm6, [dstq +strideq*0-1], 1\n movhps xm9, [dstq +strideq*2-1]\n movhps xm10, [dst4q+strideq*0-1]\n movhps xm11, [dst4q+strideq*2-1]\n psrldq xm5, xm9, 2\n shufps xm6, xm9, q2010\n psrldq xm9, xm10, 2\n shufps xm5, xm9, q2020\n shufps xm10, xm11, q2020\n movd xm9, [dst4q+stride3q +1]\n vinserti128 m6, xm10, 1\n pinsrd xm9, [dst4q+strideq*4+1], 1\n psrldq xm11, 2\n pmovzxbw m10, [leftq-1]\n shufps xm11, xm9, q1020\n movu m9, [blend_4x8_0]\n vinserti128 m5, xm11, 1\n vpblendvb m6, m10, m9\n %endif\n%else\n lea r13, [blend_8x8_0+8]\n movq xm6, [top2q -1]\n vbroadcasti128 m5, [dstq+strideq*1-1]\n vbroadcasti128 m9, [dstq+strideq*2-1]\n movhps xm6, [dstq+strideq*0-1]\n movu m11, [r13+hq*2*1+16*1]\n punpcklqdq m10, m5, m9\n vinserti128 m5, [dstq+stride3q -1], 1\n vinserti128 m9, [dstq+strideq*4-1], 1\n vpblendd m6, m10, 0xF0\n vpblendvb m6, [rsp+gprsize+80+hq*8+64-8*1], m11\n psrldq m5, 2\n psrldq m9, 2\n punpcklqdq m5, m9\n%endif\n ret\n.d5k0:\n.d6k0:\n.d7k0:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [topq+strideq*1 ]\n vpbroadcastd m5, [dstq+strideq*1 ]\n vpbroadcastd m9, [dstq+strideq*2 ]\n vpblendd xm6, [dstq+strideq*0-4], 0x2\n vpblendd m5, m9, 0x22\n vpblendd m6, m5, 0x30\n vinserti128 m5, [dstq+stride3q ], 1\n vpblendd m5, [dstq+strideq*4-20], 0x20\n %else\n movd xm6, [topq +strideq*1]\n movd xm5, [dstq +strideq*1]\n movd xm9, [dstq +stride3q ]\n movd xm10, [dst4q+strideq*1]\n movd xm11, [dst4q+stride3q ]\n pinsrd xm6, [dstq +strideq*0], 1\n pinsrd xm5, [dstq +strideq*2], 1\n pinsrd xm9, [dst4q+strideq*0], 1\n pinsrd xm10, [dst4q+strideq*2], 1\n pinsrd xm11, [dst4q+strideq*4], 1\n punpcklqdq xm6, xm5\n punpcklqdq xm5, xm9\n punpcklqdq xm9, xm10\n punpcklqdq xm10, xm11\n vinserti128 m6, xm9, 1\n vinserti128 m5, xm10, 1\n %endif\n%else\n movq xm6, [top2q ]\n movq xm5, [dstq+strideq*1]\n movq xm9, [dstq+stride3q ]\n movhps xm6, [dstq+strideq*0]\n movhps xm5, [dstq+strideq*2]\n movhps xm9, [dstq+strideq*4]\n vinserti128 m6, xm5, 1\n vinserti128 m5, xm9, 1\n%endif\n ret\n.d0k1:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [dstq +strideq*2-2]\n movd xm9, [dstq +stride3q -2]\n movd xm5, [topq +strideq*0+2]\n movd xm10, [topq +strideq*1+2]\n pinsrw xm6, [leftq+4], 0\n pinsrw xm9, [leftq+6], 0\n vinserti128 m5, [dstq +strideq*0+2], 1\n vinserti128 m10, [dstq +strideq*1+2], 1\n vinserti128 m6, [dst4q+strideq*0-2], 1\n vinserti128 m9, [dst4q+strideq*1-2], 1\n punpckldq m5, m10\n punpckldq m6, m9\n %else\n movq xm6, [dstq +strideq*2-2]\n movd xm10, [dst4q+strideq*2-2]\n movd xm5, [topq +strideq*0+2]\n movq xm9, [dst4q+strideq*0-2]\n movhps xm6, [dstq +stride3q -2]\n pinsrw xm10, [dst4q+stride3q ], 3\n pinsrd xm5, [topq +strideq*1+2], 1\n movhps xm9, [dst4q+strideq*1-2]\n pinsrd xm10, [dst8q+strideq*0-2], 2\n pinsrd xm5, [dstq +strideq*0+2], 2\n pinsrd xm10, [dst8q+strideq*1-2], 3\n pinsrd xm5, [dstq +strideq*1+2], 3\n shufps xm11, xm6, xm9, q3131\n shufps xm6, xm9, q2020\n movu m9, [blend_4x8_3+8]\n vinserti128 m6, xm10, 1\n vinserti128 m5, xm11, 1\n vpblendvb m6, [rsp+gprsize+16+8], m9\n %endif\n%else\n lea r13, [blend_8x8_1+16]\n movq xm6, [dstq +strideq*2-2]\n movq xm9, [dstq +stride3q -2]\n movq xm5, [top1q +2]\n movq xm10, [top2q +2]\n movu m11, [r13+hq*2*2+16*2]\n vinserti128 m6, [dst4q+strideq*0-2], 1\n vinserti128 m9, [dst4q+strideq*1-2], 1\n vinserti128 m5, [dstq +strideq*0+2], 1\n vinserti128 m10, [dstq +strideq*1+2], 1\n punpcklqdq m6, m9\n punpcklqdq m5, m10\n vpblendvb m6, [rsp+gprsize+16+hq*8+64+8*2], m11\n%endif\n ret\n.d1k1:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m6, [dstq+strideq*1-2]\n vpbroadcastq m9, [dstq+strideq*2-2]\n movd xm5, [topq+strideq*1+2]\n movd xm10, [dstq+strideq*0+2]\n psrldq m11, m6, 4\n psrldq m12, m9, 4\n vpblendd m5, m11, 0x10\n movq xm11, [leftq+2]\n vinserti128 m6, [dstq+stride3q -2], 1\n punpckldq xm11, xm11\n vpblendd m10, m12, 0x10\n pcmpeqd m12, m12\n pmovzxwd m11, xm11\n psrld m12, 16\n punpckldq m6, m9\n vpbroadcastd m9, [dstq+strideq*4-2]\n vpblendvb m6, m11, m12\n punpckldq m5, m10\n vpblendd m6, m9, 0x20\n %else\n movd xm5, [topq +strideq*1+2]\n movq xm6, [dstq +strideq*1-2]\n movq xm9, [dstq +stride3q -2]\n movq xm10, [dst4q+strideq*1-2]\n movd xm11, [dst4q+stride3q -2]\n pinsrd xm5, [dstq +strideq*0+2], 1\n movhps xm6, [dstq +strideq*2-2]\n movhps xm9, [dst4q+strideq*0-2]\n movhps xm10, [dst4q+strideq*2-2]\n pinsrd xm11, [dst4q+strideq*4-2], 1\n shufps xm5, xm6, q3110\n shufps xm6, xm9, q2020\n shufps xm9, xm10, q3131\n shufps xm10, xm11, q1020\n movu m11, [blend_4x8_2+4]\n vinserti128 m6, xm10, 1\n vinserti128 m5, xm9, 1\n vpblendvb m6, [rsp+gprsize+16+4], m11\n %endif\n%else\n lea r13, [blend_8x8_1+16]\n movq xm5, [top2q +2]\n vbroadcasti128 m6, [dstq+strideq*1-2]\n vbroadcasti128 m9, [dstq+strideq*2-2]\n movhps xm5, [dstq+strideq*0+2]\n shufps m10, m6, m9, q2121\n vinserti128 m6, [dstq+stride3q -2], 1\n vinserti128 m9, [dstq+strideq*4-2], 1\n movu m11, [r13+hq*2*1+16*1]\n vpblendd m5, m10, 0xF0\n punpcklqdq m6, m9\n vpblendvb m6, [rsp+gprsize+16+hq*8+64+8*1], m11\n%endif\n ret\n.d2k1:\n%if %1 == 4\n %if %2 == 4\n movq xm11, [leftq]\n movq xm6, [dstq+strideq*0-2]\n movq xm9, [dstq+strideq*1-2]\n vinserti128 m6, [dstq+strideq*2-2], 1\n vinserti128 m9, [dstq+stride3q -2], 1\n punpckldq xm11, xm11\n psrldq m5, m6, 4\n psrldq m10, m9, 4\n pmovzxwd m11, xm11\n punpckldq m6, m9\n punpckldq m5, m10\n pblendw m6, m11, 0x05\n %else\n movq xm5, [dstq +strideq*0-2]\n movq xm9, [dstq +strideq*2-2]\n movq xm10, [dst4q+strideq*0-2]\n movq xm11, [dst4q+strideq*2-2]\n movhps xm5, [dstq +strideq*1-2]\n movhps xm9, [dstq +stride3q -2]\n movhps xm10, [dst4q+strideq*1-2]\n movhps xm11, [dst4q+stride3q -2]\n shufps xm6, xm5, xm9, q2020\n shufps xm5, xm9, q3131\n shufps xm9, xm10, xm11, q2020\n shufps xm10, xm11, q3131\n pmovzxwd m11, [leftq]\n vinserti128 m6, xm9, 1\n vinserti128 m5, xm10, 1\n pblendw m6, m11, 0x55\n %endif\n%else\n mova m11, [rsp+gprsize+16+hq*8+64]\n movu xm5, [dstq+strideq*0-2]\n movu xm9, [dstq+strideq*1-2]\n vinserti128 m5, [dstq+strideq*2-2], 1\n vinserti128 m9, [dstq+stride3q -2], 1\n shufps m6, m5, m9, q1010\n shufps m5, m9, q2121\n pblendw m6, m11, 0x11\n%endif\n ret\n.d3k1:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m11, [dstq+strideq*1-2]\n vpbroadcastq m12, [dstq+strideq*2-2]\n movd xm6, [topq+strideq*1-2]\n movd xm9, [dstq+strideq*0-2]\n pblendw m11, [leftq-16+2], 0x01\n pblendw m12, [leftq-16+4], 0x01\n pinsrw xm9, [leftq- 0+0], 0\n psrldq m5, m11, 4\n psrldq m10, m12, 4\n vinserti128 m5, [dstq+stride3q +2], 1\n vinserti128 m10, [dstq+strideq*4+2], 1\n vpblendd m6, m11, 0x10\n vpblendd m9, m12, 0x10\n punpckldq m6, m9\n punpckldq m5, m10\n %else\n movd xm6, [topq +strideq*1-2]\n movq xm5, [dstq +strideq*1-2]\n movq xm9, [dstq +stride3q -2]\n movq xm10, [dst4q+strideq*1-2]\n movd xm11, [dst4q+stride3q +2]\n pinsrw xm6, [dstq +strideq*0 ], 3\n movhps xm5, [dstq +strideq*2-2]\n movhps xm9, [dst4q+strideq*0-2]\n movhps xm10, [dst4q+strideq*2-2]\n pinsrd xm11, [dst4q+strideq*4+2], 1\n shufps xm6, xm5, q2010\n shufps xm5, xm9, q3131\n shufps xm9, xm10, q2020\n shufps xm10, xm11, q1031\n movu m11, [blend_4x8_2]\n vinserti128 m6, xm9, 1\n vinserti128 m5, xm10, 1\n vpblendvb m6, [rsp+gprsize+16-4], m11\n %endif\n%else\n lea r13, [blend_8x8_1+8]\n movq xm6, [top2q -2]\n vbroadcasti128 m5, [dstq+strideq*1-2]\n vbroadcasti128 m10, [dstq+strideq*2-2]\n movhps xm6, [dstq+strideq*0-2]\n punpcklqdq m9, m5, m10\n vinserti128 m5, [dstq+stride3q -2], 1\n vinserti128 m10, [dstq+strideq*4-2], 1\n movu m11, [r13+hq*2*1+16*1]\n vpblendd m6, m9, 0xF0\n shufps m5, m10, q2121\n vpblendvb m6, [rsp+gprsize+16+hq*8+64-8*1], m11\n%endif\n ret\n.d4k1:\n%if %1 == 4\n %if %2 == 4\n vinserti128 m6, [dstq +strideq*0-2], 1\n vinserti128 m9, [dstq +strideq*1-2], 1\n movd xm5, [dstq +strideq*2+2]\n movd xm10, [dstq +stride3q +2]\n pblendw m6, [leftq-16+0], 0x01\n pblendw m9, [leftq-16+2], 0x01\n vinserti128 m5, [dst4q+strideq*0+2], 1\n vinserti128 m10, [dst4q+strideq*1+2], 1\n vpblendd m6, [topq +strideq*0-2], 0x01\n vpblendd m9, [topq +strideq*1-2], 0x01\n punpckldq m5, m10\n punpckldq m6, m9\n %else\n movd xm6, [topq +strideq*0-2]\n movq xm5, [dstq +strideq*2-2]\n movq xm9, [dst4q+strideq*0-2]\n movd xm10, [dst4q+strideq*2+2]\n pinsrd xm6, [topq +strideq*1-2], 1\n movhps xm5, [dstq +stride3q -2]\n movhps xm9, [dst4q+strideq*1-2]\n pinsrd xm10, [dst4q+stride3q +2], 1\n pinsrd xm6, [dstq +strideq*0-2], 2\n pinsrd xm10, [dst8q+strideq*0+2], 2\n pinsrd xm6, [dstq +strideq*1-2], 3\n pinsrd xm10, [dst8q+strideq*1+2], 3\n shufps xm11, xm5, xm9, q2020\n shufps xm5, xm9, q3131\n movu m9, [blend_4x8_3]\n vinserti128 m6, xm11, 1\n vinserti128 m5, xm10, 1\n vpblendvb m6, [rsp+gprsize+16-8], m9\n %endif\n%else\n lea r13, [blend_8x8_1]\n movu m11, [r13+hq*2*2+16*2]\n movq xm6, [top1q -2]\n movq xm9, [top2q -2]\n movq xm5, [dstq +strideq*2+2]\n movq xm10, [dstq +stride3q +2]\n vinserti128 m6, [dstq +strideq*0-2], 1\n vinserti128 m9, [dstq +strideq*1-2], 1\n vinserti128 m5, [dst4q+strideq*0+2], 1\n vinserti128 m10, [dst4q+strideq*1+2], 1\n punpcklqdq m6, m9\n vpblendvb m6, [rsp+gprsize+16+hq*8+64-8*2], m11\n punpcklqdq m5, m10\n%endif\n ret\n.d5k1:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [topq +strideq*0-1]\n movd xm9, [topq +strideq*1-1]\n movd xm5, [dstq +strideq*2+1]\n movd xm10, [dstq +stride3q +1]\n pcmpeqd m12, m12\n pmovzxbw m11, [leftq-8+1]\n psrld m12, 24\n vinserti128 m6, [dstq +strideq*0-1], 1\n vinserti128 m9, [dstq +strideq*1-1], 1\n vinserti128 m5, [dst4q+strideq*0+1], 1\n vinserti128 m10, [dst4q+strideq*1+1], 1\n punpckldq m6, m9\n pxor m9, m9\n vpblendd m12, m9, 0x0F\n punpckldq m5, m10\n vpblendvb m6, m11, m12\n %else\n movd xm6, [topq +strideq*0-1]\n movq xm5, [dstq +strideq*2-1]\n movq xm9, [dst4q+strideq*0-1]\n movd xm10, [dst4q+strideq*2+1]\n pinsrd xm6, [topq +strideq*1-1], 1\n movhps xm5, [dstq +stride3q -1]\n movhps xm9, [dst4q+strideq*1-1]\n pinsrd xm10, [dst4q+stride3q +1], 1\n pinsrd xm6, [dstq +strideq*0-1], 2\n pinsrd xm10, [dst8q+strideq*0+1], 2\n pinsrd xm6, [dstq +strideq*1-1], 3\n pinsrd xm10, [dst8q+strideq*1+1], 3\n shufps xm11, xm5, xm9, q2020\n vinserti128 m6, xm11, 1\n pmovzxbw m11, [leftq-3]\n psrldq xm5, 2\n psrldq xm9, 2\n shufps xm5, xm9, q2020\n movu m9, [blend_4x8_1]\n vinserti128 m5, xm10, 1\n vpblendvb m6, m11, m9\n %endif\n%else\n lea r13, [blend_8x8_0]\n movu m11, [r13+hq*2*2+16*2]\n movq xm6, [top1q -1]\n movq xm9, [top2q -1]\n movq xm5, [dstq +strideq*2+1]\n movq xm10, [dstq +stride3q +1]\n vinserti128 m6, [dstq +strideq*0-1], 1\n vinserti128 m9, [dstq +strideq*1-1], 1\n vinserti128 m5, [dst4q+strideq*0+1], 1\n vinserti128 m10, [dst4q+strideq*1+1], 1\n punpcklqdq m6, m9\n punpcklqdq m5, m10\n vpblendvb m6, [rsp+gprsize+80+hq*8+64-8*2], m11\n%endif\n ret\n.d6k1:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [topq +strideq*0]\n movd xm9, [topq +strideq*1]\n movd xm5, [dstq +strideq*2]\n movd xm10, [dstq +stride3q ]\n vinserti128 m6, [dstq +strideq*0], 1\n vinserti128 m9, [dstq +strideq*1], 1\n vinserti128 m5, [dst4q+strideq*0], 1\n vinserti128 m10, [dst4q+strideq*1], 1\n punpckldq m6, m9\n punpckldq m5, m10\n %else\n movd xm5, [dstq +strideq*2]\n movd xm6, [topq +strideq*0]\n movd xm9, [dst4q+strideq*2]\n pinsrd xm5, [dstq +stride3q ], 1\n pinsrd xm6, [topq +strideq*1], 1\n pinsrd xm9, [dst4q+stride3q ], 1\n pinsrd xm5, [dst4q+strideq*0], 2\n pinsrd xm6, [dstq +strideq*0], 2\n pinsrd xm9, [dst8q+strideq*0], 2\n pinsrd xm5, [dst4q+strideq*1], 3\n pinsrd xm6, [dstq +strideq*1], 3\n pinsrd xm9, [dst8q+strideq*1], 3\n vinserti128 m6, xm5, 1\n vinserti128 m5, xm9, 1\n %endif\n%else\n movq xm5, [dstq +strideq*2]\n movq xm9, [dst4q+strideq*0]\n movq xm6, [top1q ]\n movq xm10, [dstq +strideq*0]\n movhps xm5, [dstq +stride3q ]\n movhps xm9, [dst4q+strideq*1]\n movhps xm6, [top2q ]\n movhps xm10, [dstq +strideq*1]\n vinserti128 m5, xm9, 1\n vinserti128 m6, xm10, 1\n%endif\n ret\n.d7k1:\n%if %1 == 4\n %if %2 == 4\n movd xm5, [dstq +strideq*2-1]\n movd xm9, [dstq +stride3q -1]\n movd xm6, [topq +strideq*0+1]\n movd xm10, [topq +strideq*1+1]\n pinsrb xm5, [leftq+ 5], 0\n pinsrb xm9, [leftq+ 7], 0\n vinserti128 m6, [dstq +strideq*0+1], 1\n vinserti128 m10, [dstq +strideq*1+1], 1\n vinserti128 m5, [dst4q+strideq*0-1], 1\n vinserti128 m9, [dst4q+strideq*1-1], 1\n punpckldq m6, m10\n punpckldq m5, m9\n %else\n movd xm6, [topq +strideq*0+1]\n movq xm9, [dstq +strideq*2-1]\n movq xm10, [dst4q+strideq*0-1]\n movd xm11, [dst4q+strideq*2-1]\n pinsrd xm6, [topq +strideq*1+1], 1\n movhps xm9, [dstq +stride3q -1]\n movhps xm10, [dst4q+strideq*1-1]\n pinsrd xm11, [dst4q+stride3q -1], 1\n pinsrd xm6, [dstq +strideq*0+1], 2\n pinsrd xm11, [dst8q+strideq*0-1], 2\n pinsrd xm6, [dstq +strideq*1+1], 3\n pinsrd xm11, [dst8q+strideq*1-1], 3\n shufps xm5, xm9, xm10, q2020\n vinserti128 m5, xm11, 1\n pmovzxbw m11, [leftq+5]\n psrldq xm9, 2\n psrldq xm10, 2\n shufps xm9, xm10, q2020\n movu m10, [blend_4x8_1+8]\n vinserti128 m6, xm9, 1\n vpblendvb m5, m11, m10\n %endif\n%else\n lea r13, [blend_8x8_0+16]\n movq xm5, [dstq +strideq*2-1]\n movq xm9, [dst4q+strideq*0-1]\n movq xm6, [top1q +1]\n movq xm10, [dstq +strideq*0+1]\n movhps xm5, [dstq +stride3q -1]\n movhps xm9, [dst4q+strideq*1-1]\n movhps xm6, [top2q +1]\n movhps xm10, [dstq +strideq*1+1]\n movu m11, [r13+hq*2*2+16*2]\n vinserti128 m5, xm9, 1\n vinserti128 m6, xm10, 1\n vpblendvb m5, [rsp+gprsize+80+hq*8+64+8*2], m11\n%endif\n ret\n\n.border_block:\n DEFINE_ARGS dst, stride, left, top, pri, sec, stride3, dst4, edge\n%define rstk rsp\n%assign stack_offset stack_offset_entry\n%if %1 == 4 && %2 == 8\n PUSH r9\n %assign regs_used 10\n%else\n %assign regs_used 9\n%endif\n%if STACK_ALIGNMENT < 32\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n%endif\n ALLOC_STACK 2*16+(%2+4)*32, 16\n%define px rsp+2*16+2*32\n\n pcmpeqw m14, m14\n psllw m14, 15 ; 0x8000\n\n ; prepare pixel buffers - body/right\n%if %1 == 4\n INIT_XMM avx2\n%endif\n%if %2 == 8\n lea dst4q, [dstq+strideq*4]\n%endif\n lea stride3q, [strideq*3]\n test edgeb, 2 ; have_right\n jz .no_right\n pmovzxbw m1, [dstq+strideq*0]\n pmovzxbw m2, [dstq+strideq*1]\n pmovzxbw m3, [dstq+strideq*2]\n pmovzxbw m4, [dstq+stride3q]\n mova [px+0*32], m1\n mova [px+1*32], m2\n mova [px+2*32], m3\n mova [px+3*32], m4\n%if %2 == 8\n pmovzxbw m1, [dst4q+strideq*0]\n pmovzxbw m2, [dst4q+strideq*1]\n pmovzxbw m3, [dst4q+strideq*2]\n pmovzxbw m4, [dst4q+stride3q]\n mova [px+4*32], m1\n mova [px+5*32], m2\n mova [px+6*32], m3\n mova [px+7*32], m4\n%endif\n jmp .body_done\n.no_right:\n%if %1 == 4\n movd xm1, [dstq+strideq*0]\n movd xm2, [dstq+strideq*1]\n movd xm3, [dstq+strideq*2]\n movd xm4, [dstq+stride3q]\n pmovzxbw xm1, xm1\n pmovzxbw xm2, xm2\n pmovzxbw xm3, xm3\n pmovzxbw xm4, xm4\n movq [px+0*32], xm1\n movq [px+1*32], xm2\n movq [px+2*32], xm3\n movq [px+3*32], xm4\n%else\n pmovzxbw xm1, [dstq+strideq*0]\n pmovzxbw xm2, [dstq+strideq*1]\n pmovzxbw xm3, [dstq+strideq*2]\n pmovzxbw xm4, [dstq+stride3q]\n mova [px+0*32], xm1\n mova [px+1*32], xm2\n mova [px+2*32], xm3\n mova [px+3*32], xm4\n%endif\n movd [px+0*32+%1*2], xm14\n movd [px+1*32+%1*2], xm14\n movd [px+2*32+%1*2], xm14\n movd [px+3*32+%1*2], xm14\n%if %2 == 8\n %if %1 == 4\n movd xm1, [dst4q+strideq*0]\n movd xm2, [dst4q+strideq*1]\n movd xm3, [dst4q+strideq*2]\n movd xm4, [dst4q+stride3q]\n pmovzxbw xm1, xm1\n pmovzxbw xm2, xm2\n pmovzxbw xm3, xm3\n pmovzxbw xm4, xm4\n movq [px+4*32], xm1\n movq [px+5*32], xm2\n movq [px+6*32], xm3\n movq [px+7*32], xm4\n %else\n pmovzxbw xm1, [dst4q+strideq*0]\n pmovzxbw xm2, [dst4q+strideq*1]\n pmovzxbw xm3, [dst4q+strideq*2]\n pmovzxbw xm4, [dst4q+stride3q]\n mova [px+4*32], xm1\n mova [px+5*32], xm2\n mova [px+6*32], xm3\n mova [px+7*32], xm4\n %endif\n movd [px+4*32+%1*2], xm14\n movd [px+5*32+%1*2], xm14\n movd [px+6*32+%1*2], xm14\n movd [px+7*32+%1*2], xm14\n%endif\n.body_done:\n\n ; top\n test edgeb, 4 ; have_top\n jz .no_top\n test edgeb, 1 ; have_left\n jz .top_no_left\n test edgeb, 2 ; have_right\n jz .top_no_right\n pmovzxbw m1, [topq+strideq*0-(%1/2)]\n pmovzxbw m2, [topq+strideq*1-(%1/2)]\n movu [px-2*32-%1], m1\n movu [px-1*32-%1], m2\n jmp .top_done\n.top_no_right:\n pmovzxbw m1, [topq+strideq*0-%1]\n pmovzxbw m2, [topq+strideq*1-%1]\n movu [px-2*32-%1*2], m1\n movu [px-1*32-%1*2], m2\n movd [px-2*32+%1*2], xm14\n movd [px-1*32+%1*2], xm14\n jmp .top_done\n.top_no_left:\n test edgeb, 2 ; have_right\n jz .top_no_left_right\n pmovzxbw m1, [topq+strideq*0]\n pmovzxbw m2, [topq+strideq*1]\n mova [px-2*32+0], m1\n mova [px-1*32+0], m2\n movd [px-2*32-4], xm14\n movd [px-1*32-4], xm14\n jmp .top_done\n.top_no_left_right:\n%if %1 == 4\n movd xm1, [topq+strideq*0]\n pinsrd xm1, [topq+strideq*1], 1\n pmovzxbw xm1, xm1\n movq [px-2*32+0], xm1\n movhps [px-1*32+0], xm1\n%else\n pmovzxbw xm1, [topq+strideq*0]\n pmovzxbw xm2, [topq+strideq*1]\n mova [px-2*32+0], xm1\n mova [px-1*32+0], xm2\n%endif\n movd [px-2*32-4], xm14\n movd [px-1*32-4], xm14\n movd [px-2*32+%1*2], xm14\n movd [px-1*32+%1*2], xm14\n jmp .top_done\n.no_top:\n movu [px-2*32-%1], m14\n movu [px-1*32-%1], m14\n.top_done:\n\n ; left\n test edgeb, 1 ; have_left\n jz .no_left\n pmovzxbw xm1, [leftq+ 0]\n%if %2 == 8\n pmovzxbw xm2, [leftq+ 8]\n%endif\n movd [px+0*32-4], xm1\n pextrd [px+1*32-4], xm1, 1\n pextrd [px+2*32-4], xm1, 2\n pextrd [px+3*32-4], xm1, 3\n%if %2 == 8\n movd [px+4*32-4], xm2\n pextrd [px+5*32-4], xm2, 1\n pextrd [px+6*32-4], xm2, 2\n pextrd [px+7*32-4], xm2, 3\n%endif\n jmp .left_done\n.no_left:\n movd [px+0*32-4], xm14\n movd [px+1*32-4], xm14\n movd [px+2*32-4], xm14\n movd [px+3*32-4], xm14\n%if %2 == 8\n movd [px+4*32-4], xm14\n movd [px+5*32-4], xm14\n movd [px+6*32-4], xm14\n movd [px+7*32-4], xm14\n%endif\n.left_done:\n\n ; bottom\n DEFINE_ARGS dst, stride, dst8, dummy1, pri, sec, stride3, dummy3, edge\n test edgeb, 8 ; have_bottom\n jz .no_bottom\n lea dst8q, [dstq+%2*strideq]\n test edgeb, 1 ; have_left\n jz .bottom_no_left\n test edgeb, 2 ; have_right\n jz .bottom_no_right\n pmovzxbw m1, [dst8q-(%1/2)]\n pmovzxbw m2, [dst8q+strideq-(%1/2)]\n movu [px+(%2+0)*32-%1], m1\n movu [px+(%2+1)*32-%1], m2\n jmp .bottom_done\n.bottom_no_right:\n pmovzxbw m1, [dst8q-%1]\n pmovzxbw m2, [dst8q+strideq-%1]\n movu [px+(%2+0)*32-%1*2], m1\n movu [px+(%2+1)*32-%1*2], m2\n%if %1 == 8\n movd [px+(%2-1)*32+%1*2], xm14 ; overwritten by previous movu\n%endif\n movd [px+(%2+0)*32+%1*2], xm14\n movd [px+(%2+1)*32+%1*2], xm14\n jmp .bottom_done\n.bottom_no_left:\n test edgeb, 2 ; have_right\n jz .bottom_no_left_right\n pmovzxbw m1, [dst8q]\n pmovzxbw m2, [dst8q+strideq]\n mova [px+(%2+0)*32+0], m1\n mova [px+(%2+1)*32+0], m2\n movd [px+(%2+0)*32-4], xm14\n movd [px+(%2+1)*32-4], xm14\n jmp .bottom_done\n.bottom_no_left_right:\n%if %1 == 4\n movd xm1, [dst8q]\n pinsrd xm1, [dst8q+strideq], 1\n pmovzxbw xm1, xm1\n movq [px+(%2+0)*32+0], xm1\n movhps [px+(%2+1)*32+0], xm1\n%else\n pmovzxbw xm1, [dst8q]\n pmovzxbw xm2, [dst8q+strideq]\n mova [px+(%2+0)*32+0], xm1\n mova [px+(%2+1)*32+0], xm2\n%endif\n movd [px+(%2+0)*32-4], xm14\n movd [px+(%2+1)*32-4], xm14\n movd [px+(%2+0)*32+%1*2], xm14\n movd [px+(%2+1)*32+%1*2], xm14\n jmp .bottom_done\n.no_bottom:\n movu [px+(%2+0)*32-%1], m14\n movu [px+(%2+1)*32-%1], m14\n.bottom_done:\n\n ; actual filter\n INIT_YMM avx2\n DEFINE_ARGS dst, stride, pridmp, damping, pri, secdmp, stride3, zero\n%undef edged\n ; register to shuffle values into after packing\n vbroadcasti128 m12, [shufb_lohi]\n\n mov dampingd, r7m\n xor zerod, zerod\n movifnidn prid, prim\n sub dampingd, 31\n movifnidn secdmpd, secdmpm\n or prid, 0\n jz .border_sec_only\n movd xm0, prid\n lzcnt pridmpd, prid\n add pridmpd, dampingd\n cmovs pridmpd, zerod\n mov [rsp+0], pridmpq ; pri_shift\n or secdmpd, 0\n jz .border_pri_only\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n\n DEFINE_ARGS dst, stride, pridmp, table, pri, secdmp, stride3\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, dir, table, pri, sec, stride3\n vpbroadcastb m0, xm0 ; pri_strength\n vpbroadcastb m1, xm1 ; sec_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n lea secq, [tableq+12] ; sec_taps\n\n BORDER_PREP_REGS %1, %2\n%if %1*%2*2/mmsize > 1\n.border_v_loop:\n%endif\n BORDER_LOAD_BLOCK %1, %2, 1\n.border_k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_WORD 0*2, [rsp+0], m13, m0, m2, %1, 1\n ACCUMULATE_TAP_WORD 2*2, [rsp+8], m14, m1, m3, %1, 1\n ACCUMULATE_TAP_WORD 6*2, [rsp+8], m14, m1, m3, %1, 1\n dec kq\n jge .border_k_loop\n\n vpbroadcastd m10, [pw_2048]\n BORDER_ADJUST_PIXEL %1, m10, 1\n%if %1*%2*2/mmsize > 1\n %define vloop_lines (mmsize/(%1*2))\n lea dstq, [dstq+strideq*vloop_lines]\n add stkq, 32*vloop_lines\n dec hd\n jg .border_v_loop\n%endif\n RET\n\n.border_pri_only:\n DEFINE_ARGS dst, stride, pridmp, table, pri, _, stride3\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n DEFINE_ARGS dst, stride, dir, table, pri, _, stride3\n vpbroadcastb m0, xm0 ; pri_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n BORDER_PREP_REGS %1, %2\n vpbroadcastd m1, [pw_2048]\n%if %1*%2*2/mmsize > 1\n.border_pri_v_loop:\n%endif\n BORDER_LOAD_BLOCK %1, %2\n.border_pri_k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n ACCUMULATE_TAP_WORD 0*2, [rsp+0], m13, m0, m2, %1\n dec kq\n jge .border_pri_k_loop\n BORDER_ADJUST_PIXEL %1, m1\n%if %1*%2*2/mmsize > 1\n %define vloop_lines (mmsize/(%1*2))\n lea dstq, [dstq+strideq*vloop_lines]\n add stkq, 32*vloop_lines\n dec hd\n jg .border_pri_v_loop\n%endif\n RET\n\n.border_sec_only:\n DEFINE_ARGS dst, stride, _, damping, _, secdmp, stride3, zero\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n DEFINE_ARGS dst, stride, _, table, _, secdmp, stride3\n lea tableq, [tap_table]\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n DEFINE_ARGS dst, stride, dir, table, _, sec, stride3\n vpbroadcastb m1, xm1 ; sec_strength\n lea secq, [tableq+12] ; sec_taps\n BORDER_PREP_REGS %1, %2\n vpbroadcastd m0, [pw_2048]\n%if %1*%2*2/mmsize > 1\n.border_sec_v_loop:\n%endif\n BORDER_LOAD_BLOCK %1, %2\n.border_sec_k_loop:\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_WORD 2*2, [rsp+8], m14, m1, m3, %1\n ACCUMULATE_TAP_WORD 6*2, [rsp+8], m14, m1, m3, %1\n dec kq\n jge .border_sec_k_loop\n BORDER_ADJUST_PIXEL %1, m0\n%if %1*%2*2/mmsize > 1\n %define vloop_lines (mmsize/(%1*2))\n lea dstq, [dstq+strideq*vloop_lines]\n add stkq, 32*vloop_lines\n dec hd\n jg .border_sec_v_loop\n%endif\n RET\n%endmacro\n\nCDEF_FILTER 8, 8\nCDEF_FILTER 4, 8\nCDEF_FILTER 4, 4\n\nINIT_YMM avx2\ncglobal cdef_dir, 3, 4, 15, src, stride, var, stride3\n lea stride3q, [strideq*3]\n movq xm0, [srcq+strideq*0]\n movq xm1, [srcq+strideq*1]\n movq xm2, [srcq+strideq*2]\n movq xm3, [srcq+stride3q]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vpbroadcastq m7, [srcq+stride3q]\n vpbroadcastd m8, [pw_128]\n pxor m9, m9\n\n vpblendd m0, m0, m7, 0xf0\n vpblendd m1, m1, m6, 0xf0\n vpblendd m2, m2, m5, 0xf0\n vpblendd m3, m3, m4, 0xf0\n\n punpcklbw m0, m9\n punpcklbw m1, m9\n punpcklbw m2, m9\n punpcklbw m3, m9\n\n psubw m0, m8\n psubw m1, m8\n psubw m2, m8\n psubw m3, m8\n\n ; shuffle registers to generate partial_sum_diag[0-1] together\n vpermq m7, m0, q1032\n vpermq m6, m1, q1032\n vpermq m5, m2, q1032\n vpermq m4, m3, q1032\n\n ; start with partial_sum_hv[0-1]\n paddw m8, m0, m1\n paddw m9, m2, m3\n phaddw m10, m0, m1\n phaddw m11, m2, m3\n paddw m8, m9\n phaddw m10, m11\n vextracti128 xm9, m8, 1\n vextracti128 xm11, m10, 1\n paddw xm8, xm9 ; partial_sum_hv[1]\n phaddw xm10, xm11 ; partial_sum_hv[0]\n vinserti128 m8, xm10, 1\n vpbroadcastd m9, [div_table+44]\n pmaddwd m8, m8\n pmulld m8, m9 ; cost6[2a-d] | cost2[a-d]\n\n ; create aggregates [lower half]:\n ; m9 = m0:01234567+m1:x0123456+m2:xx012345+m3:xxx01234+\n ; m4:xxxx0123+m5:xxxxx012+m6:xxxxxx01+m7:xxxxxxx0\n ; m10= m1:7xxxxxxx+m2:67xxxxxx+m3:567xxxxx+\n ; m4:4567xxxx+m5:34567xxx+m6:234567xx+m7:1234567x\n ; and [upper half]:\n ; m9 = m0:xxxxxxx0+m1:xxxxxx01+m2:xxxxx012+m3:xxxx0123+\n ; m4:xxx01234+m5:xx012345+m6:x0123456+m7:01234567\n ; m10= m0:1234567x+m1:234567xx+m2:34567xxx+m3:4567xxxx+\n ; m4:567xxxxx+m5:67xxxxxx+m6:7xxxxxxx\n ; and then shuffle m11 [shufw_6543210x], unpcklwd, pmaddwd, pmulld, paddd\n\n pslldq m9, m1, 2\n psrldq m10, m1, 14\n pslldq m11, m2, 4\n psrldq m12, m2, 12\n pslldq m13, m3, 6\n psrldq m14, m3, 10\n paddw m9, m11\n paddw m10, m12\n paddw m9, m13\n paddw m10, m14\n pslldq m11, m4, 8\n psrldq m12, m4, 8\n pslldq m13, m5, 10\n psrldq m14, m5, 6\n paddw m9, m11\n paddw m10, m12\n paddw m9, m13\n paddw m10, m14\n pslldq m11, m6, 12\n psrldq m12, m6, 4\n pslldq m13, m7, 14\n psrldq m14, m7, 2\n paddw m9, m11\n paddw m10, m12\n paddw m9, m13\n paddw m10, m14 ; partial_sum_diag[0/1][8-14,zero]\n vbroadcasti128 m14, [shufw_6543210x]\n vbroadcasti128 m13, [div_table+16]\n vbroadcasti128 m12, [div_table+0]\n paddw m9, m0 ; partial_sum_diag[0/1][0-7]\n pshufb m10, m14\n punpckhwd m11, m9, m10\n punpcklwd m9, m10\n pmaddwd m11, m11\n pmaddwd m9, m9\n pmulld m11, m13\n pmulld m9, m12\n paddd m9, m11 ; cost0[a-d] | cost4[a-d]\n\n ; merge horizontally and vertically for partial_sum_alt[0-3]\n paddw m10, m0, m1\n paddw m11, m2, m3\n paddw m12, m4, m5\n paddw m13, m6, m7\n phaddw m0, m4\n phaddw m1, m5\n phaddw m2, m6\n phaddw m3, m7\n\n ; create aggregates [lower half]:\n ; m4 = m10:01234567+m11:x0123456+m12:xx012345+m13:xxx01234\n ; m11= m11:7xxxxxxx+m12:67xxxxxx+m13:567xxxxx\n ; and [upper half]:\n ; m4 = m10:xxx01234+m11:xx012345+m12:x0123456+m13:01234567\n ; m11= m10:567xxxxx+m11:67xxxxxx+m12:7xxxxxxx\n ; and then pshuflw m11 3012, unpcklwd, pmaddwd, pmulld, paddd\n\n pslldq m4, m11, 2\n psrldq m11, 14\n pslldq m5, m12, 4\n psrldq m12, 12\n pslldq m6, m13, 6\n psrldq m13, 10\n paddw m4, m10\n paddw m11, m12\n vpbroadcastd m12, [div_table+44]\n paddw m5, m6\n paddw m11, m13 ; partial_sum_alt[3/2] right\n vbroadcasti128 m13, [div_table+32]\n paddw m4, m5 ; partial_sum_alt[3/2] left\n pshuflw m5, m11, q3012\n punpckhwd m6, m11, m4\n punpcklwd m4, m5\n pmaddwd m6, m6\n pmaddwd m4, m4\n pmulld m6, m12\n pmulld m4, m13\n paddd m4, m6 ; cost7[a-d] | cost5[a-d]\n\n ; create aggregates [lower half]:\n ; m5 = m0:01234567+m1:x0123456+m2:xx012345+m3:xxx01234\n ; m1 = m1:7xxxxxxx+m2:67xxxxxx+m3:567xxxxx\n ; and [upper half]:\n ; m5 = m0:xxx01234+m1:xx012345+m2:x0123456+m3:01234567\n ; m1 = m0:567xxxxx+m1:67xxxxxx+m2:7xxxxxxx\n ; and then pshuflw m1 3012, unpcklwd, pmaddwd, pmulld, paddd\n\n pslldq m5, m1, 2\n psrldq m1, 14\n pslldq m6, m2, 4\n psrldq m2, 12\n pslldq m7, m3, 6\n psrldq m3, 10\n paddw m5, m0\n paddw m1, m2\n paddw m6, m7\n paddw m1, m3 ; partial_sum_alt[0/1] right\n paddw m5, m6 ; partial_sum_alt[0/1] left\n pshuflw m0, m1, q3012\n punpckhwd m1, m5\n punpcklwd m5, m0\n pmaddwd m1, m1\n pmaddwd m5, m5\n pmulld m1, m12\n pmulld m5, m13\n paddd m5, m1 ; cost1[a-d] | cost3[a-d]\n\n mova xm0, [pd_47130256+ 16]\n mova m1, [pd_47130256]\n phaddd m9, m8\n phaddd m5, m4\n phaddd m9, m5\n vpermd m0, m9 ; cost[0-3]\n vpermd m1, m9 ; cost[4-7] | cost[0-3]\n\n ; now find the best cost\n pmaxsd xm2, xm0, xm1\n pshufd xm3, xm2, q1032\n pmaxsd xm2, xm3\n pshufd xm3, xm2, q2301\n pmaxsd xm2, xm3 ; best cost\n\n ; find the idx using minpos\n ; make everything other than the best cost negative via subtraction\n ; find the min of unsigned 16-bit ints to sort out the negative values\n psubd xm4, xm1, xm2\n psubd xm3, xm0, xm2\n packssdw xm3, xm4\n phminposuw xm3, xm3\n\n ; convert idx to 32-bits\n psrld xm3, 16\n movd eax, xm3\n\n ; get idx^4 complement\n vpermd m3, m1\n psubd xm2, xm3\n psrld xm2, 10\n movd [varq], xm2\n RET\n\n%if WIN64\nDECLARE_REG_TMP 5, 6\n%else\nDECLARE_REG_TMP 8, 5\n%endif\n\n; lut:\n; t0 t1 t2 t3 t4 t5 t6 t7\n; T0 T1 T2 T3 T4 T5 T6 T7\n; L0 L1 00 01 02 03 04 05\n; L2 L3 10 11 12 13 14 15\n; L4 L5 20 21 22 23 24 25\n; L6 L7 30 31 32 33 34 35\n; 4e 4f 40 41 42 43 44 45\n; 5e 5f 50 51 52 53 54 55\n\nINIT_ZMM avx512icl\ncglobal cdef_filter_4x4, 4, 8, 13, dst, stride, left, top, pri, sec, dir, damping, edge\n%define base r7-edge_mask\n movq xmm0, [dstq+strideq*0]\n movhps xmm0, [dstq+strideq*1]\n lea r7, [edge_mask]\n movq xmm1, [topq+strideq*0-2]\n movhps xmm1, [topq+strideq*1-2]\n mov r6d, edgem\n vinserti32x4 ym0, ymm0, [leftq], 1\n lea r2, [strideq*3]\n vinserti32x4 ym1, ymm1, [dstq+strideq*2], 1\n mova m5, [base+lut_perm_4x4]\n vinserti32x4 m0, [dstq+r2], 2\n test r6b, 0x08 ; avoid buffer overread\n jz .main\n lea r3, [dstq+strideq*4-4]\n vinserti32x4 m1, [r3+strideq*0], 2\n vinserti32x4 m0, [r3+strideq*1], 3\n.main:\n movifnidn prid, prim\n mov t0d, dirm\n mova m3, [base+px_idx]\n mov r3d, dampingm\n vpermi2b m5, m0, m1 ; lut\n vpbroadcastd m0, [base+pd_268435568] ; (1 << 28) + (7 << 4)\n pxor m7, m7\n lea r3, [r7+r3*8] ; gf_shr + (damping - 30) * 8\n vpermb m6, m3, m5 ; px\n cmp r6d, 0x0f\n jne .mask_edges ; mask edges only if required\n test prid, prid\n jz .sec_only\n vpaddd m1, m3, [base+cdef_dirs+(t0+2)*4] {1to16} ; dir\n vpermb m1, m1, m5 ; k0p0 k0p1 k1p0 k1p1\n%macro CDEF_FILTER_4x4_PRI 0\n vpcmpub k1, m6, m1, 6 ; px > pN\n psubb m2, m1, m6\n lzcnt r6d, prid\n vpsubb m2{k1}, m6, m1 ; abs(diff)\n vpbroadcastb m4, prim\n and prid, 1\n vgf2p8affineqb m9, m2, [r3+r6*8] {1to8}, 0 ; abs(diff) >> shift\n movifnidn t1d, secm\n vpbroadcastd m10, [base+pri_tap+priq*4]\n vpsubb m10{k1}, m7, m10 ; apply_sign(pri_tap)\n psubusb m4, m9 ; imax(0, pri_strength - (abs(diff) >> shift)))\n pminub m2, m4\n vpdpbusd m0, m2, m10 ; sum\n%endmacro\n CDEF_FILTER_4x4_PRI\n test t1d, t1d ; sec\n jz .end_no_clip\n call .sec\n.end_clip:\n pminub m4, m6, m1\n pmaxub m1, m6\n pminub m5, m2, m3\n pmaxub m2, m3\n pminub m4, m5\n pmaxub m2, m1\n psrldq m1, m4, 2\n psrldq m3, m2, 2\n pminub m1, m4\n vpcmpw k1, m0, m7, 1\n vpshldd m6, m0, 8\n pmaxub m2, m3\n pslldq m3, m1, 1\n psubw m7, m0\n paddusw m0, m6 ; clip >0xff\n vpsubusw m0{k1}, m6, m7 ; clip <0x00\n pslldq m4, m2, 1\n pminub m1, m3\n pmaxub m2, m4\n pmaxub m0, m1\n pminub m0, m2\n jmp .end\n.sec_only:\n movifnidn t1d, secm\n call .sec\n.end_no_clip:\n vpshldd m6, m0, 8 ; (px << 8) + ((sum > -8) << 4)\n paddw m0, m6 ; (px << 8) + ((sum + (sum > -8) + 7) << 4)\n.end:\n mova xm1, [base+end_perm]\n vpermb m0, m1, m0 ; output in bits 8-15 of each dword\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n pextrd [dstq+strideq*2], xm0, 2\n pextrd [dstq+r2 ], xm0, 3\n RET\n.mask_edges_sec_only:\n movifnidn t1d, secm\n call .mask_edges_sec\n jmp .end_no_clip\nALIGN function_align\n.mask_edges:\n vpbroadcastq m8, [base+edge_mask+r6*8]\n test prid, prid\n jz .mask_edges_sec_only\n vpaddd m2, m3, [base+cdef_dirs+(t0+2)*4] {1to16}\n vpshufbitqmb k1, m8, m2 ; index in-range\n mova m1, m6\n vpermb m1{k1}, m2, m5\n CDEF_FILTER_4x4_PRI\n test t1d, t1d\n jz .end_no_clip\n call .mask_edges_sec\n jmp .end_clip\n.mask_edges_sec:\n vpaddd m4, m3, [base+cdef_dirs+(t0+4)*4] {1to16}\n vpaddd m9, m3, [base+cdef_dirs+(t0+0)*4] {1to16}\n vpshufbitqmb k1, m8, m4\n mova m2, m6\n vpermb m2{k1}, m4, m5\n vpshufbitqmb k1, m8, m9\n mova m3, m6\n vpermb m3{k1}, m9, m5\n jmp .sec_main\nALIGN function_align\n.sec:\n vpaddd m2, m3, [base+cdef_dirs+(t0+4)*4] {1to16} ; dir + 2\n vpaddd m3, [base+cdef_dirs+(t0+0)*4] {1to16} ; dir - 2\n vpermb m2, m2, m5 ; k0s0 k0s1 k1s0 k1s1\n vpermb m3, m3, m5 ; k0s2 k0s3 k1s2 k1s3\n.sec_main:\n vpbroadcastd m8, [base+sec_tap]\n vpcmpub k1, m6, m2, 6\n psubb m4, m2, m6\n vpbroadcastb m12, t1d\n lzcnt t1d, t1d\n vpsubb m4{k1}, m6, m2\n vpcmpub k2, m6, m3, 6\n vpbroadcastq m11, [r3+t1*8]\n gf2p8affineqb m10, m4, m11, 0\n psubb m5, m3, m6\n mova m9, m8\n vpsubb m8{k1}, m7, m8\n psubusb m10, m12, m10\n vpsubb m5{k2}, m6, m3\n pminub m4, m10\n vpdpbusd m0, m4, m8\n gf2p8affineqb m11, m5, m11, 0\n vpsubb m9{k2}, m7, m9\n psubusb m12, m11\n pminub m5, m12\n vpdpbusd m0, m5, m9\n ret\n\n%endif ; ARCH_X86_64\n"},"old_contents":{"kind":"string","value":"; Copyright © 2018, VideoLAN and dav1d authors\n; Copyright © 2018, Two Orioles, LLC\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n;\n; 1. Redistributions of source code must retain the above copyright notice, this\n; list of conditions and the following disclaimer.\n;\n; 2. Redistributions in binary form must reproduce the above copyright notice,\n; this list of conditions and the following disclaimer in the documentation\n; and/or other materials provided with the distribution.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n%include \"ext/x86/x86inc.asm\"\n\n%if ARCH_X86_64\n\n%macro DUP4 1-*\n %rep %0\n times 4 db %1\n %rotate 1\n %endrep\n%endmacro\n\n%macro DIRS 16 ; cdef_directions[]\n %rep 4 + 16 + 4 ; 6 7 0 1 2 3 4 5 6 7 0 1\n ; masking away unused bits allows us to use a single vpaddd {1to16}\n ; instruction instead of having to do vpbroadcastd + paddb\n db %13 & 0x3f, -%13 & 0x3f\n %rotate 1\n %endrep\n%endmacro\n\n%macro JMP_TABLE 2-*\n %xdefine %1_jmptable %%table\n %xdefine %%base mangle(private_prefix %+ _%1_avx2)\n %%table:\n %rep %0 - 1\n dd %%base %+ .%2 - %%table\n %rotate 1\n %endrep\n%endmacro\n\n%macro CDEF_FILTER_JMP_TABLE 1\nJMP_TABLE cdef_filter_%1, \\\n d6k0, d6k1, d7k0, d7k1, \\\n d0k0, d0k1, d1k0, d1k1, d2k0, d2k1, d3k0, d3k1, \\\n d4k0, d4k1, d5k0, d5k1, d6k0, d6k1, d7k0, d7k1, \\\n d0k0, d0k1, d1k0, d1k1\n%endmacro\n\nSECTION_RODATA 64\n\nlut_perm_4x4: db 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79\n db 16, 17, 0, 1, 2, 3, 4, 5, 18, 19, 8, 9, 10, 11, 12, 13\n db 20, 21, 80, 81, 82, 83, 84, 85, 22, 23, 32, 33, 34, 35, 36, 37\n db 98, 99,100,101,102,103,104,105, 50, 51, 52, 53, 54, 55, 56, 57\nedge_mask: dq 0x00003c3c3c3c0000, 0x00003f3f3f3f0000 ; 0000, 0001\n dq 0x0000fcfcfcfc0000, 0x0000ffffffff0000 ; 0010, 0011\n dq 0x00003c3c3c3c3c3c, 0x00003f3f3f3f3f3f ; 0100, 0101\n dq 0x0000fcfcfcfcfcfc, 0x0000ffffffffffff ; 0110, 0111\n dq 0x3c3c3c3c3c3c0000, 0x3f3f3f3f3f3f0000 ; 1000, 1001\n dq 0xfcfcfcfcfcfc0000, 0xffffffffffff0000 ; 1010, 1011\n dq 0x3c3c3c3c3c3c3c3c, 0x3f3f3f3f3f3f3f3f ; 1100, 1101\n dq 0xfcfcfcfcfcfcfcfc, 0xffffffffffffffff ; 1110, 1111\npx_idx: DUP4 18, 19, 20, 21, 26, 27, 28, 29, 34, 35, 36, 37, 42, 43, 44, 45\ncdef_dirs: DIRS -7,-14, 1, -6, 1, 2, 1, 10, 9, 18, 8, 17, 8, 16, 8, 15\ngf_shr: dq 0x0102040810204080, 0x0102040810204080 ; >> 0, >> 0\n dq 0x0204081020408000, 0x0408102040800000 ; >> 1, >> 2\n dq 0x0810204080000000, 0x1020408000000000 ; >> 3, >> 4\n dq 0x2040800000000000, 0x4080000000000000 ; >> 5, >> 6\nend_perm: db 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61\npri_tap: db 64, 64, 32, 32, 48, 48, 48, 48 ; left-shifted by 4\nsec_tap: db 32, 32, 16, 16\npd_268435568: dd 268435568\nblend_4x4: dd 0x00, 0x80, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00\n dd 0x80, 0x00, 0x00\nblend_4x8_0: dd 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80\nblend_4x8_1: dd 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80\n dd 0x00, 0x00\nblend_4x8_2: dd 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080\n dd 0x0000\nblend_4x8_3: dd 0x0000, 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080\n dd 0x0000, 0x0000\nblend_8x8_0: dq 0x00, 0x00, 0x80, 0x80, 0x80, 0x80\nblend_8x8_1: dq 0x0000, 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x0000, 0x0000\npd_47130256: dd 4, 7, 1, 3, 0, 2, 5, 6\ndiv_table: dd 840, 420, 280, 210, 168, 140, 120, 105, 420, 210, 140, 105\nshufw_6543210x:db 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1, 14, 15\nshufb_lohi: db 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15\npw_128: times 2 dw 128\npw_2048: times 2 dw 2048\ntap_table: ; masks for 8 bit shifts\n db 0xFF, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01\n ; weights\n db 4, 2, 3, 3, 2, 1\n db -1 * 16 + 1, -2 * 16 + 2\n db 0 * 16 + 1, -1 * 16 + 2\n db 0 * 16 + 1, 0 * 16 + 2\n db 0 * 16 + 1, 1 * 16 + 2\n db 1 * 16 + 1, 2 * 16 + 2\n db 1 * 16 + 0, 2 * 16 + 1\n db 1 * 16 + 0, 2 * 16 + 0\n db 1 * 16 + 0, 2 * 16 - 1\n ; the last 6 are repeats of the first 6 so we don't need to & 7\n db -1 * 16 + 1, -2 * 16 + 2\n db 0 * 16 + 1, -1 * 16 + 2\n db 0 * 16 + 1, 0 * 16 + 2\n db 0 * 16 + 1, 1 * 16 + 2\n db 1 * 16 + 1, 2 * 16 + 2\n db 1 * 16 + 0, 2 * 16 + 1\n\nCDEF_FILTER_JMP_TABLE 4x4\nCDEF_FILTER_JMP_TABLE 4x8\nCDEF_FILTER_JMP_TABLE 8x8\n\nSECTION .text\n\n%macro PREP_REGS 2 ; w, h\n ; off1/2/3[k] [6 total] from [tapq+12+(dir+0/2/6)*2+k]\n mov dird, r6m\n lea tableq, [cdef_filter_%1x%2_jmptable]\n lea dirq, [tableq+dirq*2*4]\n%if %1 == 4\n %if %2 == 4\n DEFINE_ARGS dst, stride, left, top, pri, sec, \\\n table, dir, dirjmp, dst4, stride3, k\n %else\n DEFINE_ARGS dst, stride, left, top, pri, sec, \\\n table, dir, dirjmp, dst4, dst8, stride3, k\n lea dst8q, [dstq+strideq*8]\n %endif\n%else\n DEFINE_ARGS dst, stride, h, top1, pri, sec, \\\n table, dir, dirjmp, top2, dst4, stride3, k\n mov hq, -8\n lea top1q, [top1q+strideq*0]\n lea top2q, [top1q+strideq*1]\n%endif\n lea dst4q, [dstq+strideq*4]\n%if %1 == 4\n lea stride3q, [strideq*3]\n%endif\n%endmacro\n\n%macro LOAD_BLOCK 2-3 0 ; w, h, init_min_max\n mov kd, 1\n pxor m15, m15 ; sum\n%if %2 == 8\n pxor m12, m12\n %if %1 == 4\n movd xm4, [dstq +strideq*0]\n movd xm6, [dstq +strideq*1]\n movd xm5, [dstq +strideq*2]\n movd xm7, [dstq +stride3q ]\n vinserti128 m4, [dst4q+strideq*0], 1\n vinserti128 m6, [dst4q+strideq*1], 1\n vinserti128 m5, [dst4q+strideq*2], 1\n vinserti128 m7, [dst4q+stride3q ], 1\n punpckldq m4, m6\n punpckldq m5, m7\n %else\n movq xm4, [dstq+strideq*0]\n movq xm5, [dstq+strideq*1]\n vinserti128 m4, [dstq+strideq*2], 1\n vinserti128 m5, [dstq+stride3q ], 1\n %endif\n punpcklqdq m4, m5\n%else\n movd xm4, [dstq+strideq*0]\n movd xm5, [dstq+strideq*1]\n vinserti128 m4, [dstq+strideq*2], 1\n vinserti128 m5, [dstq+stride3q ], 1\n punpckldq m4, m5\n%endif\n%if %3 == 1\n mova m7, m4 ; min\n mova m8, m4 ; max\n%endif\n%endmacro\n\n%macro ACCUMULATE_TAP_BYTE 7-8 0 ; tap_offset, shift, mask, strength\n ; mul_tap, w, h, clip\n ; load p0/p1\n movsxd dirjmpq, [dirq+kq*4+%1*2*4]\n add dirjmpq, tableq\n call dirjmpq\n\n%if %8 == 1\n pmaxub m7, m5\n pminub m8, m5\n pmaxub m7, m6\n pminub m8, m6\n%endif\n\n ; accumulate sum[m15] over p0/p1\n%if %7 == 4\n punpcklbw m5, m6\n punpcklbw m6, m4, m4\n psubusb m9, m5, m6\n psubusb m5, m6, m5\n por m9, m5 ; abs_diff_p01(p01 - px)\n pcmpeqb m5, m9\n por m5, %5\n psignb m6, %5, m5\n psrlw m5, m9, %2 ; emulate 8-bit shift\n pand m5, %3\n psubusb m5, %4, m5\n pminub m5, m9\n pmaddubsw m5, m6\n paddw m15, m5\n%else\n psubusb m9, m5, m4\n psubusb m5, m4, m5\n psubusb m11, m6, m4\n psubusb m6, m4, m6\n por m9, m5 ; abs_diff_p0(p0 - px)\n por m11, m6 ; abs_diff_p1(p1 - px)\n pcmpeqb m5, m9\n pcmpeqb m6, m11\n punpckhbw m10, m9, m11\n punpcklbw m9, m11\n por m5, %5\n por m11, m6, %5\n punpckhbw m6, m5, m11\n punpcklbw m5, m11\n psignb m11, %5, m6\n psrlw m6, m10, %2 ; emulate 8-bit shift\n pand m6, %3\n psubusb m6, %4, m6\n pminub m6, m10\n pmaddubsw m6, m11\n paddw m12, m6\n psignb m11, %5, m5\n psrlw m5, m9, %2 ; emulate 8-bit shift\n pand m5, %3\n psubusb m5, %4, m5\n pminub m5, m9\n pmaddubsw m5, m11\n paddw m15, m5\n%endif\n%endmacro\n\n%macro ADJUST_PIXEL 4-5 0 ; w, h, zero, pw_2048, clip\n%if %2 == 4\n %if %5 == 1\n punpcklbw m4, %3\n %endif\n pcmpgtw %3, m15\n paddw m15, %3\n pmulhrsw m15, %4\n %if %5 == 0\n packsswb m15, m15\n paddb m4, m15\n %else\n paddw m4, m15\n packuswb m4, m4 ; clip px in [0x0,0xff]\n pminub m4, m7\n pmaxub m4, m8\n %endif\n vextracti128 xm5, m4, 1\n movd [dstq+strideq*0], xm4\n movd [dstq+strideq*2], xm5\n pextrd [dstq+strideq*1], xm4, 1\n pextrd [dstq+stride3q ], xm5, 1\n%else\n pcmpgtw m6, %3, m12\n pcmpgtw m5, %3, m15\n paddw m12, m6\n paddw m15, m5\n %if %5 == 1\n punpckhbw m5, m4, %3\n punpcklbw m4, %3\n %endif\n pmulhrsw m12, %4\n pmulhrsw m15, %4\n %if %5 == 0\n packsswb m15, m12\n paddb m4, m15\n %else\n paddw m5, m12\n paddw m4, m15\n packuswb m4, m5 ; clip px in [0x0,0xff]\n pminub m4, m7\n pmaxub m4, m8\n %endif\n vextracti128 xm5, m4, 1\n %if %1 == 4\n movd [dstq +strideq*0], xm4\n movd [dst4q+strideq*0], xm5\n pextrd [dstq +strideq*1], xm4, 1\n pextrd [dst4q+strideq*1], xm5, 1\n pextrd [dstq +strideq*2], xm4, 2\n pextrd [dst4q+strideq*2], xm5, 2\n pextrd [dstq +stride3q ], xm4, 3\n pextrd [dst4q+stride3q ], xm5, 3\n %else\n movq [dstq+strideq*0], xm4\n movq [dstq+strideq*2], xm5\n movhps [dstq+strideq*1], xm4\n movhps [dstq+stride3q ], xm5\n %endif\n%endif\n%endmacro\n\n%macro BORDER_PREP_REGS 2 ; w, h\n ; off1/2/3[k] [6 total] from [tapq+12+(dir+0/2/6)*2+k]\n mov dird, r6m\n lea dirq, [tableq+dirq*2+14]\n%if %1*%2*2/mmsize > 1\n %if %1 == 4\n DEFINE_ARGS dst, stride, dir, stk, pri, sec, stride3, h, off, k\n %else\n DEFINE_ARGS dst, stride, dir, stk, pri, sec, h, off, k\n %endif\n mov hd, %1*%2*2/mmsize\n%else\n DEFINE_ARGS dst, stride, dir, stk, pri, sec, stride3, off, k\n%endif\n lea stkq, [px]\n pxor m11, m11\n%endmacro\n\n%macro BORDER_LOAD_BLOCK 2-3 0 ; w, h, init_min_max\n mov kd, 1\n%if %1 == 4\n movq xm4, [stkq+32*0]\n movhps xm4, [stkq+32*1]\n movq xm5, [stkq+32*2]\n movhps xm5, [stkq+32*3]\n vinserti128 m4, xm5, 1\n%else\n mova xm4, [stkq+32*0] ; px\n vinserti128 m4, [stkq+32*1], 1\n%endif\n pxor m15, m15 ; sum\n%if %3 == 1\n mova m7, m4 ; max\n mova m8, m4 ; min\n%endif\n%endmacro\n\n%macro ACCUMULATE_TAP_WORD 6-7 0 ; tap_offset, shift, mask, strength\n ; mul_tap, w, clip\n ; load p0/p1\n movsx offq, byte [dirq+kq+%1] ; off1\n%if %6 == 4\n movq xm5, [stkq+offq*2+32*0] ; p0\n movq xm6, [stkq+offq*2+32*2]\n movhps xm5, [stkq+offq*2+32*1]\n movhps xm6, [stkq+offq*2+32*3]\n vinserti128 m5, xm6, 1\n%else\n movu xm5, [stkq+offq*2+32*0] ; p0\n vinserti128 m5, [stkq+offq*2+32*1], 1\n%endif\n neg offq ; -off1\n%if %6 == 4\n movq xm6, [stkq+offq*2+32*0] ; p1\n movq xm9, [stkq+offq*2+32*2]\n movhps xm6, [stkq+offq*2+32*1]\n movhps xm9, [stkq+offq*2+32*3]\n vinserti128 m6, xm9, 1\n%else\n movu xm6, [stkq+offq*2+32*0] ; p1\n vinserti128 m6, [stkq+offq*2+32*1], 1\n%endif\n%if %7 == 1\n ; out of bounds values are set to a value that is a both a large unsigned\n ; value and a negative signed value.\n ; use signed max and unsigned min to remove them\n pmaxsw m7, m5 ; max after p0\n pminuw m8, m5 ; min after p0\n pmaxsw m7, m6 ; max after p1\n pminuw m8, m6 ; min after p1\n%endif\n\n ; accumulate sum[m15] over p0/p1\n ; calculate difference before converting\n psubw m5, m4 ; diff_p0(p0 - px)\n psubw m6, m4 ; diff_p1(p1 - px)\n\n ; convert to 8-bits with signed saturation\n ; saturating to large diffs has no impact on the results\n packsswb m5, m6\n\n ; group into pairs so we can accumulate using maddubsw\n pshufb m5, m12\n pabsb m9, m5\n psignb m10, %5, m5\n psrlw m5, m9, %2 ; emulate 8-bit shift\n pand m5, %3\n psubusb m5, %4, m5\n\n ; use unsigned min since abs diff can equal 0x80\n pminub m5, m9\n pmaddubsw m5, m10\n paddw m15, m5\n%endmacro\n\n%macro BORDER_ADJUST_PIXEL 2-3 0 ; w, pw_2048, clip\n pcmpgtw m9, m11, m15\n paddw m15, m9\n pmulhrsw m15, %2\n paddw m4, m15\n%if %3 == 1\n pminsw m4, m7\n pmaxsw m4, m8\n%endif\n packuswb m4, m4\n vextracti128 xm5, m4, 1\n%if %1 == 4\n movd [dstq+strideq*0], xm4\n pextrd [dstq+strideq*1], xm4, 1\n movd [dstq+strideq*2], xm5\n pextrd [dstq+stride3q], xm5, 1\n%else\n movq [dstq+strideq*0], xm4\n movq [dstq+strideq*1], xm5\n%endif\n%endmacro\n\n%macro CDEF_FILTER 2 ; w, h\nINIT_YMM avx2\ncglobal cdef_filter_%1x%2, 4, 9, 0, dst, stride, left, top, \\\n pri, sec, dir, damping, edge\n%assign stack_offset_entry stack_offset\n mov edged, edgem\n cmp edged, 0xf\n jne .border_block\n\n PUSH r9\n PUSH r10\n PUSH r11\n%if %2 == 4\n %assign regs_used 12\n %if WIN64\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n %endif\n ALLOC_STACK 0x60, 16\n pmovzxbw xm0, [leftq+1]\n vpermq m0, m0, q0110\n psrldq m1, m0, 4\n vpalignr m2, m0, m0, 12\n movu [rsp+0x10], m0\n movu [rsp+0x28], m1\n movu [rsp+0x40], m2\n%else\n PUSH r12\n %if %1 == 4\n %assign regs_used 13\n %if WIN64\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n %endif\n ALLOC_STACK 8*2+%1*%2*1, 16\n pmovzxwd m0, [leftq]\n mova [rsp+0x10], m0\n %else\n PUSH r13\n %assign regs_used 14\n %if WIN64\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n %endif\n ALLOC_STACK 8*2+%1*%2*2+32, 16\n lea r11, [strideq*3]\n movu xm4, [dstq+strideq*2]\n pmovzxwq m0, [leftq+0]\n pmovzxwq m1, [leftq+8]\n vinserti128 m4, [dstq+r11], 1\n pmovzxbd m2, [leftq+1]\n pmovzxbd m3, [leftq+9]\n mova [rsp+0x10], m0\n mova [rsp+0x30], m1\n mova [rsp+0x50], m2\n mova [rsp+0x70], m3\n mova [rsp+0x90], m4\n %endif\n%endif\n\n DEFINE_ARGS dst, stride, left, top, pri, secdmp, zero, pridmp, damping\n mov dampingd, r7m\n xor zerod, zerod\n movifnidn prid, prim\n sub dampingd, 31\n movifnidn secdmpd, secdmpm\n or prid, 0\n jz .sec_only\n movd xm0, prid\n lzcnt pridmpd, prid\n add pridmpd, dampingd\n cmovs pridmpd, zerod\n mov [rsp+0], pridmpq ; pri_shift\n or secdmpd, 0\n jz .pri_only\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n\n DEFINE_ARGS dst, stride, left, top, pri, secdmp, table, pridmp\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, left, top, pri, sec, table, dir\n vpbroadcastb m0, xm0 ; pri_strength\n vpbroadcastb m1, xm1 ; sec_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n lea secq, [tableq+12] ; sec_taps\n\n PREP_REGS %1, %2\n%if %1*%2 > mmsize\n.v_loop:\n%endif\n LOAD_BLOCK %1, %2, 1\n.k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_BYTE 2, [rsp+0], m13, m0, m2, %1, %2, 1 ; dir + 0\n ACCUMULATE_TAP_BYTE 4, [rsp+8], m14, m1, m3, %1, %2, 1 ; dir + 2\n ACCUMULATE_TAP_BYTE 0, [rsp+8], m14, m1, m3, %1, %2, 1 ; dir - 2\n dec kq\n jge .k_loop\n\n vpbroadcastd m10, [pw_2048]\n pxor m9, m9\n ADJUST_PIXEL %1, %2, m9, m10, 1\n%if %1*%2 > mmsize\n mov dstq, dst4q\n lea top1q, [rsp+0x90]\n lea top2q, [rsp+0xA0]\n lea dst4q, [dst4q+strideq*4]\n add hq, 4\n jl .v_loop\n%endif\n RET\n\n.pri_only:\n DEFINE_ARGS dst, stride, left, top, pri, _, table, pridmp\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, left, top, pri, _, table, dir\n vpbroadcastb m0, xm0 ; pri_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n PREP_REGS %1, %2\n vpbroadcastd m3, [pw_2048]\n pxor m1, m1\n%if %1*%2 > mmsize\n.pri_v_loop:\n%endif\n LOAD_BLOCK %1, %2\n.pri_k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n ACCUMULATE_TAP_BYTE 2, [rsp+0], m13, m0, m2, %1, %2 ; dir + 0\n dec kq\n jge .pri_k_loop\n ADJUST_PIXEL %1, %2, m1, m3\n%if %1*%2 > mmsize\n mov dstq, dst4q\n lea top1q, [rsp+0x90]\n lea top2q, [rsp+0xA0]\n lea dst4q, [dst4q+strideq*4]\n add hq, 4\n jl .pri_v_loop\n%endif\n RET\n\n.sec_only:\n DEFINE_ARGS dst, stride, left, top, _, secdmp, zero, _, damping\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n DEFINE_ARGS dst, stride, left, top, _, secdmp, table\n lea tableq, [tap_table]\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, left, top, _, sec, table, dir\n vpbroadcastb m1, xm1 ; sec_strength\n lea secq, [tableq+12] ; sec_taps\n PREP_REGS %1, %2\n vpbroadcastd m2, [pw_2048]\n pxor m0, m0\n%if %1*%2 > mmsize\n.sec_v_loop:\n%endif\n LOAD_BLOCK %1, %2\n.sec_k_loop:\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_BYTE 4, [rsp+8], m14, m1, m3, %1, %2 ; dir + 2\n ACCUMULATE_TAP_BYTE 0, [rsp+8], m14, m1, m3, %1, %2 ; dir - 2\n dec kq\n jge .sec_k_loop\n ADJUST_PIXEL %1, %2, m0, m2\n%if %1*%2 > mmsize\n mov dstq, dst4q\n lea top1q, [rsp+0x90]\n lea top2q, [rsp+0xA0]\n lea dst4q, [dst4q+strideq*4]\n add hq, 4\n jl .sec_v_loop\n%endif\n RET\n\n.d0k0:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m6, [dstq+strideq*1-1]\n vpbroadcastq m10, [dstq+strideq*2-1]\n movd xm5, [topq+strideq*1+1]\n movd xm9, [dstq+strideq*0+1]\n psrldq m11, m6, 2\n psrldq m12, m10, 2\n vinserti128 m6, [dstq+stride3q -1], 1\n vinserti128 m10, [dstq+strideq*4-1], 1\n vpblendd m5, m11, 0x10\n vpblendd m9, m12, 0x10\n movu m11, [blend_4x4+16]\n punpckldq m6, m10\n punpckldq m5, m9\n vpblendvb m6, [rsp+gprsize+0x28], m11\n %else\n movd xm5, [topq +strideq*1+1]\n movq xm6, [dstq +strideq*1-1]\n movq xm10, [dstq +stride3q -1]\n movq xm11, [dst4q+strideq*1-1]\n pinsrd xm5, [dstq +strideq*0+1], 1\n movhps xm6, [dstq +strideq*2-1]\n movhps xm10, [dst4q+strideq*0-1]\n movhps xm11, [dst4q+strideq*2-1]\n psrldq xm9, xm6, 2\n shufps xm5, xm9, q2010 ; -1 +0 +1 +2\n shufps xm6, xm10, q2020 ; +1 +2 +3 +4\n psrldq xm9, xm11, 2\n psrldq xm10, 2\n shufps xm10, xm9, q2020 ; +3 +4 +5 +6\n movd xm9, [dst4q+stride3q -1]\n pinsrd xm9, [dst4q+strideq*4-1], 1\n shufps xm11, xm9, q1020 ; +5 +6 +7 +8\n pmovzxbw m9, [leftq+3]\n vinserti128 m6, xm11, 1\n movu m11, [blend_4x8_0+4]\n vinserti128 m5, xm10, 1\n vpblendvb m6, m9, m11\n %endif\n%else\n lea r13, [blend_8x8_0+16]\n movq xm5, [top2q +1]\n vbroadcasti128 m10, [dstq+strideq*1-1]\n vbroadcasti128 m11, [dstq+strideq*2-1]\n movhps xm5, [dstq+strideq*0+1]\n vinserti128 m6, m10, [dstq+stride3q -1], 1\n vinserti128 m9, m11, [dstq+strideq*4-1], 1\n psrldq m10, 2\n psrldq m11, 2\n punpcklqdq m6, m9\n movu m9, [r13+hq*2*1+16*1]\n punpcklqdq m10, m11\n vpblendd m5, m10, 0xF0\n vpblendvb m6, [rsp+gprsize+80+hq*8+64+8*1], m9\n%endif\n ret\n.d1k0:\n.d2k0:\n.d3k0:\n%if %1 == 4\n %if %2 == 4\n movq xm6, [dstq+strideq*0-1]\n movq xm9, [dstq+strideq*1-1]\n vinserti128 m6, [dstq+strideq*2-1], 1\n vinserti128 m9, [dstq+stride3q -1], 1\n movu m11, [rsp+gprsize+0x10]\n pcmpeqd m12, m12\n psrldq m5, m6, 2\n psrldq m10, m9, 2\n psrld m12, 24\n punpckldq m6, m9\n punpckldq m5, m10\n vpblendvb m6, m11, m12\n %else\n movq xm6, [dstq +strideq*0-1]\n movq xm9, [dstq +strideq*2-1]\n movhps xm6, [dstq +strideq*1-1]\n movhps xm9, [dstq +stride3q -1]\n movq xm10, [dst4q+strideq*0-1]\n movhps xm10, [dst4q+strideq*1-1]\n psrldq xm5, xm6, 2\n psrldq xm11, xm9, 2\n shufps xm5, xm11, q2020\n movq xm11, [dst4q+strideq*2-1]\n movhps xm11, [dst4q+stride3q -1]\n shufps xm6, xm9, q2020\n shufps xm9, xm10, xm11, q2020\n vinserti128 m6, xm9, 1\n pmovzxbw m9, [leftq+1]\n psrldq xm10, 2\n psrldq xm11, 2\n shufps xm10, xm11, q2020\n vpbroadcastd m11, [blend_4x8_0+4]\n vinserti128 m5, xm10, 1\n vpblendvb m6, m9, m11\n %endif\n%else\n movu xm5, [dstq+strideq*0-1]\n movu xm9, [dstq+strideq*1-1]\n vinserti128 m5, [dstq+strideq*2-1], 1\n vinserti128 m9, [dstq+stride3q -1], 1\n mova m10, [blend_8x8_0+16]\n punpcklqdq m6, m5, m9\n vpblendvb m6, [rsp+gprsize+80+hq*8+64], m10\n psrldq m5, 2\n psrldq m9, 2\n punpcklqdq m5, m9\n%endif\n ret\n.d4k0:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m10, [dstq+strideq*1-1]\n vpbroadcastq m11, [dstq+strideq*2-1]\n movd xm6, [topq+strideq*1-1]\n movd xm9, [dstq+strideq*0-1]\n psrldq m5, m10, 2\n psrldq m12, m11, 2\n vpblendd m6, m10, 0x10\n vpblendd m9, m11, 0x10\n movu m10, [blend_4x4]\n vinserti128 m5, [dstq+stride3q +1], 1\n vinserti128 m12, [dstq+strideq*4+1], 1\n punpckldq m6, m9\n punpckldq m5, m12\n vpblendvb m6, [rsp+gprsize+0x40], m10\n %else\n movd xm6, [topq +strideq*1-1]\n movq xm9, [dstq +strideq*1-1]\n movq xm10, [dstq +stride3q -1]\n movq xm11, [dst4q+strideq*1-1]\n pinsrd xm6, [dstq +strideq*0-1], 1\n movhps xm9, [dstq +strideq*2-1]\n movhps xm10, [dst4q+strideq*0-1]\n movhps xm11, [dst4q+strideq*2-1]\n psrldq xm5, xm9, 2\n shufps xm6, xm9, q2010\n psrldq xm9, xm10, 2\n shufps xm5, xm9, q2020\n shufps xm10, xm11, q2020\n movd xm9, [dst4q+stride3q +1]\n vinserti128 m6, xm10, 1\n pinsrd xm9, [dst4q+strideq*4+1], 1\n psrldq xm11, 2\n pmovzxbw m10, [leftq-1]\n shufps xm11, xm9, q1020\n movu m9, [blend_4x8_0]\n vinserti128 m5, xm11, 1\n vpblendvb m6, m10, m9\n %endif\n%else\n lea r13, [blend_8x8_0+8]\n movq xm6, [top2q -1]\n vbroadcasti128 m5, [dstq+strideq*1-1]\n vbroadcasti128 m9, [dstq+strideq*2-1]\n movhps xm6, [dstq+strideq*0-1]\n movu m11, [r13+hq*2*1+16*1]\n punpcklqdq m10, m5, m9\n vinserti128 m5, [dstq+stride3q -1], 1\n vinserti128 m9, [dstq+strideq*4-1], 1\n vpblendd m6, m10, 0xF0\n vpblendvb m6, [rsp+gprsize+80+hq*8+64-8*1], m11\n psrldq m5, 2\n psrldq m9, 2\n punpcklqdq m5, m9\n%endif\n ret\n.d5k0:\n.d6k0:\n.d7k0:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [topq+strideq*1 ]\n vpbroadcastd m5, [dstq+strideq*1 ]\n vpbroadcastd m9, [dstq+strideq*2 ]\n vpblendd xm6, [dstq+strideq*0-4], 0x2\n vpblendd m5, m9, 0x22\n vpblendd m6, m5, 0x30\n vinserti128 m5, [dstq+stride3q ], 1\n vpblendd m5, [dstq+strideq*4-20], 0x20\n %else\n movd xm6, [topq +strideq*1]\n movd xm5, [dstq +strideq*1]\n movd xm9, [dstq +stride3q ]\n movd xm10, [dst4q+strideq*1]\n movd xm11, [dst4q+stride3q ]\n pinsrd xm6, [dstq +strideq*0], 1\n pinsrd xm5, [dstq +strideq*2], 1\n pinsrd xm9, [dst4q+strideq*0], 1\n pinsrd xm10, [dst4q+strideq*2], 1\n pinsrd xm11, [dst4q+strideq*4], 1\n punpcklqdq xm6, xm5\n punpcklqdq xm5, xm9\n punpcklqdq xm9, xm10\n punpcklqdq xm10, xm11\n vinserti128 m6, xm9, 1\n vinserti128 m5, xm10, 1\n %endif\n%else\n movq xm6, [top2q ]\n movq xm5, [dstq+strideq*1]\n movq xm9, [dstq+stride3q ]\n movhps xm6, [dstq+strideq*0]\n movhps xm5, [dstq+strideq*2]\n movhps xm9, [dstq+strideq*4]\n vinserti128 m6, xm5, 1\n vinserti128 m5, xm9, 1\n%endif\n ret\n.d0k1:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [dstq +strideq*2-2]\n movd xm9, [dstq +stride3q -2]\n movd xm5, [topq +strideq*0+2]\n movd xm10, [topq +strideq*1+2]\n pinsrw xm6, [leftq+4], 0\n pinsrw xm9, [leftq+6], 0\n vinserti128 m5, [dstq +strideq*0+2], 1\n vinserti128 m10, [dstq +strideq*1+2], 1\n vinserti128 m6, [dst4q+strideq*0-2], 1\n vinserti128 m9, [dst4q+strideq*1-2], 1\n punpckldq m5, m10\n punpckldq m6, m9\n %else\n movq xm6, [dstq +strideq*2-2]\n movd xm10, [dst4q+strideq*2-2]\n movd xm5, [topq +strideq*0+2]\n movq xm9, [dst4q+strideq*0-2]\n movhps xm6, [dstq +stride3q -2]\n pinsrw xm10, [dst4q+stride3q ], 3\n pinsrd xm5, [topq +strideq*1+2], 1\n movhps xm9, [dst4q+strideq*1-2]\n pinsrd xm10, [dst8q+strideq*0-2], 2\n pinsrd xm5, [dstq +strideq*0+2], 2\n pinsrd xm10, [dst8q+strideq*1-2], 3\n pinsrd xm5, [dstq +strideq*1+2], 3\n shufps xm11, xm6, xm9, q3131\n shufps xm6, xm9, q2020\n movu m9, [blend_4x8_3+8]\n vinserti128 m6, xm10, 1\n vinserti128 m5, xm11, 1\n vpblendvb m6, [rsp+gprsize+16+8], m9\n %endif\n%else\n lea r13, [blend_8x8_1+16]\n movq xm6, [dstq +strideq*2-2]\n movq xm9, [dstq +stride3q -2]\n movq xm5, [top1q +2]\n movq xm10, [top2q +2]\n movu m11, [r13+hq*2*2+16*2]\n vinserti128 m6, [dst4q+strideq*0-2], 1\n vinserti128 m9, [dst4q+strideq*1-2], 1\n vinserti128 m5, [dstq +strideq*0+2], 1\n vinserti128 m10, [dstq +strideq*1+2], 1\n punpcklqdq m6, m9\n punpcklqdq m5, m10\n vpblendvb m6, [rsp+gprsize+16+hq*8+64+8*2], m11\n%endif\n ret\n.d1k1:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m6, [dstq+strideq*1-2]\n vpbroadcastq m9, [dstq+strideq*2-2]\n movd xm5, [topq+strideq*1+2]\n movd xm10, [dstq+strideq*0+2]\n psrldq m11, m6, 4\n psrldq m12, m9, 4\n vpblendd m5, m11, 0x10\n movq xm11, [leftq+2]\n vinserti128 m6, [dstq+stride3q -2], 1\n punpckldq xm11, xm11\n vpblendd m10, m12, 0x10\n pcmpeqd m12, m12\n pmovzxwd m11, xm11\n psrld m12, 16\n punpckldq m6, m9\n vpbroadcastd m9, [dstq+strideq*4-2]\n vpblendvb m6, m11, m12\n punpckldq m5, m10\n vpblendd m6, m9, 0x20\n %else\n movd xm5, [topq +strideq*1+2]\n movq xm6, [dstq +strideq*1-2]\n movq xm9, [dstq +stride3q -2]\n movq xm10, [dst4q+strideq*1-2]\n movd xm11, [dst4q+stride3q -2]\n pinsrd xm5, [dstq +strideq*0+2], 1\n movhps xm6, [dstq +strideq*2-2]\n movhps xm9, [dst4q+strideq*0-2]\n movhps xm10, [dst4q+strideq*2-2]\n pinsrd xm11, [dst4q+strideq*4-2], 1\n shufps xm5, xm6, q3110\n shufps xm6, xm9, q2020\n shufps xm9, xm10, q3131\n shufps xm10, xm11, q1020\n movu m11, [blend_4x8_2+4]\n vinserti128 m6, xm10, 1\n vinserti128 m5, xm9, 1\n vpblendvb m6, [rsp+gprsize+16+4], m11\n %endif\n%else\n lea r13, [blend_8x8_1+16]\n movq xm5, [top2q +2]\n vbroadcasti128 m6, [dstq+strideq*1-2]\n vbroadcasti128 m9, [dstq+strideq*2-2]\n movhps xm5, [dstq+strideq*0+2]\n shufps m10, m6, m9, q2121\n vinserti128 m6, [dstq+stride3q -2], 1\n vinserti128 m9, [dstq+strideq*4-2], 1\n movu m11, [r13+hq*2*1+16*1]\n vpblendd m5, m10, 0xF0\n punpcklqdq m6, m9\n vpblendvb m6, [rsp+gprsize+16+hq*8+64+8*1], m11\n%endif\n ret\n.d2k1:\n%if %1 == 4\n %if %2 == 4\n movq xm11, [leftq]\n movq xm6, [dstq+strideq*0-2]\n movq xm9, [dstq+strideq*1-2]\n vinserti128 m6, [dstq+strideq*2-2], 1\n vinserti128 m9, [dstq+stride3q -2], 1\n punpckldq xm11, xm11\n psrldq m5, m6, 4\n psrldq m10, m9, 4\n pmovzxwd m11, xm11\n punpckldq m6, m9\n punpckldq m5, m10\n pblendw m6, m11, 0x05\n %else\n movq xm5, [dstq +strideq*0-2]\n movq xm9, [dstq +strideq*2-2]\n movq xm10, [dst4q+strideq*0-2]\n movq xm11, [dst4q+strideq*2-2]\n movhps xm5, [dstq +strideq*1-2]\n movhps xm9, [dstq +stride3q -2]\n movhps xm10, [dst4q+strideq*1-2]\n movhps xm11, [dst4q+stride3q -2]\n shufps xm6, xm5, xm9, q2020\n shufps xm5, xm9, q3131\n shufps xm9, xm10, xm11, q2020\n shufps xm10, xm11, q3131\n pmovzxwd m11, [leftq]\n vinserti128 m6, xm9, 1\n vinserti128 m5, xm10, 1\n pblendw m6, m11, 0x55\n %endif\n%else\n mova m11, [rsp+gprsize+16+hq*8+64]\n movu xm5, [dstq+strideq*0-2]\n movu xm9, [dstq+strideq*1-2]\n vinserti128 m5, [dstq+strideq*2-2], 1\n vinserti128 m9, [dstq+stride3q -2], 1\n shufps m6, m5, m9, q1010\n shufps m5, m9, q2121\n pblendw m6, m11, 0x11\n%endif\n ret\n.d3k1:\n%if %1 == 4\n %if %2 == 4\n vpbroadcastq m11, [dstq+strideq*1-2]\n vpbroadcastq m12, [dstq+strideq*2-2]\n movd xm6, [topq+strideq*1-2]\n movd xm9, [dstq+strideq*0-2]\n pblendw m11, [leftq-16+2], 0x01\n pblendw m12, [leftq-16+4], 0x01\n pinsrw xm9, [leftq- 0+0], 0\n psrldq m5, m11, 4\n psrldq m10, m12, 4\n vinserti128 m5, [dstq+stride3q +2], 1\n vinserti128 m10, [dstq+strideq*4+2], 1\n vpblendd m6, m11, 0x10\n vpblendd m9, m12, 0x10\n punpckldq m6, m9\n punpckldq m5, m10\n %else\n movd xm6, [topq +strideq*1-2]\n movq xm5, [dstq +strideq*1-2]\n movq xm9, [dstq +stride3q -2]\n movq xm10, [dst4q+strideq*1-2]\n movd xm11, [dst4q+stride3q +2]\n pinsrw xm6, [dstq +strideq*0 ], 3\n movhps xm5, [dstq +strideq*2-2]\n movhps xm9, [dst4q+strideq*0-2]\n movhps xm10, [dst4q+strideq*2-2]\n pinsrd xm11, [dst4q+strideq*4+2], 1\n shufps xm6, xm5, q2010\n shufps xm5, xm9, q3131\n shufps xm9, xm10, q2020\n shufps xm10, xm11, q1031\n movu m11, [blend_4x8_2]\n vinserti128 m6, xm9, 1\n vinserti128 m5, xm10, 1\n vpblendvb m6, [rsp+gprsize+16-4], m11\n %endif\n%else\n lea r13, [blend_8x8_1+8]\n movq xm6, [top2q -2]\n vbroadcasti128 m5, [dstq+strideq*1-2]\n vbroadcasti128 m10, [dstq+strideq*2-2]\n movhps xm6, [dstq+strideq*0-2]\n punpcklqdq m9, m5, m10\n vinserti128 m5, [dstq+stride3q -2], 1\n vinserti128 m10, [dstq+strideq*4-2], 1\n movu m11, [r13+hq*2*1+16*1]\n vpblendd m6, m9, 0xF0\n shufps m5, m10, q2121\n vpblendvb m6, [rsp+gprsize+16+hq*8+64-8*1], m11\n%endif\n ret\n.d4k1:\n%if %1 == 4\n %if %2 == 4\n vinserti128 m6, [dstq +strideq*0-2], 1\n vinserti128 m9, [dstq +strideq*1-2], 1\n movd xm5, [dstq +strideq*2+2]\n movd xm10, [dstq +stride3q +2]\n pblendw m6, [leftq-16+0], 0x01\n pblendw m9, [leftq-16+2], 0x01\n vinserti128 m5, [dst4q+strideq*0+2], 1\n vinserti128 m10, [dst4q+strideq*1+2], 1\n vpblendd m6, [topq +strideq*0-2], 0x01\n vpblendd m9, [topq +strideq*1-2], 0x01\n punpckldq m5, m10\n punpckldq m6, m9\n %else\n movd xm6, [topq +strideq*0-2]\n movq xm5, [dstq +strideq*2-2]\n movq xm9, [dst4q+strideq*0-2]\n movd xm10, [dst4q+strideq*2+2]\n pinsrd xm6, [topq +strideq*1-2], 1\n movhps xm5, [dstq +stride3q -2]\n movhps xm9, [dst4q+strideq*1-2]\n pinsrd xm10, [dst4q+stride3q +2], 1\n pinsrd xm6, [dstq +strideq*0-2], 2\n pinsrd xm10, [dst8q+strideq*0+2], 2\n pinsrd xm6, [dstq +strideq*1-2], 3\n pinsrd xm10, [dst8q+strideq*1+2], 3\n shufps xm11, xm5, xm9, q2020\n shufps xm5, xm9, q3131\n movu m9, [blend_4x8_3]\n vinserti128 m6, xm11, 1\n vinserti128 m5, xm10, 1\n vpblendvb m6, [rsp+gprsize+16-8], m9\n %endif\n%else\n lea r13, [blend_8x8_1]\n movu m11, [r13+hq*2*2+16*2]\n movq xm6, [top1q -2]\n movq xm9, [top2q -2]\n movq xm5, [dstq +strideq*2+2]\n movq xm10, [dstq +stride3q +2]\n vinserti128 m6, [dstq +strideq*0-2], 1\n vinserti128 m9, [dstq +strideq*1-2], 1\n vinserti128 m5, [dst4q+strideq*0+2], 1\n vinserti128 m10, [dst4q+strideq*1+2], 1\n punpcklqdq m6, m9\n vpblendvb m6, [rsp+gprsize+16+hq*8+64-8*2], m11\n punpcklqdq m5, m10\n%endif\n ret\n.d5k1:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [topq +strideq*0-1]\n movd xm9, [topq +strideq*1-1]\n movd xm5, [dstq +strideq*2+1]\n movd xm10, [dstq +stride3q +1]\n pcmpeqd m12, m12\n pmovzxbw m11, [leftq-8+1]\n psrld m12, 24\n vinserti128 m6, [dstq +strideq*0-1], 1\n vinserti128 m9, [dstq +strideq*1-1], 1\n vinserti128 m5, [dst4q+strideq*0+1], 1\n vinserti128 m10, [dst4q+strideq*1+1], 1\n punpckldq m6, m9\n pxor m9, m9\n vpblendd m12, m9, 0x0F\n punpckldq m5, m10\n vpblendvb m6, m11, m12\n %else\n movd xm6, [topq +strideq*0-1]\n movq xm5, [dstq +strideq*2-1]\n movq xm9, [dst4q+strideq*0-1]\n movd xm10, [dst4q+strideq*2+1]\n pinsrd xm6, [topq +strideq*1-1], 1\n movhps xm5, [dstq +stride3q -1]\n movhps xm9, [dst4q+strideq*1-1]\n pinsrd xm10, [dst4q+stride3q +1], 1\n pinsrd xm6, [dstq +strideq*0-1], 2\n pinsrd xm10, [dst8q+strideq*0+1], 2\n pinsrd xm6, [dstq +strideq*1-1], 3\n pinsrd xm10, [dst8q+strideq*1+1], 3\n shufps xm11, xm5, xm9, q2020\n vinserti128 m6, xm11, 1\n pmovzxbw m11, [leftq-3]\n psrldq xm5, 2\n psrldq xm9, 2\n shufps xm5, xm9, q2020\n movu m9, [blend_4x8_1]\n vinserti128 m5, xm10, 1\n vpblendvb m6, m11, m9\n %endif\n%else\n lea r13, [blend_8x8_0]\n movu m11, [r13+hq*2*2+16*2]\n movq xm6, [top1q -1]\n movq xm9, [top2q -1]\n movq xm5, [dstq +strideq*2+1]\n movq xm10, [dstq +stride3q +1]\n vinserti128 m6, [dstq +strideq*0-1], 1\n vinserti128 m9, [dstq +strideq*1-1], 1\n vinserti128 m5, [dst4q+strideq*0+1], 1\n vinserti128 m10, [dst4q+strideq*1+1], 1\n punpcklqdq m6, m9\n punpcklqdq m5, m10\n vpblendvb m6, [rsp+gprsize+80+hq*8+64-8*2], m11\n%endif\n ret\n.d6k1:\n%if %1 == 4\n %if %2 == 4\n movd xm6, [topq +strideq*0]\n movd xm9, [topq +strideq*1]\n movd xm5, [dstq +strideq*2]\n movd xm10, [dstq +stride3q ]\n vinserti128 m6, [dstq +strideq*0], 1\n vinserti128 m9, [dstq +strideq*1], 1\n vinserti128 m5, [dst4q+strideq*0], 1\n vinserti128 m10, [dst4q+strideq*1], 1\n punpckldq m6, m9\n punpckldq m5, m10\n %else\n movd xm5, [dstq +strideq*2]\n movd xm6, [topq +strideq*0]\n movd xm9, [dst4q+strideq*2]\n pinsrd xm5, [dstq +stride3q ], 1\n pinsrd xm6, [topq +strideq*1], 1\n pinsrd xm9, [dst4q+stride3q ], 1\n pinsrd xm5, [dst4q+strideq*0], 2\n pinsrd xm6, [dstq +strideq*0], 2\n pinsrd xm9, [dst8q+strideq*0], 2\n pinsrd xm5, [dst4q+strideq*1], 3\n pinsrd xm6, [dstq +strideq*1], 3\n pinsrd xm9, [dst8q+strideq*1], 3\n vinserti128 m6, xm5, 1\n vinserti128 m5, xm9, 1\n %endif\n%else\n movq xm5, [dstq +strideq*2]\n movq xm9, [dst4q+strideq*0]\n movq xm6, [top1q ]\n movq xm10, [dstq +strideq*0]\n movhps xm5, [dstq +stride3q ]\n movhps xm9, [dst4q+strideq*1]\n movhps xm6, [top2q ]\n movhps xm10, [dstq +strideq*1]\n vinserti128 m5, xm9, 1\n vinserti128 m6, xm10, 1\n%endif\n ret\n.d7k1:\n%if %1 == 4\n %if %2 == 4\n movd xm5, [dstq +strideq*2-1]\n movd xm9, [dstq +stride3q -1]\n movd xm6, [topq +strideq*0+1]\n movd xm10, [topq +strideq*1+1]\n pinsrb xm5, [leftq+ 5], 0\n pinsrb xm9, [leftq+ 7], 0\n vinserti128 m6, [dstq +strideq*0+1], 1\n vinserti128 m10, [dstq +strideq*1+1], 1\n vinserti128 m5, [dst4q+strideq*0-1], 1\n vinserti128 m9, [dst4q+strideq*1-1], 1\n punpckldq m6, m10\n punpckldq m5, m9\n %else\n movd xm6, [topq +strideq*0+1]\n movq xm9, [dstq +strideq*2-1]\n movq xm10, [dst4q+strideq*0-1]\n movd xm11, [dst4q+strideq*2-1]\n pinsrd xm6, [topq +strideq*1+1], 1\n movhps xm9, [dstq +stride3q -1]\n movhps xm10, [dst4q+strideq*1-1]\n pinsrd xm11, [dst4q+stride3q -1], 1\n pinsrd xm6, [dstq +strideq*0+1], 2\n pinsrd xm11, [dst8q+strideq*0-1], 2\n pinsrd xm6, [dstq +strideq*1+1], 3\n pinsrd xm11, [dst8q+strideq*1-1], 3\n shufps xm5, xm9, xm10, q2020\n vinserti128 m5, xm11, 1\n pmovzxbw m11, [leftq+5]\n psrldq xm9, 2\n psrldq xm10, 2\n shufps xm9, xm10, q2020\n movu m10, [blend_4x8_1+8]\n vinserti128 m6, xm9, 1\n vpblendvb m5, m11, m10\n %endif\n%else\n lea r13, [blend_8x8_0+16]\n movq xm5, [dstq +strideq*2-1]\n movq xm9, [dst4q+strideq*0-1]\n movq xm6, [top1q +1]\n movq xm10, [dstq +strideq*0+1]\n movhps xm5, [dstq +stride3q -1]\n movhps xm9, [dst4q+strideq*1-1]\n movhps xm6, [top2q +1]\n movhps xm10, [dstq +strideq*1+1]\n movu m11, [r13+hq*2*2+16*2]\n vinserti128 m5, xm9, 1\n vinserti128 m6, xm10, 1\n vpblendvb m5, [rsp+gprsize+80+hq*8+64+8*2], m11\n%endif\n ret\n\n.border_block:\n DEFINE_ARGS dst, stride, left, top, pri, sec, stride3, dst4, edge\n%define rstk rsp\n%assign stack_offset stack_offset_entry\n%if %1 == 4 && %2 == 8\n PUSH r9\n %assign regs_used 10\n%else\n %assign regs_used 9\n%endif\n%if WIN64\n PUSH r%+regs_used\n %assign regs_used regs_used+1\n%endif\n ALLOC_STACK 2*16+(%2+4)*32, 16\n%define px rsp+2*16+2*32\n\n pcmpeqw m14, m14\n psllw m14, 15 ; 0x8000\n\n ; prepare pixel buffers - body/right\n%if %1 == 4\n INIT_XMM avx2\n%endif\n%if %2 == 8\n lea dst4q, [dstq+strideq*4]\n%endif\n lea stride3q, [strideq*3]\n test edgeb, 2 ; have_right\n jz .no_right\n pmovzxbw m1, [dstq+strideq*0]\n pmovzxbw m2, [dstq+strideq*1]\n pmovzxbw m3, [dstq+strideq*2]\n pmovzxbw m4, [dstq+stride3q]\n mova [px+0*32], m1\n mova [px+1*32], m2\n mova [px+2*32], m3\n mova [px+3*32], m4\n%if %2 == 8\n pmovzxbw m1, [dst4q+strideq*0]\n pmovzxbw m2, [dst4q+strideq*1]\n pmovzxbw m3, [dst4q+strideq*2]\n pmovzxbw m4, [dst4q+stride3q]\n mova [px+4*32], m1\n mova [px+5*32], m2\n mova [px+6*32], m3\n mova [px+7*32], m4\n%endif\n jmp .body_done\n.no_right:\n%if %1 == 4\n movd xm1, [dstq+strideq*0]\n movd xm2, [dstq+strideq*1]\n movd xm3, [dstq+strideq*2]\n movd xm4, [dstq+stride3q]\n pmovzxbw xm1, xm1\n pmovzxbw xm2, xm2\n pmovzxbw xm3, xm3\n pmovzxbw xm4, xm4\n movq [px+0*32], xm1\n movq [px+1*32], xm2\n movq [px+2*32], xm3\n movq [px+3*32], xm4\n%else\n pmovzxbw xm1, [dstq+strideq*0]\n pmovzxbw xm2, [dstq+strideq*1]\n pmovzxbw xm3, [dstq+strideq*2]\n pmovzxbw xm4, [dstq+stride3q]\n mova [px+0*32], xm1\n mova [px+1*32], xm2\n mova [px+2*32], xm3\n mova [px+3*32], xm4\n%endif\n movd [px+0*32+%1*2], xm14\n movd [px+1*32+%1*2], xm14\n movd [px+2*32+%1*2], xm14\n movd [px+3*32+%1*2], xm14\n%if %2 == 8\n %if %1 == 4\n movd xm1, [dst4q+strideq*0]\n movd xm2, [dst4q+strideq*1]\n movd xm3, [dst4q+strideq*2]\n movd xm4, [dst4q+stride3q]\n pmovzxbw xm1, xm1\n pmovzxbw xm2, xm2\n pmovzxbw xm3, xm3\n pmovzxbw xm4, xm4\n movq [px+4*32], xm1\n movq [px+5*32], xm2\n movq [px+6*32], xm3\n movq [px+7*32], xm4\n %else\n pmovzxbw xm1, [dst4q+strideq*0]\n pmovzxbw xm2, [dst4q+strideq*1]\n pmovzxbw xm3, [dst4q+strideq*2]\n pmovzxbw xm4, [dst4q+stride3q]\n mova [px+4*32], xm1\n mova [px+5*32], xm2\n mova [px+6*32], xm3\n mova [px+7*32], xm4\n %endif\n movd [px+4*32+%1*2], xm14\n movd [px+5*32+%1*2], xm14\n movd [px+6*32+%1*2], xm14\n movd [px+7*32+%1*2], xm14\n%endif\n.body_done:\n\n ; top\n test edgeb, 4 ; have_top\n jz .no_top\n test edgeb, 1 ; have_left\n jz .top_no_left\n test edgeb, 2 ; have_right\n jz .top_no_right\n pmovzxbw m1, [topq+strideq*0-(%1/2)]\n pmovzxbw m2, [topq+strideq*1-(%1/2)]\n movu [px-2*32-%1], m1\n movu [px-1*32-%1], m2\n jmp .top_done\n.top_no_right:\n pmovzxbw m1, [topq+strideq*0-%1]\n pmovzxbw m2, [topq+strideq*1-%1]\n movu [px-2*32-%1*2], m1\n movu [px-1*32-%1*2], m2\n movd [px-2*32+%1*2], xm14\n movd [px-1*32+%1*2], xm14\n jmp .top_done\n.top_no_left:\n test edgeb, 2 ; have_right\n jz .top_no_left_right\n pmovzxbw m1, [topq+strideq*0]\n pmovzxbw m2, [topq+strideq*1]\n mova [px-2*32+0], m1\n mova [px-1*32+0], m2\n movd [px-2*32-4], xm14\n movd [px-1*32-4], xm14\n jmp .top_done\n.top_no_left_right:\n%if %1 == 4\n movd xm1, [topq+strideq*0]\n pinsrd xm1, [topq+strideq*1], 1\n pmovzxbw xm1, xm1\n movq [px-2*32+0], xm1\n movhps [px-1*32+0], xm1\n%else\n pmovzxbw xm1, [topq+strideq*0]\n pmovzxbw xm2, [topq+strideq*1]\n mova [px-2*32+0], xm1\n mova [px-1*32+0], xm2\n%endif\n movd [px-2*32-4], xm14\n movd [px-1*32-4], xm14\n movd [px-2*32+%1*2], xm14\n movd [px-1*32+%1*2], xm14\n jmp .top_done\n.no_top:\n movu [px-2*32-%1], m14\n movu [px-1*32-%1], m14\n.top_done:\n\n ; left\n test edgeb, 1 ; have_left\n jz .no_left\n pmovzxbw xm1, [leftq+ 0]\n%if %2 == 8\n pmovzxbw xm2, [leftq+ 8]\n%endif\n movd [px+0*32-4], xm1\n pextrd [px+1*32-4], xm1, 1\n pextrd [px+2*32-4], xm1, 2\n pextrd [px+3*32-4], xm1, 3\n%if %2 == 8\n movd [px+4*32-4], xm2\n pextrd [px+5*32-4], xm2, 1\n pextrd [px+6*32-4], xm2, 2\n pextrd [px+7*32-4], xm2, 3\n%endif\n jmp .left_done\n.no_left:\n movd [px+0*32-4], xm14\n movd [px+1*32-4], xm14\n movd [px+2*32-4], xm14\n movd [px+3*32-4], xm14\n%if %2 == 8\n movd [px+4*32-4], xm14\n movd [px+5*32-4], xm14\n movd [px+6*32-4], xm14\n movd [px+7*32-4], xm14\n%endif\n.left_done:\n\n ; bottom\n DEFINE_ARGS dst, stride, dst8, dummy1, pri, sec, stride3, dummy3, edge\n test edgeb, 8 ; have_bottom\n jz .no_bottom\n lea dst8q, [dstq+%2*strideq]\n test edgeb, 1 ; have_left\n jz .bottom_no_left\n test edgeb, 2 ; have_right\n jz .bottom_no_right\n pmovzxbw m1, [dst8q-(%1/2)]\n pmovzxbw m2, [dst8q+strideq-(%1/2)]\n movu [px+(%2+0)*32-%1], m1\n movu [px+(%2+1)*32-%1], m2\n jmp .bottom_done\n.bottom_no_right:\n pmovzxbw m1, [dst8q-%1]\n pmovzxbw m2, [dst8q+strideq-%1]\n movu [px+(%2+0)*32-%1*2], m1\n movu [px+(%2+1)*32-%1*2], m2\n%if %1 == 8\n movd [px+(%2-1)*32+%1*2], xm14 ; overwritten by previous movu\n%endif\n movd [px+(%2+0)*32+%1*2], xm14\n movd [px+(%2+1)*32+%1*2], xm14\n jmp .bottom_done\n.bottom_no_left:\n test edgeb, 2 ; have_right\n jz .bottom_no_left_right\n pmovzxbw m1, [dst8q]\n pmovzxbw m2, [dst8q+strideq]\n mova [px+(%2+0)*32+0], m1\n mova [px+(%2+1)*32+0], m2\n movd [px+(%2+0)*32-4], xm14\n movd [px+(%2+1)*32-4], xm14\n jmp .bottom_done\n.bottom_no_left_right:\n%if %1 == 4\n movd xm1, [dst8q]\n pinsrd xm1, [dst8q+strideq], 1\n pmovzxbw xm1, xm1\n movq [px+(%2+0)*32+0], xm1\n movhps [px+(%2+1)*32+0], xm1\n%else\n pmovzxbw xm1, [dst8q]\n pmovzxbw xm2, [dst8q+strideq]\n mova [px+(%2+0)*32+0], xm1\n mova [px+(%2+1)*32+0], xm2\n%endif\n movd [px+(%2+0)*32-4], xm14\n movd [px+(%2+1)*32-4], xm14\n movd [px+(%2+0)*32+%1*2], xm14\n movd [px+(%2+1)*32+%1*2], xm14\n jmp .bottom_done\n.no_bottom:\n movu [px+(%2+0)*32-%1], m14\n movu [px+(%2+1)*32-%1], m14\n.bottom_done:\n\n ; actual filter\n INIT_YMM avx2\n DEFINE_ARGS dst, stride, pridmp, damping, pri, secdmp, stride3, zero\n%undef edged\n ; register to shuffle values into after packing\n vbroadcasti128 m12, [shufb_lohi]\n\n mov dampingd, r7m\n xor zerod, zerod\n movifnidn prid, prim\n sub dampingd, 31\n movifnidn secdmpd, secdmpm\n or prid, 0\n jz .border_sec_only\n movd xm0, prid\n lzcnt pridmpd, prid\n add pridmpd, dampingd\n cmovs pridmpd, zerod\n mov [rsp+0], pridmpq ; pri_shift\n or secdmpd, 0\n jz .border_pri_only\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n\n DEFINE_ARGS dst, stride, pridmp, table, pri, secdmp, stride3\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n\n ; pri/sec_taps[k] [4 total]\n DEFINE_ARGS dst, stride, dir, table, pri, sec, stride3\n vpbroadcastb m0, xm0 ; pri_strength\n vpbroadcastb m1, xm1 ; sec_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n lea secq, [tableq+12] ; sec_taps\n\n BORDER_PREP_REGS %1, %2\n%if %1*%2*2/mmsize > 1\n.border_v_loop:\n%endif\n BORDER_LOAD_BLOCK %1, %2, 1\n.border_k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_WORD 0*2, [rsp+0], m13, m0, m2, %1, 1\n ACCUMULATE_TAP_WORD 2*2, [rsp+8], m14, m1, m3, %1, 1\n ACCUMULATE_TAP_WORD 6*2, [rsp+8], m14, m1, m3, %1, 1\n dec kq\n jge .border_k_loop\n\n vpbroadcastd m10, [pw_2048]\n BORDER_ADJUST_PIXEL %1, m10, 1\n%if %1*%2*2/mmsize > 1\n %define vloop_lines (mmsize/(%1*2))\n lea dstq, [dstq+strideq*vloop_lines]\n add stkq, 32*vloop_lines\n dec hd\n jg .border_v_loop\n%endif\n RET\n\n.border_pri_only:\n DEFINE_ARGS dst, stride, pridmp, table, pri, _, stride3\n lea tableq, [tap_table]\n vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask\n DEFINE_ARGS dst, stride, dir, table, pri, _, stride3\n vpbroadcastb m0, xm0 ; pri_strength\n and prid, 1\n lea priq, [tableq+priq*2+8] ; pri_taps\n BORDER_PREP_REGS %1, %2\n vpbroadcastd m1, [pw_2048]\n%if %1*%2*2/mmsize > 1\n.border_pri_v_loop:\n%endif\n BORDER_LOAD_BLOCK %1, %2\n.border_pri_k_loop:\n vpbroadcastb m2, [priq+kq] ; pri_taps\n ACCUMULATE_TAP_WORD 0*2, [rsp+0], m13, m0, m2, %1\n dec kq\n jge .border_pri_k_loop\n BORDER_ADJUST_PIXEL %1, m1\n%if %1*%2*2/mmsize > 1\n %define vloop_lines (mmsize/(%1*2))\n lea dstq, [dstq+strideq*vloop_lines]\n add stkq, 32*vloop_lines\n dec hd\n jg .border_pri_v_loop\n%endif\n RET\n\n.border_sec_only:\n DEFINE_ARGS dst, stride, _, damping, _, secdmp, stride3, zero\n movd xm1, secdmpd\n lzcnt secdmpd, secdmpd\n add secdmpd, dampingd\n cmovs secdmpd, zerod\n mov [rsp+8], secdmpq ; sec_shift\n DEFINE_ARGS dst, stride, _, table, _, secdmp, stride3\n lea tableq, [tap_table]\n vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask\n DEFINE_ARGS dst, stride, dir, table, _, sec, stride3\n vpbroadcastb m1, xm1 ; sec_strength\n lea secq, [tableq+12] ; sec_taps\n BORDER_PREP_REGS %1, %2\n vpbroadcastd m0, [pw_2048]\n%if %1*%2*2/mmsize > 1\n.border_sec_v_loop:\n%endif\n BORDER_LOAD_BLOCK %1, %2\n.border_sec_k_loop:\n vpbroadcastb m3, [secq+kq] ; sec_taps\n ACCUMULATE_TAP_WORD 2*2, [rsp+8], m14, m1, m3, %1\n ACCUMULATE_TAP_WORD 6*2, [rsp+8], m14, m1, m3, %1\n dec kq\n jge .border_sec_k_loop\n BORDER_ADJUST_PIXEL %1, m0\n%if %1*%2*2/mmsize > 1\n %define vloop_lines (mmsize/(%1*2))\n lea dstq, [dstq+strideq*vloop_lines]\n add stkq, 32*vloop_lines\n dec hd\n jg .border_sec_v_loop\n%endif\n RET\n%endmacro\n\nCDEF_FILTER 8, 8\nCDEF_FILTER 4, 8\nCDEF_FILTER 4, 4\n\nINIT_YMM avx2\ncglobal cdef_dir, 3, 4, 15, src, stride, var, stride3\n lea stride3q, [strideq*3]\n movq xm0, [srcq+strideq*0]\n movq xm1, [srcq+strideq*1]\n movq xm2, [srcq+strideq*2]\n movq xm3, [srcq+stride3q]\n lea srcq, [srcq+strideq*4]\n vpbroadcastq m4, [srcq+strideq*0]\n vpbroadcastq m5, [srcq+strideq*1]\n vpbroadcastq m6, [srcq+strideq*2]\n vpbroadcastq m7, [srcq+stride3q]\n vpbroadcastd m8, [pw_128]\n pxor m9, m9\n\n vpblendd m0, m0, m7, 0xf0\n vpblendd m1, m1, m6, 0xf0\n vpblendd m2, m2, m5, 0xf0\n vpblendd m3, m3, m4, 0xf0\n\n punpcklbw m0, m9\n punpcklbw m1, m9\n punpcklbw m2, m9\n punpcklbw m3, m9\n\n psubw m0, m8\n psubw m1, m8\n psubw m2, m8\n psubw m3, m8\n\n ; shuffle registers to generate partial_sum_diag[0-1] together\n vpermq m7, m0, q1032\n vpermq m6, m1, q1032\n vpermq m5, m2, q1032\n vpermq m4, m3, q1032\n\n ; start with partial_sum_hv[0-1]\n paddw m8, m0, m1\n paddw m9, m2, m3\n phaddw m10, m0, m1\n phaddw m11, m2, m3\n paddw m8, m9\n phaddw m10, m11\n vextracti128 xm9, m8, 1\n vextracti128 xm11, m10, 1\n paddw xm8, xm9 ; partial_sum_hv[1]\n phaddw xm10, xm11 ; partial_sum_hv[0]\n vinserti128 m8, xm10, 1\n vpbroadcastd m9, [div_table+44]\n pmaddwd m8, m8\n pmulld m8, m9 ; cost6[2a-d] | cost2[a-d]\n\n ; create aggregates [lower half]:\n ; m9 = m0:01234567+m1:x0123456+m2:xx012345+m3:xxx01234+\n ; m4:xxxx0123+m5:xxxxx012+m6:xxxxxx01+m7:xxxxxxx0\n ; m10= m1:7xxxxxxx+m2:67xxxxxx+m3:567xxxxx+\n ; m4:4567xxxx+m5:34567xxx+m6:234567xx+m7:1234567x\n ; and [upper half]:\n ; m9 = m0:xxxxxxx0+m1:xxxxxx01+m2:xxxxx012+m3:xxxx0123+\n ; m4:xxx01234+m5:xx012345+m6:x0123456+m7:01234567\n ; m10= m0:1234567x+m1:234567xx+m2:34567xxx+m3:4567xxxx+\n ; m4:567xxxxx+m5:67xxxxxx+m6:7xxxxxxx\n ; and then shuffle m11 [shufw_6543210x], unpcklwd, pmaddwd, pmulld, paddd\n\n pslldq m9, m1, 2\n psrldq m10, m1, 14\n pslldq m11, m2, 4\n psrldq m12, m2, 12\n pslldq m13, m3, 6\n psrldq m14, m3, 10\n paddw m9, m11\n paddw m10, m12\n paddw m9, m13\n paddw m10, m14\n pslldq m11, m4, 8\n psrldq m12, m4, 8\n pslldq m13, m5, 10\n psrldq m14, m5, 6\n paddw m9, m11\n paddw m10, m12\n paddw m9, m13\n paddw m10, m14\n pslldq m11, m6, 12\n psrldq m12, m6, 4\n pslldq m13, m7, 14\n psrldq m14, m7, 2\n paddw m9, m11\n paddw m10, m12\n paddw m9, m13\n paddw m10, m14 ; partial_sum_diag[0/1][8-14,zero]\n vbroadcasti128 m14, [shufw_6543210x]\n vbroadcasti128 m13, [div_table+16]\n vbroadcasti128 m12, [div_table+0]\n paddw m9, m0 ; partial_sum_diag[0/1][0-7]\n pshufb m10, m14\n punpckhwd m11, m9, m10\n punpcklwd m9, m10\n pmaddwd m11, m11\n pmaddwd m9, m9\n pmulld m11, m13\n pmulld m9, m12\n paddd m9, m11 ; cost0[a-d] | cost4[a-d]\n\n ; merge horizontally and vertically for partial_sum_alt[0-3]\n paddw m10, m0, m1\n paddw m11, m2, m3\n paddw m12, m4, m5\n paddw m13, m6, m7\n phaddw m0, m4\n phaddw m1, m5\n phaddw m2, m6\n phaddw m3, m7\n\n ; create aggregates [lower half]:\n ; m4 = m10:01234567+m11:x0123456+m12:xx012345+m13:xxx01234\n ; m11= m11:7xxxxxxx+m12:67xxxxxx+m13:567xxxxx\n ; and [upper half]:\n ; m4 = m10:xxx01234+m11:xx012345+m12:x0123456+m13:01234567\n ; m11= m10:567xxxxx+m11:67xxxxxx+m12:7xxxxxxx\n ; and then pshuflw m11 3012, unpcklwd, pmaddwd, pmulld, paddd\n\n pslldq m4, m11, 2\n psrldq m11, 14\n pslldq m5, m12, 4\n psrldq m12, 12\n pslldq m6, m13, 6\n psrldq m13, 10\n paddw m4, m10\n paddw m11, m12\n vpbroadcastd m12, [div_table+44]\n paddw m5, m6\n paddw m11, m13 ; partial_sum_alt[3/2] right\n vbroadcasti128 m13, [div_table+32]\n paddw m4, m5 ; partial_sum_alt[3/2] left\n pshuflw m5, m11, q3012\n punpckhwd m6, m11, m4\n punpcklwd m4, m5\n pmaddwd m6, m6\n pmaddwd m4, m4\n pmulld m6, m12\n pmulld m4, m13\n paddd m4, m6 ; cost7[a-d] | cost5[a-d]\n\n ; create aggregates [lower half]:\n ; m5 = m0:01234567+m1:x0123456+m2:xx012345+m3:xxx01234\n ; m1 = m1:7xxxxxxx+m2:67xxxxxx+m3:567xxxxx\n ; and [upper half]:\n ; m5 = m0:xxx01234+m1:xx012345+m2:x0123456+m3:01234567\n ; m1 = m0:567xxxxx+m1:67xxxxxx+m2:7xxxxxxx\n ; and then pshuflw m1 3012, unpcklwd, pmaddwd, pmulld, paddd\n\n pslldq m5, m1, 2\n psrldq m1, 14\n pslldq m6, m2, 4\n psrldq m2, 12\n pslldq m7, m3, 6\n psrldq m3, 10\n paddw m5, m0\n paddw m1, m2\n paddw m6, m7\n paddw m1, m3 ; partial_sum_alt[0/1] right\n paddw m5, m6 ; partial_sum_alt[0/1] left\n pshuflw m0, m1, q3012\n punpckhwd m1, m5\n punpcklwd m5, m0\n pmaddwd m1, m1\n pmaddwd m5, m5\n pmulld m1, m12\n pmulld m5, m13\n paddd m5, m1 ; cost1[a-d] | cost3[a-d]\n\n mova xm0, [pd_47130256+ 16]\n mova m1, [pd_47130256]\n phaddd m9, m8\n phaddd m5, m4\n phaddd m9, m5\n vpermd m0, m9 ; cost[0-3]\n vpermd m1, m9 ; cost[4-7] | cost[0-3]\n\n ; now find the best cost\n pmaxsd xm2, xm0, xm1\n pshufd xm3, xm2, q1032\n pmaxsd xm2, xm3\n pshufd xm3, xm2, q2301\n pmaxsd xm2, xm3 ; best cost\n\n ; find the idx using minpos\n ; make everything other than the best cost negative via subtraction\n ; find the min of unsigned 16-bit ints to sort out the negative values\n psubd xm4, xm1, xm2\n psubd xm3, xm0, xm2\n packssdw xm3, xm4\n phminposuw xm3, xm3\n\n ; convert idx to 32-bits\n psrld xm3, 16\n movd eax, xm3\n\n ; get idx^4 complement\n vpermd m3, m1\n psubd xm2, xm3\n psrld xm2, 10\n movd [varq], xm2\n RET\n\n%if WIN64\nDECLARE_REG_TMP 5, 6\n%else\nDECLARE_REG_TMP 8, 5\n%endif\n\n; lut:\n; t0 t1 t2 t3 t4 t5 t6 t7\n; T0 T1 T2 T3 T4 T5 T6 T7\n; L0 L1 00 01 02 03 04 05\n; L2 L3 10 11 12 13 14 15\n; L4 L5 20 21 22 23 24 25\n; L6 L7 30 31 32 33 34 35\n; 4e 4f 40 41 42 43 44 45\n; 5e 5f 50 51 52 53 54 55\n\nINIT_ZMM avx512icl\ncglobal cdef_filter_4x4, 4, 8, 13, dst, stride, left, top, pri, sec, dir, damping, edge\n%define base r7-edge_mask\n movq xmm0, [dstq+strideq*0]\n movhps xmm0, [dstq+strideq*1]\n lea r7, [edge_mask]\n movq xmm1, [topq+strideq*0-2]\n movhps xmm1, [topq+strideq*1-2]\n mov r6d, edgem\n vinserti32x4 ym0, ymm0, [leftq], 1\n lea r2, [strideq*3]\n vinserti32x4 ym1, ymm1, [dstq+strideq*2], 1\n mova m5, [base+lut_perm_4x4]\n vinserti32x4 m0, [dstq+r2], 2\n test r6b, 0x08 ; avoid buffer overread\n jz .main\n lea r3, [dstq+strideq*4-4]\n vinserti32x4 m1, [r3+strideq*0], 2\n vinserti32x4 m0, [r3+strideq*1], 3\n.main:\n movifnidn prid, prim\n mov t0d, dirm\n mova m3, [base+px_idx]\n mov r3d, dampingm\n vpermi2b m5, m0, m1 ; lut\n vpbroadcastd m0, [base+pd_268435568] ; (1 << 28) + (7 << 4)\n pxor m7, m7\n lea r3, [r7+r3*8] ; gf_shr + (damping - 30) * 8\n vpermb m6, m3, m5 ; px\n cmp r6d, 0x0f\n jne .mask_edges ; mask edges only if required\n test prid, prid\n jz .sec_only\n vpaddd m1, m3, [base+cdef_dirs+(t0+2)*4] {1to16} ; dir\n vpermb m1, m1, m5 ; k0p0 k0p1 k1p0 k1p1\n%macro CDEF_FILTER_4x4_PRI 0\n vpcmpub k1, m6, m1, 6 ; px > pN\n psubb m2, m1, m6\n lzcnt r6d, prid\n vpsubb m2{k1}, m6, m1 ; abs(diff)\n vpbroadcastb m4, prim\n and prid, 1\n vgf2p8affineqb m9, m2, [r3+r6*8] {1to8}, 0 ; abs(diff) >> shift\n movifnidn t1d, secm\n vpbroadcastd m10, [base+pri_tap+priq*4]\n vpsubb m10{k1}, m7, m10 ; apply_sign(pri_tap)\n psubusb m4, m9 ; imax(0, pri_strength - (abs(diff) >> shift)))\n pminub m2, m4\n vpdpbusd m0, m2, m10 ; sum\n%endmacro\n CDEF_FILTER_4x4_PRI\n test t1d, t1d ; sec\n jz .end_no_clip\n call .sec\n.end_clip:\n pminub m4, m6, m1\n pmaxub m1, m6\n pminub m5, m2, m3\n pmaxub m2, m3\n pminub m4, m5\n pmaxub m2, m1\n psrldq m1, m4, 2\n psrldq m3, m2, 2\n pminub m1, m4\n vpcmpw k1, m0, m7, 1\n vpshldd m6, m0, 8\n pmaxub m2, m3\n pslldq m3, m1, 1\n psubw m7, m0\n paddusw m0, m6 ; clip >0xff\n vpsubusw m0{k1}, m6, m7 ; clip <0x00\n pslldq m4, m2, 1\n pminub m1, m3\n pmaxub m2, m4\n pmaxub m0, m1\n pminub m0, m2\n jmp .end\n.sec_only:\n movifnidn t1d, secm\n call .sec\n.end_no_clip:\n vpshldd m6, m0, 8 ; (px << 8) + ((sum > -8) << 4)\n paddw m0, m6 ; (px << 8) + ((sum + (sum > -8) + 7) << 4)\n.end:\n mova xm1, [base+end_perm]\n vpermb m0, m1, m0 ; output in bits 8-15 of each dword\n movd [dstq+strideq*0], xm0\n pextrd [dstq+strideq*1], xm0, 1\n pextrd [dstq+strideq*2], xm0, 2\n pextrd [dstq+r2 ], xm0, 3\n RET\n.mask_edges_sec_only:\n movifnidn t1d, secm\n call .mask_edges_sec\n jmp .end_no_clip\nALIGN function_align\n.mask_edges:\n vpbroadcastq m8, [base+edge_mask+r6*8]\n test prid, prid\n jz .mask_edges_sec_only\n vpaddd m2, m3, [base+cdef_dirs+(t0+2)*4] {1to16}\n vpshufbitqmb k1, m8, m2 ; index in-range\n mova m1, m6\n vpermb m1{k1}, m2, m5\n CDEF_FILTER_4x4_PRI\n test t1d, t1d\n jz .end_no_clip\n call .mask_edges_sec\n jmp .end_clip\n.mask_edges_sec:\n vpaddd m4, m3, [base+cdef_dirs+(t0+4)*4] {1to16}\n vpaddd m9, m3, [base+cdef_dirs+(t0+0)*4] {1to16}\n vpshufbitqmb k1, m8, m4\n mova m2, m6\n vpermb m2{k1}, m4, m5\n vpshufbitqmb k1, m8, m9\n mova m3, m6\n vpermb m3{k1}, m9, m5\n jmp .sec_main\nALIGN function_align\n.sec:\n vpaddd m2, m3, [base+cdef_dirs+(t0+4)*4] {1to16} ; dir + 2\n vpaddd m3, [base+cdef_dirs+(t0+0)*4] {1to16} ; dir - 2\n vpermb m2, m2, m5 ; k0s0 k0s1 k1s0 k1s1\n vpermb m3, m3, m5 ; k0s2 k0s3 k1s2 k1s3\n.sec_main:\n vpbroadcastd m8, [base+sec_tap]\n vpcmpub k1, m6, m2, 6\n psubb m4, m2, m6\n vpbroadcastb m12, t1d\n lzcnt t1d, t1d\n vpsubb m4{k1}, m6, m2\n vpcmpub k2, m6, m3, 6\n vpbroadcastq m11, [r3+t1*8]\n gf2p8affineqb m10, m4, m11, 0\n psubb m5, m3, m6\n mova m9, m8\n vpsubb m8{k1}, m7, m8\n psubusb m10, m12, m10\n vpsubb m5{k2}, m6, m3\n pminub m4, m10\n vpdpbusd m0, m4, m8\n gf2p8affineqb m11, m5, m11, 0\n vpsubb m9{k2}, m7, m9\n psubusb m12, m11\n pminub m5, m12\n vpdpbusd m0, m5, m9\n ret\n\n%endif ; ARCH_X86_64\n"}}},{"rowIdx":490,"cells":{"commit":{"kind":"string","value":"246e1b5b8acf9f2779da4a465658f6d24cd857fb"},"subject":{"kind":"string","value":"fix string compile"},"message":{"kind":"string","value":"fix string compile\n"},"repos":{"kind":"string","value":"MateoConLechuga/Cesium"},"file_path":{"kind":"string","value":"src/strings.asm"},"license":{"kind":"string","value":"bsd-3-clause"},"unix_time":{"kind":"number","value":1583026237,"string":"1,583,026,237"},"new_contents":{"kind":"string","value":"; commonly used strings\n\nstring_cesium:\n\tdb\tcesium_name,0\nstring_cesium_version:\n\tdb\tcesium_name,' Version ',cesium_version,0\nstring_asm:\n\tdb\t'eZ80',0\nstring_c:\n\tdb\t'C',0\nstring_ice:\n\tdb\t'ICE',0\nstring_ice_source:\n\tdb\t'ICE S',0\nstring_directory:\n\tdb\t'Folder',0\nstring_usb:\n\tdb\t'USB',0\nstring_basic:\n\tdb\t'Basic',0\nstring_application:\n\tdb\t'App',0\nstring_ti:\n\tdb\t'TI-OS',0\nstring_unknown:\n\tdb\t'Unknown',0\nstring_appvar:\n\tdb\t'Data',0\nstring_mode_select:\n\tdb\t' < ',$7e,'MODE] >',0\nstring_min_os_version:\n\tdb\t'5.0.0.0.0',0\n.length := $-.\n\n; english configuration\n\nif config_english\n\nstring_primary_color:\n\tdb\t'Primary Color',0\nstring_secondary_color:\n\tdb\t'Secondary Color',0\nstring_tertiary_color:\n\tdb\t'Highlight Color',0\nstring_quaternary_color:\n\tdb\t'Inversion Color',0\nstring_quinary_color:\n\tdb\t'Hidden Program Color',0\nstring_senary_color:\n\tdb\t'Background Color',0\nstring_language:\n\tdb\t'Type: ',0\nstring_archived:\n\tdb\t'Archived',0\nstring_read_only:\n\tdb\t'Read-Only',0\nstring_hidden:\n\tdb\t'Hidden',0\nstring_system:\n\tdb\t'System',0\nstring_locked:\n\tdb\t'Locked',0\nstring_size:\n\tdb\t'Size: ',0\nstring_min_version:\n\tdb\t'Min Version:',0\nstring_ram_free:\n\tdb\t'RAM Free: ',0\nstring_rom_free:\n\tdb\t'ROM Free: ',0\nstring_file_information:\n\tdb\t'File Information',0\nstring_settings:\n\tdb\t'Settings',0\n\tdb\t$7e,'MODE]',0\nstring_delete:\n\tdb\t'Delete',0\n\tdb\t$7e,'DEL]',0\nstring_attributes:\n\tdb\t'Attrib',0\n\tdb\t$7e,'ALPHA]',0\nstring_rename:\n\tdb\t'Rename',0\n\tdb\t$7e,'GRAPH]',0\nstring_transfer:\n\tdb\t'Transfer',0\n\tdb\t$7e,'PRGM]',0\nstring_edit_prgm:\n\tdb\t'Edit Prgm',0\n\tdb\t$7e,'ZOOM]'\nstring_new_prgm:\n\tdb\t'New Prgm',0\n\tdb\t$7e,'Y=]'\nstring_editor_name:\n\tdb\t'Prgm Editor',0\nstring_delete_confirmation:\n\tdb\t'Delete?: ',$7e,'ZOOM]-Yes ',$7e,'GRAPH]-No',0\nstring_general_settings:\n\tdb\t'General Settings',0\nstring_setting_color:\n\tdb\t'Cesium Color',0\nstring_setting_indicator:\n\tdb\t'Disable busy indicator in programs',0\nstring_setting_list_count:\n\tdb\t'Show directory item count',0\nstring_setting_clock:\n\tdb\t'Display clock',0\nstring_setting_ram_backup:\n\tdb\t'Backup RAM before executing programs',0\nstring_setting_special_directories:\n\tdb\t'Show special directories',0\nstring_setting_enable_shortcuts:\n\tdb\t'Enable keypad shortcuts',0\nstring_settings_usb_edit:\n\tdb\t'Enable USB flash drive access',0\nstring_settings_delete_confirm:\n\tdb\t'Show item deletion confirmation prompt',0\nstring_new_password:\n\tdb\t'Input new password: ',0\nstring_usb_info_0:\n\tdb\t'Use any FAT32 USB flash drive',0\nstring_usb_info_1:\n\tdb\t'for external storage and transfer.',0\nstring_usb_info_2:\n\tdb\t'You will need to install LibLoad',0\nstring_usb_info_3:\n\tdb\t'and the FATDRVCE/USBDRVCE library from:',0\nstring_usb_info_4:\n\tdb\t'http://tiny.cc/clibs',0\nstring_usb_info_5:\n\tdb\t'Press ',$7e,'enter] to retry.',0\nstring_usb_info_6:\n\tdb\t'Press ',$7e,'suppr] to cancel.',0\nstring_usb_waiting:\n\tdb\t'Waiting for USB to be connected...',0\nstring_usb_no_partitions:\n\tdb\t'No FAT32 partitions found!',0\nstring_insert_fat32:\n\tdb\t'Please insert a FAT32 formatted drive.',0\nstring_partition:\n\tdb\t'Partition ',0\nstring_select_partition_0:\n\tdb\t'This drive contains multiple partitions.',0\nstring_select_partition_1:\n\tdb\t'Choose one from the list above.',0\nstring_fat_init_error_0:\n\tdb\t'Error initializing FAT partition.',0\nstring_fat_init_error_1:\n\tdb\t'Error code: ',0\nstring_fat_transferring:\n\tdb\t'Transferring...',0\nstring_ram_error:\n\tdb\t'Not enough free RAM',0\n\n; french configuration\n\nelse\n\nstring_primary_color:\n\tdb\t'Couleur primaire',0\nstring_secondary_color:\n\tdb\t'Couleur secondaire',0\nstring_tertiary_color:\n\tdb\t'Couleur surligner',0\nstring_quaternary_color:\n\tdb\t'Couleur invers',$82,0\nstring_quinary_color:\n\tdb\t'Couleur programme cach',$82,0\nstring_senary_color:\n\tdb\t'Couleur contexte',0\nstring_language:\n\tdb\t'Langage : ',0\nstring_archived:\n\tdb\t'Archiv',$82,0\nstring_hidden:\n\tdb\t'Cach',$82,0\nstring_locked:\n\tdb\t'Verrouill',$82,0\nstring_size:\n\tdb\t'Taille : ',0\nstring_min_version:\n\tdb\t'Min Version:',0\nstring_ram_free:\n\tdb\t'RAM Libre : ',0\nstring_rom_free:\n\tdb\t'ROM Libre : ',0\nstring_file_information:\n\tdb\t' Infos fichier',0\nstring_settings:\n\tdb\t'Options',0\n\tdb\t$7e,'MODE]',0\nstring_delete:\n\tdb\t'Effacer',0\n\tdb\t$7e,'SUPPR]',0\nstring_attributes:\n\tdb\t'Attrib',0\n\tdb\t$7e,'ALPHA]',0\nstring_rename:\n\tdb\t'Nom',0\n\tdb\t$7e,'GRAPH]',0\nstring_edit_prgm:\n\tdb\t'Modifier',0\n\tdb\t$7e,'ZOOM]'\nstring_new_prgm:\n\tdb\t'Nouveau',0\n\tdb\t$7e,'Y=]',0\nstring_editor_name:\n\tdb\t'Editeur de prgm',0\nstring_delete_confirmation:\n\tdb\t'Supprimer ? ',$7e,'ZOOM]-Oui ',$7e,'GRAPH]-Non',0\nstring_general_settings:\n\tdb\t'Options g',$82,'n',$82,'rales',0\nstring_setting_color:\n\tdb\t'Couleur de Cesium',0\nstring_setting_indicator:\n\tdb\t'Cacher l',$27,'indicateur de calcul en BASIC',0\nstring_setting_list_count:\n\tdb\t'Afficher le nombre de programmes',0\nstring_setting_clock:\n\tdb\t'Afficher l',$27,'horloge',0\nstring_setting_ram_backup:\n\tdb\t'Sauver la RAM avant de lancer des prgms',0\nstring_setting_special_directories:\n\tdb\t'Afficher les r',$82,'pertoires sp',$82,'ciaux',0\nstring_setting_enable_shortcuts:\n\tdb\t'Activer les raccourcis clavier',0\nstring_settings_usb_edit:\n\tdb\t'Activer le support de cl',$82,'s USB',0\nstring_settings_delete_confirm:\n\tdb\t'Afficher l',$27,'invite de suppression',0\nstring_new_password:\n\tdb\t'Saisir le nouveau mot de passe : ',0\nstring_read_only:\n\tdb\t'Lecture seule',0\nstring_system:\n\tdb\t'Systeme',0\nstring_transfer:\n\tdb\t'Transfer',0\n\tdb\t$7e,'PRGM]',0\nstring_usb_info_0:\n\tdb\t'Utilisez une cl',$82,' USB en FAT32',0\nstring_usb_info_1:\n\tdb\t'pour du stockage externe et transferts.',0\nstring_usb_info_2:\n\tdb\t'Vous devrez installer LibLoad',0\nstring_usb_info_3:\n\tdb\t'et la lib FATDRVCE/USBDRVCE depuis ici :',0\nstring_usb_info_4:\n\tdb\t'http://tiny.cc/clibs',0\nstring_usb_info_5:\n\tdb\t'Appuyez sur ',$7e,'entrer] pour retenter.',0\nstring_usb_info_6:\n\tdb\t'Appuyez sur ',$7e,'entrer] pour annuler.',0\nstring_usb_waiting:\n\tdb\t'En attente de connexion USB ...',0\nstring_usb_no_partitions:\n\tdb\t'Pas de partition FAT32 trouv',$82,'e.',0\nstring_insert_fat32:\n\tdb\t'Veuillez brancher une cl',$82,' format',$82,'e en FAT32.',0\nstring_partition:\n\tdb\t'Partition ',0\nstring_select_partition_0:\n\tdb\t'Cette cl',$82,' contient plusieurs partitions.',0\nstring_select_partition_1:\n\tdb\t'Choisissez-en une depuis la liste ci-dessus.',0\nstring_fat_init_error_0:\n\tdb\t'Erreur d',$27,'init de la partition FAT.',0\nstring_fat_init_error_1:\n\tdb\t'Code d''erreur : ',0\nstring_fat_transferring:\n\tdb\t'Transfert en cours...',0\nstring_ram_error:\n\tdb\t'Pas assez de RAM libre',0\n\nend if\n"},"old_contents":{"kind":"string","value":"; commonly used strings\n\nstring_cesium:\n\tdb\tcesium_name,0\nstring_cesium_version:\n\tdb\tcesium_name,' Version ',cesium_version,0\nstring_asm:\n\tdb\t'eZ80',0\nstring_c:\n\tdb\t'C',0\nstring_ice:\n\tdb\t'ICE',0\nstring_ice_source:\n\tdb\t'ICE S',0\nstring_directory:\n\tdb\t'Folder',0\nstring_usb:\n\tdb\t'USB',0\nstring_basic:\n\tdb\t'Basic',0\nstring_application:\n\tdb\t'App',0\nstring_ti:\n\tdb\t'TI-OS',0\nstring_unknown:\n\tdb\t'Unknown',0\nstring_appvar:\n\tdb\t'Data',0\nstring_mode_select:\n\tdb\t' < ',$7e,'MODE] >',0\nstring_min_os_version:\n\tdb\t'5.0.0.0.0',0\n.length := $-.\n\n; english configuration\n\nif config_english\n\nstring_primary_color:\n\tdb\t'Primary Color',0\nstring_secondary_color:\n\tdb\t'Secondary Color',0\nstring_tertiary_color:\n\tdb\t'Highlight Color',0\nstring_quaternary_color:\n\tdb\t'Inversion Color',0\nstring_quinary_color:\n\tdb\t'Hidden Program Color',0\nstring_senary_color:\n\tdb\t'Background Color',0\nstring_language:\n\tdb\t'Type: ',0\nstring_archived:\n\tdb\t'Archived',0\nstring_read_only:\n\tdb\t'Read-Only',0\nstring_hidden:\n\tdb\t'Hidden',0\nstring_system:\n\tdb\t'System',0\nstring_locked:\n\tdb\t'Locked',0\nstring_size:\n\tdb\t'Size: ',0\nstring_min_version:\n\tdb\t'Min Version:',0\nstring_ram_free:\n\tdb\t'RAM Free: ',0\nstring_rom_free:\n\tdb\t'ROM Free: ',0\nstring_file_information:\n\tdb\t'File Information',0\nstring_settings:\n\tdb\t'Settings',0\n\tdb\t$7e,'MODE]',0\nstring_delete:\n\tdb\t'Delete',0\n\tdb\t$7e,'DEL]',0\nstring_attributes:\n\tdb\t'Attrib',0\n\tdb\t$7e,'ALPHA]',0\nstring_rename:\n\tdb\t'Rename',0\n\tdb\t$7e,'GRAPH]',0\nstring_transfer:\n\tdb\t'Transfer',0\n\tdb\t$7e,'PRGM]',0\nstring_edit_prgm:\n\tdb\t'Edit Prgm',0\n\tdb\t$7e,'ZOOM]'\nstring_new_prgm:\n\tdb\t'New Prgm',0\n\tdb\t$7e,'Y=]'\nstring_editor_name:\n\tdb\t'Prgm Editor',0\nstring_delete_confirmation:\n\tdb\t'Delete?: ',$7e,'ZOOM]-Yes ',$7e,'GRAPH]-No',0\nstring_general_settings:\n\tdb\t'General Settings',0\nstring_setting_color:\n\tdb\t'Cesium Color',0\nstring_setting_indicator:\n\tdb\t'Disable busy indicator in programs',0\nstring_setting_list_count:\n\tdb\t'Show directory item count',0\nstring_setting_clock:\n\tdb\t'Display clock',0\nstring_setting_ram_backup:\n\tdb\t'Backup RAM before executing programs',0\nstring_setting_special_directories:\n\tdb\t'Show special directories',0\nstring_setting_enable_shortcuts:\n\tdb\t'Enable keypad shortcuts',0\nstring_settings_usb_edit:\n\tdb\t'Enable USB flash drive access',0\nstring_settings_delete_confirm:\n\tdb\t'Show item deletion confirmation prompt',0\nstring_new_password:\n\tdb\t'Input new password: ',0\nstring_usb_info_0:\n\tdb\t'Use any FAT32 USB flash drive',0\nstring_usb_info_1:\n\tdb\t'for external storage and transfer.',0\nstring_usb_info_2:\n\tdb\t'You will need to install LibLoad',0\nstring_usb_info_3:\n\tdb\t'and the FATDRVCE/USBDRVCE library from:',0\nstring_usb_info_4:\n\tdb\t'http://tiny.cc/clibs',0\nstring_usb_info_5:\n\tdb\t'Press ',$7e,'enter] to retry.',0\nstring_usb_info_6:\n\tdb\t'Press ',$7e,'suppr] to cancel.',0\nstring_usb_waiting:\n\tdb\t'Waiting for USB to be connected...',0\nstring_usb_no_partitions:\n\tdb\t'No FAT32 partitions found!',0\nstring_insert_fat32:\n\tdb\t'Please insert a FAT32 formatted drive.',0\nstring_partition:\n\tdb\t'Partition ',0\nstring_select_partition_0:\n\tdb\t'This drive contains multiple partitions.',0\nstring_select_partition_1:\n\tdb\t'Choose one from the list above.',0\nstring_fat_init_error_0:\n\tdb\t'Error initializing FAT partition.',0\nstring_fat_init_error_1:\n\tdb\t'Error code: ',0\nstring_fat_transferring:\n\tdb\t'Transferring...',0\nstring_ram_error:\n\tdb\t'Not enough free RAM',0\n\n; french configuration\n\nelse\n\nstring_primary_color:\n\tdb\t'Couleur primaire',0\nstring_secondary_color:\n\tdb\t'Couleur secondaire',0\nstring_tertiary_color:\n\tdb\t'Couleur surligner',0\nstring_quaternary_color:\n\tdb\t'Couleur invers',$82,0\nstring_quinary_color:\n\tdb\t'Couleur programme cach',$82,0\nstring_senary_color:\n\tdb\t'Couleur contexte',0\nstring_language:\n\tdb\t'Langage : ',0\nstring_archived:\n\tdb\t'Archiv',$82,0\nstring_hidden:\n\tdb\t'Cach',$82,0\nstring_locked:\n\tdb\t'Verrouill',$82,0\nstring_size:\n\tdb\t'Taille : ',0\nstring_min_version:\n\tdb\t'Min Version:',0\nstring_ram_free:\n\tdb\t'RAM Libre : ',0\nstring_rom_free:\n\tdb\t'ROM Libre : ',0\nstring_file_information:\n\tdb\t' Infos fichier',0\nstring_settings:\n\tdb\t'Options',0\n\tdb\t$7e,'MODE]',0\nstring_delete:\n\tdb\t'Effacer',0\n\tdb\t$7e,'SUPPR]',0\nstring_attributes:\n\tdb\t'Attrib',0\n\tdb\t$7e,'ALPHA]',0\nstring_rename:\n\tdb\t'Nom',0\n\tdb\t$7e,'GRAPH]',0\nstring_edit_prgm:\n\tdb\t'Modifier',0\n\tdb\t$7e,'ZOOM]'\nstring_new_prgm:\n\tdb\t'Nouveau',0\n\tdb\t$7e,'Y=]',0\nstring_editor_name:\n\tdb\t'Editeur de prgm',0\nstring_delete_confirmation:\n\tdb\t'Supprimer ? ',$7e,'ZOOM]-Oui ',$7e,'GRAPH]-Non',0\nstring_general_settings:\n\tdb\t'Options g',$82,'n',$82,'rales',0\nstring_setting_color:\n\tdb\t'Couleur de Cesium',0\nstring_setting_indicator:\n\tdb\t'Cacher l',$27,'indicateur de calcul en BASIC',0\nstring_setting_list_count:\n\tdb\t'Afficher le nombre de programmes',0\nstring_setting_clock:\n\tdb\t'Afficher l',$27,'horloge',0\nstring_setting_ram_backup:\n\tdb\t'Sauver la RAM avant de lancer des prgms',0\nstring_setting_special_directories:\n\tdb\t'Afficher les r',$82,'pertoires sp',$82,'ciaux',0\nstring_setting_enable_shortcuts:\n\tdb\t'Activer les raccourcis clavier',0\nstring_settings_usb_edit:\n\tdb\t'Activer le support de cl',$82,'s USB',0\nstring_settings_delete_confirm:\n\tdb\t'Afficher l',$27,'invite de suppression',0\nstring_new_password:\n\tdb\t'Saisir le nouveau mot de passe : ',0\nstring_read_only:\n\tdb\t'Lecture seule',0\nstring_system:\n\tdb\t'Systeme',0\nstring_transfer:\n\tdb\t'Transfer',0\n\tdb\t$7e,'PRGM]',0\nstring_usb_info_0:\n\tdb\t'Utilisez une cl',$82,' USB en FAT32',0\nstring_usb_info_1:\n\tdb\t'pour du stockage externe et transferts.',0\nstring_usb_info_2:\n\tdb\t'Vous devrez installer LibLoad',0\nstring_usb_info_3:\n\tdb\t'et la lib FATDRVCE/USBDRVCE depuis ici :',0\nstring_usb_info_4:\n\tdb\t'http://tiny.cc/clibs',0\nstring_usb_info_5:\n\tdb\t'Appuyez sur ',$7e,'entrer] pour retenter.',0\nstring_usb_info_6:\n\tdb\t'Appuyez sur ',$7e,'entrer] pour annuler.',0\nstring_usb_waiting:\n\tdb\t'En attente de connexion USB ...',0\nstring_usb_no_partitions:\n\tdb\t'Pas de partition FAT32 trouv',$82,'e.',0\nstring_insert_fat32:\n\tdb\t'Veuillez brancher une cl',$82,' format',$82,'e en FAT32.',0\nstring_partition:\n\tdb\t'Partition ',0\nstring_select_partition_0:\n\tdb\t'Cette cl',$82,' contient plusieurs partitions.',0\nstring_select_partition_1:\n\tdb\t'Choisissez-en une depuis la liste ci-dessus.',0\nstring_fat_init_error_0:\n\tdb\t'Erreur d',$27,'init de la partition FAT.',0\nstring_fat_init_error_1:\n\tdb\t'Code d\\'erreur : ',0\nstring_fat_transferring:\n\tdb\t'Transfert en cours...',0\nstring_ram_error:\n\tdb\t'Pas assez de RAM libre',0\n\nend if\n"}}},{"rowIdx":491,"cells":{"commit":{"kind":"string","value":"98cdea1628036dc6a7e7a455947ce3c345b02975"},"subject":{"kind":"string","value":"limit rate bars to their intended bounds"},"message":{"kind":"string","value":"limit rate bars to their intended bounds\n\nin some cases the rate bar code was falling through to clear sprites\nbut writing past their intended bounds corrupting unused wram.\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582821821,"string":"1,582,821,821"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR MoveSpritesOffScreen\r\n JSR LoadGameAttribute\r\n\r\n JSR DisplayScreen0\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoopEnter\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\n JMP P1RateHideLoop\r\nP1RateHideLoopEnter:\r\n LDX #$00\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoopEnter\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX #$20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\n JMP P2RateHideLoop\r\nP2RateHideLoopEnter:\r\n LDX #$00\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR MoveSpritesOffScreen\r\n JSR LoadGameAttribute\r\n\r\n JSR DisplayScreen0\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX #$20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":492,"cells":{"commit":{"kind":"string","value":"89f5b817e0c531893842dbed742da36b33418bb9"},"subject":{"kind":"string","value":"Fix player 2 sprites"},"message":{"kind":"string","value":"Fix player 2 sprites\n\nSprites for player 2 were flickering because they were comparing an\naddress rather than an immediate value.\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582818270,"string":"1,582,818,270"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR MoveSpritesOffScreen\r\n JSR LoadGameAttribute\r\n\r\n JSR DisplayScreen0\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX #$20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR MoveSpritesOffScreen\r\n JSR LoadGameAttribute\r\n\r\n JSR DisplayScreen0\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":493,"cells":{"commit":{"kind":"string","value":"bbff00443864195d4a79844fe8d5bc442338205a"},"subject":{"kind":"string","value":"disable rendering while writing game attributes"},"message":{"kind":"string","value":"disable rendering while writing game attributes\n\nif rendering is enabled during write operations the data will get\nwritten to an unintended address resulting in graphical corruption.\n\nadd a missed case when writing game attributes, snap the screen\nback to screen 0 after writing as a tradeoff between seeing screen 1\nfor a single frame vs a slight vertical misalignment for the same\nframe. not perfect, but less intensive than rewriting.\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582813589,"string":"1,582,813,589"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR MoveSpritesOffScreen\r\n JSR LoadGameAttribute\r\n\r\n JSR DisplayScreen0\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":494,"cells":{"commit":{"kind":"string","value":"bda25272a890e1866163e1ca7df2004fdcc83f7a"},"subject":{"kind":"string","value":"move sprites off screen to a consistent position"},"message":{"kind":"string","value":"move sprites off screen to a consistent position\n\nFE should be a consistent position to move sprites off screen,\nrate bar may still be visible on the y axis on some frames due\nto the way the loop is written, further investigation needed\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582811803,"string":"1,582,811,803"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$FE\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$FE\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$FE ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":495,"cells":{"commit":{"kind":"string","value":"666379018bc2d98c3d16984e68e8539c4d43540a"},"subject":{"kind":"string","value":"push initial sprite state to ppu, bug fixes"},"message":{"kind":"string","value":"push initial sprite state to ppu, bug fixes\n\npushing the initial sprite state to the ppu before we start rendering\nshould prevent a single frame of random sprites littered on the\nscreen. also fix a bug in a previous patch involving bitfields.\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582758511,"string":"1,582,758,511"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%00000110 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPUDATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%000111100 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":496,"cells":{"commit":{"kind":"string","value":"c4b4783644a95229043eebce407ab9574c5fbc9f"},"subject":{"kind":"string","value":"correct address in memory clearing routine"},"message":{"kind":"string","value":"correct address in memory clearing routine\n\nFE is written to shadow OAM to ensure sprite slots aren't drawn on\nthe screen if they are unused. $0200 is being used for shadow OAM.\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582757451,"string":"1,582,757,451"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0300, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0200, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPUDATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%000111100 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0200, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0300, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPUDATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%000111100 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":497,"cells":{"commit":{"kind":"string","value":"ec5247d2d794af0add02826096a1895e7fc2e96e"},"subject":{"kind":"string","value":"disable bg and spr rendering during ppu writes"},"message":{"kind":"string","value":"disable bg and spr rendering during ppu writes\n\nif rendering is enabled during write operations the data will get\nwritten to an unintended address resulting in graphical corruption.\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582757282,"string":"1,582,757,282"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0200, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0300, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPUDATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n\r\n LDA #%000001100 ; disable sprites, disable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\n\r\n LDA #%000111100 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0200, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0300, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPUDATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":498,"cells":{"commit":{"kind":"string","value":"297f9f0cb639ab672db151b4c83a2ce432b5a53a"},"subject":{"kind":"string","value":"update labels for readability"},"message":{"kind":"string","value":"update labels for readability\n\nsome labels were missing colons, updated some addresses to use labels\n\nSigned-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>\n"},"repos":{"kind":"string","value":"mitch3b/MashyMashy"},"file_path":{"kind":"string","value":"MashyMashy.asm"},"license":{"kind":"string","value":"mit"},"unix_time":{"kind":"number","value":1582756827,"string":"1,582,756,827"},"new_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\nPPU_SPR_DMA = $4014\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\nSND_FRAME_IRQ = $4017\r\n\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX SND_FRAME_IRQ ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX SND_DELTA_REG ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0200, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0300, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\r\n JMP FrameProcessed\r\nTryGameOver:\r\n LDA game_state\r\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA PPUDATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\r\nIncrementScroll:\r\n LDX scroll\r\n INX\r\n INX\r\n INX\r\n INX\r\n RTS\r\n\r\nDecrementScroll:\r\n LDX scroll\r\n DEX\r\n DEX\r\n DEX\r\n DEX\r\n RTS\r\n\r\nDisplayScreen0:\r\n LDA #%10011000\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nDisplayTitleScreen:\r\n LDA #%10001001\r\n STA PPU_CTRL_REG1\r\n RTS\r\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA PPU_SPR_DMA ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem:\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay:\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA PPU_DATA\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA PPU_DATA\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate:\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB:\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA:\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB:\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect:\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart:\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time:\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice:\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text:\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text:\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text:\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text: ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text:\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text:\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text:\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text:\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text:\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text:\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text:\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter: ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate:\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter:\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate:\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter:\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"},"old_contents":{"kind":"string","value":" .inesprg 1 ; 1x 16KB PRG code\r\n .ineschr 1 ; 1x 8KB CHR data\r\n .inesmap 0 ; mapper 0 = NROM, no bank swapping\r\n .inesmir 1 ; background mirroring (horizontal scrolling)\r\n\r\n;MITCH\r\n; .include \"TitleScreen.asm\"\r\n\r\n; -----------------------------------\r\n; Standard NES registers\r\n\r\nPPU_CTRL_REG1 = $2000\r\nPPU_CTRL_REG2 = $2001\r\nPPU_STATUS = $2002\r\nPPU_SPR_ADDR = $2003\r\nPPU_SPR_DATA = $2004\r\nPPU_SCROLL_REG = $2005\r\nPPU_ADDRESS = $2006\r\nPPU_DATA = $2007\r\n\r\nSND_REGISTER = $4000\r\nSND_SQUARE1_REG = $4000\r\nSND_SQUARE2_REG = $4004\r\nSND_TRIANGLE_REG = $4008\r\nSND_NOISE_REG = $400c\r\nSND_DELTA_REG = $4010\r\nSND_MASTERCTRL_REG = $4015\r\n\r\nSPR_DMA = $4014\r\nCONTROLLER_PORT = $4016\r\nCONTROLLER_PORT1 = $4016\r\nCONTROLLER_PORT2 = $4017\r\n\r\n; ################################\r\n; Game Tiles 0200 not used, used-> 0204->0228\r\n; ################################\r\n\r\nDISPLAY_NUMBERS_Y = 2\r\nDISPLAY_P1_BP_HUNDREDS_TILE = $0205\r\nDISPLAY_P1_BP_TENS_TILE = $0209\r\nDISPLAY_P1_BP_ONES_TILE = $020D\r\nDIPLAY_GT_TENS_TILES = $0211\r\nDIPLAY_GT_ONES_TILES = $0215\r\nDIPLAY_GT_TENTHS_TILES = $021D\r\nDISPLAY_P2_BP_HUNDREDS_TILE = $0221\r\nDISPLAY_P2_BP_TENS_TILE = $0225\r\nDISPLAY_P2_BP_ONES_TILE = $0229\r\n\r\n; ################################\r\n; Menu Tiles 0200->?\r\n; ################################\r\n\r\nSCREEN_WIDTH_TILES = 32\r\nSCREEN_HEIGHT_TILES = 30;\r\n; -----------------------------------\r\n\r\n .rsset $0000 ; start the reserve counter at memory address $0000\r\ndummy .rs 1 ; theres some bug writing to 0000 which is game state...\r\ngame_state .rs 1 ; reserve one byte of space to track the current state\r\nprev_game_state .rs 1 ; to see if state has changed. could hide this in game state\r\nGAME_TITLE = 1\r\nGAME_MENU = 2\r\nGAME_PLAY = 3\r\nGAME_OVER = 4\r\nGAME_SCROLL_TO_GAME = 5\r\nGAME_SCROLL_TO_MENU = 6\r\n\r\nGAME_OVER_WAIT_FRAMES = 60\r\ngame_over_frame_counter .rs 1\r\n\r\nnum_players .rs 1 ;\r\n\r\nNoiseSoundBuffer .rs 1\r\n\r\n; What bit each button is stored in a controller byte\r\nBUTTON_A = %10000000\r\nBUTTON_B = %01000000\r\nBUTTON_SELECT = %00100000\r\nBUTTON_START = %00010000\r\nBUTTON_UP = %00001000\r\nBUTTON_DOWN = %00000100\r\nBUTTON_LEFT = %00000010\r\nBUTTON_RIGHT = %00000001\r\nBUTTON_DOWN_B = %01000100 ; for ninja gaiden, mashing down+b together is important for last boss\r\n\r\nTOGGLE_BUTTONS = %11010011 ; left/right/b/a/start\r\nTOGGLE_PREV_BUTTONS = %01000010 ; left and b\r\nTOGGLE_NEXT_BUTTONS = %10010001 ; right, a or start\r\n\r\np1_buttons .rs 1 ; player 1 gamepad buttons, one bit per button\r\np2_buttons .rs 1 ; player 2 gamepad buttons, one bit per button\r\np1_prev_buttons .rs 1 ; to track what buttons changed\r\np2_prev_buttons .rs 1 ; to track what buttons changed\r\np1_buttons_new_press .rs 1;\r\np2_buttons_new_press .rs 1;\r\np1_in_press .rs 1;\r\np2_in_press .rs 1;\r\nstart_pressed .rs 1 ; TODO this should really not take a full byte\r\n\r\np1_bp_counter_ones .rs 1;\r\np1_bp_counter_tens .rs 1;\r\np1_bp_counter_hundreds .rs 1;\r\np2_bp_counter_ones .rs 1;\r\np2_bp_counter_tens .rs 1;\r\np2_bp_counter_hundreds .rs 1;\r\n\r\nrate_count_frames .rs 1;\r\np1_bp_rate_count .rs 1;\r\np2_bp_rate_count .rs 1;\r\nbp_rate_count_times_4 .rs 1; TODO don't know how to do this any other way\r\n\r\n;TODO this is the best way i can think to store the calculated values\r\np1_bp_rate_ones .rs 1;\r\np1_bp_rate_tens .rs 1;\r\np1_bp_rate_tenths .rs 1;\r\np2_bp_rate_ones .rs 1;\r\np2_bp_rate_tens .rs 1;\r\np2_bp_rate_tenths .rs 1;\r\n\r\nmenu_game_time_s_ones .rs 1\r\nmenu_game_time_s_tens .rs 1\r\n\r\nFRAMES_PER_TENTH_SEC = 6 ; NTSC is 60 fps\r\nless_than_tenth_sec_counter .rs 1\r\n\r\n; Game seconds counter\r\ngame_timer_tenths .rs 1\r\ngame_timer_ones .rs 1\r\ngame_timer_tens .rs 1\r\n\r\nmash_button .rs 1;\r\nnew_frame .rs 1;\r\nscroll .rs 1;\r\nmenu_background_needs_loading .rs 1; not sure better way to do this\r\nbackground_row .rs 1 ; used to track where in the background data we left off in terms of row number\r\nbackground_high .rs 1 ; used as local vars to figure out which ppu address to write to\r\nbackground_low .rs 1 ;\r\nbackground_data_low .rs 1 ; used to track where in the background data we left off\r\nbackground_data_high .rs 1\r\n\r\n; Menu values\r\nNUM_PLAYERS_1_X = $70\r\nNUM_PLAYERS_2_X = $88\r\nNUM_PLAYER_CHOSER_X = $0207 ; Starts at 0204\r\n\r\nREG_MENU_OPTION_CHOOSER_Y = $0200\r\nREG_MENU_OPTION_CHOOSER_X = $0203\r\nMENU_OPTION_CHOOSER_X = $30\r\nMENU_NUM_PLAYERS_Y = $30\r\nMENU_MASH_BUTTON_Y = $40\r\nMENU_SECONDS_Y = $50\r\nMENU_START_Y = $60\r\n\r\n\r\n;;;;;;;;;;;;;;;\r\n\r\n .bank 0\r\n .org $C000\r\nRESET:\r\n SEI ; disable IRQs\r\n CLD ; disable decimal mode\r\n LDX #$40\r\n STX $4017 ; disable APU frame IRQ\r\n LDX #$FF\r\n TXS ; Set up stack\r\n INX ; now X = 0\r\n STX PPU_CTRL_REG1 ; disable NMI\r\n STX PPU_CTRL_REG2 ; disable rendering\r\n STX $4010 ; disable DMC IRQs\r\n\r\nvblankwait1: ; First wait for vblank to make sure PPU is ready\r\n BIT PPU_STATUS\r\n BPL vblankwait1\r\n\r\nclrmem:\r\n LDA #$00\r\n STA $0000, x\r\n STA $0100, x\r\n STA $0200, x\r\n STA $0400, x\r\n STA $0500, x\r\n STA $0600, x\r\n STA $0700, x\r\n LDA #$FE\r\n STA $0300, x\r\n INX\r\n BNE clrmem\r\n\r\nvblankwait2: ; Second wait for vblank, PPU is ready after this\r\n BIT PPU_STATUS\r\n BPL vblankwait2\r\n\r\n;MITCH\r\nInitState:\r\n ; Set default value\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n\r\n LDA #$01\r\n STA num_players\r\n LDA #BUTTON_A\r\n STA mash_button\r\n\r\n LDA #GAME_TITLE\r\n STA game_state\r\n LDA #GAME_TITLE ; TODO want states to disagree so that it'll load the first time\r\n STA prev_game_state\r\n\r\n JSR LoadMenuBackground\r\n JSR LoadTitleBackground\r\n\r\nLoadPalettes:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$3F\r\n STA PPU_ADDRESS ; write the high byte of $3F00 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $3F00 address\r\n LDX #$00 ; start out at 0\r\nLoadPalettesLoop:\r\n LDA palette, x ; load data from address (palette + the value in x)\r\n STA PPU_DATA ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites\r\n BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\n; if compare was equal to 128, keep going down\r\n JSR LoadMenuAttribute\r\n JSR LoadTitleAttribute\r\n\r\n LDA #%00011110 ; enable sprites, enable background, no clipping on left side\r\n STA PPU_CTRL_REG2\r\n\r\n LDA #$00\r\n STA scroll\r\n STA background_row\r\n JSR PushScrollToPPU\r\n JSR DisplayTitleScreen\r\n\r\nForever:\r\n LDA new_frame\r\n BNE ProcessFrame\r\n JMP Forever\r\nProcessFrame:\r\n LDA #00\r\n STA new_frame ; reset new frame\r\n LDA game_state\r\n CMP #GAME_TITLE\r\n BNE NotTitleLogic\r\n JSR TitleLogic\r\nNotTitleLogic:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_GAME\r\n BNE NotScrollingRight\r\n JSR IncrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToGame\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToGame:\r\n LDA #GAME_PLAY\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\n JSR DisplayScreen1 ; Set to display screen1\r\n JSR LoadGame ; load game sprites\r\n JMP FrameProcessed\r\nNotScrollingRight:\r\n LDA game_state\r\n CMP #GAME_SCROLL_TO_MENU\r\n BNE NotScrolling\r\n JSR DecrementScroll\r\n STX scroll\r\n CPX #$00\r\n BEQ DoneScrollingToMenu\r\n JSR PushScrollToPPU\r\n JMP FrameProcessed\r\nDoneScrollingToMenu:\r\n LDA #GAME_MENU\r\n STA game_state\r\n JSR PushScrollToPPU ; Reset scroll to 0\r\n JSR DisplayScreen0 ; Set to display screen 0\r\n JSR LoadMenu ; load menu sprites\r\n JMP FrameProcessed\r\nNotScrolling:\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BNE TryMenu\r\n JSR CalcGameTime ; In game\r\n JSR CalcButtonPresses\r\n JSR DrawFrameCount\r\n JSR RateDisplay\r\n JMP FrameProcessed\r\nTryMenu:\r\n LDA game_state\r\n CMP #GAME_MENU\r\n BNE TryGameOver\r\n JSR QueueGameBackground\r\n JSR MenuLogic\n JMP FrameProcessed\nTryGameOver:\n LDA game_state\n CMP #GAME_OVER\r\n BNE FrameProcessed\r\n JSR GameOverLogic\r\n JMP FrameProcessed\r\nFrameProcessed:\r\n LDX rate_count_frames\r\n INX\r\n STX rate_count_frames\r\n TXA\r\n AND #%00000111 ; on'y want to decrement so often\r\n CMP #$00\r\n BNE RateCountUpdated\r\n JSR DecrementP1Rate\r\n JSR DecrementP2Rate\r\nRateCountUpdated:\r\n JMP Forever ;jump back to Forever, infinite loop\r\n\r\nLoadMenuAttribute:\r\n LDA $2002 ; read PPU status to reset the high/low latch\r\n LDA #$23\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadMenuAttributeLoop\r\n RTS\r\n\r\nLoadGameAttribute:\r\n LDA $2002 ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadGameAttributeLoop:\r\n LDA game_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadGameAttributeLoop\r\n RTS\r\n\r\nLoadTitleAttribute:\r\n LDA $2002 ; read PPU status to reset the high/low latch\r\n LDA #$27\r\n STA PPU_ADDRESS ; write the high byte of $23C0 address\r\n LDA #$C0\r\n STA PPU_ADDRESS ; write the low byte of $23C0 address\r\n LDX #$00 ; start out at 0\r\nLoadTitleAttributeLoop:\r\n LDA title_attribute, x ; normally load data from address (attribute + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$40 ; 64 total bytes necessary to do full screen\r\n BNE LoadTitleAttributeLoop\r\n RTS\r\n\r\nDecrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP1RateDone\r\n DEX\r\n STX p1_bp_rate_count\r\nDecrementP1RateDone:\r\n RTS\r\n\r\nDecrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$00\r\n BEQ DecrementP2RateDone\r\n DEX\r\n STX p2_bp_rate_count\r\nDecrementP2RateDone:\r\n RTS\r\n\r\nIncrementP1Rate:\r\n LDX p1_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP1RateDone\r\n INX\r\n STX p1_bp_rate_count\r\nIncrementP1RateDone:\r\n RTS\r\n\r\nIncrementP2Rate:\r\n LDX p2_bp_rate_count\r\n CPX #$08\r\n BEQ IncrementP2RateDone\r\n INX\r\n STX p2_bp_rate_count\r\nIncrementP2RateDone:\r\n RTS\r\n\nIncrementScroll:\n LDX scroll\n INX\n INX\n INX\n INX\n RTS\n\nDecrementScroll:\n LDX scroll\n DEX\n DEX\n DEX\n DEX\n RTS\n\r\nDisplayScreen0:\n LDA #%10011000\r\n STA PPU_CTRL_REG1\n RTS\n\nDisplayScreen1:\r\n LDA #%10011001\r\n STA PPU_CTRL_REG1\r\n RTS\n\nDisplayTitleScreen:\n LDA #%10001001\n STA PPU_CTRL_REG1\n RTS\n\r\nPushScrollToPPU:\r\n LDA #$00\r\n STA PPU_ADDRESS ; clean up PPU address registers\r\n STA PPU_ADDRESS\r\n LDA scroll ; horizontal scroll full\r\n STA PPU_SCROLL_REG\r\n LDA #$00 ; no vertical scrolling\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nNMI:\r\n LDA #$00\r\n STA PPU_SPR_ADDR ; set the low byte (00) of the RAM address\r\n LDA #$02\r\n STA $4014 ; set the high byte (02) of the RAM address, start the transfer\r\n\r\n JSR ReadController1\r\n JSR ReadController2\r\n\r\n LDA #01\r\n STA new_frame ; Tell forever loop that theres a new set of input to process\r\n\r\n; TODO think it'd be better to just load it once and store result in A\r\nGameLogic\r\n LDA game_state\r\n CMP #GAME_PLAY\r\n BEQ GameLogicPlay\r\n JMP EndGameLogic\r\nGameLogicPlay:\r\n LDA game_timer_ones\r\n CMP menu_game_time_s_ones\r\n BNE EndGameLogic\r\n LDA menu_game_time_s_tens\r\n CMP game_timer_tens\r\n BNE EndGameLogic\r\n ;;;; Just hit the game over time so call the game over\r\n LDA #GAME_OVER\r\n STA game_state\r\n JSR DisplayGameOver\r\n JSR DisplayFinalRate\r\nEndGameLogic:\r\n RTI ; return from interrupt\r\n\r\nDrawFrameCount:\r\n LDA game_timer_tenths\r\n STA DIPLAY_GT_TENTHS_TILES\r\n LDA game_timer_ones\r\n STA DIPLAY_GT_ONES_TILES\r\n LDA game_timer_tens\r\n STA DIPLAY_GT_TENS_TILES\r\nDrawButtonPresses:\r\n LDA p1_bp_counter_ones\r\n STA DISPLAY_P1_BP_ONES_TILE\r\n LDA p1_bp_counter_tens\r\n STA DISPLAY_P1_BP_TENS_TILE\r\n LDA p1_bp_counter_hundreds\r\n STA DISPLAY_P1_BP_HUNDREDS_TILE\r\n LDA p2_bp_counter_ones\r\n STA DISPLAY_P2_BP_ONES_TILE\r\n LDA p2_bp_counter_tens\r\n STA DISPLAY_P2_BP_TENS_TILE\r\n LDA p2_bp_counter_hundreds\r\n STA DISPLAY_P2_BP_HUNDREDS_TILE\r\n RTS\r\n\r\nCalcButtonPresses:\r\n LDA p1_in_press\r\n CMP #$01\r\n BEQ CheckButtonUnPressed\r\n LDA p1_buttons\r\n AND mash_button\r\n CMP mash_button\r\n BNE P1DoneBPCalc ; branch if button not down\r\n LDA #$01\r\n STA p1_in_press ; button is pressed\r\n ; We have a new press\r\n JSR IncrementP1Rate\r\n LDX p1_bp_counter_ones\r\n INX\r\n STX p1_bp_counter_ones\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p1_bp_counter_ones\r\n LDX p1_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p1_bp_counter_tens\r\n CPX #$0A\r\n BNE P1DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p1_bp_counter_tens\r\n LDX p1_bp_counter_hundreds\r\n INX\r\n STX p1_bp_counter_hundreds\r\nCheckButtonUnPressed:\r\n LDA p1_buttons\r\n AND mash_button\r\n BNE P1DoneBPCalc\r\n ;; buttons unpressed\r\n LDA #$00\r\n STA p1_in_press\r\nP1DoneBPCalc:\r\n LDA p2_buttons_new_press\r\n AND mash_button\r\n BEQ P2DoneBPCalc ; branch if button not down\r\n JSR IncrementP2Rate\r\n LDX p2_bp_counter_ones ; We have a new press\r\n INX\r\n STX p2_bp_counter_ones\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 9\r\n LDA #00\r\n STA p2_bp_counter_ones\r\n LDX p2_bp_counter_tens\r\n INX ; TODO i think there might be a way to do this in place\r\n STX p2_bp_counter_tens\r\n CPX #$0A\r\n BNE P2DoneBPCalc ; if we went over 99\r\n LDA #00\r\n STA p2_bp_counter_tens\r\n LDX p2_bp_counter_hundreds\r\n INX\r\n STX p2_bp_counter_hundreds\r\nP2DoneBPCalc:\r\n RTS\r\n\r\nCalcGameTime:\r\n LDX less_than_tenth_sec_counter\r\n INX\r\n STX less_than_tenth_sec_counter\r\n CPX #FRAMES_PER_TENTH_SEC\r\n BNE DoneGameTimeCalc\r\n LDA #$00\r\n STA less_than_tenth_sec_counter\r\n LDX game_timer_tenths\r\n INX\r\n STX game_timer_tenths\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 9\r\n LDA #00\r\n STA game_timer_tenths\r\n LDX game_timer_ones\r\n INX\r\n STX game_timer_ones\r\n CPX #$0A\r\n BNE DoneGameTimeCalc ; if we went over 99\r\n LDA #00\r\n STA game_timer_ones\r\n LDX game_timer_tens\r\n INX\r\n STX game_timer_tens\r\nDoneGameTimeCalc:\r\n RTS\r\n\r\nGameOverLogic:\r\n LDX game_over_frame_counter\r\n CPX #GAME_OVER_WAIT_FRAMES\r\n BEQ GameOverWaitDone\r\n INX\r\n STX game_over_frame_counter\r\n JMP GameOverLogicDone\r\nGameOverWaitDone:\r\n JSR DisplayPressStart\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ GameOverLogicDone\r\n ;; Wait is over and button is pressed so go back to menu\r\n LDA #GAME_SCROLL_TO_MENU\r\n STA game_state\r\n JSR MoveSpritesOffScreen\r\nGameOverLogicDone:\r\n RTS\r\n\r\nMenuLogic:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_MASH_BUTTON_Y\r\n BNE NotChoosingMashButton\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingNextMashButton\r\n JSR ToggleNextMashButton\r\n JMP MenuLogicDone\r\nNotChoosingNextMashButton:\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotChoosingMashButton\r\n JSR TogglePrevMashButton\r\n JMP MenuLogicDone\r\nNotChoosingMashButton:\r\n LDA #BUTTON_SELECT\r\n ORA #BUTTON_DOWN\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuDownButton\r\n JSR ToggleNextMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuDownButton:\r\n LDA #BUTTON_UP\r\n AND p1_buttons_new_press\r\n BEQ NotToggleMenuUpButton\r\n JSR TogglePrevMenuItem ; just toggle menu button\r\n JMP MenuLogicDone\r\nNotToggleMenuUpButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_NUM_PLAYERS_Y\r\n BNE NotToggleNumPlayers\r\n LDA #TOGGLE_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotToggleNumPlayers\r\n JSR ToggleNumPlayers\r\n JMP MenuLogicDone\r\nNotToggleNumPlayers:\r\nNotMashButton:\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_SECONDS_Y\r\n BNE NotMenuSecondsOption\r\n LDA #TOGGLE_PREV_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ MenuSecOptionCheckIncrease\r\n JSR TogglePrevTime\r\n JMP MenuLogicDone\r\nMenuSecOptionCheckIncrease:\r\n LDA #TOGGLE_NEXT_BUTTONS\r\n AND p1_buttons_new_press\r\n BEQ NotMenuSecondsOption\r\n JSR ToggleNextTime\r\n JMP MenuLogicDone\r\nMenuSecIncreaseNoFullWrap:\r\n LDA menu_game_time_s_ones\r\n CMP #$09\r\n BNE MenuSecSimpleIncrease\r\n ; Wrap the tens\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDX menu_game_time_s_tens\r\n INX\r\n STX menu_game_time_s_tens\r\n JMP MenuLogicDone\r\nMenuSecSimpleIncrease:\r\n LDX menu_game_time_s_ones\r\n INX\r\n STX menu_game_time_s_ones\r\n JMP MenuLogicDone\r\nNotMenuSecondsOption:\r\n ;if start, if start, start\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CMP #MENU_START_Y\r\n BNE MenuLogicDone\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n BEQ MenuLogicDone\r\n LDA #GAME_SCROLL_TO_GAME ; start the game\r\n STA game_state\r\n JSR LoadGameAttribute\r\n JSR MoveSpritesOffScreen\r\n JMP MenuLogicDone\r\nMenuLogicDone:\r\n RTS\r\n\r\nToggleNextMenuItem\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_START_Y\r\n BEQ GoBackToFirstMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n CLC ; clear carry\r\n ADC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneToggleNextMenuItem\r\nGoBackToFirstMenuItem:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneToggleNextMenuItem:\r\n RTS\r\n\r\nTogglePrevMenuItem\r\n LDX REG_MENU_OPTION_CHOOSER_Y\r\n CPX #MENU_NUM_PLAYERS_Y\r\n BEQ GoBackToLastMenuItem\r\n LDA REG_MENU_OPTION_CHOOSER_Y\r\n SEC ; set clear carry bit\r\n SBC #$10 ; shift down 2 16 pixels\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n JMP DoneTogglePrevMenuItem\r\nGoBackToLastMenuItem:\r\n LDA #MENU_START_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\nDoneTogglePrevMenuItem:\r\n RTS\r\n\r\n; TODO probably a less sloppy way than having separate next/prev\r\n; A->B->Start->Select->Down+B->A\r\nToggleNextMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE ToggleNextMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryB:\r\n CMP #BUTTON_B\r\n BNE ToggleNextMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE ToggleNextMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTrySelect\r\n CMP #BUTTON_SELECT\r\n BNE ToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndToggleNextMashButton\r\nToggleNextMashButtonTryDownB\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on DownB\r\nEndToggleNextMashButton:\r\n RTS\r\n\r\n; A<-B<-Start<-Select<-Down+B<-A\r\nTogglePrevMashButton:\r\n LDA mash_button\r\n CMP #BUTTON_A\r\n BNE TogglePrevMashButtonTryDownB\r\n JSR LoadMashButtonDownB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryDownB:\r\n CMP #BUTTON_DOWN_B\r\n BNE TogglePrevMashButtonTrySelect\r\n JSR LoadMashButtonSelect\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTrySelect:\r\n CMP #BUTTON_SELECT\r\n BNE TogglePrevMashButtonTryStart\r\n JSR LoadMashButtonStart\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryStart:\r\n CMP #BUTTON_START\r\n BNE TogglePrevMashButtonTryB\r\n JSR LoadMashButtonB\r\n JMP EndTogglePrevMashButton\r\nTogglePrevMashButtonTryB:\r\n JSR LoadMashButtonA ; None other to try so no need to verify we're on B\r\nEndTogglePrevMashButton:\r\n RTS\r\n\r\nToggleNumPlayers:\r\n LDA num_players\r\n EOR #%00000011 ; ignore first 6 bits. last two either 1 or 2 (01 or 10)\r\n STA num_players\r\n JSR UpdateNumPlayersArrow\r\n RTS\r\n\r\nUpdateNumPlayersArrow:\r\n LDA num_players\r\n CMP #$02\r\n BEQ UpdateNumPlayersArrowTo2\r\n LDA #NUM_PLAYERS_1_X\r\n STA NUM_PLAYER_CHOSER_X\r\n JMP UpdateNumPlayersArrowDone\r\nUpdateNumPlayersArrowTo2:\r\n LDA #NUM_PLAYERS_2_X\r\n STA NUM_PLAYER_CHOSER_X\r\nUpdateNumPlayersArrowDone:\r\n RTS\r\n\r\nTogglePrevTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo5\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo2\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo1\r\n ; we know we're at 1\r\n JMP ToggleTimeTo10\r\nToggleNextTime:\r\n LDA menu_game_time_s_ones\r\n CMP #$00 ; 10\r\n BEQ ToggleTimeTo1\r\n CMP #$05 ; 5\r\n BEQ ToggleTimeTo10\r\n CMP #$02 ; 2\r\n BEQ ToggleTimeTo5\r\n ; we know we're at 1\r\n JMP ToggleTimeTo2\r\nToggleTimeTo1:\r\n LDA #$01\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo2:\r\n LDA #$02\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo5:\r\n LDA #$05\r\n STA menu_game_time_s_ones\r\n LDA #$00\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nToggleTimeTo10:\r\n LDA #$00\r\n STA menu_game_time_s_ones\r\n LDA #$01\r\n STA menu_game_time_s_tens\r\n JMP UpdateMenuTime\r\nUpdateMenuTime:\r\n LDA menu_game_time_s_ones\r\n STA $020D\r\n LDA menu_game_time_s_tens\r\n STA $0209\r\n RTS\r\n\r\nLoadMenu:\r\nLoadMenuOptionChooser:\r\n LDA #MENU_NUM_PLAYERS_Y\r\n STA REG_MENU_OPTION_CHOOSER_Y\r\n LDA #$28 ; Arrow\r\n STA $0201 ; This whole block is a mess\r\n LDA #$00 ; attribute\r\n STA $0202\r\n LDA #$18 ; X position\r\n STA $0203\r\nLoadNumPlayerArrow:\r\n LDX #$00 ; start at 0\r\nLoadNumPlayerArrowLoop:\r\n LDA num_player_arrow, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$04 ;\r\n BNE LoadNumPlayerArrowLoop\r\n\r\n JSR UpdateNumPlayersArrow\r\n\r\nLoadMenuGameTime:\r\n LDX #$00\r\nLoadMenuGameTimeLoop:\r\n LDA menu_game_time, x\r\n STA $0208, x\r\n INX\r\n CPX #$08 ; 2 sprites (tens and ones)\r\n BNE LoadMenuGameTimeLoop\r\n JSR UpdateMenuTime\r\n\r\nLoadMashButtonDisplay\r\n LDX #$00\r\nLoadMashButtonDisplayLoop:\r\n LDA menu_button_choice, x\r\n STA $0210, x\r\n INX\r\n CPX #$18 ; 6 sprites (MAX word is 'select')\r\n BNE LoadMashButtonDisplayLoop\r\n\r\n ;TODO this is hacky. do this smarter\r\n JSR ToggleNextMashButton\r\n JSR TogglePrevMashButton\r\n RTS\r\n\r\nLoadMenuBackground:\r\n LDA PPU_STATUS ; read PPU status to reset the high/low latch\r\n LDA #$20\r\n STA PPU_ADDRESS ; write the high byte of $2000 address\r\n LDA #$00\r\n STA PPU_ADDRESS ; write the low byte of $2000 address\r\n LDX #$00 ; start out at 0\r\nLoadMenuBackground1Loop:\r\n LDA menu_background_1, x; load data from address (background + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground1Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground2Loop:\r\n LDA menu_background_2, x; load data from address (background + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground2Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground3Loop:\r\n LDA menu_background_3, x; load data from address (background + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$00 ; load all background tiles\r\n BNE LoadMenuBackground3Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\nLoadMenuBackground4Loop:\r\n LDA menu_background_4, x; load data from address (background + the value in x)\r\n STA $2007 ; write to PPU\r\n INX ; X = X + 1\r\n CPX #$C0 ; load all background tiles 6*32 = xC0\r\n BNE LoadMenuBackground4Loop ; Branch to LoadBackgroundLoop if compare was Not Equal to zero\r\n RTS\r\n\r\nLoadGameBackgroundRow:\r\n ; 256 / (4 bytes per sprite) = 64 bytes per low pointer locations\r\n LDA background_row\r\n LSR A\r\n LSR A\r\n LSR A ; divide by 8 to get the high pointer location\r\n CLC\r\n ADC #$24 ; all highs start at 24 (low starts at 0)\r\n STA background_high\r\n LDA background_row\r\n AND #%00001111 ; take mod 8 to get the low pointer location\r\n CLC\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A\r\n ASL A ; multiply by 32 to get the starting low point\r\n STA background_low\r\n ;; Setup the location to write to\r\n LDA PPU_STATUS\r\n LDA background_high\r\n STA PPU_ADDRESS\r\n LDA background_low\r\n STA PPU_ADDRESS\r\n ;; Setup the background data to write to it\r\n LDA background_low\r\n CLC\r\n ADC #LOW(game_background)\r\n STA background_data_low\r\n LDA background_high\r\n ADC #HIGH(game_background) ; includes carry from the low add\r\n SEC\r\n SBC #$24 ; really hacky, but high has the extra 24 tacked on because its a ppu address\r\n STA background_data_high\r\n LDY #$00\r\nLoadGameBackgroundRowLoop:\r\n LDA [background_data_low], y\r\n STA $2007\r\n INY\r\n CPY #$40 ; 64\r\n BNE LoadGameBackgroundRowLoop\r\n LDX background_row\r\n INX\r\n STX background_row\r\n CPX #$1E ; 30\r\n BNE LoadGameBackgroundRowDone\r\n LDX #$00\r\n STX menu_background_needs_loading\r\n STX background_row\r\nLoadGameBackgroundRowDone:\r\n LDA #$00\r\n STA PPU_SCROLL_REG\r\n STA PPU_SCROLL_REG\r\n RTS\r\n\r\nTitleLogic:\r\n LDA p1_buttons_new_press\r\n AND #BUTTON_START\r\n CMP #$00\r\n BEQ TitleLogicDone\r\n LDA #GAME_MENU\r\n STA game_state\r\n LDA #$01\r\n STA menu_background_needs_loading ; mark menu to be loaded\r\n JSR LoadMenu\r\n JSR DisplayScreen0\r\nTitleLogicDone:\r\n RTS\r\n\r\nQueueGameBackground:\r\n LDA menu_background_needs_loading\r\n CMP #$00\r\n BEQ QueueGameBackgroundDone\r\n JSR LoadGameBackgroundRow\r\n JSR DisplayScreen0 ; don't know why above is changing screen, but this will fix it\r\nQueueGameBackgroundDone:\r\n RTS\r\n\r\nLoadTitleBackground:\r\n LDA PPU_STATUS\r\n LDA #$24\r\n STA PPU_ADDRESS\r\n LDA #$00\r\n STA PPU_ADDRESS\r\n LDX #$00\r\nLoadTitleBackground1Loop:\r\n LDA title_background_1, x\r\n STA $2007\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground1Loop\r\nLoadTitleBackground2Loop:\r\n LDA title_background_2, x\r\n STA $2007\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground2Loop\r\nLoadTitleBackground3Loop:\r\n LDA title_background_3, x\r\n STA $2007\r\n INX\r\n CPX #$00\r\n BNE LoadTitleBackground3Loop\r\nLoadTitleBackground4Loop:\r\n LDA title_background_4, x\r\n STA $2007\r\n INX\r\n CPX #$C0\r\n BNE LoadTitleBackground4Loop\r\n RTS\r\n\r\nLoadGame:\r\n JSR MoveSpritesOffScreen ; TODO make sure this happens the same sort of way of going back to menu\r\n\r\n LDA #$00\r\n STA game_timer_tenths\r\n STA game_timer_ones\r\n STA game_timer_tens\r\n STA game_over_frame_counter\r\n STA p1_in_press\r\n STA p2_in_press\r\n STA p1_bp_rate_count\r\n\r\nLoadP1Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP1SpritesLoop:\r\n LDA sprites, x ; load data from address (sprites + x)\r\n STA $0204, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$1C ; Compare X to hex $1C, decimal 28 -> 7 chars, 4 bytes each\r\n BNE LoadP1SpritesLoop\r\n\r\n LDA #$00\r\n STA p1_bp_counter_ones\r\n STA p1_bp_counter_tens\r\n STA p1_bp_counter_hundreds\r\n STA p2_bp_counter_ones\r\n STA p2_bp_counter_tens\r\n STA p2_bp_counter_hundreds\r\n\r\n LDA num_players\r\n CMP #$02\r\n BNE SkipP2\r\nLoadP2Sprites:\r\n LDX #$00 ; start at 0\r\nLoadP2SpritesLoop:\r\n LDA p2_sprites, x ; load data from address (sprites + x)\r\n STA $0220, x ; store into RAM address ($0200 + x)\r\n INX ; X = X + 1\r\n CPX #$18 ; Compare X to hex $20, decimal 32\r\n BNE LoadP2SpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero\r\n ; if compare was equal to 32, keep going down\r\n\r\nSkipP2:\r\nLoadP1Label:\r\n LDX #$00\r\nLoadP1LabelLoop:\r\n LDA p1_label, x\r\n STA $0238, x\r\n INX\r\n CPX #$0C ; 3 sprites\r\n BNE LoadP1LabelLoop\r\n RTS\r\n\r\nDisplayGameOver:\r\n LDX #$00\r\nDisplayGameTextLoop:\r\n LDA game_text, x\r\n STA $0244, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayGameTextLoop\r\n LDX #$00\r\nDisplayOverTextLoop:\r\n LDA over_text, x\r\n STA $0254, x\r\n INX\r\n CPX #$10 ; 16 -> 4 sprites\r\n BNE DisplayOverTextLoop\r\n RTS\r\n\r\nDisplayPressStart:\r\n LDX #$00\r\nDisplayPressTextLoop:\r\n LDA press_text, x\r\n STA $02A4, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayPressTextLoop\r\n LDX #$00\r\nDisplayStartTextLoop:\r\n LDA start_press_text, x\r\n STA $02B8, x\r\n INX\r\n CPX #$14 ; 20 -> 5 sprites\r\n BNE DisplayStartTextLoop\r\n RTS\r\n\r\nDisplayFinalRate:\r\n JSR DisplayP1FinalRate\r\n LDA num_players\r\n CMP #$02\r\n BNE DisplayFinalRateSkipP2\r\n JSR DisplayP2FinalRate\r\nDisplayFinalRateSkipP2:\r\n RTS\r\n\r\nDisplayP1FinalRate:\r\n JSR CalculateP1FinalRate\r\n LDX #$00\r\nDisplayP1FinalRateLoop:\r\n LDA p1_final_rate, x\r\n STA $02CC, x\r\n INX\r\n CPX #$18 ; 6 sprites, but skip decimal below\r\n BNE DisplayP1FinalRateLoop\r\n LDA p1_bp_rate_tens\r\n STA $02CD\r\n LDA p1_bp_rate_ones\r\n STA $02D1\r\n LDA p1_bp_rate_tenths\r\n STA $02D9\r\n RTS\r\n\r\nDisplayP2FinalRate:\r\n JSR CalculateP2FinalRate\r\n LDX #$00\r\nDisplayP2FinalRateLoop:\r\n LDA p2_final_rate, x\r\n STA $02E4, x\r\n INX\r\n CPX #$18 ; 4 sprites, but skip decimal below\r\n BNE DisplayP2FinalRateLoop\r\n LDA p2_bp_rate_tens\r\n STA $02E5\r\n LDA p2_bp_rate_ones\r\n STA $02E9\r\n LDA p2_bp_rate_tenths\r\n STA $02F1\r\nDisplayP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP1FinalRateTry2\r\n JSR CalculateP1FinalRate_1_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP1FinalRateTry5\r\n JSR CalculateP1FinalRate_2_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP1FinalRateTry10\r\n JSR CalculateP1FinalRate_5_Sec\r\n JMP CalculateP1FinalRateDone\r\nCalculateP1FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP1FinalRate_10_Sec\r\nCalculateP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_1_Sec:\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP1FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p1_bp_counter_ones\r\n LSR A\r\n STA p1_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p1_bp_rate_tenths\r\n BCC P1FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_tenths\r\nP1FinalRate2SecNoOnesCarry:\r\n LDA p1_bp_counter_tens\r\n LSR A\r\n STA p1_bp_rate_tens\r\n BCC P1FinalRate2SecNoTensCarry\r\n LDA p1_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p1_bp_rate_ones\r\nP1FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP1FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p1_bp_counter_hundreds\r\n ASL A\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n ASL A\r\n STA p1_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP1FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p1_bp_rate_ones\r\n LDX p1_bp_rate_tens\r\n INX\r\n STX p1_bp_rate_tens\r\nCalcP1FinalRate5SecTensLess10:\r\n LDA p1_bp_counter_ones\r\n ASL A\r\n STA p1_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP1FinalRateDone\r\n SBC #$0A\r\n STA p1_bp_rate_tenths\r\n LDX p1_bp_rate_ones\r\n INX\r\n STX p1_bp_rate_ones\r\nCalcP1FinalRateDone:\r\n RTS\r\n\r\nCalculateP1FinalRate_10_Sec:\r\n LDA p1_bp_counter_hundreds\r\n STA p1_bp_rate_tens\r\n LDA p1_bp_counter_tens\r\n STA p1_bp_rate_ones\r\n LDA p1_bp_counter_ones\r\n STA p1_bp_rate_tenths\r\n RTS\r\n\r\n; TODO there has to be a better way than duplicating all this logic for the p2 rate\r\nCalculateP2FinalRate\r\n LDA menu_game_time_s_ones\r\n CMP #$01\r\n BNE CalculateP2FinalRateTry2\r\n JSR CalculateP2FinalRate_1_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry2:\r\n CMP #$02\r\n BNE CalculateP2FinalRateTry5\r\n JSR CalculateP2FinalRate_2_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry5:\r\n CMP #$05\r\n BNE CalculateP2FinalRateTry10\r\n JSR CalculateP2FinalRate_5_Sec\r\n JMP CalculateP2FinalRateDone\r\nCalculateP2FinalRateTry10: ; None left so it is 10\r\n JSR CalculateP2FinalRate_10_Sec\r\nCalculateP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_1_Sec:\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\nCalculateP2FinalRate_2_Sec: ; 2x30 = 60 max\r\n LDA p2_bp_counter_ones\r\n LSR A\r\n STA p2_bp_rate_ones ; TODO account for odd tens\r\n LDA #$00\r\n STA p2_bp_rate_tenths\r\n BCC P2FinalRate2SecNoOnesCarry ; if ones shift left a carry, add 5 to tenths\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_tenths\r\nP2FinalRate2SecNoOnesCarry:\r\n LDA p2_bp_counter_tens\r\n LSR A\r\n STA p2_bp_rate_tens\r\n BCC P2FinalRate2SecNoTensCarry\r\n LDA p2_bp_rate_ones ; Add the 5 carry over\r\n CLC\r\n ADC #$05\r\n STA p2_bp_rate_ones\r\nP2FinalRate2SecNoTensCarry:\r\n RTS\r\n\r\nCalculateP2FinalRate_5_Sec: ; max is 5*30 = 150. Mult by 2 then divide by 10\r\n LDA p2_bp_counter_hundreds\r\n ASL A\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n ASL A\r\n STA p2_bp_rate_ones\r\n CMP #$0A\r\n BCC CalcP2FinalRate5SecTensLess10\r\n SBC #$0A ; Shouldn't be more than 18 so only need to subtract 10\r\n STA p2_bp_rate_ones\r\n LDX p2_bp_rate_tens\r\n INX\r\n STX p2_bp_rate_tens\r\nCalcP2FinalRate5SecTensLess10:\r\n LDA p2_bp_counter_ones\r\n ASL A\r\n STA p2_bp_rate_tenths\r\n CMP #$0A\r\n BCC CalcP2FinalRateDone\r\n SBC #$0A\r\n STA p2_bp_rate_tenths\r\n LDX p2_bp_rate_ones\r\n INX\r\n STX p2_bp_rate_ones\r\nCalcP2FinalRateDone:\r\n RTS\r\n\r\nCalculateP2FinalRate_10_Sec:\r\n LDA p2_bp_counter_hundreds\r\n STA p2_bp_rate_tens\r\n LDA p2_bp_counter_tens\r\n STA p2_bp_rate_ones\r\n LDA p2_bp_counter_ones\r\n STA p2_bp_rate_tenths\r\n RTS\r\n\r\n ; End p2 rate logic\r\n\r\nRateDisplay:\r\n JSR P1RateDisplay\r\n LDA num_players\r\n CMP #$02\r\n BNE RateDisplaySkipP2\r\n JSR P2RateDisplay\r\nRateDisplaySkipP2:\r\n RTS\r\n\r\n;TODO small bug where if it goes back to 0, something shows up\r\nP1RateDisplay:\r\n LDA p1_bp_rate_count\r\n CMP #$00\r\n BEQ P1RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP1RateDisplayLoop:\r\n LDA p1_rate_meter, x\r\n STA $0264, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P1RateDisplayLoop\r\n CPX #$20\r\n BEQ P1RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP1RateHideLoop:\r\n LDA #$F8\r\n STA $0264, x\r\n INX\r\n CPX #$20\r\n BNE P1RateHideLoop ; TODO this will always write over the last sprite\r\nP1RateDisplayDone:\r\n RTS\r\n\r\nP2RateDisplay:\r\n LDA p2_bp_rate_count\r\n CMP #$00\r\n BEQ P2RateHideLoop\r\n ASL A\r\n ASL A\r\n STA bp_rate_count_times_4\r\n LDX #$00\r\nP2RateDisplayLoop:\r\n LDA p2_rate_meter, x\r\n STA $0284, x\r\n INX\r\n CPX bp_rate_count_times_4 ; 32 -> 8 sprites\r\n BNE P2RateDisplayLoop\r\n CPX $20\r\n BEQ P2RateDisplayDone ; if we already drew 8 sprites, then skip the 'hide' state\r\nP2RateHideLoop:\r\n LDA #$F8\r\n STA $0284, x\r\n INX\r\n CPX #$20\r\n BNE P2RateHideLoop ; TODO this will always write over the last sprite\r\nP2RateDisplayDone:\r\n RTS\r\n\r\n; TODO there has to be a better way to do this\r\nLoadMashButtonDownB\r\n LDA #BUTTON_DOWN_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonDownBLoop:\r\n LDA down_b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonDownBLoop\r\n RTS\r\n\r\nLoadMashButtonA\r\n LDA #BUTTON_A\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonALoop:\r\n LDA a_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonALoop\r\n RTS\r\n\r\nLoadMashButtonB\r\n LDA #BUTTON_B\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonBLoop:\r\n LDA b_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonBLoop\r\n RTS\r\n\r\nLoadMashButtonSelect\r\n LDA #BUTTON_SELECT\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonSelectLoop:\r\n LDA select_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonSelectLoop\r\n RTS\r\n\r\nLoadMashButtonStart\r\n LDA #BUTTON_START\r\n STA mash_button\r\n LDX #$00\r\n LDY #$00\r\nLoadMashButtonStartLoop:\r\n LDA start_text, x\r\n STA $0211, y\r\n INX\r\n INY\r\n INY\r\n INY\r\n INY ; There has to be a better way to do this\r\n CPX #$06\r\n BNE LoadMashButtonStartLoop\r\n RTS\r\n\r\nMoveSpritesOffScreen:\r\n LDX #$00\r\n LDA #$F0 ; Off screen in Y direction\r\nMoveSpritesOffScreenLoop:\r\n STA $0200, x ; Put all sprites in a Y off screen position\r\n INX\r\n INX\r\n INX\r\n INX\r\n CPX #$00 ; 0 == 256 -> 4*(64 sprites)\r\n BNE MoveSpritesOffScreenLoop\r\n RTS\r\n\r\nReadController1:\r\n LDA p1_buttons\r\n STA p1_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController1Loop:\r\n LDA CONTROLLER_PORT1\r\n LSR A ; bit0 -> Carry\r\n ROL p1_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController1Loop\r\n ; store what was newly pressed (not working)\r\n LDA p1_buttons\r\n EOR p1_prev_buttons\r\n AND p1_buttons\r\n STA p1_buttons_new_press\r\n RTS\r\n\r\nReadController2:\r\n LDA p2_buttons\r\n STA p2_prev_buttons ; backup the previous buttons\r\n LDA #$01\r\n STA CONTROLLER_PORT1\r\n LDA #$00\r\n STA CONTROLLER_PORT1\r\n LDX #$08\r\nReadController2Loop:\r\n LDA CONTROLLER_PORT2\r\n LSR A ; bit0 -> Carry\r\n ROL p2_buttons ; bit0 <- Carry\r\n DEX\r\n BNE ReadController2Loop\r\n ; store what was newly pressed (not working)\r\n LDA p2_buttons\r\n EOR p2_prev_buttons\r\n AND p2_buttons\r\n STA p2_buttons_new_press\r\n RTS\r\n\r\n; ###############################\r\n; Background/tile loading\r\n; ###############################\r\n .bank 1\r\n .org $D000\r\n .org $E000\r\npalette:\r\n .db $0F,$30,$07,$16,$0F,$10,$00,$16,$38,$39,$3A,$3B,$3C,$3D,$3E,$0F ;background palette data\r\n .db $0F,$30,$07,$16,$31,$02,$38,$3C,$0F,$1C,$15,$14,$31,$02,$38,$3C ;sprite palette data\r\n\r\npress_b_to_start:\r\n .db $19,$1B\r\n\r\nsprites:\r\n ;vert tile attr horiz\r\n .db $50, $00, $00, $80 ;p1 hundreds bp count\r\n .db $50, $00, $00, $88 ;p1 tens bp count\r\n .db $50, $00, $00, $90 ;p1 ones bp count\r\n .db $60, $00, $00, $78 ;tens game timer\r\n .db $60, $00, $00, $80 ;ones game timer\r\n .db $60, $AF, $00, $88 ;decimal point\r\n .db $60, $00, $00, $90 ;tenths game timer\r\n\r\np2_sprites:\r\n .db $70, $00, $00, $80 ;p2 hundreds game timer\r\n .db $70, $00, $00, $88 ;p2 tens game timer\r\n .db $70, $00, $00, $90 ;p2 ones game timer\r\n .db $70, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $70, $02, $00, $68 ; '2'\r\n .db $70, $28, $00, $70 ; '-'\r\n\r\np1_label:\r\n .db $50, $19, $00, $60 ; 'p' TODO these should go in the background\r\n .db $50, $01, $00, $68 ; '1'\r\n .db $50, $28, $00, $70 ; '-'\r\n\r\nnum_player_arrow:\r\n .db $30, $28, $00, $70\r\n\r\nmenu_game_time\r\n .db $50, $01, $00, $88 ;tens\r\n .db $50, $02, $00, $90 ;ones\r\n\r\nmenu_button_choice\r\n .db $40, $0A, $00, $78\r\n .db $40, $0A, $00, $80\r\n .db $40, $0A, $00, $88\r\n .db $40, $0A, $00, $90\r\n .db $40, $0A, $00, $98\r\n .db $40, $0A, $00, $A0\r\n\r\ngame_text\r\n .db $A0, $10, $00, $58\r\n .db $A0, $0A, $00, $60\r\n .db $A0, $16, $00, $68\r\n .db $A0, $0E, $00, $70\r\n\r\nover_text\r\n .db $A0, $18, $00, $80\r\n .db $A0, $1F, $00, $88\r\n .db $A0, $0E, $00, $90\r\n .db $A0, $1B, $00, $98\r\n\r\npress_text\r\n .db $B0, $19, $00, $68\r\n .db $B0, $1B, $00, $70\r\n .db $B0, $0E, $00, $78\r\n .db $B0, $1C, $00, $80\r\n .db $B0, $1C, $00, $88\r\n\r\nstart_press_text ; Don't love this name, but start_text is already used\r\n .db $B8, $1C, $00, $68\r\n .db $B8, $1D, $00, $70\r\n .db $B8, $0A, $00, $78\r\n .db $B8, $1B, $00, $80\r\n .db $B8, $1D, $00, $88\r\n\r\nup_text\r\n .db $1E, $19, $24, $24, $24, $24\r\n\r\ndown_text\r\n .db $0D, $18, $20, $17, $24, $24\r\n\r\nleft_text\r\n .db $15, $0E, $0F, $1D, $24, $24\r\n\r\nright_text\r\n .db $1B, $12, $10, $11, $1D, $24\r\n\r\nstart_text:\r\n .db $1C, $1D, $0A, $1B, $1D, $24\r\n\r\nselect_text:\r\n .db $1C, $0E, $15, $0E, $0C, $1D\r\n\r\na_text\r\n .db $0A, $24, $24, $24, $24, $24\r\n\r\nb_text\r\n .db $0B, $24, $24, $24, $24, $24\r\n\r\ndown_b_text\r\n .db $0D, $18, $20, $17, $2A, $0B\r\n\r\nrate_meter ; TODO unused\r\n .db $30, $31, $32, $33, $34, $35, $36, $37\r\n\r\np1_final_rate\r\n .db $58, $00, $00, $A8 ;tens game timer\r\n .db $58, $00, $00, $B0 ;ones game timer\r\n .db $58, $AF, $00, $B8 ;decimal point\r\n .db $58, $00, $00, $C0 ;tenths game timer\r\n .db $58, $38, $00, $C8 ; slash\r\n .db $58, $39, $00, $D0 ; s (for the '/s')\r\n\r\np1_rate_meter\r\n .db $30, $30, $00, $58\r\n .db $30, $31, $00, $60\r\n .db $30, $32, $00, $68\r\n .db $30, $33, $00, $70\r\n .db $30, $34, $00, $78\r\n .db $30, $35, $00, $80\r\n .db $30, $36, $00, $88\r\n .db $30, $37, $00, $90\r\n\r\np2_final_rate\r\n .db $78, $00, $00, $A8 ;tens game timer\r\n .db $78, $00, $00, $B0 ;ones game timer\r\n .db $78, $AF, $00, $B8 ;decimal point\r\n .db $78, $00, $00, $C0 ;tenths game timer\r\n .db $78, $38, $00, $C8 ; slash\r\n .db $78, $39, $00, $D0 ; s (for the '/s')\r\n\r\np2_rate_meter\r\n .db $90, $30, $00, $58\r\n .db $90, $31, $00, $60\r\n .db $90, $32, $00, $68\r\n .db $90, $33, $00, $70\r\n .db $90, $34, $00, $78\r\n .db $90, $35, $00, $80\r\n .db $90, $36, $00, $88\r\n .db $90, $37, $00, $90\r\n\r\nmenu_background_1:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 6\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$19,$15,$0A,$22,$0E,$1B,$1C,$24,$24,$24,$01 ;;row 7 Players\r\n .db $24,$24,$02,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 8\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\nmenu_background_2:\r\n .db $24,$24,$24,$24,$24,$24,$0B,$1E,$1D,$1D,$18,$17,$24,$24,$24,$24 ;;row 9 Button\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$1C,$0E,$0C,$18,$17,$0D,$1C,$24,$24,$24,$24 ;;row 11 Seconds\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$1C,$1D,$0A,$1B,$1D,$24,$24,$24,$24 ;;row 13 Start\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 15\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 16\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_3:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\nmenu_background_4:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ngame_background:\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 1\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 2\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 3\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 4\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 5\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 6\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 7\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 8\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 9\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 10\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 11\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 12\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 13\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 14\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24,$24 ;;row 15\r\n .db $24,$24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$24,$24,$24,$24 ;;row 16\r\n .db $24,$24,$24,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 17\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 18\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 19\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 20\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 21\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 22\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 23\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 24\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 25\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 27\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 28\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26 ;;row 29\r\n .db $24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24 ;;row 30\r\n .db $26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24,$26,$24\r\n\r\ntitle_background_1:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 1\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 2\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 3\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 4\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C ;;row 5\r\n .db $60,$61,$62,$63,$64,$65,$66,$67,$68,$69,$6A,$6B,$6C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C ;;row 6\r\n .db $70,$71,$72,$73,$74,$75,$76,$77,$78,$79,$7A,$7B,$7C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C ;;row 7\r\n .db $80,$81,$82,$83,$84,$85,$86,$87,$88,$89,$8A,$8B,$8C,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C ;;row 8\r\n .db $90,$91,$92,$93,$94,$95,$96,$97,$98,$99,$9A,$9B,$9C,$0A,$0A,$0A\r\ntitle_background_2:\r\n .db $0A,$0A,$0A,$A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC ;;row 9\r\n .db $A0,$A1,$A2,$A3,$A4,$A5,$A6,$A7,$A8,$A9,$AA,$AB,$AC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC ;;row 10\r\n .db $B0,$B1,$B2,$B3,$B4,$B5,$B6,$B7,$B8,$B9,$BA,$BB,$BC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC ;;row 11\r\n .db $C0,$C1,$C2,$C3,$C4,$C5,$C6,$C7,$C8,$C9,$CA,$CB,$CC,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 12\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 13\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$00,$01,$02,$03,$04 ;;row 14 Controller\r\n .db $05,$06,$07,$08,$09,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$10,$11,$12,$13,$14 ;;row 15 Controller\r\n .db $15,$16,$17,$18,$19,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$20,$21,$22,$23,$24 ;;row 16 Controller\r\n .db $25,$26,$27,$28,$29,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_3:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$30,$31,$32,$33,$34 ;;row 17 Controller\r\n .db $35,$36,$37,$38,$39,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$40,$41,$42,$43,$44 ;;row 18 Controller\r\n .db $45,$46,$47,$48,$49,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$50,$51,$52,$53,$54 ;;row 19 Controller\r\n .db $55,$56,$57,$58,$59,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 20\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 21\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E9,$EB,$DE,$EC,$EC,$0A ;;row 22 press start\r\n .db $0A,$EC,$ED,$DA,$EB,$ED,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 23\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 24\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\ntitle_background_4:\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$ED,$E6 ;;row 24 Not TM nor C\r\n .db $0A,$E7,$E8,$EB,$0A,$FF,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$DA,$0A,$E6,$E2,$ED,$DC,$E1 ;;row 26 A Mitch3a Game\r\n .db $D3,$DA,$0A,$E0,$DA,$E6,$DE,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$E0,$E2,$ED,$E1,$EE,$DB,$F9,$DC,$E8,$E6,$F8,$E6,$E2,$ED,$DC ;;row 27 github link\r\n .db $E1,$D3,$DB,$F8,$E6,$DA,$EC,$E1,$F2,$E6,$DA,$EC,$E1,$F2,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$E7,$E8,$ED,$0A,$E5,$E2,$DC,$DE,$E7,$EC,$DE,$DD ;;row 28 not licensed by nintendo\r\n .db $0A,$DB,$F2,$0A,$E7,$E2,$E7,$ED,$DE,$E7,$DD,$E8,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 29\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A ;;row 30\r\n .db $0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A,$0A\r\n\r\ngame_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;4x4 rows (12-15)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\ntitle_attribute:\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;1x4 rows (0-3)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;2x4 rows (4-7)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;3x4 rows (8-11)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;4x4 rows (12-15)\r\n .db %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101, %01010101 ;5x4 rows (16-19)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;6x4 rows (20-23)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;7x4 rows (24-27)\r\n .db %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 ;8x4 rows (28-30)\r\n\r\n .org $FFFA ;first of the three vectors starts here\r\n .dw NMI ;when an NMI happens (once per frame if enabled) the\r\n ;processor will jump to the label NMI:\r\n .dw RESET ;when the processor first turns on or is reset, it will jump\r\n ;to the label RESET:\r\n .dw 0 ;external interrupt IRQ is not used\r\n\r\n;;;;;;;;;;;;;;\r\n\r\n .bank 2\r\n .org $0000\r\n .incbin \"mario.chr\" ;includes 8KB graphics file from SMB1\r\n"}}},{"rowIdx":499,"cells":{"commit":{"kind":"string","value":"b40d93a8b88491b394a9aab5321fd722f9aa4fc9"},"subject":{"kind":"string","value":"Comment tweaks"},"message":{"kind":"string","value":"Comment tweaks\n"},"repos":{"kind":"string","value":"kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom"},"file_path":{"kind":"string","value":"puzz15.asm"},"license":{"kind":"string","value":"bsd-2-clause"},"unix_time":{"kind":"number","value":1582719506,"string":"1,582,719,506"},"new_contents":{"kind":"string","value":"; \"15 puzzle\" for the Apple I\n\n; Jeff Jetton\n; Februrary 2020\n\n; Written for the dasm assembler, but should assemble under others\n; with a few tweaks here and there.\n\n\n\n processor 6502\n \n ; Contants\nKBD equ $D010 ; Location of input character from keyboard\nKBDCR equ $D011 ; Keyboard control: Indicator that a new input\n ; character is ready\nPRBYTE equ $FFDC ; WozMon routine to diaplay register A in hex\nECHO equ $FFEF ; WozMon routine to display register A char\nGETLINE equ $FF1F ; Entry point back to WozMonitor\n\n\n ; Zero-page variables\n seg.u VARS\n\n org $0000\n\nPUZZ ds 16 ; The puzzle board state\nCURMOV ds 1 ; ASCII code of the letter chosen as the current move\nCUROFF ds 1 ; Offset in the board of the location of that move's letter\nEMPOFF ds 1 ; Current offset of the empty space\nTEMPCMP ds 1 ; Stores some temp bits used for row/col comparisons in HNDLMOV\nADJFAC ds 1 ; Adjustment factor to use when shifting tiles in HNDLMOV\nDIFFLVL ds 1 ; Difficulty level (raw ascii of number chosen)\nMOVELO ds 1 ; Tracks total number of moves\nMOVEHI ds 1 ; ...using two bytes of binary-coded decimal (0000-9999)\nTXTLO ds 1 ; Where the printxt routine looks for the string address\nTXTHI ds 1 ; (two bytes)\nPRNG ds 1 ; Running pseudo-random number generator\nSHUFCTR ds 1 ; Counter of valid moves when \"shuffling\" new puzzle in INITPUZ\nPREVMOV ds 1 ; Keeps track of previous randomly-selected move in INITPUZ\n \n \n; Main program --------------------------------------------------------------\n\n seg CODE\n org $0300\n \n ; Init the program\n cld ; Start with BCD mode off\n ldx #$FF\n txs ; Reset stack to $FF\n lda #42 ; Set PNRG seed\n sta PRNG\n jsr INITPUZ ; Set up an ordered puzzle board\n \n ; Show welcome message and ask if user wants instructions\n lda #<TXT_WELCOME ; Store low byte of text data location\n sta TXTLO\n lda #>TXT_WELCOME ; Store high byte of text data location\n sta TXTHI\n jsr PRINTXT ; Call generic print function\n \n ; Get and handle answer to instructions question\n jsr GETYN\n bne NEWGAME ; Skip to game if they didn't type \"Y\"\n lda #<TXT_INSTRUCT ; Otherwise, print instructions...\n sta TXTLO\n lda #>TXT_INSTRUCT\n sta TXTHI\n jsr PRINTXT\n jsr PRINPUZ ; Show the (currently solved) puzzle as an example\n\nNEWGAME jsr GETDIFF ; Ask for difficulty level\n jsr SHUFPUZ ; Shuffle up a new puzzle and reset move counter\n jsr PRINPUZ ; Print initial board state\n\nNXTMOVE jsr INCMOVE ; Handle next move by first incrementing move counter\n jsr PRINMOV ; Show that move number\nGETMOVE jsr GETKEY ; Grab keyboard input\n jsr ECHO\n cmp #\"Q\" ; Is user trying to quit?\n bne NOQUIT\n jmp ENDGAME\n \nNOQUIT jsr HNDLMOV ; Get move and, if valid, update puzzle board\n lda CUROFF ; Is the current offset 16 (i.e. move was invalid?)\n cmp #16\n bne SKIPERR ; Skip error display if the move was valid\n jsr PRINERR\n jmp GETMOVE ; Get new move, but don't incr. counter or show move #\n \nSKIPERR jsr PRINPUZ ; Display current board state\n jsr NEWLINE\n jsr CHKWIN ; Check for a winning board (sets Z if so)\n beq WINNER\n jmp NXTMOVE\n \nWINNER jsr PRINYAY ; Display a random interjection\n lda #<TXT_WINNER1 ; Display next part of winning message\n sta TXTLO\n lda #>TXT_WINNER1\n sta TXTHI\n jsr PRINTXT\n lda DIFFLVL ; Show difficulty level\n jsr ECHO\n lda #<TXT_WINNER2 ; Display rest of winning message\n sta TXTLO\n lda #>TXT_WINNER2\n sta TXTHI\n jsr PRINTXT\n jsr PRINMOV ; Display total moves\n \n lda #<TXT_REPLAY ; Prompt for playing another round\n sta TXTLO\n lda #>TXT_REPLAY\n sta TXTHI\n jsr PRINTXT\n jsr GETYN ; Get valid Y or N input\n bne ENDGAME\n jmp NEWGAME\n \nENDGAME lda #<TXT_BYE\n sta TXTLO\n lda #>TXT_BYE\n sta TXTHI\n jsr PRINTXT\n jmp GETLINE ; Return to WozMonitor\n\n\n\n \n; Subroutines ***************************************************************\n\n\nNEWLINE SUBROUTINE ; Just print out a newline (destroys A)\n lda #$0D\n jsr ECHO\n rts\n\n\n\nPRINTXT SUBROUTINE ; Put string pointer in TXTLO & TXTHI before calling\n ldy #0 ; Y is the offset within the string\n.loop lda (TXTLO),Y ; Load A with whatever's at pointer + Y\n beq .end ; If char data is zero, that's the end\n jsr ECHO ; Otherwise, print it\n iny\n jmp .loop\n.end rts ; Note that we've destoyed A & Y\n\n\n\nGETKEY SUBROUTINE ; Get one character of input and munge it into valid ASCII\n ; Also cycles the PRNG while waiting for key input!\n jsr NEXTRND ; Cycle PRNG\n lda KBDCR ; Check PIA for keyboard input\n bpl GETKEY ; Loop if A is \"positive\" (bit 7 low)\n lda KBD ; Get the keyboard character\n and #%01111111 ; Clear bit 7, which is always set for some reason\n rts\n\n\n\nGETYN SUBROUTINE ; Gets a valid Y or N response from user. Sets Z flag on Y.\n jsr GETKEY\n jsr ECHO\n cmp #\"N\"\n beq .nope\n cmp #\"Y\"\n beq .yup\n jsr PRINERR\n jmp GETYN ; Try again\n.nope tsx ; This clears the zero flag\n.yup rts\n\n\n\nNEXTRND SUBROUTINE ; Cycle the PRNG (simple 8-bit Xorshift)\n lda PRNG\n asl\n bcc .noeor\n eor #$A9\n.noeor sta PRNG\n rts\n\n\n\nPRINPUZ SUBROUTINE ; Display the current puzzle state\n jsr NEWLINE\n jsr NEWLINE\n ldx #0 ; Offset into PUZZ data\n ldy #4 ; Counts columns, for linebreaks\n.loop lda PUZZ,X\n jsr ECHO ; Print current slot\n dey\n bne .skipln ; Skip to inx if not at end of line\n ldy #4 ; Otherwise reset y and do a newline\n jsr NEWLINE\n.skipln inx\n cpx #16\n bne .loop\n jsr NEWLINE\n rts\n\n\n\nINCMOVE SUBROUTINE ; Does some BCD fussing around to increment the counter\n sed\n lda MOVELO\n clc\n adc #1\n sta MOVELO\n lda MOVEHI\n adc #0 ; Add anything in the carry bit to the high byte\n sta MOVEHI\n cld\n rts\n \n \n \nPRINMOV SUBROUTINE ; Displays move number. Destroys A.\n lda MOVEHI\n beq .low ; Skip to the low byte if high byte is still zero\n jsr PRBYTE\n.low lda MOVELO\n jsr PRBYTE\n rts\n\n\n\nPRINERR SUBROUTINE ; Displays a standard input error message\n lda #<TXT_BADMOVE\n sta TXTLO\n lda #>TXT_BADMOVE\n sta TXTHI\n jsr PRINTXT\n rts\n\n\n\nPRINYAY SUBROUTINE ; Prints a randomly-selected expression of joy\n jsr NEXTRND\n lda PRNG ; Put latest random number in A\n and #%00111000 ; Get bits 3-5 as a \"multiple of 8\" offset\n tax\n.loop lda YAYLKP,X\n beq .done\n jsr ECHO\n inx\n jmp .loop\n.done rts\n\n\n\nINITPUZ SUBROUTINE ; Create a new, ordered puzzle\n ; Put the space in the last byte of the puzz data\n lda #\" \"\n sta PUZZ + 15\n lda #15\n sta EMPOFF\n ; Work backwards through alphabet for the rest of the puzzle\n ldx #15\n ldy #\"O\"\n.loop tya\n sta.wx PUZZ-1 ; STA PUZZ-1,X\n dey\n dex\n bne .loop\n rts\n\n\n\nSHUFPUZ SUBROUTINE ; Randomly shuffle puzzle board and init game variables\n ; Reset move counter and seed the previous valid move variable\n lda #0\n sta MOVELO\n sta MOVEHI\n sta PREVMOV\n ; Get number of \"shuffle\" moves based on DIFFLVL and DIFFLKP table\n ldx DIFFLVL\n lda.wx DIFFLKP-\"1\" ; DIFFLKP-\"1\", X\n sta SHUFCTR\n ; Push tiles around at random for SHUFCTR number of valid moves\n.loop2 jsr NEXTRND\n lda PRNG\n and #%00001111 ; Get lower 4 bits of current random value\n clc\n adc #\"A\" ; Convert random 0-15 value to ascii A-P\n cmp PREVMOV ; We don't want the same letter as last valid move\n beq .loop2\n jsr HNDLMOV ; Try making that move\n lda CUROFF ; ...was it valid?\n cmp #16\n beq .loop2 ; No? Then it doesn't count. Try again.\n lda CURMOV ; Otherwise, it \"counts\", so we'll remember the move\n sta PREVMOV\n dec SHUFCTR ; ...and decrement the counter\n bne .loop2\n ; As long as the number of \"shuffles\" is odd, it's unlikely that we've\n ; randomly wound up back at a solved board. But since it COULD happen\n ; (moreso at low diff levels), we'd better check and redo if so...\n jsr CHKWIN ; CHKWIN puts 0 in A right before returning if a winner\n beq SHUFPUZ\n rts\n\n \n \nHNDLMOV SUBROUTINE ; Handle the current move in register A\n\n ; There are three steps to be done:\n ; 1. Figure out the offset of the chosen letter (if a valid letter)\n ; 2. Determine the adjustment factor based on the relationship between\n ; the chosen tile and the empty space, or mark move as invalid\n ; 3. Use the adjustment factor to shift the tile(s) appropriately\n \n ; Step 1: Did the user pick a letter that's on the board? If so, where?\n sta CURMOV ; Store input letter as current move\n ldx #0\n.loop lda PUZZ,X ; Look at one of the tiles on the board\n cmp CURMOV ; Is it the current move?\n beq .found\n inx ; Nope. Bump up the offset...\n cpx #16 ; Are we at the end of the board?\n bne .loop ; No? Keep checking\n stx CUROFF ; Otherwise, we're done. User chose a weird letter.\n rts ; Return with offset set to 16 (indicating bad move)\n\n ; Step 2: Is the tile moveable toward the space? If so, how?\n.found stx CUROFF\n ; A moveable tile must be on the same row or column as the empty space\n ; First check if CUROFF is on the same ROW as EMPOFF (bits 2 & 3 match)\n txa\n and #%00001100 ; Isolate bits 2 & 3 of the offset of the current move\n sta TEMPCMP ; Remember the result\n lda EMPOFF\n and #%00001100 ; Isolate bits 2 & 3 of the offset of the empty spot\n cmp TEMPCMP ; Do the bits match?\n bne .chkcol ; No? Bummer. Branch ahead and check for same column.\n txa ; Yes? Subtract EMPOFF from CUROFF (which is still in X)\n sec\n sbc EMPOFF\n bpl .posadj\n lda #-1 ; CUROFF < EMPOFF = adjustment factor of -1\n jmp .shift\n.posadj lda #1 ; CUROFF > EMPOFF = adjustment factor of +1\n jmp .shift\n \n.chkcol ; Check if CUROFF is on the same COLUMN as EMPOFF (bits 0 & 1 match)\n txa ; Get current move offset from X again\n and #%00000011 ; Isolate bits 0 & 1\n sta TEMPCMP\n lda EMPOFF\n and #%00000011 ; Same for offset of empty space\n cmp TEMPCMP ; If they match, they're in the same column\n beq .setadj\n ldx #16 ; Load X with 16, indicating an invalid move\n stx CUROFF\n rts ; Back to the game at hand\n \n.setadj txa\n sec\n sbc EMPOFF\n bpl .posad2\n lda #-4 ; CUROFF < EMPOFF = adjustment factor of -4 (1 row \"up\")\n jmp .shift\n.posad2 lda #4 ; CUROFF > EMPOFF = adjustment factor of 4 (1 row down)\n\n ; Step 3: Shift the tiles appropriately.\n ; This section takes care of swaping the space with an adjacent tile,\n ; over and over until the space is in the original move offset.\n ; The amount/direction by which the space is shifted each time is the\n ; \"adjustment factor\" which lives register in A by this point.\n.shift sta ADJFAC ; A contains the current adjustment factor. Remember it.\n.again lda EMPOFF ; Put current EMPOFF into X\n tax\n clc\n adc ADJFAC ; Temp offset is current empoff plus adjustment factor\n tay ; Maintain that temp offset in Y\n lda PUZZ,Y ; Put whatever's in temp offset into A\n sta PUZZ,X ; And store it where the empty space was\n lda #\" \" ; The empty space...\n sta PUZZ,Y ; Goes where the temp offset is\n sty EMPOFF ; And that temp offset is the new empty space offset\n cpy CUROFF ; Is the temp offset where the original move offset is?\n bne .again\n rts\n\n\n\nCHKWIN SUBROUTINE ; Compare current board to sorted board\n ldx #15\n lda #\"O\"\n sta TEMPCMP\n.loop lda.wx PUZZ-1 ; lda PUZZ-1,X\n cmp TEMPCMP\n bne .nowin\n dec TEMPCMP\n dex\n bne .loop\n ; If we made it this far, we have a winning board and the Zero flag\n ; will be set (due to the previous dex), indicating the win\n.nowin rts ; But if we jumped here, Z will be unset (due to failed cmp)\n ; indicating a non-winning board state\n\n \n \n\nGETDIFF SUBROUTINE ; Prompt for and get/set difficulty level\n ; Check for valid input and puts result in DIFFLVL\n lda #<TXT_DIFFASK\n sta TXTLO\n lda #>TXT_DIFFASK\n sta TXTHI\n jsr PRINTXT\n.input jsr GETKEY\n jsr ECHO\n sta DIFFLVL ; Store input as ASCII code, not as actual number\n cmp #\"1\" ; Compare input (in register A) to ascii 1\n bpl .nxtchk ; If result is positive, input was >= 1. So far so good.\n jmp .inval\n.nxtchk lda #\"5\" ; Subtract input from ascii 5\n sec\n sbc DIFFLVL\n bmi .inval ; If result is negative, input was > 5 and invalid\n rts ; At this point, we're good, so return\n.inval jsr PRINERR\n jmp .input\n \n\n\n; Stored data ****************************************************************\n\nDIFFLKP ; Lookup table translating difficulty levels to number of \"shuffles\"\n ; Low values should be odd (reduced chance of shuffling a solved board)\n .byte 3 ; Level 1, only three moves\n .byte 9 ; 2\n .byte 19 ; 3\n .byte 35 ; 4\n .byte 255 ; Level 5, the full monty\n \nYAYLKP ; Lookup table of strings for a random winner message\n ; First seven strings are padded to ensure 8 byte offsets\n dc \"HOORAY!\"\n .byte 0\n dc \"HUZZAH!\"\n .byte 0\n dc \"WOOHOO!\"\n .byte 0\n dc \"YIPPIE!\"\n .byte 0\n dc \"SWEET!\"\n .byte 0\n .byte 0\n dc \"COOL!\"\n .byte 0\n .byte 0\n .byte 0\n dc \"NICE!\"\n .byte 0\n .byte 0\n .byte 0\n dc \"GADZOOKS!\"\n .byte 0\n\nTXT_WELCOME\n .byte $0D\n .byte $0D\n dc \"15 PUZZLE - BY JEFF JETTON\"\n .byte $0D\n .byte $0D\n dc \"INSTRUCTIONS (Y/N)? \"\n .byte $00\n\nTXT_INSTRUCT\n .byte $0D\n .byte $0D\n dc \"TYPE A LETTER THAT'S ON THE SAME ROW OR\"\n .byte $0D\n dc \"COLUMN AS THE EMPTY SPACE TO SLIDE THAT\"\n .byte $0D\n dc \"LETTER (AND ANY IN BETWEEN) TOWARD THE\"\n .byte $0D\n dc \"SPACE. TYPE Q to QUIT.\"\n .byte $0D\n .byte $0D\n dc \"SOLVED PUZZLE LOOKS LIKE THIS:\"\n .byte $0D\n .byte $00\n \nTXT_DIFFASK\n .byte $0D\n .byte $0D\n dc \"DIFFICULTY LEVEL (1-5)? \"\n .byte $00\n\nTXT_BADMOVE\n .byte $0D\n dc \"INVALID CHOICE. TRY AGAIN: \"\n .byte $00\n \nTXT_WINNER1\n dc \" YOU SOLVED A LEVEL \"\n .byte $00\n \nTXT_WINNER2\n dc \" PUZZLE!\"\n .byte $0D\n .byte $0D\n dc \"TOTAL MOVES: \"\n .byte $00\n \nTXT_REPLAY\n .byte $0D\n .byte $0D\n dc \"PLAY AGAIN (Y/N)? \"\n .byte $00\n\nTXT_BYE\n .byte $0D\n .byte $0D\n dc \"BYE!\"\n .byte $0D\n .byte $0D\n byte $00"},"old_contents":{"kind":"string","value":"; \"15 puzzle\" for the Apple I\n\n; Jeff Jetton\n; Februrary 2020\n\n; Written for the dasm assembler, but should assemble under others\n; with a few tweaks here and there.\n\n\n\n; TODO: UPdate maketape to create monitor text file\n; https://www.applefritter.com/node/24600#comment-60100\n; TODO: Rewrite initpuzz and checkwin to refer to an A-O string? Does that save any bytes?\n\n processor 6502\n \n ; Contants\nKBD equ $D010 ; Location of input character from keyboard\nKBDCR equ $D011 ; Keyboard control: Indicator that a new input\n ; character is ready\nPRBYTE equ $FFDC ; WozMon routine to diaplay register A in hex\nECHO equ $FFEF ; WozMon routine to display register A char\nGETLINE equ $FF1F ; Entry point back to WozMonitor\n\n\n ; Zero-page variables\n seg.u VARS\n\n org $0000\n\nPUZZ ds 16 ; The puzzle board state\nCURMOV ds 1 ; ASCII code of the letter chosen as the current move\nCUROFF ds 1 ; Offset in the board of the location of that move's letter\nEMPOFF ds 1 ; Current offset of the empty space\nTEMPCMP ds 1 ; Stores some temp bits used for row/col comparisons in HNDLMOV\nADJFAC ds 1 ; Adjustment factor to use when shifting tiles in HNDLMOV\nDIFFLVL ds 1 ; Difficulty level (raw ascii of number chosen)\nMOVELO ds 1 ; Tracks total number of moves\nMOVEHI ds 1 ; ...using two bytes of binary-coded decimal (0000-9999)\nTXTLO ds 1 ; Where the printxt routine looks for the string address\nTXTHI ds 1 ; (two bytes)\nPRNG ds 1 ; Running pseudo-random number generator\nSHUFCTR ds 1 ; Counter of valid moves when \"shuffling\" new puzzle in INITPUZ\nPREVMOV ds 1 ; Keeps track of previous randomly-selected move in INITPUZ\n \n \n; Main program --------------------------------------------------------------\n\n seg CODE\n org $0300\n \n ; Init the program\n cld ; Start with BCD mode off\n ldx #$FF\n txs ; Reset stack to $FF\n lda #42 ; Set PNRG seed\n sta PRNG\n jsr INITPUZ ; Set up an ordered puzzle board\n \n ; Show welcome message and ask if user wants instructions\n lda #<TXT_WELCOME ; Store low byte of text data location\n sta TXTLO\n lda #>TXT_WELCOME ; Store high byte of text data location\n sta TXTHI\n jsr PRINTXT ; Call generic print function\n \n ; Get and handle answer to instructions question\n jsr GETYN\n bne NEWGAME ; Skip to game if they didn't type \"Y\"\n lda #<TXT_INSTRUCT ; Otherwise, print instructions...\n sta TXTLO\n lda #>TXT_INSTRUCT\n sta TXTHI\n jsr PRINTXT\n jsr PRINPUZ ; Show the (currently solved) puzzle as an example\n\nNEWGAME jsr GETDIFF ; Ask for difficulty level\n jsr SHUFPUZ ; Shuffle up a new puzzle and reset move counter\n jsr PRINPUZ ; Print initial board state\n\nNXTMOVE jsr INCMOVE ; Handle next move by first incrementing move counter\n jsr PRINMOV ; Show that move number\nGETMOVE jsr GETKEY ; Grab keyboard input\n jsr ECHO\n cmp #\"Q\" ; Is user trying to quit?\n bne NOQUIT\n jmp ENDGAME\n \nNOQUIT jsr HNDLMOV ; Get move and, if valid, update puzzle board\n lda CUROFF ; Is the current offset 16 (i.e. move was invalid?)\n cmp #16\n bne SKIPERR ; Skip error display if the move was valid\n jsr PRINERR\n jmp GETMOVE ; Get new move, but don't incr. counter or show move #\n \nSKIPERR jsr PRINPUZ ; Display current board state\n jsr NEWLINE\n jsr CHKWIN ; Check for a winning board (sets Z if so)\n beq WINNER\n jmp NXTMOVE\n \nWINNER jsr PRINYAY ; Display a random interjection\n lda #<TXT_WINNER1 ; Display next part of winning message\n sta TXTLO\n lda #>TXT_WINNER1\n sta TXTHI\n jsr PRINTXT\n lda DIFFLVL ; Show difficulty level\n jsr ECHO\n lda #<TXT_WINNER2 ; Display rest of winning message\n sta TXTLO\n lda #>TXT_WINNER2\n sta TXTHI\n jsr PRINTXT\n jsr PRINMOV ; Display total moves\n \n lda #<TXT_REPLAY ; Prompt for playing another round\n sta TXTLO\n lda #>TXT_REPLAY\n sta TXTHI\n jsr PRINTXT\n jsr GETYN ; Get valid Y or N input\n bne ENDGAME\n jmp NEWGAME\n \nENDGAME lda #<TXT_BYE\n sta TXTLO\n lda #>TXT_BYE\n sta TXTHI\n jsr PRINTXT\n jmp GETLINE ; Return to WozMonitor\n\n\n\n \n; Subroutines ***************************************************************\n\n\nNEWLINE SUBROUTINE ; Just print out a newline (destroys A)\n lda #$0D\n jsr ECHO\n rts\n\n\n\nPRINTXT SUBROUTINE ; Put string pointer in TXTLO & TXTHI before calling\n ldy #0 ; Y is the offset within the string\n.loop lda (TXTLO),Y ; Load A with whatever's at pointer + Y\n beq .end ; If char data is zero, that's the end\n jsr ECHO ; Otherwise, print it\n iny\n jmp .loop\n.end rts ; Note that we've destoyed A & Y\n\n\n\nGETKEY SUBROUTINE ; Get one character of input and munge it into valid ASCII\n ; Also cycles the PRNG while waiting for key input!\n jsr NEXTRND ; Cycle PRNG\n lda KBDCR ; Check PIA for keyboard input\n bpl GETKEY ; Loop if A is \"positive\" (bit 7 low)\n lda KBD ; Get the keyboard character\n and #%01111111 ; Clear bit 7, which is always set for some reason\n rts\n\n\n\nGETYN SUBROUTINE ; Gets a valid Y or N response from user. Sets Z flag on Y.\n jsr GETKEY\n jsr ECHO\n cmp #\"N\"\n beq .nope\n cmp #\"Y\"\n beq .yup\n jsr PRINERR\n jmp GETYN ; Try again\n.nope tsx ; This clears the zero flag\n.yup rts\n\n\n\nNEXTRND SUBROUTINE ; Cycle the PRNG (simple 8-bit Xorshift)\n lda PRNG\n asl\n bcc .noeor\n eor #$A9\n.noeor sta PRNG\n rts\n\n\n\nPRINPUZ SUBROUTINE ; Display the current puzzle state\n jsr NEWLINE\n jsr NEWLINE\n ldx #0 ; Offset into PUZZ data\n ldy #4 ; Counts columns, for linebreaks\n.loop lda PUZZ,X\n jsr ECHO ; Print current slot\n dey\n bne .skipln ; Skip to inx if not at end of line\n ldy #4 ; Otherwise reset y and do a newline\n jsr NEWLINE\n.skipln inx\n cpx #16\n bne .loop\n jsr NEWLINE\n rts\n\n\n\nINCMOVE SUBROUTINE ; Does some BCD fussing around to increment the counter\n sed\n lda MOVELO\n clc\n adc #1\n sta MOVELO\n lda MOVEHI\n adc #0 ; Add anything in the carry bit to the high byte\n sta MOVEHI\n cld\n rts\n \n \n \nPRINMOV SUBROUTINE ; Displays move number. Destroys A.\n lda MOVEHI\n beq .low ; Skip to the low byte if high byte is still zero\n jsr PRBYTE\n.low lda MOVELO\n jsr PRBYTE\n rts\n\n\n\nPRINERR SUBROUTINE ; Displays a standard input error message\n lda #<TXT_BADMOVE\n sta TXTLO\n lda #>TXT_BADMOVE\n sta TXTHI\n jsr PRINTXT\n rts\n\n\n\nPRINYAY SUBROUTINE ; Prints a randomly-selected expression of joy\n jsr NEXTRND\n lda PRNG ; Put latest random number in A\n and #%00111000 ; Get bits 3-5 as a \"multiple of 8\" offset\n tax\n.loop lda YAYLKP,X\n beq .done\n jsr ECHO\n inx\n jmp .loop\n.done rts\n\n\n\nINITPUZ SUBROUTINE ; Create a new, ordered puzzle\n ; Put the space in the last byte of the puzz data\n lda #\" \"\n sta PUZZ + 15\n lda #15\n sta EMPOFF\n ; Work backwards through alphabet for the rest of the puzzle\n ldx #15\n ldy #\"O\"\n.loop tya\n sta.wx PUZZ-1 ; STA PUZZ-1,X\n dey\n dex\n bne .loop\n rts\n\n\n\nSHUFPUZ SUBROUTINE ; Randomly shuffle puzzle board and init game variables\n ; Reset move counter and seed the previous valid move variable\n lda #0\n sta MOVELO\n sta MOVEHI\n sta PREVMOV\n ; Get number of \"shuffle\" moves based on DIFFLVL and DIFFLKP table\n ldx DIFFLVL\n lda.wx DIFFLKP-\"1\" ; DIFFLKP-\"1\", X\n sta SHUFCTR\n ; Push tiles around at random for SHUFCTR number of valid moves\n.loop2 jsr NEXTRND\n lda PRNG\n and #%00001111 ; Get lower 4 bits of current random value\n clc\n adc #\"A\" ; Convert random 0-15 value to ascii A-P\n cmp PREVMOV ; We don't want the same letter as last valid move\n beq .loop2\n jsr HNDLMOV ; Try making that move\n lda CUROFF ; ...was it valid?\n cmp #16\n beq .loop2 ; No? Then it doesn't count. Try again.\n lda CURMOV ; Otherwise, it \"counts\", so we'll remember the move\n sta PREVMOV\n dec SHUFCTR ; ...and decrement the counter\n bne .loop2\n ; As long as the number of \"shuffles\" is odd, it's unlikely that we've\n ; randomly wound up back at a solved board. But since it COULD happen\n ; (moreso at low diff levels), we'd better check and redo if so...\n jsr CHKWIN ; CHKWIN puts 0 in A right before returning if a winner\n beq SHUFPUZ\n rts\n\n \n \nHNDLMOV SUBROUTINE ; Handle the current move in register A\n\n ; There are three steps to be done:\n ; 1. Figure out the offset of the chosen letter (if a valid letter)\n ; 2. Determine the adjustment factor based on the relationship between\n ; the chosen tile and the empty space, or mark move as invalid\n ; 3. Use the adjustment factor to shift the tile(s) appropriately\n \n ; Step 1: Did the user pick a letter that's on the board? If so, where?\n sta CURMOV ; Store input letter as current move\n ldx #0\n.loop lda PUZZ,X ; Look at one of the tiles on the board\n cmp CURMOV ; Is it the current move?\n beq .found\n inx ; Nope. Bump up the offset...\n cpx #16 ; Are we at the end of the board?\n bne .loop ; No? Keep checking\n stx CUROFF ; Otherwise, we're done. User chose a weird letter.\n rts ; Return with offset set to 16 (indicating bad move)\n\n ; Step 2: Is the tile moveable toward the space? If so, how?\n.found stx CUROFF\n ; A moveable tile must be on the same row or column as the empty space\n ; First check if CUROFF is on the same ROW as EMPOFF (bits 2 & 3 match)\n txa\n and #%00001100 ; Isolate bits 2 & 3 of the offset of the current move\n sta TEMPCMP ; Remember the result\n lda EMPOFF\n and #%00001100 ; Isolate bits 2 & 3 of the offset of the empty spot\n cmp TEMPCMP ; Do the bits match?\n bne .chkcol ; No? Bummer. Branch ahead and check for same column.\n txa ; Yes? Subtract EMPOFF from CUROFF (which is still in X)\n sec\n sbc EMPOFF\n bpl .posadj\n lda #-1 ; CUROFF < EMPOFF = adjustment factor of -1\n jmp .shift\n.posadj lda #1 ; CUROFF > EMPOFF = adjustment factor of +1\n jmp .shift\n \n.chkcol ; Check if CUROFF is on the same COLUMN as EMPOFF (bits 0 & 1 match)\n txa ; Get current move offset from X again\n and #%00000011 ; Isolate bits 0 & 1\n sta TEMPCMP\n lda EMPOFF\n and #%00000011 ; Same for offset of empty space\n cmp TEMPCMP ; If they match, they're in the same column\n beq .setadj\n ldx #16 ; Load X with 16, indicating an invalid move\n stx CUROFF\n rts ; Back to the game at hand\n \n.setadj txa\n sec\n sbc EMPOFF\n bpl .posad2\n lda #-4 ; CUROFF < EMPOFF = adjustment factor of -4 (1 row \"up\")\n jmp .shift\n.posad2 lda #4 ; CUROFF > EMPOFF = adjustment factor of 4 (1 row down)\n\n ; Step 3: Shift the tiles appropriately.\n ; This section takes care of swaping the space with an adjacent tile,\n ; over and over until the space is in the original move offset.\n ; The amount/direction by which the space is shifted each time is the\n ; \"adjustment factor\" which lives register in A by this point.\n.shift sta ADJFAC ; A contains the current adjustment factor. Remember it.\n.again lda EMPOFF ; Put current EMPOFF into X\n tax\n clc\n adc ADJFAC ; Temp offset is current empoff plus adjustment factor\n tay ; Maintain that temp offset in Y\n lda PUZZ,Y ; Put whatever's in temp offset into A\n sta PUZZ,X ; And store it where the empty space was\n lda #\" \" ; The empty space...\n sta PUZZ,Y ; Goes where the temp offset is\n sty EMPOFF ; And that temp offset is the new empty space offset\n cpy CUROFF ; Is the temp offset where the original move offset is?\n bne .again\n rts\n\n\n\nCHKWIN SUBROUTINE ; Compare current board to sorted board\n ldx #15\n lda #\"O\"\n sta TEMPCMP\n.loop lda.wx PUZZ-1 ; lda PUZZ-1,X\n cmp TEMPCMP\n bne .nowin\n dec TEMPCMP\n dex\n bne .loop\n ; If we made it this far, we have a winning board and the Zero flag\n ; will be set (due to the previous dex), indicating the win\n.nowin rts ; But if we jumped here, Z will be unset (due to failed cmp)\n ; indicating a non-winning board state\n\n \n \n\nGETDIFF SUBROUTINE ; Prompt for and get/set difficulty level\n ; Check for valid input and puts result in DIFFLVL\n lda #<TXT_DIFFASK\n sta TXTLO\n lda #>TXT_DIFFASK\n sta TXTHI\n jsr PRINTXT\n.input jsr GETKEY\n jsr ECHO\n sta DIFFLVL ; Store input as ASCII code, not as actual number\n cmp #\"1\" ; Compare input (in register A) to ascii 1\n bpl .nxtchk ; If result is positive, input was >= 1. So far so good.\n jmp .inval\n.nxtchk lda #\"5\" ; Subtract input from ascii 5\n sec\n sbc DIFFLVL\n bmi .inval ; If result is negative, input was > 5 and invalid\n rts ; At this point, we're good, so return\n.inval jsr PRINERR\n jmp .input\n \n\n\n; Stored data ****************************************************************\n\nDIFFLKP ; Lookup table translating difficulty levels to number of \"shuffles\"\n ; Low values should be odd (reduced chance of shuffling a solved board)\n .byte 3 ; Level 1, only three moves\n .byte 9 ; 2\n .byte 19 ; 3\n .byte 35 ; 4\n .byte 255 ; Level 5, the full monty\n \nYAYLKP ; Lookup table of strings for a random winner message\n ; First seven strings are padded to ensure 8 byte offsets\n dc \"HOORAY!\"\n .byte 0\n dc \"HUZZAH!\"\n .byte 0\n dc \"WOOHOO!\"\n .byte 0\n dc \"YIPPIE!\"\n .byte 0\n dc \"SWEET!\"\n .byte 0\n .byte 0\n dc \"COOL!\"\n .byte 0\n .byte 0\n .byte 0\n dc \"NICE!\"\n .byte 0\n .byte 0\n .byte 0\n dc \"GADZOOKS!\"\n .byte 0\n\nTXT_WELCOME\n .byte $0D\n .byte $0D\n dc \"15 PUZZLE - BY JEFF JETTON\"\n .byte $0D\n .byte $0D\n dc \"INSTRUCTIONS (Y/N)? \"\n .byte $00\n\nTXT_INSTRUCT\n .byte $0D\n .byte $0D\n dc \"TYPE A LETTER THAT'S ON THE SAME ROW OR\"\n .byte $0D\n dc \"COLUMN AS THE EMPTY SPACE TO SLIDE THAT\"\n .byte $0D\n dc \"LETTER (AND ANY IN BETWEEN) TOWARD THE\"\n .byte $0D\n dc \"SPACE. TYPE Q to QUIT.\"\n .byte $0D\n .byte $0D\n dc \"SOLVED PUZZLE LOOKS LIKE THIS:\"\n .byte $0D\n .byte $00\n \nTXT_DIFFASK\n .byte $0D\n .byte $0D\n dc \"DIFFICULTY LEVEL (1-5)? \"\n .byte $00\n\nTXT_BADMOVE\n .byte $0D\n dc \"INVALID CHOICE. TRY AGAIN: \"\n .byte $00\n \nTXT_WINNER1\n dc \" YOU SOLVED A LEVEL \"\n .byte $00\n \nTXT_WINNER2\n dc \" PUZZLE!\"\n .byte $0D\n .byte $0D\n dc \"TOTAL MOVES: \"\n .byte $00\n \nTXT_REPLAY\n .byte $0D\n .byte $0D\n dc \"PLAY AGAIN (Y/N)? \"\n .byte $00\n\nTXT_BYE\n .byte $0D\n .byte $0D\n dc \"BYE!\"\n .byte $0D\n .byte $0D\n byte $00"}}}],"truncated":false,"partial":true},"paginationData":{"pageIndex":4,"numItemsPerPage":100,"numTotalItems":107492,"offset":400,"length":100}},"jwt":"eyJhbGciOiJFZERTQSIsImtpZCI6IjVHZDBvd0g5MTM2eDZjc1FvbE1zcktNWUZoRVFoUm5PVVVybEpjOUhaUEEifQ.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc4NjgyNjQwNywianRpIjoiMTcxZjg0NTAtMDY4Yy00Y2JhLTljNWUtZGYyMzczNWQ0YzQzIiwic3ViIjoiL2RhdGFzZXRzL3Byb2plY3QtdGhlbWlzL2dpdC1jb21taXRzIiwiZXhwIjoxNzg2ODMwMDA3LCJpc3MiOiJodHRwczovL2h1Z2dpbmdmYWNlLmNvIn0.l73C4ybi1L2fCbWJPHp1JUc5W7kbD59Df1UJow3QtlQ7V9FcokbWk9qqABHlSx9vFisTPaYerZotzcVICxB0Dg","displayUrls":true,"splitSizeSummaries":[{"config":"default","split":"train","numRows":107492,"numBytesParquet":1334929200}]},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
commit stringlengths 40 40 | subject stringlengths 0 1.12k | message stringlengths 11 14.5k | repos stringlengths 8 11.5k | file_path stringlengths 6 191 | license stringclasses 12
values | unix_time int64 805M 1.66B | new_contents stringlengths 14 20M | old_contents stringlengths 1 20M |
|---|---|---|---|---|---|---|---|---|
07f659d43455d21737207229ff23f8870c69dd6e | Added back instrument wav upload. | Added back instrument wav upload.
| BlockoS/dmf-player,BlockoS/dmf-player,BlockoS/dmf-player | pce/player.asm | bsd-3-clause | 1,596,577,643 | ; Copyright (c) 2015-2019, Vincent "MooZ" Cruz and other contributors. All rights reserved.
; Copyrights licensed under the New BSD License.
; See the accompanying LICENSE file for terms.
;;------------------------------------------------------------------------------------------
; [todo]
; fx callback : don't set... | ; Copyright (c) 2015-2019, Vincent "MooZ" Cruz and other contributors. All rights reserved.
; Copyrights licensed under the New BSD License.
; See the accompanying LICENSE file for terms.
;;------------------------------------------------------------------------------------------
; [todo]
; fx callback : don't set... |
207f30b096ababa81e0307985b7df8d0340ed199 | Started bringing back instruments. | Started bringing back instruments.
| BlockoS/dmf-player,BlockoS/dmf-player,BlockoS/dmf-player | pce/player.asm | bsd-3-clause | 1,596,401,977 | ; Copyright (c) 2015-2019, Vincent "MooZ" Cruz and other contributors. All rights reserved.
; Copyrights licensed under the New BSD License.
; See the accompanying LICENSE file for terms.
;;------------------------------------------------------------------------------------------
; [todo]
; fx callback : don't set... | ; Copyright (c) 2015-2019, Vincent "MooZ" Cruz and other contributors. All rights reserved.
; Copyrights licensed under the New BSD License.
; See the accompanying LICENSE file for terms.
;;------------------------------------------------------------------------------------------
; [todo]
; fx callback : don't set... |
176f030f444b6e17e31d4957eccae3ca660c9267 | relocate: simplified the relocation example a bit, using latest DISP changes | relocate: simplified the relocation example a bit, using latest DISP changes
| z00m128/sjasmplus,z00m128/sjasmplus,z00m128/sjasmplus,z00m128/sjasmplus | examples/relocation/relocation_main.asm | bsd-3-clause | 1,595,712,959 | OPT --syntax=abfw
DEVICE ZXSPECTRUM48, $5D00
; prepare the code from address 0 to have table of offsets "from current address"
; (but store the resulting code from $8000)
ORG $8000
DISP $0000
RELOCATE_START
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;... | OPT --syntax=abfw
DEVICE ZXSPECTRUM48, $5D00
; prepare the code from address 0 to have table of offsets "from current address"
ORG $0000
RELOCATE_START
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; relocator code, using address in BC as where the code d... |
b1787e5a0fb6d20119ee91bc2f231717acbe09b8 | Clean up push nasm test | Clean up push nasm test
| copy/v86,copy/v86,copy/v86,copy/v86,copy/v86,copy/v86,copy/v86 | tests/nasm/push.asm | bsd-2-clause | 1,595,380,214 | global _start
section .data
align 16
myaddress:
dd 0xdeadbeef
%include "header.inc"
;; push r/m - push edx
db 0xff
db 0xf2
;; push r/m - push bx
db 0x66
db 0xff
db 0xf3
;; push imm
push 0xdeadbeef
push WORD 0xd00d
;; push r/m - me... | global _start
section .data
align 16
myquad:
dq 0x1234567890abcdef
mydword:
dd 0xcafebabe
myaddress:
dd 0xdeadbeef
%include "header.inc"
;; push r/m - push edx
db 0xff
db 0xf2
;; push r/m - push bx
db 0x66
db 0xff
db 0xf3
push 0xdeadbeef
push WORD 0xd00d
push... |
a3420c5f3210ef2b3429b0cd1328efa04b1fa91d | Fix manual pcmpeqb nasm test | Fix manual pcmpeqb nasm test
It mistakenly tested the pand instruction earlier.
| copy/v86,copy/v86,copy/v86,copy/v86,copy/v86,copy/v86,copy/v86 | tests/nasm/pcmpeqb.asm | bsd-2-clause | 1,595,380,213 | global _start
section .data
align 16
quad1:
dq 0x00ad00adad007fff
quad2:
dq 0x7fff00428000ffff
quad3:
dq 0x01008080f0f0ff42
quad4:
dq 0x0000000000000000
mydword:
dd 0xcafebabe
myaddress:
dq 0x00adbeefc0de00ce
%include "header.inc"
movq mm0, [quad1]
movq mm1, [quad2]
movq mm2, [quad3]
movq mm3, [quad4]... | global _start
section .data
align 16
quad1:
dq 0x00ad00adad007fff
quad2:
dq 0x7fff00428000ffff
quad3:
dq 0x01008080f0f0ff42
quad4:
dq 0x0000000000000000
mydword:
dd 0xcafebabe
myaddress:
dq 0x00adbeefc0de00ce
%include "header.inc"
movq mm0, [quad1]
movq mm1, [quad2]
movq mm2, [quad3]
movq mm3, [quad4]... |
6802f6ab5f4cf5b0b1b33a66bafc0d77c26abfa8 | Update maskmovq test to use "test memory" the same way as maskmovdqu | Update maskmovq test to use "test memory" the same way as maskmovdqu
| copy/v86,copy/v86,copy/v86,copy/v86,copy/v86,copy/v86,copy/v86 | tests/nasm/maskmovq.asm | bsd-2-clause | 1,595,380,212 | global _start
section .data
align 16
quad0:
dq 0x1234567890abcdef
quad1:
dq 0xffffffffffffffff
mask0:
dq 0x8080808080808080
mask1:
dq 0x10203080405080ff
%include "header.inc"
movq mm0, [quad0]
movq mm1, [quad1]
movq mm2, [quad0]
movq mm3, [quad1]
movq mm6, [mask0]
movq mm7, [mask1]
;; Look out for size... | global _start
section .data
align 16
quad0:
dq 0x1234567890abcdef
quad1:
dq 0xffffffffffffffff
mask0:
dq 0x8080808080808080
mask1:
dq 0x10203080405080ff
%include "header.inc"
movq mm0, [quad0]
movq mm1, [quad1]
movq mm2, [quad0]
movq mm3, [quad1]
movq mm6, [mask0]
movq mm7, [mask1]
;; Look out for size... |
6cf58c8e7deb54e287afeee6710b2a3774eded9c | x86: Add cdef_filter SSE optimizations | x86: Add cdef_filter SSE optimizations
| videolan/dav1d,videolan/dav1d | src/x86/cdef_sse.asm | bsd-2-clause | 1,595,252,401 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2019, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2019, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... |
2e9363d41449f09dae335312968e85214bd27ba4 | Change to imager_tsr to add real floppy drive as B - not currently working correctly | Change to imager_tsr to add real floppy drive as B - not currently working correctly
| reenigne/reenigne,reenigne/reenigne,reenigne/reenigne,reenigne/reenigne | 8088/xtserver/imager/imager_tsr.asm | unlicense | 1,594,484,896 | org 0x100
%include "../../defaults_common.asm"
jmp loader
; This is basically a copy of the int 0x6X routines in keyboard_kernel.asm, except
; that these ones use int 0x10 to write to the screen.
loadDataRoutine:
push ax
push bx
push cx
push dx
push si
push ds
sendReady:
push di
mov al,'R'... | org 0x100
%include "../../defaults_common.asm"
jmp loader
; This is basically a copy of the int 0x6X routines in keyboard_kernel.asm, except
; that these ones use int 0x10 to write to the screen.
loadDataRoutine:
push ax
push bx
push cx
push dx
push si
push ds
sendReady:
push di
mov al,'R'... |
bb3156533b9baf836b746c638111fca82c65f98a | ppindirect.asm: make it possible to assemble to a binary | ppindirect.asm: make it possible to assemble to a binary
Add a couple of dd/db directives to ppindirect.asm to make it possible
to actually run it through the assembler.
Signed-off-by: H. Peter Anvin (Intel) <8a453bad9912ffe59bc0f0b8abe03df9be19379e@zytor.com>
| techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm | test/ppindirect.asm | bsd-2-clause | 1,594,427,083 | ;Testname=test; Arguments=-E -o ppindirect.out; Files=ppindirect.out
; Fun tests of the preprocessor indirection mode...
bits 64
%assign foo1 11
%assign foo11 1111
%assign foo2 22
%assign foo22 2222
%assign foo3 33
%assign foo33 3333
%assign n 2
dd foo%[foo%[n]]*100
dd foo%[n]*100
%assign foo%[foo%[n]] fo... | ;Testname=test; Arguments=-E -o ppindirect.out; Files=ppindirect.out
; Fun tests of the preprocessor indirection mode...
%assign foo1 11
%assign foo11 1111
%assign foo2 22
%assign foo22 2222
%assign foo3 33
%assign foo33 3333
%assign n 2
foo%[foo%[n]]*100
foo%[n]*100
%assign foo%[foo%[n]] foo%[foo%[n]]*100
;%a... |
30b3411642eb00ac87ef4c9b8d64ef50d7c1335b | Fix macos example | Fix macos example
| mjbrusso/util.asm | examples/readint.asm | mit | 1,594,335,269 | %include '../util.asm'
section .text
global _start
_start:
lea rdi, [prompt]
call printstr
call readint
mov r14, rax
mov rdi, rax
call printint
shl r14, 1 ; r14 *= 2
lea rdi, [str2]
call printstr
mov rdi, r14
call printint
call endl
call exit0
... | %include '../util.asm'
section .text
global _start
_start:
mov rdi, prompt
call printstr
call readint
mov r14, rax
mov rdi, rax
call printint
shl r14, 1 ; r14 *= 2
mov rdi, str2
call printstr
mov rdi, r14
call printint
call endl
call exit0
... |
c6c9c025abdb1d0dd5a37b5f7fca67c839717ca4 | Create macOS port | Create macOS port
| mjbrusso/util.asm | util.asm | mit | 1,594,315,606 | ;*********************************************************************
; util.asm
; Author: mjbrusso
; Contributors: AlessandroFonseca
; Version: 1.1
; Licensed under the MIT license (see "license.txt").
;*********************************************************************
section .text
global exit, exit0,... | ;*********************************************************************
; util.asm
; Author: Marcos José Brusso
; Version: 1.1
; Licensed under the MIT license (see "license.txt").
;*********************************************************************
section .text
global exit, exit0, strlen, itoa, atoi, endl... |
422c8c4f1e2504b11527177a0154758e198a20ea | k_test.asm: comment out %pragma list options | k_test.asm: comment out %pragma list options
Disable the %pragma list options in k_test.asm to avoid nasty
surprises. LISTOPT is -L+ by default and can be overridden on the
command line, so the %pragma is not just unnecessary but problematic.
Signed-off-by: H. Peter Anvin (Intel) <8a453bad9912ffe59bc0f0b8abe03df9be19... | techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm | test/k_test.asm | bsd-2-clause | 1,594,224,188 | bits 64
default rel
%use altreg
section .text
bar equ 0xcc
;; Each instruction group separated by blank should encode identially
;; k_mov kreg size_suffix size_name gpr big_gpr
%macro k_mov 5
kmov%2 %1,[foo]
kmov %1,%3 [foo]
kmov %3 [foo],%1
kmov%2 [foo],%1
kmov %3 [foo],%1
kmov [foo],%3 %1
kmov %3... | bits 64
default rel
%use altreg
section .text
bar equ 0xcc
;; Each instruction group separated by blank should encode identially
;; k_mov kreg size_suffix size_name gpr big_gpr
%macro k_mov 5
kmov%2 %1,[foo]
kmov %1,%3 [foo]
kmov %3 [foo],%1
kmov%2 [foo],%1
kmov %3 [foo],%1
kmov [foo],%3 %1
kmov %3... |
f13ec245791fbfd2d72dd949d39b825b955add0a | Override default contrast for TI83 (#196) | Override default contrast for TI83 (#196)
| KnightOS/kernel,KnightOS/kernel | src/00/display.asm | mit | 1,593,803,297 | #ifndef COLOR
initDisplay:
; Initialize LCD
ld a, 1 + LCD_CMD_AUTOINCDEC_SETX
call lcdDelay
out (PORT_LCD_CMD), a ; X-Increment Mode
ld a, 1 + LCD_CMD_SETOUTPUTMODE
call lcdDelay
out (PORT_LCD_CMD), a ; 8-bit mode
ld a, 1 + LCD_CMD_SETDISPLAY
call lcdDelay
out (PORT_LCD_CMD), a... | #ifndef COLOR
initDisplay:
; Initialize LCD
ld a, 1 + LCD_CMD_AUTOINCDEC_SETX
call lcdDelay
out (PORT_LCD_CMD), a ; X-Increment Mode
ld a, 1 + LCD_CMD_SETOUTPUTMODE
call lcdDelay
out (PORT_LCD_CMD), a ; 8-bit mode
ld a, 1 + LCD_CMD_SETDISPLAY
call lcdDelay
out (PORT_LCD_CMD), a... |
6ac8f20145625074d22adf9c3c14d3f16409bf38 | PCM replay WIP | PCM replay WIP
| BlockoS/dmf-player,BlockoS/dmf-player,BlockoS/dmf-player | pce/player.asm | bsd-3-clause | 1,593,638,833 | ; Copyright (c) 2015-2019, Vincent "MooZ" Cruz and other contributors. All rights reserved.
; Copyrights licensed under the New BSD License.
; See the accompanying LICENSE file for terms.
;;-------_----------------------------------------------------------------------------------
; The song data will be mapped on ban... | ; Copyright (c) 2015-2019, Vincent "MooZ" Cruz and other contributors. All rights reserved.
; Copyrights licensed under the New BSD License.
; See the accompanying LICENSE file for terms.
;;-------_----------------------------------------------------------------------------------
; The song data will be mapped on ban... |
7f1095a0239d6b9d797ce37227aac55d4b47969d | emptyarg.asm: add expansion test for a range with a single parameter | emptyarg.asm: add expansion test for a range with a single parameter
Add a test for %{1:1}, as reported in BR 3392611.
Signed-off-by: H. Peter Anvin (Intel) <8a453bad9912ffe59bc0f0b8abe03df9be19379e@zytor.com>
| techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm | test/emptyarg.asm | bsd-2-clause | 1,593,546,861 | %define EMPTY
%macro bar 1
db "bar", __LINE__, %0, %1
%endmacro
%macro baz 2
db "baz", __LINE__, %0, %1, %2
%endmacro
%macro nothing 0
db "nothing", __LINE__, %0
%endmacro
%macro xyzzy 1-2
db "xyzzy", __LINE__, %0, %1, %2, %3
%endmacro
%macro vararg 0-*
db "vararg", __LINE__, %0
%assign %%i 1
%rep %0
db ... | %define EMPTY
%macro bar 1
db "bar", __LINE__, %0, %1
%endmacro
%macro baz 2
db "baz", __LINE__, %0, %1, %2
%endmacro
%macro nothing 0
db "nothing", __LINE__, %0
%endmacro
%macro xyzzy 1-2
db "xyzzy", __LINE__, %0, %1, %2, %3
%endmacro
%macro vararg 0-*
db "vararg", __LINE__, %0
%assign %%i 1
%rep %0
db ... |
464ca6c2f37b93180cc27ea41889ffaf1eab388e | x86: Fix 32-bit build with PIC enabled | x86: Fix 32-bit build with PIC enabled
| videolan/dav1d,videolan/dav1d | src/x86/mc_sse.asm | bsd-2-clause | 1,593,045,241 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... |
a2e656a7c27f3b68cb397c0a590267920297a4b8 | Fixed boot ROM regression; CGB games were given the wrong palettes | Fixed boot ROM regression; CGB games were given the wrong palettes
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,593,020,092 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... |
ac5f7d0c4c549fc5ae2d24005b54a00b43ef2fc4 | x86inc: Improve warnings for use of unsupported instructions | x86inc: Improve warnings for use of unsupported instructions
| videolan/dav1d,videolan/dav1d | src/ext/x86/x86inc.asm | bsd-2-clause | 1,593,001,168 | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2020 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2020 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... |
c19484d8e5c63ddbe55f99add3e6cb1f58651ec4 | x86inc: Add missing 'blsr' BMI1 instruction | x86inc: Add missing 'blsr' BMI1 instruction
| videolan/dav1d,videolan/dav1d | src/ext/x86/x86inc.asm | bsd-2-clause | 1,593,001,167 | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2020 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2020 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... |
8ec5ff0eff128de60613f128a397292665c0d717 | x86inc: Add template defines for EVEX broadcasts | x86inc: Add template defines for EVEX broadcasts
Broadcasting a memory operand is binary flag, you either broadcast
or you don't, and there's only a single possible element size for
any given instruction.
The instruction syntax however requires the broadcast semanticts
to be explicitly defined, which is an issue when... | videolan/dav1d,videolan/dav1d | src/ext/x86/x86inc.asm | bsd-2-clause | 1,592,940,999 | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2020 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2019 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... |
388ab18c453db88e340572d519bfe9b90380db5f | +Scr_AddArrayStringIndexed | +Scr_AddArrayStringIndexed | D4edalus/CoD4x1.8_Server_Pub,callofduty4x/CoD4x_Server,D4edalus/CoD4x1.8_Server_Pub,callofduty4x/CoD4x_Server,callofduty4x/CoD4x_Server,callofduty4x/CoD4x_Server,D4edalus/CoD4x1.8_Server_Pub,callofduty4x/CoD4x_Server,D4edalus/CoD4x1.8_Server_Pub | src/asmsource/pluginexports.asm | agpl-3.0 | 1,592,748,813 | ;===========================================================================
; Copyright (C) 2010-2013 Ninja and TheKelm
; This file is part of CoD4X18-Server source code.
; CoD4X18-Server source code is free software: you can redistribute it and/or modify
; it under the terms of the GNU Affero General P... | ;===========================================================================
; Copyright (C) 2010-2013 Ninja and TheKelm
; This file is part of CoD4X18-Server source code.
; CoD4X18-Server source code is free software: you can redistribute it and/or modify
; it under the terms of the GNU Affero General P... |
bf7adb75676f834ef279d79e7001ec6375619a38 | x86: Branch before waiting on popcnt in ipred_z AVX2 functions | x86: Branch before waiting on popcnt in ipred_z AVX2 functions
Some specific Haswell CPU:s have a hardware bug where the popcnt
instruction doesn't set zero flag correctly, which causes the wrong
branch to be taken.
popcnt also has a 3-cycle latency on Intel CPU:s, so doing the branch
on the input value instead of th... | videolan/dav1d,videolan/dav1d | src/x86/ipred.asm | bsd-2-clause | 1,592,592,341 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
4f08e3fe968f8a6d290f4e580b36e5ab64a6500c | dpdk backend template | dpdk backend template
| hanw/p4c,hanw/p4c,hanw/p4c,hanw/p4c | backends/dpdk/sai.asm | apache-2.0 | 1,592,333,297 | // define globals
(defm local_metadata (struct local_metadata_t))
(defv wcmp_group_id_valid (bit 1))
(defv wcmp_group_id_value (bit 12))
(defv nexthop_id_valid (bit 1))
(defv nexthop_id_value (bit 10))
(defv router_interface_id_valid (bit 1))
(defv route_interface_id_value (bit 10))
(defv neighbor_id_valid (bit 1))
(de... | (header ethernet_t
(field dst_addr (bit 48))
(field src_addr (bit 48))
(field ether_type (bit 16)))
(header ipv4_t
(field version (bit 4))
(field ihl (bit 4))
(field dscp (bit 6))
(field ecn (bit 2))
(field total_len (bit 16))
(field identification (bit 16))
(field flags (bit 3))
(field frag_offset (bit 13))... |
0be942792de64d8055df93c1e9d377e7478ed21d | More trace experiments | More trace experiments
| reenigne/reenigne,reenigne/reenigne,reenigne/reenigne,reenigne/reenigne | 8088/trace/trace.asm | unlicense | 1,591,869,859 | %include "../defaults_bin.asm"
FASTSAMPLING EQU 0 ; Set to one to sample at 14.318MHz. Default is 4.77MHz.
LENGTH EQU 2048 ; Number of samples to capture.
REFRESH EQU 18;0;19 ; Refresh period in cycles, or 0 to disable
cli
mov ax,cs
mov ss,ax
mov sp,0xfffe
%macro outputByte 0
%rep 8
rcr... | %include "../defaults_bin.asm"
FASTSAMPLING EQU 0 ; Set to one to sample at 14.318MHz. Default is 4.77MHz.
LENGTH EQU 2048 ; Number of samples to capture.
REFRESH EQU 18;0;19 ; Refresh period in cycles, or 0 to disable
cli
mov ax,cs
mov ss,ax
mov sp,0xfffe
%macro outputByte 0
%rep 8
rcr... |
eac0e6ce2ee3650f72360b7e82d1a2c47b6aa3d8 | x86: use btc instead of xor+test in fgy_32x32xn_avx2 | x86: use btc instead of xor+test in fgy_32x32xn_avx2
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
e0757a8f3b5306c06f5e2b6f50dd20ed65bae01c | x86: add AVX2 SIMD for generate_grain_uv_{422,444} | x86: add AVX2 SIMD for generate_grain_uv_{422,444}
gen_grain_uv_ar0_8bpc_420_c: 72275.4
gen_grain_uv_ar0_8bpc_420_avx2: 7253.4
gen_grain_uv_ar0_8bpc_422_c: 111742.9
gen_grain_uv_ar0_8bpc_422_avx2: 13704.1
gen_grain_uv_ar0_8bpc_444_c: 205688.5
gen_grain_uv_ar0_8bpc_444_avx2: 25007.5
gen_grain_uv_ar1_8bpc_420_c: 100682.... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
721d99e693db56bcbe402dadd2b0c1db2860ce41 | x86: add SSSE3 version of mc.resize() | x86: add SSSE3 version of mc.resize()
resize_8bpc_c: 1613670.2
resize_8bpc_ssse3: 110469.5
resize_8bpc_avx2: 93580.6
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc_ssse3.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... |
14dea084ad21b351d339ec20712264b1de314de6 | x86: Eliminate redundant 3-operand register syntax in itx | x86: Eliminate redundant 3-operand register syntax in itx
Purely a cosmetic change.
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/itx.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
a575ccd05a423f51b35e2ca00f527e436f1a9c93 | x86: add SSSE3 SIMD for generate_grain_uv_{422,444} | x86: add SSSE3 SIMD for generate_grain_uv_{422,444}
gen_grain_uv_ar0_8bpc_420_c: 72275.4
gen_grain_uv_ar0_8bpc_420_ssse3: 7274.8
gen_grain_uv_ar0_8bpc_422_c: 111742.9
gen_grain_uv_ar0_8bpc_422_ssse3: 13724.8
gen_grain_uv_ar0_8bpc_444_c: 205688.5
gen_grain_uv_ar0_8bpc_444_ssse3: 26218.3
gen_grain_uv_ar1_8bpc_420_c: 100... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain_ssse3.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
53eaddd5d152c1c9bc15fda323d0fc43a658e947 | x86: add SSSE3 versions for filmgrain.fguv_32x32xn[422/444] | x86: add SSSE3 versions for filmgrain.fguv_32x32xn[422/444]
fguv_32x32xn_8bpc_420_csfl0_c: 14568.2
fguv_32x32xn_8bpc_420_csfl0_ssse3: 1162.3
fguv_32x32xn_8bpc_420_csfl1_c: 10682.0
fguv_32x32xn_8bpc_420_csfl1_ssse3: 910.3
fguv_32x32xn_8bpc_422_csfl0_c: 16370.5
fguv_32x32xn_8bpc_422_csfl0_ssse3: 1202.6
fguv_32x32xn_8bpc... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain_ssse3.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
eb4feb320341a8cdbee38c243a309af693231d46 | x86: add AVX2 version of mc.resize() | x86: add AVX2 version of mc.resize()
resize_8bpc_c: 1637609.7
resize_8bpc_avx2: 95162.6
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
eb464d11ddffc4d62e198c04c1d028c89bcdab2f | x86: add AVX2 SIMD for ipred.cfl_ac[444] | x86: add AVX2 SIMD for ipred.cfl_ac[444]
cfl_ac_444_w4_8bpc_c: 499.1
cfl_ac_444_w4_8bpc_ssse3: 24.3
cfl_ac_444_w4_8bpc_avx2: 28.9
cfl_ac_444_w8_8bpc_c: 1240.2
cfl_ac_444_w8_8bpc_ssse3: 47.4
cfl_ac_444_w8_8bpc_avx2: 34.9
cfl_ac_444_w16_8bpc_c: 1785.7
cfl_ac_444_w16_8bpc_ssse3: 86.7
cfl_ac_444_w16_8bpc_avx2: 54.6
cfl_ac... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/ipred.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
601169b15b988f325a18be7cc536cfdab4dbe76a | x86: tables: Add resize_filter table | x86: tables: Add resize_filter table
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/tables.asm | bsd-2-clause | 1,591,108,584 | ; Copyright (c) 2019, The rav1e contributors. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia... | ; Copyright (c) 2019, The rav1e contributors. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia... |
d205a15d6e32b9cc3e1a41da0d5faf3a3386d1e8 | x86: add AVX2 versions for filmgrain.fguv_32x32xn[422/444] | x86: add AVX2 versions for filmgrain.fguv_32x32xn[422/444]
fguv_32x32xn_8bpc_420_csfl0_c: 14568.2
fguv_32x32xn_8bpc_420_csfl0_avx2: 940.2
fguv_32x32xn_8bpc_420_csfl1_c: 10682.0
fguv_32x32xn_8bpc_420_csfl1_avx2: 783.3
fguv_32x32xn_8bpc_422_csfl0_c: 16370.5
fguv_32x32xn_8bpc_422_csfl0_avx2: 1557.3
fguv_32x32xn_8bpc_422_... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
746bb6c1bdc2beca6618a9cb3be9d8b16fd57cd1 | x86: use btc instead of xor+test or 32byte alignment in fgy_32x32xn_ssse3 | x86: use btc instead of xor+test or 32byte alignment in fgy_32x32xn_ssse3
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain_ssse3.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
cc1af6be577b3e9c54b0bfdb9456135daf80d84e | meson/x86: add option to disable AVX-512 asm | meson/x86: add option to disable AVX-512 asm
Allows building with nasm < 2.14.
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
4ea2c53718f029e534a1000118afcdef8fd7eba0 | x86: don't use vptest in SSSE3 version | x86: don't use vptest in SSSE3 version
This is the VEX (AVX) encoded variant for the SSE4 instruction ptest,
so emulate it using pmovmskb in the SSSE3 version.
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc_ssse3.asm | bsd-2-clause | 1,591,108,584 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... |
3a166419f274aff432b47ccc4749c99abfe451f9 | Fix DoS infinite magic ticket patch corrupting some code, causing crashes on real hardware | Fix DoS infinite magic ticket patch corrupting some code, causing crashes on real hardware
| LagoLunatic/DSVEdit,LagoLunatic/DSVEdit | asm/dos_infinite_magical_tickets.asm | mit | 1,590,980,583 | .nds
.relativeinclude on
.erroronwarning on
@Overlay41Start equ 0x02308920
@FreeSpace equ @Overlay41Start ; Note: This is intentionally put at the same location as "dos_magical_ticket.asm".
.open "ftc/overlay9_0", 0219E3E0h
; This patch should be applied after "dos_magical_ticket.asm".
; When starting a new game, g... | .nds
.relativeinclude on
.erroronwarning on
@Overlay41Start equ 0x02308920
@FreeSpace equ @Overlay41Start + 0x7C
.open "ftc/overlay9_0", 0219E3E0h
; This patch should be applied after "dos_magical_ticket.asm".
; When starting a new game, give the player a Magical Ticket.
; There's not enough space so we overwrite t... |
5e8ea2d9687ab2ed65950e76e343c9919a4bc8ea | Change unit test region to NTSC (US) | Change unit test region to NTSC (US)
| undisbeliever/untech-engine,undisbeliever/untech-engine | unit_tests/src/unit-tests.asm | mit | 1,590,585,025 | // This file is part of the UnTech Game Engine.
// Copyright (c) 2016 - 2019, Marcus Rowe <undisbeliever@gmail.com>.
// Distributed under The MIT License: https://opensource.org/licenses/MIT
define MEMORY_MAP = HIROM
define ROM_SIZE = 1
define ROM_SPEED = slow
define REGION = US
define ROM_NAME = "UNTECH UNIT TESTS"
... | // This file is part of the UnTech Game Engine.
// Copyright (c) 2016 - 2019, Marcus Rowe <undisbeliever@gmail.com>.
// Distributed under The MIT License: https://opensource.org/licenses/MIT
define MEMORY_MAP = HIROM
define ROM_SIZE = 1
define ROM_SPEED = slow
define REGION = Australia
define ROM_NAME = "UNTECH UNIT ... |
157123e118589e48273efe3f90eb93afb49b3eab | Fix clearing OAM and initializeing wave RAM | Fix clearing OAM and initializeing wave RAM
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,589,732,651 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... |
a8725ad780b29bbd25f089fe67aecd5e196ab37d | i#1522 AppInit: Fix crash caused by misaligned stack on Win10 x64 (#4294) | i#1522 AppInit: Fix crash caused by misaligned stack on Win10 x64 (#4294)
Fixes a crash when the preinject library does *not* take over: it was missing a pop on x64.
Issue: #1522 | AmesianX/dynamorio,AmesianX/dynamorio,AmesianX/dynamorio,AmesianX/dynamorio,AmesianX/dynamorio,AmesianX/dynamorio | core/arch/pre_inject_asm.asm | lgpl-2.1 | 1,589,381,183 | /* **********************************************************
* Copyright (c) 2013-2015 Google, Inc. All rights reserved.
* Copyright (c) 2007-2009 VMware, Inc. All rights reserved.
* ********************************************************** */
/*
* Redistribution and use in source and binary forms, with or wit... | /* **********************************************************
* Copyright (c) 2013-2015 Google, Inc. All rights reserved.
* Copyright (c) 2007-2009 VMware, Inc. All rights reserved.
* ********************************************************** */
/*
* Redistribution and use in source and binary forms, with or wit... |
4d97f5a9d959679d472e7aa9f68503a69eb47202 | x86: Use 'test' instead of 'or' to compare with zero | x86: Use 'test' instead of 'or' to compare with zero
Allows for macro-op fusion.
| videolan/dav1d,videolan/dav1d | src/x86/cdef_avx2.asm | bsd-2-clause | 1,589,119,623 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
24220defd649fc8984b0e9e959b7ab70694f480a | Save 16 bytes in the CGB boot ROM | Save 16 bytes in the CGB boot ROM
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,589,022,711 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... |
184743637eebf34f5fc673057dbca954037f3599 | Fix silly regression | Fix silly regression
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,716,646 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... |
730567dc609a1213d6395ca92d4be00c072a2817 | Proper color mixing | Proper color mixing
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,716,382 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM)
ld h, $... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM
ld h, $D... |
a3f261184d2a732b32eb30d6b3538b04fba31988 | Optimize more | Optimize more
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,632,288 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
call ClearMemoryPage8000
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM
ld h, $D... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... |
f46f138e9fbda089a1a9f71b88d608b38b932315 | Clear VRAM correctly | Clear VRAM correctly
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,625,683 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... |
72a90ba91c8b8ee07859fc25f6b536a5f5afaaad | Hacky color blending | Hacky color blending
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,547,823 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... |
b057e0d10af8394671e2af8d463c2f948e860f5f | Save 4 more bytes in the CGB boot ROM | Save 4 more bytes in the CGB boot ROM
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,540,073 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... |
19126df7f4b69ca8001b6d2ca6b2c703b7625195 | Save 8 bytes in the CGB boot ROM | Save 8 bytes in the CGB boot ROM
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/cgb_boot.asm | mit | 1,588,538,516 | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... | ; SameBoy CGB bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
call ClearMemoryPage
ld a, 2
ld c, $70
ld [c], a
; Clear RAM Bank 2 (Like the original boot ROM... |
a72bfd4ebc1b81af90c8d3245a44a6fa89134e50 | PCInet-PCI II Am79c970 | PCInet-PCI II Am79c970
| davidjwalling/CustomOS | src/os.asm | mit | 1,587,854,135 | ;=======================================================================================================================
;
; File: os.asm
;
; Project: OS
;
; Description: A rudimentary operating system for the x86 architecture.
;
; Revised: 1 January 2020
;
; Ass... | ;=======================================================================================================================
;
; File: os.asm
;
; Project: OS
;
; Description: A rudimentary operating system for the x86 architecture.
;
; Revised: 1 January 2020
;
; Ass... |
0197c966da91cc2cecc0884ccaf332aa81b32deb | test: Add BR3392630 | test: Add BR3392630
Add the test code into the existing xdefine testing.
Suggested-by: C. Masloch <33adfa7aa2bbcf32c58163f4aa6af99d90610803@ulukai.org>
Link: https://bugzilla.nasm.us/show_bug.cgi?id=3392630
Signed-off-by: Chang S. Bae <1d3f92548958be2d2740f7fde91f16f33389a300@intel.com>
| techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm | test/xdefine.asm | bsd-2-clause | 1,587,503,493 | %idefine d dword
%define _1digits_nocheck(d) (((d)% 10)+'0')
%xdefine _1digits(d) (!!(d/10)*(1<<32)+ _1digits_nocheck(d))
db _1digits(8) ; Should be 0x38
%define n 0x21
%xdefine ctr n
%define n 0x22
db ctr, n ; Should be 0x21, 0x22
%define MNSUFFIX
%define MNCURRENT TEST%[MNSUFFIX]
%xdefine ... | %idefine d dword
%define _1digits_nocheck(d) (((d)% 10)+'0')
%xdefine _1digits(d) (!!(d/10)*(1<<32)+ _1digits_nocheck(d))
db _1digits(8) ; Should be 0x38
%define n 0x21
%xdefine ctr n
%define n 0x22
db ctr, n ; Should be 0x21, 0x22
|
114e8f0ee53ba34d22452dc4bdc0e9ec263189c8 | x86: Eliminate redundant 3-operand register syntax in itx | x86: Eliminate redundant 3-operand register syntax in itx
Purely a cosmetic change.
| videolan/dav1d,videolan/dav1d | src/x86/itx.asm | bsd-2-clause | 1,587,431,558 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
12b46a2bfca588b54924721e750cc9c9e3c2d3bc | Keyboard kernel fixes from Pavel Zagrebin | Keyboard kernel fixes from Pavel Zagrebin
| reenigne/reenigne,reenigne/reenigne,reenigne/reenigne,reenigne/reenigne | 8088/dos/keyboard_kernel.asm | unlicense | 1,586,162,787 | %include "../defaults_bin.asm"
jmp codeStart
db '20171011-keyb',0
codeStart:
mov ax,cs
mov ds,ax
call findIP
findIP:
pop bx
sub bx,findIP
sub di,0x500
cmp di,kernelEnd
je lengthOk1
or byte[flags + bx],1
lengthOk1:
mov ah,0
mov cx,checkSum
mov si,bx
checksumLoop:
lodsb
add ah,al
... | %include "../defaults_bin.asm"
jmp codeStart
db '20171011-keyb',0
codeStart:
mov ax,cs
mov ds,ax
call findIP
findIP:
pop bx
sub bx,findIP
sub di,0x500
cmp di,kernelEnd
je lengthOk1
or byte[flags + bx],1
lengthOk1:
mov ah,0
mov cx,checkSum
mov si,bx
checksumLoop:
lodsb
add ah,al
... |
1717ac939c12e31a358056a36c2fa7a8882e71ed | x86_abi_support: do not decorate coff functions | x86_abi_support: do not decorate coff functions
:private_extern only applies to macho. Match x86inc.asm logic:
%if FORMAT_ELF
global %2:function hidden
%elif FORMAT_MACHO
global %2:private_extern
%else
global %2
%endif
May fix a build issue on windows:
vp8/encoder/x86/block_error_sse2.asm:18: error:
COFF form... | webmproject/libvpx,ShiftMediaProject/libvpx,webmproject/libvpx,ShiftMediaProject/libvpx,webmproject/libvpx,ShiftMediaProject/libvpx,webmproject/libvpx,webmproject/libvpx,webmproject/libvpx,ShiftMediaProject/libvpx,ShiftMediaProject/libvpx,ShiftMediaProject/libvpx | vpx_ports/x86_abi_support.asm | bsd-3-clause | 1,586,156,817 | ;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing proje... | ;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing proje... |
53ca4bb19cc4f3147891c03d10959d57e0edcc01 | test: Add BR 3392630 | test: Add BR 3392630
Add the test code into the existing xdefine testing.
Suggested-by: C. Masloch <33adfa7aa2bbcf32c58163f4aa6af99d90610803@ulukai.org>
Link: https://bugzilla.nasm.us/show_bug.cgi?id=3392630
Signed-off-by: Chang S. Bae <1d3f92548958be2d2740f7fde91f16f33389a300@intel.com>
| techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm,techkey/nasm | test/xdefine.asm | bsd-2-clause | 1,585,780,904 | %idefine d dword
%define _1digits_nocheck(d) (((d)% 10)+'0')
%xdefine _1digits(d) (!!(d/10)*(1<<32)+ _1digits_nocheck(d))
db _1digits(8) ; Should be 0x38
%define n 0x21
%xdefine ctr n
%define n 0x22
db ctr, n ; Should be 0x21, 0x22
%define MNSUFFIX
%define MNCURRENT TEST%[MNSUFFIX]
%xdefine ... | %idefine d dword
%define _1digits_nocheck(d) (((d)% 10)+'0')
%xdefine _1digits(d) (!!(d/10)*(1<<32)+ _1digits_nocheck(d))
db _1digits(8) ; Should be 0x38
%define n 0x21
%xdefine ctr n
%define n 0x22
db ctr, n ; Should be 0x21, 0x22
|
b73acaa894ac4bb66d04d27919e436c158be7fe8 | x86: use btc instead of xor+test or 32byte alignment in fgy_32x32xn_ssse3 | x86: use btc instead of xor+test or 32byte alignment in fgy_32x32xn_ssse3
| videolan/dav1d,videolan/dav1d | src/x86/film_grain_ssse3.asm | bsd-2-clause | 1,585,752,622 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
fcc94fa905ba4d87f3383d517fbf6fcb08006ffc | x86: use btc instead of xor+test in fgy_32x32xn_avx2 | x86: use btc instead of xor+test in fgy_32x32xn_avx2
| videolan/dav1d,videolan/dav1d | src/x86/film_grain.asm | bsd-2-clause | 1,585,752,581 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
4dd943156dba5e182cee8d5fda764ab1c8537eae | x86: don't use vptest in SSSE3 version | x86: don't use vptest in SSSE3 version
This is the VEX (AVX) encoded variant for the SSE4 instruction ptest,
so emulate it using pmovmskb in the SSSE3 version.
| videolan/dav1d,videolan/dav1d | src/x86/mc_ssse3.asm | bsd-2-clause | 1,585,664,768 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source c... |
b3d12b3c7fe4b12f4dee68d0f15dfb2c825c867e | nasm: require 2.14 with -DCHROMIUM | nasm: require 2.14 with -DCHROMIUM
BUG=webm:1679
Change-Id: I75b1f860d111febf0aabe38b89d845ef296728a4
| ShiftMediaProject/libvpx,webmproject/libvpx,webmproject/libvpx,webmproject/libvpx,ShiftMediaProject/libvpx,webmproject/libvpx,webmproject/libvpx,ShiftMediaProject/libvpx,ShiftMediaProject/libvpx,webmproject/libvpx,ShiftMediaProject/libvpx,ShiftMediaProject/libvpx | vpx_ports/x86_abi_support.asm | bsd-3-clause | 1,585,636,599 | ;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing proje... | ;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing proje... |
b583d4af8d0917ce102706223546756b7a4b9c66 | max ammo: fix warnpc address. | max ammo: fix warnpc address.
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/max_ammo_display.asm | mit | 1,585,472,302 | ;;; Display in HUD the maximum number of ammo that samus can carry
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p=section),
;;; or a variant of xkas that supports arch directive
lorom
arch snes.cpu
;;; $9D98: Draw two HUD digits ;;;
;;; Parameters:
;;; A: Number to draw ... | ;;; Display in HUD the maximum number of ammo that samus can carry
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p=section),
;;; or a variant of xkas that supports arch directive
lorom
arch snes.cpu
;;; $9D98: Draw two HUD digits ;;;
;;; Parameters:
;;; A: Number to draw ... |
f2467150ea47c3a81d47dbf29330b90d814a342e | asm: added fixed place function for save last stats | asm: added fixed place function for save last stats
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/credits_varia.asm | mit | 1,585,086,633 | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... |
58cd6694adbf6105cae60eaccc6ca41666f1b487 | asm: fixed stack issues in credits | asm: fixed stack issues in credits
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/credits_varia.asm | mit | 1,585,077,381 | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... |
870f144475e0d585f5ffa4722336c556d2e90296 | max ammo display: working version with three digits for super/pb | max ammo display: working version with three digits for super/pb
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/max_ammo_display.asm | mit | 1,585,072,931 | ;;; Display in HUD the maximum number of ammo that samus can carry
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p=section),
;;; or a variant of xkas that supports arch directive
lorom
arch snes.cpu
;;; $9D98: Draw two HUD digits ;;;
;;; Parameters:
;;; A: Number to draw ... | ;;; Display in HUD the maximum number of ammo that samus can carry
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p=section),
;;; or a variant of xkas that supports arch directive
lorom
arch snes.cpu
;;; $9D98: Draw two HUD digits ;;;
;;; Parameters:
;;; A: Number to draw ... |
2a6aa853a77fcf396d3a84a782447004053f86b5 | asm: redone save/load stats to implement 'last stats'. testing TODO | asm: redone save/load stats to implement 'last stats'. testing TODO
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/credits_varia.asm | mit | 1,584,918,719 | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... |
f633ed26e12faf476836fc37d354ee05f9060ea7 | asm: redinted credits | asm: redinted credits
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/credits_varia.asm | mit | 1,584,876,549 | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... | // custom credits
arch snes.cpu
lorom
// Defines for the script and credits data
define speed $f770
define set $9a17
define delay $9a0d
define draw $0000
define end $f6fe, $99fe
define blank $1fc0
define row $0040
define pink "table tables/pink.tbl"
define yellow "table tables/yellow.tbl"
define cyan "table tables/cya... |
4bc5d2ed9b3ec2891ea9025d0821f6000c749a17 | asm: tracking - reindented and removed all arm pump code | asm: tracking - reindented and removed all arm pump code
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/tracking.asm | mit | 1,584,875,988 | arch snes.cpu
lorom
// Addresses to helper functions for stat tracking
define inc_stat $dfd800 // Inc stat, stat id in A
define dec_stat $dfd840 // Dec stat, stat id in A
define store_stat $dfd880 // Store stat, value in A, stat id in X
define load_stat $dfd8b0 // Load stat, stat id in A, ... | arch snes.cpu
lorom
// Addresses to helper functions for stat tracking
define inc_stat $dfd800 // Inc stat, stat id in A
define dec_stat $dfd840 // Dec stat, stat id in A
define store_stat $dfd880 // Store stat, value in A, stat id in X
define load_stat $dfd8b0 // Load stat, stat id in A, ... |
943b3a8f4afe92038dc03e34f776e353ace25466 | asm: reindented bomb_torizo | asm: reindented bomb_torizo
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/bomb_torizo.asm | mit | 1,584,831,468 |
;;; makes it so that BT will wake up only once you picked up
;;; the item he's holding, whatever it is
lorom
arch snes.cpu
!CurrentRoom = $7e079b
!BTRoom = #$9804
!BTRoomFlag = $7ed86c ; some free RAM for the flag
!PickedUp = #$bbbb
;;; hijack item collection routine (different hijack point than endingtot... |
;;; makes it so that BT will wake up only once you picked up
;;; the item he's holding, whatever it is
lorom
arch snes.cpu
!CurrentRoom = $7e079b
!BTRoom = #$9804
!BTRoomFlag = $7ed86c ; some free RAM for the flag
!PickedUp = #$bbbb
;;; hijack item collection routine (different hijack point than endingt... |
f3c90d0f015770f1089224e78e44f1f32555ca7e | asm: random music - fixed bug in RNG seed + simplified music change algorithm | asm: random music - fixed bug in RNG seed + simplified music change algorithm
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/random_music.asm | mit | 1,584,819,367 | ;;; Randomize music in game
;;;
;;; Music will change only if music requested by the game is different from last
;;; requested music.
;;;
;;; Uses RNG routine but does not alter current RNG number.
;;; Uses tracking patch RTA timer to seed RNG.
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p... | ;;; Randomize music in game
;;;
;;; Music will change only if music requested by the game is different from last
;;; requested music.
;;;
;;; Uses RNG routine but does not alter current RNG number.
;;; Uses tracking patch RTA timer to seed RNG.
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p... |
2a62830c74e7282857b779ed6a0c85dc081b7cbe | asm: random music - lower proba of WS/Tourian songs to happen | asm: random music - lower proba of WS/Tourian songs to happen
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/random_music.asm | mit | 1,584,813,982 | ;;; Randomize music in game
;;;
;;; Music will change only if music requested by the game is different from last
;;; requested music.
;;;
;;; Uses RNG routine but does not alter current RNG number.
;;; Uses tracking patch RTA timer to seed RNG.
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p... | ;;; Randomize music in game
;;;
;;; Music will change only if music requested by the game is different from last
;;; requested music.
;;;
;;; Uses RNG routine but does not alter current RNG number.
;;; Uses tracking patch RTA timer to seed RNG.
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p... |
37a95e5bd57e671fa0b0e7b99f7821ac464e1966 | asm: reindent random_music | asm: reindent random_music
| theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver,theonlydude/RandomMetroidSolver | itemrandomizerweb/patches/random_music.asm | mit | 1,584,812,984 | ;;; Randomize music in game
;;;
;;; Music will change only if music requested by the game is different from last
;;; requested music.
;;;
;;; Uses RNG routine but does not alter current RNG number.
;;; Uses tracking patch RTA timer to seed RNG.
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p... | ;;; Randomize music in game
;;;
;;; Music will change only if music requested by the game is different from last
;;; requested music.
;;;
;;; Uses RNG routine but does not alter current RNG number.
;;; Uses tracking patch RTA timer to seed RNG.
;;;
;;; compile with asar (https://www.smwcentral.net/?a=details&id=14560&p... |
d8568fe2396accac7f321a36fa94bfd92a02df4b | Update documentation | Update documentation
| davidjwalling/CustomOS | os.002/os.asm | mit | 1,584,417,124 | ;=======================================================================================================================
;
; File: os.asm
;
; Project: os.002
;
; Description: This sample program adds code to load the operating system kernel program from the disk image.
; ... | ;=======================================================================================================================
;
; File: os.asm
;
; Project: os.002
;
; Description: This sample program adds code to load the operating system kernel program from the disk image.
; ... |
97829c1fdbccedaf014ee7e9d9f982a58b890668 | More readable logs from find_handle and recv in asm kernel | More readable logs from find_handle and recv in asm kernel
| olsner/os,olsner/os,olsner/os,olsner/os,olsner/os | kasm/kstart.asm | mit | 1,584,193,252 | [map all]
;
; Configuration
; NB: Enable too many of these and the kernel pops too close to 8kB and stops
; working.
%define log_switch_to 0
%define log_switch_next 0
%define log_idle 0
%define log_runqueue 0
%define log_runqueue_panic 0
%define log_fpu_switch 0 ; Note: may clobber user registers if activated :)
%defin... | [map all]
;
; Configuration
; NB: Enable too many of these and the kernel pops too close to 8kB and stops
; working.
%define log_switch_to 0
%define log_switch_next 0
%define log_idle 0
%define log_runqueue 0
%define log_runqueue_panic 0
%define log_fpu_switch 0 ; Note: may clobber user registers if activated :)
%defin... |
e1376102480a26b7b464d8e672b56a82c9a32da1 | Implement #9280 for MSVC64 (#9358) | Implement #9280 for MSVC64 (#9358)
Follow-up to 4d4a056bc | gerdstolpmann/ocaml,gerdstolpmann/ocaml,gerdstolpmann/ocaml,gerdstolpmann/ocaml,gerdstolpmann/ocaml,gerdstolpmann/ocaml | runtime/amd64nt.asm | lgpl-2.1 | 1,583,845,827 | ;**************************************************************************
;* *
;* OCaml *
;* *
;* X... | ;**************************************************************************
;* *
;* OCaml *
;* *
;* X... |
ee939a378258b647fa95a6c61aaf3314d6b69f42 | New boot ROM animation in the DMG boot ROM | New boot ROM animation in the DMG boot ROM
| LIJI32/SameBoy,LIJI32/SameBoy,LIJI32/SameBoy | BootROMs/dmg_boot.asm | mit | 1,583,509,038 | ; SameBoy DMG bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
.clearVRAMLoop
ldi [hl], a
bit 5, h
jr z, .clearVRAMLoop
; Init Audio
ld a, $80
ldh [$26]... | ; SameBoy DMG bootstrap ROM
; Todo: use friendly names for HW registers instead of magic numbers
SECTION "BootCode", ROM0[$0]
Start:
; Init stack pointer
ld sp, $fffe
; Clear memory VRAM
ld hl, $8000
.clearVRAMLoop
ldi [hl], a
bit 5, h
jr z, .clearVRAMLoop
; Init Audio
ld a, $80
ldh [$26]... |
1a65d795f7b83f3538538a1f444285668793b988 | x86: add prep_8tap AVX512 asm | x86: add prep_8tap AVX512 asm
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
884b0f6e0b46bcb1edbc76e5393fc13796795a49 | x86: Fix AVX2 inverse identity transform overflow/clipping | x86: Fix AVX2 inverse identity transform overflow/clipping
The coefficients after the first (8-bit) 1D identity transform may
require more than 16 bits precision before downshifting in some cases,
and they may also need to be clipped to int16_t after downshifting.
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/itx.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
153e37e3a5ea7a841b343fc1a7219c613b3431aa | x86: Add mc w_mask 4:2:2 AVX-512 (Ice Lake) asm | x86: Add mc w_mask 4:2:2 AVX-512 (Ice Lake) asm
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
167371c3ac91507b51418b61af60c5119c19dfb3 | x86/msac: add an avx2 version for msac_decode_symbol_adapt16 | x86/msac: add an avx2 version for msac_decode_symbol_adapt16
msac_decode_symbol_adapt16_c: 55.1
msac_decode_symbol_adapt16_sse2: 30.3
msac_decode_symbol_adapt16_avx2: 28.0
Most code written by Henrik Gramner.
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/msac.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
d73e5334ee465072db6a5f5563ac5f756444bdfd | x86: Fix SSSE3 inverse identity transform overflow/clipping | x86: Fix SSSE3 inverse identity transform overflow/clipping
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/itx_ssse3.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
6f7773dff705c47245df23d19559caeca2ceee1a | x86: add avx512icl cpu flag to x86inc.asm | x86: add avx512icl cpu flag to x86inc.asm
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/ext/x86/x86inc.asm | bsd-2-clause | 1,583,503,017 | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2019 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2019 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... |
729b09fc80014f963adfe4b57459c95d16359494 | x86: add prep_bilin AVX512 asm | x86: add prep_bilin AVX512 asm
------------------------------------------
mct_bilinear_w4_0_8bpc_avx2: 3.8
mct_bilinear_w4_0_8bpc_avx512icl: 3.7
---------------------
mct_bilinear_w8_0_8bpc_avx2: 5.0
mct_bilinear_w8_0_8bpc_avx512icl: 4.8
---------------------
mct_bilinear_w16_0_8bpc_avx2: 8.5
mct_biline... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
09186ea8a715b4e479a5f16b6d56c786aac3a78f | Simplify shifting in generate_grain_y/uv AVX2 | Simplify shifting in generate_grain_y/uv AVX2
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/film_grain.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2019, VideoLAN and dav1d authors
; Copyright © 2019, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
e1762480709d87bfe2c946e87d2532622d4179bd | x86: Add mc w_mask 4:4:4 AVX-512 (Ice Lake) asm | x86: Add mc w_mask 4:4:4 AVX-512 (Ice Lake) asm
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
ce58d98b7b73c2d811a0baf88639b475591227ea | x86inc: save xmm_regs_used in spill_xmm for non-win64 | x86inc: save xmm_regs_used in spill_xmm for non-win64
This allows for AVX-512 code to issue vzeroupper automatically in RET,
when not specified in cglobal but later on, along WIN64_SPILL_XMM.
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/ext/x86/x86inc.asm | bsd-2-clause | 1,583,503,017 | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2019 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... | ;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2019 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Henrik Gramner... |
c8118d72c1c9d83a8be630bd4d5312241fc87582 | x86: Add mc w_mask 4:2:0 AVX-512 (Ice Lake) asm | x86: Add mc w_mask 4:2:0 AVX-512 (Ice Lake) asm
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
ee51cf16781d93824ad4548c9daf745231322259 | x86: replace "mov hb, Xb" by "movzx hd, Xb" in MC | x86: replace "mov hb, Xb" by "movzx hd, Xb" in MC
It's a little easier for the CPU to simply overwrite a 32-bit reg rather
than writing it's low 8 bits while conserving bits 8 to 31.
In order to do that it actually fetches those bits, merge to a 32-bit
value, and write that back to the 32-bit GPR.
As those are always... | xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
13f1dd284e1fb64a188618daa9f01d1be3963bab | x86: Fix overflows in SSSE3 idct | x86: Fix overflows in SSSE3 idct
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/itx_ssse3.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
92edd252bd8dd99c43ad3965817bd409881fbce0 | x86: Add mc avg/w_avg/mask AVX-512 (Ice Lake) asm | x86: Add mc avg/w_avg/mask AVX-512 (Ice Lake) asm
| xiph/rav1e,xiph/rav1e,xiph/rav1e | src/x86/mc.asm | bsd-2-clause | 1,583,503,017 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
3a6a55d8d5883cf094bc3a140e568420014bbf47 | x86: Fix crash in AVX2 cdef_filter with <32-byte stack alignment | x86: Fix crash in AVX2 cdef_filter with <32-byte stack alignment
| videolan/dav1d,videolan/dav1d | src/x86/cdef.asm | bsd-2-clause | 1,583,359,545 | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... | ; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copy... |
246e1b5b8acf9f2779da4a465658f6d24cd857fb | fix string compile | fix string compile
| MateoConLechuga/Cesium | src/strings.asm | bsd-3-clause | 1,583,026,237 | ; commonly used strings
string_cesium:
db cesium_name,0
string_cesium_version:
db cesium_name,' Version ',cesium_version,0
string_asm:
db 'eZ80',0
string_c:
db 'C',0
string_ice:
db 'ICE',0
string_ice_source:
db 'ICE S',0
string_directory:
db 'Folder',0
string_usb:
db 'USB',0
string_basic:
db 'Basic',0
string_... | ; commonly used strings
string_cesium:
db cesium_name,0
string_cesium_version:
db cesium_name,' Version ',cesium_version,0
string_asm:
db 'eZ80',0
string_c:
db 'C',0
string_ice:
db 'ICE',0
string_ice_source:
db 'ICE S',0
string_directory:
db 'Folder',0
string_usb:
db 'USB',0
string_basic:
db 'Basic',0
string_... |
98cdea1628036dc6a7e7a455947ce3c345b02975 | limit rate bars to their intended bounds | limit rate bars to their intended bounds
in some cases the rate bar code was falling through to clear sprites
but writing past their intended bounds corrupting unused wram.
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>
| mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,821,821 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
89f5b817e0c531893842dbed742da36b33418bb9 | Fix player 2 sprites | Fix player 2 sprites
Sprites for player 2 were flickering because they were comparing an
address rather than an immediate value.
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>
| mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,818,270 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
bbff00443864195d4a79844fe8d5bc442338205a | disable rendering while writing game attributes | disable rendering while writing game attributes
if rendering is enabled during write operations the data will get
written to an unintended address resulting in graphical corruption.
add a missed case when writing game attributes, snap the screen
back to screen 0 after writing as a tradeoff between seeing screen 1
for... | mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,813,589 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
bda25272a890e1866163e1ca7df2004fdcc83f7a | move sprites off screen to a consistent position | move sprites off screen to a consistent position
FE should be a consistent position to move sprites off screen,
rate bar may still be visible on the y axis on some frames due
to the way the loop is written, further investigation needed
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>
| mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,811,803 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
666379018bc2d98c3d16984e68e8539c4d43540a | push initial sprite state to ppu, bug fixes | push initial sprite state to ppu, bug fixes
pushing the initial sprite state to the ppu before we start rendering
should prevent a single frame of random sprites littered on the
screen. also fix a bug in a previous patch involving bitfields.
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.c... | mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,758,511 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
c4b4783644a95229043eebce407ab9574c5fbc9f | correct address in memory clearing routine | correct address in memory clearing routine
FE is written to shadow OAM to ensure sprite slots aren't drawn on
the screen if they are unused. $0200 is being used for shadow OAM.
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>
| mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,757,451 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
ec5247d2d794af0add02826096a1895e7fc2e96e | disable bg and spr rendering during ppu writes | disable bg and spr rendering during ppu writes
if rendering is enabled during write operations the data will get
written to an unintended address resulting in graphical corruption.
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>
| mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,757,282 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
297f9f0cb639ab672db151b4c83a2ce432b5a53a | update labels for readability | update labels for readability
some labels were missing colons, updated some addresses to use labels
Signed-off-by: bunder2015 <8895d4710d634bf3eedbb49460627c10b2e5d1b0@gmail.com>
| mitch3b/MashyMashy | MashyMashy.asm | mit | 1,582,756,827 | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... | .inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; background mirroring (horizontal scrolling)
;MITCH
; .include "TitleScreen.asm"
; -----------------------------------
; Standard NES registers
PPU_CTRL_REG1 = $2... |
b40d93a8b88491b394a9aab5321fd722f9aa4fc9 | Comment tweaks | Comment tweaks
| kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom,kervinck/gigatron-rom | puzz15.asm | bsd-2-clause | 1,582,719,506 | ; "15 puzzle" for the Apple I
; Jeff Jetton
; Februrary 2020
; Written for the dasm assembler, but should assemble under others
; with a few tweaks here and there.
processor 6502
; Contants
KBD equ $D010 ; Location of input character from keyboard
KBDCR equ $D011 ... | ; "15 puzzle" for the Apple I
; Jeff Jetton
; Februrary 2020
; Written for the dasm assembler, but should assemble under others
; with a few tweaks here and there.
; TODO: UPdate maketape to create monitor text file
; https://www.applefritter.com/node/24600#comment-60100
; TODO: Rewrite initpuzz and checkwin to... |
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