prompt stringlengths 162 4.26M | response stringlengths 109 5.16M |
|---|---|
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {
require (numIds > 0)
val idWidth... | module IDPool(
input clock,
input reset,
input io_free_valid,
input [2:0] io_free_bits,
input io_alloc_ready,
output io_alloc_valid,
output [2:0] io_alloc_bits
);
reg [7:0] bitmap;
reg [2:0] select;
reg valid;
wire [7:0] taken = io_alloc_ready ? 8'h1 <<... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module data_40x37(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [36:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [36:0] W0_data
);
reg [36:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] ... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or c... | module ClockCrossingReg_w32(
input clock,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
reg [31:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util.{Cat, Valid}
import org.chipsalliance.cde.config.Parameters
import fr... | module CaptureChain_JTAGIdcodeBundle(
input clock,
input reset,
input io_chainIn_shift,
input io_chainIn_data,
input io_chainIn_capture,
input io_chainIn_update,
output io_chainOut_data
);
reg regs_0;
reg regs_1;
reg regs_2;
reg regs_3;
reg regs_4;
reg regs_5;
reg regs_6;
reg regs_7... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module LoopBranchPredictorColumn(
input clock,
input reset,
input [36:0] io_f2_req_idx,
input io_f3_req_fire,
input io_f3_pred_in,
output io_f3_pred,
output [9:0] io_f3_meta_s_cnt,
input io_update_mispredict,
input io_update_repair,
input [36... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundRawFNToRecFN_e8_s24(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [9:0] io_in_sExp,
input [26:0] io_in_sig,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exception... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module ebtb(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [39:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [39:0] W0_data
);
ebtb_ext ebtb_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_da... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module regfile_48x65(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [64:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [64:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [64:0] R2_data,
input... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RecFNToIN_e11_s53_i64(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [63:0] io_out,
output [2:0] io_intExceptionFlags
);
wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61];
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire ... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module FMADecoder(
input [6:0] io_uopc,
output [1:0] io_cmd
);
wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);
assign io_cmd = {|{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decod... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RecFNToIN_e11_s53_i32(
input [64:0] io_in,
input [2:0] io_roundingMode,
input io_signedOut,
output [2:0] io_intExceptionFlags
);
wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0);
... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module TageTable_1(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module ghist_1(
input [3:0] R0_addr,
input R0_clk,
output [71:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [71:0] W0_data
);
ghist_0_ext ghist_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_ad... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.roc... | module PipelinedMultiplier(
input clock,
input reset,
input io_req_valid,
input [4:0] io_req_bits_fn,
input io_req_bits_dw,
input [63:0] io_req_bits_in1,
input [63:0] io_req_bits_in2,
output [63:0] io_resp_bits_data
);
reg in_pipe_v;
reg [4:0] in_pipe... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module TageTable_5(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module TageTable_4(
input clock,
input reset,
input io_f1_req_valid,
input [39:0] io_f1_req_pc,
input [63:0] io_f1_req_ghist,
output io_f3_resp_0_valid,
output [2:0] io_f3_resp_0_bits_ctr,
output [1:0] io_f3_resp_0_bits_u,
output io_f3_resp_1_valid,
output [... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module tail_40x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [5:0] R1_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module DivUnit(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [4:0] io_req_bits_uop_ctrl_op_fcn,
input io_req_bits_uop_ctrl_fcn_dw,
input [7:0] io_req_bits_uop_br_mask,
input [4:0] io_req_bits_uop_rob_idx,
input [5:0] io_req_bit... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
... | module dataArrayWay_1(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module BasicDispatcher(
output io_ren_uops_0_ready,
input io_ren_uops_0_valid,
input [6:0] io_ren_uops_0_bits_uopc,
input [31:0] io_ren_uops_0_bits_inst,
input [31:0] io_ren_uops_0_bits_debug_inst,
input io_ren_uops_0_bits_is_rvc,
input [39:0] io_ren_uops_0_bits_debug_pc,
inp... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericDeserializer_TLBeatw87_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output io_out_bits_head,
output io_out_bits_tail
);
reg [31... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module hi_us_4(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_dat... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module BranchPredictor(
input clock,
input reset,
input io_f0_req_valid,
input [39:0] io_f0_req_bits_pc,
input [63:0] io_f0_req_bits_ghist_old_history,
output io_resp_f1_preds_0_taken,
output io_resp_f1_preds_0_is_br,
output io_resp_f1_preds_0_is_ja... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or c... | module ClockCrossingReg_w55(
input clock,
input [54:0] io_d,
output [54:0] io_q,
input io_en
);
reg [54:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end
assign io_q = cdc_reg;
endmodule |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module lo_us_2(
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [7:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_0_ext hi_us_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
class Atomics(params: TLBundleParameters) extends Module
{
val io = IO(new Bundle {
val write = Flipped(Bool()) // ignore opcode... | module Atomics(
input io_write,
input [2:0] io_a_opcode,
input [2:0] io_a_param,
input [3:0] io_a_mask,
input [31:0] io_a_data,
input [31:0] io_data_in,
output [31:0] io_data_out
);
wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};
wire [3:0] signBit = io_a_mask & {1'h1, ~(io_a_m... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyField... | module TLEFromBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedg... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module DivSqrtRecF64(
input clock,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
output io_out... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module data_35x43(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [42:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [42:0] W0_data
);
reg [42:0] Memory[0:34];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] ... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module data_33x44(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [43:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [43:0] W0_data
);
reg [43:0] Memory[0:32];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] ... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module btb_1(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [55:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [55:0] W0_data,
input [3:0] W0_mask
);
btb_0_ext btb_0_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module SinkE(
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid;
assign io_resp_bits_sink = io_e_bits_sink;
endmodule |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have ... | module AsyncResetRegVec_w1_i0(
input clock,
input reset,
input io_d,
output io_q
);
reg reg_0;
always @(posedge clock or posedge reset) begin
if (reset)
reg_0 <= 1'h0;
else
reg_0 <= io_d;
end
assign io_q = reg_0;
endmodule |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundAnyRawFNToRecFN_ie8_is24_oe11_os53(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out
);
wire isNaNOut = io_invalidExc | io_in_isN... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module tag_array_0(
input [5:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [79:0] RW0_wdata,
output [79:0] RW0_rdata,
input [3:0] RW0_wmask
);
tag_array_0_ext tag_array_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyField... | module TLAFromBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(posedg... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module FPUExeUnit(
input clock,
input reset,
output [9:0] io_fu_types,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debu... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericSerializer_TLBeatw87_f32(
input clock,
input reset,
input io_in_bits_head,
input io_in_bits_tail,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
wire [0:0][31:0] _GEN = '{32'h0};
reg [31:0] data_1;
reg [... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericSerializer_TLBeatw10_f32(
input io_in_bits_head,
output [31:0] io_out_bits_flit
);
assign io_out_bits_flit = {30'h0, io_in_bits_head, 1'h1};
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericSerializer_TLBeatw67_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [64:0] io_in_bits_payload,
input io_in_bits_head,
input io_in_bits_tail,
input io_out_ready,
output io_out_valid,
output [31:0... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rock... | module IBuf(
input clock,
input reset,
output io_imem_ready,
input io_imem_valid,
input io_imem_bits_btb_taken,
input io_imem_bits_btb_bridx,
input [4:0] io_imem_bits_btb_entry,
input [7:0] io_imem_bits_btb_bht_history,
input [39:0] io_imem_bits_pc,
... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module DivSqrtRecFM_small_e5_s11(
input clock,
input reset,
output io_inReady,
input io_inValid,
input io_sqrtOp,
input [16:0] io_a,
input [16:0] io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [16:... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module Rob(
input clock,
input reset,
input io_enq_valids_0,
input [6:0] io_enq_uops_0_uopc,
input [31:0] io_enq_uops_0_debug_inst,
input io_enq_uops_0_is_rvc,
input io_enq_uops_0_is_br,
input io_enq_uops_0_is_jalr,
input io_enq_uops_0_is_jal,... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module PhitToFlit_p32_f32_TestHarness_UNIQUIFIED(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_phit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module MulAddRecFNToRaw_postMul_e11_s53(
input io_fromPreMul_isSigNaNAny,
input io_fromPreMul_isNaNAOrB,
input io_fromPreMul_isInfA,
input io_fromPreMul_isZeroA,
input io_fromPreMul_isInfB,
input io_fromPreMul_isZeroB,
input io_fromPreMul_sign... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
... | module MulAddRecFNPipe_l2_e11_s53(
input clock,
input reset,
input io_validin,
input [1:0] io_op,
input [64:0] io_a,
input [64:0] io_b,
input [64:0] io_c,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags,
output io_validout
);... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module lo_us_3(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_dat... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module next_33x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:32];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyField... | module TLCToBeat_SerialRAM_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_bits_head
);
assign io_beat_bits_head = 1'h1;
endmodule |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericSerializer_TLBeatw88_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [85:0] io_in_bits_payload,
input io_in_bits_head,
input io_in_bits_tail,
input io_out_ready,
output io_out_valid,
output [31:0... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module regfile_52x64(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [63:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [63:0] R2_data,
input... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copi... | module Repeater_TLBundleA_a28d64s3k1z3u(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [2:0] ... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module ListBuffer_PutBufferAEntry_q40_e40(
input clock,
input reset,
output io_push_ready,
input io_push_valid,
input [5:0] io_push_bits_index,
input [31:0] io_push_bits_data_data,
input [3:0] io_push_bits_data_mask,
input io_push_bits_data_corrupt,
output [... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module table_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [43:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [43:0] W0_data,
input [3:0] W0_mask
);
table_ext table_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericDeserializer_TLBeatw88_f32(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output [85:0] io_out_bits_payload,
output io_out_bits_head,
output ... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module head_15x6(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data,
input [3:0] W1_addr,
input W1_en,
input W1_clk,
input [5:0] W1_data
);
reg [5:0] Memory[0... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module ListBuffer_QueuedRequest_q21_e33(
input clock,
input reset,
output io_push_ready,
input io_push_valid,
input [4:0] io_push_bits_index,
input io_push_bits_data_prio_0,
input io_push_bits_data_prio_2,
input io_push_bits_data_control,
input ... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//-----------------------------------------------------------------------... | module BoomProbeUnit(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [1:0] io_req_bits_param,
input [3:0] io_req_bits_size,
input [1:0] io_req_bits_source,
input [31:0] io_req_bits_address,
input io_rep_ready,
output io_r... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericDeserializer_TLBeatw10_f32(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output io_out_bits_head,
output io_out_bits_tail
);
assign io_in_ready = io_out_ready;
assign io_out_val... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module meta_0_0(
input [3:0] R0_addr,
input R0_clk,
output [119:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [119:0] W0_data
);
meta_0_0_ext meta_0_0_ext (
.R0_addr (R0_addr),
.R0_en (1'h1),
.R0_clk (R0_clk),
.R0_data (R0_data),
... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//-----------------------------------------------------------------------... | module BoomIOMSHR(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_deb... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
... | module rockettile_icache_data_arrays_1(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [255:0] RW0_wdata,
output [255:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext (
.RW0_ad... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module SourceB(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_param,
input [12:0] io_req_bits_tag,
input [9:0] io_req_bits_set,
input io_req_bits_clients,
input io_b_ready,
output io_b_valid,
ou... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module CompareRecFN(
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [4:0] io_exceptionFlags
);
wire rawA_isNaN = (&(io_a[63:62])) & io_a[61];
wire rawB_isNaN = (&(io_b[63:62])) & io_b[61];
wire ordered = ~rawA... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class ExpandedInstruct... | module RVCExpander(
input [31:0] io_in,
output [31:0] io_out_bits,
output io_rvc
);
wire [2:0] _io_out_s_funct_T_2 = {io_in[12], io_in[6:5]};
wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_2 == 3'h1, 2'h0};
wire [7:0][2:0] _GEN = {{3'h3}, {3'h2}, {3'h0}, {3'h0}, {3'h7}, {3'h6}, {_io_... |
Generate the Verilog code corresponding to this Chisel code package testchipip.uart
import chisel3._
import chisel3.util._
import chisel3.experimental.{IntParam}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import sifive.block... | module UARTAdapter(
input clock,
input reset,
input io_uart_txd,
output io_uart_rxd
);
wire _rxq_io_enq_ready;
wire _rxq_io_deq_valid;
wire [7:0] _rxq_io_deq_bits;
wire [3:0] _rxq_io_count;
wire _rxm_io_in_ready;
wire _txq_io_enq_ready;
wire _txq_io_deq_valid;
w... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//-----------------------------------------------------------------------... | module BoomWritebackUnit(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [19:0] io_req_bits_tag,
input [5:0] io_req_bits_idx,
input [2:0] io_req_bits_param,
input [3:0] io_req_bits_way_en,
input io_req_bits_voluntary,
input ... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module BranchMaskGenerationLogic(
input clock,
input reset,
input io_is_branch_0,
input io_will_fire_0,
output [2:0] io_br_tag_0,
output [7:0] io_br_mask_0,
output io_is_full_0,
input [7:0] io_brupdate_b1_resolve_mask,
input [7:0] io_brupdate_b2_uop_br_mask,
input... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module MulAddRecFNToRaw_preMul_e5_s11(
input [1:0] io_op,
input [16:0] io_a,
input [16:0] io_b,
input [16:0] io_c,
output [10:0] io_mulAddA,
output [10:0] io_mulAddB,
output [21:0] io_mulAddC,
output io_toPostMul_isSigNaNAny,
output io_toPostMul_isNaNAOrB,
output io_toPostM... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module RegisterReadDecode(
input io_iss_valid,
input [6:0] io_iss_uop_uopc,
input [31:0] io_iss_uop_inst,
input [31:0] io_iss_uop_debug_inst,
input io_iss_uop_is_rvc,
input [39:0] io_iss_uop_debug_pc,
input [2:0] io_iss_uop_iq_type,
input [9:0] io_iss_uop_fu_code,
input [1:0]... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copi... | module Repeater_TLBundleA_a12d64s7k1z3u(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [6:0] ... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module next_40x6(
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0:39];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module GenericDeserializer_TLBeatw67_f32_TestHarness_UNIQUIFIED(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_flit,
input io_out_ready,
output io_out_valid,
output [64:0] io_out_bits_payload,
output io_ou... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module MulAddRecFNToRaw_postMul_e5_s11(
input io_fromPreMul_isSigNaNAny,
input io_fromPreMul_isNaNAOrB,
input io_fromPreMul_isInfA,
input io_fromPreMul_isZeroA,
input io_fromPreMul_isInfB,
input io_fromPreMul_isZeroB,
input io_fromPreMul_signProd,
... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11(
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [6:0] io_in_sExp,
input [13:0] io_in_sig,
input [2:0] io_roundingMode,
outp... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module ALUExeUnit(
input clock,
input reset,
input io_req_valid,
input [6:0] io_req_bits_uop_uopc,
input [31:0] io_req_bits_uop_inst,
input [31:0] io_req_bits_uop_debug_inst,
input io_req_bits_uop_is_rvc,
input [39:0] io_req_bits_uop_debug_pc,
input [2:0] io_req_... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyField... | module TLBFromBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(pose... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module ram_3x77(
input [1:0] R0_addr,
input R0_en,
input R0_clk,
output [76:0] R0_data,
input [1:0] W0_addr,
input W0_en,
input W0_clk,
input [76:0] W0_data
);
reg [76:0] Memory[0:2];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= ... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundRawFNToRecFN_e11_s53_1(
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [2:0] io_roundingMode,
output [64:0] i... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//-----------------------------------------------------------------------... | module lb_16x64(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data
);
reg [63:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <=... |
Generate the Verilog code corresponding to this Chisel code /*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If no... | module tail_21x6(
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [5:0] R0_data,
input [4:0] R1_addr,
input R1_en,
input R1_clk,
output [5:0] R1_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [5:0] W0_data
);
reg [5:0] Memory[0... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module data(
input [10:0] R0_addr,
input R0_en,
input R0_clk,
output [7:0] R0_data,
input [10:0] W0_addr,
input W0_en,
input W0_clk,
input [7:0] W0_data,
input [3:0] W0_mask
);
data_ext data_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module MulAddRecFNToRaw_postMul_e8_s24(
input io_fromPreMul_isSigNaNAny,
input io_fromPreMul_isNaNAOrB,
input io_fromPreMul_isInfA,
input io_fromPreMul_isZeroA,
input io_fromPreMul_isInfB,
input io_fromPreMul_isZeroB,
input io_fromPreMul_signProd,
... |
Generate the Verilog code corresponding to this Chisel code package sifive.blocks.devices.uart
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
/** UARTRx module recivies serial input from Rx port and transmits them to Rx fifo in parallel
*
* ==Datapass==
* Port(Rx) -> sample -> shifte... | module UARTRx_TestHarness_UNIQUIFIED(
input clock,
input reset,
input io_en,
input io_in,
output io_out_valid,
output [7:0] io_out_bits,
input [15:0] io_div
);
reg [1:0] debounce;
reg [12:0] prescaler;
reg [3:0] data_count;
reg [3:0] sample_count;
... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyField... | module TLAFromBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
input io_protocol_ready,
output io_protocol_valid,
output [2:0] io_protocol_bits_opcode,
output [2:0] io_protocol_bits_param,
output [7:0] io_protocol_bits_size,
output [7:0] io_protocol_bits_sourc... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyField... | module TLDFromBeat_serial_tl_0_a64d64s8k8z8c(
input clock,
input reset,
output io_beat_ready,
input io_beat_valid,
input io_beat_bits_head,
input io_beat_bits_tail
);
reg is_const;
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;
wire _GEN = io_beat_ready_0 & io_beat_valid;
always @(pose... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24(
input io_in_isZero,
input io_in_sign,
input [8:0] io_in_sExp,
input [64:0] io_in_sig,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
... | module FPUDecoder(
input [31:0] io_inst,
output io_sigs_wen,
output io_sigs_ren1,
output io_sigs_ren2,
output io_sigs_ren3,
output io_sigs_swap12,
output io_sigs_swap23,
output [1:0] io_sigs_typeTagIn,
output [1:0] io_sigs_typeTagOut,
output io_sig... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
... | module FPUFMAPipe_l3_f32(
input clock,
input reset,
input io_in_valid,
input io_in_bits_ren3,
input io_in_bits_swap23,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_fmaCmd,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
input [64:0] io_in... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11(
input io_in_isZero,
input io_in_sign,
input [8:0] io_in_sExp,
input [64:0] io_in_sig,
input [2:0] io_roundingMode,
output [16:0] io_out,
output [4:0] io_exceptionFlags
);
wire roundingMode_near_even = io_roundingMode == 3'h0;
... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module ram_7x77(
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [76:0] R0_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [76:0] W0_data
);
reg [76:0] Memory[0:6];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= ... |
Generate the Verilog code corresponding to this Chisel code //******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//----------------... | module RegisterReadDecode_2(
input io_iss_valid,
input [6:0] io_iss_uop_uopc,
input [31:0] io_iss_uop_inst,
input [31:0] io_iss_uop_debug_inst,
input io_iss_uop_is_rvc,
input [39:0] io_iss_uop_debug_pc,
input [2:0] io_iss_uop_iq_type,
input [9:0] io_iss_uop_fu_code,
input [1:... |
Generate the Verilog code corresponding to this Chisel code package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSer... | module PhitToFlit_p32_f32(
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits_phit,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_flit
);
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_flit = io_... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module DivSqrtRecF64_mulAddZ31(
input clock,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [2:0] io_roundingMode,
output [3:0] io_usingMulAdd,
o... |
Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPref... | module hi_us_0(
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_dat... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
... | module FPToFP(
input clock,
input reset,
input io_in_valid,
input io_in_bits_ren2,
input [1:0] io_in_bits_typeTagOut,
input io_in_bits_wflags,
input [2:0] io_in_bits_rm,
input [64:0] io_in_bits_in1,
input [64:0] io_in_bits_in2,
output io_out_valid... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
... | module cc_banks_5(
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlock... | module table_512x1(
input [8:0] R0_addr,
input R0_en,
input R0_clk,
output R0_data,
input [8:0] W0_addr,
input W0_en,
input W0_clk,
input W0_data
);
reg Memory[0:511];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
... |
Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
... | module dataArrayWay_2(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
dataArrayWay_0_ext dataArrayWay_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW... |
Generate the Verilog code corresponding to this Chisel code /*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and And... | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53(
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:... |
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