content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, ... |
-------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
--------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
entity xtc_top_sdram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type;
nmi: ... |
library ieee;
use ieee.std_logic_1164.all;
entity clock_counter is
generic
(
f: integer := 50000000
);
port
(
clock_i: in std_logic;
clock_o: out std_logic
);
end entity;
architecture behavior of clock_counter is
begin
process (clock_i)
variable counter: integer := 0;
... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Codeword_Generator_1
-- Module Name: Controller_Codeword_Generator_1... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:44:28 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_9_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll_vga.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ========================================... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity sys_wb8_tb is
end sys_wb8_tb;
architecture Behavior of sys_wb8_tb is
component sys_toplevel_wb8
Port(
I_clk: in std_logic;
I_reset: in std_logic := '0';
I_serial_rx: in std_logic;
I_inte... |
--------------------------------------------------------------------------------
-- sha1_pad.vhd
-- Pads SHA1 input to nearest 16 word msg and appends length nibble
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: miglib_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: miglib_arty
-- Description: MIG interface comp... |
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- can... |
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- can... |
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- can... |
component pr_region_alternate_mm_bridge_0 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: gen_crc8_tbl_check.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter50 is
port(C, CLR, hold : in std_logic;
Q : out std_logic_vector(5 downto 0));
end counter50;
architecture archi of counter50 is
signal tmp: std_logic_vector(5 downto 0);
begin
process (C, CLR, ... |
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity control_tb is
end;
architecture bench of control_tb is
component control
Port ( Switches : in STD_LOGIC_VECTOR (0 to 7);
clk_12hz : in std_logic;
clk_1hz5 : in std_logic;
Leds : out STD_LOGIC_VECTOR (0 t... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vecto... |
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vecto... |
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vecto... |
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vecto... |
entity issue13 is
end entity;
architecture test of issue13 is
constant c0: bit_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of bit_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
0 => "10101010");
begin
process is
variable cmp : bit_vecto... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_endpoint is
end entity psl_test_endpoint;
architecture test of psl_test_endpoint is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_endpoint is
end entity psl_test_endpoint;
architecture test of psl_test_endpoint is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s... |
entity jcore4 is
end entity;
architecture test of jcore4 is
type rt is record
x : bit_vector(1 to 3);
end record;
type at is array (integer range <>) of rt;
signal a : at(1 to 3);
begin
end architecture;
|
entity jcore4 is
end entity;
architecture test of jcore4 is
type rt is record
x : bit_vector(1 to 3);
end record;
type at is array (integer range <>) of rt;
signal a : at(1 to 3);
begin
end architecture;
|
entity jcore4 is
end entity;
architecture test of jcore4 is
type rt is record
x : bit_vector(1 to 3);
end record;
type at is array (integer range <>) of rt;
signal a : at(1 to 3);
begin
end architecture;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
cont... |
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
cont... |
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
cont... |
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
cont... |
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in ... |
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in ... |
library verilog;
use verilog.vl_types.all;
entity dp512x32_col is
port(
CLKA : in vl_logic;
CLKB : in vl_logic;
CSBA : in vl_logic;
CSBB : in vl_logic;
RWBA : in vl_logic;
RWBB : in ... |
----------------------------------------------------------------------------------
-- Simple FIR filter using systolic form.
-- Initial version: Colm Ryan (cryan@bbn.com)
-- Create Date: 06/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library ieee... |
----------------------------------------------------------------------------------
-- Module Name: tb_test_source_3840_2160 - Behavioral
--
-- Description: A testbench for tb_test_source
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20.08.2015 21:08:13
-- Design Name:
-- Module Name: video_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 10:55:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: i... |
-- Btrace 448
-- Btrace Package
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
package btrace_pack is
type color_t is (black, red, green, yellow, blue, magenta, cyan, white);
type comp_op is (gt, gte, eq);
type point i... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the o... |
----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Polynom Division with Inversion+Multiplication
-- Computes the g/h mod f IN GF(2**m)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- g_i ... |
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5_dec IS
PORT (
clr... |
library IEEE;
use IEEE.std_logic_1164.ALL;
library WORK;
use WORK.cpu_pack.t_cpu_mem_word;
use WORK.cpu_pack.t_cpu_mask;
use WORK.cpu_pack.t_cpu_word;
package memory_pack is
-- synthesis translate_off
constant CPU_MEM_SIZE : natural := 256;
type t_cpu_memory is array(CP... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:26:06 03/11/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/FETCH/FETCH_TOPLEVEL_tbd.vhd
-- Project Name: FETCH
-- Target Device:
-- Tool ... |
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