content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
entity Control is
port(
Opcode: in std_logic_vector(5 downto 0);
RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump: out std_logic;
ALUOp: out std_logic_vector(1 downto 0)
);
end Control;
architecture Structural of Control is
begin
process(... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
package pack is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
end package;
use work.pack.all;
entity sub is
port ( x : buffer rbit );
end entity;
architecture test of sub is
begin
x <= '1';
x <= '0'; -- Error
end architecture;
entity buf... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- #################################################################################################
-- # << NEO430 - High-Precision Timer >> #
-- # ********************************************************************************************* #
-- # This timer u... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_nov;
architecture behaviour of s298_nov is
constant s00000000000000: std_logic_vector(7 do... |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: GAME_CTRL
-- AUTHORS: Tomáš Bannert <xbanne00@stud.feec.vutbr.cz>
-- Jakub Cabal <jakubcabal@gma... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
use std.textio.all;
package init_funcs is
function read_file(data_file_name: string) return vga_memory_ptr;
function chr(sl: std_logic) return character;
function str(slv: std_logic_vector) return string;
end package ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply_block1.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------... |
-- #################################################################################################
-- # << NEO430 - General Purpose Parallel IO Unit >> #
-- # ********************************************************************************************* #
-- # 16-bit paral... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias1: electrical;
term... |
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_filter_tb is
end;
architecture sym of dvb_ts_filter_tb is
signal ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic0x is
port(
clka:in std_logic;
codop0x: in std_logic_vector ( 3 downto 0 );
PortA0x: in std_logic_vector ( 7 downto 0 );
PortB0x: in std_logic_vector ( 7 downto 0 );
out0x: out std_l... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE porrinha_user_package IS
COMPONENT porrinha_user
PORT (Choice, Guess, Fim, FimFim, winner, clk: IN STD_LOGIC;
guess_opt: IN STD_LOGIC_VECTOR(2 downto 0);
P1, P2: IN STD_LOGIC_VECTOR(1 downto 0);
pal: OUT STD_LOGIC_VECTOR(1 downto 0);
guess_user: OUT STD_... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- LEDDecoder.vhd
--
--
--**********************************************************************************
library IEEE;
use IEEE.STD... |
entity tb_if01 is
end tb_if01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_if01 is
signal c0, c1 : std_logic;
signal r : std_logic;
begin
dut: entity work.if01
port map (c0, c1, r);
process
begin
c0 <= '1';
c1 <= '0';
wait for 1 ns;
assert r = '0' severity failur... |
--Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associate... |
library ieee;
use ieee.std_logic_1164.all;
package rec03_pkg is
type myenum is (s0, s1, s2, s3);
type myrec is record
a : myenum;
b : std_logic;
end record;
end rec03_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
package rec03_pkg is
type myenum is (s0, s1, s2, s3);
type myrec is record
a : myenum;
b : std_logic;
end record;
end rec03_pkg;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ps2KeyboardInterface IS
PORT (
clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
END ps2KeyboardInterfa... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ps2KeyboardInterface IS
PORT (
clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
END ps2KeyboardInterfa... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ps2KeyboardInterface IS
PORT (
clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
END ps2KeyboardInterfa... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ps2KeyboardInterface IS
PORT (
clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
END ps2KeyboardInterfa... |
-- -------------------------------------------------------------
--
-- Entity Declaration for adc
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: adc... |
-- NEED RESULT: ARCH00178.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00178: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00178: Old transaction... |
architecture RTL of FIFO is
signal sig1 : std_logic;
signal sig2 : std_logic;
-- Violations below
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity test is
generic(
ROW_BITS : integer := 8;
WIDTH : integer := 16
);
port(
clk : in std_logic;
rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
rd_dat... |
library verilog;
use verilog.vl_types.all;
entity mem_stage is
port(
clk : in vl_logic;
reset : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
busy : out vl_logic;
fwd_data : out ... |
----------------------------------------------------------------------------------------------------
-- inverter_maia_2.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
--------------------------------------------... |
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:41:32 2017
-- Host : GILAMONSTER running 64-bit major rel... |
--------------------------------------------------------------------------------
-- Numonyx 128 Mbit EMBEDDED FLASH MEMORY J3 Version D --
--------------------------------------------------------------------------------
-- See <flash.h> and <flash.c> for information on usage and bus interface.... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:44:25 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TbPC.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Descriptio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:44:25 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TbPC.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Descriptio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:44:25 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TbPC.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Descriptio... |
-- NEED RESULT: ARCH&(TEST_NUM): Relational operators are correctly predefined for generically sized types passed
-- NEED RESULT: ARCH&(TEST_NUM): Relational operators are correctly predefined for types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:19:19 05/27/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_bits_aggregator.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- D... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
-------------------------------------------------------------------------------
-- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $
-------------------------------------------------------------------------------
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------... |
entity test is end;
|
-- Author : K. Abdelouahab
-- Company : DREAM - Institut Pascal - Unviersite Clermont Auvergne
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity sconv is
generic (
LINE_WIDTH_MAX : integer := 320;
IN_SIZE : integer := 8;
OUT_SIZE : integer ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ADDRESS_DECODER is
port(
-- address input
PA: in unsigned(15 downto 0);
-- chip selects output
-- memory
CSROMH: out std_logic;
CSROML: out std_logic;
CSRAM : out std_logic;
-- io chips
CSUART: o... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:01:14 2017
-- Host : DarkCube running 64-bit major re... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY UnitWithParams_0 IS
GENERIC(
DATA_WIDTH : INTEGER := 64
);
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_vld : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(... |
-------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-- Date : 12-May-14
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
--------------------------------------------... |
entity func8 is
end entity;
architecture test of func8 is
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
... |
entity func8 is
end entity;
architecture test of func8 is
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:20:02 06/05/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-- UART Receiver
-- 20/07/2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
port(
clk, reset: in std_logic; -- Clock and reset
rx: in std_logic; -- UART RX (Receive) pin
baud16_tick: in std_logic; -- 16x oversampled baud tick
data_out: out ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
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