content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity bug5 is
port(
clk : in std_logic;
addr : std_logic_vector
);
end bug5;
architecture behavioral of bug5 is
-- This complains with stack trace:
-- Fatal: signal cannot have unconstrained array type
signal last_addr_s : std_logic_vector(addr'range);
... |
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sumador is
Port ( Operador1 : in STD_LOGIC_VECTOR (31 downto 0);
Resultado : out STD_LOGIC_VECTOR (31 downto 0));
end Sumador;
architecture Behavioral of sumador is
begin
process(Operador1)
begin
Resultado <= Opera... |
-- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity test3 is port (
a : in std_logic;
b : in std_logic;
c : out std_logic);
end entity;
architecture Behavioral of test3 is
begin
c <= a and b;
end Behavioral... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual pr... |
-------------------------------------------------------------------------------
--! @project Iterate hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be... |
------------------------------------------------------------------------------
-- axi_sha256_sl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE W... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
-------------------------------------------------------------------------------
-- Title : FIR - Filter
-- Author : Franz Steinbacher, Michael Wurm
-------------------------------------------------------------------------------
-- Description : Finite Impule Response Filter with Avalon MM interface for
-- co... |
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (... |
-- file: dcm_6_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is no... |
entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n... |
entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n... |
entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n... |
entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n... |
entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n... |
-- Project generated by script.
-- Date: Dom,20/01/2013-11:22:53
-- Author: rogerio
-- Comments: Entity Description: and2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity and2 is
port (x, y: in std_logic; z: out std_logic);
end and2;
architecture l... |
entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA,... |
entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA,... |
entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA,... |
entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA,... |
entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA,... |
--
-- Copyright (C) 2013 Joel Pérez Izquierdo
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This p... |
entity hintbug is
end entity;
architecture test of hintbug is
function func(x : bit) return bit_vector is
begin
return x & '1';
end function;
begin
p1: process is
variable v : bit_vector(1 downto 0);
variable x : bit := '1';
begin
v := func(x); -- ... |
--------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 15:52:58 09/08/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/P09_Binary_to_Gray_Code_Converter/Binary_to_Gray_Code_Converter_TB.vhd
-- Pro... |
----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prog_rom is
Port( address : in STD_LOGIC_VECTOR(9 ... |
-------------------------------------------------------------------------------
--system_xadc_wiz_0_0_interrupt_control.vhd version v2.01.a
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyrig... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cache_tb IS
END cache_tb;
ARCHITECTURE behavior OF cache_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cache
Generic (WIDTH : natural := 13; -- Length of address
DWIDTH : natural := 13;... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.op... |
-- NEED RESULT: ENT00004: Entity name after 'end' not present passed
-- NEED RESULT: ENT00004_1: Entity name after 'end' present passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:25:58 04/28/2017
-- Design Name:
-- Module Name: rotary_machine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_utilities.all;
--! @brief Component f... |
----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Multiplication
-- Implementation with Double-And-Add algorithm
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- xp_i - X part ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity FakeVgaCam is
port (
RstN : in bit1;
Clk : in bit1;
--
VSync : out bit1;
HRef : out bit1;
D : out word(8-1 downto 0)
);
end entity;
architectu... |
architecture RTL of FIFO is
begin
process is
begin
end process;
process
begin
end process;
-- Violations below
process is begin
end process;
a <= b;
process begin
end process;
b <= z;
end architecture RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Title : ALU set lower than
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Set_Lower_Than.vhd
-- Autho... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lz4_pkg.all;
entity lz4_assembly is
port (
clk_i : in std_logic;
reset_i : in std_logic;
litLength_i : in std_logic_vector(9 downto 0);
offset_i : in std_logic_vector(9 downto ... |
architecture RTL of FIFO is
begin
Proc1 (Clock, A, Sig1, Sig2, Var1, Var2, Period);
READ (L => BufLine, VALUE => Q);
LABEL1: Proc1 (Clock);
LABEL2 : READ (L => BufLine,
VALUE => Q);
LABEL1: postponed Proc1 (Clock);
LABEL2 : postponed READ (L => BufLine,
VALUE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY testFSM IS
END testFSM;
Architecture Test of testFSM IS
COMPONENT fsm IS
PORT(
clk, reset, run : IN STD_LOGIC;
IR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
R0, R1, R2, R3, R4, R5, R6, R7, Aset, Gset,IRSet, done : OUT STD_LOGIC;
multSel : OUT STD_LOGIC_VECTOR(3 DO... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
constant CFG_OCLKCDIV : integer :... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
constant CFG_OCLKCDIV : integer :... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
constant CFG_OCLKCDIV : integer :... |
-- Clock generator
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
constant CFG_OCLKCDIV : integer :... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: X... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
----... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:20:39 2017
-- Host : Juice-Laptop running 64-bit major re... |
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity async_fifo is
port (
-- Global clear
clear : in std_logic ;
-- Write side
w_clock : in std_logic ;
w_enable : in std_logic ;
w_data : in std_logic_vector(7 downto ... |
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredoutput(template2)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity basic is
port(
clock:in std_logic;
address:in std_logic_vector(12 downto 0);
q:out std_logic_vector(7 downto 0)
);
end basic;
... |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 14:24:11 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_encryption is
end test_encryption;
architecture behavior of test_encryption is
signal data_in: std_logic_vector(0 to 63);
signal key: std_logic_vector(0 to 63);
signal data_out: std_logic_vector(0 to 63);
begin
uut:entity encrypt port map(... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity alu is
port (
clk : in std_logic;
reset : in std_logic;
opcode : in opcode_t;
opa : in word_t;
opb : in word_t;
result : out word_t
);
end alu;
|
-- very simple arbiter, slot 0 has highest priority, everything else can starve
-- due to lack of better knowledge: no generics are used.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xi... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:09)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectua... |
-- NEED RESULT: ENT00227.P00227: Associated scalar inout ports with static subtypes passed
-- NEED RESULT: ENT00227: Associated scalar inout ports with static subtypes passed
-- NEED RESULT: ENT00227.P00227: Associated scalar inout ports with static subtypes passed
---------------------------------------------------... |
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, component, resolved, when-el... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
prefix_generic_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
prefix_g... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
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