content stringlengths 1 1.04M ⌀ |
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Counter Generator Definitions
use work.counters_gen_pkg.all;
package dsp_cores_pkg is
-----------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod10_1 is
Port ( outp : out std_logic_vector(3 downto 0);
UP : in std_logic;
clk : in std_logic;
carry: out std_logic;
clr : in std_logic;
dir : out std_logic;
DOWN : in... |
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_basic.vhd,v 1.5 2004-10-09 22:18:35 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised fo... |
entity test is
end entity;
architecture a of test is
function fun(var : boolean) return boolean is
begin
return var;
end function;
begin
main : process
constant c : boolean := fun;
begin
wait;
end process;
end architecture;
|
entity test is
end entity;
architecture a of test is
function fun(var : boolean) return boolean is
begin
return var;
end function;
begin
main : process
constant c : boolean := fun;
begin
wait;
end process;
end architecture;
|
entity test is
end entity;
architecture a of test is
function fun(var : boolean) return boolean is
begin
return var;
end function;
begin
main : process
constant c : boolean := fun;
begin
wait;
end process;
end architecture;
|
entity protected6 is
end entity;
architecture test of protected6 is
type p is protected
impure function sum return integer;
end protected;
type p is protected body
type int_vector is array (natural range <>) of integer;
variable v : int_vector(1 to 2 ** 20) := (others => 1);
... |
package table is
type STD_ULOGIC is ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' );
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
end package;
package body table is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant resolution_table : stdlogic_table := (
... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
library IEEE;
use IEEE.std_logic_1164.all;
entity Transmissao is
port (
dados_ascii : in std_logic_vector(6 downto 0);
partida : in std_logic;
reset : in std_logic;
clock : in std_logic;
tick_tx : in std_logic;
dado_serial : out std_logic;
registrador : out... |
-- NEED RESULT: ENT00002: 'begin' may be present in entity declarations passed
-- NEED RESULT: ENT00002_1: 'begin' may be absent in entity declarations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All r... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implem... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
library ieee;
use ieee.std_logic_1164.all;
entity dff08a is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
en : std_logic;
rst : std_logic);
end dff08a;
architecture behav of dff08a is
signal p : std_logic_vector(7 downto 0);
begin
... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_369 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_369;
architecture augh of sub_369 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_369 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_369;
architecture augh of sub_369 is
signal carry_inA : std_l... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath_challenge IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
initx, inity, loady, loadx, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 d... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampler_pkg is
type t_sample_state is (idle, playing, finished, fetch1, fetch2);
type t_sample_mode is (mono8, mono16);
type t_voice_state is record
state : t_sample_state;
position : unsigne... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampler_pkg is
type t_sample_state is (idle, playing, finished, fetch1, fetch2);
type t_sample_mode is (mono8, mono16);
type t_voice_state is record
state : t_sample_state;
position : unsigne... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampler_pkg is
type t_sample_state is (idle, playing, finished, fetch1, fetch2);
type t_sample_mode is (mono8, mono16);
type t_voice_state is record
state : t_sample_state;
position : unsigne... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampler_pkg is
type t_sample_state is (idle, playing, finished, fetch1, fetch2);
type t_sample_mode is (mono8, mono16);
type t_voice_state is record
state : t_sample_state;
position : unsigne... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_xbrk is
port(
D_valid : in vl_logic;
E_valid : in vl_logic;
F_pc : in vl_logic_vector(26 downto 0);
clk : in vl_logic;
reset_n : in ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Colorgen is
Port ( iter : in STD_LOGIC_VECTOR (7 downto 0);
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 down... |
----------------------------------------------------------------------------------
--This is adapted from this code: https://eewiki.net/pages/viewpage.action?pageId=10125324
<<<<<<< HEAD
--modification: now sends 3 I2C packets with only a single ena signal pulse:
--write: [device id | register address | value]
--read: ... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Crossbar Core. Please refer to the documentation
--! in plasoc_crossbar.vhd for more information. Also, keep
--! in mind that this... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Entity: arith_addw_tb
--
-- Authors: Thomas B. Preusser <thomas... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Entity: arith_addw_tb
--
-- Authors: Thomas B. Preusser <thomas... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:29:11 2017
-- Host : GILAMONSTER running 64-bit major rel... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:09:48 04/20/2015
-- Design Name:
-- Module Name: datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY invert_arithmetic IS
GENERIC
(
length : integer
);
PORT
(
input : IN std_logic_vector(length-1 downto 0);
output : OUT std_logic_vector(length-1 downto 0)
);
END invert_arithmetic;
ARCHITECTURE behavior OF invert_arithmetic IS
COMPONENT ... |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- ftfifo.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Author: Stephen A. Rodgers
--
-- Copyright (c) 2005, Stephen A. Rodgers
--
-- Steve Rodgers <hwstar@rodgers.sdcoxmail.com>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on whi... |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Compare2 is
port( randomnum0 : in std_logic_vector(3 downto 0);
usernum0 : in std_logic_vector(3 downto 0);
randomnum1 : in std_logic_vector(3 downto 0);
u... |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Th... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NAND3 is port(
A,B,C: in std_logic;
Z: out std_logic
);
end NAND3;
architecture NAND3 of NAND3 is
begin
Z<=(not A) and (not B) and (not C);
end NAND3; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NAND3 is port(
A,B,C: in std_logic;
Z: out std_logic
);
end NAND3;
architecture NAND3 of NAND3 is
begin
Z<=(not A) and (not B) and (not C);
end NAND3; |
-- This is a 16 bit Linear Feedback Shift Register
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity LFSR16 is
port(
CLK : in std_logic;
RESET : in std_logic;
LD : in std_logic;
EN : in std_logic;
DIN : in std_logic_vector (0 to 15);
PRN : out std_logic_vector (... |
library verilog;
use verilog.vl_types.all;
entity View2 is
port(
Rb : in vl_logic;
Reset : in vl_logic;
CLK : in vl_logic;
Win : out vl_logic;
Lose : out vl_logic;
hex0 : out vl_... |
library verilog;
use verilog.vl_types.all;
entity View2 is
port(
Rb : in vl_logic;
Reset : in vl_logic;
CLK : in vl_logic;
Win : out vl_logic;
Lose : out vl_logic;
hex0 : out vl_... |
entity call3 is
end;
architecture behav of call3 is
procedure p2 (n : natural) is
begin
for i in 1 to n loop
report "hello 2";
wait for 1 ns;
end loop;
end p2;
procedure p (n : natural) is
begin
for i in 1 to n loop
p2 (i);
report "hello 1";
wait for 1 ns;
end l... |
entity call3 is
end;
architecture behav of call3 is
procedure p2 (n : natural) is
begin
for i in 1 to n loop
report "hello 2";
wait for 1 ns;
end loop;
end p2;
procedure p (n : natural) is
begin
for i in 1 to n loop
p2 (i);
report "hello 1";
wait for 1 ns;
end l... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_lib.all;
entity pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end pulser;
architecture Behaviora... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hex2bcd is
Generic ( precision : integer;
width : integer;
bits : integer;
ndigits : integer := 4 );
Port ( hex : in unsigned (precision-1 downto 0);
bcd : out STD_LOGIC_VECTOR (widt... |
entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
... |
entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
... |
entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
... |
entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
... |
entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.numeric_bit.all;
entity xor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xor_gate;
architecture rtl of xor_gate is
begin
c_o <= a_i xor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.numeric_bit.all;
entity xor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xor_gate;
architecture rtl of xor_gate is
begin
c_o <= a_i xor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.numeric_bit.all;
entity xor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xor_gate;
architecture rtl of xor_gate is
begin
c_o <= a_i xor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.numeric_bit.all;
entity xor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xor_gate;
architecture rtl of xor_gate is
begin
c_o <= a_i xor b_i;
end architecture rtl;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- #################################################################################################
-- # << NEO430 - Arbitrary Frequency Generator >> #
-- # ********************************************************************************************* #
-- # Number contr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
USE work.opc_pack.all;
ENTITY tb_operator_overloading IS END tb_operator_overloading;
ARCHITECTURE test OF tb_operator_overloading IS
COMPONENT operator_overloading IS
PORT(a, b: IN opc;
q: OUT opc);
END COMPONENT;
SIGNAL a, b, q: opc;
BEGIN
T1: operator_overloading PORT MAP(a, b, q);
a<='X',
'1... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
... |
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