content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils.all;
use work.color_util.all;
entity dualport_ram is
generic ( SIZE : natural := 8 );
port ( clk : in std_logic;
wr : in std_logic;
wraddr : in std_logic_vector (31 downto 0); -- MIPS-facing
... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_ENTITY_INST : entity FIFO(rtl);
-- Violations below
U_INST1 : INST1
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package OneHotGPR is
subtype operation is std_logic_vector(2 downto 0);
subtype command is std_logic_vector(17 downto 0);
subtype mem_addr is std_logic_vector(4 downto 0);
subtype operand is std_logic_vector(15 downto 0);
constant ADD: operation :... |
-----------------------------------------------
-- Transmit State Machine --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmit is
generic (
NDBits : natural := 8
);
port (
CLK : in std_logic;
RST : in ... |
--------------------------------------------------------------------------------
-- PS2 Keyboard Controller --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> ... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
-- Testbench for FIR Moving Average filter which averages L points
entity Testbench is
end Testbench;
architecture test of Testbench is
-- Constants to initialize generics of ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
library ieee;
use ieee.std_logic_1164.all;
entity ID_EX is
port (
RtD_in : in std_logic_vector(4 downto 0);
RdD_in : in std_logic_vector(4 downto 0);
SignImm_in : in std_logic_vector(31 downto 0);
RD1_in : in std_logic_vector(31 downto 0);
RD2_in : in std_logic_vector(31... |
library ieee;
use ieee.std_logic_1164.all;
entity ApbMasterBfmE is
generic (
G_ADDR_WIDTH : positive := 8; --* address bus width
G_DATA_WIDTH : positive := 8; --* data bus width
G_SLAVE_COUNT : positive := 1
);
port (
PRreset_n_i : in std_logic;
PClk_i : in std_logic
);
end e... |
library ieee;
use ieee.std_logic_1164.all;
entity ApbMasterBfmE is
generic (
G_ADDR_WIDTH : positive := 8; --* address bus width
G_DATA_WIDTH : positive := 8; --* data bus width
G_SLAVE_COUNT : positive := 1
);
port (
PRreset_n_i : in std_logic;
PClk_i : in std_logic
);
end e... |
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity e1 is
end e1;
architecture behav of e1 is
begin
assert false report "arch" severity note;
end behav;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free ha... |
-------------------------------------------------------------------------------
-- $Id: priority_reg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- priority_reg.vhd - entity/architecture pair
---------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: priority_reg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- priority_reg.vhd - entity/architecture pair
---------------------------------------------... |
------------------------------------------------------------
-- VHDL PCB_Project1
-- 2013 12 2 3 0 48
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
------------------------------------------------------------
------------------------------------------------------------
-- V... |
-- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, e... |
-- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, e... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
use ieee.std_logic_1164.ALL;
use ieee.std_logic_1164.ALL;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confid... |
-- NEED RESULT: ARCH00400.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00400.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00400: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH0040... |
-------------------------------------------------------------------------------
-- xps_sysmon_adc_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_sysmon_adc_v2_00_a;
use xps... |
package foo is
end package foo;
package body foo is
end package body foo;
|
--
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law o... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use work.pp_types.all;
use work.pp_constants.all;
entity pp_alu_cont... |
--
-- The interface to the VGA driver module. Extended to both read and write
-- to the framebuffer (to check the color values of a particular pixel).
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaDriverBuffer is
Port( CLK, we : in ... |
library verilog;
use verilog.vl_types.all;
entity dcfifo_mixed_widths is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_width_r : vl_notype;
lpm_widthu_r : vl_notype;
lpm_numwords : integer := 2;
delay_rdusedw : integer := 1;
... |
-- megafunction wizard: %ALTFP_INV%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_INV
-- ============================================================
-- File Name: kn_kalman_inv.vhd
-- Megafunction Name(s):
-- ALTFP_INV
--
-- Simulation Library Files(s):
-- lpm
-- ======================... |
-- megafunction wizard: %ALTFP_INV%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_INV
-- ============================================================
-- File Name: kn_kalman_inv.vhd
-- Megafunction Name(s):
-- ALTFP_INV
--
-- Simulation Library Files(s):
-- lpm
-- ======================... |
--! @file multiplier.vhd
--!
--! @authors Salvatore Barone <salvator.barone@gmail.com> <br>
--! Alfonso Di Martino <alfonsodimartino160989@gmail.com> <br>
--! Sossio Fiorillo <fsossio@gmail.com> <br>
--! Pietro Liguori <pie.liguori@gmail.com> <br>
--!
--! @date 03 07 2017
--!
--! @copyright
--! Copyright 2017... |
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity extender_32bit is
port (
INPUT_16 :in std_logic_vector( 15 downto 0);
OUTPUT_32 :out std_logic_vector(31 downto 0)
);
end extender_32bit;
architecture Behavioral of extender_32bit is
begin
OUTPUT_32 <= std_logic_vector(resize(sig... |
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity extender_32bit is
port (
INPUT_16 :in std_logic_vector( 15 downto 0);
OUTPUT_32 :out std_logic_vector(31 downto 0)
);
end extender_32bit;
architecture Behavioral of extender_32bit is
begin
OUTPUT_32 <= std_logic_vector(resize(sig... |
-- Program defined by '{psmname}.{psmext}'.
--
-- Generated by {assembler}: 2015-07-08T15:28:55.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UniSim;
use UniSim.vComponents.all;
entity main_Page0 is
port (
Clock : in std_logic;
Fetch : in std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity spi_tx_ram_controller_tb is
end;
architecture behavioural of spi_tx_ram_controller_tb is
signal ctrl : ctrl_t;
signal... |
-------------------------------------------------------------------------------
-- Title : Generic clock divider
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.... |
-- megafunction wizard: %Altera PLL v13.0%
-- GENERATION: XML
-- syspll1.vhd
-- Generated using ACDS version 13.0 156 at 2013.07.12.16:42:19
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity syspll1 is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '... |
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Rotacao de deslocamento 32 bits
entity rot_32 is port(
SET_ROLL, EN_TIME, CLOCK_M, RST: in std_logic;
SPEED: in std_logic_vector(2 downto 0);
REG_IN: in std_logic_vector(31 downto 0);
REG_OUT: out std_logic_vector(31 downto 0)
);
end rot_32;
... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- $Id: sys_tst_rlink_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_arty - syn
-- Descriptio... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity ent is
port (
insn_i : in std_ulogic_vector(31 downto 0);
ispr1_o : out std_ulogic_vector(5 downto 0);
ispr2_o : out std_ulogic_vector(5 downto 0)
);
end entity ent;
architecture behaviour of ent is
-- SPR... |
------------------------------------------------------------------------------
-- Clock generator for VGA/TMDS video output.
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP... |
------------------------------------------------------------------------------
-- Clock generator for VGA/TMDS video output.
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP... |
------------------------------------------------------------------------------
-- Clock generator for VGA/TMDS video output.
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 04/21/2018 01:23:15 PM
-- Module Name: system_top - Behavioral
-- Description: System-level wrapper for processor components
--
-- Additional Comments: "Death must be so beautiful. To lie in... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity ALUControl is
port(
ALUOp : in std_logic_vector(1 downto 0);
Funct : in std_logic_vector(5 downto 0);
Operation : out std_logic_vector(3 downto 0)
);
end ALUControl;
architecture Structural of ALUControl is
begin
process(ALUOp, Funct)
variable functTemp : s... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel
--
-- $Id: chip-e.vhd,v 1.3 2005-04-07 20:44:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in sou... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_interface is
end entity;
architecture tb of tb_ulpi_interface is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_interface is
end entity;
architecture tb of tb_ulpi_interface is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_interface is
end entity;
architecture tb of tb_ulpi_interface is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR ... |
-- $Id: pdp11_ubmap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ubmap - syn
-- Description: pdp11: 1... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity bram is
generic(memory_file : string := "code.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 16; -- address width... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity bram is
generic(memory_file : string := "code.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 16; -- address width... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:12 04/22/2016
-- Design Name:
-- Module Name: PC_OFFSET - Combinational
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:12 04/22/2016
-- Design Name:
-- Module Name: PC_OFFSET - Combinational
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:12 04/22/2016
-- Design Name:
-- Module Name: PC_OFFSET - Combinational
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
entity call8 is
end;
architecture behav of call8 is
type int_vector is array (natural range <>) of integer;
constant c : integer := 16#0123_4567#;
procedure check (s : int_vector) is
begin
wait for 2 ns;
assert s (2) = c;
end;
signal s : int_vector (0 to 3) := (123, 234, c, 345);
begin
s (2) ... |
entity call8 is
end;
architecture behav of call8 is
type int_vector is array (natural range <>) of integer;
constant c : integer := 16#0123_4567#;
procedure check (s : int_vector) is
begin
wait for 2 ns;
assert s (2) = c;
end;
signal s : int_vector (0 to 3) := (123, 234, c, 345);
begin
s (2) ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_rnd;
architecture behaviour of train4_rnd is
constant st0: std_logic_vector(1 downto 0... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:47:25 07/01/2015
-- Design Name:
-- Module Name: intlv_completo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
entity e is
end entity;
package p is
function f(x : boolean) return boolean;
end package;
use work.p.all;
architecture test of e is
function f1(x : boolean) return boolean is
begin
return x and f(x);
end function;
function f2(x, y : boolean) return boolean is
begin
return x a... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D12_C1 is
port(
load : in STD_LOGIC;
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC
);
end D12_C1;
architecture D12_C1 of D12_C1 is
signal t:std_logic;
signal temp:std_logic_vector(7 downto 0);
begin
process(clk,load... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity prog_counter is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity prog_counter is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logi... |
library verilog;
use verilog.vl_types.all;
entity arm_wb_stage is
port(
clk : in vl_logic;
MEMWB_data_read_from_mem: in vl_logic_vector(31 downto 0);
MEMWB_rd_data : in vl_logic_vector(31 downto 0);
MEMWB_rd_we : in vl_logic;
MEMWB_rd_data_se... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package arbiter_types is
constant ARB_DEVICES: integer := 8;
type arb_ACK_I_t is array(0 to ARB_DEVICES-1) of std_logic;
type arb_DAT_I_t is array(0 to ARB_DEVICES-1) of std_logic_vector(7 downto 0);
type arb_STB_O_t is array(0 to ARB_DEVICES-1) ... |
library ieee;
use ieee.std_logic_1164.all;
entity add3 is
port ( Num : in std_logic_vector(3 downto 0);
Sum : out std_logic_vector(3 downto 0)
);
end add3;
architecture sum_estru of add3 is
begin
Sum <= Num when Num = "0000" else
Num when Num = "0001" else
Num when Num = "0010" else
Num w... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Nox && Gabbe
--
-- Create Date: 14:49:40 09/16/2014
-- Design Name:
-- Module Name: big_little_endian - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: C... |
-------------------------------------------------------------------------------
-- Title : Quadrature Decoder
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
----------------... |
-------------------------------------------------------------------------------
-- Title : Quadrature Decoder
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
----------------... |
-- NEED RESULT: ARCH00667: Simple, selected, indexed, slice names in alias decl (variables) passed
-- NEED RESULT: ARCH00667: Simple, selected, indexed, slice names in alias decl (variables) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Inter... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : cpu_test.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-03-... |
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- ... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY... |
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