content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- File Name: NameStorePkg.vhd
-- Design Unit Name: NameStorePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for name.
--
-- Developed... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity fastfilterElement is
generic(
KERNEL_SIZE : integer;
PIXEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_log... |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Brett Bourgeois
--
-- Create Date: 11:49:41 04/24/2015
-- Design Name:
-- Module Name: decode_dp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... |
-- NEED RESULT: ARCH00179.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P3: Multi iner... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cnt02 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
low : out std_logic
);
end cnt02;
architecture behav of cnt02 is
signal counter : integer range 0 to 63;
begin
process(clk)
begin
if rising_edge(... |
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpc... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity heartbeat is
port ( clk: out std_logic);
end heartbeat;
architecture behaviour of heartbeat
is
constant clk_period : time := 10 ns;
begin
-- Clock process definition
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wa... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
entity foo is end;
architecture bar of foo is
constant xA : std.standard.INTEGER;
constant xB : INTEGER := -128;
constant xC : INTEGER := 127;
constant yA : std.standard.NATURAL;
constant yB : NATURAL := 0;
constant yC : NATURAL := 127;
constant zA : std.standard.POSITIVE;
constant zB : POSITIVE := 1;
const... |
component ghrd_10as066n2_pb_lwh2f is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_log... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
entity tb_vector8_test1 is
end tb_vector8_test1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_vector8_test1 is
signal r : std_logic;
begin
dut: entity work.vector8_test1
port map (r);
process
begin
wait for 1 ns;
assert r = '1' severity failure;
wait;
end process;
end... |
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redis... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in st... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--ÀûÓÃbufferʵÏֵķÖƵÆ÷£¬´úÂëÁ¿ÉÙÓÚÓÃCNT10¸ÄÔì
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY FrequencyDivider is
PORT(
data: in std_logic_vector(15 downto 0);--16λԤÖÃÊý£¬load·Ç¸ßµçƽÖÃÊý
en,clk:in std_logic;--ʹÄÜ£¬Ê±ÖÓ
q: buffer std_logic_vector(15 downto 0);--16λ¼ÆÊý
co... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipeline"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
----------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipeline"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
----------------------------------------------------------------------------... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xil... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
-------------------------------------------------------------------------------
--
-- T8x48 ROM
-- Wrapper for ROM model from the LPM library.
--
-- $Id: t48_rom-lpm-a.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution ... |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
use work.PhoenixPackage.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
entity topNoC is
end;
architecture topNoC of topNoC is
signal clock : regNrot:=(others=>'0');
signal reset : s... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:23:34 03/25/2015
-- Design Name:
-- Module Name: RISC_MACHINE - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00366.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: A... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2015
-- Entity: usb_cmd_pkg
-- Date:2015-01-18
-- Author: Gideon
-- Description: This package defines the commands that can be sent to the
-- sequencer.
---------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- avalon64_to_avalon8_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_11... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: seg7dec
-- // Date: 12/9/2004
-- // Description: Display Component
-- // Class: CSE 378
-- ================================================... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:30 03/24/2014
-- Design Name:
-- Module Name: nmea_frame_extractor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:30 03/24/2014
-- Design Name:
-- Module Name: nmea_frame_extractor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/27/2016
-- Design Name: i2s_pkg.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
... |
library ieee;
use ieee.std_logic_1164.all;
entity dff05 is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic);
end dff05;
architecture behav of dff05 is
begin
process (clk) is
begin
if rising_edge (clk) then
if d (7) = '1' then
q (0) ... |
architecture RTL of FIFO is
begin
process is
begin
end process;
process (a) is
begin
end process;
-- Violations below
process is
begin
end process;
process (a)is
begin
end process;
process (a) is
begin
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_563;
architecture augh of sub_563 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_563;
architecture augh of sub_563 is
signal carry_inA : std_l... |
-------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios CN FPGA directIO part
--
--! @details This is the toplevel of the Nios CN FPGA directIO design for the
--! INK DE2-115 Evaluation Board.
--
----------------------------------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
--======================================================================
-- timer.vhd :: A simple 16-bit Timer
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
us... |
--======================================================================
-- timer.vhd :: A simple 16-bit Timer
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
us... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 13:21:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls
--
-- !!! Do not edit this... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY EmptyUnitWithSpi IS
PORT(
spi_clk : IN STD_LOGIC;
spi_cs : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
spi_miso : OUT STD_LOGIC;
spi_mosi : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF EmptyUnitWithSpi IS
BEGIN
... |
-- $Id: fifo_2c_dram2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram2 - syn
-- Description: FIFO, tw... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY thermometersLogicTB IS
END thermometersLogicTB;
ARCHITECTURE behavior OF thermometersLogicTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT thermometersLogic
PORT(
rsTxBusy : IN std_logic;
... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Oct 10 12:25:03 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
library verilog;
use verilog.vl_types.all;
entity datapath_vlg_vec_tst is
end datapath_vlg_vec_tst;
|
---------------------------------------------------------------------------------
--Generator------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
----------------------------------------------------------------------
-- brdRstClk (for some Fusion (Embeded/Start/SCS) Dev Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known c... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
-- Keep Comment
G_GEN_1 => 3,-- Comment
-- Keep Comment
G_GEN_2 => 4, -- Comment
-- Keep Comment
G_GEN_3 => 5-- Comment
-- Keep Comment
)
port map (
-- Keep Comment
PORT_1 => w_por... |
-----------------------------------------------------------------------
-- MULTIPLICAÇÃO POR SOMAS SUCESSIVAS
--
-- Mcando, Mcador - Multiplicando e Multiplicador, de N bits
-- start, endop - Início e fim de operação de multiplicação
-- produto - Resultado, com 2N bits
-------------------------------------... |
-----------------------------------------------------------------------
-- MULTIPLICAÇÃO POR SOMAS SUCESSIVAS
--
-- Mcando, Mcador - Multiplicando e Multiplicador, de N bits
-- start, endop - Início e fim de operação de multiplicação
-- produto - Resultado, com 2N bits
-------------------------------------... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_s... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:03 2017
-- Host : Juice-Laptop running 64-bit majo... |
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-08T14:22:41+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.enforcement_types_PaceEnforcer.all;
entity PaceEnforcer_enforcer_AEI is
port
(
clk : in std_logic;
reset ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
---------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
---------------------------------------------------------... |
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