content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00104.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00104: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00104: Old transactions ... |
--CPU
-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- basic IEEE library
use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type
entity CPU is
port ( clk : in std_logic; -- Systen clock
collision : in std_logic;
... |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT ... |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT ... |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT ... |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT ... |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT ... |
-- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT ... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package codec_8b10b_pack is
subtype b8_t is std_ulogic_vector(7 downto 0);
subtype b10_t is std_ulogic_vector(9 downto 0);
type rd_t is (undef, plus1, minus1);
procedure data_8b10b(
b8_i : in b8_t;
rd_i : in rd_t;
b10_o : out b10_t;
rd... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library verilog;
use verilog.vl_types.all;
entity rs is
port(
clock : in vl_logic;
rs_free : out vl_logic;
rs_lok : out vl_logic;
rs_sok : out vl_logic;
rg_ok : out vl_logic;
rg_num : in vl_log... |
library verilog;
use verilog.vl_types.all;
entity rs is
port(
clock : in vl_logic;
rs_free : out vl_logic;
rs_lok : out vl_logic;
rs_sok : out vl_logic;
rg_ok : out vl_logic;
rg_num : in vl_log... |
library IEEE;
use ieee.std_logic_1164.all;
entity cnt is
port(
rst: in std_logic;
T: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end entity;
architecture cnt of cnt is
component tc_trig is
port(T: in std_logic;
C: in std_logic;
R: in std_logic;
Q, notQ: out std_logic);
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca_top
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
-- entity that contains an FSM to decode midi type 1 files such that the FPGA can
-- play them
--
-- Determines if a file that has been sent to midi_ram is actually a midi file.
--
-- Reads the following data:
-- * number of tracks
-- * address and length of each track
library ieee;
use ieee.std_logic_1164.all;
use i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- not both this and below -- USE ieee.std_logic_arith.all;
--use IEEE.numeric_bit.all; -- for integer to bit_vector conversion
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
-- VGA std format 640 by 480 pixels in a frame
-- register them, count line by lin... |
module elevator |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_her... |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_her... |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_her... |
-- delay.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
--
-- Component that delays an input signal by
-- a given amount of cycles.
library ieee;
use ieee.std_logic_1164.all;
entity delay is
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- re... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity condition_code_register is
port(
clk: in std_logic;
enable: in std_logic;
c_D: in std_logic;
z_D: in std_logic;
n_D: in std_logic;
lt_D: in std_logic;
c_Q: out std_logic;
z_Q: out std_logic;
n_Q: out std_logic... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vrefofkplusone is
port (
clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Yofk : in ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PS_to_PL_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 3... |
----------------------------------------
-- Main Processor - Testbench : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 9/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture behave of testb... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_logic is
generic (
g_version : unsigned(7 downto 0) := X"FF";
g_simulation : boolean := true;
g_clock_freq : natural := 50_000_000;
g_baud_rate ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada ... |
library ieee;
use ieee.std_logic_1164.all;
entity SRAM is
port (
clk : in std_logic;
load : in boolean;
addr : in std_logic_vector(19 downto 0);
data : inout std_logic_vector(31 downto 0);
clkPin1 : out std_logic;
clkPin2 : out std_logic;
xStorePin : out std... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library ieee;
use ieee.std_logic_1164.all;
entity ram2 is
generic (
WIDTH : integer := 32;
SIZE : integer := 64;
ADDRWIDTH : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logi... |
ARCHITECTURE behavior OF timingDemo IS
BEGIN
p1 : PROCESS() --add sesitivity list for the signal connecting to port E
--remeber to creat a variable here
BEGIN
END PROCESS;
p2: PROCESS() --add sesitivity list for the signals connecting to port O and port P
BEGIN
END PROCESS;
--transmit th... |
library ieee;
use ieee.std_logic_1164.all;
entity ddr4_dimm_wrapper is
port (
sys_reset : in std_logic;
c0_ddr4_act_n : in std_logic;
c0_ddr4_adr : in std_logic_vector(16 downto 0);
c0_ddr4_ba : in std_logic_vector(1 downto 0);
c0_ddr4_bg : in std_logic_vector(0 downto 0);
c0_ddr4_cke : in ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- LV network: False
-- Data width: 32
-- Parity: False
-- Fault injectors: True
-----------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- LV network: False
-- Data width: 32
-- Parity: False
-- Fault injectors: True
-----------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- LV network: False
-- Data width: 32
-- Parity: False
-- Fault injectors: True
-----------... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
library verilog;
use verilog.vl_types.all;
entity pipeline_vlg_tst is
end pipeline_vlg_tst;
|
library verilog;
use verilog.vl_types.all;
entity pipeline_vlg_tst is
end pipeline_vlg_tst;
|
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentat... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : fan.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-04-28
--... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic ( widthB : natural := 1;
widthA : natural := 1);
po... |
library ieee;
use ieee.std_logic_1164.all;
entity disptree is
port (
clk : in std_logic;
A : in std_logic_vector(5 downto 1);
B : out std_logic_vector(5 downto 1)
);
end disptree;
architecture rtl of disptree is
begin
gen_for : for i in 1 to 4 generate
test1: process (... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shooting_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end shooting_sound;
architecture content... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shooting_sound is
generic(
ADDR_WIDTH: integer := 5
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(8 downto 0)
);
end shooting_sound;
architecture content... |
-----------------------------------------------------------------------------
-- Module for transmitting data from the 50MHz byte-format to the 25MHz
-- PHY nibble-format. Adds preamble, SFD and CRC.
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- package for lfsr next state determination
-- the determination use the maximum feedback taps
-- the sequence will cycle through all values from 0 to 2^n-1
-- the lfsr should start with state (others => '0')
-- and the state (others => '1... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Codeslot
--
-- gemaakt door
--
-- __ ___ _
-- / |/ /___ ___ _______(_)_______
-- / /|_/ / __ `/ / / / ___/ / ___/ _ \
-- / / / / /_/ / /_/ / / / / /__/ __/
-- /_/ /_/\__,_/\__,_/_/ /_/\___/\___/
-- ____ ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:27 2017
-- Host : DarkCube running 64-bit major releas... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Global package
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floa... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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