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-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
--16bit data is big endian if true
papBigEnd_g : boolean := false;
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr if pap_cs is set
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if pap_cs = '1' then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
ap_address <= pap_addr_s(ap_address'left+2 downto 2);
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s;
ap_chipselect <= pap_cs_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = false else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = false else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = true else
"0011" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "00" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = true else
"1100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s when papBigEnd_g = false else
pap_wrdata_s(7 downto 0) & pap_wrdata_s(15 downto 8);
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss when papBigEnd_g = false else
pap_rddata_ss(7 downto 0) & pap_rddata_ss(15 downto 8);
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp and pap_cs_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
--16bit data is big endian if true
papBigEnd_g : boolean := false;
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr if pap_cs is set
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if pap_cs = '1' then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
ap_address <= pap_addr_s(ap_address'left+2 downto 2);
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s;
ap_chipselect <= pap_cs_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = false else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = false else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = true else
"0011" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "00" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = true else
"1100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s when papBigEnd_g = false else
pap_wrdata_s(7 downto 0) & pap_wrdata_s(15 downto 8);
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss when papBigEnd_g = false else
pap_rddata_ss(7 downto 0) & pap_rddata_ss(15 downto 8);
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp and pap_cs_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
--16bit data is big endian if true
papBigEnd_g : boolean := false;
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr if pap_cs is set
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if pap_cs = '1' then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
ap_address <= pap_addr_s(ap_address'left+2 downto 2);
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s;
ap_chipselect <= pap_cs_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 0) = "11" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 0) = "10" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 0) = "01" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 0) = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= --little endian
"0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = false else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = false else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" and papBigEnd_g = false else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = false else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = false else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" and papBigEnd_g = false else
--big endian
"0001" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" and papBigEnd_g = true else
"0010" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" and papBigEnd_g = true else
"0011" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "00" and papBigEnd_g = true else
"0100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" and papBigEnd_g = true else
"1000" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" and papBigEnd_g = true else
"1100" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "00" and papBigEnd_g = true else
(others => '0');
ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s when papBigEnd_g = false else
pap_wrdata_s(7 downto 0) & pap_wrdata_s(15 downto 8);
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss when papBigEnd_g = false else
pap_rddata_ss(7 downto 0) & pap_rddata_ss(15 downto 8);
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp and pap_cs_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
-------------------------------------------------------------------------------
--
-- T410/411 controller toplevel without tri-states.
--
-- $Id: t410_notri.vhd,v 1.4 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t410_notri is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t410_notri;
use work.t400_core_comp_pack.t400_core;
use work.t400_tech_comp_pack.t400_por;
use work.t400_tech_comp_pack.generic_ram_ena;
architecture struct of t410_notri is
component t410_rom
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(8 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end component;
signal por_n_s : std_logic;
signal pm_addr_s : std_logic_vector(9 downto 0);
signal pm_data_s : std_logic_vector(7 downto 0);
signal dm_addr_s : std_logic_vector(5 downto 0);
signal dm_we_s : std_logic;
signal dm_data_to_core_s,
dm_data_from_core_s : std_logic_vector(3 downto 0);
signal gnd4_s : std_logic_vector(3 downto 0);
begin
gnd4_s <= (others => '0');
-----------------------------------------------------------------------------
-- T400 core
-----------------------------------------------------------------------------
core_b : t400_core
generic map (
opt_type_g => t400_opt_type_410_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => t400_opt_no_microbus_c,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
por_n_i => por_n_s,
reset_n_i => reset_n_i,
cko_i => cko_i,
pm_addr_o => pm_addr_s,
pm_data_i => pm_data_s,
dm_addr_o => dm_addr_s,
dm_we_o => dm_we_s,
dm_data_o => dm_data_from_core_s,
dm_data_i => dm_data_to_core_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o,
io_d_o => io_d_o,
io_d_en_o => io_d_en_o,
io_g_i => io_g_i,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o,
io_in_i => gnd4_s,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Program memory
-----------------------------------------------------------------------------
pmem_b : t410_rom
port map (
ck_i => ck_i,
addr_i => pm_addr_s(8 downto 0),
data_o => pm_data_s
);
-----------------------------------------------------------------------------
-- Data memory
-----------------------------------------------------------------------------
dmem_b : generic_ram_ena
generic map (
addr_width_g => 5,
data_width_g => 4
)
port map (
clk_i => ck_i,
a_i => dm_addr_s(4 downto 0),
we_i => dm_we_s,
ena_i => ck_en_i,
d_i => dm_data_from_core_s,
d_o => dm_data_to_core_s
);
-----------------------------------------------------------------------------
-- Power-on reset circuit
-----------------------------------------------------------------------------
por_b : t400_por
generic map (
delay_g => 4,
cnt_width_g => 2
)
port map (
clk_i => ck_i,
por_n_o => por_n_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2006/06/05 20:03:11 arniml
-- include generic_ram_ena
--
-- Revision 1.2 2006/05/08 02:36:38 arniml
-- hand-down clock divider option
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2 is
generic (WIDTH: integer := 8);
port ( I_A, I_B : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
I_Sel : in STD_LOGIC;
O_Y : out STD_LOGIC_VECTOR (WIDTH-1 downto 0));
end mux2;
architecture Behavioral of mux2 is
begin
O_Y <= I_B when I_Sel = '1' else I_A;
end Behavioral;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:45:28 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_auto_pc_0/gcd_zynq_snick_auto_pc_0_stub.vhdl
-- Design : gcd_zynq_snick_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gcd_zynq_snick_auto_pc_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end gcd_zynq_snick_auto_pc_0;
architecture stub of gcd_zynq_snick_auto_pc_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2";
begin
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.jtag.all;
use work.config.all;
entity core is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN;
bscanen : integer := CFG_BOUNDSCAN_EN;
oepol : integer := 0
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
dataen : out std_logic_vector(31 downto 0);
cbin : in std_logic_vector(7 downto 0);
cbout : out std_logic_vector(7 downto 0);
cben : out std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : out std_ulogic;
gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_sclout : out std_ulogic;
i2c_sclen : out std_ulogic;
i2c_sclin : in std_ulogic;
i2c_sdaout : out std_ulogic;
i2c_sdaen : out std_ulogic;
i2c_sdain : in std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdioin : in std_logic;
emdioout : out std_logic;
emdioen : out std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tdoen : out std_ulogic;
chain_tck : out std_ulogic;
chain_tckn : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic
);
end;
architecture rtl of core is
signal vcc : std_logic_vector(15 downto 0);
signal gnd : std_ulogic;
signal clk1x : std_ulogic;
signal clk2x : std_ulogic;
signal clk4x : std_ulogic;
signal clk8x : std_ulogic;
signal lclk : std_ulogic;
-- signal lclkapb : std_ulogic;
signal lspw_clk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal letx_clk : std_ulogic;
signal llock : std_ulogic;
signal scanen : std_ulogic;
signal testrst : std_ulogic;
signal testoen : std_ulogic;
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
begin
-- Scan test mux logic not connected boundary scan chain
scanen <= dsubre when (testen = '1' and scantest = 1) else '0';
testrst <= dsuen when (testen = '1' and scantest = 1) else '1';
testoen <= dsurx when (testen = '1' and scantest = 1) else '0';
-- PLL for system clock
clkgen0: clkgen
generic map(
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
noclkfb => CFG_CLK_NOFB,
freq => 50000)
port map(
clkin => clk,
pciclkin => clk,
clk => clk1x,
clkn => open,
clk2x => clk2x,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo,
clk4x => clk4x,
clk1xu => open,
clk2xu => open,
clkb => open,
clkc => open,
clk8x => open);
cgi.pllrst <= resetn;
cgi.pllref <= lclk; -- Note: Used as fbclk if CFG_CLK_NOFB = 0
cgi.clksel <= (others => '0');
-- PLL is bypassed, and disabled, when either testen(0) = 1 or clksel =
-- "00". Bit 0 of pllctrl input is used as the disable signal
cgi.pllctrl(0) <= '1' when (clksel = "00" or (testen = '1' and scantest = 1)) else '0';
cgi.pllctrl(1) <= '0';
-- Simulate lock signal when PLL not used
llock <= '1' when (clksel = "00" or (testen = '1' and scantest = 1)) else cgo.clklock;
lock <= llock;
-- Clock muxing inside boundary scan chain for CORE clock
core_clock_mux : entity work.core_clock_mux
generic map(
tech => fabtech,
scantest => scantest)
port map(
clksel => clksel,
testen => testen,
clkin => clk,
clk1x => clk1x,
clk2x => clk2x,
clk4x => clk4x,
clkout => lclk);
-- Clock muxing inside boundary scan chain for APB CORE clock
--apb_core_clock_mux : entity work.core_clock_mux
-- generic map(
-- tech => fabtech,
-- scantest => scantest)
-- port map(
-- clksel => clksel,
-- testen => testen,
-- clkin => clk,
-- clk1x => clk1x,
-- clk2x => clk1x,
-- clk4x => clk1x,
-- clkout => lclkapb);
-- Clock muxing inside boundary scan chain for SPW clock
spw_core_clock_mux : entity work.core_clock_mux
generic map(
tech => fabtech,
scantest => scantest)
port map(
clksel => spw_clksel,
testen => testen,
clkin => clk,
clk1x => spw_clk,
clk2x => spw_clk,
clk4x => spw_clk,
clkout => lspw_clk);
-- Ethernet Clock Mux for scan test
gtxclkmux : clkmux generic map (tech => fabtech) port map (gtx_clk,clk,testen,lgtx_clk);
rxclkclkmux : clkmux generic map (tech => fabtech) port map (erx_clk,clk,testen,lerx_clk);
txclkclkmux : clkmux generic map (tech => fabtech) port map (etx_clk,clk,testen,letx_clk);
-- Clock outputs
sdclk <= lclk;
-- Control the GPIO direction during test
-- Scantest mode. Lower half of the gpio are scan chain inputs in testmode
-- and upper half of the gpio are outputs, i.e. maximum number of scan
-- chains is the half number of GPIOs
-- Note: testen and testoen should have priority over resetn because the registers
-- in the reset generator are part of the scan chain, and the direction
-- of gpio(23:12) would then depend on the value of a register in the
-- scan chain.
gpioen(CFG_GRGPIO_WIDTH-1 downto (CFG_GRGPIO_WIDTH/2)) <= lgpioen(CFG_GRGPIO_WIDTH-1 downto (CFG_GRGPIO_WIDTH/2))
when (testoen = '0') else (others => '0') when oepol = 1 else (others => '1');
gpioen((CFG_GRGPIO_WIDTH/2)-1 downto 0) <= lgpioen((CFG_GRGPIO_WIDTH/2)-1 downto 0)
when (testoen = '0') else (others => '1') when oepol = 1 else (others => '0');
leon3core0 : entity work.leon3core
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart,
pclow, scantest*(1 - is_fpga(fabtech)))
port map (
resetn, clksel, lclk, lclk, --lclkapb,
llock, errorn,
address, datain, dataout, dataen, cbin, cbout, cben,
sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn,
wdogn, gpioin, gpioout, lgpioen,
i2c_sclout, i2c_sclen, i2c_sclin, i2c_sdaout, i2c_sdaen, i2c_sdain,
spi_miso, spi_mosi, spi_sck, spi_slvsel,
prom32,
spw_clksel,lspw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs,
lgtx_clk, lerx_clk, erxd, erx_dv, letx_clk, etxd, etx_en, etx_er, erx_er, erx_col, erx_crs, emdint, emdioin, emdioout, emdioen, emdc ,
trst, tck, tms, tdi, tdo, tdoen,
scanen, testen, testrst, testoen,
chain_tck, chain_tckn, chain_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
end;
|
entity tb_test is
end tb_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test is
signal a : std_logic_vector (31 downto 0) := (others => '0');
signal b : std_logic_vector (31 downto 0);
begin
dut: entity work.test
port map (a_in => a, b_out => b);
process
begin
a <= x"0000_0003";
wait for 1 ns;
assert b = x"0000_0007" severity failure;
wait;
end process;
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ecc_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ecc_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:06 wig Exp $
-- $Date: 2004/04/06 10:50:06 $
-- $Log: inst_ecc_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:06 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ecc_e
--
architecture rtl of inst_ecc_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity program_counter is
generic (
interrupt_vector : unsigned(11 downto 0) := X"3FF";
stack_depth : positive := 30
);
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
rst_req : out std_logic;
bram_pause : in STD_LOGIC;
call : in STD_LOGIC;
ret : in std_logic;
inter_j : in std_logic;
jump : in STD_LOGIC;
jmp_addr : in unsigned (11 downto 0);
address : out unsigned (11 downto 0));
end program_counter;
architecture Behavioral of program_counter is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type stack_t is array (stack_depth-1 downto 0) of unsigned(11 downto 0);
signal stack : stack_t := (others => (others => '0'));
signal pointer : unsigned (log2ceil(stack_depth+1)-1 downto 0);
signal counter : unsigned (12 downto 0);
signal jmp_int : std_logic;
signal jmp_done : std_logic;
signal addr_o : unsigned (11 downto 0);
begin
jmp_int <= jump or call or inter_j;
address <= interrupt_vector when inter_j = '1' else addr_o ;
clken : process (clk)
variable p : unsigned(pointer'left+1 downto 0);
variable addr_next : unsigned (11 downto 0);
begin
if (rising_edge(clk)) then
if (reset = '1') then
counter <= x"001" & '0';
addr_o <= (others => '0');
jmp_done <= '0';
pointer <= (others => '0');
rst_req <= '0';
else
if (bram_pause = '1') then
-- counter <= addr_o & '1';
jmp_done <= jmp_done;
-- addr_o <= counter(12 downto 1);
elsif (ret = '1' and jmp_done <= '0') then
p := ('0' & pointer) - 1;
if (p = (p'range => '1')) then
rst_req <= '1';
else
pointer <= p(pointer'range);
addr_next := stack(to_integer(p));
counter <= addr_next & '1';
addr_o <= addr_next;
jmp_done <= '1';
end if;
elsif (inter_j = '1') then
p := ('0' & pointer) + 1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o-1;
pointer <= p(pointer'range);
counter <= (interrupt_vector & '1') + ("" & '1');
addr_o <= interrupt_vector;
jmp_done <= '1';
end if;
elsif (jmp_int = '1' and jmp_done <= '0') then
if (call = '1') then
p := ('0' & pointer) +1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o+1;
pointer <= p(pointer'range);
end if;
end if;
counter <= jmp_addr & '1';
addr_o <= jmp_addr;
jmp_done <= '1';
else
jmp_done <= '0';
counter <= counter + 1;
addr_o <= counter(12 downto 1);
end if;
end if;
end if;
end process clken;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity program_counter is
generic (
interrupt_vector : unsigned(11 downto 0) := X"3FF";
stack_depth : positive := 30
);
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
rst_req : out std_logic;
bram_pause : in STD_LOGIC;
call : in STD_LOGIC;
ret : in std_logic;
inter_j : in std_logic;
jump : in STD_LOGIC;
jmp_addr : in unsigned (11 downto 0);
address : out unsigned (11 downto 0));
end program_counter;
architecture Behavioral of program_counter is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type stack_t is array (stack_depth-1 downto 0) of unsigned(11 downto 0);
signal stack : stack_t := (others => (others => '0'));
signal pointer : unsigned (log2ceil(stack_depth+1)-1 downto 0);
signal counter : unsigned (12 downto 0);
signal jmp_int : std_logic;
signal jmp_done : std_logic;
signal addr_o : unsigned (11 downto 0);
begin
jmp_int <= jump or call or inter_j;
address <= interrupt_vector when inter_j = '1' else addr_o ;
clken : process (clk)
variable p : unsigned(pointer'left+1 downto 0);
variable addr_next : unsigned (11 downto 0);
begin
if (rising_edge(clk)) then
if (reset = '1') then
counter <= x"001" & '0';
addr_o <= (others => '0');
jmp_done <= '0';
pointer <= (others => '0');
rst_req <= '0';
else
if (bram_pause = '1') then
-- counter <= addr_o & '1';
jmp_done <= jmp_done;
-- addr_o <= counter(12 downto 1);
elsif (ret = '1' and jmp_done <= '0') then
p := ('0' & pointer) - 1;
if (p = (p'range => '1')) then
rst_req <= '1';
else
pointer <= p(pointer'range);
addr_next := stack(to_integer(p));
counter <= addr_next & '1';
addr_o <= addr_next;
jmp_done <= '1';
end if;
elsif (inter_j = '1') then
p := ('0' & pointer) + 1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o-1;
pointer <= p(pointer'range);
counter <= (interrupt_vector & '1') + ("" & '1');
addr_o <= interrupt_vector;
jmp_done <= '1';
end if;
elsif (jmp_int = '1' and jmp_done <= '0') then
if (call = '1') then
p := ('0' & pointer) +1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o+1;
pointer <= p(pointer'range);
end if;
end if;
counter <= jmp_addr & '1';
addr_o <= jmp_addr;
jmp_done <= '1';
else
jmp_done <= '0';
counter <= counter + 1;
addr_o <= counter(12 downto 1);
end if;
end if;
end if;
end process clken;
end Behavioral;
|
--------------------------------------------------------------------------
--
-- Engineer: Jeff Gerfen
-- Create Date: 2016.02.26
-- Design Name: counter
-- Module Name: counter
--
-- DESCRIPTION:
-- Simple up counter with synchronous load and synchronous reset controls.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity db_1shot_counter is
Port ( RST : in STD_LOGIC;
CLK : in STD_LOGIC;
INC : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (7 downto 0));
end db_1shot_counter;
architecture Behavioral of db_1shot_counter is
signal s_count : std_logic_vector (7 downto 0) := "00000000";
begin
proc: process(CLK, RST, INC, s_count)
begin
if(rising_edge(CLK)) then
if(RST = '1') then -- synchronous reset
s_count <= "00000000";
elsif(INC = '1') then
s_count <= s_count + '1';
end if;
end if;
end process proc;
COUNT <= s_count;
end Behavioral;
|
entity test is
constant a : b :=
foo /= bar nand baz nor qux;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc292.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p26n01i00292ent IS
type mytime is range 0 to 30
units
fs;
end units;
END c03s01b03x00p26n01i00292ent;
ARCHITECTURE c03s01b03x00p26n01i00292arch OF c03s01b03x00p26n01i00292ent IS
BEGIN
TESTING: PROCESS
variable i:integer;
variable t:mytime;
BEGIN
t:= 20 fs;
i:= mytime'POS(t);
assert NOT( i=20 )
report "***PASSED TEST: c03s01b03x00p26n01i00292"
severity NOTE;
assert ( i=20 )
report "***FAILED TEST: c03s01b03x00p26n01i00292 - POS attribute can be used to convert between abstract values and physical values."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p26n01i00292arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc292.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p26n01i00292ent IS
type mytime is range 0 to 30
units
fs;
end units;
END c03s01b03x00p26n01i00292ent;
ARCHITECTURE c03s01b03x00p26n01i00292arch OF c03s01b03x00p26n01i00292ent IS
BEGIN
TESTING: PROCESS
variable i:integer;
variable t:mytime;
BEGIN
t:= 20 fs;
i:= mytime'POS(t);
assert NOT( i=20 )
report "***PASSED TEST: c03s01b03x00p26n01i00292"
severity NOTE;
assert ( i=20 )
report "***FAILED TEST: c03s01b03x00p26n01i00292 - POS attribute can be used to convert between abstract values and physical values."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p26n01i00292arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc292.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p26n01i00292ent IS
type mytime is range 0 to 30
units
fs;
end units;
END c03s01b03x00p26n01i00292ent;
ARCHITECTURE c03s01b03x00p26n01i00292arch OF c03s01b03x00p26n01i00292ent IS
BEGIN
TESTING: PROCESS
variable i:integer;
variable t:mytime;
BEGIN
t:= 20 fs;
i:= mytime'POS(t);
assert NOT( i=20 )
report "***PASSED TEST: c03s01b03x00p26n01i00292"
severity NOTE;
assert ( i=20 )
report "***FAILED TEST: c03s01b03x00p26n01i00292 - POS attribute can be used to convert between abstract values and physical values."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p26n01i00292arch;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
STATE1a,
STATE1,
STATE2,
STATE3,
STATE4,
STATE5,
STATE6,
STATE7,
STATE8,
STATE9,
STATE10,
FUNCTION_EXIT,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE10 : std_logic_vector(0 to 15) := x"0110";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
-- constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
-- constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
-- constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
-- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
-- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
-- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
reg1 <= reg1_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE2 =>
current_state <= STATE2;
when U_STATE5 =>
current_state <= STATE5;
when U_STATE7 =>
current_state <= STATE7;
when U_STATE10 =>
current_state <= STATE10;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
reg1_next <= reg1;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- Push number of bytes to allocate
thrd2intrfc_value <= x"00000008";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE1a;
when STATE1a =>
-- Push number of bytes to allocate
thrd2intrfc_value <= x"00000004";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE1;
when STATE1 =>
-- Call malloc
thrd2intrfc_function <= FUNCTION_CALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE2;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE2 =>
-- Read the value HWTI gave us
reg1_next <= intrfc2thrd_value;
next_state <= STATE5;
when STATE3 =>
thrd2intrfc_value <= reg1;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE4;
when STATE4 =>
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE5;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE5 =>
thrd2intrfc_value <= x"00000008";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE6;
when STATE6 =>
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE7;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE7 =>
reg1_next <= reg1(16 to 31) & intrfc2thrd_value(16 to 31);
next_state <= STATE8;
when STATE8 =>
thrd2intrfc_value <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE9;
when STATE9 =>
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE10;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE10 =>
thrd2intrfc_value <= reg1;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-- revision history:
-- 06.07.2015 Alex Schoenberger created
-- 07.08.2015 Patrick Appenheimer cpu_datapath instanciated
-- 10.08.2015 Bahri Enis Demirtel cpu_control added
library IEEE;
use IEEE.std_logic_1164.ALL;
library WORK;
use WORK.cpu_pack.all;
entity cpu is
port(
clk : in std_logic;
rst : in std_logic;
instr_addr : out std_logic_vector(31 downto 0);
data_addr : out std_logic_vector(31 downto 0);
rd_mask : out std_logic_vector(3 downto 0);
wr_mask : out std_logic_vector(3 downto 0);
instr_stall : in std_logic;
data_stall : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
data_to_cpu : in std_logic_vector(31 downto 0);
data_from_cpu : out std_logic_vector(31 downto 0)
);
end entity cpu;
architecture structure_cpu of cpu is
signal alu_op : std_logic_vector(5 downto 0);
signal exc_mux1 : std_logic_vector(1 downto 0);
signal exc_mux2 : std_logic_vector(1 downto 0);
signal exc_alu_zero : std_logic_vector(0 downto 0);
signal memstg_mux : std_logic;
signal id_regdest_mux : std_logic_vector (1 downto 0);
signal id_regshift_mux : std_logic_vector (1 downto 0);
signal id_enable_regs : std_logic;
signal in_mux_pc : std_logic;
signal stage_control : std_logic_vector (4 downto 0);
begin
-- control logic
u1_control: entity work.control_pipeline(behavioural)
PORT MAP(clk, rst, rd_mask, wr_mask, instr_stall, data_stall, instr_in, alu_op, exc_mux1, exc_mux2,
exc_alu_zero, memstg_mux, id_regdest_mux, id_regshift_mux, id_enable_regs, in_mux_pc, stage_control
);
-- datapath
u2_datapath: entity work.cpu_datapath(structure_cpu_datapath)
PORT MAP(clk, rst, instr_addr, data_addr, instr_in, data_to_cpu, data_from_cpu, alu_op, exc_mux1, exc_mux2,
exc_alu_zero, memstg_mux, id_regdest_mux, id_regshift_mux, id_enable_regs, in_mux_pc, stage_control
);
end architecture structure_cpu;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
port(
data: in STD_LOGIC_VECTOR(3 downto 0);
segments: out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture seven_seg_decoder_arch of seven_seg_decoder is
begin
process(data)
begin
case data is
when X"0" => segments <= not "0111111";
when X"1" => segments <= not "0000110";
when X"2" => segments <= not "1011011";
when X"3" => segments <= not "1001111";
when X"4" => segments <= not "1100110";
when X"5" => segments <= not "1101101";
when X"6" => segments <= not "1111101";
when X"7" => segments <= not "0000111";
when X"8" => segments <= not "1111111";
when X"9" => segments <= not "1101111";
when X"A" => segments <= not "1110111";
when X"B" => segments <= not "1111100";
when X"C" => segments <= not "0111001";
when X"D" => segments <= not "1011110";
when X"E" => segments <= not "1111001";
when X"F" => segments <= not "1110001";
when others => segments <= not "0000000";
end case;
end process;
end;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_3;
end architecture ARCH;
|
entity tb_min01 is
end tb_min01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_min01 is
signal l, r : natural;
signal res : natural;
begin
min01_1: entity work.min01
port map (
a => l,
b => r,
o => res);
process
begin
l <= 12;
r <= 15;
wait for 1 ns;
assert res = 12 severity failure;
wait;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.08.2016 16:52:51
-- Design Name:
-- Module Name: cpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity cpu is
Port (
clk : in std_ulogic;
inst_mem_data : in data_t;
inst_mem_addr : out addr_t;
data_mem_data_r : in data_t;
data_mem_data_w : out data_t;
data_mem_addr : out addr_t;
data_mem_we : out std_ulogic
);
end cpu;
architecture Behavioral of cpu is
signal rstack_push : std_ulogic;
signal rstack_pop : std_ulogic;
signal rstack_data_read : data_t;
signal rstack_data_write : data_t;
signal dstack_push : std_ulogic;
signal dstack_pop : std_ulogic;
signal dstack_data_read : data_t;
signal dstack_data_write : data_t;
begin
control: entity work.control port map (
clk => clk,
inst_mem_data => inst_mem_data,
inst_mem_addr => inst_mem_addr,
data_mem_data_read => data_mem_data_r,
data_mem_data_write =>data_mem_data_w,
data_mem_addr => data_mem_addr,
data_mem_we => data_mem_we,
dstack_data_read => dstack_data_read,
dstack_data_write => dstack_data_write,
dstack_push => dstack_push,
dstack_pop => dstack_pop,
rstack_data_read => rstack_data_read,
rstack_data_write => rstack_data_write,
rstack_push => rstack_push,
rstack_pop => rstack_pop
);
rstack: entity work.stack_256x16 port map (
push => rstack_push,
pop => rstack_pop,
dout => rstack_data_read,
din => rstack_data_write,
clk => clk
);
dstack: entity work.stack_256x16 port map (
push => dstack_push,
pop => dstack_pop,
dout => dstack_data_read,
din => dstack_data_write,
clk => clk
);
end Behavioral;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
component dspba_mux2 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_mux3 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_mux4 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xin3 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intadd_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intadd_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intaddsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intaddsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
component dspba_mux2 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_mux3 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_mux4 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xin3 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intadd_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intadd_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intaddsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intaddsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
port(
clk, not_reset: in std_logic;
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vga;
architecture sync of vga is
-- VGA 640x480 sync parameters
constant HD: integer := 640; -- horizontal display area
constant HF: integer := 16; -- h. front porch
constant HB: integer := 48; -- h. back porch
constant HR: integer := 96; -- h. retrace
constant VD: integer := 480; -- vertical display area
constant VF: integer := 11; -- v. front porch
constant VB: integer := 31; -- v. back porch
constant VR: integer := 2; -- v. retrace
-- mod-2 counter
signal mod2, mod2_next: std_logic;
-- sync counters
signal v_count, v_count_next: std_logic_vector(9 downto 0);
signal h_count, h_count_next: std_logic_vector(9 downto 0);
-- output buffer
signal v_sync, h_sync: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
mod2 <= '0';
v_count <= (others => '0');
h_count <= (others => '0');
v_sync <= '0';
h_sync <= '0';
elsif clk'event and clk = '0' then
mod2 <= mod2_next;
v_count <= v_count_next;
h_count <= h_count_next;
v_sync <= v_sync_next;
h_sync <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2 = '1' else '0';
-- end of counters (799 and 524 pixels)
h_end <= '1' when h_count = (HD + HF + HB + HR - 1) else '0';
v_end <= '1' when v_count = (VD + VF + VB + VR - 1) else '0';
-- mod-800 horizontal sync counter
process(h_count, h_end, pixel_tick)
begin
if pixel_tick = '1' then
if h_end = '1' then
h_count_next <= (others => '0');
else
h_count_next <= h_count + 1;
end if;
else
h_count_next <= h_count;
end if;
end process;
-- mod-525 vertical sync counter
process(v_count, h_end, v_end, pixel_tick)
begin
if pixel_tick = '1' and h_end = '1' then
if v_end = '1' then
v_count_next <= (others => '0');
else
v_count_next <= v_count + 1;
end if;
else
v_count_next <= v_count;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <= '1' when (h_count >= (HD + HF)) and
(h_count <= (HD + HF + HR - 1)) else
'0';
v_sync_next <= '1' when (v_count >= (VD + VF)) and
(v_count <= (VD + VF + VR - 1)) else
'0';
-- video on/off
video_on <= '1' when (h_count < HD) and (v_count < VD) else '0';
-- output signal
hsync <= h_sync;
vsync <= v_sync;
pixel_x <= h_count;
pixel_y <= v_count;
p_tick <= pixel_tick;
end sync;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
port(
clk, not_reset: in std_logic;
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vga;
architecture sync of vga is
-- VGA 640x480 sync parameters
constant HD: integer := 640; -- horizontal display area
constant HF: integer := 16; -- h. front porch
constant HB: integer := 48; -- h. back porch
constant HR: integer := 96; -- h. retrace
constant VD: integer := 480; -- vertical display area
constant VF: integer := 11; -- v. front porch
constant VB: integer := 31; -- v. back porch
constant VR: integer := 2; -- v. retrace
-- mod-2 counter
signal mod2, mod2_next: std_logic;
-- sync counters
signal v_count, v_count_next: std_logic_vector(9 downto 0);
signal h_count, h_count_next: std_logic_vector(9 downto 0);
-- output buffer
signal v_sync, h_sync: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
mod2 <= '0';
v_count <= (others => '0');
h_count <= (others => '0');
v_sync <= '0';
h_sync <= '0';
elsif clk'event and clk = '0' then
mod2 <= mod2_next;
v_count <= v_count_next;
h_count <= h_count_next;
v_sync <= v_sync_next;
h_sync <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2 = '1' else '0';
-- end of counters (799 and 524 pixels)
h_end <= '1' when h_count = (HD + HF + HB + HR - 1) else '0';
v_end <= '1' when v_count = (VD + VF + VB + VR - 1) else '0';
-- mod-800 horizontal sync counter
process(h_count, h_end, pixel_tick)
begin
if pixel_tick = '1' then
if h_end = '1' then
h_count_next <= (others => '0');
else
h_count_next <= h_count + 1;
end if;
else
h_count_next <= h_count;
end if;
end process;
-- mod-525 vertical sync counter
process(v_count, h_end, v_end, pixel_tick)
begin
if pixel_tick = '1' and h_end = '1' then
if v_end = '1' then
v_count_next <= (others => '0');
else
v_count_next <= v_count + 1;
end if;
else
v_count_next <= v_count;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <= '1' when (h_count >= (HD + HF)) and
(h_count <= (HD + HF + HR - 1)) else
'0';
v_sync_next <= '1' when (v_count >= (VD + VF)) and
(v_count <= (VD + VF + VR - 1)) else
'0';
-- video on/off
video_on <= '1' when (h_count < HD) and (v_count < VD) else '0';
-- output signal
hsync <= h_sync;
vsync <= v_sync;
pixel_x <= h_count;
pixel_y <= v_count;
p_tick <= pixel_tick;
end sync;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue371 is
end issue371;
architecture behav of issue371 is
signal clock : std_logic;
signal chip_select_sig : std_logic;
signal address_sig : std_logic_vector(2 downto 0);
signal write_sig : std_logic;
signal host_data_bus_sig : std_logic_vector(7 downto 0);
procedure wait_for_ticks (num_clock_cycles : in integer) is
begin
for i in 1 to num_clock_cycles loop
wait until rising_edge(clock);
end loop;
end procedure wait_for_ticks;
procedure host_write (addr: in std_logic_vector;
byte : in std_logic_vector;
signal clock : in std_logic;
signal chip_select : out std_logic;
signal address : out std_logic_vector;
signal write : out std_logic;
signal host_data_bus : out std_logic_vector;
invert_cs_etc : in std_logic
) is
begin
wait until rising_edge(clock);
write <= '1' xor invert_cs_etc;
chip_select <= '1' xor invert_cs_etc;
address <= addr;
host_data_bus <= byte;
wait_for_ticks(1);
write <= '0' xor invert_cs_etc;
chip_select <= '0' xor invert_cs_etc;
for i in address'LOW to address'HIGH loop
address(i) <= '0';
end loop;
for i in host_data_bus'LOW to host_data_bus'HIGH loop
host_data_bus(i) <= '0';
end loop;
wait until rising_edge(clock);
end procedure host_write;
begin
process
begin
for i in 0 to 10 loop
clock <= '0';
wait for 1 us;
clock <= '1';
wait for 1 us;
end loop;
wait;
end process;
process
begin
host_write("001", X"aa", clock, chip_select_sig, address_sig, write_sig, host_data_bus_sig, '0');
for i in address_sig'LOW to address_sig'HIGH loop
assert address_sig(i) = '0';
end loop;
for i in host_data_bus_sig'LOW to host_data_bus_sig'HIGH loop
assert host_data_bus_sig(i) = '0';
end loop;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue371 is
end issue371;
architecture behav of issue371 is
signal clock : std_logic;
signal chip_select_sig : std_logic;
signal address_sig : std_logic_vector(2 downto 0);
signal write_sig : std_logic;
signal host_data_bus_sig : std_logic_vector(7 downto 0);
procedure wait_for_ticks (num_clock_cycles : in integer) is
begin
for i in 1 to num_clock_cycles loop
wait until rising_edge(clock);
end loop;
end procedure wait_for_ticks;
procedure host_write (addr: in std_logic_vector;
byte : in std_logic_vector;
signal clock : in std_logic;
signal chip_select : out std_logic;
signal address : out std_logic_vector;
signal write : out std_logic;
signal host_data_bus : out std_logic_vector;
invert_cs_etc : in std_logic
) is
begin
wait until rising_edge(clock);
write <= '1' xor invert_cs_etc;
chip_select <= '1' xor invert_cs_etc;
address <= addr;
host_data_bus <= byte;
wait_for_ticks(1);
write <= '0' xor invert_cs_etc;
chip_select <= '0' xor invert_cs_etc;
for i in address'LOW to address'HIGH loop
address(i) <= '0';
end loop;
for i in host_data_bus'LOW to host_data_bus'HIGH loop
host_data_bus(i) <= '0';
end loop;
wait until rising_edge(clock);
end procedure host_write;
begin
process
begin
for i in 0 to 10 loop
clock <= '0';
wait for 1 us;
clock <= '1';
wait for 1 us;
end loop;
wait;
end process;
process
begin
host_write("001", X"aa", clock, chip_select_sig, address_sig, write_sig, host_data_bus_sig, '0');
for i in address_sig'LOW to address_sig'HIGH loop
assert address_sig(i) = '0';
end loop;
for i in host_data_bus_sig'LOW to host_data_bus_sig'HIGH loop
assert host_data_bus_sig(i) = '0';
end loop;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncreg
-- File: syncreg.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Technology wrapper for sync registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity syncreg is
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end;
architecture tmap of syncreg is
begin
sync0 : if has_syncreg(tech) = 0 generate
--syncreg : block
-- signal c : std_logic_vector(stages-1 downto 0);
--begin
-- x0 : process(clk)
-- begin
-- if rising_edge(clk) then
-- for i in 0 to stages-1 loop
-- c(i) <= d;
-- if i /= 0 then c(i) = c(i-1); end if;
-- end loop;
-- end if;
-- end process;
-- q <= c(stages-1);
--end block syncreg;
syncreg : block
signal c : std_logic_vector(stages downto 0);
attribute keep : boolean;
attribute keep of c : signal is true;
begin
c(0) <= d;
syncregs : for i in 1 to stages generate
dff : grdff
generic map(tech => tech)
port map(clk => clk, d => c(i-1), q => c(i));
end generate;
q <= c(stages);
end block syncreg;
end generate;
end;
|
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SnTSdfEs3KlwjK2NF45a2mAyhqII+d1b5OnSL6xmeX2N+vmlD5l4bG43s4rPjA7Y4Sq+x5Pdx05U
L8kzV7IQt6bBNtJjrWx3aXdtSqdSJlozu72eNuvQAmYIqz8PT0K+q89Wk1Tg7XzAke8BFp/uomaf
ZjTQ63VvLBMy841H8iXZg/QMtgYebGeQJ4QNzGd9XiThPjF5wnyTIr/WBMS73nhyVNu/6q/kgvAm
DjuzWH03NxiyXOQCGi3H7pEBqIqyBt32XFWIq5s5BhYwVTMTdA4DXj5KFYW/lNEyNc37K1nN/60x
pDQerig6nEEs1u+WJfUIQ32mSpTz7vXpOm4aWLO5qp8UoUP8QqvNV2NmFxfgLYUXwaQF16ZMk/p/
fOgAAPNMtQ3tzjZ4k/cu2R8NsmOj3KtJE3p2Venv/Vv4RlKOoGBatFY6//HbvhtEAClfcVSn98vB
azcpSJRjeY5rIm7zzSW5p5QnqsXFEt6bQL3Oj+kuLN0T7kt8j6tPAuMoKGztwYPrCsw7JxEGAfHY
BkQplu/d5tim+h0Ox7yNr2CwcQg0fWIzy0xQxEjnEt1WU253/eHigP9skfgXIsW7MyDp+xGIB00k
n0wdKaFvd5CgPmKsGxR0AT2Cc1yvhRZ3YVRPIgJLh8qP/SSYoTuJpvDp04vGeqJFSOpCz5SHLfC0
eL7L5Um7UvRYcTsdVCy3iDNSvVsX4Wr8wJAlQaXOogyR8M1I/IGzwrY0LZLsby+d9AffgIGmpqxp
cyGPHaDY/Q7yGri12wYWz3UbytKiSt99OBnsI+7ixIk6qFcJS/R20cBb3l2+3HvWIHV7Eim5mEQH
8/IPykOy0I8KNcHiWaXPCVoiJ4rMZAP+2drBhbhodP59pnHohLxApM9sj+xOmgCAQJu7C5TpLXYr
odA7/bK1gL4LuMlEiGUMUmtrJoWg/M1yLKhkZ9CKKeZYxXnrokC940pJxp6W58qugqfrs1HSW93L
ApQzPbhIBYqeZjWdbU9cukQTkvSZPeoNRaXP2AVe26Y3UdtCubStetjVI1rGQax0X4mnKX1dicIM
81V5kkChVeMfhPl/Hp71vpullz7HJVp4+Be8RYGul/z9/ZsSxiChYm2K7vhWYX8oFa1zDqswaroP
eOHs0igAL8wykKwWGIKEGk0mig9JiWgp4h02+kgwpjlTXIMh8uEZxrz+SKXMQFSQgEOzJ6kf/i62
ohmUI9bzprHpj2I7S9aZutdGgXdFeYLpb38pioZWsfJj1+8r1fAo2FTHSaIbXRwT+BWWpdjWFrTG
WUUuzoNDm97vEYhEk6vJRZzMiOAIiqec8AfWXlKwse/8HOQXTXL0Iaslw9+HZ5WJe7/8qi/WZ0gi
166wNR2EbPE8XvYqGGPn37proG0=
`protect end_protected
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:46 wig Exp $
-- $Date: 2004/04/06 10:50:46 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:46 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eba_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ebb_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ebc_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
;
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
;
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
;
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_peripheral is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : in t_io_req;
io_resp : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_peripheral;
architecture structural of sid_peripheral is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal control : t_sid_control;
signal sid_addr : unsigned(7 downto 0);
signal sid_wren : std_logic;
signal sid_wdata : std_logic_vector(7 downto 0);
signal sid_rdata : std_logic_vector(7 downto 0);
signal sid_write : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- 4042000
reqs(1) => io_req_filt, -- 4042800
resps(0) => io_resp_regs,
resps(1) => io_resp_filt );
i_regs: entity work.sid_io_regs
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control );
i_sid_mapper: entity work.sid_mapper
port map (
clock => clock,
reset => reset,
control => control,
slot_req => slot_req,
slot_resp => slot_resp,
sid_addr => sid_addr,
sid_wren => sid_wren,
sid_wdata => sid_wdata,
sid_rdata => sid_rdata );
i_sid_engine: entity work.sid_top
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
addr => sid_addr,
wren => sid_wren,
wdata => sid_wdata,
rdata => sid_rdata,
comb_wave_l => control.comb_wave_left,
comb_wave_r => control.comb_wave_right,
io_req_filt => io_req_filt,
io_resp_filt => io_resp_filt,
start_iter => start_iter,
sample_left => sample_left,
sample_right => sample_right );
sid_write <= '1' when slot_req.bus_write='1' and slot_req.bus_address(15 downto 8)=X"D4" else '0';
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_peripheral is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : in t_io_req;
io_resp : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_peripheral;
architecture structural of sid_peripheral is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal control : t_sid_control;
signal sid_addr : unsigned(7 downto 0);
signal sid_wren : std_logic;
signal sid_wdata : std_logic_vector(7 downto 0);
signal sid_rdata : std_logic_vector(7 downto 0);
signal sid_write : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- 4042000
reqs(1) => io_req_filt, -- 4042800
resps(0) => io_resp_regs,
resps(1) => io_resp_filt );
i_regs: entity work.sid_io_regs
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control );
i_sid_mapper: entity work.sid_mapper
port map (
clock => clock,
reset => reset,
control => control,
slot_req => slot_req,
slot_resp => slot_resp,
sid_addr => sid_addr,
sid_wren => sid_wren,
sid_wdata => sid_wdata,
sid_rdata => sid_rdata );
i_sid_engine: entity work.sid_top
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
addr => sid_addr,
wren => sid_wren,
wdata => sid_wdata,
rdata => sid_rdata,
comb_wave_l => control.comb_wave_left,
comb_wave_r => control.comb_wave_right,
io_req_filt => io_req_filt,
io_resp_filt => io_resp_filt,
start_iter => start_iter,
sample_left => sample_left,
sample_right => sample_right );
sid_write <= '1' when slot_req.bus_write='1' and slot_req.bus_address(15 downto 8)=X"D4" else '0';
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_peripheral is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : in t_io_req;
io_resp : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_peripheral;
architecture structural of sid_peripheral is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal control : t_sid_control;
signal sid_addr : unsigned(7 downto 0);
signal sid_wren : std_logic;
signal sid_wdata : std_logic_vector(7 downto 0);
signal sid_rdata : std_logic_vector(7 downto 0);
signal sid_write : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- 4042000
reqs(1) => io_req_filt, -- 4042800
resps(0) => io_resp_regs,
resps(1) => io_resp_filt );
i_regs: entity work.sid_io_regs
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control );
i_sid_mapper: entity work.sid_mapper
port map (
clock => clock,
reset => reset,
control => control,
slot_req => slot_req,
slot_resp => slot_resp,
sid_addr => sid_addr,
sid_wren => sid_wren,
sid_wdata => sid_wdata,
sid_rdata => sid_rdata );
i_sid_engine: entity work.sid_top
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
addr => sid_addr,
wren => sid_wren,
wdata => sid_wdata,
rdata => sid_rdata,
comb_wave_l => control.comb_wave_left,
comb_wave_r => control.comb_wave_right,
io_req_filt => io_req_filt,
io_resp_filt => io_resp_filt,
start_iter => start_iter,
sample_left => sample_left,
sample_right => sample_right );
sid_write <= '1' when slot_req.bus_write='1' and slot_req.bus_address(15 downto 8)=X"D4" else '0';
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_peripheral is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : in t_io_req;
io_resp : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_peripheral;
architecture structural of sid_peripheral is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal control : t_sid_control;
signal sid_addr : unsigned(7 downto 0);
signal sid_wren : std_logic;
signal sid_wdata : std_logic_vector(7 downto 0);
signal sid_rdata : std_logic_vector(7 downto 0);
signal sid_write : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- 4042000
reqs(1) => io_req_filt, -- 4042800
resps(0) => io_resp_regs,
resps(1) => io_resp_filt );
i_regs: entity work.sid_io_regs
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control );
i_sid_mapper: entity work.sid_mapper
port map (
clock => clock,
reset => reset,
control => control,
slot_req => slot_req,
slot_resp => slot_resp,
sid_addr => sid_addr,
sid_wren => sid_wren,
sid_wdata => sid_wdata,
sid_rdata => sid_rdata );
i_sid_engine: entity work.sid_top
generic map (
g_filter_div => g_filter_div,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
addr => sid_addr,
wren => sid_wren,
wdata => sid_wdata,
rdata => sid_rdata,
comb_wave_l => control.comb_wave_left,
comb_wave_r => control.comb_wave_right,
io_req_filt => io_req_filt,
io_resp_filt => io_resp_filt,
start_iter => start_iter,
sample_left => sample_left,
sample_right => sample_right );
sid_write <= '1' when slot_req.bus_write='1' and slot_req.bus_address(15 downto 8)=X"D4" else '0';
end structural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_axceleratorpkg
-- File: usbhc_axceleratorpkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for axcelerator
-- usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_axceleratorpkg is
component usbhc_axcelerator_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean;
end usbhc_axceleratorpkg;
package body usbhc_axceleratorpkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_axceleratorpkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_axceleratorpkg
-- File: usbhc_axceleratorpkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for axcelerator
-- usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_axceleratorpkg is
component usbhc_axcelerator_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean;
end usbhc_axceleratorpkg;
package body usbhc_axceleratorpkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_axceleratorpkg;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00608
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 11.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00608)
-- PKG00608
-- PKG00608/BODY
-- ENT00608_Test_Bench(ARCH00608_Test_Bench)
-- CONF00608
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00608 of E00000 is
begin
process
begin
test_report ( "ARCH00608" ,
"A context clause may appear before any design unit in a "&
"design file" ,
True ) ;
wait ;
end process ;
end ARCH00608 ;
--
library WORK ;
package PKG00608 is
procedure Proc ;
end PKG00608 ;
--
library WORK ;
use WORK.STANDARD_TYPES.all ;
package body PKG00608 is
procedure Proc is
begin
null ;
end Proc ;
end PKG00608 ;
--
library WORK, STD ;
entity ENT00608_Test_Bench is
end ENT00608_Test_Bench ;
use WORK.PKG00608.all ;
architecture ARCH00608_Test_Bench of ENT00608_Test_Bench is
begin
L1:
block
component UUT
end component ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00608_Test_Bench ;
--
library WORK ;
use WORK.ENT00608_Test_bench ;
use WORK.E00000 ;
configuration CONF00608 of ENT00608_Test_Bench is
for ARCH00608_Test_Bench
for L1
for CIS1 : UUT
use entity E00000 ( ARCH00608 );
end for ;
end for ;
end for ;
end CONF00608 ;
--
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
m_axis_aclk : in std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
m_axis_tkeep : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
m_axis_tvalid <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => m_axis_tready,
out_data => m_axis_tdata
);
m_axis_tkeep <= "1111";
m_axis_tlast <= '1' when period_count = 0 else '0';
period_counter: process(m_axis_aclk) is
begin
if rising_edge(m_axis_aclk) then
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and m_axis_tready = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end if;
end process;
end;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.all;
ENTITY alu_test IS
END alu_test;
ARCHITECTURE behavior OF alu_test IS
COMPONENT alu
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
opsel : IN std_logic_vector(3 downto 0);
oflw : OUT std_logic;
clk : IN std_logic;
Ylow : OUT std_logic_vector(7 downto 0);
Yhigh : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal opsel : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal oflw : std_logic;
signal Ylow : std_logic_vector(7 downto 0);
signal Yhigh : std_logic_vector(7 downto 0);
signal Ytemp : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
a => a,
b => b,
opsel => opsel,
oflw => oflw,
clk => clk,
Ylow => Ylow,
Yhigh => Yhigh
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
Ytemp <= Yhigh(7 downto 0) & Ylow(7 downto 0);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= std_logic_vector(to_unsigned(120,8)); --addition test, no carry
b <= std_logic_vector(to_unsigned(38,8));
opsel <= "0000";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(213,8)); --addition test, carry on
b <= std_logic_vector(to_unsigned(119,8));
opsel <= "0000";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(248,8)); --subtract, no oflw
b <= std_logic_vector(to_unsigned(153,8));
opsel <= "0001";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(190,8)); --subtract, oflw on
b <= std_logic_vector(to_unsigned(217,8));
opsel <= "0001";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(11,8)); --multiply, no oflw
b <= std_logic_vector(to_unsigned(9,8));
opsel <= "0010";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(57,8)); --multiply, oflw on
b <= std_logic_vector(to_unsigned(64,8));
opsel <= "0010";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(120,8)); --division, no oflw (BEWARE OF DURATION)
b <= std_logic_vector(to_unsigned(11,8));
opsel <= "0011";
wait for clk_period*50;
a <= std_logic_vector(to_unsigned(125,8)); --division, oflw on
b <= std_logic_vector(to_unsigned(138,8));
opsel <= "0011";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(250,8)); -- logical and
b <= std_logic_vector(to_unsigned(61,8));
opsel <= "0100";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(138,8)); --logical or
b <= std_logic_vector(to_unsigned(66,8));
opsel <= "0101";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(147,8)); --logical xor
b <= std_logic_vector(to_unsigned(82,8));
opsel <= "0110";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(138,8)); --logical not
b <= std_logic_vector(to_unsigned(66,8));
opsel <= "0111";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(146,8)); --shift left, oflw on (>128)
b <= std_logic_vector(to_unsigned(61,8));
opsel <= "1000";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(239,8)); --shift right, oflw on (odd number)
b <= std_logic_vector(to_unsigned(62,8));
opsel <= "1001";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(150,8)); --rotate left
b <= std_logic_vector(to_unsigned(64,8));
opsel <= "1010";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(77,8)); --rotate right
b <= std_logic_vector(to_unsigned(68,8));
opsel <= "1011";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(146,8)); --compare equality
b <= std_logic_vector(to_unsigned(146,8));
opsel <= "1100";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(211,8)); --check a>b
b <= std_logic_vector(to_unsigned(146,8));
opsel <= "1100";
wait for clk_period*10;
a <= std_logic_vector(to_unsigned(208,8)); --check b>a
b <= std_logic_vector(to_unsigned(211,8));
opsel <= "1100";
wait for clk_period*10;
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_b_e
--
-- Generated
-- by: wig
-- on: Thu Jan 27 08:21:01 2005
-- cmd: h:/work/mix_new/mix/mix_0.pl -strip -nodelta ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-conf-c.vhd,v 1.2 2005/01/27 07:29:28 wig Exp $
-- $Date: 2005/01/27 07:29:28 $
-- $Log: inst_b_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2005/01/27 07:29:28 wig
-- reworked %OPEN% setup and testcase
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.48 2005/01/26 14:01:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--
--
-- This file is a part of JOP, the Java Optimized Processor
--
-- Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- fifo.vhd
--
-- simple fifo
--
-- uses FF and every rd or wr has to 'bubble' through the hole fifo.
--
-- Author: Martin Schoeberl martin.schoeberl@chello.at
--
--
-- resources on ACEX1K
--
-- (width+2)*depth-1 LCs
--
--
-- 2002-01-06 first working version
-- 2002-11-03 a signal for reaching threshold
-- 2005-02-20 change entity order for modelsim vcom
--
library ieee;
use ieee.std_logic_1164.all;
entity fifo_elem is
generic (width : integer);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
rd_prev : out std_logic;
full : out std_logic
);
end fifo_elem;
architecture rtl of fifo_elem is
signal buf : std_logic_vector(width-1 downto 0);
signal f : std_logic;
begin
dout <= buf;
process(clk, reset, f)
begin
full <= f;
if (reset='1') then
buf <= (others => '0');
f <= '0';
rd_prev <= '0';
elsif rising_edge(clk) then
rd_prev <= '0';
if f='0' then
if wr='1' then
rd_prev <= '1';
buf <= din;
f <= '1';
end if;
else
if rd='1' then
f <= '0';
end if;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic (width : integer := 8; depth : integer := 4; thres : integer := 2);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
half : out std_logic
);
end fifo ;
architecture rtl of fifo is
component fifo_elem is
generic (width : integer);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
rd_prev : out std_logic;
full : out std_logic
);
end component;
signal r, w, rp, f : std_logic_vector(depth-1 downto 0);
type d_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal di, do : d_array;
begin
g1: for i in 0 to depth-1 generate
f1: fifo_elem generic map (width)
port map (clk, reset, di(i), do(i), r(i), w(i), rp(i), f(i));
x: if i<depth-1 generate
r(i) <= rp(i+1);
w(i+1) <= f(i);
di(i+1) <= do(i);
end generate;
end generate;
di(0) <= din;
dout <= do(depth-1);
w(0) <= wr;
r(depth-1) <= rd;
full <= f(0);
half <= f(depth-thres);
empty <= not f(depth-1);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc974.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00974ent IS
END c06s03b00x00p05n01i00974ent;
ARCHITECTURE c06s03b00x00p05n01i00974arch OF c06s03b00x00p05n01i00974ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: R1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V1.BOOLEAN;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00974 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00974arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc974.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00974ent IS
END c06s03b00x00p05n01i00974ent;
ARCHITECTURE c06s03b00x00p05n01i00974arch OF c06s03b00x00p05n01i00974ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: R1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V1.BOOLEAN;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00974 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00974arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc974.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00974ent IS
END c06s03b00x00p05n01i00974ent;
ARCHITECTURE c06s03b00x00p05n01i00974arch OF c06s03b00x00p05n01i00974ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: R1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V1.BOOLEAN;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00974 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00974arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3196.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03196ent IS
END c14s03b00x00p42n01i03196ent;
ARCHITECTURE c14s03b00x00p42n01i03196arch OF c14s03b00x00p42n01i03196ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.10";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,boolean'(TRUE));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03196 - This test will write TEXT into file iofile.10."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03196arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3196.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03196ent IS
END c14s03b00x00p42n01i03196ent;
ARCHITECTURE c14s03b00x00p42n01i03196arch OF c14s03b00x00p42n01i03196ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.10";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,boolean'(TRUE));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03196 - This test will write TEXT into file iofile.10."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03196arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3196.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03196ent IS
END c14s03b00x00p42n01i03196ent;
ARCHITECTURE c14s03b00x00p42n01i03196arch OF c14s03b00x00p42n01i03196ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.10";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,boolean'(TRUE));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03196 - This test will write TEXT into file iofile.10."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03196arch;
|
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00066.P1_1: exit statement does not effect outer loop passed
-- NEED RESULT: ARCH00066.P1_2: exit with no label only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00066.P1_2: exit with no label only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00066.P1_2: exit with no label only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00066.P1_2: exit statement does not effect outer loop passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00066
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.10 (1)
-- 8.10 (3)
-- 8.10 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00066)
-- ENT00066_Test_Bench(ARCH00066_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00066 of E00000 is
signal Dummy : Boolean := false ;
begin
P1_1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
variable done : boolean := false ;
begin
L1 :
for i in boolean loop
--
correct := true ;
L2 :
for j in 1 to 3 loop
correct := (j = 1) and correct ;
exit ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00066.P1_1" ,
"exit with no label or condition only effects " &
"innermost (labeled) loop",
correct ) ;
--
correct := true ;
while not done loop
correct := (not done) and correct ;
done := true ;
exit ;
correct := false ;
end loop ;
--
test_report ( "ARCH00066.P1_1" ,
"exit with no label or condition only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
correct := true ;
done := false ;
loop
correct := (not done) and correct ;
done := true ;
exit ;
correct := false ;
end loop ;
--
test_report ( "ARCH00066.P1_1" ,
"exit with no label or condition only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00066.P1_1" ,
"exit statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_1 ;
--
P1_2 :
process ( Dummy )
variable correct : boolean := true ;
variable counter : integer := 0 ;
variable done : boolean := false ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= boolean'High loop
--
correct := true ;
for j in 1 to 3 loop
correct := correct and (j = 1) ;
exit when j = j ;
correct := false ;
end loop ;
--
test_report ( "ARCH00066.P1_2" ,
"exit with no label only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
correct := true ;
L2 :
while not done loop
correct := (not done) and correct ;
done := true ;
exit when done = done ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00066.P1_2" ,
"exit with no label only effects " &
"innermost (labeled) loop",
correct ) ;
--
correct := true ;
done := false ;
L3 :
loop
correct := (not done) and correct ;
done := true ;
exit when done = done ;
correct := false ;
end loop L3 ;
--
test_report ( "ARCH00066.P1_2" ,
"exit with no label only effects " &
"innermost (labeled) loop",
correct ) ;
--
v_boolean :=
boolean'Succ (v_boolean) ;
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (c_boolean_1) ) ;
test_report ( "ARCH00066.P1_2" ,
"exit statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_2 ;
--
--
end ARCH00066 ;
--
entity ENT00066_Test_Bench is
end ENT00066_Test_Bench ;
--
architecture ARCH00066_Test_Bench of ENT00066_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00066 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00066_Test_Bench ;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ddrv4
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-e.vhd,v 1.1 2004/04/06 10:44:18 wig Exp $
-- $Date: 2004/04/06 10:44:18 $
-- $Log: ddrv4-e.vhd,v $
-- Revision 1.1 2004/04/06 10:44:18 wig
-- Adding result/padio
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ddrv4
--
entity ddrv4 is
-- Generics:
-- No Generated Generics for Entity ddrv4
-- Generated Port Declaration:
port(
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end ddrv4;
--
-- End of Generated Entity ddrv4
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
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