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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: ft245uart.vhd
-- Authors: Jan Schirok - TU Dresden
-- Description: UART via USB FTDI FT245BL FIFO interface
-- interface: APB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ft245 is
type ft245_in_type is record
rddata : std_logic_vector(7 downto 0); -- data read from ft245
rxfn : std_logic; -- data avail (low active)
txen : std_logic; -- transmit possible (low active)
pwrenn : std_logic; -- dev is active (low active)
end record;
type ft245_out_type is record
wrdata : std_logic_vector(7 downto 0); -- data to ft245
oen : std_logic; -- output enable pad (low active)
rdn : std_logic; -- read enable (low active)
wr : std_logic; -- write enable (high active)
end record;
component ft245uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
use work.ft245.all;
entity ft245uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
abits : integer := 8);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ft245i : in ft245_in_type;
ft245o : out ft245_out_type);
end;
architecture rtl of ft245uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- CYCLE DEFINITIONS FOR FT245 COMMUNICATION
--number of counter bits for cycles
constant CYC_WIDTH : integer := 6;
--minimum length of ft245o.rdn pulse
constant RDPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(2, CYC_WIDTH);
--number of clk periods until rddata is valid
constant RDTODATA : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(6, CYC_WIDTH);
--minimum length of ft245o.wr pulse in clk periods
constant WRPULSE : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(8, CYC_WIDTH);
--timeout for rdwait/wrwait (cycles to wait for rxfn/txen => '1')
constant TIMEOUT : std_logic_vector(CYC_WIDTH-1 downto 0)
:= conv_std_logic_vector(63, CYC_WIDTH);
--zero definition
constant CYNULL : std_logic_vector(CYC_WIDTH-1 downto 0)
:= (CYC_WIDTH-1 downto 0 => '0');
type rxtxfsmtype is (idle, rdact, rddata, rdwait, wrdata, wrwait);
type ft245regs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
loopb : std_ulogic; -- loop back mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
break : std_ulogic; -- break detected (data==0x0, reset in SW)
irq : std_ulogic; -- tx/rx interrupt (internal)
ft245i : ft245_in_type; -- input register
ft245o : ft245_out_type; -- output register
rxtxstate : rxtxfsmtype; -- recv/transmit fsm
-- rcnt : std_logic_vector(0 downto 0);
-- tcnt : std_logic_vector(0 downto 0);
rhold : std_logic_vector(7 downto 0);
thold : std_logic_vector(7 downto 0);
cyclecnt : std_logic_vector(CYC_WIDTH-1 downto 0);
end record;
signal r, rin : ft245regs;
begin
uartop : process(rst, r, apbi )
variable rdata : std_logic_vector(31 downto 0);
-- variable scaler : std_logic_vector(11 downto 0);
-- variable rxclk, txclk : std_logic_vector(2 downto 0);
-- variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddr : std_logic_vector(7 downto 2);
variable v : ft245regs;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- dready := '0'; thempty := '1';
-- dready := r.rcnt(0); --rfull := dready; tfull := r.tcnt(0);
-- thempty := not r.tcnt(0);
--thempty := not tfull;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddr(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold;
v.rsempty := '1';
-- v.rcnt(0) := '0';
when "000001" =>
rdata(3 downto 0) := r.break & r.tsempty & r.tsempty & not(r.rsempty); --fifo==shiftreg
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
--no fifo => rdata(31)='0'
rdata(7) := r.loopb;
rdata(3 downto 0) := r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
-- no scaler
null;
when "000100" =>
-- no debug
null;
when others =>
null;
end case;
end if;
paddr := "000000"; paddr(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddr(7 downto 2) is
when "000000" =>
v.thold := apbi.pwdata(7 downto 0);
v.tsempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when "000001" =>
v.break := apbi.pwdata(3);
when "000010" =>
v.loopb := apbi.pwdata(7);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
when "000100" =>
when others =>
null;
end case;
end if;
-- FSM
case r.rxtxstate is
when idle =>
-- loopback mode, rx/tx active, recv buf empty, send buf full
if r.loopb = '1' and r.rxen = '1' and r.txen = '1' and
r.rsempty = '1' and r.tsempty = '0' then
v.rxtxstate := idle; -- loop back in one cycle
v.rhold := r.thold; -- copy transmit byte in recv buf
v.rsempty := '0';
v.tsempty := '1';
-- something to recv, recv enabled, recv hold reg empty
elsif r.ft245i.rxfn = '0' and r.rxen = '1' and r.rsempty = '1' then
v.rxtxstate := rdact;
v.cyclecnt := RDTODATA;
v.ft245o.oen := '1'; -- pad oen deact
v.ft245o.rdn := '0'; -- read enable
-- external send fifo not full, send enabled, send reg not empty
elsif r.ft245i.txen = '0' and r.txen = '1' and r.tsempty = '0' then
v.rxtxstate := wrdata;
v.cyclecnt := WRPULSE;
v.ft245o.wr := '1';
v.ft245o.oen := '0'; -- pad oen act
v.ft245o.wrdata := r.thold;
v.tsempty := '1';
if r.tirqen = '1' then
v.irq := '1';
end if;
end if;
when rdact =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rddata;
--rdn stays low
v.cyclecnt := RDPULSE;
end if;
when rddata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := rdwait;
v.rsempty := '0';
if r.rirqen = '1' then
v.irq := '1'; -- irq if enabled
end if;
v.rhold := r.ft245i.rddata;
if r.ft245i.rddata = "00000000" then
v.break := '1';
end if;
v.ft245o.rdn := '1'; -- deactivate
v.cyclecnt := TIMEOUT;
end if;
when rdwait =>
v.cyclecnt := r.cyclecnt - 1;
-- value read or timeout
if v.ft245i.rxfn = '1' or v.cyclecnt = CYNULL then
v.rxtxstate := idle;
end if;
when wrdata =>
v.cyclecnt := r.cyclecnt - 1;
if v.cyclecnt = CYNULL then
v.rxtxstate := wrwait;
v.cyclecnt := TIMEOUT;
v.ft245o.wr := '0';
end if;
when wrwait =>
v.cyclecnt := r.cyclecnt - 1;
--either tx byte accepted or timeout
if r.ft245i.txen = '1' or r.cyclecnt = CYNULL then
v.rxtxstate := idle;
v.ft245o.oen := '1'; -- output pad deact
v.tsempty := '1';
end if;
end case;
-- reset if no power enable at ft245
if r.ft245i.pwrenn = '1' then
v.rxtxstate := idle;
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rsempty := '1'; v.tsempty := '1';
v.irq := '0';
end if;
-- reset operation
if rst = '0' then
v.rxen := '0'; v.txen := '0';
v.rirqen := '0'; v.tirqen := '0';
v.loopb := '0';
v.rsempty := '1'; v.tsempty := '1';
v.break := '0';
v.irq := '0';
v.ft245o.wrdata := (others => '0');
v.ft245o.oen := '1';
v.ft245o.rdn := '1';
v.ft245o.wr := '0';
v.rxtxstate := idle;
v.rhold := (others => '0');
v.thold := (others => '0');
v.cyclecnt := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
ft245o <= r.ft245o;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
r.ft245i <= ft245i;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": FT245 UART rev " & tost(REVISION) & ", no fifo " &
", irq " & tost(pirq));
-- pragma translate_on
end;
|
-- Projeto gerado via script.
-- Data: Sáb,31/12/2011-01:19:07
-- Autor: rogerio
-- Comentario: Descrição da Entidade: nor2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nor2 is
port (a, b: in std_logic; y: out std_logic);
end nor2;
architecture logica of nor2 is
begin
-- Comandos.
y <= a nor b;
end logica;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
-- pragma translate_off
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
-- pragma translate_on
package StdIO is
-- pragma translate_off
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
-- pragma translate_on
end package StdIO;
package body StdIO is
-- pragma translate_off
function ToChar(N: Std_ULogic_Vector(0 to 3)) return Character is
begin
case N is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('A');
when "1011" => return('B');
when "1100" => return('C');
when "1101" => return('D');
when "1110" => return('E');
when "1111" => return('F');
when others => return('X');
end case;
end ToChar;
function FromChar(C: Character) return Std_ULogic_Vector is
variable R: Std_ULogic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean) is
variable B: Boolean;
variable C: Character;
constant SL: Integer := VALUE'Length;
variable SV: Std_ULogic_Vector(0 to SL-1);
variable S: String(1 to SL/4-1);
begin
if VALUE'Length mod 4 /= 0 then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
loop
Read(L, C, B);
exit when ((C /= ' ') and (C /= CR) and (C /= HT)) or (not B);
end loop;
SV(0 to 3) := FromChar(C);
if Is_X(SV(0 to 3)) or (not B) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
Read(L, S, B);
if not B then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
for i in 1 to SL/4-1 loop
SV(4*i to 4*i+3) := FromChar(S(i));
if Is_X(SV(4*i to 4*i+3)) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
end loop;
GOOD := True;
VALUE := SV;
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector) is
variable GOOD: Boolean;
begin
HRead(L, VALUE, GOOD);
assert GOOD
report "HREAD: access incorrect";
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean) is
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
assert GOOD
report "HREAD: access incorrect";
end HRead;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
constant PL: Integer := 4-(VALUE'Length mod 4);
constant PV: Std_ULogic_Vector(1 to PL) := (others => '0');
constant TL: Integer := PL + VALUE'Length;
constant TV: Std_ULogic_Vector(0 to TL-1) := PV & Value;
variable S: String(1 to TL/4);
begin
if PL /= 4 then
for i in 0 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(1 to TL/4), JUSTIFIED, FIELD);
else
for i in 1 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(2 to TL/4), JUSTIFIED, FIELD);
end if;
end HWrite;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
begin
HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
end HWrite;
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
type Char_Array is array (Std_ULogic) of Character;
constant ToChar: Char_Array := "UX01ZWLH-";
begin
Write(L, ToChar(VALUE), JUSTIFIED, FIELD);
end Write;
-- pragma translate_on
end package body StdIO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
-- pragma translate_off
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
-- pragma translate_on
package StdIO is
-- pragma translate_off
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
-- pragma translate_on
end package StdIO;
package body StdIO is
-- pragma translate_off
function ToChar(N: Std_ULogic_Vector(0 to 3)) return Character is
begin
case N is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('A');
when "1011" => return('B');
when "1100" => return('C');
when "1101" => return('D');
when "1110" => return('E');
when "1111" => return('F');
when others => return('X');
end case;
end ToChar;
function FromChar(C: Character) return Std_ULogic_Vector is
variable R: Std_ULogic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean) is
variable B: Boolean;
variable C: Character;
constant SL: Integer := VALUE'Length;
variable SV: Std_ULogic_Vector(0 to SL-1);
variable S: String(1 to SL/4-1);
begin
if VALUE'Length mod 4 /= 0 then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
loop
Read(L, C, B);
exit when ((C /= ' ') and (C /= CR) and (C /= HT)) or (not B);
end loop;
SV(0 to 3) := FromChar(C);
if Is_X(SV(0 to 3)) or (not B) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
Read(L, S, B);
if not B then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
for i in 1 to SL/4-1 loop
SV(4*i to 4*i+3) := FromChar(S(i));
if Is_X(SV(4*i to 4*i+3)) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
end loop;
GOOD := True;
VALUE := SV;
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector) is
variable GOOD: Boolean;
begin
HRead(L, VALUE, GOOD);
assert GOOD
report "HREAD: access incorrect";
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean) is
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
assert GOOD
report "HREAD: access incorrect";
end HRead;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
constant PL: Integer := 4-(VALUE'Length mod 4);
constant PV: Std_ULogic_Vector(1 to PL) := (others => '0');
constant TL: Integer := PL + VALUE'Length;
constant TV: Std_ULogic_Vector(0 to TL-1) := PV & Value;
variable S: String(1 to TL/4);
begin
if PL /= 4 then
for i in 0 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(1 to TL/4), JUSTIFIED, FIELD);
else
for i in 1 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(2 to TL/4), JUSTIFIED, FIELD);
end if;
end HWrite;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
begin
HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
end HWrite;
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
type Char_Array is array (Std_ULogic) of Character;
constant ToChar: Char_Array := "UX01ZWLH-";
begin
Write(L, ToChar(VALUE), JUSTIFIED, FIELD);
end Write;
-- pragma translate_on
end package body StdIO;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1216.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n02i01216ent IS
END c08s01b00x00p26n02i01216ent;
ARCHITECTURE c08s01b00x00p26n02i01216arch OF c08s01b00x00p26n02i01216ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
BEGIN
-- First, wait for 1fs;
wait for 1 fs;
assert FALSE
report "***PASSED TEST: c08s01b00x00p26n02i01216 - This test needs manual check. Assertion Failure Note should not appear."
severity NOTE;
-- Then, wait until the end of time.
wait;
assert (FALSE)
report "Should never have executed this statement."
severity FAILURE;
END PROCESS TESTING;
END c08s01b00x00p26n02i01216arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1216.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n02i01216ent IS
END c08s01b00x00p26n02i01216ent;
ARCHITECTURE c08s01b00x00p26n02i01216arch OF c08s01b00x00p26n02i01216ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
BEGIN
-- First, wait for 1fs;
wait for 1 fs;
assert FALSE
report "***PASSED TEST: c08s01b00x00p26n02i01216 - This test needs manual check. Assertion Failure Note should not appear."
severity NOTE;
-- Then, wait until the end of time.
wait;
assert (FALSE)
report "Should never have executed this statement."
severity FAILURE;
END PROCESS TESTING;
END c08s01b00x00p26n02i01216arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1216.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n02i01216ent IS
END c08s01b00x00p26n02i01216ent;
ARCHITECTURE c08s01b00x00p26n02i01216arch OF c08s01b00x00p26n02i01216ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
BEGIN
-- First, wait for 1fs;
wait for 1 fs;
assert FALSE
report "***PASSED TEST: c08s01b00x00p26n02i01216 - This test needs manual check. Assertion Failure Note should not appear."
severity NOTE;
-- Then, wait until the end of time.
wait;
assert (FALSE)
report "Should never have executed this statement."
severity FAILURE;
END PROCESS TESTING;
END c08s01b00x00p26n02i01216arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dmul_64ns_64ns_64_6_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dmul_64ns_64ns_64_6_max_dsp is
--------------------- Component ---------------------
component feedforward_ap_dmul_4_max_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dmul_4_max_dsp_64_u : component feedforward_ap_dmul_4_max_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dmul_64ns_64ns_64_6_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dmul_64ns_64ns_64_6_max_dsp is
--------------------- Component ---------------------
component feedforward_ap_dmul_4_max_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dmul_4_max_dsp_64_u : component feedforward_ap_dmul_4_max_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : project top file
-- Project :
-------------------------------------------------------------------------------
-- File : matrizled.vhd
-- Author : Pedro Messias Jose da Cunha Bastos
-- Company :
-- Created : 2015-04-28
-- Last update : 2015-04-29
-- Target Device :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-28 1.0 Ordep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity matrizled is
port (
sysclk : in std_logic;
reset_n : in std_logic;
data_i : in std_logic_vector(17 downto 0);
serial_o : out std_logic;
clk_o : out std_logic;
stb_o : out std_logic);
end entity matrizled;
architecture matrizled_rtl of matrizled is
signal sel_int : std_logic_vector(4 downto 0);
signal enable_int : std_logic;
begin -- architecture matrizled_rtl
multiplexer_inst1 : entity work.multiplexer
generic map (
N_INPUTS => 18)
port map (
data_32_i => data_i,
sel_i => sel_int,
out_o => serial_o);
clk_divider_inst1 : entity work.clk_divider
generic map (
MAX_VALUE => 20)
port map (
sysclk => sysclk,
reset_n => reset_n,
clk_divider_o => enable_int);
interface_inst1 : entity work.interface
generic map (
MAX_VALUE => 18,
MAX_VALUE_BITS => 5)
port map (
sysclk => sysclk,
reset_n => reset_n,
en_i => enable_int,
ctrl_o => sel_int,
stb_o => stb_o,
clk => clk_o);
end architecture matrizled_rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils.all;
entity sync is
port (
clk : in std_logic;
en : in std_logic;
hsync : out std_logic := '1';
vsync : out std_logic := '1';
retracing : out std_logic := '1'; -- maybe we don't need this?
-- Dunno why, but if I zero-initialize these, the very first pixel is black in the bitmap_tb
col : out std_logic_vector (9 downto 0) := (others => '1'); -- 640 = 10_1000_0000b
row : out std_logic_vector (8 downto 0) := (others => '1') -- 480 = 1_1110_0000b
);
end entity sync;
architecture behavioral of sync is
constant h_display : natural := 640;
constant h_front : natural := 20;
constant h_sync : natural := 96;
constant h_back : natural := 44;
constant h_retrace : natural := h_front + h_sync + h_back;
constant h_max : natural := h_retrace + h_display - 1;
constant v_display : natural := 480;
constant v_front : natural := 14;
constant v_sync : natural := 1;
constant v_back : natural := 30;
constant v_retrace : natural := v_front + v_sync + v_back;
constant v_max : natural := v_retrace + v_display - 1;
begin
process(en, clk)
variable h_idx: integer range 0 to h_max := 0;
variable v_idx: integer range 0 to v_max := 0;
variable in_retrace : boolean := true;
begin
if rising_edge(clk) and en = '1' then
if h_idx >= h_max - h_sync then hsync <= '0'; end if;
if v_idx >= v_max - v_sync then vsync <= '0'; end if;
in_retrace := h_idx < h_back - 1 or h_idx > h_display + h_back - 2
or v_idx < v_back or v_idx > v_display + v_back - 1;
retracing <= high_if (in_retrace);
if not in_retrace then
row <= std_logic_vector(to_unsigned(v_idx - v_back, row'length));
col <= std_logic_vector(to_unsigned(h_idx - h_back + 1, col'length));
end if;
if h_idx = h_max then
h_idx := 0;
hsync <= '1';
if v_idx = v_max then
v_idx := 0;
vsync <= '1';
else
v_idx := v_idx + 1;
end if;
else
h_idx := h_idx + 1;
end if;
end if;
end process;
end architecture;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2961.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit;
FUNCTION boo ( PARM_VAL: bit_vector:="1010")RETURN bit_vector;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time;
end c02s03b00x00p02n01i02961pkg;
package body c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: bit_vector:="1010") RETURN bit_vector IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN PARM_VAL;
END;
end c02s03b00x00p02n01i02961pkg;
ENTITY c02s03b00x00p02n01i02961ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
END c02s03b00x00p02n01i02961ent;
use work.c02s03b00x00p02n01i02961pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02961arch OF c02s03b00x00p02n01i02961ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
bb <= boo;
bv <= boo;
bo <= boo;
cc <= boo;
ii <= boo;
rr <= boo;
ss <= boo;
tt <= boo;
WAIT FOR 1 ns;
assert NOT( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***PASSED TEST: c02s03b00x00p02n01i02961"
severity NOTE;
assert ( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***FAILED TEST: c02s03b00x00p02n01i02961 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02961arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2961.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit;
FUNCTION boo ( PARM_VAL: bit_vector:="1010")RETURN bit_vector;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time;
end c02s03b00x00p02n01i02961pkg;
package body c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: bit_vector:="1010") RETURN bit_vector IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN PARM_VAL;
END;
end c02s03b00x00p02n01i02961pkg;
ENTITY c02s03b00x00p02n01i02961ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
END c02s03b00x00p02n01i02961ent;
use work.c02s03b00x00p02n01i02961pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02961arch OF c02s03b00x00p02n01i02961ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
bb <= boo;
bv <= boo;
bo <= boo;
cc <= boo;
ii <= boo;
rr <= boo;
ss <= boo;
tt <= boo;
WAIT FOR 1 ns;
assert NOT( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***PASSED TEST: c02s03b00x00p02n01i02961"
severity NOTE;
assert ( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***FAILED TEST: c02s03b00x00p02n01i02961 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02961arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2961.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit;
FUNCTION boo ( PARM_VAL: bit_vector:="1010")RETURN bit_vector;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time;
end c02s03b00x00p02n01i02961pkg;
package body c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: bit_vector:="1010") RETURN bit_vector IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN PARM_VAL;
END;
end c02s03b00x00p02n01i02961pkg;
ENTITY c02s03b00x00p02n01i02961ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
END c02s03b00x00p02n01i02961ent;
use work.c02s03b00x00p02n01i02961pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02961arch OF c02s03b00x00p02n01i02961ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
bb <= boo;
bv <= boo;
bo <= boo;
cc <= boo;
ii <= boo;
rr <= boo;
ss <= boo;
tt <= boo;
WAIT FOR 1 ns;
assert NOT( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***PASSED TEST: c02s03b00x00p02n01i02961"
severity NOTE;
assert ( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***FAILED TEST: c02s03b00x00p02n01i02961 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02961arch;
|
architecture RTL of FIFO is
begin
process
begin
z <= a;
if a then
a <= b;
if b then
b <= c;
if c then
c <= d;
end if;
end if;
end if;
-- Comment
if a then
a <= b;
if b then
b <= c;
if c then
c <= d;
end if;
end if;
end if;
-- Violations below
z <= a;
if a then
a <= b;
if b then
b <= c;
if c then
c <= d;
end if;
end if;
end if;
end process;
end architecture RTL;
|
--Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux2 is
port(
bus0 : in std_logic_vector(3 downto 0);
bus1 : in std_logic_vector(3 downto 0);
S : in std_logic;
R : out std_logic_vector(3 downto 0)
);
end mux2;
architecture Behavioural of mux2 is
begin
with S select
R <= bus0 when '0',
bus1 when others;
end Behavioural;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
IO_RD_EN : inout std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
WR_EN : in std_logic;
DATA : out std_logic_vector(31 downto 0);
RD_EN : inout std_logic;
DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
IO_RD_EN : inout std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
WR_EN : in std_logic;
DATA : out std_logic_vector(31 downto 0);
RD_EN : inout std_logic;
DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:39:42 03/11/2014
-- Design Name:
-- Module Name: UARTController - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTController is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
w_data : in STD_LOGIC_VECTOR (7 downto 0);
w_start : in STD_LOGIC;
tx : out STD_LOGIC;
w_done : out STD_LOGIC;
r_data : out STD_LOGIC_VECTOR (7 downto 0);
r_done : out STD_LOGIC);
end UARTController;
architecture Behavioral of UARTController is
component BaudRateGenerator port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC
);
end component;
component UARTReciever port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
rx : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0);
rx_done : out STD_LOGIC);
end component;
component UARTTransmitter port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : in STD_LOGIC;
d_in : in STD_LOGIC_VECTOR (7 downto 0);
tx_start : in STD_LOGIC;
tx_done : out STD_LOGIC;
tx : out STD_LOGIC);
end component;
signal tick : std_logic;
begin
BRG: entity work.BaudRateGenerator port map (clk => clk,rst => rst,tick => tick);
URx: entity work.UARTReciever port map (clk => clk, rst => rst, tick => tick, rx => rx, d_out => r_data, rx_done => r_done);
UTx: entity work.UARTTransmitter port map (clk => clk, rst => rst, tick => tick, d_in => w_data, tx_start => w_start, tx_done => w_done, tx => tx);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:46 02/24/2015
-- Design Name:
-- Module Name: rc_shr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(71 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end rc_shr;
architecture Behavioral of rc_shr is
signal sh_reg : std_logic_vector(71 downto 0);
begin
pr_shr: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
sh_reg <= rc_in;
else
sh_reg <= sh_reg(63 downto 0) & sh_reg(71 downto 64);
end if;
end if;
end process;
rc_out <= sh_reg(71 downto 64);
end Behavioral;
|
-- NEED RESULT: *** There should be two default assertion messages output
-- NEED RESULT: Assertion Violation.
-- NEED RESULT: Assertion Violation.
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00321
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (1)
-- 9.4 (2)
-- 9.4 (3)
-- 9.4 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00321_Test_Bench(ARCH00321_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00321_Test_Bench is
end ENT00321_Test_Bench ;
architecture ARCH00321_Test_Bench of ENT00321_Test_Bench is
begin
process
begin
print ( "*** There should be two default assertion messages output" ) ;
wait ;
end process ;
L : assert False severity Note ; -- Assertion with a label
assert False severity Note ; -- Assertion without a label;
end ARCH00321_Test_Bench ;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY fsqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END fsqrt;
ARCHITECTURE fsqrt_arch OF fsqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fsqrt_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 1,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END fsqrt_arch;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Synth RAM
-- Module Name: Synth RAM
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a synthesizable RAM.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the synthesizable RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the synthesizable RAM.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity synth_ram is
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end synth_ram;
architecture Behavioral of synth_ram is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rw = '1' then
memory_ram(to_integer(unsigned(address))) <= data_in((ram_word_size - 1) downto (0));
end if;
data_out((ram_word_size - 1) downto (0)) <= memory_ram(to_integer(unsigned(address)));
end if;
end process;
end Behavioral; |
-- file: standard_soc_assoc.vhd
-- description: standard SoC with peripherals and external blocks
-- date: 09/2019
-- author: Sergio Johann Filho <sergio.filho@pucrs.br>
--
-- Standard SoC configuration template for prototyping. Dual GPIO ports,
-- a counter, a timer, dual UARTs and dual SPIs are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0);
-- MAC Sync I/O space: 0xe0ff4000 - 0xe0ff43ff
sync_mac_i: in std_logic_vector(31 downto 0);
sync_mac_o: out std_logic_vector(31 downto 0);
sync_mac_en_o: out std_logic;
sync_mac_rst_o: out std_logic;
-- MAC Async I/O space: 0xe0ff4400 - 0xe0ff47ff
async_mac_i: in std_logic_vector(31 downto 0);
async_mac_o: out std_logic_vector(31 downto 0);
async_mac_en_o: out std_logic;
async_mac_rst_o: out std_logic;
-- Delay line I/O space: 0xe0ff4800 - 0xe0ff4bff
de_pause_o: out std_logic_vector(1 downto 0);
de_config_o: out std_logic_vector(4 downto 0);
de_cde_sel_o: out std_logic_vector(3 downto 0);
de_mde_sel_l_o: out std_logic_vector(3 downto 0);
de_mde_sel_b_o: out std_logic_vector(3 downto 0);
de_cde_ctrl_o: out std_logic_vector(15 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal s0cause: std_logic_vector(4 downto 0);
signal gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(15 downto 0);
signal pbddr, pbout, pbin, pbin_inv, pbin_mask: std_logic_vector(15 downto 0);
signal paaltcfg0: std_logic_vector(31 downto 0);
signal paalt: std_logic_vector(15 downto 0);
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_gpiob, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_uart: std_logic;
signal uartcause, uartcause_inv, uartmask: std_logic_vector(3 downto 0);
signal uart0_tx, uart0_rx, uart0_enable_w, uart0_enable_r, uart0_write_busy, uart0_data_avail: std_logic;
signal uart0_data_read, uart0_data_write: std_logic_vector(7 downto 0);
signal uart0_divisor: std_logic_vector(15 downto 0);
signal uart1_tx, uart1_rx, uart1_enable_w, uart1_enable_r, uart1_write_busy, uart1_data_avail: std_logic;
signal uart1_data_read, uart1_data_write: std_logic_vector(7 downto 0);
signal uart1_divisor: std_logic_vector(15 downto 0);
signal int_spi: std_logic;
signal spicause, spicause_inv, spimask: std_logic_vector(3 downto 0);
signal spi0_data_write, spi0_data_read: std_logic_vector(7 downto 0);
signal spi0_clk_div: std_logic_vector(8 downto 0);
signal spi0_data_valid, spi0_data_xfer, spi0_ssn, spi0_clk_i, spi0_clk_o, spi0_do, spi0_di: std_logic;
signal spi1_data_write, spi1_data_read: std_logic_vector(7 downto 0);
signal spi1_clk_div: std_logic_vector(8 downto 0);
signal spi1_data_valid, spi1_data_xfer, spi1_ssn, spi1_clk_i, spi1_clk_o, spi1_do, spi1_di: std_logic;
signal async_mac_en_r, async_mac_rst_r, sync_mac_en_r, sync_mac_rst_r: std_logic;
signal async_mac_r, sync_mac_r: std_logic_vector(31 downto 0);
signal de_pause_r: std_logic_vector(1 downto 0);
signal de_config_r: std_logic_vector(4 downto 0);
signal de_cde_sel_r: std_logic_vector(3 downto 0);
signal de_mde_sel_l_r, de_mde_sel_b_r: std_logic_vector(3 downto 0);
signal de_cde_ctrl_r: std_logic_vector(15 downto 0);
signal de_cde_ctrl_we_r: std_logic;
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "00000" else '0';
s0cause <= int_spi & int_uart & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "00" & int_gpiob & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_gpiob <= '1' when ((pbin xor pbin_inv) and pbin_mask) /= "0000" else '0';
pain <= gpioa_in(15 downto 0);
gpioa_out <= paalt;
gpioa_ddr <= paddr;
pbin <= gpiob_in(15 downto 0);
gpiob_out <= pbout;
gpiob_ddr <= pbddr;
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
int_uart <= '1' when ((uartcause xor uartcause_inv) and uartmask) /= "0000" else '0';
uartcause <= uart1_write_busy & uart1_data_avail & uart0_write_busy & uart0_data_avail;
int_spi <= '1' when ((spicause xor spicause_inv) and spimask) /= "0000" else '0';
spicause <= "00" & spi1_data_valid & spi0_data_valid;
-- PORT A alternate config MUXes for outputs
paalt(0) <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
paalt(1) <= spi1_clk_o when paaltcfg0(3 downto 2) = "11" else paout(1);
paalt(2) <= uart0_tx when paaltcfg0(5 downto 4) = "01" else spi1_do when paaltcfg0(5 downto 4) = "11" else paout(2);
paalt(3) <= spi1_do when paaltcfg0(7 downto 6) = "11" else paout(3);
paalt(4) <= uart1_tx when paaltcfg0(9 downto 8) = "01" else paout(4);
paalt(5) <= spi0_clk_o when paaltcfg0(11 downto 10) = "10" else paout(5);
paalt(6) <= spi0_do when paaltcfg0(13 downto 12) = "10" else paout(6);
paalt(7) <= spi0_do when paaltcfg0(15 downto 14) = "10" else paout(7);
paalt(8) <= int_timer1_ctc when paaltcfg0(17 downto 16) = "01" else int_timer1_ocr when paaltcfg0(17 downto 16) = "10" else paout(8);
paalt(9) <= spi1_clk_o when paaltcfg0(19 downto 18) = "11" else paout(9);
paalt(10) <= uart0_tx when paaltcfg0(21 downto 20) = "01" else spi1_do when paaltcfg0(21 downto 20) = "11" else paout(10);
paalt(11) <= spi1_do when paaltcfg0(23 downto 22) = "11" else paout(11);
paalt(12) <= uart1_tx when paaltcfg0(25 downto 24) = "01" else paout(12);
paalt(13) <= spi0_clk_o when paaltcfg0(27 downto 26) = "10" else paout(13);
paalt(14) <= spi0_do when paaltcfg0(29 downto 28) = "10" else paout(14);
paalt(15) <= spi0_do when paaltcfg0(31 downto 30) = "10" else paout(15);
-- PORT A alternate config MUXes for inputs
uart0_rx <= pain(3) when paaltcfg0(7 downto 6) = "01" else pain(11) when paaltcfg0(23 downto 22) = "01" else '1';
uart1_rx <= pain(5) when paaltcfg0(11 downto 10) = "01" else pain(13) when paaltcfg0(27 downto 26) = "01" else '1';
spi0_ssn <= pain(4) when paaltcfg0(9 downto 8) = "10" else pain(12) when paaltcfg0(25 downto 24) = "10" else '1';
spi0_clk_i <= pain(5) when paaltcfg0(11 downto 10) = "10" else pain(13) when paaltcfg0(27 downto 26) = "10" else '0';
spi0_di <= pain(6) when paaltcfg0(13 downto 12) = "10" else pain(14) when paaltcfg0(29 downto 28) = "10" else
pain(7) when paaltcfg0(15 downto 14) = "10" else pain(15) when paaltcfg0(31 downto 30) = "10" else '0';
spi1_ssn <= pain(0) when paaltcfg0(1 downto 0) = "11" else pain(8) when paaltcfg0(17 downto 16) = "11" else '1';
spi1_clk_i <= pain(1) when paaltcfg0(3 downto 2) = "11" else pain(9) when paaltcfg0(19 downto 18) = "11" else '0';
spi1_di <= pain(2) when paaltcfg0(5 downto 4) = "11" else pain(10) when paaltcfg0(21 downto 20) = "11" else
pain(3) when paaltcfg0(7 downto 6) = "11" else pain(11) when paaltcfg0(23 downto 22) = "11" else '0';
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
uart0_enable_r <= '0';
uart1_enable_r <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0000" => -- Segment Reserved
case class is
when "1111" =>
case device is
when "010000" => -- MAC Sync I/O space: 0xe0ff4000 - 0xe0ff43ff
case funct is
when "0000" => -- 0xe0ff4000 (RW)
data_o <= sync_mac_r;
when "0001" => -- 0xe0ff4010 (RO)
data_o <= sync_mac_i;
when "0010" => -- 0xe0ff4020 (RW)
data_o <= x"0000000" & "000" & sync_mac_rst_r;
when others =>
end case;
when "010001" => -- MAC Async I/O space: 0xe0ff4400 - 0xe0ff47ff
case funct is
when "0000" => -- 0xe0ff4400 (RW)
data_o <= async_mac_r;
when "0001" => -- 0xe0ff4410 (RO)
data_o <= async_mac_i;
when "0010" => -- 0xe0ff4420 (RW)
data_o <= x"0000000" & "000" & async_mac_rst_r;
when others =>
end case;
when "010010" => -- Delay line I/O space: 0xe0ff4800 - 0xe0ff4bff
case funct is
when "0000" => -- 0xe0ff4800 (RW)
data_o <= x"000000" & "000" & de_config_r;
when "0001" => -- 0xe0ff4810 (RW)
data_o <= x"0000000" & de_cde_sel_r;
when "0010" => -- 0xe0ff4820 (RW)
data_o <= x"0000000" & de_mde_sel_l_r;
when "0011" => -- 0xe0ff4830 (RW)
data_o <= x"0000000" & de_mde_sel_b_r;
when "0100" => -- 0xe0ff4840 (RW)
data_o <= x"0000" & de_cde_ctrl_r;
when "0101" => -- 0xe0ff4850 (RW)
data_o <= x"0000000" & "00" & de_pause_r;
when others =>
end case;
when others =>
end case;
when others =>
end case;
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"000000" & "000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"0000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"0000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"0000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"0000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"0000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
data_o <= x"0000" & pbddr;
when "0001" => -- PBOUT (RW)
data_o <= x"0000" & pbout;
when "0010" => -- PBIN (RO)
data_o <= x"0000" & pbin;
when "0011" => -- PBIN_INV (RW)
data_o <= x"0000" & pbin_inv;
when "0100" => -- PBIN_MASK (RW)
data_o <= x"0000" & pbin_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0011" => -- UARTs
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & uartcause;
when "000010" => -- UARTCAUSE_INV (RW)
data_o <= x"0000000" & uartcause_inv;
when "000011" => -- UARTMASK (RW)
data_o <= x"0000000" & uartmask;
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
data_o <= x"000000" & uart0_data_read;
uart0_enable_r <= '1';
when "0001" => -- UART0DIV (RW)
data_o <= x"0000" & uart0_divisor;
when others =>
end case;
when "010001" => -- UART1
case funct is
when "0000" => -- UART1 (RW)
data_o <= x"000000" & uart1_data_read;
uart1_enable_r <= '1';
when "0001" => -- UART1DIV (RW)
data_o <= x"0000" & uart1_divisor;
when others =>
end case;
when others =>
end case;
when "0100" => -- SPIs
case device is
when "000001" => -- SPICAUSE (RO)
data_o <= x"0000000" & spicause;
when "000010" => -- SPICAUSE_INV (RW)
data_o <= x"0000000" & spicause_inv;
when "000011" => -- SPIMASK (RW)
data_o <= x"0000000" & spimask;
when "010000" => -- SPI0
case funct is
when "0000" => -- SPI0 (RW)
data_o <= x"000000" & spi0_data_read;
when "0001" => -- SPI0CTRL (RW)
data_o <= x"0000" & "0000" & spi0_clk_div & "0" & spi0_data_valid & spi0_data_xfer;
when others =>
end case;
when "010001" => -- SPI1
case funct is
when "0000" => -- SPI1 (RW)
data_o <= x"000000" & spi1_data_read;
when "0001" => -- SPI1CTRL (RW)
data_o <= x"0000" & "0000" & spi1_clk_div & "0" & spi1_data_valid & spi1_data_xfer;
when others =>
end case;
when others =>
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
else
uart0_enable_r <= '0';
uart1_enable_r <= '0';
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
pbout <= (others => '0');
pbin_inv <= (others => '0');
pbin_mask <= (others => '0');
pbddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
uartcause_inv <= (others => '0');
uartmask <= (others => '0');
uart0_enable_w <= '0';
uart0_data_write <= (others => '0');
uart0_divisor <= (others => '0');
uart1_enable_w <= '0';
uart1_data_write <= (others => '0');
uart1_divisor <= (others => '0');
spicause_inv <= (others => '0');
spimask <= (others => '0');
spi0_data_write <= (others => '0');
spi0_data_xfer <= '0';
spi0_clk_div <= (others => '0');
spi1_data_write <= (others => '0');
spi1_data_xfer <= '0';
spi1_clk_div <= (others => '0');
sync_mac_en_r <= '0';
sync_mac_rst_r <= '1';
sync_mac_r <= (others => '0');
async_mac_en_r <= '0';
async_mac_rst_r <= '1';
async_mac_r <= (others => '0');
de_pause_r <= (others => '1');
de_config_r <= (others => '0');
de_cde_sel_r <= (others => '1');
de_mde_sel_l_r <= (others => '1');
de_mde_sel_b_r <= (others => '0');
de_cde_ctrl_r <= x"0001";
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0000" => -- Segment Reserved
case class is
when "1111" =>
case device is
when "010000" => -- MAC Sync I/O space: 0xe0ff4000 - 0xe0ff43ff
case funct is
when "0000" => -- 0xe0ff4000 (RW)
sync_mac_r <= data_i;
sync_mac_en_r <= '1';
-- when "0001" => -- 0xe0ff4010 (RO)
when "0010" => -- 0xe0ff4020 (RW)
sync_mac_rst_r <= data_i(0);
when others =>
end case;
when "010001" => -- MAC Async I/O space: 0xe0ff4400 - 0xe0ff47ff
case funct is
when "0000" => -- 0xe0ff4400 (RW)
async_mac_r <= data_i;
async_mac_en_r <= '1';
-- when "0001" => -- 0xe0ff4410 (RO)
when "0010" => -- 0xe0ff4420 (RW)
async_mac_rst_r <= data_i(0);
when others =>
end case;
when "010010" => -- Delay line I/O space: 0xe0ff4800 - 0xe0ff4bff
case funct is
when "0000" => -- 0xe0ff4800 (RW)
if (de_pause_r = "11") then
de_config_r <= data_i(4 downto 0);
end if;
when "0001" => -- 0xe0ff4810 (RW)
if (de_pause_r(1) = '1') then
de_cde_sel_r <= data_i(3 downto 0);
end if;
when "0010" => -- 0xe0ff4820 (RW)
if (de_pause_r(0) = '1') then
de_mde_sel_l_r <= data_i(3 downto 0);
end if;
when "0011" => -- 0xe0ff4830 (RW)
if (de_pause_r(0) = '1') then
de_mde_sel_b_r <= data_i(3 downto 0);
end if;
when "0100" => -- 0xe0ff4840 (RW)
if (de_pause_r(1) = '1') then
de_cde_ctrl_r <= data_i(15 downto 0);
end if;
when "0101" => -- 0xe0ff4850 (RW)
de_pause_r <= data_i(1 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(31 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(15 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(15 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(15 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
pbddr <= data_i(15 downto 0);
when "0001" => -- PBOUT (RW)
pbout <= data_i(15 downto 0);
when "0011" => -- PBIN_INV (RW)
pbin_inv <= data_i(15 downto 0);
when "0100" => -- PBIN_MASK (RW)
pbin_mask <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0011" => -- UARTs
case device is
when "000010" => -- UARTCAUSE_INV (RW)
uartcause_inv <= data_i(3 downto 0);
when "000011" => -- UARTMASK (RW)
uartmask <= data_i(3 downto 0);
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
uart0_data_write <= data_i(7 downto 0);
uart0_enable_w <= '1';
when "0001" => -- UART0DIV (RW)
uart0_divisor <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- UART1
case funct is
when "0000" => -- UART1 (RW)
uart1_data_write <= data_i(7 downto 0);
uart1_enable_w <= '1';
when "0001" => -- UART1DIV (RW)
uart1_divisor <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0100" => -- SPIs
case device is
when "000010" => -- SPICAUSE_INV (RW)
spicause_inv <= data_i(3 downto 0);
when "000011" => -- SPIMASK (RW)
spimask <= data_i(3 downto 0);
when "010000" => -- SPI0
case funct is
when "0000" => -- SPI0 (RW)
spi0_data_write <= data_i(7 downto 0);
spi0_data_xfer <= '1';
when "0001" => -- SPI0CTRL (RW)
spi0_data_xfer <= data_i(0);
spi0_clk_div <= data_i(11 downto 3);
when others =>
end case;
when "010001" => -- SPI1
case funct is
when "0000" => -- SPI1 (RW)
spi1_data_write <= data_i(7 downto 0);
spi1_data_xfer <= '1';
when "0001" => -- SPI1CTRL (RW)
spi1_data_xfer <= data_i(0);
spi1_clk_div <= data_i(11 downto 3);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
else
uart0_enable_w <= '0';
uart1_enable_w <= '0';
async_mac_en_r <= '0';
sync_mac_en_r <= '0';
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
uart0: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart0_divisor(11 downto 0),
enable_read => uart0_enable_r,
enable_write => uart0_enable_w,
data_in => uart0_data_write,
data_out => uart0_data_read,
uart_read => uart0_rx,
uart_write => uart0_tx,
busy_write => uart0_write_busy,
data_avail => uart0_data_avail
);
uart1: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart1_divisor(11 downto 0),
enable_read => uart1_enable_r,
enable_write => uart1_enable_w,
data_in => uart1_data_write,
data_out => uart1_data_read,
uart_read => uart1_rx,
uart_write => uart1_tx,
busy_write => uart1_write_busy,
data_avail => uart1_data_avail
);
spi0: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => spi0_data_write,
data_o => spi0_data_read,
data_valid_o => spi0_data_valid,
wren_i => spi0_data_xfer,
clk_div_i => spi0_clk_div,
spi_ssn_i => spi0_ssn,
spi_clk_i => spi0_clk_i,
spi_clk_o => spi0_clk_o,
spi_do_o => spi0_do,
spi_di_i => spi0_di
);
spi1: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => spi1_data_write,
data_o => spi1_data_read,
data_valid_o => spi1_data_valid,
wren_i => spi1_data_xfer,
clk_div_i => spi1_clk_div,
spi_ssn_i => spi1_ssn,
spi_clk_i => spi1_clk_i,
spi_clk_o => spi1_clk_o,
spi_do_o => spi1_do,
spi_di_i => spi1_di
);
sync_mac_en_o <= sync_mac_en_r;
sync_mac_rst_o <= sync_mac_rst_r;
sync_mac_o <= sync_mac_r;
async_mac_en_o <= async_mac_en_r;
async_mac_rst_o <= async_mac_rst_r;
async_mac_o <= async_mac_r;
de_pause_o <= de_pause_r;
de_config_o <= de_config_r;
de_cde_sel_o <= de_cde_sel_r;
de_mde_sel_l_o <= de_mde_sel_l_r;
de_mde_sel_b_o <= de_mde_sel_b_r;
de_cde_ctrl_o <= de_cde_ctrl_r;
end peripherals_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY binaryto4hex IS
PORT (
binary : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
output0, output1, output2, output3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END binaryto4hex;
ARCHITECTURE Behavioural OF binaryto4hex IS
COMPONENT binary_to_sevenSeg
PORT (
binary_value : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sevenSeg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
BEGIN
bintoseg1 : binary_to_sevenSeg
PORT MAP(
binary_value => binary(15 DOWNTO 12),
sevenSeg => output3
);
bintoseg2 : binary_to_sevenSeg
PORT MAP(
binary_value => binary(11 DOWNTO 8),
sevenSeg => output2
);
bintoseg3 : binary_to_sevenSeg
PORT MAP(
binary_value => binary(7 DOWNTO 4),
sevenSeg => output1
);
bintoseg4 : binary_to_sevenSeg
PORT MAP(
binary_value => binary(3 DOWNTO 0),
sevenSeg => output0
);
END Behavioural; |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: gudilkoalex@gmail.com
--
-- File: Pendant_decoder_testbench.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- Testbench for UART pendant decoder
--
-- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Pendant_decoder_testbench is
end Pendant_decoder_testbench;
architecture behavioral of Pendant_decoder_testbench is
constant SYSCLK_PERIOD : time := 20 ns; -- 50MHZ
constant SYSCLK_LF_PERIOD : time := 100 ns; -- 10MHZ
constant SYSCLK_Khz_PERIOD : time := 0.256 us; -- 3900 Khz. REAL FREQ is 39 Khz (T=25.6 us)
signal SYSCLK : std_logic := '0';
signal SYSCLK_LF : std_logic := '0';
signal SYSCLK_Khz : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal s_UART_DATA1_IN : std_logic_vector (7 downto 0);
signal s_UART_DATA2_IN : std_logic_vector (7 downto 0);
signal s_UART_DATA_OUT : std_logic_vector (7 downto 0);
signal s_UART_Tx_Gate : std_logic;
signal s_UART_Write_mode : std_logic;
signal s_UART_DATA_OUT2 : std_logic_vector (7 downto 0);
signal s_UART_Tx_Gate2 : std_logic;
signal s_ACLR_UART_Rx_Out_N : std_logic;
signal s_Disp_axis_reg : std_logic_vector (23 downto 0);
signal s_Current_axis_reg : std_logic_vector (23 downto 0);
signal s_MODE_out : std_logic_vector (2 downto 0);
signal s_Mode_Ready_out : std_logic;
signal s_AXIS_out : std_logic_vector (3 downto 0);
signal s_Axis_Ready_out : std_logic;
signal s_LED_reg : std_logic_vector (23 downto 0);
signal s_Button_reg : std_logic_vector (23 downto 0);
signal s_Speed_reg : std_logic_vector (23 downto 0);
component PENDANT_DECODER
-- ports
port(
-- Inputs
RESET_N : in std_logic;
SCLK_IN : in std_logic;
SCLK_Khz_IN : in std_logic; -- External SCLK xx Khz
SCLK_LF_IN : in std_logic; -- External SCLK 10 Mhz
UART_DATA1_IN : in std_logic_vector(7 downto 0);
UART_DATA2_IN : in std_logic_vector(7 downto 0);
Disp_axis_reg : in std_logic_vector(23 downto 0); -- Data FROM PMAC (confirmation of axis and mode selection)
LED_reg : in std_logic_vector(23 downto 0); -- Data FROM PMAC (indicators on programmable LEDs)
sw1 : in std_logic;
sw2 : in std_logic;
-- Outputs
Current_axis_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
Speed_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
Button_reg : out std_logic_vector(23 downto 0); -- Data TO PMAC
UART_DATA_OUT : out std_logic_vector(7 downto 0);
UART_Tx_Gate : out std_logic; -- latch UART data in external Tx registers
UART_Write_mode : out std_logic;
UART_DATA_OUT2 : out std_logic_vector(7 downto 0); -- Data TO pendant (LED control)
UART_Tx_Gate2 : out std_logic; -- latch UART data in external Tx registers (LED control)
MODE_out : out std_logic_vector(2 downto 0);
Mode_Ready_out : out std_logic;
AXIS_out : out std_logic_vector(3 downto 0);
Axis_Ready_out : out std_logic;
ACLR_UART_Rx_Out_N : out std_logic; -- clear UART Rx reg (active low)
flag1 : out std_logic
-- Inouts
);
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
SYSCLK_LF <= not SYSCLK_LF after (SYSCLK_LF_PERIOD / 2.0 );
SYSCLK_Khz <= not SYSCLK_Khz after (SYSCLK_Khz_PERIOD / 2.0 );
-- Instantiate Unit Under Test: PENDANT_DECODER
PENDANT_DECODER_0 : PENDANT_DECODER
-- port map
port map(
-- Inputs
RESET_N => NSYSRESET,
SCLK_IN => SYSCLK,
SCLK_LF_IN => SYSCLK_LF,
SCLK_Khz_IN => SYSCLK_Khz,
UART_DATA1_IN => s_UART_DATA1_IN,
UART_DATA2_IN => s_UART_DATA2_IN,
Disp_axis_reg => s_Disp_axis_reg,
LED_reg => s_LED_reg,
sw1 => '0',
sw2 => '0',
-- Outputs
Current_axis_reg => s_Current_axis_reg,
Speed_reg => s_Speed_reg,
Button_reg => s_Button_reg,
UART_DATA_OUT => s_UART_DATA_OUT,
UART_Tx_Gate => s_UART_Tx_Gate,
UART_Write_mode => s_UART_Write_mode,
UART_DATA_OUT2 => s_UART_DATA_OUT2,
UART_Tx_Gate2 => s_UART_Tx_Gate2,
MODE_out => s_MODE_out,
Mode_Ready_out => s_Mode_Ready_out,
AXIS_out => s_Axis_out,
Axis_Ready_out => s_Axis_Ready_out,
ACLR_UART_Rx_Out_N => s_ACLR_UART_Rx_Out_N,
flag1 => open
-- Inouts
);
process
begin
-----------------
--Initialization
--Reset for 10 clk cycles
-----------------
s_UART_DATA1_IN <= (others => '0');
s_UART_DATA2_IN <= (others => '0');
s_Disp_axis_reg <= (others => '0');
s_LED_reg <= (others => '0');
--AXIS CHANGE
--------------------------------------
--send axis X code
wait for ( SYSCLK_PERIOD * 20 );
s_UART_DATA1_IN <= x"55"; -- axis X (1st part)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"16"; -- axis Y (2nd part) - wrong!
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"400000"; -- Y confirmation, FALSE
wait for ( SYSCLK_PERIOD * 3 );
s_Disp_axis_reg <= x"880000"; -- false confirmation, FALSE
wait for ( SYSCLK_PERIOD * 3 );
s_Disp_axis_reg <= x"800000"; -- X confirmation, TRUE
--------------------------------------
--send axis Y code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"56"; -- axis Y
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"16"; -- axis Y
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"400000"; -- Y confirmation, TRUE
-------------------------------------
--send axis X code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"800000"; -- X confirmation, TRUE
-------------------------------------
--send axis Y code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"56"; -- axis Y
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"16"; -- axis Y
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"400000"; -- Y confirmation, TRUE
-------------------------------------
--send axis Z code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"57"; -- axis Z
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"17"; -- axis Z
--emulate Axis change before confirmation
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 2 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"200000"; -- Z confirmation, TRUE
-------------------------------------
--send axis A4 code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"58"; -- axis 4
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"18"; -- axis 4
--emulate Axis change before confirmation
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate axis confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"800000"; -- X confirmation, FALSE
wait for ( SYSCLK_PERIOD * 4 );
s_Disp_axis_reg <= x"100000"; -- A4 confirmation, TRUE
-------------------------------------
--MODE CHANGE
--------------------------------------
--send mode MANU code
wait for ( SYSCLK_PERIOD * 15 );
s_UART_DATA1_IN <= x"52"; -- MANU
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"12"; -- MANU
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000002"; -- INC confirmation, FALSE
wait for ( SYSCLK_PERIOD * 4 );
s_Disp_axis_reg <= x"000001"; -- MANU confirmation, TRUE
--------------------------------------
--send mode INC code
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"53"; -- INC
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"13"; -- INC
--emulate Axis change before confirmation
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"55"; -- axis X
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"15"; -- axis X
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000002"; -- INC confirmation, TRUE
--send mode HPG code
wait for ( SYSCLK_PERIOD * 7 );
s_UART_DATA1_IN <= x"54"; -- HPG
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"14"; -- HPG
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000004"; -- HPG confirmation, TRUE
--send mode MANU code
wait for ( SYSCLK_PERIOD * 7 );
s_UART_DATA1_IN <= x"52"; -- MANU
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"12"; -- MANU
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000001"; -- MANU confirmation, TRUE
--send mode INC code
wait for ( SYSCLK_PERIOD * 7 );
s_UART_DATA1_IN <= x"53"; -- INC
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"13"; -- INC
-- emulate mode confirmation
wait for ( SYSCLK_PERIOD * 8 );
s_Disp_axis_reg <= x"000002"; -- INC confirmation, TRUE
--------------------------------------
wait for ( SYSCLK_PERIOD * 30 );
-------------------------------------
--BUTTONS press
--------------------------------------
--press F1
wait for ( SYSCLK_PERIOD * 50 );
s_UART_DATA1_IN <= x"41"; -- F1 press
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"01"; -- F1 release (will not be processed)
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"01"; -- F1 release
-- emulate LED control
wait for ( SYSCLK_PERIOD * 8 );
s_LED_reg <= x"000001"; -- LED1 ON
--press F2
wait for ( SYSCLK_PERIOD * 110 );
s_UART_DATA1_IN <= x"42"; -- F2 press
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"02"; -- F2 release (will not be processed)
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"02"; -- F2 release
-- emulate LED control
wait for ( SYSCLK_PERIOD * 8 );
s_LED_reg <= x"000003"; -- LED1 and LED2 ON
--press F3
wait for ( SYSCLK_PERIOD * 110 );
s_UART_DATA1_IN <= x"43"; -- F3 press
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"03"; -- F3 release (will not be processed)
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"03"; -- F3 release
-- emulate LED control
wait for ( SYSCLK_PERIOD * 8 );
s_LED_reg <= x"000004"; -- LED3 ON
wait for ( SYSCLK_PERIOD * 110 );
s_LED_reg <= x"000000"; -- LED1-3 OFF
----------------------
-- TEST J+ and J-
----------------------
wait for ( SYSCLK_PERIOD * 110 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (1st)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (2nd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
--s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (3rd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (4th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5D"; -- J+ pressed (5th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1D"; -- J+ released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 10 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (1st)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (2nd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (3rd)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (4th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 5 );
s_UART_DATA1_IN <= x"5C"; -- J- pressed (5th)
wait for ( SYSCLK_PERIOD * 3 );
s_UART_DATA2_IN <= x"1C"; -- J- released
wait for ( SYSCLK_PERIOD * 1 );
s_UART_DATA1_IN <= x"00"; -- UART1 reg cleared
s_UART_DATA2_IN <= x"00"; -- UART2 reg cleared
wait for ( SYSCLK_PERIOD * 800 );
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_pwm is
end tb_pwm;
architecture behav of tb_pwm is
signal clk_10 : std_logic := '0';
signal rst : std_logic := '0';
signal duty : std_logic_vector(7 downto 0) := "00000000";
signal outSig : std_logic := '0';
begin
process
begin
clk_10 <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
begin
wait for 205 ns;
rst <= '1';
wait for 205 ns;
rst <= '0';
wait for 10 ns;
wait for 5 ms;
duty <= X"64";
wait for 5 ms;
duty <= X"FF";
wait for 5 ms;
assert false report "done" severity failure;
wait;
end process;
pwm: entity work.pwmUnit
port map(
clk_10 =>clk_10,
rst =>rst,
duty =>duty,
outSig =>outSig
);
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
sync_out : out std_logic;
pc_out : out std_logic_vector(15 downto 0);
inst_out : out std_logic_vector(7 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal vect_bit : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal vectoring : std_logic;
signal set_i_flag : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal a16 : std_logic;
begin
inst_out <= i_reg; -- for debug only
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => interrupt,
vectoring => vectoring,
set_i_flag => set_i_flag,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
copy_d2p => copy_d2p,
vect_bit => vect_bit,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
new_flags => new_flags,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
-- from processor state machine and decoder
sync => sync,
latch_dreg => latch_dreg,
set_i_flag => set_i_flag,
vectoring => vectoring,
reg_update => reg_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
vect_bit => vect_bit,
interrupt => interrupt,
vect_addr => vect_addr );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(8-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END LUT_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF LUT_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"LUT.mif",
DEFAULT_DATA,
8,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(3),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(3)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.LUT_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 3 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<3)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_12a is
end entity inline_12a;
architecture test of inline_12a is
-- code from book
type biases is (forward, reverse);
type regions is (cutoff, saturation, linear);
signal bias : biases;
signal region : regions;
-- end code from book
constant threshold_voltage : voltage := 0.6;
constant k : real := 0.0125;
terminal gate, source, drain : electrical;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgs across gate to source;
quantity vgd across gate to drain;
begin
-- code from book
case bias use
when forward =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == 0.5 * k * (vgs - threshold_voltage)**2;
when linear =>
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end case;
when reverse =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == -0.5 * k * (vgd - threshold_voltage)**2;
when linear =>
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end case;
end case;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_12a is
end entity inline_12a;
architecture test of inline_12a is
-- code from book
type biases is (forward, reverse);
type regions is (cutoff, saturation, linear);
signal bias : biases;
signal region : regions;
-- end code from book
constant threshold_voltage : voltage := 0.6;
constant k : real := 0.0125;
terminal gate, source, drain : electrical;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgs across gate to source;
quantity vgd across gate to drain;
begin
-- code from book
case bias use
when forward =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == 0.5 * k * (vgs - threshold_voltage)**2;
when linear =>
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end case;
when reverse =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == -0.5 * k * (vgd - threshold_voltage)**2;
when linear =>
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end case;
end case;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_12a is
end entity inline_12a;
architecture test of inline_12a is
-- code from book
type biases is (forward, reverse);
type regions is (cutoff, saturation, linear);
signal bias : biases;
signal region : regions;
-- end code from book
constant threshold_voltage : voltage := 0.6;
constant k : real := 0.0125;
terminal gate, source, drain : electrical;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgs across gate to source;
quantity vgd across gate to drain;
begin
-- code from book
case bias use
when forward =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == 0.5 * k * (vgs - threshold_voltage)**2;
when linear =>
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end case;
when reverse =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == -0.5 * k * (vgd - threshold_voltage)**2;
when linear =>
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end case;
end case;
-- end code from book
end architecture test;
|
entity simp is
port (
i1, i2 : in bit;
o : out bit
) ;
end entity ; -- simp
architecture arch of simp is
signal int : bit;
begin
int <= i1 AND i2; -- available to the outside world
o <= NOT int;
end architecture ; -- arch |
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65376)
`protect data_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65376)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65376)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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MqeuAzODeSeyXUjAmtRk/YKLjxr8nuOxyWbnXtP8FjFHIdI7+BJHuS2+H2h4JfKQp24FFW27GxbH
ylrfeu1B/qG8f84OZotCqbwvryvYpSPvqVMMuLo31isfToskc6Oy9V1HDTpbcmaUNmAUlTRmL2br
rJFsgVbSDL4pDC+L60Geq7n0H8UrTwHgrxsDFfYmkjiX+voc+fdh5GiG0lj5HLg1AgR3UIZBpmXq
nYIhcu7Y/yAiTjdPN7cCWWIEz/CwAjiZAv3svDmJgnHVJuP4Bf+7xZTE7f63NiYYvbbsb++AYi3v
qvKiOlI/sIQjbeF3AAlwxPKPICp8T/3U7XYwk6Kgcftpwcj1P/UUpVGvAY5HXTximioH0oG1kSZV
yulDlEj3wvvYBzMGJoAZTd/U8+eaK0YBJZ0wa9U8ocT2rXp1EsxXtP1sURcvx1sSGd84OGeA
`protect end_protected
|
---------------------------------------------------------------------
-- Interrupt multiplexer
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Manages LXP32 interrupts. Interrupts with lower numbers have
-- higher priority.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_interrupt_mux is
port(
clk_i: in std_logic;
rst_i: in std_logic;
irq_i: in std_logic_vector(7 downto 0);
interrupt_valid_o: out std_logic;
interrupt_vector_o: out std_logic_vector(2 downto 0);
interrupt_ready_i: in std_logic;
interrupt_return_i: in std_logic;
wakeup_o: out std_logic;
sp_waddr_i: in std_logic_vector(7 downto 0);
sp_we_i: in std_logic;
sp_wdata_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_interrupt_mux is
signal irq_reg: std_logic_vector(irq_i'range):=(others=>'0');
type state_type is (Ready,Requested,WaitForExit);
signal state: state_type:=Ready;
signal pending_interrupts: std_logic_vector(irq_i'range):=(others=>'0');
signal interrupt_valid: std_logic:='0';
signal interrupts_enabled: std_logic_vector(7 downto 0):=(others=>'0');
signal interrupts_wakeup: std_logic_vector(7 downto 0):=(others=>'0');
begin
-- Note: "disabled" interrupts (i.e. for which interrupts_enabled_i(i)='0')
-- are ignored completely, meaning that the interrupt handler won't be
-- called even if the interrupt is enabled later.
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
irq_reg<=(others=>'0');
pending_interrupts<=(others=>'0');
state<=Ready;
interrupt_valid<='0';
interrupt_vector_o<=(others=>'-');
wakeup_o<='0';
else
irq_reg<=irq_i;
pending_interrupts<=(pending_interrupts or
(irq_i and not irq_reg)) and
interrupts_enabled and not interrupts_wakeup;
case state is
when Ready =>
for i in pending_interrupts'reverse_range loop -- lower interrupts have priority
if pending_interrupts(i)='1' then
pending_interrupts(i)<='0';
interrupt_valid<='1';
interrupt_vector_o<=std_logic_vector(to_unsigned(i,3));
state<=Requested;
exit;
end if;
end loop;
when Requested =>
if interrupt_ready_i='1' then
interrupt_valid<='0';
state<=WaitForExit;
end if;
when WaitForExit =>
if interrupt_return_i='1' then
state<=Ready;
end if;
end case;
if (irq_i and (not irq_reg) and interrupts_enabled and interrupts_wakeup)/=X"00" then
wakeup_o<='1';
else
wakeup_o<='0';
end if;
end if;
end if;
end process;
interrupt_valid_o<=interrupt_valid;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
interrupts_enabled<=(others=>'0');
interrupts_wakeup<=(others=>'0');
elsif sp_we_i='1' and sp_waddr_i=X"FC" then
interrupts_enabled<=sp_wdata_i(7 downto 0);
interrupts_wakeup<=sp_wdata_i(15 downto 8);
end if;
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1203.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01203ent IS
END c08s01b00x00p08n03i01203ent;
ARCHITECTURE c08s01b00x00p08n03i01203arch OF c08s01b00x00p08n03i01203ent IS
type SWORD is ARRAY(0 to 31) of integer;
signal Res : SWORD;
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
for k in 0 to 31 loop
wait on Res(k);
end loop;
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01203 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01203arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1203.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01203ent IS
END c08s01b00x00p08n03i01203ent;
ARCHITECTURE c08s01b00x00p08n03i01203arch OF c08s01b00x00p08n03i01203ent IS
type SWORD is ARRAY(0 to 31) of integer;
signal Res : SWORD;
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
for k in 0 to 31 loop
wait on Res(k);
end loop;
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01203 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01203arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1203.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n03i01203ent IS
END c08s01b00x00p08n03i01203ent;
ARCHITECTURE c08s01b00x00p08n03i01203arch OF c08s01b00x00p08n03i01203ent IS
type SWORD is ARRAY(0 to 31) of integer;
signal Res : SWORD;
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
for k in 0 to 31 loop
wait on Res(k);
end loop;
assert FALSE
report "***FAILED TEST: c08s01b00x00p08n03i01203 - Signal name in the ON expression is not static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n03i01203arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
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-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
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-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
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-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
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-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L:out std_logic;
healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L:out std_logic
);
end router_credit_based_parity;
architecture behavior of router_credit_based_parity is
COMPONENT parity_checker_packet_detector is
generic(DATA_WIDTH : integer := 32
);
port(
reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
faulty_packet, healthy_packet: out std_logic
);
end COMPONENT;
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
-- all the parity_checkers
PC_N: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_N, valid_in =>valid_in_N, faulty_packet => faulty_packet_N , healthy_packet => healthy_packet_N);
PC_E: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_E, valid_in =>valid_in_E, faulty_packet => faulty_packet_E , healthy_packet => healthy_packet_E);
PC_W: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_W, valid_in =>valid_in_W, faulty_packet => faulty_packet_W , healthy_packet => healthy_packet_W);
PC_S: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_S, valid_in =>valid_in_S, faulty_packet => faulty_packet_S , healthy_packet => healthy_packet_S);
PC_L: parity_checker_packet_detector generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(reset => reset, clk => clk, RX => RX_L, valid_in =>valid_in_L, faulty_packet => faulty_packet_L , healthy_packet => healthy_packet_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
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-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file weight_out.vhd when simulating
-- the core, weight_out. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY weight_out IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END weight_out;
ARCHITECTURE weight_out_a OF weight_out IS
-- synthesis translate_off
COMPONENT wrapped_weight_out
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_weight_out USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 6,
c_addrb_width => 6,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "artix7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "weight_out.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 45,
c_read_depth_b => 45,
c_read_width_a => 320,
c_read_width_b => 320,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 45,
c_write_depth_b => 45,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 320,
c_write_width_b => 320,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_weight_out
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END weight_out_a;
|
architecture RTL of ENTITY1 is
constant c_size : integer := 5;
constant c_ones : std_logic_vector(c_size - 1 downto 0) := (others => '1');
constant c_zeros : std_logic_vector(c_size - 1 downto 0) := (others => '0');
signal data : std_logic_vector(c_size - 1 downto 0);
begin
data <= c_ones;
PROC_NAME : process () is
begin
data <= c_ones & c_zeros;
if (sig2 = '0') then
data <= c_zeros;
end if;
if (sig2 = '1') then
data <= c_ones;
end if;
if (sig3 = '1') then
data <= c_zeros;
end if;
end process PROC_NAME;
end architecture RTL;
|
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`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect begin_protected
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`protect begin_protected
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`protect begin_protected
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu_cached is
end entity;
architecture test of mblite_simu_cached is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mmem_o : dmem_out_type;
signal mmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := X"00003FFC";
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_core: entity work.cached_mblite
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
mmem_o => mmem_o,
mmem_i => mmem_i,
irq_i => irq_i,
irq_o => irq_o );
-- IRQ generation @ 100 kHz (every 10 us)
process
begin
for i in 1 to 50 loop
wait for 10 us;
wait until clock='1';
irq_i <= '1';
wait until clock='1';
irq_i <= '0';
end loop;
wait;
end process;
process
begin
wait until reset='0';
wait until clock='1';
wait until clock='1';
while true loop
invalidate <= '0';
wait until clock='1';
invalidate <= '0';
wait until clock='1';
wait until clock='1';
end loop;
end process;
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
mmem_i.dat_i <= (others => 'X');
if mmem_o.ena_o = '1' then
if mmem_o.adr_o(31 downto 25) = "0000000" then
if mmem_o.we_o = '1' then
for i in 0 to 3 loop
if mmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := mmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
mmem_i.dat_i <= memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if mmem_o.we_o = '1' then -- write
case mmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := mmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(mmem_o.adr_o) & " dropped";
end case;
else -- read
case mmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
mmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
mmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
mmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
mmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(mmem_o.adr_o) & " dropped";
mmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
mmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu_cached is
end entity;
architecture test of mblite_simu_cached is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mmem_o : dmem_out_type;
signal mmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := X"00003FFC";
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_core: entity work.cached_mblite
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
mmem_o => mmem_o,
mmem_i => mmem_i,
irq_i => irq_i,
irq_o => irq_o );
-- IRQ generation @ 100 kHz (every 10 us)
process
begin
for i in 1 to 50 loop
wait for 10 us;
wait until clock='1';
irq_i <= '1';
wait until clock='1';
irq_i <= '0';
end loop;
wait;
end process;
process
begin
wait until reset='0';
wait until clock='1';
wait until clock='1';
while true loop
invalidate <= '0';
wait until clock='1';
invalidate <= '0';
wait until clock='1';
wait until clock='1';
end loop;
end process;
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
mmem_i.dat_i <= (others => 'X');
if mmem_o.ena_o = '1' then
if mmem_o.adr_o(31 downto 25) = "0000000" then
if mmem_o.we_o = '1' then
for i in 0 to 3 loop
if mmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := mmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
mmem_i.dat_i <= memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if mmem_o.we_o = '1' then -- write
case mmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := mmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(mmem_o.adr_o) & " dropped";
end case;
else -- read
case mmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
mmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
mmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
mmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
mmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(mmem_o.adr_o) & " dropped";
mmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
mmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_aea_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aea_e-rtl-a.vhd,v 1.2 2004/08/18 10:47:05 wig Exp $
-- $Date: 2004/08/18 10:47:05 $
-- $Log: inst_aea_e-rtl-a.vhd,v $
-- Revision 1.2 2004/08/18 10:47:05 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_aea_e
--
architecture rtl of inst_aea_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Entity: align_read_to_bram
-- Date:2015-03-14
-- Author: Gideon
--
-- Description: This module aligns 32 bit reads from memory to writes to BRAM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity align_read_to_bram is
port (
clock : in std_logic;
reset : in std_logic;
rdata : in std_logic_vector(31 downto 0);
rdata_valid : in std_logic;
first_word : in std_logic;
last_word : in std_logic;
offset : in unsigned(1 downto 0);
last_bytes : in unsigned(1 downto 0);
wdata : out std_logic_vector(31 downto 0);
wmask : out std_logic_vector(3 downto 0);
wnext : out std_logic );
end align_read_to_bram;
-- This unit implements data rotation. This is done to support streaming from memory.
-- Length that this unit gets is: actual length + offset + 3. This indicates the last byte that
-- is being read and thus valid for writing.
-- int (size / 4) = number of words to be accessed.
-- (size and 3) = info about byte enables of last beat 0 = 0001, 1 = 0011, 2 = 0111, 3 = 1111.
-- for writing, these byte enables shall still be rotated to the right.
-- offset = info about byte enables of first beat, and rotation value
-- Note that for an offset of 0, it doesn't really matter if we write a few extra bytes in the BRAM,
-- because we're aligned. However, for an offset other than 0, it determines whether
-- we should write the last beat or not.
architecture arch of align_read_to_bram is
type t_state is (idle, stream, last);
signal state : t_state;
signal remain : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
wmask <= X"0";
wnext <= '0';
-- we always get 3210, regardless of the offset.
-- If the offset is 0, we pass all data
-- If the offset is 1, we save 3 bytes (321x), and go to the next state
-- If the offset is 2, we save 2 bytes (32xx), and go to the next state
-- If the offset is 3, we save 1 byte (3xxx), and go to the next state
-- In case the offset was sent to the DRAM, we get:
-- If the offset is 1, we save 3 bytes (x321), and go to the next state
-- If the offset is 2, we save 2 bytes (xx32), and go to the next state
-- If the offset is 3, we save 1 byte (xxx3), and go to the next state
case state is
when idle =>
wdata <= rdata;
if rdata_valid = '1' then -- we assume first word
remain <= rdata;
case offset is
when "00" => -- aligned
wmask <= X"F";
wnext <= '1';
when others =>
if last_word = '1' then
state <= last;
else
state <= stream;
end if;
end case;
end if;
when stream =>
case offset is
when "01" =>
-- We use 3 bytes from the previous word, and one from the current word
wdata <= rdata(31 downto 24) & remain(23 downto 0);
when "10" =>
-- We use 2 bytes from the previous word, and two from the current word
wdata <= rdata(31 downto 16) & remain(15 downto 0);
when "11" =>
-- We use 1 bytes from the previous word, and three from the current word
wdata <= rdata(31 downto 8) & remain( 7 downto 0);
when others =>
wdata <= rdata;
end case;
if rdata_valid = '1' then
remain <= rdata;
wmask <= X"F";
wnext <= '1';
if last_word = '1' then
if offset > last_bytes then
state <= idle;
else
state <= last;
end if;
end if;
end if;
when last =>
case offset is
when "01" =>
-- We use 3 bytes from the previous word, and one from the current word
wdata <= rdata(31 downto 24) & remain(23 downto 0);
when "10" =>
-- We use 2 bytes from the previous word, and two from the current word
wdata <= rdata(31 downto 16) & remain(15 downto 0);
when "11" =>
-- We use 1 bytes from the previous word, and three from the current word
wdata <= rdata(31 downto 8) & remain( 7 downto 0);
when others =>
wdata <= rdata;
end case;
wmask <= X"F";
state <= idle;
-- case last_bytes is
-- when "01" =>
-- wmask <= "0001";
-- when "10" =>
-- wmask <= "0011";
-- when "11" =>
-- wmask <= "0111";
-- when others =>
-- wmask <= "0000";
-- end case;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
end if;
end if;
end process;
end arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:03:04 11/07/2015
-- Design Name:
-- Module Name: register_n_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity register_n_bit is
generic (n : natural := 8;
delay : time := 0 ns);
Port ( I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0));
end register_n_bit;
architecture Behavioral of register_n_bit is
begin
process (clock, load, reset_n)
begin
if (reset_n = '0') then
O <= (others => '0');
elsif (clock = '1' and rising_edge(clock)) then
if (load = '1') then
O <= I after delay;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_rom_base : unsigned(27 downto 0) := X"0F80000";
g_ram_base : unsigned(27 downto 0) := X"0F70000";
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(3 downto 0);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= '1';
when c_cart_kernal_enable =>
control_i.kernal_enable <= io_req.data(0);
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_ethernet_enable =>
control_i.eth_enable <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
when c_cart_cartridge_rom_base =>
io_resp.data <= std_logic_vector(g_rom_base(23 downto 16));
when c_cart_cartridge_type =>
io_resp.data(3 downto 0) <= control_i.cartridge_type;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_ethernet_enable =>
io_resp.data(0) <= control_i.eth_enable;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_rom_base : unsigned(27 downto 0) := X"0F80000";
g_ram_base : unsigned(27 downto 0) := X"0F70000";
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(3 downto 0);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= '1';
when c_cart_kernal_enable =>
control_i.kernal_enable <= io_req.data(0);
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_ethernet_enable =>
control_i.eth_enable <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
when c_cart_cartridge_rom_base =>
io_resp.data <= std_logic_vector(g_rom_base(23 downto 16));
when c_cart_cartridge_type =>
io_resp.data(3 downto 0) <= control_i.cartridge_type;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_ethernet_enable =>
io_resp.data(0) <= control_i.eth_enable;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_rom_base : unsigned(27 downto 0) := X"0F80000";
g_ram_base : unsigned(27 downto 0) := X"0F70000";
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(3 downto 0);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= '1';
when c_cart_kernal_enable =>
control_i.kernal_enable <= io_req.data(0);
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_ethernet_enable =>
control_i.eth_enable <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
when c_cart_cartridge_rom_base =>
io_resp.data <= std_logic_vector(g_rom_base(23 downto 16));
when c_cart_cartridge_type =>
io_resp.data(3 downto 0) <= control_i.cartridge_type;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_ethernet_enable =>
io_resp.data(0) <= control_i.eth_enable;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- ION_INTERNAL_PKG.vhdl -- Configuration constants, utility types & functions.
--------------------------------------------------------------------------------
-- For use within the core component modules only.
-- Modules instantiating an ion_core entity do not need this package.
--------------------------------------------------------------------------------
-- FIXME Plenty of remnants from the old ION version, refactor!
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
package ION_INTERNAL_PKG is
---- Basic types ---------------------------------------------------------------
subtype t_halfword is std_logic_vector(15 downto 0);
subtype t_byte is std_logic_vector(7 downto 0);
subtype t_pc is std_logic_vector(31 downto 2);
subtype t_regindex is std_logic_vector(4 downto 0);
---- Interface types -----------------------------------------------------------
type t_cpumem_mosi is record
addr : t_word;
rd_en : std_logic;
wr_be : std_logic_vector(3 downto 0);
wr_data : t_word;
end record t_cpumem_mosi;
type t_cpumem_miso is record
rd_data : t_word;
mwait : std_logic;
end record t_cpumem_miso;
type t_cache_mosi is record
function_code : std_logic_vector(2 downto 0);
function_en : std_logic; -- 1 to perform function_code operation.
data_cache : std_logic; -- 1 to operate on D-cache, 0 for I-Cache.
end record t_cache_mosi;
type t_cache_miso is record
present : std_logic; -- Hardwired to 1 when cache is present.
end record t_cache_miso;
type t_cop0_mosi is record
index : t_regindex;
we : std_logic;
data : t_word;
pc_restart : t_pc;
in_delay_slot : std_logic;
pipeline_stalled : std_logic;
exception : std_logic;
hw_irq : std_logic;
hw_irq_reg : std_logic_vector(7 downto 2);
eret : std_logic;
rfe : std_logic;
unknown_opcode : std_logic;
missing_cop : std_logic;
syscall : std_logic;
stall : std_logic;
end record t_cop0_mosi;
type t_cop0_miso is record
data : t_word;
pc_load_en : std_logic;
pc_load_value : t_pc;
hw_irq_enable_mask: std_logic_vector(5 downto 0);
global_irq_enable : std_logic;
kernel : std_logic;
end record t_cop0_miso;
---- System configuration constants --------------------------------------------
-- True to use standard-ish MIPS-1 memory map, false to use Plasma's
-- (see implementation of function decode_addr_old below).
constant USE_MIPS1_ADDR_MAP : boolean := true;
-- Reset vector address.
constant RESET_VECTOR : t_word := X"bfc00000";
-- General exception vector address.
constant GENERAL_EXCEPTION_VECTOR : t_word := X"bfc00180";
-- Object code in bytes, i.e. as read from a binary or HEX file.
-- This type is used to define BRAM init constants from external scripts.
type t_obj_code is array(integer range <>) of std_logic_vector(7 downto 0);
-- Types used to define memories for synthesis or simulation.
type t_word_table is array(integer range <>) of t_word;
type t_hword_table is array(integer range <>) of t_halfword;
type t_byte_table is array(integer range <>) of t_byte;
---- Object code management -- initialization helper functions -----------------
-- Dummy t_obj_code constant, to be used essentially as a syntactic placeholder.
constant default_object_code : t_obj_code(0 to 3) := (
X"00", X"00", X"00", X"00"
);
-- Build t_obj_code if given size (in bytes) filled with zeros.
function zero_objcode(size : integer) return t_obj_code;
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The constant is a 32-bit, big endian word table.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- The object code is truncated if it doesn't fit the given table size.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
function objcode_to_wtable(oC : t_obj_code; size : integer) return t_word_table;
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The constant is a 16-bit, big endian word table.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- The object code is truncated if it doesn't fit the given table size.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
function objcode_to_htable(oC : t_obj_code; size : integer) return t_hword_table;
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- It will put the whole object code into a byte table if slice=-1, otherwise
-- it will extract the selected slice (0 to 3) and put only that in the table.
-- If slice = -1, the size is that fo the whole data block.
-- If slice >= 0, the size is that of the slice, i.e. 1/4 of the block size.
-- The constant is an 8-bit byte table in BIG ENDIAN format.
-- Slice 0 is the lowest byte, slice 3 is the highest byte.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- The object code is truncated if it doesn't fit the given table size.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
function objcode_to_btable(oC : t_obj_code; size : integer;
slice : integer := -1) return t_byte_table;
---- More basic types and constants --------------------------------------------
subtype t_addr is std_logic_vector(31 downto 0);
subtype t_dword is std_logic_vector(63 downto 0);
subtype t_regnum is std_logic_vector(4 downto 0);
type t_rbank is array(0 to 31) of t_word;
-- This is used as a textual shortcut only
constant ZERO : t_word := (others => '0');
-- control word for ALU
type t_alu_control is record
logic_sel : std_logic_vector(1 downto 0);
shift_sel : std_logic_vector(1 downto 0);
shift_amount : std_logic_vector(4 downto 0);
neg_sel : std_logic_vector(1 downto 0);
use_arith : std_logic;
use_logic : std_logic_vector(1 downto 0);
cy_in : std_logic;
use_slt : std_logic;
arith_unsigned : std_logic;
end record t_alu_control;
-- Flags coming from the ALU
type t_alu_flags is record
inp1_lt_zero : std_logic;
inp1_eq_zero : std_logic;
inp1_lt_inp2 : std_logic;
inp1_eq_inp2 : std_logic;
end record t_alu_flags;
-- Debug info output by sinthesizable MPU core; meant to debug the core itself,
-- not to debug software!
type t_debug_info is record
cache_enabled : std_logic;
unmapped_access : std_logic;
end record t_debug_info;
-- 32-cycle mul/div module control. Bits 4-3 & 1-0 of IR.
subtype t_mult_function is std_logic_vector(3 downto 0);
constant MULT_NOTHING : t_mult_function := "0000";
constant MULT_MADDU : t_mult_function := "0101"; -- 5
constant MULT_MADD : t_mult_function := "0100"; -- 4
constant MULT_READ_LO : t_mult_function := "1010"; -- 18
constant MULT_READ_HI : t_mult_function := "1000"; -- 16
constant MULT_WRITE_LO : t_mult_function := "1011"; -- 19
constant MULT_WRITE_HI : t_mult_function := "1001"; -- 17
constant MULT_MULT : t_mult_function := "1101"; -- 25
constant MULT_SIGNED_MULT : t_mult_function := "1100"; -- 24
constant MULT_DIVIDE : t_mult_function := "1111"; -- 26
constant MULT_SIGNED_DIVIDE : t_mult_function := "1110"; -- 27
-- Computes ceil(log2(A)), e.g. address width of memory block
-- CAN BE USED IN SYNTHESIZABLE CODE as long as called with constant arguments
function log2(A : natural) return natural;
end package;
package body ION_INTERNAL_PKG is
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
function zero_objcode(size : integer) return t_obj_code is
variable oc : t_obj_code(0 to size-1) := (others => X"00");
begin
return oc;
end function zero_objcode;
function objcode_to_wtable(oC : t_obj_code;
size : integer)
return t_word_table is
variable br : t_word_table(integer range 0 to size/4-1):=(others => X"00000000");
variable i, address, index : integer;
begin
-- Copy object code to start of BRAM...
i := 0;
for i in 0 to oC'length-1 loop
case i mod 4 is
when 0 => index := 24;
when 1 => index := 16;
when 2 => index := 8;
when others => index := 0;
end case;
address := i / 4;
if address >= size or address >= br'high then
exit;
end if;
br(address)(index+7 downto index) := oC(i);
end loop;
return br;
end function objcode_to_wtable;
function objcode_to_htable(oC : t_obj_code;
size : integer)
return t_hword_table is
variable br : t_hword_table(integer range 0 to size-1):=(others => X"0000");
variable i, address, index : integer;
begin
-- Copy object code to start of BRAM...
i := 0;
for i in 0 to oC'length-1 loop
case i mod 2 is
when 1 => index := 8;
when others => index := 0;
end case;
address := i / 2;
if address >= size then
exit;
end if;
br(address)(index+7 downto index) := oC(i);
end loop;
return br;
end function objcode_to_htable;
function objcode_to_btable(oC : t_obj_code;
size : integer;
slice : integer := -1)
return t_byte_table is
variable br : t_byte_table(integer range 0 to size-1):=(others => X"00");
variable i, address, index : integer;
begin
if slice < 0 then
-- Copy object code to start of table, leave the rest filled with zeros.
for i in 0 to oC'length-1 loop
if i >= size then
exit;
end if;
br(i) := oC(i);
end loop;
else
-- Remember, oC is big endian and slice 0 is the low byte.
i := 0; -- TODO check bounds!
while ((i*4)+(3-slice)) < (oC'length) loop
if i >= size then
exit;
end if;
br(i) := oC((3-slice) + (i*4));
i := i + 1;
end loop;
end if;
return br;
end function objcode_to_btable;
end package body;
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity passive is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_conductance_conductance : in sfixed (-22 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
derivedvariable_conductance_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_g_in : in sfixed (-22 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end passive;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of passive is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_none_fopen : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_none_fopen_next : sfixed (18 downto -13) := to_sfixed(0.0 ,18,-13);
signal DerivedVariable_conductance_g : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
signal DerivedVariable_conductance_g_next : sfixed (-22 downto -53) := to_sfixed(0.0 ,-22,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_conductance_conductance )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep, param_conductance_conductance )
begin
derivedvariable_none_fopen_next <= resize(( to_sfixed ( 1 ,1 , -1 ) ),18,-13);
derivedvariable_conductance_g_next <= resize(( param_conductance_conductance ),-22,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_none_fopen <= derivedvariable_none_fopen_next;
derivedvariable_conductance_g <= derivedvariable_conductance_g_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= derivedvariable_conductance_g_in;derivedvariable_conductance_g_out <= derivedvariable_conductance_g;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Experiments on custom attributes ended in a crash.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
-- Issue:
-- I'm not sure if my experimental code is allowed in VHDL, but it let GHDL
-- crash. So I'm reporting just an unhandled exception.
--
-- GHDL's output is:
-- .\attribute.vhdl:64:58: can't match 'image attribute with type character
-- .\attribute.vhdl:64:53: (location of 'image attribute)
-- finish_sem_name: cannot handle IIR_KIND_OVERLOAD_LIST (??:??:??)
--
-- ******************** GHDL Bug occured ****************************
-- Please report this bug on https://github.com/tgingold/ghdl/issues
-- GHDL release: GHDL 0.34dev (commit: 2016-02-11; git branch: paebbels/master'; hash: f24fdfb) [Dunoon edition]
-- Compiled with GNAT Version: GPL 2015 (20150428-49)
-- In directory: H:\Austausch\PoC\temp\ghdl\
-- Command line:
-- C:\Tools\GHDL.new\bin\ghdl.exe -a --std=08 .\attribute.vhdl
-- Exception TYPES.INTERNAL_ERROR raised
-- Exception information:
-- Exception name: TYPES.INTERNAL_ERROR
-- Message: errorout.adb:66
-- ******************************************************************
--
-- GHDL calls:
-- PS> ghdl.exe -a --std=93c .\attribute.vhdl
-- PS> ghdl.exe -a --std=08 .\attribute.vhdl
--
library IEEE;
use IEEE.std_logic_1164.all;
entity test is
end entity;
architecture tb of test is
function to_string(slv : STD_LOGIC_VECTOR) return STRING is
variable Result : STRING(slv'length - 1 downto 0);
begin
for i in slv'range loop
Result(i + 1) := STD_LOGIC'image(slv(i));
end loop;
return Result;
end function;
attribute serialize : to_string;
signal mySignal : STD_LOGIC_VECTOR(7 downto 0);
attribute serialize of mySignal : signal is to_string[STD_LOGIC_VECTOR return STRING];
begin
mySignal <= x"24";
process
begin
report "mySignal=" & mySignal'serialize severity NOTE;
wait;
end process;
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:53 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_1/system_auto_us_1_stub.vhdl
-- Design : system_auto_us_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_auto_us_1 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end system_auto_us_1;
architecture stub of system_auto_us_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
begin
end;
|
-- A Year Month Day counter
--
-- entity name: g23_lab5_testbed
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 20/04/2014
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY g23_lab5_testbed IS
PORT (
clock : in STD_LOGIC; -- ASYNC, Should be connected to the master 50MHz clock.
reset : in STD_LOGIC; -- ASYNC, When high the counts are all set to zero.
enable : in STD_LOGIC := '1';
increment : in STD_LOGIC; -- increase the current value
dst_set : in STD_LOGIC;
sync_mars : in STD_LOGIC;
syncing : out STD_LOGIC;
mode : in STD_LOGIC_VECTOR(1 downto 0);
mode2 : in STD_LOGIC_VECTOR(1 downto 0);
digit_3 : out STD_LOGIC_VECTOR(6 downto 0);
digit_2 : out STD_LOGIC_VECTOR(6 downto 0);
digit_1 : out STD_LOGIC_VECTOR(6 downto 0);
digit_0 : out STD_LOGIC_VECTOR(6 downto 0);
epulse_out : out STD_LOGIC;
mpulse_out : out STD_LOGIC;
dst_out : out STD_LOGIC;
Date_is_reached : out STD_LOGIC;
earth_active : out STD_LOGIC;
mars_active : out STD_LOGIC
);
end g23_lab5_testbed;
ARCHITECTURE alpha OF g23_lab5_testbed IS
COMPONENT g23_7_segment_decoder
PORT (
code : in std_logic_vector(3 downto 0);
RippleBlank_In : in std_logic;
RippleBlank_Out : out std_logic;
segments : out std_logic_vector(6 downto 0)
);
END COMPONENT;
COMPONENT g23_14_to_BCD
PORT (
input : in STD_LOGIC_VECTOR(13 downto 0);
output : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT g23_YMD_counter
PORT (
clock : in STD_LOGIC; -- ASYNC, Should be connected to the master 50MHz clock.
reset : in STD_LOGIC; -- ASYNC, When high the counts are all set to zero.
count_enable : in STD_LOGIC; -- SYNC, A pulse with a width of 1 master clock cycle.
load_enable : in STD_LOGIC; -- SYNC, if high sets count values to Y_Set, M_Set, and D_Set inputs
y_inc : in STD_LOGIC;
m_inc : in STD_LOGIC;
d_inc : in STD_LOGIC;
y_set : in STD_LOGIC_VECTOR(11 downto 0);
m_set : in STD_LOGIC_VECTOR(3 downto 0);
d_set : in STD_LOGIC_VECTOR(4 downto 0);
years : out STD_LOGIC_VECTOR(11 downto 0);
months : out STD_LOGIC_VECTOR(3 downto 0);
days : out STD_LOGIC_VECTOR(4 downto 0)
);
END COMPONENT;
COMPONENT g23_HMS_counter
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
load_enable : IN STD_LOGIC;
count_enable: IN STD_LOGIC;
dst : IN STD_LOGIC;
h_set : IN STD_LOGIC_VECTOR(4 downto 0);
m_set : IN STD_LOGIC_VECTOR(5 downto 0);
s_set : IN STD_LOGIC_VECTOR(5 downto 0);
h_inc : IN STD_LOGIC;
m_inc : IN STD_LOGIC;
s_inc : IN STD_LOGIC;
hours : OUT STD_LOGIC_VECTOR(4 downto 0);
minutes : OUT STD_LOGIC_VECTOR(5 downto 0);
seconds : OUT STD_LOGIC_VECTOR(5 downto 0);
end_of_day : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT g23_basic_timer
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
EPULSE : out STD_LOGIC;
MPULSE : out STD_LOGIC
);
END COMPONENT;
COMPONENT g23_UTC_to_MTC
PORT (
clock : in STD_LOGIC; -- ASYNC, Should be connected to the master 50MHz clock.
reset : in STD_LOGIC; -- ASYNC, When high the counts are all set to zero.
enable : in STD_LOGIC; -- SYNC, A pulse with a width of 1 master clock cycle.
-- Earth date input
Year : in STD_LOGIC_VECTOR(11 downto 0);
Month : in STD_LOGIC_VECTOR(3 downto 0);
Day : in STD_LOGIC_VECTOR(4 downto 0);
-- Earth time input
Hour : in STD_LOGIC_VECTOR(4 downto 0);
Minute : in STD_LOGIC_VECTOR(5 downto 0);
Second : in STD_LOGIC_VECTOR(5 downto 0);
-- MTC time on the prime meridian on Mars
Mars_hours : out STD_LOGIC_VECTOR(4 downto 0);
Mars_minutes : out STD_LOGIC_VECTOR(5 downto 0);
Mars_seconds : out STD_LOGIC_VECTOR(5 downto 0);
-- Debug
Year_out : out STD_LOGIC_VECTOR(11 downto 0);
Month_out : out STD_LOGIC_VECTOR(3 downto 0);
Day_out : out STD_LOGIC_VECTOR(4 downto 0);
Num_days : out STD_LOGIC_VECTOR(13 downto 0);
Num_secs : out STD_LOGIC_VECTOR(16 downto 0);
Date_is_reached : out STD_LOGIC
);
END COMPONENT;
COMPONENT g23_binary_to_BCD
PORT (
clock : in std_logic; -- to clock the lpm_rom register
bin : in unsigned(5 downto 0);
BCD : out std_logic_vector(7 downto 0)
);
END COMPONENT;
signal RB_Out3 : STD_LOGIC;
signal RB_Out2 : STD_LOGIC;
signal all_digits : STD_LOGIC_VECTOR(13 downto 0);
signal bcd_digits : STD_LOGIC_VECTOR(15 downto 0);
signal earth_min_sec, mars_min_sec : STD_LOGIC_VECTOR(13 downto 0);
signal earth_min_bcd, mars_min_bcd : STD_LOGIC_VECTOR(7 downto 0);
signal earth_sec_bcd, mars_sec_bcd : STD_LOGIC_VECTOR(7 downto 0);
signal earth_time_sig : STD_LOGIC_VECTOR(13 downto 0);
signal earth_date_sig : STD_LOGIC_VECTOR(13 downto 0);
signal mars_time_sig : STD_LOGIC_VECTOR(13 downto 0);
signal time_zone_sig : STD_LOGIC_VECTOR(13 downto 0);
signal earth_year_sig : STD_LOGIC_VECTOR(13 downto 0);
signal earth_month_sig : STD_LOGIC_VECTOR(3 downto 0);
signal earth_day_sig : STD_LOGIC_VECTOR(4 downto 0);
signal earth_hour_sig : STD_LOGIC_VECTOR(4 downto 0);
signal earth_min_sig : STD_LOGIC_VECTOR(5 downto 0);
signal earth_sec_sig : STD_LOGIC_VECTOR(5 downto 0);
signal mars_hour_sig : STD_LOGIC_VECTOR(4 downto 0);
signal mars_min_sig : STD_LOGIC_VECTOR(5 downto 0);
signal mars_sec_sig : STD_LOGIC_VECTOR(5 downto 0);
signal earth_y_inc, earth_mo_inc, earth_d_inc : STD_LOGIC;
signal earth_h_inc, earth_mi_inc, earth_s_inc : STD_LOGIC;
signal mars_h_inc, mars_mi_inc, mars_s_inc : STD_LOGIC;
signal mars_hour_set : STD_LOGIC_VECTOR(4 downto 0);
signal mars_min_set, mars_sec_set : STD_LOGIC_VECTOR(5 downto 0);
signal eod : STD_LOGIC;
signal epulse : STD_LOGIC;
signal mpulse : STD_LOGIC;
signal last_increment_state : STD_LOGIC;
signal inc_pulse : STD_LOGIC;
signal date_reached_sig : STD_LOGIC;
signal dst_pulse : STD_LOGIC;
BEGIN
syncing <= NOT sync_mars;
process(clock)
variable e_blinker : STD_LOGIC := '0';
variable m_blinker : STD_LOGIC := '0';
variable last_dst_state : STD_LOGIC := '0';
begin
if(rising_edge(clock)) then
mpulse_out <= m_blinker;
epulse_out <= e_blinker;
-- Makes epulse_out and mpulse_out change color on every pulse
if(mpulse = '1') THEN
m_blinker := NOT m_blinker;
end if;
if(epulse = '1') THEN
e_blinker := NOT e_blinker;
end if;
if(inc_pulse = '1') then
inc_pulse <= '0';
end if;
if(dst_pulse = '1') then
dst_pulse <= '0';
end if;
if(dst_set = '1' AND last_dst_state = '0') then
dst_pulse <= '1';
end if;
last_dst_state := dst_set;
if(increment = '1' AND last_increment_state = '0') then
inc_pulse <= '1';
end if;
last_increment_state <= increment;
end if;
end process;
to_4_BCD : g23_14_to_BCD
PORT MAP (
input => all_digits,
output => bcd_digits
);
earth_active <= NOT mode(1);
mars_active <= mode(1);
--mode
with mode select
all_digits <=
earth_time_sig when "00", -- earth time
earth_date_sig when "01", -- earth date
mars_time_sig when "10", -- mars time
time_zone_sig when "11"; -- time zone
--mode 2: allows you to choose year,month,day for dates and hours,minutes,seconds for times and mars,earth for time zone
with mode2 select
earth_time_sig <=
"000000000" & earth_hour_sig when "00",
"00000000" & earth_min_sig when "01",
"00000000" & earth_sec_sig when "10",
"00000000000000" when "11";
with mode2 select
earth_date_sig <=
earth_year_sig when "00",
"0000000000" & earth_month_sig when "01",
"000000000" & earth_day_sig when "10",
"00000000000000" when "11";
with mode2 select
mars_time_sig <=
"000000000" & mars_hour_sig when "00",
"00000000" & mars_min_sig when "01",
"00000000" & mars_sec_sig when "10",
"00000000000000" when "11";
with mode2 select
time_zone_sig <=
"00000000000000" when "00",
"00000000000000" when "01",
"00000000000000" when "10",
"00000000000000" when "11";
--manually set day light savings time
dst_out <= dst_set;
earth_y_inc <= '1' when (inc_pulse & mode & mode2 = "10100") else '0';
earth_mo_inc <= '1' when (inc_pulse & mode & mode2 = "10101") else '0';
earth_d_inc <= '1' when (inc_pulse & mode & mode2 = "10110") else '0';
earth_h_inc <= '1' when (inc_pulse & mode & mode2 = "10000") else '0';
earth_mi_inc <= '1' when (inc_pulse & mode & mode2 = "10001") else '0';
earth_s_inc <= '1' when (inc_pulse & mode & mode2 = "10010") else '0';
mars_h_inc <= '1' when (inc_pulse & mode & mode2 = "11000") else '0';
mars_mi_inc <= '1' when (inc_pulse & mode & mode2 = "11001") else '0';
mars_s_inc <= '1' when (inc_pulse & mode & mode2 = "11010") else '0';
--Earth YMD counter
YMD_counter : g23_YMD_counter
PORT MAP (
clock => clock,
reset => reset,
count_enable => eod,
load_enable => '0',
y_inc => earth_y_inc,
m_inc => earth_mo_inc,
d_inc => earth_d_inc,
y_set => "000000000000",
m_set => "0000",
d_set => "00000",
years => earth_year_sig(11 downto 0),
months => earth_month_sig,
days => earth_day_sig
);
-- Earth HMS counter
earth_hms : g23_HMS_counter
PORT MAP (
clk => clock,
reset => reset,
load_enable => '0',
count_enable => epulse,
dst => dst_pulse,
h_inc => earth_h_inc,
m_inc => earth_mi_inc,
s_inc => earth_s_inc,
h_set => "00000",
m_set => "000000",
s_set => "000000",
hours => earth_hour_sig,
minutes => earth_min_sig,
seconds => earth_sec_sig,
end_of_day => eod
);
-- Mars HMS counter
mars_hms : g23_HMS_counter
PORT MAP (
clk => clock,
reset => reset,
load_enable => NOT sync_mars OR date_reached_sig,
count_enable => mpulse,
dst => '0',
h_set => mars_hour_set,
m_set => mars_min_set,
s_set => mars_sec_set,
h_inc => mars_h_inc,
m_inc => mars_mi_inc,
s_inc => mars_s_inc,
hours => mars_hour_sig,
minutes => mars_min_sig,
seconds => mars_sec_sig
);
-- UTC to MTC
utc_mtc : g23_UTC_to_MTC
PORT MAP (
clock => clock,
reset => reset,
enable => NOT sync_mars,
Year => earth_year_sig(11 downto 0),
Month => earth_month_sig,
Day => earth_day_sig,
Hour => earth_hour_sig,
Minute => earth_min_sig,
Second => earth_sec_sig,
Mars_hours => mars_hour_set,
Mars_minutes => mars_min_set,
Mars_seconds => mars_sec_set,
Date_is_reached => date_reached_sig
);
Date_is_reached <= date_reached_sig;
basic_timer : g23_basic_timer
PORT MAP (
clk => clock,
enable => enable,
reset => reset,
EPULSE => epulse,
MPULSE => mpulse
);
--LCD outputs
decode_3 : g23_7_segment_decoder
PORT MAP (
code => bcd_digits(15 downto 12),
RippleBlank_In => '1',
RippleBlank_Out => RB_Out3,
segments => digit_3
);
decode_2 : g23_7_segment_decoder
PORT MAP (
code => bcd_digits(11 downto 8),
RippleBlank_In => RB_Out3,
RippleBlank_Out => RB_Out2,
segments => digit_2
);
decode_1 : g23_7_segment_decoder
PORT MAP (
code => bcd_digits(7 downto 4),
RippleBlank_In => RB_Out2,
segments => digit_1
);
decode_0 : g23_7_segment_decoder
PORT MAP (
code => bcd_digits(3 downto 0),
RippleBlank_In => '0',
segments => digit_0
);
END alpha; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_on is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_on;
architecture imp of hwt_led_on is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '1';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_on is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_on;
architecture imp of hwt_led_on is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '1';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY shd_pe_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END shd_pe_fifo;
ARCHITECTURE shd_pe_fifo_arch OF shd_pe_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF shd_pe_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF shd_pe_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF shd_pe_fifo_arch : ARCHITECTURE IS "shd_pe_fifo,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF shd_pe_fifo_arch: ARCHITECTURE IS "shd_pe_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END shd_pe_fifo_arch;
|
--
-- SpaceWire core with character-stream interface.
--
-- This entity provides a SpaceWire core with a character-stream interface.
-- The interface provides means for connection initiation, sending and
-- receiving of N-Chars and TimeCodes, and error reporting.
--
-- This entity instantiates spwlink, spwrecv, spwxmit and one of the
-- spwrecvfront implementations. It also implements a receive FIFO and
-- a transmit FIFO.
--
-- The SpaceWire standard requires that each transceiver use an initial
-- signalling rate of 10 Mbit/s. This implies that the system clock frequency
-- must be a multiple of 10 MHz. See the manual for further details on
-- bitrates and clocking.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwstream is
generic (
-- System clock frequency in Hz.
-- This must be set to the frequency of "clk". It is used to setup
-- counters for reset timing, disconnect timeout and to transmit
-- at 10 Mbit/s during the link handshake.
sysfreq: real := 200000000.0;
-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
-- This must be set to the frequency of "txclk". It is used to
-- transmit at 10 Mbit/s during the link handshake.
txclkfreq: real := 0.0;
-- Selection of a receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
-- Maximum number of bits received per system clock
-- (must be 1 in case of impl_generic).
rxchunk: integer range 1 to 4 := 1;
-- Selection of a transmitter implementation.
tximpl: spw_implementation_type := impl_generic;
-- Size of the receive FIFO as the 2-logarithm of the number of bytes.
-- Must be at least 6 (64 bytes).
rxfifosize_bits: integer range 6 to 14 := 11;
-- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
txfifosize_bits: integer range 2 to 14 := 11
);
port (
-- System clock.
clk: in std_logic;
-- Receiver sample clock (only for impl_fast)
rxclk: in std_logic;
-- Transmit clock (only for impl_fast)
txclk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Enables automatic link start on receipt of a NULL character.
autostart: in std_logic;
-- Enables link start once the Ready state is reached.
-- Without autostart or linkstart, the link remains in state Ready.
linkstart: in std_logic;
-- Do not start link (overrides linkstart and autostart) and/or
-- disconnect a running link.
linkdis: in std_logic;
-- Scaling factor minus 1, used to scale the transmit base clock into
-- the transmission bit rate. The system clock (for impl_generic) or
-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
-- Changing this signal will immediately change the transmission rate.
-- During link setup, the transmission rate is always 10 Mbit/s.
txdivcnt: in std_logic_vector(7 downto 0);
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside the entity until it can be processed.
tick_in: in std_logic;
-- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
ctrl_in: in std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
time_in: in std_logic_vector(5 downto 0);
-- Pulled high by the application to write an N-Char to the transmit
-- queue. If "txwrite" and "txrdy" are both high on the rising edge
-- of "clk", a character is added to the transmit queue.
-- This signal has no effect if "txrdy" is low.
txwrite: in std_logic;
-- Control flag to be sent with the next N_Char.
-- Must be valid while txwrite is high.
txflag: in std_logic;
-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while txwrite is high.
txdata: in std_logic_vector(7 downto 0);
-- High if the entity is ready to accept an N-Char for transmission.
txrdy: out std_logic;
-- High if the transmission queue is at least half full.
txhalff: out std_logic;
-- High for one clock cycle if a TimeCode was just received.
tick_out: out std_logic;
-- Control bits of the last received TimeCode.
ctrl_out: out std_logic_vector(1 downto 0);
-- Counter value of the last received TimeCode.
time_out: out std_logic_vector(5 downto 0);
-- High if "rxflag" and "rxdata" contain valid data.
-- This signal is high unless the receive FIFO is empty.
rxvalid: out std_logic;
-- High if the receive FIFO is at least half full.
rxhalff: out std_logic;
-- High if the received character is EOP or EEP; low if the received
-- character is a data byte. Valid if "rxvalid" is high.
rxflag: out std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid if "rxvalid" is high.
rxdata: out std_logic_vector(7 downto 0);
-- Pulled high by the application to accept a received character.
-- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
-- a character is removed from the receive FIFO and "rxvalid", "rxflag"
-- and "rxdata" are updated.
-- This signal has no effect if "rxvalid" is low.
rxread: in std_logic;
-- High if the link state machine is currently in the Started state.
started: out std_logic;
-- High if the link state machine is currently in the Connecting state.
connecting: out std_logic;
-- High if the link state machine is currently in the Run state, indicating
-- that the link is fully operational. If none of started, connecting or running
-- is high, the link is in an initial state and the transmitter is not yet enabled.
running: out std_logic;
-- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errdisc: out std_logic;
-- Parity error detected in state Run. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errpar: out std_logic;
-- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
-- the link. This indication is auto-clearing.
erresc: out std_logic;
-- Credit error detected. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errcred: out std_logic;
-- Data In signal from SpaceWire bus.
spw_di: in std_logic;
-- Strobe In signal from SpaceWire bus.
spw_si: in std_logic;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwstream;
architecture spwstream_arch of spwstream is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- Reset time (6.4 us) in system clocks
constant reset_time: integer := integer(sysfreq * 6.4e-6);
-- Disconnect time (850 ns) in system clocks
constant disconnect_time: integer := integer(sysfreq * 850.0e-9);
-- Initial tx clock scaler (10 Mbit).
type impl_to_real_type is array(spw_implementation_type) of real;
constant tximpl_to_txclk_freq: impl_to_real_type :=
(impl_generic => sysfreq, impl_fast => txclkfreq);
constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
constant default_divcnt: std_logic_vector(7 downto 0) :=
std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
-- Registers.
type regs_type is record
-- packet state
rxpacket: std_logic; -- '1' when receiving a packet
rxeep: std_logic; -- '1' when rx EEP character pending
txpacket: std_logic; -- '1' when transmitting a packet
txdiscard: std_logic; -- '1' when discarding a tx packet
-- FIFO pointers
rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
-- FIFO state
rxfifo_rvalid: std_logic; -- '1' if s_rxfifo_rdata is valid
txfifo_rvalid: std_logic; -- '1' if s_txfifo_rdata is valid
rxfull: std_logic; -- '1' if RX fifo is full
rxhalff: std_logic; -- '1' if RX fifo is at least half full
txfull: std_logic; -- '1' if TX fifo is full
txhalff: std_logic; -- '1' if TX fifo is at least half full
rxroom: std_logic_vector(5 downto 0);
end record;
constant regs_reset: regs_type := (
rxpacket => '0',
rxeep => '0',
txpacket => '0',
txdiscard => '0',
rxfifo_raddr => (others => '0'),
rxfifo_waddr => (others => '0'),
txfifo_raddr => (others => '0'),
txfifo_waddr => (others => '0'),
rxfifo_rvalid => '0',
txfifo_rvalid => '0',
rxfull => '0',
rxhalff => '0',
txfull => '0',
txhalff => '0',
rxroom => (others => '0') );
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Interface signals to components.
signal recv_rxen: std_logic;
signal recvo: spw_recv_out_type;
signal recv_inact: std_logic;
signal recv_inbvalid: std_logic;
signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
signal xmiti: spw_xmit_in_type;
signal xmito: spw_xmit_out_type;
signal xmit_divcnt: std_logic_vector(7 downto 0);
signal linki: spw_link_in_type;
signal linko: spw_link_out_type;
-- Memory interface signals.
signal s_rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
signal s_rxfifo_rdata: std_logic_vector(8 downto 0);
signal s_rxfifo_wen: std_logic;
signal s_rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
signal s_rxfifo_wdata: std_logic_vector(8 downto 0);
signal s_txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
signal s_txfifo_rdata: std_logic_vector(8 downto 0);
signal s_txfifo_wen: std_logic;
signal s_txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
signal s_txfifo_wdata: std_logic_vector(8 downto 0);
begin
-- Instantiate link controller.
link_inst: spwlink
generic map (
reset_time => reset_time )
port map (
clk => clk,
rst => rst,
linki => linki,
linko => linko,
rxen => recv_rxen,
recvo => recvo,
xmiti => xmiti,
xmito => xmito );
-- Instantiate receiver.
recv_inst: spwrecv
generic map(
disconnect_time => disconnect_time,
rxchunk => rxchunk )
port map (
clk => clk,
rxen => recv_rxen,
recvo => recvo,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits );
-- Instantiate transmitter.
xmit_sel0: if tximpl = impl_generic generate
xmit_inst: spwxmit
port map (
clk => clk,
rst => rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
xmit_sel1: if tximpl = impl_fast generate
xmit_fast_inst: spwxmit_fast
port map (
clk => clk,
txclk => txclk,
rst => rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
-- Instantiate receiver front-end.
recvfront_sel0: if rximpl = impl_generic generate
recvfront_generic_inst: spwrecvfront_generic
port map (
clk => clk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
recvfront_sel1: if rximpl = impl_fast generate
recvfront_fast_inst: spwrecvfront_fast
generic map (
rxchunk => rxchunk )
port map (
clk => clk,
rxclk => rxclk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
-- Instantiate RX memory.
rxmem: spwram
generic map (
abits => rxfifosize_bits,
dbits => 9 )
port map (
rclk => clk,
wclk => clk,
ren => '1',
raddr => s_rxfifo_raddr,
rdata => s_rxfifo_rdata,
wen => s_rxfifo_wen,
waddr => s_rxfifo_waddr,
wdata => s_rxfifo_wdata );
-- Instantiate TX memory.
txmem: spwram
generic map (
abits => txfifosize_bits,
dbits => 9 )
port map (
rclk => clk,
wclk => clk,
ren => '1',
raddr => s_txfifo_raddr,
rdata => s_txfifo_rdata,
wen => s_txfifo_wen,
waddr => s_txfifo_waddr,
wdata => s_txfifo_wdata );
-- Combinatorial process
process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread) is
variable v: regs_type;
variable v_tmprxroom: unsigned(rxfifosize_bits-1 downto 0);
variable v_tmptxroom: unsigned(txfifosize_bits-1 downto 0);
begin
v := r;
v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
-- Keep track of whether we are sending and/or receiving a packet.
if linko.rxchar = '1' then
-- got character
v.rxpacket := not linko.rxflag;
end if;
if linko.txack = '1' then
-- send character
v.txpacket := not s_txfifo_rdata(8);
end if;
-- Update RX fifo pointers.
if (rxread = '1') and (r.rxfifo_rvalid = '1') then
-- read from fifo
v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
end if;
if r.rxfull = '0' then
if (linko.rxchar = '1') or (r.rxeep = '1') then
-- write to fifo (received char or pending EEP)
v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
end if;
v.rxeep := '0';
end if;
-- Keep track of whether the RX fifo contains valid data.
-- (use new value of rxfifo_raddr)
v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
-- Update room in RX fifo (use new value of rxfifo_waddr).
v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
v.rxfull := bool_to_logic(v_tmprxroom = 0);
v.rxhalff := not v_tmprxroom(v_tmprxroom'high);
if v_tmprxroom > 63 then
v.rxroom := (others => '1');
else
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0));
end if;
-- Update TX fifo pointers.
if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
-- read from fifo
v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
if s_txfifo_rdata(8) = '1' then
v.txdiscard := '0'; -- got EOP/EEP, stop discarding data
end if;
end if;
if (r.txfull = '0') and (txwrite = '1') then
-- write to fifo
v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
end if;
-- Keep track of whether the TX fifo contains valid data.
-- (use new value of txfifo_raddr)
v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
-- Update room in TX fifo (use new value of txfifo_waddr).
v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
v.txfull := bool_to_logic(v_tmptxroom = 0);
v.txhalff := not v_tmptxroom(v_tmptxroom'high);
-- If the link is lost, set a flag to discard the current packet.
if linko.running = '0' then
v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket
v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket
v.rxpacket := '0';
v.txpacket := '0';
end if;
-- Clear the discard flag when the link is explicitly disabled.
if linkdis = '1' then
v.txdiscard := '0';
end if;
-- Drive control signals to RX fifo.
s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr
s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep);
s_rxfifo_waddr <= r.rxfifo_waddr;
if r.rxeep = '1' then
s_rxfifo_wdata <= "100000001";
else
s_rxfifo_wdata <= linko.rxflag & linko.rxdata;
end if;
-- Drive control signals to TX fifo.
s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr
s_txfifo_wen <= (not r.txfull) and txwrite;
s_txfifo_waddr <= r.txfifo_waddr;
s_txfifo_wdata <= txflag & txdata;
-- Drive inputs to spwlink.
linki.autostart <= autostart;
linki.linkstart <= linkstart;
linki.linkdis <= linkdis;
linki.rxroom <= r.rxroom;
linki.tick_in <= tick_in;
linki.ctrl_in <= ctrl_in;
linki.time_in <= time_in;
linki.txwrite <= r.txfifo_rvalid and not r.txdiscard;
linki.txflag <= s_txfifo_rdata(8);
linki.txdata <= s_txfifo_rdata(7 downto 0);
-- Drive divcnt input to spwxmit.
if linko.running = '1' then
xmit_divcnt <= txdivcnt;
else
xmit_divcnt <= default_divcnt;
end if;
-- Drive outputs.
txrdy <= not r.txfull;
txhalff <= r.txhalff;
tick_out <= linko.tick_out;
ctrl_out <= linko.ctrl_out;
time_out <= linko.time_out;
rxvalid <= r.rxfifo_rvalid;
rxhalff <= r.rxhalff;
rxflag <= s_rxfifo_rdata(8);
rxdata <= s_rxfifo_rdata(7 downto 0);
started <= linko.started;
connecting <= linko.connecting;
running <= linko.running;
errdisc <= linko.errdisc;
errpar <= linko.errpar;
erresc <= linko.erresc;
errcred <= linko.errcred;
-- Reset.
if rst = '1' then
v.rxpacket := '0';
v.rxeep := '0';
v.txpacket := '0';
v.txdiscard := '0';
v.rxfifo_raddr := (others => '0');
v.rxfifo_waddr := (others => '0');
v.txfifo_raddr := (others => '0');
v.txfifo_waddr := (others => '0');
v.rxfifo_rvalid := '0';
v.txfifo_rvalid := '0';
end if;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwstream_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity adder is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of adder is
begin
process(a, b) begin
y <= a + b;
end process;
end BH;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity adder is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of adder is
begin
process(a, b) begin
y <= a + b;
end process;
end BH;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: halfaddr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity halfaddr is
port(a, b : in std_logic;
sum, c_out : out std_logic);
end entity halfaddr;
architecture arch_halfaddr of halfaddr is
begin
sum <= a xor b;
c_out <= a and b;
end architecture arch_halfaddr;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNOXVOQUET is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 24) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
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