content stringlengths 1 1.04M ⌀ |
|---|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE I... |
entity FIFO is
end entity FIFO;
entity --Comment
--Comment
--Comment
FIFO is
end entity
FIFO;
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr;... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shifter is
port(
ib : in std_logic_vector(31 downto 0);
shdir : in std_logic;
shamt : in std_logic_vector(4 downto 0);
q : out std_logic_vector(31 downto 0)
);
end shifter;
architecture behv of shifter... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:42:50 01/12/2014
-- Design Name:
-- Module Name: peripherics - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
-- tb.vhd : FPGA top level testbench
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.s... |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-----------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.nexys4_pack.all;
use work.plasoc_interconnect_crossbar_wrap_pack.plasoc_interconnect_crossbar_wrap;
use work.plasoc_interconnect_crossbar_wrap_pack.clogb2;
use work.plasoc_cpu_0_crossbar_wrap_pack.plasoc_cpu_0... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ShiftRegister is
Port ( CLK : in STD_LOGIC;
signalOutput : out My_STD_LOGIC_VECTOR); -- missing `(7 downto 0)` here
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal Q : STD_LOGIC_VECTOR (7 downto 0) := "10011000";
begin
... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_McEliece_QD-Goppa_Decrypt_v4
-- Module Name: Tb_McEliece_QD-Goppa_Decrypt_v4... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_fifo is
port(
atm : in vl_logic_vector(35 downto 0);
clk : in vl_logic;
dbrk_traceme : in vl_logic;
dbrk_traceoff : in vl_logic;
dbrk_traceon : in ... |
-- NEED RESULT: ARCH00035.P1: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P2: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P3: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH000... |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : ... |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : ... |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : ... |
package repro is
function return_true return boolean;
end repro;
package body repro is
function slv_ones(constant width : in integer) return bit_vector is
begin
return (1 to width => '1');
end function;
function return_true return boolean is
constant ones_c : bit_vector(31 downto 0) := slv_ones(32... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:50 04/20/2016
-- Design Name:
-- Module Name: /home/tj/Desktop/UMD_RISC-16G5/ProjectLab2/Combined/Combined_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-------------------------------------------------------------------------------
--
-- Title : xor2
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : xor2.vhd
-- Generated : Fr... |
-------------------------------------------------------------------------------
--
-- Title : xor2
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : xor2.vhd
-- Generated : Fr... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Simple output buffer for simulation target.
-------------------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Simple output buffer for simulation target.
-------------------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Simple output buffer for simulation target.
-------------------------------------------------------------------------... |
entity test is
end test;
architecture behv of test is
-- Crash "** Fatal: tree kind T_TYPE_CONV does not have item I_ATTRS"
constant AWIDTH : integer := integer(4); -- or natural
signal a : bit_vector (AWIDTH downto 0);
begin
end behv;
|
entity test is
end test;
architecture behv of test is
-- Crash "** Fatal: tree kind T_TYPE_CONV does not have item I_ATTRS"
constant AWIDTH : integer := integer(4); -- or natural
signal a : bit_vector (AWIDTH downto 0);
begin
end behv;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_171 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_171;
architecture augh of add_171 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_171 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_171;
architecture augh of add_171 is
signal carry_inA : std_l... |
-- NEED RESULT: ARCH00493: Aggregates with others choice associated with function return (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use work.wbgen2_pkg.all;
entity wbgen2_fifo_sync is
generic (
g_width : integer;
g_size : integer;
g_usedw_size : integer);
port
(
clk_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : i... |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin
process
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word : integer := 1024;
begin end process;
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00421: Block statements passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
--... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
c <= d;
FOR_LABEL: for i in 0 to 7 generate
end generate;
a <= b;
IF_LABEL : if a ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
-- Copyright (C) 2022 Nick Gasson
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation; either version... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_565;
architecture augh of mul_565 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_565;
architecture augh of mul_565 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
o : out std_logic
);
end;
architecture a of ent is
begin
end;
|
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
u... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RAM_ARBITER_TEST IS
END RAM_ARBITER_TEST;
ARCHITECTURE behavior OF RAM_ARBITER_TEST IS
COMPONENT RAM_ARBITER_NEW
PORT(
RST_N : IN std_logic;
CLOCK : IN std_logic;
RST_DONE : OUT std_logic;
RD_EN_C1 : IN std_logic;
WR_EN_C1 : IN std_logic;
RDADDR_C1 : IN std_logic... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity add03 is
port (
a, b : std_logic_vector(8 DOWNTO 0);
borrow : std_logic;
res : out std_logic_vector(8 DOWNTO 0));
end add03;
LIBRARY ieee;
USE ieee.std_logic_arith.all;
architecture behav of add03 is
signal t : signed(8 DOWNTO 0);
begin
t <= signed(... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std... |
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.general_pkg.all;
entity dynamic_uart_tx is
port(
clk : in std_logic;
srst : in std_logic;
clocks_per_bit : in unsigned(15 downto 0); -- minimum 4, reccommended 16+
data_bits : in uns... |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Founda... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:01 11/26/2013
-- Design Name:
-- Module Name: Wing_VGA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity periferico_io is
Port ( reset : i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY testMUX IS
END testMUX;
Architecture Test OF testMUX IS
COMPONENT mux IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e, f : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END COMPONE... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- SHA256 Hashing Module - Testbench
-- Kristian Klomsten Skordal <kristian.skordal@wafflemail.net>
library ieee;
use ieee.std_logic_1164.all;
entity tb_sha256 is
end entity tb_sha256;
architecture testbench of tb_sha256 is
-- Input signals:
signal reset : std_logic := '0';
signal update : std_logic := '0';
sign... |
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
end process;
end architecture RTL;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity projeto1 is
port(
clock : in std_logic;
direction, reset : in std_logic := '0';
enable : in std_logic := '1';
q : out std_logic_vector (3 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
process (clock,... |
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