content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- fsm.vhd: Finite State Machine
-- Author(s):
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity fsm is
port(
... |
library ieee;
use ieee.std_logic_1164.all;
entity topo_comparadores is
port (SEQ_3, SEQ_2, SEQ_1, SEQ_0 : IN STD_LOGIC_VECTOR(4 downto 0);
CONTA_DES: IN STD_LOGIC_VECTOR(9 downto 0);
TESTE_PASS: IN STD_LOGIC;
PASS_CERTO, SALDO : OUT STD_LOGIC
);
end topo_comparadores;
architecture topo_comparadores_arch of to... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:34 2019
-- Host : varun-laptop running 64-bit Service ... |
-- $Id: $
-- File name: tb_ClkDivide.vhd
-- Created: 2/29/2012
-- Author: David Kauer
-- Lab Section: 2
-- Version: 1.0 Initial Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_SpiClkDivide is
generic( CLK_PERIOD : Time := 10 ns );
end tb_SpiClkDivide;
archi... |
-- Hello world program.
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
begin
process
variable l : line;
begin
write (l, String'("Hello world!"));
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: fp_sub.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
library verilog;
use verilog.vl_types.all;
entity meio_somador3 is
port(
a : in vl_logic;
b : in vl_logic;
c : in vl_logic;
soma : out vl_logic;
cout : out vl_logic
);
end meio_somador3;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY genAND IS
GENERIC
(
size : integer
);
PORT
(
input0 : IN std_logic_vector(size-1 downto 0);
input1 : IN std_logic_vector(size-1 downto 0);
output : OUT std_logic_vector(size-1 downto 0)
);
END genAND;
ARCHITECTURE behavior OF genAND IS
... |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity epdm_tb is
generic
(
TUNING_WORD_N : positive := 22
);
end entity;
architecture rtl of epdm_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk... |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_performance_monitors is
end usb_system_cpu_nios2_performance_monitors;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Teste da entidade or3.
library ieee;
use ieee.std_logic_1164.all;
entity or3_tb is
end or3_tb;
architecture logica of or3_tb is
-- Declaração do componente.
component or3
port (a,b,c: in std_logic; y: out std... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
library IEEE;
use IEEE.std_logic_1164.all;
entity fulladder is
port(a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end entity fulladder;
architecture structeral of fulladder is
begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (a and c_in) or (b and c_in);
end architecture;
|
-------------------------------------------------------------------------------
-- leon3_zc702_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.s... |
-------------------------------------------------------------------------------
-- leon3_zc702_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.s... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:55:45 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.1... |
----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince-Ringuet
-- Engineer:
--
-- Create Date: 11:58:40 10/14/2011
-- Design Name:
-- Module Name: eth_tx_stream - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Desc... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY prbs_tb IS
END prbs_tb;
ARCHITECTURE behavior OF prbs_tb IS
-- Component Declaration
COMPONENT PRBS
PORT ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:15:39 04/13/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab2/ProgramCounter/ProgramCounter/IM_tb.vhd
-- Project Name: ProgramCounter
-- Target Device:
-- ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major rel... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity foo is end;
architecture bar of foo is
type BIT is ('0', '1');
type COMP is record
a : BIT;
b : BIT;
end record;
procedure prok is begin
-- name
X := '0';
-- positional array aggregate
(X,Y) := "00";
-- named array aggregate
(1 => X, 0 => Y) := "00";
-- mixed array aggregate
(X, 1 => Y... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library verilog;
use verilog.vl_types.all;
entity NbitCounter_vlg_sample_tst is
port(
clear : in vl_logic;
clk : in vl_logic;
enable : in vl_logic;
sampler_tx : out vl_logic
);
end NbitCounter_vlg_sample_tst;
|
altaccumulate3_inst : altaccumulate3 PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
result => result_sig
);
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rom is
port(
clk: in std_logic;
address: in unsigned(10 downto 0); -- 2^11 addresses
data: out unsigned(14 downto 0) --words are 15 bits wide
);
end entity;
architecture a_rom of rom is
type mem is array (0 to 64) of... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
library ieee;
use ieee.std_logic_1164.all;
entity add32 is
port ( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end entity add32;
architecture Behaviora... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vComponents.all;
package vga_mouse_pkg is
--- TOP LEVEL COMPONENTS ---
component mousecomp
port (
clk : in std_logic;
resolution : in ... |
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
----------------------------------... |
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
----------------------------------... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===============================... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may ... |
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic... |
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture structure of FIFOSyncTop is
component FIFODualPortRam
Generic (
DataWidth : integer range 2 to 64 := 8;
AdressWidth : integer range 2 to 10 := 4);
Port (
Reset_n_i : in STD_LOGIC;
ClkA : in STD_LOGIC;
DataA_i : in STD_LOGIC_VECTOR (DataWidth - 1 ... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- cb20_gpio_block_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 4;
AV_DATA_W ... |
-- NEED RESULT: ARCH00673: Variable values persist over simulation time passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-----------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pixel_difference_2d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid ... |
library verilog;
use verilog.vl_types.all;
entity color_mapper is
port(
BallX : in vl_logic;
BallY : in vl_logic;
Ball_size : in vl_logic;
BlockX : in vl_logic;
BlockY : in vl_logic;
Block_size : in ... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_ROM_SCREEN
-- AUTHORS: Tomáš Bannert <xbanne00@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please... |
-- 2-input single-bit multiplexer
-- this circuit takes two single-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2_single_bit is
port (
-- inputs
in_signal_0 : in ... |
-- Projeto gerado via script.
-- Data: Sáb,31/12/2011-01:19:07
-- Autor: rogerio
-- Comentario: Descrição da Entidade: or2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity or2 is
port (a, b: in std_logic; y: out std_logic);
end or2;
architecture logica of or2 is
begin
-... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
|
use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
|
use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top IS
END top;
ARCHITECTURE behavior OF top IS
component packet_simulation port(
clock : IN std_logic;
data_valid: out std_logic;
data_out : out std_logic_vector(7 downto 0);
start_packet: out std_logic;
end_packet : out std_logic
);end c... |
library ieee;
use ieee.std_logic_1164.all;
package wbgen2_pkg is
component wbgen2_dpssram
generic (
g_data_width : natural;
g_size : natural;
g_addr_width : natural;
g_dual_clock : boolean;
g_use_bwsel : boolean);
port (
clk_a_i : in std_logic;
clk_b_i ... |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 22:10:00 12/14/2016
-- Design Name: i2s_tx_tb.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.... |
entity tb_func04 is
end tb_func04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func04 is
signal a, b, r : std_logic_vector(7 downto 0);
begin
dut: entity work.func04
port map (a, b, r);
process
begin
a <= x"5d";
b <= x"78";
wait for 1 ns;
assert r = x"79" severity ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
-- megafunction wizard: %LPM_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mult
-- ============================================================
-- File Name: mult.vhd
-- Megafunction Name(s):
-- lpm_mult
--
-- Simulation Library Files(s):
-- lpm
-- ==============================================... |
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
tx : out std_logic);
end entity;
architecture tb of test is
begin
process
procedure transmit(data : std_logic_vector;
signal tx : out std_logic) is
variable norm : std_logic_vector(data'length - 1 downto 0) := d... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
-- Date : Thu Apr 5 01:27:51 2018
-- Host : varun-laptop running 64-bit Se... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:50:16 10/22/2015
-- Design Name:
-- Module Name: four_bit_nand - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
-- Copyright (c) 2019 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including... |
-- Copyright (c) 2019 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depe... |
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depe... |
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depe... |
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depe... |
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
... |
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
end generate;
GEN_LABEL : case expression generate
end GENERATE;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:06 2017
-- Host : WK117 running 64-bit major release ... |
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