content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 23-02-2016
-- Module Name: crc_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.al... |
entity repro1 is
generic (c : natural := 4);
end repro1;
architecture behav of repro1 is
constant cmap : string (1 to 5) :=
(1 => 'a', 2 => 'b', 3 => 'c', 4 => 'd', 5 => 'e');
begin
process
variable v : character;
begin
v := cmap (c);
assert v = 'd' report "bad value" severity error;
wait;
... |
entity repro1 is
generic (c : natural := 4);
end repro1;
architecture behav of repro1 is
constant cmap : string (1 to 5) :=
(1 => 'a', 2 => 'b', 3 => 'c', 4 => 'd', 5 => 'e');
begin
process
variable v : character;
begin
v := cmap (c);
assert v = 'd' report "bad value" severity error;
wait;
... |
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
... |
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
... |
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- system_ac1_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_0... |
component osc is
port (
clkout : out std_logic; -- clk
oscena : in std_logic := 'X' -- oscena
);
end component osc;
u0 : component osc
port map (
clkout => CONNECTED_TO_clkout, -- clkout.clk
oscena => CONNECTED_TO_oscena -- oscena.oscena
);
|
-------------------------------------------------------------------------------
-- Title : Package for Ultrasonic transmitter
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Package for Ultrasonic transmitter
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_Controller is
port(
CLKin : in std_logic;
READADDRin : in std_logic_vector(22 downto 0);
WRITEADDRin : in std_logic_vector(22 downto 0);
DATAin : in std_logic_vector(14 downto 0);
... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator Registers
--------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
-- ********************
-- * Flip Flop tipo D *
-- ********************
-- Con reinicio asíncrono y activador
library ieee; use ieee.std_logic_1164.all;
entity ffden is
port(
clk, rst: in std_logic;
en: in std_logic; -- Activador
d: in std_logic;
q: out std_logic
);
end ffden;
architec... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 10:33:26 09/30/2015
-- Design Name:
-- Module Name: D_Type_FFs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descript... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- NEED RESULT: ARCH00320.P2: Execution continues with first statement after last statement in process is executed passed
-- NEED RESULT: ARCH00320.P1: Execution continues with first statement after last statement in process is executed passed
--------------------------------------------------------------------------... |
entity tb_arr04 is
end tb_arr04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr04 is
signal clk : std_logic;
signal rst : std_logic;
signal sel_i : std_logic;
signal v : std_logic;
signal r : std_logic_vector(0 to 1);
begin
dut: entity work.arr04
port map (clk => clk, rst => r... |
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further informati... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-------------------------------------------------------------------------------
-- Title : FSMC Slave, synchronous
-------------------------------------------------------------------------------
-- Author : Carl Treudler (Carl.Treudler@DLR.de)
-----------------------------------------------------------------------... |
-- file: UARTClockManager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer ... |
-- $Id: sys_tst_mig_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_mig_arty - syn
-- Description: ... |
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc... |
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc... |
----------------------------------------------------------------------------------
-- Data de criação: 18 de setembro de 2014;
-- Module Name: Teste de interface de recepção de dados;
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LO... |
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_dezctr is
end tb_dezctr;
-- Beim Testen den Prescaler anpassen
architecture sim of tb_dezctr is
component dezctr
port (
clk50 : in std_logic;
reset_n : in std_logic;
sw_i : in std_logic_vector(9 downto 0);
pb_i : in st... |
---------------------------------------------------------------------
-- Instruction fetch
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The first stage of the LXP32 pipeline.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.a... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_arith.ALL;
entity dynamic is
port (
clk_1hz : in std_logic;
leds : out std_logic_vector(3 downto 0)
);
end dynamic;
architecture Behavioral of dynamic is
signal output : std_logic_vecto... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Interrupt Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric... |
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and m... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}... |
-------------------------------------------------------------------------------
-- Title : u2p_nios_ddr2
-- Author : Gideon Zweijtzer <gideon.zweijtzer@technolution.eu>
-------------------------------------------------------------------------------
-- Description: Toplevel with just the alt-mem phy. Testing an... |
-- cb20_pwm_interface_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 6;
AV_DATA_... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Simple SD and MMC model
--
-- $Id: card.vhd,v 1.2 2005-02-13 17:06:22 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and us... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Control Circuit (FSM)
ENTITY control_circuit IS
PORT (
clock, reset : IN STD_LOGIC;
func : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
done, A_in, G_in, G_out, extern, R0_in, R1_in : OUT STD_LOGIC :=... |
-- $Id: tb_cdata2byte.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_cdata2byte - sim
-- Description: Test ben... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RomSmelk3006 is
port (
clk : in std_logic;
addr : in std_logic_vector(13 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of RomSmelk3006 is
... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--======================================================================
-- sim.vhd :: SOC simulation testbench
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity TEST_TOP is
end TE... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_packet_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_packet_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--... |
---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmRom
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (
INT : integer := -25;
SL : std_logic := '1'
);
port (
a : in signed(7 downto 0);
b : in signed(7 downto 0);
const : out signed(7 downto 0);
absolute1 : out unsigned(7 downto 0);
absolute2 : out unsigned(7 do... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
component nios_system is
port (
alu_a_export : out std_logic_vector(31 downto 0); -- export
alu_b_export : out std_logic_vector(31 downto 0); -- export
alu_carry_out_export : in std_logic := 'X'; -- export
... |
-------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
---------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
---------------------------------------------------------------------... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY tb_controller IS
END tb_controller;
ARCHITECTURE behavior OF tb_controller IS
--Inputs
SIGNAL tb_opcode : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_regDst : std_logic;
SIGNAL tb_jump : std_logic... |
-- $Id: rlink_cext_vhpi.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: rlink_cext_vhpi
-- Description: VHDL ... |
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:43:34 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bi... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : BusMonCore.vhd
-- /_... |
library ieee;
use ieee.std_logic_1164.all;
entity tb_and6 is
end tb_and6;
architecture behav of tb_and6 is
signal i0, i1, i2, i3, i4, i5 : std_logic;
signal o : std_logic;
begin
dut : entity work.and6
port map (i0 => i0, i1 => i1, i2 => i2, i3 => i4, i4 => i4,
i5 => i5, o => o);
process
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prova is
port(
entrada : in std_logic_vector (6 downto 0) := "0000000";
display : out std_logic_vector (6 downto 0)
);
end prova;
architecture Behavioral of prova is
signal bcd : std_logic_vector (6 downto 0);
begin
-- BCD.
process (entrada)
begin
if (entrad... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY principal_tb IS
END principal_tb;
ARCHITECTURE behavior OF principal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MODULOPRINCIPAL
PORT(
rst : IN std_logic;
CLK : IN std_logic;
ALURE... |
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00619.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00619.P2: Multi transport transactions occurred on concurrent signal asg passed
--... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(Num_Hex_Digits: Integer:= 8);
------------... |
library ieee;
use ieee.std_logic_1164.all;
entity theunit is
port (dout : out std_ulogic);
end;
architecture rtl of theunit is
subtype thenum_t is integer range 0 to 1;
type rec_t is record
-- NOTE: changing order of these members prevents crash
data0 : std_ulogic;
bankm : std_ulogic_vector(thenum_t)... |
architecture RTL of FIFO is
begin
block_label : block is begin end block BLOCK_LABEL;
BLOCK_LABEL : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
|
------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity divider_2 is
port( data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector( 10 downto 0));
end divider_2;
architecture behavior of divider_2 is
begin
data_out(6 downto 0)<= data_in(7 downto 1);
data_out(10 downto 7)<=(ot... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:44 06/26/2017
-- Design Name:
-- Module Name: /media/sf_SistemiEmbedded/workbench/ISE/SE/complex_modulus/tb_complex_abs.vhd
-- Project Name: complex_modulus
-- Target Device:
-- Tool v... |
entity test is
type t is range 0 to 1.0E+2;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity exit02 is
port (val : std_logic_vector (3 downto 0);
res : out integer);
end exit02;
architecture behav of exit02 is
function ffs (v : std_logic_vector (3 downto 0)) return natural
is
variable r : natural;
begin
r := 4;
for i in v'reverse_r... |
-- -------------------------------------------------------------
--
-- Entity Declaration for INST_AB_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MI... |
library ieee;
use ieee.std_logic_1164.all;
entity encrypt is
port( data_in: in std_logic_vector(0 to 63);
key: in std_logic_vector(0 to 63);
data_out: out std_logic_vector(0 to 63));
end encrypt;
architecture behavior of encrypt is
component initial_permutation
port( data_in: in std_logic_vector(0 to 63);
pe... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot_f - arch and entity
-----------------------------------------------------------... |
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