tiny-gpu/README.md

tiny-gpu — author's additions only

Upstream: https://github.com/adam-maj/tiny-gpu (MIT). Not mirrored here; see ../THIRD_PARTY.md.

File	What it is
skr_findings.md	Yosys synthesis of the whole design: RTL cells → generic gates, flip-flop flavours, why arithmetic evaporates
FPGA.md	Measured LUT/FF counts across iCE40, ECP5, Gowin, Xilinx 7-series, Intel MAX 10; device fit table; the 183-port-bit wrapper problem
arch.md	The artifact chain: SystemVerilog → sv2v → yosys/netlistsvg → OpenLane GDS → 3D view
docs/schematics/*.svg	RTL schematics per module, from yosys + netlistsvg
gds/built/gpu.gds	The OpenLane/SKY130 place-and-route result built locally (33 MB)
tiny-gpu.edam.json	Edalize project file for the sv2v output