task_id stringlengths 3 21 | task_number int64 1 156 | description stringlengths 28 4.81k | header stringlengths 33 297 | module_code stringlengths 67 1.58k | testbench stringlengths 2.29k 10.3k |
|---|---|---|---|---|---|
mux2to1v | 1 | Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b. | module top_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
| module top_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
module stimulus_gen (
input clk,
output logic [99:0] a,b,
output logic sel,
output reg[511:0] wavedrom_title,
output reg wa... |
m2014_q6b | 2 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Assume that you want to Implement the FSM using three flip-... | module top_module(
input [3:1] y,
input w,
output reg Y2);
| module top_module(
input [3:1] y,
input w,
output reg Y2);
always_comb begin
case ({y, w})
4'h0: Y2 = 1'b0;
4'h1: Y2 = 1'b0;
4'h2: Y2 = 1'b1;
4'h3: Y2 = 1'b1;
4'h4: Y2 = 1'b0;
4'h5: Y2 = 1'b1;
4'h6: Y2 = 1'b0;
4'h7: Y2 = 1'b0;
4'h8: Y2 = 1'b0;
4'h9: Y2 = 1'b1;
4'ha: Y2 = 1'b1;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input [3:1] y,
input w,
output reg Y2);
always_comb begin
case ({y, w})
4'h0: Y2 = 1'b0;
4'h1: Y2 = 1'b0;
4'h2: Y2 = 1'b1;
4'h3: Y2 = 1'b1;
4'h4: Y2 = 1'b0;
4'h5: Y2 = 1'b1;
4'h6: Y2 = 1'b0;
4'h7: Y2 = 1'b0;... |
ringer | 3 | Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode... | module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
| module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
module stimulus_gen (
input clk,
output reg ring, vibrate_mode,
output reg[5... |
alwaysblock1 | 4 | Build an AND gate using both an assign statement and a combinational always block. | module top_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
| module top_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title... |
zero | 5 | Build a circuit that always outputs a LOW. | module top_module(
output zero);
| module top_module(
output zero);
assign zero = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
output zero);
assign zero = 1'b0;
endmodule
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// ou... |
circuit7 | 6 | This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time clk a q
// 0ns 0 x x
// 5ns 1 0 x
... | module top_module (
input clk,
input a,
output reg q
);
| module top_module (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
module stimulus_gen (
input clk,
output logic a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module s... |
ece241_2014_q5a | 7 | You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circ... | module top_module (
input clk,
input areset,
input x,
output z
);
| module top_module (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <= x ? B : C;
C: state <= x ? B : C;
endcase
end
end
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <=... |
fsm3 | 8 | The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a positive edge triggered asynchronous reset that resets the FSM to state A.
// state | next state in=0, next state in=1 | output
// A | A, B | 0
// B | C, B | 0
// ... | module top_module (
input clk,
input in,
input areset,
output out
);
| module top_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(pos... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
... |
vector2 | 9 | Build a circuit that reverses the byte order of a 32-bit vector. | module top_module (
input [31:0] in,
output [31:0] out
);
| module top_module (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
module stimulus_gen (
input clk,
output logic [31:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
)... |
m2014_q4c | 10 | Implement a simple D flip flop with active high synchronous reset (reset output to 0). | module top_module (
input clk,
input d,
input r,
output logic q
);
| module top_module (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
module stimulus_gen (
input clk,
output logic d, r
);
initial begin
repeat(100) @(posedge clk, n... |
mt2015_q4a | 11 | Implement the boolean function z = (x^y) & x. | module top_module(
input x,
input y,
output z);
| module top_module(
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(101) @(nege... |
shift18 | 12 | Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by "amount." Assume the right shit is an arithmetic right shift.
// Signals are defined as below:
// (1) load: Loads shift register with data[63:0] instead of shifting. Act... | module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
| module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <=... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q... |
ece241_2013_q8 | 13 | Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have a negative edge triggered asynchronous reset. You may only have 3 states in your... | module top_module (
input clk,
input aresetn,
input x,
output reg z
);
| module top_module (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S1... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (sta... |
m2014_q6 | 14 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Implement this state machine in Verilog. | module top_module (
input clk,
input reset,
input w,
output z
);
| module top_module (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A: next = w ? A : B;
B: next = w ? D : C;
C: next = w ? D... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A... |
fsm_ps2data | 15 | We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM shou... | module top_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
| module top_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
... |
2012_q2b | 16 |
// Consider the state machine shown below:
// A (0) --1--> B
// A (0) --0--> A
// B (0) --1--> C
// B (0) --0--> D
// C (0) --1--> E
// C (0) --0--> D
// D (0) --1--> F
// D (0) --0--> A
// E (1) --1--> E
// E (1) --0--> D
// F (1) --1--> C
// F (1) --0--> D
// Assume that a one-hot code is used with the state assig... | module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
| module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
module stimulus_gen (
input clk,
output logic[5:0] y,
output logic w,
input tb_match
);
int errored1 = 0;... |
vector0 | 17 | Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc. | module top_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
| module top_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
module stimulus_gen (
input clk,
output reg [2:0] vec,
output reg[511:0] wavedrom_title,
outpu... |
kmap4 | 18 | Implement the circuit described by the Karnaugh map below.
// ab
// cd 00 01 11 10
// 00 | 0 | 1 | 0 | 1 |
// 01 | 1 | 0 | 1 | 0 |
// 11 | 0 | 1 | 0 | 1 |
// 10 | 1 | 0 | 1 | 0 | | module top_module (
input a,
input b,
input c,
input d,
output reg out
);
| module top_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out = 1;
4'h5: out = 0;
4'h7: out = 1;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out ... |
vector1 | 19 | Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes. | module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
| module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
module stimulus_gen (
input clk,
output logic [15:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
... |
norgate | 20 | Create a module that implements a NOR gate. | module top_module(
input a,
input b,
output out
);
| module top_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
//... |
alwaysblock2 | 21 | Build an XOR gate three ways, using an assign statement (output out_assign), a combinational always block (output out_always_comb), and a clocked always block (output out_always_ff). Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed. | module top_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
| module top_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
... |
m2014_q6c | 22 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Resets into state A. For this part, assume that a one-hot c... | module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
| module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
module stimulus_gen (
input clk,
output logic[6:1] y,
output logic w,
input tb_match
);
int errored1 = 0;... |
mux256to1 | 23 | Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc. | module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
| module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
module stimulus_gen (
input clk,
output logic [255:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<... |
2014_q4a | 24 | Consider an n-bit shift register circuit. Inputs E are for enabling shift, R for value to load, L is asserted when it should load, and w is the input to the first stage of the shift register. Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers. | module top_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
| module top_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
module stimulus_gen (
input clk,
output logic w, R, E, L
);
initial begin
repeat... |
ece241_2014_q4 | 25 | Given the finite state machine circuit described below, assume that the D flip-flops are initially reset to zero before the machine begins.
// Build this circuit in Verilog.
// Input x goes to three different two-input gates: a XOR, an AND, and a OR gate. Each of the three gates is connected to the input of a D flip-... | module top_module (
input clk,
input x,
output z
);
| module top_module (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
module stimulus_gen (
input clk,
output logic x,
output reg[511:0]... |
circuit4 | 26 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d q
// 0ns 0 0 0 0 0
/... | module top_module (
input a,
input b,
input c,
input d,
output q
);
| module top_module (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to mo... |
rule110 | 27 | Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete). There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the... | module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
| module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |
(q[$bits... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] ... |
fsm3s | 28 | The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous active high reset that resets the FSM to state A.
// State | Next state in=0, Next state in=1 | Output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
/... | module top_module (
input clk,
input in,
input reset,
output out
);
| module top_module (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(pose... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
... |
circuit5 | 29 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d e q
// 0ns x x x x x ... | module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
| module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
module s... |
bugs_mux2 | 30 | Find the bug and fix this 8-bit wide 2-to-1 mux.
// module top_module (
// input sel,
// input [7:0] a,
// input [7:0] b,
// output out );
// assign out = (~sel & a) | (sel & b);
// endmodule | module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
| module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
module stimulus_gen (
input clk,
output logic sel,
output logic [7:0] a, b,
out... |
mt2015_muxdff | 31 | Consider this Verilog module "full_module":
// module full_module (
// input [2:0] r,
// input L,
// input clk,
// output reg [2:0] q
);
// always @(posedge clk) begin
// if (L) begin
// q <= r;
// end else begin
// q <= {q[1] ^ q[2], q[0], q[2]};
// end
// end
// endmodul... | module top_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
| module top_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.
*/
module reference_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
module stimulus_gen... |
edgecapture | 32 | For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (active high synchronous reset). | module top_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
| module top_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
module stimul... |
dff8 | 33 | Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk. | module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
| module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input [7:0] d,
output reg [7:0] q);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
module stimulus_gen (
input clk,
output reg [7:0] d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enabl... |
ece241_2014_q1c | 34 | Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred. | module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
| module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
module stimulus_gen (
input clk,
output logic [7:0] a, ... |
review2015_fsmonehot | 35 | Given the following Moore state machine with 3 input (d, done_counting, ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in the diagram below, assume outputs are 0 and inputs are don't cares.
// S () --d=0--> S
// S () --d=1--> S1
// S1 () --d=0--> S
// S1 () --d=1--> S11
// S11 () --d=0--> S110... | module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
| module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
parameter S=0, S1=1,... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
out... |
counter_2bc | 36 | Build a two-bit saturating counter. The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged. areset is a positive edge triggered asy... | module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
| module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
if(state < 3 && train_taken)
state... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
... |
always_casez | 37 | Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high. | module top_module (
input [7:0] in,
output reg [2:0] pos
);
| module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4;
8'bzz1zzzzz: pos = 3'h5;
8'bz1zzzzzz: pos = 3'h6;
8... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4... |
always_nolatches | 38 | Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif)... | module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
| module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
... |
m2014_q4j | 39 | Implement a 4-bit adder with full adders. The output sum should include the overflow bit. | module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
| module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
assign sum = x+y;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
assign sum = x+y;
endmodule
module stimulus_gen (
input clk,
output logic [3:0] x,y
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{x,y} <= $random;
end
... |
history_shift | 40 | Build a 32-bit global history shift register, including support for rolling back state in response to a pipeline flush caused by a branch misprediction. When a branch prediction is made (predict_valid = 1), shift in predict_taken from the LSB side to update the branch history for the predicted branch. (predict_history[... | module top_module
(
input clk,
input areset,
input predict_valid,
input predict_taken,
output logic [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
| module top_module
(
input clk,
input areset,
input predict_valid,
input predict_taken,
output logic [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
always@(posedge clk, posedge areset)
if (areset) begin
predict_history = 0;... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module
(
input clk,
input areset,
input predict_valid,
input predict_taken,
output logic [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
always@(posedge cl... |
wire_decl | 41 | Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire `out`, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a ... | module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n );
| module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n );
wire w1, w2;
assign w1 = a&b;
assign w2 = c&d;
assign out = w1|w2;
assign out_n = ~out;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
// hdlbits_prop {len: 5}
module reference_module (
input a,
input b,
input c,
input d,
output out,
output out_n );
wire w1, w2;
assign w1 = a&b;
assign w2 = c&d;
assign out = w1|w2;
assign out_n = ~out;
endmodule
module stimulus_gen (
input clk,
... |
dff | 42 | Create a single D flip-flop. | module top_module(
input clk,
input d,
output reg q);
| module top_module(
input clk,
input d,
output reg q);
initial
q = 1'hx;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input d,
output reg q);
initial
q = 1'hx;
always @(posedge clk)
q <= d;
endmodule
module stimulus_gen (
input clk,
output reg d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add tw... |
ece241_2013_q12 | 43 | In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function. First, create an 8-bit shift register with 8 D-type flip-flops. Label th... | module top_module (
input clk,
input enable,
input S,
input A,
input B,
input C,
output reg Z
);
| module top_module (
input clk,
input enable,
input S,
input A,
input B,
input C,
output reg Z
);
reg [7:0] q;
always @(posedge clk) begin
if (enable)
q <= {q[6:0], S};
end
assign Z = q[ {A, B, C} ];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input enable,
input S,
input A,
input B,
input C,
output reg Z
);
reg [7:0] q;
always @(posedge clk) begin
if (enable)
q <= {q[6:0], S};
end
assign Z = q[ {A, B, C} ];
endmodule
module stimulus_gen (
inp... |
thermostat | 44 | A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate. The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, tu... | module top_module(
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
| module top_module(
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
assign fan = (mode ? too_cold : too_hot) | fan_on;
assign heater = (mode & too_cold);
assign aircon = (~mode & too_hot);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
assign fan = (mode ? too_cold : too_hot) | fan_on;
assign heater = (mode & too_cold);
assign aircon = (~mode & too_hot);
en... |
ece241_2013_q2 | 45 | A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, ... | module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
| module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
wire pos0, pos1;
assign out_sop = c&d | ~a&~b&c;
assign pos0 = c & (~b|d)&(~a|b);
assign pos1 = c & (~b|d)&(~a|d);
assign out_pos = (pos0 == pos1) ? pos0 : 1'bx;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
wire pos0, pos1;
assign out_sop = c&d | ~a&~b&c;
assign pos0 = c & (~b|d)&(~a|b);
assign pos1 = c & (~b|d)&(~a|d);
assign out_pos = (pos0 == pos1) ? pos0... |
lfsr32 | 46 | A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce each bit's next value, while bit positions without a tap shift. Build a... | module top_module(
input clk,
input reset,
output reg [31:0] q);
| module top_module(
input clk,
input reset,
output reg [31:0] q);
logic [31:0] q_next;
always@(q) begin
q_next = q[31:1];
q_next[31] = q[0];
q_next[21] ^= q[0];
q_next[1] ^= q[0];
q_next[0] ^= q[0];
end
always @(posedge clk) begin
if (reset)
q <= 32'h1;
else
q <= q_next;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output reg [31:0] q);
logic [31:0] q_next;
always@(q) begin
q_next = q[31:1];
q_next[31] = q[0];
q_next[21] ^= q[0];
q_next[1] ^= q[0];
q_next[0] ^= q[0];
end
always @(posedge clk) begin
if (r... |
circuit3 | 47 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d q
// 0ns 0 0 0 0 0
/... | module top_module (
input a,
input b,
input c,
input d,
output q
);
| module top_module (
input a,
input b,
input c,
input d,
output q
);
assign q = (a|b) & (c|d);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output q
);
assign q = (a|b) & (c|d);
endmodule
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two por... |
7420 | 48 | The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates.
// Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs. | module top_module(
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
| module top_module(
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
assign p1y = ~&( {p1a, p1b, p1c, p1d} );
assign p2y = ~&( {p2a, p2b, p2c, p2d} );
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
assign p1y = ~&( {p1a, p1b, p1c, p1d} );
assign p2y = ~&( {p2a, p2b, p2c, p2d} );
endmodule
module... |
popcount255 | 49 | A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector. | module top_module (
input [254:0] in,
output reg [7:0] out
);
| module top_module (
input [254:0] in,
output reg [7:0] out
);
always_comb begin
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [254:0] in,
output reg [7:0] out
);
always_comb begin
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
module stimulus_gen (
input clk,
output logic [254:0] in,
output reg[511:0] wavedrom_title,
... |
gatesv | 50 | You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:
// (1) out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate i... | module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
| module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = in[2:0] & in[3:1];
assign out_any = in[2:0] | in[3:1];
assign out_different = in^{in[0], in[3:1]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = in[2:0] & in[3:1];
assign out_any = in[2:0] | in[3:1];
assign out_different = in^{in[0], in[3:1]};
endmodule
module s... |
circuit6 | 51 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a q
// 0ns x x
// 5ns x x
// 10ns x x ... | module top_module (
input [2:0] a,
output reg [15:0] q
);
| module top_module (
input [2:0] a,
output reg [15:0] q
);
always @(*)
case (a)
0: q = 4658;
1: q = 44768;
2: q = 10196;
3: q = 23054;
4: q = 8294;
5: q = 25806;
6: q = 50470;
7: q = 12057;
endcase
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [2:0] a,
output reg [15:0] q
);
always @(*)
case (a)
0: q = 4658;
1: q = 44768;
2: q = 10196;
3: q = 23054;
4: q = 8294;
5: q = 25806;
6: q = 50470;
7: q = 12057;
endcase
endmodule
module stimul... |
countslow | 52 | Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the "slowena" input if high indicates when the counter should ... | module top_module(
input clk,
input slowena,
input reset,
output reg [3:0] q);
| module top_module(
input clk,
input slowena,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else if (slowena) begin
if (q == 9)
q <= 0;
else
q <= q+1;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input slowena,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else if (slowena) begin
if (q == 9)
q <= 0;
else
q <= q+1;
end
endmodule
module stimulus_gen (
input cl... |
m2014_q4f | 53 | Implement the following circuit in Verilog. Two inputs (in1 and in2) go to an AND gate, but the in2 input to the AND gate has a bubble. The output of the AND gate is connected to 'out'. | module top_module (
input in1,
input in2,
output logic out
);
| module top_module (
input in1,
input in2,
output logic out
);
assign out = in1 & ~in2;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input in1,
input in2,
output logic out
);
assign out = in1 & ~in2;
endmodule
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
en... |
m2014_q4h | 54 | The module assigns the output port to the same value as the input port combinationally. | module top_module(
input in,
output out);
| module top_module(
input in,
output out);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input in,
output out);
assign out = in;
endmodule
module stimulus_gen (
input clk,
output reg in = 0
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
m... |
fsm1 | 55 | Consider the follow Moore machine with the diagram described below:
// B (1) --0--> A
// B (1) --1--> B
// A (0) --0--> B
// A (0) --1--> A
// Write Verilog implementing this state machine. It should asynchronously reset into state B if reset if high. | module top_module (
input clk,
input in,
input areset,
output out
);
| module top_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1;
reg state;
reg next;
always_comb begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= B;
else s... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1;
reg state;
reg next;
always_comb begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
end
always @(posedge clk, ... |
dualedge | 56 | A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list. Build a circuit that functionally behaves like a dual-edge triggered flip-flop. | module top_module(
input clk,
input d,
output reg q);
| module top_module(
input clk,
input d,
output reg q);
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
reg qp, qn;
always @(posedge clk)
qp <= d;
always @(negedge clk)
qn <= d;
// assign q = clk ? qp : qn; // This causes q to change too early when clk changes. Need delay ... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input d,
output reg q);
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
reg qp, qn;
always @(posedge clk)
qp <= d;
always @(negedge clk)
qn <= d;
// assign q = clk ? qp : qn; // T... |
xnorgate | 57 | Create a module that implements an XNOR gate. | module top_module(
input a,
input b,
output out
);
| module top_module(
input a,
input b,
output out
);
assign out = ~(a^b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out
);
assign out = ~(a^b);
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// ... |
mt2015_q4 | 58 | Module A implements the boolean function z = (x^y) & x.
// Module B can be described by the following simulation waveform:
// time x y z
// 0ns 0 0 1
// 5ns 0 0 1 ... | module top_module(
input x,
input y,
output z);
| module top_module(
input x,
input y,
output z);
assign z = x|~y;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input x,
input y,
output z);
assign z = x|~y;
endmodule
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(100) @(negedge c... |
rotate100 | 59 | Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.
// (1) lo... | module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
| module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena == 2'h1)
q <= {q[0], q[99:1]};
else if (ena == 2'h2)
q <= {q[98:0], q[99]};
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena == 2'h1)
q <= {q[0], q[99:1]};
else if (ena == 2'h2)
q <= {q[98:0], q[9... |
review2015_count1k | 60 | Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is active high synchronous, and should reset the counter to 0. | module top_module(
input clk,
input reset,
output reg [9:0] q);
| module top_module(
input clk,
input reset,
output reg [9:0] q);
always @(posedge clk)
if (reset || q == 999)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output reg [9:0] q);
always @(posedge clk)
if (reset || q == 999)
q <= 0;
else
q <= q+1;
endmodule
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output ... |
notgate | 61 | Create a module that implements a NOT gate. | module top_module(
input in,
output out
);
| module top_module(
input in,
output out
);
assign out = ~in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input in,
output out
);
assign out = ~in;
endmodule
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0... |
fsm_onehot | 62 | Given the follow state machine with 1 input and 2 outputs (the outputs are given as "(out1, out2)"):
// S0 (0, 0) --0--> S0
// S0 (0, 0) --1--> S1
// S1 (0, 0) --0--> S0
// S1 (0, 0) --1--> S2
// S2 (0, 0) --0--> S0
// S2 (0, 0) --1--> S3
// S3 (0, 0) --0--> S0
// S3 (0, 0) --1--> S4
// S4 (0, 0) --0--> S0
// S4 (0, 0... | module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
| module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
assign out1 = state[8] | state[9];
assign out2 = state[7] | state[9];
assign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);
assign next_state[1] = in && (state[0] | state[8] | state[9... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
assign out1 = state[8] | state[9];
assign out2 = state[7] | state[9];
assign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9])... |
ece241_2013_q7 | 63 | A JK flip-flop has the below truth table. Note: Qold is the output of the flip-flop before the positive clock edge.
// J | K | Q
// 0 | 0 | Qold
// 0 | 1 | 0
// 1 | 0 | 1
// 1 | 1 | ~Qold | module top_module (
input clk,
input j,
input k,
output reg Q
);
| module top_module (
input clk,
input j,
input k,
output reg Q
);
always @(posedge clk)
Q <= j&~Q | ~k&Q;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input j,
input k,
output reg Q
);
always @(posedge clk)
Q <= j&~Q | ~k&Q;
endmodule
module stimulus_gen (
input clk,
output logic j, k,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two... |
popcount3 | 64 | A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector. | module top_module (
input [2:0] in,
output [1:0] out
);
| module top_module (
input [2:0] in,
output [1:0] out
);
assign out = in[0]+in[1]+in[2];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [2:0] in,
output [1:0] out
);
assign out = in[0]+in[1]+in[2];
endmodule
module stimulus_gen (
input clk,
output logic [2:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module... |
vector5 | 65 | Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal. Example: out[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^ e. | module top_module (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
| module top_module (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
endmodule
module stimulus_gen (
input clk,
output logic a, b, c, d, e
);
initial ... |
lemmings1 | 66 | The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine. In the Lemmings' 2D world, Lemmings can be in one of two states: walking left (walk_left is 1) or walking right (walk_right is 1). It will switch directions if it hits an obstacle. In par... | module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
| module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
parameter WL=0, WR=1;
reg state;
reg next;
always_comb begin
case (state)
WL: next = bump_left ? WR : WL;
WR: next = bump_right ? WL: WR;
endcase
end
always @(p... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
parameter WL=0, WR=1;
reg state;
reg next;
always_comb begin
case (state)
WL: next = bump_left ? WR : WL;
WR: nex... |
circuit1 | 67 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b q
// 0ns 0 0 0
// 5ns 0 0 0 ... | module top_module (
input a,
input b,
output q
);
| module top_module (
input a,
input b,
output q
);
assign q = a&b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
output q
);
assign q = a&b;
endmodule
module stimulus_gen (
input clk,
output logic a,b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// ou... |
7458 | 68 | The 7458 is a chip with four AND gates and two OR gates. Create a module in Verilog with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an `assign` statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, wher... | module top_module(
input p1a,
input p1b,
input p1c,
input p1d,
input p1e,
input p1f,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
| module top_module(
input p1a,
input p1b,
input p1c,
input p1d,
input p1e,
input p1f,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
assign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};
assign p2y = &{p2a, p2b} | &{p2c, p2d};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input p1a,
input p1b,
input p1c,
input p1d,
input p1e,
input p1f,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
assign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};
assign p2y = &{p2a, p2b} | &{... |
2014_q3c | 69 | Given the state-assigned table shown below, implement the logic functions Y[0] and z.
// Present state y[2:0] | Next state Y[2:0] x=0, Next state Y[2:0] x=1 | Output z
// 000 | 000, 001 | 0
// 001 | 001, 100 | 0
// 010 | 010, 001 | 0
// 011 | 001, 010 | 1
// 100 | 011, 100 | 1
| module top_module (
input clk,
input x,
input [2:0] y,
output reg Y0,
output reg z
);
| module top_module (
input clk,
input x,
input [2:0] y,
output reg Y0,
output reg z
);
always @(*) begin
case ({y[2:0], x})
4'h0: Y0 = 0;
4'h1: Y0 = 1;
4'h2: Y0 = 1;
4'h3: Y0 = 0;
4'h4: Y0 = 0;
4'h5: Y0 = 1;
4'h6: Y0 = 1;
4'h7: Y0 = 0;
4'h8: Y0 = 1;
4'h9: Y0 = 0;
default: Y0 = 1... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input x,
input [2:0] y,
output reg Y0,
output reg z
);
always_comb begin
case ({y[2:0], x})
4'h0: Y0 = 0;
4'h1: Y0 = 1;
4'h2: Y0 = 1;
4'h3: Y0 = 0;
4'h4: Y0 = 0;
4'h5: Y0 = 1;
4'h6: Y0 = 1;
4'h7... |
m2014_q4e | 70 | Implement a 2-input NOR gate. | module top_module (
input in1,
input in2,
output logic out
);
| module top_module (
input in1,
input in2,
output logic out
);
assign out = ~(in1 | in2);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input in1,
input in2,
output logic out
);
assign out = ~(in1 | in2);
endmodule
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
... |
wire4 | 71 | Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: a -> w
// ; b -> x; b -> y; c -> z. | module top_module (
input a,
input b,
input c,
output w,
output x,
output y,
output z );
| module top_module (
input a,
input b,
input c,
output w,
output x,
output y,
output z );
assign {w,x,y,z} = {a,b,b,c};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
output w,
output x,
output y,
output z );
assign {w,x,y,z} = {a,b,b,c};
endmodule
module stimulus_gen (
input clk,
output logic a, b, c,
output reg[511:0] wavedrom_title,
output reg wavedrom_e... |
m2014_q4b | 72 | Implement a D flip flop, positive edge triggered, with an asynchronous reset "ar". | module top_module (
input clk,
input d,
input ar,
output logic q
);
| module top_module (
input clk,
input d,
input ar,
output logic q
);
always@(posedge clk or posedge ar) begin
if (ar)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input d,
input ar,
output logic q
);
always@(posedge clk or posedge ar) begin
if (ar)
q <= 0;
else
q <= d;
end
endmodule
module stimulus_gen (
input clk,
output logic d, ar
);
initial begin
repeat(100)... |
always_case | 73 | Create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the corresponding data input. Otherwise, output 0. The data inputs and outputs are all 4 bits wide. | module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
| module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
always @(*) begin
case (sel)
3'h0: out = data0;
3'h1: out = data1;
3'h2: out = data2;
3'h3: out = data3;
3'h4: out = d... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
always @(*) begin
case (sel)
3'h0: out = data0;
3'h1: out = data1... |
timer | 74 | Implement a timer that counts down for a given number of clock cycles, then asserts a signal to indicate that the given duration has elapsed. A good way to implement this is with a down-counter that asserts an output signal when the count becomes 0. At each clock cycle:
// (1) If load = 1, load the internal counter wi... | module top_module(
input clk,
input load,
input [9:0] data,
output tc
);
| module top_module(
input clk,
input load,
input [9:0] data,
output tc
);
logic [9:0] count_value;
always @(posedge clk)
if(load) count_value <= data;
else if(count_value != 0) count_value <= count_value - 1;
assign tc = count_value == 0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input [9:0] data,
output tc
);
logic [9:0] count_value;
always @(posedge clk)
if(load) count_value <= data;
else if(count_value != 0) count_value <= count_value - 1;
assign tc = count_value == 0;
end... |
review2015_fsmseq | 75 | Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Reset is active high synchronous. | module top_module(
input clk,
input reset,
input data,
output start_shifting);
| module top_module(
input clk,
input reset,
input data,
output start_shifting);
parameter S=0, S1=1, S11=2, S110=3, Done=4;
reg [2:0] state, next;
always_comb begin
case (state)
S: next = data ? S1: S;
S1: next = data ? S11: S;
S11: next = data ? S11 : S110;
S110: next = data ? Done : S;
Don... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
input data,
output start_shifting);
parameter S=0, S1=1, S11=2, S110=3, Done=4;
reg [2:0] state, next;
always_comb begin
case (state)
S: next = data ? S1: S;
S1: next = data ? S11: S;
S11: nex... |
dff8r | 76 | Create 8 D flip-flops with active high synchronous reset setting the output to zero. All DFFs should be triggered by the positive edge of clk. | module top_module(
input clk,
input [7:0] d,
input reset,
output reg [7:0] q);
| module top_module(
input clk,
input [7:0] d,
input reset,
output reg [7:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input [7:0] d,
input reset,
output reg [7:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= d;
endmodule
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wa... |
edgedetect2 | 77 | For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs. | module top_module(
input clk,
input [7:0] in,
output reg [7:0] anyedge);
| module top_module(
input clk,
input [7:0] in,
output reg [7:0] anyedge);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in;
anyedge <= in ^ d_last;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input [7:0] in,
output reg [7:0] anyedge);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in;
anyedge <= in ^ d_last;
end
endmodule
module stimulus_gen (
input clk,
input tb_match,
output reg [7:... |
count1to10 | 78 | Make a decade counter that counts 1 through 10, inclusive. The reset input is active high synchronous, and should reset the counter to 1. | module top_module(
input clk,
input reset,
output reg [3:0] q);
| module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 10)
q <= 1;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 10)
q <= 1;
else
q <= q+1;
endmodule
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output r... |
circuit9 | 79 | This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time clk a q
// 0ns 0 1 x
// 5ns 1 1 4
... | module top_module (
input clk,
input a,
output reg [2:0] q
);
| module top_module (
input clk,
input a,
output reg [2:0] q
);
always @(posedge clk)
if (a)
q <= 4;
else if (q == 6)
q <= 0;
else
q <= q + 1'b1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input a,
output reg [2:0] q
);
always @(posedge clk)
if (a)
q <= 4;
else if (q == 6)
q <= 0;
else
q <= q + 1'b1;
endmodule
module stimulus_gen (
input clk,
output logic a,
output reg[511:0] wavedro... |
lfsr5 | 80 | A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps po... | module top_module(
input clk,
input reset,
output reg [4:0] q);
| module top_module(
input clk,
input reset,
output reg [4:0] q);
logic [4:0] q_next;
always @(q) begin
q_next = q[4:1];
q_next[4] = q[0];
q_next[2] ^= q[0];
end
always @(posedge clk) begin
if (reset)
q <= 5'h1;
else
q <= q_next;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output reg [4:0] q);
logic [4:0] q_next;
always @(q) begin
q_next = q[4:1];
q_next[4] = q[0];
q_next[2] ^= q[0];
end
always @(posedge clk) begin
if (reset)
q <= 5'h1;
else
q <= q_next;
en... |
bugs_addsubz | 81 | The following adder-subtractor with zero flag doesn't work. Fix the bug(s).
// synthesis verilog_input_version verilog_2001
// module top_module (
// input do_sub,
// input [7:0] a,
// input [7:0] b,
// output reg [7:0] out,
// output reg result_is_zero
// );//
// always @(*) begin
// ... | module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
| module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = (out == 0);
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = (out == 0);
end
endmodule
mod... |
m2014_q3 | 82 | Consider the function f shown in the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient. Implement this function.
// x[1]x[2]
// x[3]x[4] 00 01 11 10
// 00 | d | 0 | d | d |
// 01 | 0 | d | 1 | 0 |
// 11 | 1 | 1 | d | d |
// 10 | 1 | 1 | 0 | d | | module top_module (
input [4:1] x,
output logic f
);
| module top_module (
input [4:1] x,
output logic f
);
always_comb begin
case (x)
4'h0: f = 1'bx;
4'h1: f = 1'bx;
4'h2: f = 0;
4'h3: f = 1'bx;
4'h4: f = 1;
4'h5: f = 1'bx;
4'h6: f = 1;
4'h7: f = 0;
4'h8: f = 0;
4'h9: f = 0;
4'ha: f = 1'bx;
4'hb: f = 1;
4'hc: f = 1;
4'hd: f... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [4:1] x,
output logic f
);
always_comb begin
case (x)
4'h0: f = 1'bx;
4'h1: f = 1'bx;
4'h2: f = 0;
4'h3: f = 1'bx;
4'h4: f = 1;
4'h5: f = 1'bx;
4'h6: f = 1;
4'h7: f = 0;
4'h8: f = 0;
4'h9: f = 0;... |
bugs_case | 83 | This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. If the 8-bit input is 8'h45, 8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d, 8'h3e, or 8'h46, the 4-bit output wi... | module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
| module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
// uhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch?
// and have one of the entries be wrong? (duplicate case, using different base!)
always @(*) begin
out = 0;
valid = 1;
case (code)
8'h45: o... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
// uhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch?
// and have one of the entries be wrong? (duplicate case, using different base!)
alway... |
vectorr | 84 | Given an 8-bit input vector [7:0], reverse its bit ordering. | module top_module (
input [7:0] in,
output [7:0] out
);
| module top_module (
input [7:0] in,
output [7:0] out
);
assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] in,
output [7:0] out
);
assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule
module stimulus_gen (
input clk,
output logic [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedro... |
kmap3 | 85 | Implement the circuit described by the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient.
// ab
// cd 01 00 10 11
// 00 | d | 0 | 1 | 1 |
// 01 | 0 | 0 | d | d |
// 11 | 0 | 1 | 1 | 1 |
// 10 | 0 | 1 | 1 | 1 | | module top_module (
input a,
input b,
input c,
input d,
output reg out
);
| module top_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 0;
4'h3: out = 1;
4'h2: out = 1;
4'h4: out = 1'bx;
4'h5: out = 0;
4'h7: out = 0;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 0;
4'h3: out = 1;
4'h2: out = 1;
4'h4: out ... |
review2015_shiftcount | 86 | Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circui... | module top_module(
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q);
| module top_module(
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q);
always @(posedge clk) begin
if (shift_ena)
q <= { q[2:0], data };
else if (count_ena)
q <= q - 1'b1;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q);
always @(posedge clk) begin
if (shift_ena)
q <= { q[2:0], data };
else if (count_ena)
q <= q - 1'b1;
end
endmodule
module stimulus_gen (
... |
wire | 87 | Create a module with one input and one output that behaves like a wire. | module top_module(
input in,
output out);
| module top_module(
input in,
output out);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input in,
output out);
assign out = in;
endmodule
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] ... |
review2015_fsmshift | 88 | This module is a part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should be active high synchronous. | module top_module(
input clk,
input reset,
output shift_ena);
| module top_module(
input clk,
input reset,
output shift_ena);
parameter B0=0, B1=1, B2=2, B3=3, Done=4;
reg [2:0] state, next;
always_comb begin
case (state)
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = Done;
Done: next = Done;
endcase
end
always @(posedge clk)
if (reset) ... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output shift_ena);
parameter B0=0, B1=1, B2=2, B3=3, Done=4;
reg [2:0] state, next;
always_comb begin
case (state)
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = Done;
Done: next... |
count15 | 89 | Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is active high synchronous, and should reset the counter to 0. | module top_module(
input clk,
input reset,
output reg [3:0] q);
| module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1;
endmodule
module stimulus_gen (
input clk,
output reg reset,
input tb_match,
output reg wavedrom_enable,
output r... |
always_if | 90 | Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement. | module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
| module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) out_always = (sel_b1 & sel_b2) ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) out_always = (sel_b1 & sel_b2) ? b : a;
endmodule
module stimulus_gen (
inp... |
kmap1 | 91 | Implement the circuit described by the Karnaugh map below.
// a
// bc 0 1
// 00 | 0 | 1 |
// 01 | 1 | 1 |
// 11 | 1 | 1 |
// 10 | 1 | 1 |
| module top_module(
input a,
input b,
input c,
output out
);
| module top_module(
input a,
input b,
input c,
output out
);
assign out = (a | b | c);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
input c,
output out
);
assign out = (a | b | c);
endmodule
module stimulus_gen (
input clk,
output reg a, b, c,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module ... |
2013_q2afsm | 92 | Consider the FSM described by the state diagram shown below:
// A --r1=0,r2=0,r3=0--> A
// A --r1=1--> B
// A --r1=0,r2=1--> C
// A --r1=0,r2=0,r3=0--> D
// B (g1=1) --r1=1--> B
// B (g1=1) --r1=0--> A
// C (g2=1) --r2=1--> C
// C (g2=1) --r2=0--> A
// Resetn is an active-low synchronous reset that resets into state ... | module top_module (
input clk,
input resetn,
input [3:1] r,
output [3:1] g
);
| module top_module (
input clk,
input resetn,
input [3:1] r,
output [3:1] g
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state, next;
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next;
end
always@(state,r) begin
case (state)
A: if (r[1]) next = B;
else if (r[2]) next = C;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input resetn,
input [3:1] r,
output [3:1] g
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state, next;
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next;
end
always@(state,r) begin
case (sta... |
count10 | 93 | Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0. | module top_module(
input clk,
input reset,
output reg [3:0] q);
| module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 9)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 9)
q <= 0;
else
q <= q+1;
endmodule
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output re... |
fsm_ps2 | 94 | The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has in[3]=1 (but in[3] of the other two bytes may be 1 or 0 depending on data). We want ... | module top_module (
input clk,
input [7:0] in,
input reset,
output done
);
| module top_module (
input clk,
input [7:0] in,
input reset,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DON... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input [7:0] in,
input reset,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 ... |
mux2to1 | 95 | Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. | module top_module (
input a,
input b,
input sel,
output out
);
| module top_module (
input a,
input b,
input sel,
output out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input sel,
output out
);
assign out = sel ? b : a;
endmodule
module stimulus_gen (
input clk,
output logic a,b,sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to mod... |
gates4 | 96 | Build a combinational circuit with four inputs, in[3:0]. There are 3 outputs:
// (1) out_and: output of a 4-input AND gate.
// (2) out_or: output of a 4-input OR gate.
// (3) out_xor: output of a 4-input XOR gate.
| module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
| module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
module stimulus_gen (
input clk,
output logic [3:0] in,
output reg[511:0] wavedrom_... |
2014_q3bfsm | 97 | Given the state-assigned table shown below, implement the finite-state machine. Reset should synchronous active high reset the FSM to state 000.
// Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1, Output z
// 000 | 000, 001 | 0
// 001 | 001, 100 | 0
// 010 | 010, 001 | 0
// 011 | 001, 010 | 1
// 10... | module top_module (
input clk,
input reset,
input x,
output reg z
);
| module top_module (
input clk,
input reset,
input x,
output reg z
);
parameter A=0, B=1, C=2, D=3, E=4;
reg [2:0] state, next;
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
always_comb begin
case (state)
A: next = x ? B : A;
B: next = x ? E : B;
C: next = x ? B : ... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input reset,
input x,
output reg z
);
parameter A=0, B=1, C=2, D=3, E=4;
reg [2:0] state, next;
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
always_comb begin
case (state)
A: n... |
2013_q2bfsm | 98 | Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input (synchronous, active low) called resetn. The FSM has to work as follows. As l... | module top_module (
input clk,
input resetn,
input x,
input y,
output f,
output g
);
| module top_module (
input clk,
input resetn,
input x,
input y,
output f,
output g
);
parameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;
reg [3:0] state, next;
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next;
end
always_comb begin
case (state)
A: next = B;
B:... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input resetn,
input x,
input y,
output f,
output g
);
parameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;
reg [3:0] state, next;
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next;
... |
dff8p | 99 | Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk. | module top_module(
input clk,
input [7:0] d,
input reset,
output reg [7:0] q);
| module top_module(
input clk,
input [7:0] d,
input reset,
output reg [7:0] q);
always @(negedge clk)
if (reset)
q <= 8'h34;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input [7:0] d,
input reset,
output reg [7:0] q);
always @(negedge clk)
if (reset)
q <= 8'h34;
else
q <= d;
endmodule
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0... |
reduction | 100 | Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits. | module top_module (
input [7:0] in,
output parity
);
| module top_module (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
m... |
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