task_id stringlengths 3 21 | task_number int64 1 156 | description stringlengths 28 4.81k | header stringlengths 33 297 | module_code stringlengths 67 1.58k | testbench stringlengths 2.29k 10.3k |
|---|---|---|---|---|---|
mux2to1v | 1 | Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b. | module top_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
| module top_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
module stimulus_gen (
input clk,
output logic [99:0] a,b,
output logic sel,
output reg[511:0] wavedrom_title,
output reg wa... |
m2014_q6b | 2 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Assume that you want to Implement the FSM using three flip-... | module top_module(
input [3:1] y,
input w,
output reg Y2);
| module top_module(
input [3:1] y,
input w,
output reg Y2);
always_comb begin
case ({y, w})
4'h0: Y2 = 1'b0;
4'h1: Y2 = 1'b0;
4'h2: Y2 = 1'b1;
4'h3: Y2 = 1'b1;
4'h4: Y2 = 1'b0;
4'h5: Y2 = 1'b1;
4'h6: Y2 = 1'b0;
4'h7: Y2 = 1'b0;
4'h8: Y2 = 1'b0;
4'h9: Y2 = 1'b1;
4'ha: Y2 = 1'b1;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input [3:1] y,
input w,
output reg Y2);
always_comb begin
case ({y, w})
4'h0: Y2 = 1'b0;
4'h1: Y2 = 1'b0;
4'h2: Y2 = 1'b1;
4'h3: Y2 = 1'b1;
4'h4: Y2 = 1'b0;
4'h5: Y2 = 1'b1;
4'h6: Y2 = 1'b0;
4'h7: Y2 = 1'b0;... |
ringer | 3 | Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode... | module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
| module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
module stimulus_gen (
input clk,
output reg ring, vibrate_mode,
output reg[5... |
alwaysblock1 | 4 | Build an AND gate using both an assign statement and a combinational always block. | module top_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
| module top_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title... |
zero | 5 | Build a circuit that always outputs a LOW. | module top_module(
output zero);
| module top_module(
output zero);
assign zero = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
output zero);
assign zero = 1'b0;
endmodule
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// ou... |
circuit7 | 6 | This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time clk a q
// 0ns 0 x x
// 5ns 1 0 x
... | module top_module (
input clk,
input a,
output reg q
);
| module top_module (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
module stimulus_gen (
input clk,
output logic a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module s... |
ece241_2014_q5a | 7 | You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circ... | module top_module (
input clk,
input areset,
input x,
output z
);
| module top_module (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <= x ? B : C;
C: state <= x ? B : C;
endcase
end
end
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <=... |
fsm3 | 8 | The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a positive edge triggered asynchronous reset that resets the FSM to state A.
// state | next state in=0, next state in=1 | output
// A | A, B | 0
// B | C, B | 0
// ... | module top_module (
input clk,
input in,
input areset,
output out
);
| module top_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(pos... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
... |
vector2 | 9 | Build a circuit that reverses the byte order of a 32-bit vector. | module top_module (
input [31:0] in,
output [31:0] out
);
| module top_module (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
module stimulus_gen (
input clk,
output logic [31:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
)... |
m2014_q4c | 10 | Implement a simple D flip flop with active high synchronous reset (reset output to 0). | module top_module (
input clk,
input d,
input r,
output logic q
);
| module top_module (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
module stimulus_gen (
input clk,
output logic d, r
);
initial begin
repeat(100) @(posedge clk, n... |
mt2015_q4a | 11 | Implement the boolean function z = (x^y) & x. | module top_module(
input x,
input y,
output z);
| module top_module(
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(101) @(nege... |
shift18 | 12 | Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by "amount." Assume the right shit is an arithmetic right shift.
// Signals are defined as below:
// (1) load: Loads shift register with data[63:0] instead of shifting. Act... | module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
| module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <=... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q... |
ece241_2013_q8 | 13 | Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have a negative edge triggered asynchronous reset. You may only have 3 states in your... | module top_module (
input clk,
input aresetn,
input x,
output reg z
);
| module top_module (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S1... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (sta... |
m2014_q6 | 14 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Implement this state machine in Verilog. | module top_module (
input clk,
input reset,
input w,
output z
);
| module top_module (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A: next = w ? A : B;
B: next = w ? D : C;
C: next = w ? D... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A... |
fsm_ps2data | 15 | We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM shou... | module top_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
| module top_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
... |
2012_q2b | 16 |
// Consider the state machine shown below:
// A (0) --1--> B
// A (0) --0--> A
// B (0) --1--> C
// B (0) --0--> D
// C (0) --1--> E
// C (0) --0--> D
// D (0) --1--> F
// D (0) --0--> A
// E (1) --1--> E
// E (1) --0--> D
// F (1) --1--> C
// F (1) --0--> D
// Assume that a one-hot code is used with the state assig... | module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
| module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
module stimulus_gen (
input clk,
output logic[5:0] y,
output logic w,
input tb_match
);
int errored1 = 0;... |
vector0 | 17 | Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc. | module top_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
| module top_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
module stimulus_gen (
input clk,
output reg [2:0] vec,
output reg[511:0] wavedrom_title,
outpu... |
kmap4 | 18 | Implement the circuit described by the Karnaugh map below.
// ab
// cd 00 01 11 10
// 00 | 0 | 1 | 0 | 1 |
// 01 | 1 | 0 | 1 | 0 |
// 11 | 0 | 1 | 0 | 1 |
// 10 | 1 | 0 | 1 | 0 | | module top_module (
input a,
input b,
input c,
input d,
output reg out
);
| module top_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out = 1;
4'h5: out = 0;
4'h7: out = 1;
... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out ... |
vector1 | 19 | Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes. | module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
| module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
module stimulus_gen (
input clk,
output logic [15:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
... |
norgate | 20 | Create a module that implements a NOR gate. | module top_module(
input a,
input b,
output out
);
| module top_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
//... |
alwaysblock2 | 21 | Build an XOR gate three ways, using an assign statement (output out_assign), a combinational always block (output out_always_comb), and a clocked always block (output out_always_ff). Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed. | module top_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
| module top_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
... |
m2014_q6c | 22 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Resets into state A. For this part, assume that a one-hot c... | module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
| module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
module stimulus_gen (
input clk,
output logic[6:1] y,
output logic w,
input tb_match
);
int errored1 = 0;... |
mux256to1 | 23 | Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc. | module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
| module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
module stimulus_gen (
input clk,
output logic [255:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<... |
2014_q4a | 24 | Consider an n-bit shift register circuit. Inputs E are for enabling shift, R for value to load, L is asserted when it should load, and w is the input to the first stage of the shift register. Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers. | module top_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
| module top_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
module stimulus_gen (
input clk,
output logic w, R, E, L
);
initial begin
repeat... |
ece241_2014_q4 | 25 | Given the finite state machine circuit described below, assume that the D flip-flops are initially reset to zero before the machine begins.
// Build this circuit in Verilog.
// Input x goes to three different two-input gates: a XOR, an AND, and a OR gate. Each of the three gates is connected to the input of a D flip-... | module top_module (
input clk,
input x,
output z
);
| module top_module (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
module stimulus_gen (
input clk,
output logic x,
output reg[511:0]... |
circuit4 | 26 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d q
// 0ns 0 0 0 0 0
/... | module top_module (
input a,
input b,
input c,
input d,
output q
);
| module top_module (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to mo... |
rule110 | 27 | Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete). There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the... | module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
| module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |
(q[$bits... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] ... |
fsm3s | 28 | The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous active high reset that resets the FSM to state A.
// State | Next state in=0, Next state in=1 | Output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
/... | module top_module (
input clk,
input in,
input reset,
output out
);
| module top_module (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(pose... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
... |
circuit5 | 29 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d e q
// 0ns x x x x x ... | module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
| module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
module s... |
bugs_mux2 | 30 | Find the bug and fix this 8-bit wide 2-to-1 mux.
// module top_module (
// input sel,
// input [7:0] a,
// input [7:0] b,
// output out );
// assign out = (~sel & a) | (sel & b);
// endmodule | module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
| module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
module stimulus_gen (
input clk,
output logic sel,
output logic [7:0] a, b,
out... |
mt2015_muxdff | 31 | Consider this Verilog module "full_module":
// module full_module (
// input [2:0] r,
// input L,
// input clk,
// output reg [2:0] q
);
// always @(posedge clk) begin
// if (L) begin
// q <= r;
// end else begin
// q <= {q[1] ^ q[2], q[0], q[2]};
// end
// end
// endmodul... | module top_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
| module top_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.
*/
module reference_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
module stimulus_gen... |
edgecapture | 32 | For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (active high synchronous reset). | module top_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
| module top_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
module stimul... |
dff8 | 33 | Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk. | module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
| module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input [7:0] d,
output reg [7:0] q);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
module stimulus_gen (
input clk,
output reg [7:0] d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enabl... |
ece241_2014_q1c | 34 | Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred. | module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
| module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
module stimulus_gen (
input clk,
output logic [7:0] a, ... |
review2015_fsmonehot | 35 | Given the following Moore state machine with 3 input (d, done_counting, ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in the diagram below, assume outputs are 0 and inputs are don't cares.
// S () --d=0--> S
// S () --d=1--> S1
// S1 () --d=0--> S
// S1 () --d=1--> S11
// S11 () --d=0--> S110... | module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
| module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
parameter S=0, S1=1,... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
out... |
counter_2bc | 36 | Build a two-bit saturating counter. The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged. areset is a positive edge triggered asy... | module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
| module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
if(state < 3 && train_taken)
state... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
... |
always_casez | 37 | Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high. | module top_module (
input [7:0] in,
output reg [2:0] pos
);
| module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4;
8'bzz1zzzzz: pos = 3'h5;
8'bz1zzzzzz: pos = 3'h6;
8... | `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4... |
always_nolatches | 38 | Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif)... | module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
| module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
... |
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