plateform stringclasses 1
value | repo_name stringclasses 2
values | name stringlengths 1 78 | ext stringclasses 2
values | path stringlengths 15 1.11k | size int64 1 8.55M | source_encoding stringclasses 11
values | md5 stringlengths 32 32 | text stringlengths 0 8.49M |
|---|---|---|---|---|---|---|---|---|
google | android | via_dma | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/via/via_dma.c | 20,693 | utf_8 | 145ff82b9dd168dc029babb24e4cfb00 | /* via_dma.c -- DMA support for the VIA Unichrome/Pro
*
*
* Authors:
* Tungsten Graphics,
* Erdi Chen,
* Thomas Hellstrom.
*/
#include <drm/drmP.h>
#include <drm/via_drm.h>
#include "via_drv.h"
#include "via_3d_reg.h"
#define CMDBUF_ALIGNMENT_SIZE (0x100)
#define CMDBUF_ALIGNMENT_MASK (0x0ff)
/* def... |
google | android | intel_fifo_underrun | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_fifo_underrun.c | 12,055 | utf_8 | 3eb293b732f9351ab00aaf769c43bd41 | /*
*
*/
#include "i915_drv.h"
#include "intel_drv.h"
/**
* DOC: fifo underrun handling
*
* The i915 driver checks for display fifo underruns using the interrupt signals
* provided by the hardware. This is enabled by default and fairly useful to
* debug display issues, especially watermark settings.
*
* If an u... |
google | android | intel_dp | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_dp.c | 178,275 | utf_8 | 9d8d4326c364106342d41bc9b0bbdb52 | /*
*
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915... |
google | android | dvo_ns2501 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/dvo_ns2501.c | 22,578 | utf_8 | 811925b22621f348abe933b6a678b5e9 | /*
*
*
*/
#include "dvo.h"
#include "i915_reg.h"
#include "i915_drv.h"
#define NS2501_VID 0x1305
#define NS2501_DID 0x6726
#define NS2501_VID_LO 0x00
#define NS2501_VID_HI 0x01
#define NS2501_DID_LO 0x02
#define NS2501_DID_HI 0x03
#define NS2501_REV 0x04
#define NS2501_RSVD 0x05
#define NS2501_FREQ_LO 0x06
#define N... |
google | android | intel_sprite | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_sprite.c | 32,927 | utf_8 | e59020c69ec33357d3fe36685379749b | /*
*
* New plane/sprite handling.
*
* The older chips had a separate interface for programming plane related
* registers; newer ones are much simpler and we can use the new DRM plane
* support.
*/
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_rect.h>
#include <drm/... |
google | android | intel_atomic | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_atomic.c | 9,397 | utf_8 | 30f4f4edf8e21af86483fc0fe79736e5 | /*
*/
/**
* DOC: atomic modeset support
*
* The functions here implement the state management and hardware programming
* dispatch required by the atomic modeset infrastructure.
* See intel_atomic_plane.c for the plane-specific atomic functionality.
*/
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <d... |
google | android | intel_dvo | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_dvo.c | 16,201 | utf_8 | dc1b06fba31389797995f871de1e818f | /*
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "dvo.h"
#define SIL164_ADDR 0x38
#define CH7xxx_ADDR 0x76
#define TFP410_ADDR 0x38
#define NS2501_ADDR ... |
google | android | intel_acpi | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_acpi.c | 3,662 | utf_8 | 5378fa72d14bfd15bea9f42b78d82067 | /*
* Intel ACPI functions
*
* _DSM related code stolen from nouveau_acpi.c.
*/
#include <linux/pci.h>
#include <linux/acpi.h>
#include <drm/drmP.h>
#include "i915_drv.h"
#define INTEL_DSM_REVISION_ID 1 /* For Calpella anyway... */
#define INTEL_DSM_FN_PLATFORM_MUX_INFO 1 /* No args */
static struct intel_dsm_priv... |
google | android | i915_irq | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_irq.c | 129,950 | utf_8 | 463a5933dfaa3ab2b977cbe310ca7070 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
*/
/*
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/sysrq.h>
#include <linux/slab.h>
#include <linux/circ_buf.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
/**
* DOC... |
google | android | intel_atomic_plane | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_atomic_plane.c | 7,611 | utf_8 | 61a18e058606c03c99e0c64eb8b4d47f | /*
*/
/**
* DOC: atomic plane helpers
*
* The functions here are used by the atomic plane helper functions to
* implement legacy plane updates (i.e., drm_plane->update_plane() and
* drm_plane->disable_plane()). This allows plane updates to use the
* atomic state infrastructure and perform plane updates as separ... |
google | android | intel_csr | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_csr.c | 13,520 | utf_8 | ee23378ad99c6bd9769806b25f32398e | /*
*
*/
#include <linux/firmware.h>
#include "i915_drv.h"
#include "i915_reg.h"
/**
* DOC: csr support for dmc
*
* Display Context Save and Restore (CSR) firmware support added from gen9
* onwards to drive newly added DMC (Display microcontroller) in display
* engine to save and restore the state of display engi... |
google | android | intel_dp_mst | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_dp_mst.c | 17,968 | utf_8 | 4d6c57d270e875cbf6fde7f0970ef107 | /*
*
*/
#include <drm/drmP.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder... |
google | android | i915_gem | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem.c | 137,968 | utf_8 | c9bc425301133c02839101053e1dd7e3 | /*
*
*/
#include <drm/drmP.h>
#include <drm/drm_vma_manager.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_vgpu.h"
#include "i915_trace.h"
#include "intel_drv.h"
#include <linux/shmem_fs.h>
#include <linux/slab.h>
#include <linux/swap.h>
#include <linux/pci.h>
#include <linux/dma-buf.h>
#define RQ_... |
google | android | i915_gem_fence | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_fence.c | 25,373 | utf_8 | 0d1c5a7cb77926494e64da0cc03a9509 | /*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
/**
* DOC: fence register handling
*
* Important to avoid confusions: "fences" in the i915 driver are not execution
* fences used to track command completion but hardware detiler objects which
* wrap a given range of the global GTT. Each ... |
google | android | dvo_ch7017 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/dvo_ch7017.c | 12,696 | utf_8 | 294b567205e5a31c418bb39f6de39c65 | /*
*
*/
#include "dvo.h"
#define CH7017_TV_DISPLAY_MODE 0x00
#define CH7017_FLICKER_FILTER 0x01
#define CH7017_VIDEO_BANDWIDTH 0x02
#define CH7017_TEXT_ENHANCEMENT 0x03
#define CH7017_START_ACTIVE_VIDEO 0x04
#define CH7017_HORIZONTAL_POSITION 0x05
#define CH7017_VERTICAL_POSITION 0x06
#define CH7017_BLACK_LEVEL ... |
google | android | intel_panel | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_panel.c | 55,311 | utf_8 | c32226ecc1c05fb6f7f70723cf7fdb19 | /*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/pwm.h>
#include "intel_drv.h"
#define CRC_PMIC_PWM_PERIOD_NS 21333
void
intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
{
drm_mo... |
google | android | i915_gem_execbuffer | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_execbuffer.c | 48,277 | utf_8 | fe2dc7b7cbde7f4a0726b1677d88f05d | /*
*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
#include <linux/dma_remapping.h>
#include <linux/uaccess.h>
#define __EXEC_OBJECT_HAS_PIN (1<<31)
#define __EXEC_OBJECT_HAS_FENCE (1<<30)
#define __EXEC_OBJECT_NEEDS_MAP (1<<29)
#define __E... |
google | android | i915_gem_tiling | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_tiling.c | 10,270 | utf_8 | 5b3a32b0c87086fec96f977997f5f896 | /*
*
*/
#include <linux/string.h>
#include <linux/bitops.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
/**
* DOC: buffer object tiling
*
* i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
* declare fence register requirements.
*
* In principle GEM doesn't ... |
google | android | i915_gem_dmabuf | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_dmabuf.c | 8,130 | utf_8 | a4d4cbad150d9fea7824b1ef3a43d541 | /*
*/
#include <drm/drmP.h>
#include "i915_drv.h"
#include <linux/dma-buf.h>
static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf)
{
return to_intel_bo(buf->priv);
}
static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attachment,
enum dma_data_direction dir)
{
struct dr... |
google | android | i915_ioc32 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_ioc32.c | 3,102 | utf_8 | 14e719305ae8bc6a250bda97110f26ae | /**
* \file i915_ioc32.c
*
* 32-bit ioctl compatibility routines for the i915 DRM.
*
*/
#include <linux/compat.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
struct drm_i915_getparam32 {
s32 param;
/*
* We screwed up the generic ioctl struct here and used a variable-sized
* pointer.... |
google | android | i915_gem_evict | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_evict.c | 7,427 | utf_8 | 78688c8032e0907cca24dede76cd3ef2 | /*
*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "i915_trace.h"
static bool
mark_free(struct i915_vma *vma, struct list_head *unwind)
{
if (vma->pin_count)
return false;
if (WARN_ON(!list_empty(&vma->exec_list)))
return false;
list_add(&vma->exec_lis... |
google | android | dvo_ch7xxx | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/dvo_ch7xxx.c | 8,376 | utf_8 | e88edeba2b59a6896e0da2886f9e55fe | /**************************************************************************
**************************************************************************/
#include "dvo.h"
#define CH7xxx_REG_VID 0x4a
#define CH7xxx_REG_DID 0x4b
#define CH7011_VID 0x83 /* 7010 as well */
#define CH7010B_VID 0x05
#define CH7009A_VID 0x... |
google | android | i915_debugfs | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_debugfs.c | 147,103 | utf_8 | 1a0f59fc98cc5013d02dbd16c3338564 | /*
*
*/
#include <linux/seq_file.h>
#include <linux/circ_buf.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/list_sort.h>
#include <asm/msr-index.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include "intel_ringbuffer.h"
#include <drm/i915_dr... |
google | android | intel_ddi | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_ddi.c | 93,235 | utf_8 | 24d3fe31661d8ca67fd0341c63425d61 | /*
*
*/
#include "i915_drv.h"
#include "intel_drv.h"
struct ddi_buf_trans {
u32 trans1; /* balance leg enable, de-emph level */
u32 trans2; /* vref sel, vswing */
u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
};
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
* them for both DP a... |
google | android | intel_audio | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_audio.c | 24,788 | utf_8 | def67d8f5032602ae760463e3af8240a | /*
*/
#include <linux/kernel.h>
#include <linux/component.h>
#include <drm/i915_component.h>
#include "intel_drv.h"
#include <drm/drmP.h>
#include <drm/drm_edid.h>
#include "i915_drv.h"
/**
* DOC: High Definition Audio over HDMI and Display Port
*
* The graphics and audio drivers together support High Definition Au... |
google | android | intel_dsi_panel_vbt | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 20,298 | utf_8 | dd428ff27765b27a653cd2ee08f19fb1 | /*
*
*/
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/i915_drm.h>
#include <drm/drm_panel.h>
#include <linux/slab.h>
#include <video/mipi_display.h>
#include <asm/intel-mid.h>
#include <video/mipi_display.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
... |
google | android | intel_overlay | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_overlay.c | 41,134 | utf_8 | 06e9eb02ce1c272b5cb4e1c735ab6246 | /*
*
* Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_drv.h"
/* Limits for overlay size. According to intel doc, the real limits are:
* Y width: 4095, UV width (planar): 2047, Y height: 2047,
*... |
google | android | i915_sysfs | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_sysfs.c | 18,402 | utf_8 | 91937b2a119d2e21880caba3d200023d | /*
*
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/stat.h>
#include <linux/sysfs.h>
#include "intel_drv.h"
#include "i915_drv.h"
#define dev_to_drm_minor(d) dev_get_drvdata((d))
#ifdef CONFIG_PM
static u32 calc_residency(struct drm_device *dev, const u32 reg)
{
struct drm_i915_private *dev_p... |
google | android | i915_gem_stolen | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_stolen.c | 19,759 | utf_8 | 8c967480d8cf79043d6aa764d78db829 | /*
*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#define KB(x) ((x) * 1024)
#define MB(x) (KB(x) * 1024)
/*
* The BIOS typically reserves some of the system's memory for the exclusive
* use of the integrated graphics. This memory is no longer available for
* use by the OS and so the us... |
google | android | i915_gpu_error | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gpu_error.c | 38,959 | utf_8 | 56966ba310b6b6d204e1edf73260fe84 | /*
*
*/
#include <generated/utsrelease.h>
#include "i915_drv.h"
static const char *ring_str(int ring)
{
switch (ring) {
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
case VECS: return "vebox";
case VCS2: return "bsd2";
default: return "";
}
}
static const char *pin_flag(int pinned... |
google | android | i915_guc_submission | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_guc_submission.c | 27,769 | utf_8 | 871b1e02781fc58a1d6f58d493ee7ccb | /*
*
*/
#include <linux/firmware.h>
#include <linux/circ_buf.h>
#include "i915_drv.h"
#include "intel_guc.h"
/**
* DOC: GuC Client
*
* i915_guc_client:
* We use the term client to avoid confusion with contexts. A i915_guc_client is
* equivalent to GuC object guc_context_desc. This context descriptor is
* alloca... |
google | android | i915_gem_debug | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_debug.c | 2,192 | utf_8 | a5a302307d1533ee6380eb4a7679576e | /*
*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#if WATCH_LISTS
int
i915_verify_lists(struct drm_device *dev)
{
static int warned;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_object *obj;
struct intel_engine_cs *ring;
int err = 0;
int i;
if (warned)
ret... |
google | android | i915_trace_points | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_trace_points.c | 210 | utf_8 | 9164f88ce40501b2b7403e9053964005 | /*
*/
#include "i915_drv.h"
#ifndef __CHECKER__
#define CREATE_TRACE_POINTS
#include "i915_trace.h"
#endif |
google | android | intel_dsi | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_dsi.c | 36,468 | utf_8 | cea02476dbdd1c7124cf61192565337f | /*
*/
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/i915_drm.h>
#include <drm/drm_panel.h>
#include <drm/drm_mipi_dsi.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi... |
google | android | intel_guc_loader | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_guc_loader.c | 18,896 | utf_8 | 89a9e5a6c3071c57c23950cd23d394ed | /*
*/
#include <linux/firmware.h>
#include "i915_drv.h"
#include "intel_guc.h"
/**
* DOC: GuC
*
* intel_guc:
* Top level structure of guc. It handles firmware loading and manages client
* pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
* ExecList submission.
*
* Firmware versioning:
... |
google | android | intel_fbdev | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_fbdev.c | 23,163 | utf_8 | e4a2f6ebc8bd474dded59a1f5b82d01a | /*
*
* Authors:
* David Airlie
*/
#include <linux/async.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/sysrq.h>
#include <linux/delay.h>
#include <linux/fb.h>
#inclu... |
google | android | i915_dma | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_dma.c | 40,037 | utf_8 | 9a9206fc9a0868ec13caf674871a435c | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
*/
/*
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/async.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_legacy.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_d... |
google | android | dvo_tfp410 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/dvo_tfp410.c | 8,195 | utf_8 | 4091ace9fb3f255999f8c42a65c374db | /*
*
*/
#include "dvo.h"
/* register definitions according to the TFP410 data sheet */
#define TFP410_VID 0x014C
#define TFP410_DID 0x0410
#define TFP410_VID_LO 0x00
#define TFP410_VID_HI 0x01
#define TFP410_DID_LO 0x02
#define TFP410_DID_HI 0x03
#define TFP410_REV 0x04
#define TFP410_CTL_1 0x08
#define TFP41... |
google | android | intel_hdmi | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_hdmi.c | 67,050 | utf_8 | ee0937955e4e743c2d2938fc3e764be3 | /*
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
static struct drm_device *intel_hdmi_... |
google | android | i915_params | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_params.c | 8,190 | utf_8 | fc5e3d780e94f92f100caa1db84a5954 | /*
*/
#include "i915_drv.h"
struct i915_params i915 __read_mostly = {
.modeset = -1,
.panel_ignore_lid = 1,
.semaphores = -1,
.lvds_channel_mode = 0,
.panel_use_ssc = -1,
.vbt_sdvo_panel_type = -1,
.enable_rc6 = -1,
.enable_fbc = -1,
.enable_execlists = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.en... |
google | android | intel_crt | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_crt.c | 24,113 | utf_8 | bee5aa80193227ad2bf1d8d4c80cee74 | /*
*/
#include <linux/dmi.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
/* Here's the desired hotplug ... |
google | android | intel_display | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_display.c | 446,865 | utf_8 | 4e949124ee9b671bddb41b7eb5e181dc | /*
*/
#include <linux/dmi.h>
#include <linux/module.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
#include <drm/drm_edid.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.... |
google | android | intel_frontbuffer | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_frontbuffer.c | 9,009 | utf_8 | bd790836f808fa77819f8f9634c0080c | /*
*/
/**
* DOC: frontbuffer tracking
*
* Many features require us to track changes to the currently active
* frontbuffer, especially rendering targeted at the frontbuffer.
*
* To be able to do so GEM tracks frontbuffers using a bitmask for all possible
* frontbuffer slots through i915_gem_track_fb(). The funct... |
google | android | intel_bios | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_bios.c | 39,104 | utf_8 | 47ab7b95cef693a2a3a924421f215498 | /*
*
*/
#include <linux/dmi.h>
#include <drm/drm_dp_helper.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "intel_bios.h"
#define SLAVE_ADDR1 0x70
#define SLAVE_ADDR2 0x72
static int panel_type;
static const void *
find_section(const void *_bdb, int section_id)
{
const struct bdb_he... |
google | android | i915_drv | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_drv.c | 50,417 | utf_8 | f360c417430a06e404a4c6cba6c18306 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
*/
/*
*
*
*/
#include <linux/device.h>
#include <linux/acpi.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
#include <linux/console.h>
#include <linux/module.h>
#include <linux/pm... |
google | android | intel_uncore | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_uncore.c | 43,432 | utf_8 | 421d337cdb7db6f7832c02c9523b7d39 | /*
*/
#include "i915_drv.h"
#include "intel_drv.h"
#include "i915_vgpu.h"
#include <linux/pm_runtime.h>
#define FORCEWAKE_ACK_TIMEOUT_MS 50
#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
#de... |
google | android | i915_gem_shrinker | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_shrinker.c | 10,575 | utf_8 | d83a82448755eba5afeafd8f47964869 | /*
*
*/
#include <linux/oom.h>
#include <linux/shmem_fs.h>
#include <linux/slab.h>
#include <linux/swap.h>
#include <linux/pci.h>
#include <linux/dma-buf.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
static bool mutex_is_locked_by(struct mutex *mutex, struct task_str... |
google | android | intel_runtime_pm | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_runtime_pm.c | 65,965 | utf_8 | 3f549c11b681b2bd23ef06cf2d5a928c | /*
*
*/
#include <linux/pm_runtime.h>
#include <linux/vgaarb.h>
#include "i915_drv.h"
#include "intel_drv.h"
/**
* DOC: runtime pm
*
* The i915 driver supports dynamic enabling and disabling of entire hardware
* blocks at runtime. This is especially important on the display side where
* since on the GT side a lo... |
google | android | intel_renderstate_gen6 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_renderstate_gen6.c | 5,122 | utf_8 | 3a260c614484f7a4d7811e02b608483a | /*
*
* Generated by: intel-gpu-tools-1.8-220-g01153e7
*/
#include "intel_renderstate.h"
static const u32 gen6_null_state_relocs[] = {
0x00000020,
0x00000024,
0x0000002c,
0x000001e0,
0x000001e4,
-1,
};
static const u32 gen6_null_state_batch[] = {
0x69040000,
0x790d0001,
0x00000000,
0x00000000,
0x78180000,
... |
google | android | i915_gem_userptr | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_userptr.c | 24,207 | utf_8 | 2ee0eaab9c3c998139c75d215003d8e1 | /*
*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
#include <linux/mmu_context.h>
#include <linux/mmu_notifier.h>
#include <linux/mempolicy.h>
#include <linux/swap.h>
struct i915_mm_struct {
struct mm_struct *mm;
struct drm_device *dev;
stru... |
google | android | intel_fbc | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_fbc.c | 31,702 | utf_8 | 5153f4ab0c8a1f9bdbef99ebea56c2eb | /*
*/
/**
* DOC: Frame Buffer Compression (FBC)
*
* FBC tries to save memory bandwidth (and so power consumption) by
* compressing the amount of memory used by the display. It is total
* transparent to user space and completely handled in the kernel.
*
* The benefits of FBC are mostly visible with solid backgro... |
google | android | dvo_ivch | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/dvo_ivch.c | 12,195 | utf_8 | 217194e3c19a297629893bbc06d1da55 | /*
*
*/
#include "dvo.h"
/*
* register definitions for the i82807aa.
*
* Documentation on this chipset can be found in datasheet #29069001 at
* intel.com.
*/
/*
* VCH Revision & GMBus Base Addr
*/
#define VR00 0x00
# define VR00_BASE_ADDRESS_MASK 0x007f
/*
* Functionality Enable
*/
#define VR01 0x01
/*
*... |
google | android | intel_renderstate_gen9 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_renderstate_gen9.c | 14,001 | utf_8 | 4c7880b1c2f8797d8740f57a21639ab9 | /*
*
* Generated by: intel-gpu-tools-1.8-220-g01153e7
*/
#include "intel_renderstate.h"
static const u32 gen9_null_state_relocs[] = {
0x000007a8,
0x000007b4,
0x000007bc,
0x000007cc,
-1,
};
static const u32 gen9_null_state_batch[] = {
0x7a000004,
0x01000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
... |
google | android | intel_opregion | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_opregion.c | 28,315 | utf_8 | c62691f92d4be36167ddafb9e334197b | /*
*
*/
#include <linux/acpi.h>
#include <acpi/video.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "intel_drv.h"
#define PCI_ASLE 0xe4
#define PCI_ASLS 0xfc
#define PCI_SWSCI 0xe8
#define PCI_SWSCI_SCISEL (1 << 15)
#define PCI_SWSCI_GSSCIE (1 << 0)
#define OPREGION_HEADER_OFFSET... |
google | android | intel_modes | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_modes.c | 4,050 | utf_8 | 2c545cdc048cf1e081c4822ce0a29ec9 | /*
*/
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <drm/drm_edid.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include "i915_drv.h"
/**
* intel_connector_update_modes - update connector from edid
*/
int intel_connector_update_modes(struct drm_connector *connector,
struct edid ... |
google | android | i915_gem_batch_pool | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_batch_pool.c | 4,533 | utf_8 | 3541df440e2b6534702d2e8d4a68fb20 | /*
*
*/
#include "i915_drv.h"
#include "i915_gem_batch_pool.h"
/**
* DOC: batch pool
*
*/
void i915_gem_batch_pool_init(struct drm_device *dev,
struct i915_gem_batch_pool *pool)
{
int n;
pool->dev = dev;
for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)
INIT_LIST_HEAD(&pool->cache_list[n]);
}
/**
*... |
google | android | i915_vgpu | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_vgpu.c | 9,325 | utf_8 | a026bccc9795b582fe0c9a92ee26887c | /*
*/
#include "intel_drv.h"
#include "i915_vgpu.h"
/**
* DOC: Intel GVT-g guest support
*
* Intel GVT-g is a graphics virtualization technology which shares the
* GPU among multiple virtual machines on a time-sharing basis. Each
* virtual machine is presented a virtual GPU (vGPU), which has equivalent
* feature... |
google | android | intel_pm | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_pm.c | 211,381 | utf_8 | e2c6ea6b5e4ba3156f92f4e266b5e1de | /*
*
*/
#include <linux/cpufreq.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "../../../platform/x86/intel_ips.h"
#include <linux/module.h>
/**
* RC6 is a special power stage which allows the GPU to enter an very
* low-voltage mode when idle, using down to 0V while at this stage. This
* stage is entere... |
google | android | intel_i2c | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_i2c.c | 18,391 | utf_8 | 2ac550bc5f1be4c335fb1fa2483a1c34 | /*
*/
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/export.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
struct gmbus_pin {
const char *name;
int reg;
};
/* Map gmbus pin pairs to names and registers. */
static const struct gmbus_pin gmbus_pi... |
google | android | intel_sideband | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_sideband.c | 7,828 | utf_8 | 64a8f35a7df16f43f32ed6f94c4d7b6b | /*
*
*/
#include "i915_drv.h"
#include "intel_drv.h"
/*
* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
* VLV_VLV2_PUNIT_HAS_0.8.docx
*/
/* Standard MMIO read, non-posted */
#define SB_MRD_NP 0x00
/* Standard MMIO write, non-posted */
#define SB_MWR_NP 0x01
/* Private register read, double-word addressing, non-... |
google | android | dvo_sil164 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/dvo_sil164.c | 6,747 | utf_8 | 31e1c36de45c00fbe5f2c1639b14de98 | /**************************************************************************
**************************************************************************/
#include "dvo.h"
#define SIL164_VID 0x0001
#define SIL164_DID 0x0006
#define SIL164_VID_LO 0x00
#define SIL164_VID_HI 0x01
#define SIL164_DID_LO 0x02
#define SIL164_DID... |
google | android | intel_lrc | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_lrc.c | 77,824 | utf_8 | e9a905e6146b9ffae032cd7ac563c527 | /*
*
*/
/**
* DOC: Logical Rings, Logical Ring Contexts and Execlists
*
* Motivation:
* GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
* These expanded contexts enable a number of new abilities, especially
* "Execlists" (also implemented in this file).
*
* One of the main differences wi... |
google | android | intel_hotplug | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_hotplug.c | 16,816 | utf_8 | a15a201db86ab7dcb208339fde85d700 | /*
*/
#include <linux/kernel.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "intel_drv.h"
/**
* DOC: Hotplug
*
* Simply put, hotplug occurs when a display is connected to or disconnected
* from the system. However, there may be adapters and docking stations and
* Display Port sh... |
google | android | intel_lvds | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_lvds.c | 34,231 | utf_8 | cbca0b30febef7c515fd22c71b817b77 | /*
*/
#include <acpi/button.h>
#include <linux/dmi.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include <linux/acpi.h>
/* Private str... |
google | android | i915_gem_gtt | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_gtt.c | 93,584 | utf_8 | 5dedee1a8c311dad4f986e976200049a | /*
*
*/
#include <linux/seq_file.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_vgpu.h"
#include "i915_trace.h"
#include "intel_drv.h"
/**
* DOC: Global GTT views
*
* Background and previous state
*
* Historically objects could exists (be bound) in global GTT space only a... |
google | android | i915_suspend | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_suspend.c | 6,485 | utf_8 | dba2e645a6ae060f30c85e3e3bb4874e | /*
*
*/
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "intel_drv.h"
#include "i915_reg.h"
static void i915_save_display(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
/* Display arbitration control */
if (INTEL_INFO(dev)->gen <= 4)
dev_priv->regfile.saveDSPARB = I915_R... |
google | android | i915_gem_context | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_context.c | 28,622 | utf_8 | f520d5bdbf8334046b6abff053a05ae7 | /*
*
*/
/*
* This file implements HW context support. On gen5+ a HW context consists of an
* opaque GPU object which is referenced at times of context saves and restores.
* With RC6 enabled, the context is also referenced as the GPU enters and exists
* from RC6 (GPU has it's own internal power context, except on ... |
google | android | intel_ringbuffer | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_ringbuffer.c | 85,835 | utf_8 | 2ea06dfd4bf6d5e9cacdd9ef49a133ce | /*
*
*/
#include <drm/drmP.h>
#include "i915_drv.h"
#include <drm/i915_drm.h>
#include "i915_trace.h"
#include "intel_drv.h"
bool
intel_ring_initialized(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
if (!dev)
return false;
if (i915.enable_execlists) {
struct intel_context *dctx = ring->de... |
google | android | i915_cmd_parser | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_cmd_parser.c | 36,752 | utf_8 | 16d965b23bd615746cfa8265aa5ebe68 | /*
*
*/
#include "i915_drv.h"
/**
* DOC: batch buffer command parser
*
* Motivation:
* Certain OpenGL features (e.g. transform feedback, performance monitoring)
* require userspace code to submit batches containing commands such as
* MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
* gener... |
google | android | intel_psr | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_psr.c | 24,323 | utf_8 | 651d3a4ec8ecd6f16ea8c195d79f8776 | /*
*/
/**
* DOC: Panel Self Refresh (PSR/SRD)
*
* Since Haswell Display controller supports Panel Self-Refresh on display
* panels witch have a remote frame buffer (RFB) implemented according to PSR
* spec in eDP1.3. PSR feature allows the display to go to lower standby states
* when system is idle but display i... |
google | android | intel_sdvo | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_sdvo.c | 92,328 | utf_8 | dc1309f2e4ff28dbc8838e1ebbcabfdc | /*
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "intel_sdvo_regs.h"
#defin... |
google | android | intel_renderstate_gen8 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_renderstate_gen8.c | 13,793 | utf_8 | 615f26732ab54efe24204a357cde711f | /*
*
* Generated by: intel-gpu-tools-1.8-220-g01153e7
*/
#include "intel_renderstate.h"
static const u32 gen8_null_state_relocs[] = {
0x00000798,
0x000007a4,
0x000007ac,
0x000007bc,
-1,
};
static const u32 gen8_null_state_batch[] = {
0x7a000004,
0x01000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
... |
google | android | intel_mocs | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_mocs.c | 10,974 | utf_8 | 3fe7d0185284399cc4fa1d05168446ee | /*
*/
#include "intel_mocs.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
/* structures required */
struct drm_i915_mocs_entry {
u32 control_value;
u16 l3cc_value;
};
struct drm_i915_mocs_table {
u32 size;
const struct drm_i915_mocs_entry *table;
};
/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
... |
google | android | intel_dsi_pll | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_dsi_pll.c | 16,579 | utf_8 | bbaab2db0edef26bf6f4c51e9caf2e61 | /*
*/
#include <linux/kernel.h>
#include "intel_drv.h"
#include "i915_drv.h"
#include "intel_dsi.h"
#define DSI_HSS_PACKET_SIZE 4
#define DSI_HSE_PACKET_SIZE 4
#define DSI_HSA_PACKET_EXTRA_SIZE 6
#define DSI_HBP_PACKET_EXTRA_SIZE 6
#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6
#define DSI_HFP_PACKET_EXTRA_SIZE 6
#define D... |
google | android | i915_gem_render_state | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/i915_gem_render_state.c | 5,460 | utf_8 | f1278b4fe476ab0ec4de24d8eab2a815 | /*
*
*/
#include "i915_drv.h"
#include "intel_renderstate.h"
static const struct intel_renderstate_rodata *
render_state_get_rodata(struct drm_device *dev, const int gen)
{
switch (gen) {
case 6:
return &gen6_null_state;
case 7:
return &gen7_null_state;
case 8:
return &gen8_null_state;
case 9:
return &ge... |
google | android | intel_renderstate_gen7 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_renderstate_gen7.c | 4,641 | utf_8 | ec59b7ed6306ab557ff25e8dec7676e2 | /*
*
* Generated by: intel-gpu-tools-1.8-220-g01153e7
*/
#include "intel_renderstate.h"
static const u32 gen7_null_state_relocs[] = {
0x0000000c,
0x00000010,
0x00000018,
0x000001ec,
-1,
};
static const u32 gen7_null_state_batch[] = {
0x69040000,
0x61010008,
0x00000000,
0x00000001, /* reloc */
0x00000001, ... |
google | android | intel_tv | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i915/intel_tv.c | 49,500 | utf_8 | 9b2beb991387470f38285afc95c74ee6 | /*
* Integrated TV-out support for the 915GM and 945GM.
*/
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
enum tv_margin {
TV_MARGIN_LEFT, TV_MARGIN_TOP,
TV_MARGIN_RIGHT, TV_MARGIN_BO... |
google | android | intr | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/intr.c | 8,800 | utf_8 | 5cdc299900e5181e0b3269e73ed01b0b | /*
* Tegra host1x Interrupt Management
*
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <trace/events/host1x.h>
#include "channel.h"
#include "dev.h"
#include "intr.h"
/* Wait list management */
enum waitlist_state {
WLS_PENDING,
WLS_REMOVED,
WLS_CAN... |
google | android | mipi | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/mipi.c | 14,913 | utf_8 | de86eede8c9248b79a51bcd959335254 | /*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/host1x.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "dev.h"
#define MIPI_CAL_CTRL 0x00
#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
#define MIPI_CAL_CTRL_P... |
google | android | debug | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/debug.c | 5,130 | utf_8 | ddb7465cec890795ac0e3cd23350fcf9 | /*
*
*/
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include "dev.h"
#include "debug.h"
#include "channel.h"
unsigned int host1x_debug_trace_cmdbuf;
static pid_t host1x_debug_force_timeout_pid;
static u32 host1x_debug_force_timeout_val;
static u32 host1x_deb... |
google | android | cdma | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/cdma.c | 12,750 | utf_8 | e1420ab54bf4f5ba3e9f537ad1401804 | /*
* Tegra host1x Command DMA
*
*/
#include <asm/cacheflush.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/host1x.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/kfifo.h>
#include <linux/slab.h>
#include <trace/events/host1x.h>
#include "cdma.h"
#include "channe... |
google | android | job | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/job.c | 13,411 | utf_8 | d2a9d38c8b1e0bf41af2e44cd93dce5c | /*
* Tegra host1x Job
*
*/
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/host1x.h>
#include <linux/kref.h>
#include <linux/module.h>
#include <linux/scatterlist.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <trace/events/host1x.h>
#include "channel.h"
#include "dev.h"
#includ... |
google | android | dev | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/dev.c | 5,823 | utf_8 | e1c1be716979e98f58ec32fbc6b5bd8d | /*
* Tegra host1x driver
*
*/
#include <linux/module.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#define CREATE_TRACE_POINTS
#include <trace/events/host1x.h>
#include "bus.h"
#include "dev.h"
#include "intr.h"
#inc... |
google | android | bus | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/bus.c | 14,250 | utf_8 | a44af41cbbdaba0a9a3e7c7da6c61eb8 | /*
*/
#include <linux/host1x.h>
#include <linux/of.h>
#include <linux/slab.h>
#include "bus.h"
#include "dev.h"
static DEFINE_MUTEX(clients_lock);
static LIST_HEAD(clients);
static DEFINE_MUTEX(drivers_lock);
static LIST_HEAD(drivers);
static DEFINE_MUTEX(devices_lock);
static LIST_HEAD(devices);
struct host1x_subdev ... |
google | android | syncpt | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/syncpt.c | 11,020 | utf_8 | 795cb1b8256cb0658db312bc1d299a92 | /*
* Tegra host1x Syncpoints
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <trace/events/host1x.h>
#include "syncpt.h"
#include "dev.h"
#include "intr.h"
#include "debug.h"
#define SYNCPT_CHECK_PERIOD (2 * HZ)
#define MAX_STUCK_CHECK_COUNT 15
static struct host1x_syncpt_ba... |
google | android | channel | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/channel.c | 3,195 | utf_8 | c6bd42e933abfdd2353117e605598d25 | /*
* Tegra host1x Channel
*
*/
#include <linux/slab.h>
#include <linux/module.h>
#include "channel.h"
#include "dev.h"
#include "job.h"
/* Constructor for the host1x device list */
int host1x_channel_list_init(struct host1x *host)
{
INIT_LIST_HEAD(&host->chlist.list);
mutex_init(&host->chlist_mutex);
if (host->in... |
google | android | syncpt_hw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/syncpt_hw.c | 2,947 | utf_8 | f9a138eb584fd69d08dac069c7d48da4 | /*
* Tegra host1x Syncpoints
*
*/
#include <linux/io.h>
#include "../dev.h"
#include "../syncpt.h"
/*
* Write the current syncpoint value back to hw.
*/
static void syncpt_restore(struct host1x_syncpt *sp)
{
struct host1x *host = sp->host;
int min = host1x_syncpt_read_min(sp);
host1x_sync_writel(host, min, HOST... |
google | android | debug_hw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/debug_hw.c | 9,166 | utf_8 | f90f9bfc050ea9f4da4d487e67b8b681 | /*
*
*/
#include "../dev.h"
#include "../debug.h"
#include "../cdma.h"
#include "../channel.h"
#define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
enum {
HOST1X_OPCODE_SETCLASS = 0x00,
HOST1X_OPCODE_INCR = 0x01,
HOST1X_OPCODE_NONINCR = 0x02,
HOST1X_OPCODE_MASK = 0x03,
HOST1X_OPCODE_IMM = 0x04,
HOST1X_OPCODE_RESTART = 0... |
google | android | host1x02 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/host1x02.c | 1,205 | utf_8 | 76b12e7b6e2da5e16c7f65a6d78d68d3 | /*
* Host1x init for Tegra114 SoCs
*
*/
/* include hw specification */
#include "host1x02.h"
#include "host1x02_hardware.h"
/* include code */
#include "cdma_hw.c"
#include "channel_hw.c"
#include "debug_hw.c"
#include "intr_hw.c"
#include "syncpt_hw.c"
#include "../dev.h"
int host1x02_init(struct host1x *host)
{
h... |
google | android | cdma_hw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/cdma_hw.c | 9,127 | utf_8 | adb6580673a69a28c496434e83e16d31 | /*
* Tegra host1x Command DMA
*
*/
#include <linux/slab.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include "../cdma.h"
#include "../channel.h"
#include "../dev.h"
#include "../debug.h"
/*
* Put the restart at the end of pushbuffer memory
*/
static void push_buffer_init(struct push_buffer *pb... |
google | android | host1x04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/host1x04.c | 1,205 | utf_8 | bdec1e2b317cbbc90a88c045931ab202 | /*
* Host1x init for Tegra124 SoCs
*
*/
/* include hw specification */
#include "host1x04.h"
#include "host1x04_hardware.h"
/* include code */
#include "cdma_hw.c"
#include "channel_hw.c"
#include "debug_hw.c"
#include "intr_hw.c"
#include "syncpt_hw.c"
#include "../dev.h"
int host1x04_init(struct host1x *host)
{
h... |
google | android | host1x01 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/host1x01.c | 1,228 | utf_8 | 618ea2a2a3ed52f6d70a2463a0442b4c | /*
* Host1x init for T20 and T30 Architecture Chips
*
*/
/* include hw specification */
#include "host1x01.h"
#include "host1x01_hardware.h"
/* include code */
#include "cdma_hw.c"
#include "channel_hw.c"
#include "debug_hw.c"
#include "intr_hw.c"
#include "syncpt_hw.c"
#include "../dev.h"
int host1x01_init(struct h... |
google | android | intr_hw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/intr_hw.c | 4,188 | utf_8 | d7754224f0561d0ae534ddc725b906da | /*
* Tegra host1x Interrupt Management
*
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include "../intr.h"
#include "../dev.h"
/*
* Sync point threshold interrupt service function
* Handles sync point threshold triggers, in interrupt context
*/
static void host1x_intr_syncpt_handle... |
google | android | channel_hw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/host1x/hw/channel_hw.c | 5,151 | utf_8 | 17b2efc04d58c15d4105f7c4a0f006ed | /*
* Tegra host1x Channel
*
*/
#include <linux/host1x.h>
#include <linux/slab.h>
#include <trace/events/host1x.h>
#include "../channel.h"
#include "../dev.h"
#include "../intr.h"
#include "../job.h"
#define HOST1X_CHANNEL_SIZE 16384
#define TRACE_MAX_LENGTH 128U
static void trace_write_gather(struct host1x_cdma *cdm... |
google | android | vga_switcheroo | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/vga/vga_switcheroo.c | 29,732 | utf_8 | c2d74b24820b762c2050e22d95af5ae6 | /*
* vga_switcheroo.c - Support for laptop with dual GPU using one set of outputs
*
*
*/
#define pr_fmt(fmt) "vga_switcheroo: " fmt
#include <linux/console.h>
#include <linux/debugfs.h>
#include <linux/fb.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#includ... |
google | android | vgaarb | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/vga/vgaarb.c | 36,438 | utf_8 | 2b0d5fd9a1b02b4814c415b368afb2c6 | /*
* vgaarb.c: Implements the VGA arbitration. For details refer to
* Documentation/vgaarbiter.txt
*
*
*
*/
#define pr_fmt(fmt) "vgaarb: " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/sched.h... |
google | android | vme | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/vme/vme.c | 38,004 | utf_8 | ed004ffd72324786c75d705a609c5b7f | /*
* VME Bridge Framework
*
* option) any later version.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/highmem.h>
#include <linux/interrupt.h... |
google | android | vme_ca91cx42 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/vme/bridges/vme_ca91cx42.c | 49,845 | utf_8 | 39f1dbdd9edae201830b41ee97981cdf | /*
* Support for the Tundra Universe I/II VME-PCI Bridge Chips
*
* option) any later version.
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/poll.h>
#include <linux/interrupt.h>
#include <linu... |
google | android | vme_tsi148 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/vme/bridges/vme_tsi148.c | 72,161 | utf_8 | 691ad7a19ac7a366433a39312d4aa577 | /*
* Support for the Tundra TSI148 VME-PCI Bridge Chip
*
* option) any later version.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/proc_fs.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/dma-mapp... |
google | android | vme_vmivme7805 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/vme/boards/vme_vmivme7805.c | 2,728 | utf_8 | 3a2c949ab25e5a20d338115ff437a3fc | /*
* Support for the VMIVME-7805 board access to the Universe II bridge.
*
* option) any later version.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/io.h>
#include "vme_vmivme7805.h"
static int vmic_probe(struct pci_dev... |
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