text stringlengths 938 1.05M |
|---|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be... |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
/... |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pm_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it a... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output... |
//Test Bench for Register File
`define N 16
`define K 4
module regfile_tb;
reg clk;
wire [`N-1:0] a,b;
reg [`N-1:0] x;
reg [`K-1:0] sa, sb, d;
reg ld;
regfile #(.n(`N), .k(`K)) r1 (clk, x, ld, d, sa, sb, a, b);
initial begin
clk = 0;
end
initial begin
$monitor("time:%t\tld: %b\tsa: %... |
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Branch ... |
module fir_inj (x_in,clk,y,p_desc0_p_O_FD,p_desc1_p_O_FD,p_desc2_p_O_FD,p_desc3_p_O_FD,p_desc4_p_O_FD,p_desc5_p_O_FD,p_desc6_p_O_FD,p_desc7_p_O_FD,p_desc8_p_O_FD,p_desc9_p_O_FD,p_desc10_p_O_FD,p_desc11_p_O_FD,p_desc12_p_O_FD,p_desc13_p_O_FD,p_desc14_p_O_FD,p_desc15_p_O_FD,p_desc16_p_O_FD,p_desc17_p_O_FD,p_desc18_p_O_FD... |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
/... |
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documen... |
module ADT7310P32S16 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* inters... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:58:55 05/17/2016
// Design Name:
// Module Name: escritor_lector_rtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependen... |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Test.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ===================... |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:44:16 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cor... |
// MBT 9/6/2014
//
// BSG Front Side Bus
//
// This is a *full duplex* front side bus
// that allows output and input traffic
// to proceed independently, from nodes
// into the bsg out assembler; and from
// bsg in assembler to nodes.
//
// It is designed to interoperate with
// the "MURN ring protocol" and nodes,
// ... |
module HeadFieldExtractor (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid,
output wire[63:0] headers_data,
output wire headers_last,
... |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ *********... |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20... |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:09 2017
// Host : TacitMonolith running 64-bit Ubuntu ... |
/*
=========================================================================================================================
| Verilog module for driving a half-bridge (HB) conveter topology in digital current mode control. |
| |
| Theory of operation: This module is very similar to a duty cycle mode... |
`include "mem_beh.v"
`include "regfile_beh.v"
`include "components.v"
`include "control_units.v"
`include "alu_beh.v"
`include "mux2to1_beh.v"
module kustar;
reg clock, clear;
wire [31:0] MuxtoPC, PCtoMux, MuxtoMem, MemtoInstReg, SigntoShift, ShifttoMux, MemdatatoMux, MuxtoWriteData;
wire [31:0] RegtoA, RegtoB, AtoMu... |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:03:52 2017
// Host : GILAMONSTER running 64-bit major rel... |
module fifo_tb();
// Declarations/*{{{*/
// Slave side
reg s_aclk;
reg s_aresetn;
reg s_axis_tvalid;
wire s_axis_tready;
reg [63:0] s_axis_tdata;
reg [7:0] s_axis_tkeep;
reg ... |
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_D_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test D (11 AM)
*/
module Traffic_Test;
// Inputs... |
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter v771499 = "v771499.list"
) (
input vclk,
output [3:0] v894180,
output [0:0] vinit
);
localparam p0 = v771499;
wire [0:7] w1;
wire [0:3] w2;
wire [0:7] w3;
wire w4;
assign v894180 = w2;
assign ... |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
... |
//-----------------------------------------------------------------
//
// The original verilog code provided by Clifford E. Cummings,
// Sunburst Design, Inc.
//
// Email: <cliffc@sunburst-design.com>
// Web: www.sunburst-design.com
//
//----------------------------------------------------------------
... |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software... |
/**************************************************************************
*
* File Name: MT48LC4M16A2.V
* Version: 2.1
* Date: June 6th, 2002
* Model: BUS Functional
* Simulator: Model Technology
*
* Dependencies: None
*
* Email: modelsupport@micron.com
* Company: Micro... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
... |
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// `include "define.v"
// `include "regfile.v"
// `include "hilo_reg.v"
// `include "BranchControl.v"
// `include "HazardControl.v"
// `include "ForwardControl.v"
// `include "IF.v"
// `include "IF_ID.v"
// `include "ID.v"
// `include "ID_EX.v"
// `include "EX.v"
// `include "ALU.v"
// `include "decoder.v"
// `include ... |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution an... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 11th August 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free... |
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either ve... |
module pipeline(
input Clk,
output [31:0] PC_in,PC_out,
output [2:0]PCSrc,
//1
/*output[5:0] Op_IF,
output[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF,
output[5:0] Func_IF,
*/
//3
/*output[31:0] Branch_addr_EX,PC_Add_EX,
output[2:0] Condition_EX,
output Branch_EX,
output[2:0]PC_write_EX,
output[3:0]Mem_Write_Byte_en_EX,Rd_Write_By... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:25:47 05/08/2012
// Design Name: cls_spi
// Module Name: G:/Projects/s6atlystest/cls_spi_tb.v
// Project Name: s6atlystest
// Target Device:
// Tool versions: ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// Single-bit clock-domain crossing synchronizer
//
// Notes:
// A synchronizer is a device that takes an asynchronous
// input and produces an output signal that transitions
// synchronous to a sample clock
//
// The single-bit clock domain synchronizer safely
// transfers the output from clock domain A to
// clock ... |
// Copyright (c) 2013, Simon Que
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the... |
(** * Auto: More Automation *)
Require Import Coq.omega.Omega.
Require Import Maps.
Require Import Imp.
(** Up to now, we've used the more manual part of Coq's tactic
facilities. In this chapter, we'll learn more about some of Coq's
powerful automation features: proof search via the [auto] tactic,
automa... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
//-------------------------------------------------------------------
//-- counter_tb.v
//-- Banco de pruebas para el contador
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-----------------------------------------------------------------... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// MBT 7/7/16
//
// bsg_channel_tunnel
//
// This module allows you to multiplex multiple streams over a shared
// interconnect without having deadlock occur because of stream interleaving.
//
// There are three models for interleaving streams:
//
// a. Your stream is guaranteed to be sunk by the remote node without
/... |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:58:40 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1... |
// Copyright 2008, 2009 by Jakub Bednarski
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later v... |
module qsys_serial_device#(
parameter address_size=8)(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output reg[31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [7:0] avs_ctrl_address,
input avs_ctrl_write,
input... |
// DESCRIPTION: Verilator: Test symbol table scope map and general public
// signal reflection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
module t (
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #... |
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave_0_base(
clk,sck,mosi,miso,ssel,rst_n,reciv... |
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally d... |
/* -*- tab-width: 4 -*-
*
* Electric(tm) VLSI Design System
*
* File: jtagController.v
*
* Copyright (c) 2005 Sun Microsystems and Static Free Software
*
* Electric(tm) is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Sof... |
`timescale 1ns/1ps
`include "sata_defines.v"
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
output linkup, //link is finished
output sata_ready,
output sata_busy,
//input write_d... |
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distri... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
`include "e200_defines.v"
module tb_top();
reg clk;
reg lfextclk;
reg rst_n;
wire hfclkrst;
wire hfclk = clk & (~hfclkrst);
`define CPU_TOP u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top
`define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu
`define ITCM `CPU_TOP.u_e200_... |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_byp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and... |
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// a... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:07:21 09/17/2015
// Design Name: Manual Keypad Scanner and Encoder
// Module Name: Lab2Part1Fall2015AJM
//////////////////////////////... |
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_cpu_reset_server_request_put O 1 reg
// cpu_reset_server_response_get O 1 reg
// RDY_cpu_reset_... |
module antiDroopIIR_16 (
input clk,
input trig,
input signed [15:0] din,
input signed [6:0] tapWeight,
input accClr_en,
//input oflowClr,
(* shreg_extract = "no" *) output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multipl... |
/*
* Programing Notes:
1, there are four SPRs in uartlite, access using mtspr/mfspr instructions
2, the four register are:
control register
ctrl[0]: tx_start
ctrl[1]: rx_disenable
ctrl[2]: tx_interrupt_ebable - currently not in use
ctrl[3]: rx_interrupt_ena... |
/****************************************
Mul Unit
- Booth Algorithm
- 32bit Adder
Make : 2010/12/07
Update :
****************************************/
`default_nettype none
module execute_mul_booth32(
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [63:0] oDATA... |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gr... |
/**
* bsg_cache_non_blocking_dma.v
*
* DMA engine
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_dma
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This test demonstrates an issue with sign extension.
// Assigning to localparms larger than 32 bits broke in 3.862
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Mike Thyer.
module t (/*AUTOARG*/
// Inputs
cl... |
// Library - static, Cell - th44w3, View - schematic
// LAST TIME SAVED: May 23 17:58:12 2014
// NETLIST TIME: May 23 17:58:31 2014
`timescale 1ns / 1ns
module th44w3 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w3";
specpar... |
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "li... |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or... |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, w... |
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_cpu_reset_server_request_put O 1 reg
// cpu_reset_server_response_get O 1 reg
// RDY_cpu_reset_server_response_get O 1 reg
// cpu_imem_master_awvalid O 1 reg
// cpu_imem... |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* ... |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major rel... |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distri... |
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This p... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/* Atari on an FPGA
Masters of Engineering Project
Cornell University, 2007
Daniel Beer
RIOT.v
Redesign of the MOS 6532 chip. Provides RAM, I/O and timers to the Atari.
*/
`timescale 1ns / 1ps
`include "riot.vh"
module RIOT(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS,... |
/*
* Quarter-wave sine table.
* Features:
* - Parameterized for arbitrary input & output widths
* - 1/2 LSB angle offset for glitch-free quarter wave sine table
* - Unsigned quarter wave Lookup table
* - Sine table size is 2^(ANGLE_WIDTH-2) x OUT_WIDTH-1
* - 2 clock delay between input and output
*
* For a size exampl... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:14 04/19/2014
// Design Name:
// Module Name: Image_viewer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
/... |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:36:35 2017
// Host : TheMosass-PC running 64-bit major re... |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required ... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
logic [3:0] array_oned... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:01:37 04/27/2014
// Design Name: Image_viewer_top
// Module Name: /home/student/Dropbox/EE 201 Final Project/SynchronousRead/top_tb.v
// Project Name: Synchronous... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
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