repo_name string | path string | copies string | size string | content string | license string |
|---|---|---|---|---|---|
mitake/linux | fs/configfs/symlink.c | 8620 | 7556 | /* -*- mode: c; c-basic-offset: 8; -*-
* vim: noexpandtab sw=8 ts=8 sts=0:
*
* symlink.c - operations for configfs symlinks.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 021110-1307, USA.
*
* Based on sysfs:
* sysfs is Copyright (C) 2001, 2002, 2003 Patrick Mochel
*
* configfs Copyright (C) 2005 Oracle. All rights reserved.
*/
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/namei.h>
#include <linux/slab.h>
#include <linux/configfs.h>
#include "configfs_internal.h"
/* Protects attachments of new symlinks */
DEFINE_MUTEX(configfs_symlink_mutex);
static int item_depth(struct config_item * item)
{
struct config_item * p = item;
int depth = 0;
do { depth++; } while ((p = p->ci_parent) && !configfs_is_root(p));
return depth;
}
static int item_path_length(struct config_item * item)
{
struct config_item * p = item;
int length = 1;
do {
length += strlen(config_item_name(p)) + 1;
p = p->ci_parent;
} while (p && !configfs_is_root(p));
return length;
}
static void fill_item_path(struct config_item * item, char * buffer, int length)
{
struct config_item * p;
--length;
for (p = item; p && !configfs_is_root(p); p = p->ci_parent) {
int cur = strlen(config_item_name(p));
/* back up enough to print this bus id with '/' */
length -= cur;
strncpy(buffer + length,config_item_name(p),cur);
*(buffer + --length) = '/';
}
}
static int create_link(struct config_item *parent_item,
struct config_item *item,
struct dentry *dentry)
{
struct configfs_dirent *target_sd = item->ci_dentry->d_fsdata;
struct configfs_symlink *sl;
int ret;
ret = -ENOENT;
if (!configfs_dirent_is_ready(target_sd))
goto out;
ret = -ENOMEM;
sl = kmalloc(sizeof(struct configfs_symlink), GFP_KERNEL);
if (sl) {
sl->sl_target = config_item_get(item);
spin_lock(&configfs_dirent_lock);
if (target_sd->s_type & CONFIGFS_USET_DROPPING) {
spin_unlock(&configfs_dirent_lock);
config_item_put(item);
kfree(sl);
return -ENOENT;
}
list_add(&sl->sl_list, &target_sd->s_links);
spin_unlock(&configfs_dirent_lock);
ret = configfs_create_link(sl, parent_item->ci_dentry,
dentry);
if (ret) {
spin_lock(&configfs_dirent_lock);
list_del_init(&sl->sl_list);
spin_unlock(&configfs_dirent_lock);
config_item_put(item);
kfree(sl);
}
}
out:
return ret;
}
static int get_target(const char *symname, struct path *path,
struct config_item **target, struct super_block *sb)
{
int ret;
ret = kern_path(symname, LOOKUP_FOLLOW|LOOKUP_DIRECTORY, path);
if (!ret) {
if (path->dentry->d_sb == sb) {
*target = configfs_get_config_item(path->dentry);
if (!*target) {
ret = -ENOENT;
path_put(path);
}
} else {
ret = -EPERM;
path_put(path);
}
}
return ret;
}
int configfs_symlink(struct inode *dir, struct dentry *dentry, const char *symname)
{
int ret;
struct path path;
struct configfs_dirent *sd;
struct config_item *parent_item;
struct config_item *target_item = NULL;
struct config_item_type *type;
sd = dentry->d_parent->d_fsdata;
/*
* Fake invisibility if dir belongs to a group/default groups hierarchy
* being attached
*/
ret = -ENOENT;
if (!configfs_dirent_is_ready(sd))
goto out;
parent_item = configfs_get_config_item(dentry->d_parent);
type = parent_item->ci_type;
ret = -EPERM;
if (!type || !type->ct_item_ops ||
!type->ct_item_ops->allow_link)
goto out_put;
ret = get_target(symname, &path, &target_item, dentry->d_sb);
if (ret)
goto out_put;
ret = type->ct_item_ops->allow_link(parent_item, target_item);
if (!ret) {
mutex_lock(&configfs_symlink_mutex);
ret = create_link(parent_item, target_item, dentry);
mutex_unlock(&configfs_symlink_mutex);
if (ret && type->ct_item_ops->drop_link)
type->ct_item_ops->drop_link(parent_item,
target_item);
}
config_item_put(target_item);
path_put(&path);
out_put:
config_item_put(parent_item);
out:
return ret;
}
int configfs_unlink(struct inode *dir, struct dentry *dentry)
{
struct configfs_dirent *sd = dentry->d_fsdata;
struct configfs_symlink *sl;
struct config_item *parent_item;
struct config_item_type *type;
int ret;
ret = -EPERM; /* What lack-of-symlink returns */
if (!(sd->s_type & CONFIGFS_ITEM_LINK))
goto out;
sl = sd->s_element;
parent_item = configfs_get_config_item(dentry->d_parent);
type = parent_item->ci_type;
spin_lock(&configfs_dirent_lock);
list_del_init(&sd->s_sibling);
spin_unlock(&configfs_dirent_lock);
configfs_drop_dentry(sd, dentry->d_parent);
dput(dentry);
configfs_put(sd);
/*
* drop_link() must be called before
* list_del_init(&sl->sl_list), so that the order of
* drop_link(this, target) and drop_item(target) is preserved.
*/
if (type && type->ct_item_ops &&
type->ct_item_ops->drop_link)
type->ct_item_ops->drop_link(parent_item,
sl->sl_target);
spin_lock(&configfs_dirent_lock);
list_del_init(&sl->sl_list);
spin_unlock(&configfs_dirent_lock);
/* Put reference from create_link() */
config_item_put(sl->sl_target);
kfree(sl);
config_item_put(parent_item);
ret = 0;
out:
return ret;
}
static int configfs_get_target_path(struct config_item * item, struct config_item * target,
char *path)
{
char * s;
int depth, size;
depth = item_depth(item);
size = item_path_length(target) + depth * 3 - 1;
if (size > PATH_MAX)
return -ENAMETOOLONG;
pr_debug("%s: depth = %d, size = %d\n", __func__, depth, size);
for (s = path; depth--; s += 3)
strcpy(s,"../");
fill_item_path(target, path, size);
pr_debug("%s: path = '%s'\n", __func__, path);
return 0;
}
static int configfs_getlink(struct dentry *dentry, char * path)
{
struct config_item *item, *target_item;
int error = 0;
item = configfs_get_config_item(dentry->d_parent);
if (!item)
return -EINVAL;
target_item = configfs_get_config_item(dentry);
if (!target_item) {
config_item_put(item);
return -EINVAL;
}
down_read(&configfs_rename_sem);
error = configfs_get_target_path(item, target_item, path);
up_read(&configfs_rename_sem);
config_item_put(item);
config_item_put(target_item);
return error;
}
static void *configfs_follow_link(struct dentry *dentry, struct nameidata *nd)
{
int error = -ENOMEM;
unsigned long page = get_zeroed_page(GFP_KERNEL);
if (page) {
error = configfs_getlink(dentry, (char *)page);
if (!error) {
nd_set_link(nd, (char *)page);
return (void *)page;
}
}
nd_set_link(nd, ERR_PTR(error));
return NULL;
}
static void configfs_put_link(struct dentry *dentry, struct nameidata *nd,
void *cookie)
{
if (cookie) {
unsigned long page = (unsigned long)cookie;
free_page(page);
}
}
const struct inode_operations configfs_symlink_inode_operations = {
.follow_link = configfs_follow_link,
.readlink = generic_readlink,
.put_link = configfs_put_link,
.setattr = configfs_setattr,
};
| gpl-2.0 |
EPDCenter/android_kernel_rockchip_mk908 | net/ipv6/ping.c | 173 | 5794 | /*
* INET An implementation of the TCP/IP protocol suite for the LINUX
* operating system. INET is implemented using the BSD Socket
* interface as the means of communication with the user level.
*
* "Ping" sockets
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Based on ipv4/ping.c code.
*
* Authors: Lorenzo Colitti (IPv6 support)
* Vasiliy Kulikov / Openwall (IPv4 implementation, for Linux 2.6),
* Pavel Kankovsky (IPv4 implementation, for Linux 2.4.32)
*
*/
#include <net/addrconf.h>
#include <net/ipv6.h>
#include <net/ip6_route.h>
#include <net/protocol.h>
#include <net/udp.h>
#include <net/transp_v6.h>
#include <net/ping.h>
struct proto pingv6_prot = {
.name = "PINGv6",
.owner = THIS_MODULE,
.init = ping_init_sock,
.close = ping_close,
.connect = ip6_datagram_connect,
.disconnect = udp_disconnect,
.setsockopt = ipv6_setsockopt,
.getsockopt = ipv6_getsockopt,
.sendmsg = ping_v6_sendmsg,
.recvmsg = ping_recvmsg,
.bind = ping_bind,
.backlog_rcv = ping_queue_rcv_skb,
.hash = ping_hash,
.unhash = ping_unhash,
.get_port = ping_get_port,
.obj_size = sizeof(struct raw6_sock),
};
EXPORT_SYMBOL_GPL(pingv6_prot);
static struct inet_protosw pingv6_protosw = {
.type = SOCK_DGRAM,
.protocol = IPPROTO_ICMPV6,
.prot = &pingv6_prot,
.ops = &inet6_dgram_ops,
.no_check = UDP_CSUM_DEFAULT,
.flags = INET_PROTOSW_REUSE,
};
/* Compatibility glue so we can support IPv6 when it's compiled as a module */
int dummy_ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len)
{
return -EAFNOSUPPORT;
}
int dummy_datagram_recv_ctl(struct sock *sk, struct msghdr *msg,
struct sk_buff *skb)
{
return -EAFNOSUPPORT;
}
int dummy_icmpv6_err_convert(u8 type, u8 code, int *err)
{
return -EAFNOSUPPORT;
}
void dummy_ipv6_icmp_error(struct sock *sk, struct sk_buff *skb, int err,
__be16 port, u32 info, u8 *payload) {}
int dummy_ipv6_chk_addr(struct net *net, const struct in6_addr *addr,
struct net_device *dev, int strict)
{
return 0;
}
int __init pingv6_init(void)
{
pingv6_ops.ipv6_recv_error = ipv6_recv_error;
pingv6_ops.datagram_recv_ctl = datagram_recv_ctl;
pingv6_ops.icmpv6_err_convert = icmpv6_err_convert;
pingv6_ops.ipv6_icmp_error = ipv6_icmp_error;
pingv6_ops.ipv6_chk_addr = ipv6_chk_addr;
return inet6_register_protosw(&pingv6_protosw);
}
/* This never gets called because it's not possible to unload the ipv6 module,
* but just in case.
*/
void pingv6_exit(void)
{
pingv6_ops.ipv6_recv_error = dummy_ipv6_recv_error;
pingv6_ops.datagram_recv_ctl = dummy_datagram_recv_ctl;
pingv6_ops.icmpv6_err_convert = dummy_icmpv6_err_convert;
pingv6_ops.ipv6_icmp_error = dummy_ipv6_icmp_error;
pingv6_ops.ipv6_chk_addr = dummy_ipv6_chk_addr;
inet6_unregister_protosw(&pingv6_protosw);
}
int ping_v6_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
size_t len)
{
struct inet_sock *inet = inet_sk(sk);
struct ipv6_pinfo *np = inet6_sk(sk);
struct icmp6hdr user_icmph;
int addr_type;
struct in6_addr *daddr;
int iif = 0;
struct flowi6 fl6;
int err;
int hlimit;
struct dst_entry *dst;
struct rt6_info *rt;
struct pingfakehdr pfh;
pr_debug("ping_v6_sendmsg(sk=%p,sk->num=%u)\n", inet, inet->inet_num);
err = ping_common_sendmsg(AF_INET6, msg, len, &user_icmph,
sizeof(user_icmph));
if (err)
return err;
if (msg->msg_name) {
struct sockaddr_in6 *u = (struct sockaddr_in6 *) msg->msg_name;
if (msg->msg_namelen < sizeof(struct sockaddr_in6) ||
u->sin6_family != AF_INET6) {
return -EINVAL;
}
if (sk->sk_bound_dev_if &&
sk->sk_bound_dev_if != u->sin6_scope_id) {
return -EINVAL;
}
daddr = &(u->sin6_addr);
iif = u->sin6_scope_id;
} else {
if (sk->sk_state != TCP_ESTABLISHED)
return -EDESTADDRREQ;
daddr = &np->daddr;
}
if (!iif)
iif = sk->sk_bound_dev_if;
addr_type = ipv6_addr_type(daddr);
if (__ipv6_addr_needs_scope_id(addr_type) && !iif)
return -EINVAL;
if (addr_type & IPV6_ADDR_MAPPED)
return -EINVAL;
/* TODO: use ip6_datagram_send_ctl to get options from cmsg */
memset(&fl6, 0, sizeof(fl6));
fl6.flowi6_proto = IPPROTO_ICMPV6;
fl6.saddr = np->saddr;
fl6.daddr = *daddr;
fl6.fl6_icmp_type = user_icmph.icmp6_type;
fl6.fl6_icmp_code = user_icmph.icmp6_code;
security_sk_classify_flow(sk, flowi6_to_flowi(&fl6));
if (!fl6.flowi6_oif && ipv6_addr_is_multicast(&fl6.daddr))
fl6.flowi6_oif = np->mcast_oif;
dst = ip6_sk_dst_lookup_flow(sk, &fl6, daddr, 1);
if (IS_ERR(dst))
return PTR_ERR(dst);
rt = (struct rt6_info *) dst;
np = inet6_sk(sk);
if (!np)
return -EBADF;
if (!fl6.flowi6_oif && ipv6_addr_is_multicast(&fl6.daddr))
fl6.flowi6_oif = np->mcast_oif;
pfh.icmph.type = user_icmph.icmp6_type;
pfh.icmph.code = user_icmph.icmp6_code;
pfh.icmph.checksum = 0;
pfh.icmph.un.echo.id = inet->inet_sport;
pfh.icmph.un.echo.sequence = user_icmph.icmp6_sequence;
pfh.iov = msg->msg_iov;
pfh.wcheck = 0;
pfh.family = AF_INET6;
if (ipv6_addr_is_multicast(&fl6.daddr))
hlimit = np->mcast_hops;
else
hlimit = np->hop_limit;
if (hlimit < 0)
hlimit = ip6_dst_hoplimit(dst);
lock_sock(sk);
err = ip6_append_data(sk, ping_getfrag, &pfh, len,
0, hlimit,
np->tclass, NULL, &fl6, rt,
MSG_DONTWAIT, np->dontfrag);
if (err) {
ICMP6_INC_STATS_BH(sock_net(sk), rt->rt6i_idev,
ICMP6_MIB_OUTERRORS);
ip6_flush_pending_frames(sk);
} else {
err = icmpv6_push_pending_frames(sk, &fl6,
(struct icmp6hdr *) &pfh.icmph,
len);
}
release_sock(sk);
if (err)
return err;
return len;
}
| gpl-2.0 |
Altaf-Mahdi/android_kernel_oneplus_msm8994 | fs/btrfs/extent_io.c | 173 | 129418 | #include <linux/bitops.h>
#include <linux/slab.h>
#include <linux/bio.h>
#include <linux/mm.h>
#include <linux/pagemap.h>
#include <linux/page-flags.h>
#include <linux/spinlock.h>
#include <linux/blkdev.h>
#include <linux/swap.h>
#include <linux/writeback.h>
#include <linux/pagevec.h>
#include <linux/prefetch.h>
#include <linux/cleancache.h>
#include "extent_io.h"
#include "extent_map.h"
#include "compat.h"
#include "ctree.h"
#include "btrfs_inode.h"
#include "volumes.h"
#include "check-integrity.h"
#include "locking.h"
#include "rcu-string.h"
static struct kmem_cache *extent_state_cache;
static struct kmem_cache *extent_buffer_cache;
static struct bio_set *btrfs_bioset;
#ifdef CONFIG_BTRFS_DEBUG
static LIST_HEAD(buffers);
static LIST_HEAD(states);
static DEFINE_SPINLOCK(leak_lock);
static inline
void btrfs_leak_debug_add(struct list_head *new, struct list_head *head)
{
unsigned long flags;
spin_lock_irqsave(&leak_lock, flags);
list_add(new, head);
spin_unlock_irqrestore(&leak_lock, flags);
}
static inline
void btrfs_leak_debug_del(struct list_head *entry)
{
unsigned long flags;
spin_lock_irqsave(&leak_lock, flags);
list_del(entry);
spin_unlock_irqrestore(&leak_lock, flags);
}
static inline
void btrfs_leak_debug_check(void)
{
struct extent_state *state;
struct extent_buffer *eb;
while (!list_empty(&states)) {
state = list_entry(states.next, struct extent_state, leak_list);
printk(KERN_ERR "btrfs state leak: start %llu end %llu "
"state %lu in tree %p refs %d\n",
(unsigned long long)state->start,
(unsigned long long)state->end,
state->state, state->tree, atomic_read(&state->refs));
list_del(&state->leak_list);
kmem_cache_free(extent_state_cache, state);
}
while (!list_empty(&buffers)) {
eb = list_entry(buffers.next, struct extent_buffer, leak_list);
printk(KERN_ERR "btrfs buffer leak start %llu len %lu "
"refs %d\n", (unsigned long long)eb->start,
eb->len, atomic_read(&eb->refs));
list_del(&eb->leak_list);
kmem_cache_free(extent_buffer_cache, eb);
}
}
#else
#define btrfs_leak_debug_add(new, head) do {} while (0)
#define btrfs_leak_debug_del(entry) do {} while (0)
#define btrfs_leak_debug_check() do {} while (0)
#endif
#define BUFFER_LRU_MAX 64
struct tree_entry {
u64 start;
u64 end;
struct rb_node rb_node;
};
struct extent_page_data {
struct bio *bio;
struct extent_io_tree *tree;
get_extent_t *get_extent;
unsigned long bio_flags;
/* tells writepage not to lock the state bits for this range
* it still does the unlocking
*/
unsigned int extent_locked:1;
/* tells the submit_bio code to use a WRITE_SYNC */
unsigned int sync_io:1;
};
static noinline void flush_write_bio(void *data);
static inline struct btrfs_fs_info *
tree_fs_info(struct extent_io_tree *tree)
{
return btrfs_sb(tree->mapping->host->i_sb);
}
int __init extent_io_init(void)
{
extent_state_cache = kmem_cache_create("btrfs_extent_state",
sizeof(struct extent_state), 0,
SLAB_RECLAIM_ACCOUNT | SLAB_MEM_SPREAD, NULL);
if (!extent_state_cache)
return -ENOMEM;
extent_buffer_cache = kmem_cache_create("btrfs_extent_buffer",
sizeof(struct extent_buffer), 0,
SLAB_RECLAIM_ACCOUNT | SLAB_MEM_SPREAD, NULL);
if (!extent_buffer_cache)
goto free_state_cache;
btrfs_bioset = bioset_create(BIO_POOL_SIZE,
offsetof(struct btrfs_io_bio, bio));
if (!btrfs_bioset)
goto free_buffer_cache;
return 0;
free_buffer_cache:
kmem_cache_destroy(extent_buffer_cache);
extent_buffer_cache = NULL;
free_state_cache:
kmem_cache_destroy(extent_state_cache);
extent_state_cache = NULL;
return -ENOMEM;
}
void extent_io_exit(void)
{
btrfs_leak_debug_check();
/*
* Make sure all delayed rcu free are flushed before we
* destroy caches.
*/
rcu_barrier();
if (extent_state_cache)
kmem_cache_destroy(extent_state_cache);
if (extent_buffer_cache)
kmem_cache_destroy(extent_buffer_cache);
if (btrfs_bioset)
bioset_free(btrfs_bioset);
}
void extent_io_tree_init(struct extent_io_tree *tree,
struct address_space *mapping)
{
tree->state = RB_ROOT;
INIT_RADIX_TREE(&tree->buffer, GFP_ATOMIC);
tree->ops = NULL;
tree->dirty_bytes = 0;
spin_lock_init(&tree->lock);
spin_lock_init(&tree->buffer_lock);
tree->mapping = mapping;
}
static struct extent_state *alloc_extent_state(gfp_t mask)
{
struct extent_state *state;
state = kmem_cache_alloc(extent_state_cache, mask);
if (!state)
return state;
state->state = 0;
state->private = 0;
state->tree = NULL;
btrfs_leak_debug_add(&state->leak_list, &states);
atomic_set(&state->refs, 1);
init_waitqueue_head(&state->wq);
trace_alloc_extent_state(state, mask, _RET_IP_);
return state;
}
void free_extent_state(struct extent_state *state)
{
if (!state)
return;
if (atomic_dec_and_test(&state->refs)) {
WARN_ON(state->tree);
btrfs_leak_debug_del(&state->leak_list);
trace_free_extent_state(state, _RET_IP_);
kmem_cache_free(extent_state_cache, state);
}
}
static struct rb_node *tree_insert(struct rb_root *root, u64 offset,
struct rb_node *node)
{
struct rb_node **p = &root->rb_node;
struct rb_node *parent = NULL;
struct tree_entry *entry;
while (*p) {
parent = *p;
entry = rb_entry(parent, struct tree_entry, rb_node);
if (offset < entry->start)
p = &(*p)->rb_left;
else if (offset > entry->end)
p = &(*p)->rb_right;
else
return parent;
}
rb_link_node(node, parent, p);
rb_insert_color(node, root);
return NULL;
}
static struct rb_node *__etree_search(struct extent_io_tree *tree, u64 offset,
struct rb_node **prev_ret,
struct rb_node **next_ret)
{
struct rb_root *root = &tree->state;
struct rb_node *n = root->rb_node;
struct rb_node *prev = NULL;
struct rb_node *orig_prev = NULL;
struct tree_entry *entry;
struct tree_entry *prev_entry = NULL;
while (n) {
entry = rb_entry(n, struct tree_entry, rb_node);
prev = n;
prev_entry = entry;
if (offset < entry->start)
n = n->rb_left;
else if (offset > entry->end)
n = n->rb_right;
else
return n;
}
if (prev_ret) {
orig_prev = prev;
while (prev && offset > prev_entry->end) {
prev = rb_next(prev);
prev_entry = rb_entry(prev, struct tree_entry, rb_node);
}
*prev_ret = prev;
prev = orig_prev;
}
if (next_ret) {
prev_entry = rb_entry(prev, struct tree_entry, rb_node);
while (prev && offset < prev_entry->start) {
prev = rb_prev(prev);
prev_entry = rb_entry(prev, struct tree_entry, rb_node);
}
*next_ret = prev;
}
return NULL;
}
static inline struct rb_node *tree_search(struct extent_io_tree *tree,
u64 offset)
{
struct rb_node *prev = NULL;
struct rb_node *ret;
ret = __etree_search(tree, offset, &prev, NULL);
if (!ret)
return prev;
return ret;
}
static void merge_cb(struct extent_io_tree *tree, struct extent_state *new,
struct extent_state *other)
{
if (tree->ops && tree->ops->merge_extent_hook)
tree->ops->merge_extent_hook(tree->mapping->host, new,
other);
}
/*
* utility function to look for merge candidates inside a given range.
* Any extents with matching state are merged together into a single
* extent in the tree. Extents with EXTENT_IO in their state field
* are not merged because the end_io handlers need to be able to do
* operations on them without sleeping (or doing allocations/splits).
*
* This should be called with the tree lock held.
*/
static void merge_state(struct extent_io_tree *tree,
struct extent_state *state)
{
struct extent_state *other;
struct rb_node *other_node;
if (state->state & (EXTENT_IOBITS | EXTENT_BOUNDARY))
return;
other_node = rb_prev(&state->rb_node);
if (other_node) {
other = rb_entry(other_node, struct extent_state, rb_node);
if (other->end == state->start - 1 &&
other->state == state->state) {
merge_cb(tree, state, other);
state->start = other->start;
other->tree = NULL;
rb_erase(&other->rb_node, &tree->state);
free_extent_state(other);
}
}
other_node = rb_next(&state->rb_node);
if (other_node) {
other = rb_entry(other_node, struct extent_state, rb_node);
if (other->start == state->end + 1 &&
other->state == state->state) {
merge_cb(tree, state, other);
state->end = other->end;
other->tree = NULL;
rb_erase(&other->rb_node, &tree->state);
free_extent_state(other);
}
}
}
static void set_state_cb(struct extent_io_tree *tree,
struct extent_state *state, unsigned long *bits)
{
if (tree->ops && tree->ops->set_bit_hook)
tree->ops->set_bit_hook(tree->mapping->host, state, bits);
}
static void clear_state_cb(struct extent_io_tree *tree,
struct extent_state *state, unsigned long *bits)
{
if (tree->ops && tree->ops->clear_bit_hook)
tree->ops->clear_bit_hook(tree->mapping->host, state, bits);
}
static void set_state_bits(struct extent_io_tree *tree,
struct extent_state *state, unsigned long *bits);
/*
* insert an extent_state struct into the tree. 'bits' are set on the
* struct before it is inserted.
*
* This may return -EEXIST if the extent is already there, in which case the
* state struct is freed.
*
* The tree lock is not taken internally. This is a utility function and
* probably isn't what you want to call (see set/clear_extent_bit).
*/
static int insert_state(struct extent_io_tree *tree,
struct extent_state *state, u64 start, u64 end,
unsigned long *bits)
{
struct rb_node *node;
if (end < start)
WARN(1, KERN_ERR "btrfs end < start %llu %llu\n",
(unsigned long long)end,
(unsigned long long)start);
state->start = start;
state->end = end;
set_state_bits(tree, state, bits);
node = tree_insert(&tree->state, end, &state->rb_node);
if (node) {
struct extent_state *found;
found = rb_entry(node, struct extent_state, rb_node);
printk(KERN_ERR "btrfs found node %llu %llu on insert of "
"%llu %llu\n", (unsigned long long)found->start,
(unsigned long long)found->end,
(unsigned long long)start, (unsigned long long)end);
return -EEXIST;
}
state->tree = tree;
merge_state(tree, state);
return 0;
}
static void split_cb(struct extent_io_tree *tree, struct extent_state *orig,
u64 split)
{
if (tree->ops && tree->ops->split_extent_hook)
tree->ops->split_extent_hook(tree->mapping->host, orig, split);
}
/*
* split a given extent state struct in two, inserting the preallocated
* struct 'prealloc' as the newly created second half. 'split' indicates an
* offset inside 'orig' where it should be split.
*
* Before calling,
* the tree has 'orig' at [orig->start, orig->end]. After calling, there
* are two extent state structs in the tree:
* prealloc: [orig->start, split - 1]
* orig: [ split, orig->end ]
*
* The tree locks are not taken by this function. They need to be held
* by the caller.
*/
static int split_state(struct extent_io_tree *tree, struct extent_state *orig,
struct extent_state *prealloc, u64 split)
{
struct rb_node *node;
split_cb(tree, orig, split);
prealloc->start = orig->start;
prealloc->end = split - 1;
prealloc->state = orig->state;
orig->start = split;
node = tree_insert(&tree->state, prealloc->end, &prealloc->rb_node);
if (node) {
free_extent_state(prealloc);
return -EEXIST;
}
prealloc->tree = tree;
return 0;
}
static struct extent_state *next_state(struct extent_state *state)
{
struct rb_node *next = rb_next(&state->rb_node);
if (next)
return rb_entry(next, struct extent_state, rb_node);
else
return NULL;
}
/*
* utility function to clear some bits in an extent state struct.
* it will optionally wake up any one waiting on this state (wake == 1).
*
* If no bits are set on the state struct after clearing things, the
* struct is freed and removed from the tree
*/
static struct extent_state *clear_state_bit(struct extent_io_tree *tree,
struct extent_state *state,
unsigned long *bits, int wake)
{
struct extent_state *next;
unsigned long bits_to_clear = *bits & ~EXTENT_CTLBITS;
if ((bits_to_clear & EXTENT_DIRTY) && (state->state & EXTENT_DIRTY)) {
u64 range = state->end - state->start + 1;
WARN_ON(range > tree->dirty_bytes);
tree->dirty_bytes -= range;
}
clear_state_cb(tree, state, bits);
state->state &= ~bits_to_clear;
if (wake)
wake_up(&state->wq);
if (state->state == 0) {
next = next_state(state);
if (state->tree) {
rb_erase(&state->rb_node, &tree->state);
state->tree = NULL;
free_extent_state(state);
} else {
WARN_ON(1);
}
} else {
merge_state(tree, state);
next = next_state(state);
}
return next;
}
static struct extent_state *
alloc_extent_state_atomic(struct extent_state *prealloc)
{
if (!prealloc)
prealloc = alloc_extent_state(GFP_ATOMIC);
return prealloc;
}
static void extent_io_tree_panic(struct extent_io_tree *tree, int err)
{
btrfs_panic(tree_fs_info(tree), err, "Locking error: "
"Extent tree was modified by another "
"thread while locked.");
}
/*
* clear some bits on a range in the tree. This may require splitting
* or inserting elements in the tree, so the gfp mask is used to
* indicate which allocations or sleeping are allowed.
*
* pass 'wake' == 1 to kick any sleepers, and 'delete' == 1 to remove
* the given range from the tree regardless of state (ie for truncate).
*
* the range [start, end] is inclusive.
*
* This takes the tree lock, and returns 0 on success and < 0 on error.
*/
int clear_extent_bit(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, int wake, int delete,
struct extent_state **cached_state,
gfp_t mask)
{
struct extent_state *state;
struct extent_state *cached;
struct extent_state *prealloc = NULL;
struct rb_node *node;
u64 last_end;
int err;
int clear = 0;
if (delete)
bits |= ~EXTENT_CTLBITS;
bits |= EXTENT_FIRST_DELALLOC;
if (bits & (EXTENT_IOBITS | EXTENT_BOUNDARY))
clear = 1;
again:
if (!prealloc && (mask & __GFP_WAIT)) {
prealloc = alloc_extent_state(mask);
if (!prealloc)
return -ENOMEM;
}
spin_lock(&tree->lock);
if (cached_state) {
cached = *cached_state;
if (clear) {
*cached_state = NULL;
cached_state = NULL;
}
if (cached && cached->tree && cached->start <= start &&
cached->end > start) {
if (clear)
atomic_dec(&cached->refs);
state = cached;
goto hit_next;
}
if (clear)
free_extent_state(cached);
}
/*
* this search will find the extents that end after
* our range starts
*/
node = tree_search(tree, start);
if (!node)
goto out;
state = rb_entry(node, struct extent_state, rb_node);
hit_next:
if (state->start > end)
goto out;
WARN_ON(state->end < start);
last_end = state->end;
/* the state doesn't have the wanted bits, go ahead */
if (!(state->state & bits)) {
state = next_state(state);
goto next;
}
/*
* | ---- desired range ---- |
* | state | or
* | ------------- state -------------- |
*
* We need to split the extent we found, and may flip
* bits on second half.
*
* If the extent we found extends past our range, we
* just split and search again. It'll get split again
* the next time though.
*
* If the extent we found is inside our range, we clear
* the desired bit on it.
*/
if (state->start < start) {
prealloc = alloc_extent_state_atomic(prealloc);
BUG_ON(!prealloc);
err = split_state(tree, state, prealloc, start);
if (err)
extent_io_tree_panic(tree, err);
prealloc = NULL;
if (err)
goto out;
if (state->end <= end) {
state = clear_state_bit(tree, state, &bits, wake);
goto next;
}
goto search_again;
}
/*
* | ---- desired range ---- |
* | state |
* We need to split the extent, and clear the bit
* on the first half
*/
if (state->start <= end && state->end > end) {
prealloc = alloc_extent_state_atomic(prealloc);
BUG_ON(!prealloc);
err = split_state(tree, state, prealloc, end + 1);
if (err)
extent_io_tree_panic(tree, err);
if (wake)
wake_up(&state->wq);
clear_state_bit(tree, prealloc, &bits, wake);
prealloc = NULL;
goto out;
}
state = clear_state_bit(tree, state, &bits, wake);
next:
if (last_end == (u64)-1)
goto out;
start = last_end + 1;
if (start <= end && state && !need_resched())
goto hit_next;
goto search_again;
out:
spin_unlock(&tree->lock);
if (prealloc)
free_extent_state(prealloc);
return 0;
search_again:
if (start > end)
goto out;
spin_unlock(&tree->lock);
if (mask & __GFP_WAIT)
cond_resched();
goto again;
}
static void wait_on_state(struct extent_io_tree *tree,
struct extent_state *state)
__releases(tree->lock)
__acquires(tree->lock)
{
DEFINE_WAIT(wait);
prepare_to_wait(&state->wq, &wait, TASK_UNINTERRUPTIBLE);
spin_unlock(&tree->lock);
schedule();
spin_lock(&tree->lock);
finish_wait(&state->wq, &wait);
}
/*
* waits for one or more bits to clear on a range in the state tree.
* The range [start, end] is inclusive.
* The tree lock is taken by this function
*/
static void wait_extent_bit(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits)
{
struct extent_state *state;
struct rb_node *node;
spin_lock(&tree->lock);
again:
while (1) {
/*
* this search will find all the extents that end after
* our range starts
*/
node = tree_search(tree, start);
if (!node)
break;
state = rb_entry(node, struct extent_state, rb_node);
if (state->start > end)
goto out;
if (state->state & bits) {
start = state->start;
atomic_inc(&state->refs);
wait_on_state(tree, state);
free_extent_state(state);
goto again;
}
start = state->end + 1;
if (start > end)
break;
cond_resched_lock(&tree->lock);
}
out:
spin_unlock(&tree->lock);
}
static void set_state_bits(struct extent_io_tree *tree,
struct extent_state *state,
unsigned long *bits)
{
unsigned long bits_to_set = *bits & ~EXTENT_CTLBITS;
set_state_cb(tree, state, bits);
if ((bits_to_set & EXTENT_DIRTY) && !(state->state & EXTENT_DIRTY)) {
u64 range = state->end - state->start + 1;
tree->dirty_bytes += range;
}
state->state |= bits_to_set;
}
static void cache_state(struct extent_state *state,
struct extent_state **cached_ptr)
{
if (cached_ptr && !(*cached_ptr)) {
if (state->state & (EXTENT_IOBITS | EXTENT_BOUNDARY)) {
*cached_ptr = state;
atomic_inc(&state->refs);
}
}
}
static void uncache_state(struct extent_state **cached_ptr)
{
if (cached_ptr && (*cached_ptr)) {
struct extent_state *state = *cached_ptr;
*cached_ptr = NULL;
free_extent_state(state);
}
}
/*
* set some bits on a range in the tree. This may require allocations or
* sleeping, so the gfp mask is used to indicate what is allowed.
*
* If any of the exclusive bits are set, this will fail with -EEXIST if some
* part of the range already has the desired bits set. The start of the
* existing range is returned in failed_start in this case.
*
* [start, end] is inclusive This takes the tree lock.
*/
static int __must_check
__set_extent_bit(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, unsigned long exclusive_bits,
u64 *failed_start, struct extent_state **cached_state,
gfp_t mask)
{
struct extent_state *state;
struct extent_state *prealloc = NULL;
struct rb_node *node;
int err = 0;
u64 last_start;
u64 last_end;
bits |= EXTENT_FIRST_DELALLOC;
again:
if (!prealloc && (mask & __GFP_WAIT)) {
prealloc = alloc_extent_state(mask);
BUG_ON(!prealloc);
}
spin_lock(&tree->lock);
if (cached_state && *cached_state) {
state = *cached_state;
if (state->start <= start && state->end > start &&
state->tree) {
node = &state->rb_node;
goto hit_next;
}
}
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, start);
if (!node) {
prealloc = alloc_extent_state_atomic(prealloc);
BUG_ON(!prealloc);
err = insert_state(tree, prealloc, start, end, &bits);
if (err)
extent_io_tree_panic(tree, err);
prealloc = NULL;
goto out;
}
state = rb_entry(node, struct extent_state, rb_node);
hit_next:
last_start = state->start;
last_end = state->end;
/*
* | ---- desired range ---- |
* | state |
*
* Just lock what we found and keep going
*/
if (state->start == start && state->end <= end) {
if (state->state & exclusive_bits) {
*failed_start = state->start;
err = -EEXIST;
goto out;
}
set_state_bits(tree, state, &bits);
cache_state(state, cached_state);
merge_state(tree, state);
if (last_end == (u64)-1)
goto out;
start = last_end + 1;
state = next_state(state);
if (start < end && state && state->start == start &&
!need_resched())
goto hit_next;
goto search_again;
}
/*
* | ---- desired range ---- |
* | state |
* or
* | ------------- state -------------- |
*
* We need to split the extent we found, and may flip bits on
* second half.
*
* If the extent we found extends past our
* range, we just split and search again. It'll get split
* again the next time though.
*
* If the extent we found is inside our range, we set the
* desired bit on it.
*/
if (state->start < start) {
if (state->state & exclusive_bits) {
*failed_start = start;
err = -EEXIST;
goto out;
}
prealloc = alloc_extent_state_atomic(prealloc);
BUG_ON(!prealloc);
err = split_state(tree, state, prealloc, start);
if (err)
extent_io_tree_panic(tree, err);
prealloc = NULL;
if (err)
goto out;
if (state->end <= end) {
set_state_bits(tree, state, &bits);
cache_state(state, cached_state);
merge_state(tree, state);
if (last_end == (u64)-1)
goto out;
start = last_end + 1;
state = next_state(state);
if (start < end && state && state->start == start &&
!need_resched())
goto hit_next;
}
goto search_again;
}
/*
* | ---- desired range ---- |
* | state | or | state |
*
* There's a hole, we need to insert something in it and
* ignore the extent we found.
*/
if (state->start > start) {
u64 this_end;
if (end < last_start)
this_end = end;
else
this_end = last_start - 1;
prealloc = alloc_extent_state_atomic(prealloc);
BUG_ON(!prealloc);
/*
* Avoid to free 'prealloc' if it can be merged with
* the later extent.
*/
err = insert_state(tree, prealloc, start, this_end,
&bits);
if (err)
extent_io_tree_panic(tree, err);
cache_state(prealloc, cached_state);
prealloc = NULL;
start = this_end + 1;
goto search_again;
}
/*
* | ---- desired range ---- |
* | state |
* We need to split the extent, and set the bit
* on the first half
*/
if (state->start <= end && state->end > end) {
if (state->state & exclusive_bits) {
*failed_start = start;
err = -EEXIST;
goto out;
}
prealloc = alloc_extent_state_atomic(prealloc);
BUG_ON(!prealloc);
err = split_state(tree, state, prealloc, end + 1);
if (err)
extent_io_tree_panic(tree, err);
set_state_bits(tree, prealloc, &bits);
cache_state(prealloc, cached_state);
merge_state(tree, prealloc);
prealloc = NULL;
goto out;
}
goto search_again;
out:
spin_unlock(&tree->lock);
if (prealloc)
free_extent_state(prealloc);
return err;
search_again:
if (start > end)
goto out;
spin_unlock(&tree->lock);
if (mask & __GFP_WAIT)
cond_resched();
goto again;
}
int set_extent_bit(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, u64 * failed_start,
struct extent_state **cached_state, gfp_t mask)
{
return __set_extent_bit(tree, start, end, bits, 0, failed_start,
cached_state, mask);
}
/**
* convert_extent_bit - convert all bits in a given range from one bit to
* another
* @tree: the io tree to search
* @start: the start offset in bytes
* @end: the end offset in bytes (inclusive)
* @bits: the bits to set in this range
* @clear_bits: the bits to clear in this range
* @cached_state: state that we're going to cache
* @mask: the allocation mask
*
* This will go through and set bits for the given range. If any states exist
* already in this range they are set with the given bit and cleared of the
* clear_bits. This is only meant to be used by things that are mergeable, ie
* converting from say DELALLOC to DIRTY. This is not meant to be used with
* boundary bits like LOCK.
*/
int convert_extent_bit(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, unsigned long clear_bits,
struct extent_state **cached_state, gfp_t mask)
{
struct extent_state *state;
struct extent_state *prealloc = NULL;
struct rb_node *node;
int err = 0;
u64 last_start;
u64 last_end;
again:
if (!prealloc && (mask & __GFP_WAIT)) {
prealloc = alloc_extent_state(mask);
if (!prealloc)
return -ENOMEM;
}
spin_lock(&tree->lock);
if (cached_state && *cached_state) {
state = *cached_state;
if (state->start <= start && state->end > start &&
state->tree) {
node = &state->rb_node;
goto hit_next;
}
}
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, start);
if (!node) {
prealloc = alloc_extent_state_atomic(prealloc);
if (!prealloc) {
err = -ENOMEM;
goto out;
}
err = insert_state(tree, prealloc, start, end, &bits);
prealloc = NULL;
if (err)
extent_io_tree_panic(tree, err);
goto out;
}
state = rb_entry(node, struct extent_state, rb_node);
hit_next:
last_start = state->start;
last_end = state->end;
/*
* | ---- desired range ---- |
* | state |
*
* Just lock what we found and keep going
*/
if (state->start == start && state->end <= end) {
set_state_bits(tree, state, &bits);
cache_state(state, cached_state);
state = clear_state_bit(tree, state, &clear_bits, 0);
if (last_end == (u64)-1)
goto out;
start = last_end + 1;
if (start < end && state && state->start == start &&
!need_resched())
goto hit_next;
goto search_again;
}
/*
* | ---- desired range ---- |
* | state |
* or
* | ------------- state -------------- |
*
* We need to split the extent we found, and may flip bits on
* second half.
*
* If the extent we found extends past our
* range, we just split and search again. It'll get split
* again the next time though.
*
* If the extent we found is inside our range, we set the
* desired bit on it.
*/
if (state->start < start) {
prealloc = alloc_extent_state_atomic(prealloc);
if (!prealloc) {
err = -ENOMEM;
goto out;
}
err = split_state(tree, state, prealloc, start);
if (err)
extent_io_tree_panic(tree, err);
prealloc = NULL;
if (err)
goto out;
if (state->end <= end) {
set_state_bits(tree, state, &bits);
cache_state(state, cached_state);
state = clear_state_bit(tree, state, &clear_bits, 0);
if (last_end == (u64)-1)
goto out;
start = last_end + 1;
if (start < end && state && state->start == start &&
!need_resched())
goto hit_next;
}
goto search_again;
}
/*
* | ---- desired range ---- |
* | state | or | state |
*
* There's a hole, we need to insert something in it and
* ignore the extent we found.
*/
if (state->start > start) {
u64 this_end;
if (end < last_start)
this_end = end;
else
this_end = last_start - 1;
prealloc = alloc_extent_state_atomic(prealloc);
if (!prealloc) {
err = -ENOMEM;
goto out;
}
/*
* Avoid to free 'prealloc' if it can be merged with
* the later extent.
*/
err = insert_state(tree, prealloc, start, this_end,
&bits);
if (err)
extent_io_tree_panic(tree, err);
cache_state(prealloc, cached_state);
prealloc = NULL;
start = this_end + 1;
goto search_again;
}
/*
* | ---- desired range ---- |
* | state |
* We need to split the extent, and set the bit
* on the first half
*/
if (state->start <= end && state->end > end) {
prealloc = alloc_extent_state_atomic(prealloc);
if (!prealloc) {
err = -ENOMEM;
goto out;
}
err = split_state(tree, state, prealloc, end + 1);
if (err)
extent_io_tree_panic(tree, err);
set_state_bits(tree, prealloc, &bits);
cache_state(prealloc, cached_state);
clear_state_bit(tree, prealloc, &clear_bits, 0);
prealloc = NULL;
goto out;
}
goto search_again;
out:
spin_unlock(&tree->lock);
if (prealloc)
free_extent_state(prealloc);
return err;
search_again:
if (start > end)
goto out;
spin_unlock(&tree->lock);
if (mask & __GFP_WAIT)
cond_resched();
goto again;
}
/* wrappers around set/clear extent bit */
int set_extent_dirty(struct extent_io_tree *tree, u64 start, u64 end,
gfp_t mask)
{
return set_extent_bit(tree, start, end, EXTENT_DIRTY, NULL,
NULL, mask);
}
int set_extent_bits(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, gfp_t mask)
{
return set_extent_bit(tree, start, end, bits, NULL,
NULL, mask);
}
int clear_extent_bits(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, gfp_t mask)
{
return clear_extent_bit(tree, start, end, bits, 0, 0, NULL, mask);
}
int set_extent_delalloc(struct extent_io_tree *tree, u64 start, u64 end,
struct extent_state **cached_state, gfp_t mask)
{
return set_extent_bit(tree, start, end,
EXTENT_DELALLOC | EXTENT_UPTODATE,
NULL, cached_state, mask);
}
int set_extent_defrag(struct extent_io_tree *tree, u64 start, u64 end,
struct extent_state **cached_state, gfp_t mask)
{
return set_extent_bit(tree, start, end,
EXTENT_DELALLOC | EXTENT_UPTODATE | EXTENT_DEFRAG,
NULL, cached_state, mask);
}
int clear_extent_dirty(struct extent_io_tree *tree, u64 start, u64 end,
gfp_t mask)
{
return clear_extent_bit(tree, start, end,
EXTENT_DIRTY | EXTENT_DELALLOC |
EXTENT_DO_ACCOUNTING, 0, 0, NULL, mask);
}
int set_extent_new(struct extent_io_tree *tree, u64 start, u64 end,
gfp_t mask)
{
return set_extent_bit(tree, start, end, EXTENT_NEW, NULL,
NULL, mask);
}
int set_extent_uptodate(struct extent_io_tree *tree, u64 start, u64 end,
struct extent_state **cached_state, gfp_t mask)
{
return set_extent_bit(tree, start, end, EXTENT_UPTODATE, NULL,
cached_state, mask);
}
int clear_extent_uptodate(struct extent_io_tree *tree, u64 start, u64 end,
struct extent_state **cached_state, gfp_t mask)
{
return clear_extent_bit(tree, start, end, EXTENT_UPTODATE, 0, 0,
cached_state, mask);
}
/*
* either insert or lock state struct between start and end use mask to tell
* us if waiting is desired.
*/
int lock_extent_bits(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, struct extent_state **cached_state)
{
int err;
u64 failed_start;
while (1) {
err = __set_extent_bit(tree, start, end, EXTENT_LOCKED | bits,
EXTENT_LOCKED, &failed_start,
cached_state, GFP_NOFS);
if (err == -EEXIST) {
wait_extent_bit(tree, failed_start, end, EXTENT_LOCKED);
start = failed_start;
} else
break;
WARN_ON(start > end);
}
return err;
}
int lock_extent(struct extent_io_tree *tree, u64 start, u64 end)
{
return lock_extent_bits(tree, start, end, 0, NULL);
}
int try_lock_extent(struct extent_io_tree *tree, u64 start, u64 end)
{
int err;
u64 failed_start;
err = __set_extent_bit(tree, start, end, EXTENT_LOCKED, EXTENT_LOCKED,
&failed_start, NULL, GFP_NOFS);
if (err == -EEXIST) {
if (failed_start > start)
clear_extent_bit(tree, start, failed_start - 1,
EXTENT_LOCKED, 1, 0, NULL, GFP_NOFS);
return 0;
}
return 1;
}
int unlock_extent_cached(struct extent_io_tree *tree, u64 start, u64 end,
struct extent_state **cached, gfp_t mask)
{
return clear_extent_bit(tree, start, end, EXTENT_LOCKED, 1, 0, cached,
mask);
}
int unlock_extent(struct extent_io_tree *tree, u64 start, u64 end)
{
return clear_extent_bit(tree, start, end, EXTENT_LOCKED, 1, 0, NULL,
GFP_NOFS);
}
int extent_range_clear_dirty_for_io(struct inode *inode, u64 start, u64 end)
{
unsigned long index = start >> PAGE_CACHE_SHIFT;
unsigned long end_index = end >> PAGE_CACHE_SHIFT;
struct page *page;
while (index <= end_index) {
page = find_get_page(inode->i_mapping, index);
BUG_ON(!page); /* Pages should be in the extent_io_tree */
clear_page_dirty_for_io(page);
page_cache_release(page);
index++;
}
return 0;
}
int extent_range_redirty_for_io(struct inode *inode, u64 start, u64 end)
{
unsigned long index = start >> PAGE_CACHE_SHIFT;
unsigned long end_index = end >> PAGE_CACHE_SHIFT;
struct page *page;
while (index <= end_index) {
page = find_get_page(inode->i_mapping, index);
BUG_ON(!page); /* Pages should be in the extent_io_tree */
account_page_redirty(page);
__set_page_dirty_nobuffers(page);
page_cache_release(page);
index++;
}
return 0;
}
/*
* helper function to set both pages and extents in the tree writeback
*/
static int set_range_writeback(struct extent_io_tree *tree, u64 start, u64 end)
{
unsigned long index = start >> PAGE_CACHE_SHIFT;
unsigned long end_index = end >> PAGE_CACHE_SHIFT;
struct page *page;
while (index <= end_index) {
page = find_get_page(tree->mapping, index);
BUG_ON(!page); /* Pages should be in the extent_io_tree */
set_page_writeback(page);
page_cache_release(page);
index++;
}
return 0;
}
/* find the first state struct with 'bits' set after 'start', and
* return it. tree->lock must be held. NULL will returned if
* nothing was found after 'start'
*/
static struct extent_state *
find_first_extent_bit_state(struct extent_io_tree *tree,
u64 start, unsigned long bits)
{
struct rb_node *node;
struct extent_state *state;
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, start);
if (!node)
goto out;
while (1) {
state = rb_entry(node, struct extent_state, rb_node);
if (state->end >= start && (state->state & bits))
return state;
node = rb_next(node);
if (!node)
break;
}
out:
return NULL;
}
/*
* find the first offset in the io tree with 'bits' set. zero is
* returned if we find something, and *start_ret and *end_ret are
* set to reflect the state struct that was found.
*
* If nothing was found, 1 is returned. If found something, return 0.
*/
int find_first_extent_bit(struct extent_io_tree *tree, u64 start,
u64 *start_ret, u64 *end_ret, unsigned long bits,
struct extent_state **cached_state)
{
struct extent_state *state;
struct rb_node *n;
int ret = 1;
spin_lock(&tree->lock);
if (cached_state && *cached_state) {
state = *cached_state;
if (state->end == start - 1 && state->tree) {
n = rb_next(&state->rb_node);
while (n) {
state = rb_entry(n, struct extent_state,
rb_node);
if (state->state & bits)
goto got_it;
n = rb_next(n);
}
free_extent_state(*cached_state);
*cached_state = NULL;
goto out;
}
free_extent_state(*cached_state);
*cached_state = NULL;
}
state = find_first_extent_bit_state(tree, start, bits);
got_it:
if (state) {
cache_state(state, cached_state);
*start_ret = state->start;
*end_ret = state->end;
ret = 0;
}
out:
spin_unlock(&tree->lock);
return ret;
}
/*
* find a contiguous range of bytes in the file marked as delalloc, not
* more than 'max_bytes'. start and end are used to return the range,
*
* 1 is returned if we find something, 0 if nothing was in the tree
*/
static noinline u64 find_delalloc_range(struct extent_io_tree *tree,
u64 *start, u64 *end, u64 max_bytes,
struct extent_state **cached_state)
{
struct rb_node *node;
struct extent_state *state;
u64 cur_start = *start;
u64 found = 0;
u64 total_bytes = 0;
spin_lock(&tree->lock);
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, cur_start);
if (!node) {
if (!found)
*end = (u64)-1;
goto out;
}
while (1) {
state = rb_entry(node, struct extent_state, rb_node);
if (found && (state->start != cur_start ||
(state->state & EXTENT_BOUNDARY))) {
goto out;
}
if (!(state->state & EXTENT_DELALLOC)) {
if (!found)
*end = state->end;
goto out;
}
if (!found) {
*start = state->start;
*cached_state = state;
atomic_inc(&state->refs);
}
found++;
*end = state->end;
cur_start = state->end + 1;
node = rb_next(node);
if (!node)
break;
total_bytes += state->end - state->start + 1;
if (total_bytes >= max_bytes)
break;
}
out:
spin_unlock(&tree->lock);
return found;
}
static noinline void __unlock_for_delalloc(struct inode *inode,
struct page *locked_page,
u64 start, u64 end)
{
int ret;
struct page *pages[16];
unsigned long index = start >> PAGE_CACHE_SHIFT;
unsigned long end_index = end >> PAGE_CACHE_SHIFT;
unsigned long nr_pages = end_index - index + 1;
int i;
if (index == locked_page->index && end_index == index)
return;
while (nr_pages > 0) {
ret = find_get_pages_contig(inode->i_mapping, index,
min_t(unsigned long, nr_pages,
ARRAY_SIZE(pages)), pages);
for (i = 0; i < ret; i++) {
if (pages[i] != locked_page)
unlock_page(pages[i]);
page_cache_release(pages[i]);
}
nr_pages -= ret;
index += ret;
cond_resched();
}
}
static noinline int lock_delalloc_pages(struct inode *inode,
struct page *locked_page,
u64 delalloc_start,
u64 delalloc_end)
{
unsigned long index = delalloc_start >> PAGE_CACHE_SHIFT;
unsigned long start_index = index;
unsigned long end_index = delalloc_end >> PAGE_CACHE_SHIFT;
unsigned long pages_locked = 0;
struct page *pages[16];
unsigned long nrpages;
int ret;
int i;
/* the caller is responsible for locking the start index */
if (index == locked_page->index && index == end_index)
return 0;
/* skip the page at the start index */
nrpages = end_index - index + 1;
while (nrpages > 0) {
ret = find_get_pages_contig(inode->i_mapping, index,
min_t(unsigned long,
nrpages, ARRAY_SIZE(pages)), pages);
if (ret == 0) {
ret = -EAGAIN;
goto done;
}
/* now we have an array of pages, lock them all */
for (i = 0; i < ret; i++) {
/*
* the caller is taking responsibility for
* locked_page
*/
if (pages[i] != locked_page) {
lock_page(pages[i]);
if (!PageDirty(pages[i]) ||
pages[i]->mapping != inode->i_mapping) {
ret = -EAGAIN;
unlock_page(pages[i]);
page_cache_release(pages[i]);
goto done;
}
}
page_cache_release(pages[i]);
pages_locked++;
}
nrpages -= ret;
index += ret;
cond_resched();
}
ret = 0;
done:
if (ret && pages_locked) {
__unlock_for_delalloc(inode, locked_page,
delalloc_start,
((u64)(start_index + pages_locked - 1)) <<
PAGE_CACHE_SHIFT);
}
return ret;
}
/*
* find a contiguous range of bytes in the file marked as delalloc, not
* more than 'max_bytes'. start and end are used to return the range,
*
* 1 is returned if we find something, 0 if nothing was in the tree
*/
static noinline u64 find_lock_delalloc_range(struct inode *inode,
struct extent_io_tree *tree,
struct page *locked_page,
u64 *start, u64 *end,
u64 max_bytes)
{
u64 delalloc_start;
u64 delalloc_end;
u64 found;
struct extent_state *cached_state = NULL;
int ret;
int loops = 0;
again:
/* step one, find a bunch of delalloc bytes starting at start */
delalloc_start = *start;
delalloc_end = 0;
found = find_delalloc_range(tree, &delalloc_start, &delalloc_end,
max_bytes, &cached_state);
if (!found || delalloc_end <= *start) {
*start = delalloc_start;
*end = delalloc_end;
free_extent_state(cached_state);
return found;
}
/*
* start comes from the offset of locked_page. We have to lock
* pages in order, so we can't process delalloc bytes before
* locked_page
*/
if (delalloc_start < *start)
delalloc_start = *start;
/*
* make sure to limit the number of pages we try to lock down
* if we're looping.
*/
if (delalloc_end + 1 - delalloc_start > max_bytes && loops)
delalloc_end = delalloc_start + PAGE_CACHE_SIZE - 1;
/* step two, lock all the pages after the page that has start */
ret = lock_delalloc_pages(inode, locked_page,
delalloc_start, delalloc_end);
if (ret == -EAGAIN) {
/* some of the pages are gone, lets avoid looping by
* shortening the size of the delalloc range we're searching
*/
free_extent_state(cached_state);
cached_state = NULL;
if (!loops) {
unsigned long offset = (*start) & (PAGE_CACHE_SIZE - 1);
max_bytes = PAGE_CACHE_SIZE - offset;
loops = 1;
goto again;
} else {
found = 0;
goto out_failed;
}
}
BUG_ON(ret); /* Only valid values are 0 and -EAGAIN */
/* step three, lock the state bits for the whole range */
lock_extent_bits(tree, delalloc_start, delalloc_end, 0, &cached_state);
/* then test to make sure it is all still delalloc */
ret = test_range_bit(tree, delalloc_start, delalloc_end,
EXTENT_DELALLOC, 1, cached_state);
if (!ret) {
unlock_extent_cached(tree, delalloc_start, delalloc_end,
&cached_state, GFP_NOFS);
__unlock_for_delalloc(inode, locked_page,
delalloc_start, delalloc_end);
cond_resched();
goto again;
}
free_extent_state(cached_state);
*start = delalloc_start;
*end = delalloc_end;
out_failed:
return found;
}
int extent_clear_unlock_delalloc(struct inode *inode,
struct extent_io_tree *tree,
u64 start, u64 end, struct page *locked_page,
unsigned long op)
{
int ret;
struct page *pages[16];
unsigned long index = start >> PAGE_CACHE_SHIFT;
unsigned long end_index = end >> PAGE_CACHE_SHIFT;
unsigned long nr_pages = end_index - index + 1;
int i;
unsigned long clear_bits = 0;
if (op & EXTENT_CLEAR_UNLOCK)
clear_bits |= EXTENT_LOCKED;
if (op & EXTENT_CLEAR_DIRTY)
clear_bits |= EXTENT_DIRTY;
if (op & EXTENT_CLEAR_DELALLOC)
clear_bits |= EXTENT_DELALLOC;
clear_extent_bit(tree, start, end, clear_bits, 1, 0, NULL, GFP_NOFS);
if (!(op & (EXTENT_CLEAR_UNLOCK_PAGE | EXTENT_CLEAR_DIRTY |
EXTENT_SET_WRITEBACK | EXTENT_END_WRITEBACK |
EXTENT_SET_PRIVATE2)))
return 0;
while (nr_pages > 0) {
ret = find_get_pages_contig(inode->i_mapping, index,
min_t(unsigned long,
nr_pages, ARRAY_SIZE(pages)), pages);
for (i = 0; i < ret; i++) {
if (op & EXTENT_SET_PRIVATE2)
SetPagePrivate2(pages[i]);
if (pages[i] == locked_page) {
page_cache_release(pages[i]);
continue;
}
if (op & EXTENT_CLEAR_DIRTY)
clear_page_dirty_for_io(pages[i]);
if (op & EXTENT_SET_WRITEBACK)
set_page_writeback(pages[i]);
if (op & EXTENT_END_WRITEBACK)
end_page_writeback(pages[i]);
if (op & EXTENT_CLEAR_UNLOCK_PAGE)
unlock_page(pages[i]);
page_cache_release(pages[i]);
}
nr_pages -= ret;
index += ret;
cond_resched();
}
return 0;
}
/*
* count the number of bytes in the tree that have a given bit(s)
* set. This can be fairly slow, except for EXTENT_DIRTY which is
* cached. The total number found is returned.
*/
u64 count_range_bits(struct extent_io_tree *tree,
u64 *start, u64 search_end, u64 max_bytes,
unsigned long bits, int contig)
{
struct rb_node *node;
struct extent_state *state;
u64 cur_start = *start;
u64 total_bytes = 0;
u64 last = 0;
int found = 0;
if (search_end <= cur_start) {
WARN_ON(1);
return 0;
}
spin_lock(&tree->lock);
if (cur_start == 0 && bits == EXTENT_DIRTY) {
total_bytes = tree->dirty_bytes;
goto out;
}
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, cur_start);
if (!node)
goto out;
while (1) {
state = rb_entry(node, struct extent_state, rb_node);
if (state->start > search_end)
break;
if (contig && found && state->start > last + 1)
break;
if (state->end >= cur_start && (state->state & bits) == bits) {
total_bytes += min(search_end, state->end) + 1 -
max(cur_start, state->start);
if (total_bytes >= max_bytes)
break;
if (!found) {
*start = max(cur_start, state->start);
found = 1;
}
last = state->end;
} else if (contig && found) {
break;
}
node = rb_next(node);
if (!node)
break;
}
out:
spin_unlock(&tree->lock);
return total_bytes;
}
/*
* set the private field for a given byte offset in the tree. If there isn't
* an extent_state there already, this does nothing.
*/
int set_state_private(struct extent_io_tree *tree, u64 start, u64 private)
{
struct rb_node *node;
struct extent_state *state;
int ret = 0;
spin_lock(&tree->lock);
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, start);
if (!node) {
ret = -ENOENT;
goto out;
}
state = rb_entry(node, struct extent_state, rb_node);
if (state->start != start) {
ret = -ENOENT;
goto out;
}
state->private = private;
out:
spin_unlock(&tree->lock);
return ret;
}
void extent_cache_csums_dio(struct extent_io_tree *tree, u64 start, u32 csums[],
int count)
{
struct rb_node *node;
struct extent_state *state;
spin_lock(&tree->lock);
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, start);
BUG_ON(!node);
state = rb_entry(node, struct extent_state, rb_node);
BUG_ON(state->start != start);
while (count) {
state->private = *csums++;
count--;
state = next_state(state);
}
spin_unlock(&tree->lock);
}
static inline u64 __btrfs_get_bio_offset(struct bio *bio, int bio_index)
{
struct bio_vec *bvec = bio->bi_io_vec + bio_index;
return page_offset(bvec->bv_page) + bvec->bv_offset;
}
void extent_cache_csums(struct extent_io_tree *tree, struct bio *bio, int bio_index,
u32 csums[], int count)
{
struct rb_node *node;
struct extent_state *state = NULL;
u64 start;
spin_lock(&tree->lock);
do {
start = __btrfs_get_bio_offset(bio, bio_index);
if (state == NULL || state->start != start) {
node = tree_search(tree, start);
BUG_ON(!node);
state = rb_entry(node, struct extent_state, rb_node);
BUG_ON(state->start != start);
}
state->private = *csums++;
count--;
bio_index++;
state = next_state(state);
} while (count);
spin_unlock(&tree->lock);
}
int get_state_private(struct extent_io_tree *tree, u64 start, u64 *private)
{
struct rb_node *node;
struct extent_state *state;
int ret = 0;
spin_lock(&tree->lock);
/*
* this search will find all the extents that end after
* our range starts.
*/
node = tree_search(tree, start);
if (!node) {
ret = -ENOENT;
goto out;
}
state = rb_entry(node, struct extent_state, rb_node);
if (state->start != start) {
ret = -ENOENT;
goto out;
}
*private = state->private;
out:
spin_unlock(&tree->lock);
return ret;
}
/*
* searches a range in the state tree for a given mask.
* If 'filled' == 1, this returns 1 only if every extent in the tree
* has the bits set. Otherwise, 1 is returned if any bit in the
* range is found set.
*/
int test_range_bit(struct extent_io_tree *tree, u64 start, u64 end,
unsigned long bits, int filled, struct extent_state *cached)
{
struct extent_state *state = NULL;
struct rb_node *node;
int bitset = 0;
spin_lock(&tree->lock);
if (cached && cached->tree && cached->start <= start &&
cached->end > start)
node = &cached->rb_node;
else
node = tree_search(tree, start);
while (node && start <= end) {
state = rb_entry(node, struct extent_state, rb_node);
if (filled && state->start > start) {
bitset = 0;
break;
}
if (state->start > end)
break;
if (state->state & bits) {
bitset = 1;
if (!filled)
break;
} else if (filled) {
bitset = 0;
break;
}
if (state->end == (u64)-1)
break;
start = state->end + 1;
if (start > end)
break;
node = rb_next(node);
if (!node) {
if (filled)
bitset = 0;
break;
}
}
spin_unlock(&tree->lock);
return bitset;
}
/*
* helper function to set a given page up to date if all the
* extents in the tree for that page are up to date
*/
static void check_page_uptodate(struct extent_io_tree *tree, struct page *page)
{
u64 start = page_offset(page);
u64 end = start + PAGE_CACHE_SIZE - 1;
if (test_range_bit(tree, start, end, EXTENT_UPTODATE, 1, NULL))
SetPageUptodate(page);
}
/*
* When IO fails, either with EIO or csum verification fails, we
* try other mirrors that might have a good copy of the data. This
* io_failure_record is used to record state as we go through all the
* mirrors. If another mirror has good data, the page is set up to date
* and things continue. If a good mirror can't be found, the original
* bio end_io callback is called to indicate things have failed.
*/
struct io_failure_record {
struct page *page;
u64 start;
u64 len;
u64 logical;
unsigned long bio_flags;
int this_mirror;
int failed_mirror;
int in_validation;
};
static int free_io_failure(struct inode *inode, struct io_failure_record *rec,
int did_repair)
{
int ret;
int err = 0;
struct extent_io_tree *failure_tree = &BTRFS_I(inode)->io_failure_tree;
set_state_private(failure_tree, rec->start, 0);
ret = clear_extent_bits(failure_tree, rec->start,
rec->start + rec->len - 1,
EXTENT_LOCKED | EXTENT_DIRTY, GFP_NOFS);
if (ret)
err = ret;
ret = clear_extent_bits(&BTRFS_I(inode)->io_tree, rec->start,
rec->start + rec->len - 1,
EXTENT_DAMAGED, GFP_NOFS);
if (ret && !err)
err = ret;
kfree(rec);
return err;
}
static void repair_io_failure_callback(struct bio *bio, int err)
{
complete(bio->bi_private);
}
/*
* this bypasses the standard btrfs submit functions deliberately, as
* the standard behavior is to write all copies in a raid setup. here we only
* want to write the one bad copy. so we do the mapping for ourselves and issue
* submit_bio directly.
* to avoid any synchronization issues, wait for the data after writing, which
* actually prevents the read that triggered the error from finishing.
* currently, there can be no more than two copies of every data bit. thus,
* exactly one rewrite is required.
*/
int repair_io_failure(struct btrfs_fs_info *fs_info, u64 start,
u64 length, u64 logical, struct page *page,
int mirror_num)
{
struct bio *bio;
struct btrfs_device *dev;
DECLARE_COMPLETION_ONSTACK(compl);
u64 map_length = 0;
u64 sector;
struct btrfs_bio *bbio = NULL;
struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
int ret;
BUG_ON(!mirror_num);
/* we can't repair anything in raid56 yet */
if (btrfs_is_parity_mirror(map_tree, logical, length, mirror_num))
return 0;
bio = btrfs_io_bio_alloc(GFP_NOFS, 1);
if (!bio)
return -EIO;
bio->bi_private = &compl;
bio->bi_end_io = repair_io_failure_callback;
bio->bi_size = 0;
map_length = length;
ret = btrfs_map_block(fs_info, WRITE, logical,
&map_length, &bbio, mirror_num);
if (ret) {
bio_put(bio);
return -EIO;
}
BUG_ON(mirror_num != bbio->mirror_num);
sector = bbio->stripes[mirror_num-1].physical >> 9;
bio->bi_sector = sector;
dev = bbio->stripes[mirror_num-1].dev;
kfree(bbio);
if (!dev || !dev->bdev || !dev->writeable) {
bio_put(bio);
return -EIO;
}
bio->bi_bdev = dev->bdev;
bio_add_page(bio, page, length, start - page_offset(page));
btrfsic_submit_bio(WRITE_SYNC, bio);
wait_for_completion(&compl);
if (!test_bit(BIO_UPTODATE, &bio->bi_flags)) {
/* try to remap that extent elsewhere? */
bio_put(bio);
btrfs_dev_stat_inc_and_print(dev, BTRFS_DEV_STAT_WRITE_ERRS);
return -EIO;
}
printk_ratelimited_in_rcu(KERN_INFO "btrfs read error corrected: ino %lu off %llu "
"(dev %s sector %llu)\n", page->mapping->host->i_ino,
start, rcu_str_deref(dev->name), sector);
bio_put(bio);
return 0;
}
int repair_eb_io_failure(struct btrfs_root *root, struct extent_buffer *eb,
int mirror_num)
{
u64 start = eb->start;
unsigned long i, num_pages = num_extent_pages(eb->start, eb->len);
int ret = 0;
for (i = 0; i < num_pages; i++) {
struct page *p = extent_buffer_page(eb, i);
ret = repair_io_failure(root->fs_info, start, PAGE_CACHE_SIZE,
start, p, mirror_num);
if (ret)
break;
start += PAGE_CACHE_SIZE;
}
return ret;
}
/*
* each time an IO finishes, we do a fast check in the IO failure tree
* to see if we need to process or clean up an io_failure_record
*/
static int clean_io_failure(u64 start, struct page *page)
{
u64 private;
u64 private_failure;
struct io_failure_record *failrec;
struct btrfs_fs_info *fs_info;
struct extent_state *state;
int num_copies;
int did_repair = 0;
int ret;
struct inode *inode = page->mapping->host;
private = 0;
ret = count_range_bits(&BTRFS_I(inode)->io_failure_tree, &private,
(u64)-1, 1, EXTENT_DIRTY, 0);
if (!ret)
return 0;
ret = get_state_private(&BTRFS_I(inode)->io_failure_tree, start,
&private_failure);
if (ret)
return 0;
failrec = (struct io_failure_record *)(unsigned long) private_failure;
BUG_ON(!failrec->this_mirror);
if (failrec->in_validation) {
/* there was no real error, just free the record */
pr_debug("clean_io_failure: freeing dummy error at %llu\n",
failrec->start);
did_repair = 1;
goto out;
}
spin_lock(&BTRFS_I(inode)->io_tree.lock);
state = find_first_extent_bit_state(&BTRFS_I(inode)->io_tree,
failrec->start,
EXTENT_LOCKED);
spin_unlock(&BTRFS_I(inode)->io_tree.lock);
if (state && state->start == failrec->start) {
fs_info = BTRFS_I(inode)->root->fs_info;
num_copies = btrfs_num_copies(fs_info, failrec->logical,
failrec->len);
if (num_copies > 1) {
ret = repair_io_failure(fs_info, start, failrec->len,
failrec->logical, page,
failrec->failed_mirror);
did_repair = !ret;
}
ret = 0;
}
out:
if (!ret)
ret = free_io_failure(inode, failrec, did_repair);
return ret;
}
/*
* this is a generic handler for readpage errors (default
* readpage_io_failed_hook). if other copies exist, read those and write back
* good data to the failed position. does not investigate in remapping the
* failed extent elsewhere, hoping the device will be smart enough to do this as
* needed
*/
static int bio_readpage_error(struct bio *failed_bio, struct page *page,
u64 start, u64 end, int failed_mirror,
struct extent_state *state)
{
struct io_failure_record *failrec = NULL;
u64 private;
struct extent_map *em;
struct inode *inode = page->mapping->host;
struct extent_io_tree *failure_tree = &BTRFS_I(inode)->io_failure_tree;
struct extent_io_tree *tree = &BTRFS_I(inode)->io_tree;
struct extent_map_tree *em_tree = &BTRFS_I(inode)->extent_tree;
struct bio *bio;
int num_copies;
int ret;
int read_mode;
u64 logical;
BUG_ON(failed_bio->bi_rw & REQ_WRITE);
ret = get_state_private(failure_tree, start, &private);
if (ret) {
failrec = kzalloc(sizeof(*failrec), GFP_NOFS);
if (!failrec)
return -ENOMEM;
failrec->start = start;
failrec->len = end - start + 1;
failrec->this_mirror = 0;
failrec->bio_flags = 0;
failrec->in_validation = 0;
read_lock(&em_tree->lock);
em = lookup_extent_mapping(em_tree, start, failrec->len);
if (!em) {
read_unlock(&em_tree->lock);
kfree(failrec);
return -EIO;
}
if (em->start > start || em->start + em->len < start) {
free_extent_map(em);
em = NULL;
}
read_unlock(&em_tree->lock);
if (!em) {
kfree(failrec);
return -EIO;
}
logical = start - em->start;
logical = em->block_start + logical;
if (test_bit(EXTENT_FLAG_COMPRESSED, &em->flags)) {
logical = em->block_start;
failrec->bio_flags = EXTENT_BIO_COMPRESSED;
extent_set_compress_type(&failrec->bio_flags,
em->compress_type);
}
pr_debug("bio_readpage_error: (new) logical=%llu, start=%llu, "
"len=%llu\n", logical, start, failrec->len);
failrec->logical = logical;
free_extent_map(em);
/* set the bits in the private failure tree */
ret = set_extent_bits(failure_tree, start, end,
EXTENT_LOCKED | EXTENT_DIRTY, GFP_NOFS);
if (ret >= 0)
ret = set_state_private(failure_tree, start,
(u64)(unsigned long)failrec);
/* set the bits in the inode's tree */
if (ret >= 0)
ret = set_extent_bits(tree, start, end, EXTENT_DAMAGED,
GFP_NOFS);
if (ret < 0) {
kfree(failrec);
return ret;
}
} else {
failrec = (struct io_failure_record *)(unsigned long)private;
pr_debug("bio_readpage_error: (found) logical=%llu, "
"start=%llu, len=%llu, validation=%d\n",
failrec->logical, failrec->start, failrec->len,
failrec->in_validation);
/*
* when data can be on disk more than twice, add to failrec here
* (e.g. with a list for failed_mirror) to make
* clean_io_failure() clean all those errors at once.
*/
}
num_copies = btrfs_num_copies(BTRFS_I(inode)->root->fs_info,
failrec->logical, failrec->len);
if (num_copies == 1) {
/*
* we only have a single copy of the data, so don't bother with
* all the retry and error correction code that follows. no
* matter what the error is, it is very likely to persist.
*/
pr_debug("bio_readpage_error: cannot repair, num_copies == 1. "
"state=%p, num_copies=%d, next_mirror %d, "
"failed_mirror %d\n", state, num_copies,
failrec->this_mirror, failed_mirror);
free_io_failure(inode, failrec, 0);
return -EIO;
}
if (!state) {
spin_lock(&tree->lock);
state = find_first_extent_bit_state(tree, failrec->start,
EXTENT_LOCKED);
if (state && state->start != failrec->start)
state = NULL;
spin_unlock(&tree->lock);
}
/*
* there are two premises:
* a) deliver good data to the caller
* b) correct the bad sectors on disk
*/
if (failed_bio->bi_vcnt > 1) {
/*
* to fulfill b), we need to know the exact failing sectors, as
* we don't want to rewrite any more than the failed ones. thus,
* we need separate read requests for the failed bio
*
* if the following BUG_ON triggers, our validation request got
* merged. we need separate requests for our algorithm to work.
*/
BUG_ON(failrec->in_validation);
failrec->in_validation = 1;
failrec->this_mirror = failed_mirror;
read_mode = READ_SYNC | REQ_FAILFAST_DEV;
} else {
/*
* we're ready to fulfill a) and b) alongside. get a good copy
* of the failed sector and if we succeed, we have setup
* everything for repair_io_failure to do the rest for us.
*/
if (failrec->in_validation) {
BUG_ON(failrec->this_mirror != failed_mirror);
failrec->in_validation = 0;
failrec->this_mirror = 0;
}
failrec->failed_mirror = failed_mirror;
failrec->this_mirror++;
if (failrec->this_mirror == failed_mirror)
failrec->this_mirror++;
read_mode = READ_SYNC;
}
if (!state || failrec->this_mirror > num_copies) {
pr_debug("bio_readpage_error: (fail) state=%p, num_copies=%d, "
"next_mirror %d, failed_mirror %d\n", state,
num_copies, failrec->this_mirror, failed_mirror);
free_io_failure(inode, failrec, 0);
return -EIO;
}
bio = btrfs_io_bio_alloc(GFP_NOFS, 1);
if (!bio) {
free_io_failure(inode, failrec, 0);
return -EIO;
}
bio->bi_private = state;
bio->bi_end_io = failed_bio->bi_end_io;
bio->bi_sector = failrec->logical >> 9;
bio->bi_bdev = BTRFS_I(inode)->root->fs_info->fs_devices->latest_bdev;
bio->bi_size = 0;
bio_add_page(bio, page, failrec->len, start - page_offset(page));
pr_debug("bio_readpage_error: submitting new read[%#x] to "
"this_mirror=%d, num_copies=%d, in_validation=%d\n", read_mode,
failrec->this_mirror, num_copies, failrec->in_validation);
ret = tree->ops->submit_bio_hook(inode, read_mode, bio,
failrec->this_mirror,
failrec->bio_flags, 0);
return ret;
}
/* lots and lots of room for performance fixes in the end_bio funcs */
int end_extent_writepage(struct page *page, int err, u64 start, u64 end)
{
int uptodate = (err == 0);
struct extent_io_tree *tree;
int ret = 0;
tree = &BTRFS_I(page->mapping->host)->io_tree;
if (tree->ops && tree->ops->writepage_end_io_hook) {
ret = tree->ops->writepage_end_io_hook(page, start,
end, NULL, uptodate);
if (ret)
uptodate = 0;
}
if (!uptodate) {
ClearPageUptodate(page);
SetPageError(page);
ret = ret < 0 ? ret : -EIO;
mapping_set_error(page->mapping, ret);
}
return 0;
}
/*
* after a writepage IO is done, we need to:
* clear the uptodate bits on error
* clear the writeback bits in the extent tree for this IO
* end_page_writeback if the page has no more pending IO
*
* Scheduling is not allowed, so the extent state tree is expected
* to have one and only one object corresponding to this IO.
*/
static void end_bio_extent_writepage(struct bio *bio, int err)
{
struct bio_vec *bvec = bio->bi_io_vec + bio->bi_vcnt - 1;
struct extent_io_tree *tree;
u64 start;
u64 end;
do {
struct page *page = bvec->bv_page;
tree = &BTRFS_I(page->mapping->host)->io_tree;
/* We always issue full-page reads, but if some block
* in a page fails to read, blk_update_request() will
* advance bv_offset and adjust bv_len to compensate.
* Print a warning for nonzero offsets, and an error
* if they don't add up to a full page. */
if (bvec->bv_offset || bvec->bv_len != PAGE_CACHE_SIZE)
printk("%s page write in btrfs with offset %u and length %u\n",
bvec->bv_offset + bvec->bv_len != PAGE_CACHE_SIZE
? KERN_ERR "partial" : KERN_INFO "incomplete",
bvec->bv_offset, bvec->bv_len);
start = page_offset(page);
end = start + bvec->bv_offset + bvec->bv_len - 1;
if (--bvec >= bio->bi_io_vec)
prefetchw(&bvec->bv_page->flags);
if (end_extent_writepage(page, err, start, end))
continue;
end_page_writeback(page);
} while (bvec >= bio->bi_io_vec);
bio_put(bio);
}
/*
* after a readpage IO is done, we need to:
* clear the uptodate bits on error
* set the uptodate bits if things worked
* set the page up to date if all extents in the tree are uptodate
* clear the lock bit in the extent tree
* unlock the page if there are no other extents locked for it
*
* Scheduling is not allowed, so the extent state tree is expected
* to have one and only one object corresponding to this IO.
*/
static void end_bio_extent_readpage(struct bio *bio, int err)
{
int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
struct bio_vec *bvec_end = bio->bi_io_vec + bio->bi_vcnt - 1;
struct bio_vec *bvec = bio->bi_io_vec;
struct extent_io_tree *tree;
u64 start;
u64 end;
int mirror;
int ret;
if (err)
uptodate = 0;
do {
struct page *page = bvec->bv_page;
struct extent_state *cached = NULL;
struct extent_state *state;
struct btrfs_io_bio *io_bio = btrfs_io_bio(bio);
pr_debug("end_bio_extent_readpage: bi_sector=%llu, err=%d, "
"mirror=%lu\n", (u64)bio->bi_sector, err,
io_bio->mirror_num);
tree = &BTRFS_I(page->mapping->host)->io_tree;
/* We always issue full-page reads, but if some block
* in a page fails to read, blk_update_request() will
* advance bv_offset and adjust bv_len to compensate.
* Print a warning for nonzero offsets, and an error
* if they don't add up to a full page. */
if (bvec->bv_offset || bvec->bv_len != PAGE_CACHE_SIZE)
printk("%s page read in btrfs with offset %u and length %u\n",
bvec->bv_offset + bvec->bv_len != PAGE_CACHE_SIZE
? KERN_ERR "partial" : KERN_INFO "incomplete",
bvec->bv_offset, bvec->bv_len);
start = page_offset(page);
end = start + bvec->bv_offset + bvec->bv_len - 1;
if (++bvec <= bvec_end)
prefetchw(&bvec->bv_page->flags);
spin_lock(&tree->lock);
state = find_first_extent_bit_state(tree, start, EXTENT_LOCKED);
if (state && state->start == start) {
/*
* take a reference on the state, unlock will drop
* the ref
*/
cache_state(state, &cached);
}
spin_unlock(&tree->lock);
mirror = io_bio->mirror_num;
if (uptodate && tree->ops && tree->ops->readpage_end_io_hook) {
ret = tree->ops->readpage_end_io_hook(page, start, end,
state, mirror);
if (ret)
uptodate = 0;
else
clean_io_failure(start, page);
}
if (!uptodate && tree->ops && tree->ops->readpage_io_failed_hook) {
ret = tree->ops->readpage_io_failed_hook(page, mirror);
if (!ret && !err &&
test_bit(BIO_UPTODATE, &bio->bi_flags))
uptodate = 1;
} else if (!uptodate) {
/*
* The generic bio_readpage_error handles errors the
* following way: If possible, new read requests are
* created and submitted and will end up in
* end_bio_extent_readpage as well (if we're lucky, not
* in the !uptodate case). In that case it returns 0 and
* we just go on with the next page in our bio. If it
* can't handle the error it will return -EIO and we
* remain responsible for that page.
*/
ret = bio_readpage_error(bio, page, start, end, mirror, NULL);
if (ret == 0) {
uptodate =
test_bit(BIO_UPTODATE, &bio->bi_flags);
if (err)
uptodate = 0;
uncache_state(&cached);
continue;
}
}
if (uptodate && tree->track_uptodate) {
set_extent_uptodate(tree, start, end, &cached,
GFP_ATOMIC);
}
unlock_extent_cached(tree, start, end, &cached, GFP_ATOMIC);
if (uptodate) {
SetPageUptodate(page);
} else {
ClearPageUptodate(page);
SetPageError(page);
}
unlock_page(page);
} while (bvec <= bvec_end);
bio_put(bio);
}
/*
* this allocates from the btrfs_bioset. We're returning a bio right now
* but you can call btrfs_io_bio for the appropriate container_of magic
*/
struct bio *
btrfs_bio_alloc(struct block_device *bdev, u64 first_sector, int nr_vecs,
gfp_t gfp_flags)
{
struct bio *bio;
bio = bio_alloc_bioset(gfp_flags, nr_vecs, btrfs_bioset);
if (bio == NULL && (current->flags & PF_MEMALLOC)) {
while (!bio && (nr_vecs /= 2)) {
bio = bio_alloc_bioset(gfp_flags,
nr_vecs, btrfs_bioset);
}
}
if (bio) {
bio->bi_size = 0;
bio->bi_bdev = bdev;
bio->bi_sector = first_sector;
}
return bio;
}
struct bio *btrfs_bio_clone(struct bio *bio, gfp_t gfp_mask)
{
return bio_clone_bioset(bio, gfp_mask, btrfs_bioset);
}
/* this also allocates from the btrfs_bioset */
struct bio *btrfs_io_bio_alloc(gfp_t gfp_mask, unsigned int nr_iovecs)
{
return bio_alloc_bioset(gfp_mask, nr_iovecs, btrfs_bioset);
}
static int __must_check submit_one_bio(int rw, struct bio *bio,
int mirror_num, unsigned long bio_flags)
{
int ret = 0;
struct bio_vec *bvec = bio->bi_io_vec + bio->bi_vcnt - 1;
struct page *page = bvec->bv_page;
struct extent_io_tree *tree = bio->bi_private;
u64 start;
start = page_offset(page) + bvec->bv_offset;
bio->bi_private = NULL;
bio_get(bio);
if (tree->ops && tree->ops->submit_bio_hook)
ret = tree->ops->submit_bio_hook(page->mapping->host, rw, bio,
mirror_num, bio_flags, start);
else
btrfsic_submit_bio(rw, bio);
if (bio_flagged(bio, BIO_EOPNOTSUPP))
ret = -EOPNOTSUPP;
bio_put(bio);
return ret;
}
static int merge_bio(int rw, struct extent_io_tree *tree, struct page *page,
unsigned long offset, size_t size, struct bio *bio,
unsigned long bio_flags)
{
int ret = 0;
if (tree->ops && tree->ops->merge_bio_hook)
ret = tree->ops->merge_bio_hook(rw, page, offset, size, bio,
bio_flags);
BUG_ON(ret < 0);
return ret;
}
static int submit_extent_page(int rw, struct extent_io_tree *tree,
struct page *page, sector_t sector,
size_t size, unsigned long offset,
struct block_device *bdev,
struct bio **bio_ret,
unsigned long max_pages,
bio_end_io_t end_io_func,
int mirror_num,
unsigned long prev_bio_flags,
unsigned long bio_flags)
{
int ret = 0;
struct bio *bio;
int nr;
int contig = 0;
int this_compressed = bio_flags & EXTENT_BIO_COMPRESSED;
int old_compressed = prev_bio_flags & EXTENT_BIO_COMPRESSED;
size_t page_size = min_t(size_t, size, PAGE_CACHE_SIZE);
if (bio_ret && *bio_ret) {
bio = *bio_ret;
if (old_compressed)
contig = bio->bi_sector == sector;
else
contig = bio_end_sector(bio) == sector;
if (prev_bio_flags != bio_flags || !contig ||
merge_bio(rw, tree, page, offset, page_size, bio, bio_flags) ||
bio_add_page(bio, page, page_size, offset) < page_size) {
ret = submit_one_bio(rw, bio, mirror_num,
prev_bio_flags);
if (ret < 0)
return ret;
bio = NULL;
} else {
return 0;
}
}
if (this_compressed)
nr = BIO_MAX_PAGES;
else
nr = bio_get_nr_vecs(bdev);
bio = btrfs_bio_alloc(bdev, sector, nr, GFP_NOFS | __GFP_HIGH);
if (!bio)
return -ENOMEM;
bio_add_page(bio, page, page_size, offset);
bio->bi_end_io = end_io_func;
bio->bi_private = tree;
if (bio_ret)
*bio_ret = bio;
else
ret = submit_one_bio(rw, bio, mirror_num, bio_flags);
return ret;
}
static void attach_extent_buffer_page(struct extent_buffer *eb,
struct page *page)
{
if (!PagePrivate(page)) {
SetPagePrivate(page);
page_cache_get(page);
set_page_private(page, (unsigned long)eb);
} else {
WARN_ON(page->private != (unsigned long)eb);
}
}
void set_page_extent_mapped(struct page *page)
{
if (!PagePrivate(page)) {
SetPagePrivate(page);
page_cache_get(page);
set_page_private(page, EXTENT_PAGE_PRIVATE);
}
}
/*
* basic readpage implementation. Locked extent state structs are inserted
* into the tree that are removed when the IO is done (by the end_io
* handlers)
* XXX JDM: This needs looking at to ensure proper page locking
*/
static int __extent_read_full_page(struct extent_io_tree *tree,
struct page *page,
get_extent_t *get_extent,
struct bio **bio, int mirror_num,
unsigned long *bio_flags, int rw)
{
struct inode *inode = page->mapping->host;
u64 start = page_offset(page);
u64 page_end = start + PAGE_CACHE_SIZE - 1;
u64 end;
u64 cur = start;
u64 extent_offset;
u64 last_byte = i_size_read(inode);
u64 block_start;
u64 cur_end;
sector_t sector;
struct extent_map *em;
struct block_device *bdev;
struct btrfs_ordered_extent *ordered;
int ret;
int nr = 0;
size_t pg_offset = 0;
size_t iosize;
size_t disk_io_size;
size_t blocksize = inode->i_sb->s_blocksize;
unsigned long this_bio_flag = 0;
set_page_extent_mapped(page);
if (!PageUptodate(page)) {
if (cleancache_get_page(page) == 0) {
BUG_ON(blocksize != PAGE_SIZE);
goto out;
}
}
end = page_end;
while (1) {
lock_extent(tree, start, end);
ordered = btrfs_lookup_ordered_extent(inode, start);
if (!ordered)
break;
unlock_extent(tree, start, end);
btrfs_start_ordered_extent(inode, ordered, 1);
btrfs_put_ordered_extent(ordered);
}
if (page->index == last_byte >> PAGE_CACHE_SHIFT) {
char *userpage;
size_t zero_offset = last_byte & (PAGE_CACHE_SIZE - 1);
if (zero_offset) {
iosize = PAGE_CACHE_SIZE - zero_offset;
userpage = kmap_atomic(page);
memset(userpage + zero_offset, 0, iosize);
flush_dcache_page(page);
kunmap_atomic(userpage);
}
}
while (cur <= end) {
unsigned long pnr = (last_byte >> PAGE_CACHE_SHIFT) + 1;
if (cur >= last_byte) {
char *userpage;
struct extent_state *cached = NULL;
iosize = PAGE_CACHE_SIZE - pg_offset;
userpage = kmap_atomic(page);
memset(userpage + pg_offset, 0, iosize);
flush_dcache_page(page);
kunmap_atomic(userpage);
set_extent_uptodate(tree, cur, cur + iosize - 1,
&cached, GFP_NOFS);
unlock_extent_cached(tree, cur, cur + iosize - 1,
&cached, GFP_NOFS);
break;
}
em = get_extent(inode, page, pg_offset, cur,
end - cur + 1, 0);
if (IS_ERR_OR_NULL(em)) {
SetPageError(page);
unlock_extent(tree, cur, end);
break;
}
extent_offset = cur - em->start;
BUG_ON(extent_map_end(em) <= cur);
BUG_ON(end < cur);
if (test_bit(EXTENT_FLAG_COMPRESSED, &em->flags)) {
this_bio_flag = EXTENT_BIO_COMPRESSED;
extent_set_compress_type(&this_bio_flag,
em->compress_type);
}
iosize = min(extent_map_end(em) - cur, end - cur + 1);
cur_end = min(extent_map_end(em) - 1, end);
iosize = ALIGN(iosize, blocksize);
if (this_bio_flag & EXTENT_BIO_COMPRESSED) {
disk_io_size = em->block_len;
sector = em->block_start >> 9;
} else {
sector = (em->block_start + extent_offset) >> 9;
disk_io_size = iosize;
}
bdev = em->bdev;
block_start = em->block_start;
if (test_bit(EXTENT_FLAG_PREALLOC, &em->flags))
block_start = EXTENT_MAP_HOLE;
free_extent_map(em);
em = NULL;
/* we've found a hole, just zero and go on */
if (block_start == EXTENT_MAP_HOLE) {
char *userpage;
struct extent_state *cached = NULL;
userpage = kmap_atomic(page);
memset(userpage + pg_offset, 0, iosize);
flush_dcache_page(page);
kunmap_atomic(userpage);
set_extent_uptodate(tree, cur, cur + iosize - 1,
&cached, GFP_NOFS);
unlock_extent_cached(tree, cur, cur + iosize - 1,
&cached, GFP_NOFS);
cur = cur + iosize;
pg_offset += iosize;
continue;
}
/* the get_extent function already copied into the page */
if (test_range_bit(tree, cur, cur_end,
EXTENT_UPTODATE, 1, NULL)) {
check_page_uptodate(tree, page);
unlock_extent(tree, cur, cur + iosize - 1);
cur = cur + iosize;
pg_offset += iosize;
continue;
}
/* we have an inline extent but it didn't get marked up
* to date. Error out
*/
if (block_start == EXTENT_MAP_INLINE) {
SetPageError(page);
unlock_extent(tree, cur, cur + iosize - 1);
cur = cur + iosize;
pg_offset += iosize;
continue;
}
pnr -= page->index;
ret = submit_extent_page(rw, tree, page,
sector, disk_io_size, pg_offset,
bdev, bio, pnr,
end_bio_extent_readpage, mirror_num,
*bio_flags,
this_bio_flag);
if (!ret) {
nr++;
*bio_flags = this_bio_flag;
} else {
SetPageError(page);
unlock_extent(tree, cur, cur + iosize - 1);
}
cur = cur + iosize;
pg_offset += iosize;
}
out:
if (!nr) {
if (!PageError(page))
SetPageUptodate(page);
unlock_page(page);
}
return 0;
}
int extent_read_full_page(struct extent_io_tree *tree, struct page *page,
get_extent_t *get_extent, int mirror_num)
{
struct bio *bio = NULL;
unsigned long bio_flags = 0;
int ret;
ret = __extent_read_full_page(tree, page, get_extent, &bio, mirror_num,
&bio_flags, READ);
if (bio)
ret = submit_one_bio(READ, bio, mirror_num, bio_flags);
return ret;
}
static noinline void update_nr_written(struct page *page,
struct writeback_control *wbc,
unsigned long nr_written)
{
wbc->nr_to_write -= nr_written;
if (wbc->range_cyclic || (wbc->nr_to_write > 0 &&
wbc->range_start == 0 && wbc->range_end == LLONG_MAX))
page->mapping->writeback_index = page->index + nr_written;
}
/*
* the writepage semantics are similar to regular writepage. extent
* records are inserted to lock ranges in the tree, and as dirty areas
* are found, they are marked writeback. Then the lock bits are removed
* and the end_io handler clears the writeback ranges
*/
static int __extent_writepage(struct page *page, struct writeback_control *wbc,
void *data)
{
struct inode *inode = page->mapping->host;
struct extent_page_data *epd = data;
struct extent_io_tree *tree = epd->tree;
u64 start = page_offset(page);
u64 delalloc_start;
u64 page_end = start + PAGE_CACHE_SIZE - 1;
u64 end;
u64 cur = start;
u64 extent_offset;
u64 last_byte = i_size_read(inode);
u64 block_start;
u64 iosize;
sector_t sector;
struct extent_state *cached_state = NULL;
struct extent_map *em;
struct block_device *bdev;
int ret;
int nr = 0;
size_t pg_offset = 0;
size_t blocksize;
loff_t i_size = i_size_read(inode);
unsigned long end_index = i_size >> PAGE_CACHE_SHIFT;
u64 nr_delalloc;
u64 delalloc_end;
int page_started;
int compressed;
int write_flags;
unsigned long nr_written = 0;
bool fill_delalloc = true;
if (wbc->sync_mode == WB_SYNC_ALL)
write_flags = WRITE_SYNC;
else
write_flags = WRITE;
trace___extent_writepage(page, inode, wbc);
WARN_ON(!PageLocked(page));
ClearPageError(page);
pg_offset = i_size & (PAGE_CACHE_SIZE - 1);
if (page->index > end_index ||
(page->index == end_index && !pg_offset)) {
page->mapping->a_ops->invalidatepage(page, 0);
unlock_page(page);
return 0;
}
if (page->index == end_index) {
char *userpage;
userpage = kmap_atomic(page);
memset(userpage + pg_offset, 0,
PAGE_CACHE_SIZE - pg_offset);
kunmap_atomic(userpage);
flush_dcache_page(page);
}
pg_offset = 0;
set_page_extent_mapped(page);
if (!tree->ops || !tree->ops->fill_delalloc)
fill_delalloc = false;
delalloc_start = start;
delalloc_end = 0;
page_started = 0;
if (!epd->extent_locked && fill_delalloc) {
u64 delalloc_to_write = 0;
/*
* make sure the wbc mapping index is at least updated
* to this page.
*/
update_nr_written(page, wbc, 0);
while (delalloc_end < page_end) {
nr_delalloc = find_lock_delalloc_range(inode, tree,
page,
&delalloc_start,
&delalloc_end,
128 * 1024 * 1024);
if (nr_delalloc == 0) {
delalloc_start = delalloc_end + 1;
continue;
}
ret = tree->ops->fill_delalloc(inode, page,
delalloc_start,
delalloc_end,
&page_started,
&nr_written);
/* File system has been set read-only */
if (ret) {
SetPageError(page);
goto done;
}
/*
* delalloc_end is already one less than the total
* length, so we don't subtract one from
* PAGE_CACHE_SIZE
*/
delalloc_to_write += (delalloc_end - delalloc_start +
PAGE_CACHE_SIZE) >>
PAGE_CACHE_SHIFT;
delalloc_start = delalloc_end + 1;
}
if (wbc->nr_to_write < delalloc_to_write) {
int thresh = 8192;
if (delalloc_to_write < thresh * 2)
thresh = delalloc_to_write;
wbc->nr_to_write = min_t(u64, delalloc_to_write,
thresh);
}
/* did the fill delalloc function already unlock and start
* the IO?
*/
if (page_started) {
ret = 0;
/*
* we've unlocked the page, so we can't update
* the mapping's writeback index, just update
* nr_to_write.
*/
wbc->nr_to_write -= nr_written;
goto done_unlocked;
}
}
if (tree->ops && tree->ops->writepage_start_hook) {
ret = tree->ops->writepage_start_hook(page, start,
page_end);
if (ret) {
/* Fixup worker will requeue */
if (ret == -EBUSY)
wbc->pages_skipped++;
else
redirty_page_for_writepage(wbc, page);
update_nr_written(page, wbc, nr_written);
unlock_page(page);
ret = 0;
goto done_unlocked;
}
}
/*
* we don't want to touch the inode after unlocking the page,
* so we update the mapping writeback index now
*/
update_nr_written(page, wbc, nr_written + 1);
end = page_end;
if (last_byte <= start) {
if (tree->ops && tree->ops->writepage_end_io_hook)
tree->ops->writepage_end_io_hook(page, start,
page_end, NULL, 1);
goto done;
}
blocksize = inode->i_sb->s_blocksize;
while (cur <= end) {
if (cur >= last_byte) {
if (tree->ops && tree->ops->writepage_end_io_hook)
tree->ops->writepage_end_io_hook(page, cur,
page_end, NULL, 1);
break;
}
em = epd->get_extent(inode, page, pg_offset, cur,
end - cur + 1, 1);
if (IS_ERR_OR_NULL(em)) {
SetPageError(page);
break;
}
extent_offset = cur - em->start;
BUG_ON(extent_map_end(em) <= cur);
BUG_ON(end < cur);
iosize = min(extent_map_end(em) - cur, end - cur + 1);
iosize = ALIGN(iosize, blocksize);
sector = (em->block_start + extent_offset) >> 9;
bdev = em->bdev;
block_start = em->block_start;
compressed = test_bit(EXTENT_FLAG_COMPRESSED, &em->flags);
free_extent_map(em);
em = NULL;
/*
* compressed and inline extents are written through other
* paths in the FS
*/
if (compressed || block_start == EXTENT_MAP_HOLE ||
block_start == EXTENT_MAP_INLINE) {
/*
* end_io notification does not happen here for
* compressed extents
*/
if (!compressed && tree->ops &&
tree->ops->writepage_end_io_hook)
tree->ops->writepage_end_io_hook(page, cur,
cur + iosize - 1,
NULL, 1);
else if (compressed) {
/* we don't want to end_page_writeback on
* a compressed extent. this happens
* elsewhere
*/
nr++;
}
cur += iosize;
pg_offset += iosize;
continue;
}
/* leave this out until we have a page_mkwrite call */
if (0 && !test_range_bit(tree, cur, cur + iosize - 1,
EXTENT_DIRTY, 0, NULL)) {
cur = cur + iosize;
pg_offset += iosize;
continue;
}
if (tree->ops && tree->ops->writepage_io_hook) {
ret = tree->ops->writepage_io_hook(page, cur,
cur + iosize - 1);
} else {
ret = 0;
}
if (ret) {
SetPageError(page);
} else {
unsigned long max_nr = end_index + 1;
set_range_writeback(tree, cur, cur + iosize - 1);
if (!PageWriteback(page)) {
printk(KERN_ERR "btrfs warning page %lu not "
"writeback, cur %llu end %llu\n",
page->index, (unsigned long long)cur,
(unsigned long long)end);
}
ret = submit_extent_page(write_flags, tree, page,
sector, iosize, pg_offset,
bdev, &epd->bio, max_nr,
end_bio_extent_writepage,
0, 0, 0);
if (ret)
SetPageError(page);
}
cur = cur + iosize;
pg_offset += iosize;
nr++;
}
done:
if (nr == 0) {
/* make sure the mapping tag for page dirty gets cleared */
set_page_writeback(page);
end_page_writeback(page);
}
unlock_page(page);
done_unlocked:
/* drop our reference on any cached states */
free_extent_state(cached_state);
return 0;
}
static int eb_wait(void *word)
{
io_schedule();
return 0;
}
void wait_on_extent_buffer_writeback(struct extent_buffer *eb)
{
wait_on_bit(&eb->bflags, EXTENT_BUFFER_WRITEBACK, eb_wait,
TASK_UNINTERRUPTIBLE);
}
static int lock_extent_buffer_for_io(struct extent_buffer *eb,
struct btrfs_fs_info *fs_info,
struct extent_page_data *epd)
{
unsigned long i, num_pages;
int flush = 0;
int ret = 0;
if (!btrfs_try_tree_write_lock(eb)) {
flush = 1;
flush_write_bio(epd);
btrfs_tree_lock(eb);
}
if (test_bit(EXTENT_BUFFER_WRITEBACK, &eb->bflags)) {
btrfs_tree_unlock(eb);
if (!epd->sync_io)
return 0;
if (!flush) {
flush_write_bio(epd);
flush = 1;
}
while (1) {
wait_on_extent_buffer_writeback(eb);
btrfs_tree_lock(eb);
if (!test_bit(EXTENT_BUFFER_WRITEBACK, &eb->bflags))
break;
btrfs_tree_unlock(eb);
}
}
/*
* We need to do this to prevent races in people who check if the eb is
* under IO since we can end up having no IO bits set for a short period
* of time.
*/
spin_lock(&eb->refs_lock);
if (test_and_clear_bit(EXTENT_BUFFER_DIRTY, &eb->bflags)) {
set_bit(EXTENT_BUFFER_WRITEBACK, &eb->bflags);
spin_unlock(&eb->refs_lock);
btrfs_set_header_flag(eb, BTRFS_HEADER_FLAG_WRITTEN);
__percpu_counter_add(&fs_info->dirty_metadata_bytes,
-eb->len,
fs_info->dirty_metadata_batch);
ret = 1;
} else {
spin_unlock(&eb->refs_lock);
}
btrfs_tree_unlock(eb);
if (!ret)
return ret;
num_pages = num_extent_pages(eb->start, eb->len);
for (i = 0; i < num_pages; i++) {
struct page *p = extent_buffer_page(eb, i);
if (!trylock_page(p)) {
if (!flush) {
flush_write_bio(epd);
flush = 1;
}
lock_page(p);
}
}
return ret;
}
static void end_extent_buffer_writeback(struct extent_buffer *eb)
{
clear_bit(EXTENT_BUFFER_WRITEBACK, &eb->bflags);
smp_mb__after_atomic();
wake_up_bit(&eb->bflags, EXTENT_BUFFER_WRITEBACK);
}
static void end_bio_extent_buffer_writepage(struct bio *bio, int err)
{
int uptodate = err == 0;
struct bio_vec *bvec = bio->bi_io_vec + bio->bi_vcnt - 1;
struct extent_buffer *eb;
int done;
do {
struct page *page = bvec->bv_page;
bvec--;
eb = (struct extent_buffer *)page->private;
BUG_ON(!eb);
done = atomic_dec_and_test(&eb->io_pages);
if (!uptodate || test_bit(EXTENT_BUFFER_IOERR, &eb->bflags)) {
set_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
ClearPageUptodate(page);
SetPageError(page);
}
end_page_writeback(page);
if (!done)
continue;
end_extent_buffer_writeback(eb);
} while (bvec >= bio->bi_io_vec);
bio_put(bio);
}
static int write_one_eb(struct extent_buffer *eb,
struct btrfs_fs_info *fs_info,
struct writeback_control *wbc,
struct extent_page_data *epd)
{
struct block_device *bdev = fs_info->fs_devices->latest_bdev;
u64 offset = eb->start;
unsigned long i, num_pages;
unsigned long bio_flags = 0;
int rw = (epd->sync_io ? WRITE_SYNC : WRITE) | REQ_META;
int ret = 0;
clear_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
num_pages = num_extent_pages(eb->start, eb->len);
atomic_set(&eb->io_pages, num_pages);
if (btrfs_header_owner(eb) == BTRFS_TREE_LOG_OBJECTID)
bio_flags = EXTENT_BIO_TREE_LOG;
for (i = 0; i < num_pages; i++) {
struct page *p = extent_buffer_page(eb, i);
clear_page_dirty_for_io(p);
set_page_writeback(p);
ret = submit_extent_page(rw, eb->tree, p, offset >> 9,
PAGE_CACHE_SIZE, 0, bdev, &epd->bio,
-1, end_bio_extent_buffer_writepage,
0, epd->bio_flags, bio_flags);
epd->bio_flags = bio_flags;
if (ret) {
set_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
SetPageError(p);
if (atomic_sub_and_test(num_pages - i, &eb->io_pages))
end_extent_buffer_writeback(eb);
ret = -EIO;
break;
}
offset += PAGE_CACHE_SIZE;
update_nr_written(p, wbc, 1);
unlock_page(p);
}
if (unlikely(ret)) {
for (; i < num_pages; i++) {
struct page *p = extent_buffer_page(eb, i);
unlock_page(p);
}
}
return ret;
}
int btree_write_cache_pages(struct address_space *mapping,
struct writeback_control *wbc)
{
struct extent_io_tree *tree = &BTRFS_I(mapping->host)->io_tree;
struct btrfs_fs_info *fs_info = BTRFS_I(mapping->host)->root->fs_info;
struct extent_buffer *eb, *prev_eb = NULL;
struct extent_page_data epd = {
.bio = NULL,
.tree = tree,
.extent_locked = 0,
.sync_io = wbc->sync_mode == WB_SYNC_ALL,
.bio_flags = 0,
};
int ret = 0;
int done = 0;
int nr_to_write_done = 0;
struct pagevec pvec;
int nr_pages;
pgoff_t index;
pgoff_t end; /* Inclusive */
int scanned = 0;
int tag;
pagevec_init(&pvec, 0);
if (wbc->range_cyclic) {
index = mapping->writeback_index; /* Start from prev offset */
end = -1;
} else {
index = wbc->range_start >> PAGE_CACHE_SHIFT;
end = wbc->range_end >> PAGE_CACHE_SHIFT;
scanned = 1;
}
if (wbc->sync_mode == WB_SYNC_ALL)
tag = PAGECACHE_TAG_TOWRITE;
else
tag = PAGECACHE_TAG_DIRTY;
retry:
if (wbc->sync_mode == WB_SYNC_ALL)
tag_pages_for_writeback(mapping, index, end);
while (!done && !nr_to_write_done && (index <= end) &&
(nr_pages = pagevec_lookup_tag(&pvec, mapping, &index, tag,
min(end - index, (pgoff_t)PAGEVEC_SIZE-1) + 1))) {
unsigned i;
scanned = 1;
for (i = 0; i < nr_pages; i++) {
struct page *page = pvec.pages[i];
if (!PagePrivate(page))
continue;
if (!wbc->range_cyclic && page->index > end) {
done = 1;
break;
}
spin_lock(&mapping->private_lock);
if (!PagePrivate(page)) {
spin_unlock(&mapping->private_lock);
continue;
}
eb = (struct extent_buffer *)page->private;
/*
* Shouldn't happen and normally this would be a BUG_ON
* but no sense in crashing the users box for something
* we can survive anyway.
*/
if (!eb) {
spin_unlock(&mapping->private_lock);
WARN_ON(1);
continue;
}
if (eb == prev_eb) {
spin_unlock(&mapping->private_lock);
continue;
}
ret = atomic_inc_not_zero(&eb->refs);
spin_unlock(&mapping->private_lock);
if (!ret)
continue;
prev_eb = eb;
ret = lock_extent_buffer_for_io(eb, fs_info, &epd);
if (!ret) {
free_extent_buffer(eb);
continue;
}
ret = write_one_eb(eb, fs_info, wbc, &epd);
if (ret) {
done = 1;
free_extent_buffer(eb);
break;
}
free_extent_buffer(eb);
/*
* the filesystem may choose to bump up nr_to_write.
* We have to make sure to honor the new nr_to_write
* at any time
*/
nr_to_write_done = wbc->nr_to_write <= 0;
}
pagevec_release(&pvec);
cond_resched();
}
if (!scanned && !done) {
/*
* We hit the last page and there is more work to be done: wrap
* back to the start of the file
*/
scanned = 1;
index = 0;
goto retry;
}
flush_write_bio(&epd);
return ret;
}
/**
* write_cache_pages - walk the list of dirty pages of the given address space and write all of them.
* @mapping: address space structure to write
* @wbc: subtract the number of written pages from *@wbc->nr_to_write
* @writepage: function called for each page
* @data: data passed to writepage function
*
* If a page is already under I/O, write_cache_pages() skips it, even
* if it's dirty. This is desirable behaviour for memory-cleaning writeback,
* but it is INCORRECT for data-integrity system calls such as fsync(). fsync()
* and msync() need to guarantee that all the data which was dirty at the time
* the call was made get new I/O started against them. If wbc->sync_mode is
* WB_SYNC_ALL then we were called for data integrity and we must wait for
* existing IO to complete.
*/
static int extent_write_cache_pages(struct extent_io_tree *tree,
struct address_space *mapping,
struct writeback_control *wbc,
writepage_t writepage, void *data,
void (*flush_fn)(void *))
{
struct inode *inode = mapping->host;
int ret = 0;
int done = 0;
int nr_to_write_done = 0;
struct pagevec pvec;
int nr_pages;
pgoff_t index;
pgoff_t end; /* Inclusive */
int scanned = 0;
int tag;
/*
* We have to hold onto the inode so that ordered extents can do their
* work when the IO finishes. The alternative to this is failing to add
* an ordered extent if the igrab() fails there and that is a huge pain
* to deal with, so instead just hold onto the inode throughout the
* writepages operation. If it fails here we are freeing up the inode
* anyway and we'd rather not waste our time writing out stuff that is
* going to be truncated anyway.
*/
if (!igrab(inode))
return 0;
pagevec_init(&pvec, 0);
if (wbc->range_cyclic) {
index = mapping->writeback_index; /* Start from prev offset */
end = -1;
} else {
index = wbc->range_start >> PAGE_CACHE_SHIFT;
end = wbc->range_end >> PAGE_CACHE_SHIFT;
scanned = 1;
}
if (wbc->sync_mode == WB_SYNC_ALL)
tag = PAGECACHE_TAG_TOWRITE;
else
tag = PAGECACHE_TAG_DIRTY;
retry:
if (wbc->sync_mode == WB_SYNC_ALL)
tag_pages_for_writeback(mapping, index, end);
while (!done && !nr_to_write_done && (index <= end) &&
(nr_pages = pagevec_lookup_tag(&pvec, mapping, &index, tag,
min(end - index, (pgoff_t)PAGEVEC_SIZE-1) + 1))) {
unsigned i;
scanned = 1;
for (i = 0; i < nr_pages; i++) {
struct page *page = pvec.pages[i];
/*
* At this point we hold neither mapping->tree_lock nor
* lock on the page itself: the page may be truncated or
* invalidated (changing page->mapping to NULL), or even
* swizzled back from swapper_space to tmpfs file
* mapping
*/
if (!trylock_page(page)) {
flush_fn(data);
lock_page(page);
}
if (unlikely(page->mapping != mapping)) {
unlock_page(page);
continue;
}
if (!wbc->range_cyclic && page->index > end) {
done = 1;
unlock_page(page);
continue;
}
if (wbc->sync_mode != WB_SYNC_NONE) {
if (PageWriteback(page))
flush_fn(data);
wait_on_page_writeback(page);
}
if (PageWriteback(page) ||
!clear_page_dirty_for_io(page)) {
unlock_page(page);
continue;
}
ret = (*writepage)(page, wbc, data);
if (unlikely(ret == AOP_WRITEPAGE_ACTIVATE)) {
unlock_page(page);
ret = 0;
}
if (ret)
done = 1;
/*
* the filesystem may choose to bump up nr_to_write.
* We have to make sure to honor the new nr_to_write
* at any time
*/
nr_to_write_done = wbc->nr_to_write <= 0;
}
pagevec_release(&pvec);
cond_resched();
}
if (!scanned && !done) {
/*
* We hit the last page and there is more work to be done: wrap
* back to the start of the file
*/
scanned = 1;
index = 0;
goto retry;
}
btrfs_add_delayed_iput(inode);
return ret;
}
static void flush_epd_write_bio(struct extent_page_data *epd)
{
if (epd->bio) {
int rw = WRITE;
int ret;
if (epd->sync_io)
rw = WRITE_SYNC;
ret = submit_one_bio(rw, epd->bio, 0, epd->bio_flags);
BUG_ON(ret < 0); /* -ENOMEM */
epd->bio = NULL;
}
}
static noinline void flush_write_bio(void *data)
{
struct extent_page_data *epd = data;
flush_epd_write_bio(epd);
}
int extent_write_full_page(struct extent_io_tree *tree, struct page *page,
get_extent_t *get_extent,
struct writeback_control *wbc)
{
int ret;
struct extent_page_data epd = {
.bio = NULL,
.tree = tree,
.get_extent = get_extent,
.extent_locked = 0,
.sync_io = wbc->sync_mode == WB_SYNC_ALL,
.bio_flags = 0,
};
ret = __extent_writepage(page, wbc, &epd);
flush_epd_write_bio(&epd);
return ret;
}
int extent_write_locked_range(struct extent_io_tree *tree, struct inode *inode,
u64 start, u64 end, get_extent_t *get_extent,
int mode)
{
int ret = 0;
struct address_space *mapping = inode->i_mapping;
struct page *page;
unsigned long nr_pages = (end - start + PAGE_CACHE_SIZE) >>
PAGE_CACHE_SHIFT;
struct extent_page_data epd = {
.bio = NULL,
.tree = tree,
.get_extent = get_extent,
.extent_locked = 1,
.sync_io = mode == WB_SYNC_ALL,
.bio_flags = 0,
};
struct writeback_control wbc_writepages = {
.sync_mode = mode,
.nr_to_write = nr_pages * 2,
.range_start = start,
.range_end = end + 1,
};
while (start <= end) {
page = find_get_page(mapping, start >> PAGE_CACHE_SHIFT);
if (clear_page_dirty_for_io(page))
ret = __extent_writepage(page, &wbc_writepages, &epd);
else {
if (tree->ops && tree->ops->writepage_end_io_hook)
tree->ops->writepage_end_io_hook(page, start,
start + PAGE_CACHE_SIZE - 1,
NULL, 1);
unlock_page(page);
}
page_cache_release(page);
start += PAGE_CACHE_SIZE;
}
flush_epd_write_bio(&epd);
return ret;
}
int extent_writepages(struct extent_io_tree *tree,
struct address_space *mapping,
get_extent_t *get_extent,
struct writeback_control *wbc)
{
int ret = 0;
struct extent_page_data epd = {
.bio = NULL,
.tree = tree,
.get_extent = get_extent,
.extent_locked = 0,
.sync_io = wbc->sync_mode == WB_SYNC_ALL,
.bio_flags = 0,
};
ret = extent_write_cache_pages(tree, mapping, wbc,
__extent_writepage, &epd,
flush_write_bio);
flush_epd_write_bio(&epd);
return ret;
}
int extent_readpages(struct extent_io_tree *tree,
struct address_space *mapping,
struct list_head *pages, unsigned nr_pages,
get_extent_t get_extent)
{
struct bio *bio = NULL;
unsigned page_idx;
unsigned long bio_flags = 0;
struct page *pagepool[16];
struct page *page;
int i = 0;
int nr = 0;
for (page_idx = 0; page_idx < nr_pages; page_idx++) {
page = list_entry(pages->prev, struct page, lru);
prefetchw(&page->flags);
list_del(&page->lru);
if (add_to_page_cache_lru(page, mapping,
page->index, GFP_NOFS)) {
page_cache_release(page);
continue;
}
pagepool[nr++] = page;
if (nr < ARRAY_SIZE(pagepool))
continue;
for (i = 0; i < nr; i++) {
__extent_read_full_page(tree, pagepool[i], get_extent,
&bio, 0, &bio_flags, READ);
page_cache_release(pagepool[i]);
}
nr = 0;
}
for (i = 0; i < nr; i++) {
__extent_read_full_page(tree, pagepool[i], get_extent,
&bio, 0, &bio_flags, READ);
page_cache_release(pagepool[i]);
}
BUG_ON(!list_empty(pages));
if (bio)
return submit_one_bio(READ, bio, 0, bio_flags);
return 0;
}
/*
* basic invalidatepage code, this waits on any locked or writeback
* ranges corresponding to the page, and then deletes any extent state
* records from the tree
*/
int extent_invalidatepage(struct extent_io_tree *tree,
struct page *page, unsigned long offset)
{
struct extent_state *cached_state = NULL;
u64 start = page_offset(page);
u64 end = start + PAGE_CACHE_SIZE - 1;
size_t blocksize = page->mapping->host->i_sb->s_blocksize;
start += ALIGN(offset, blocksize);
if (start > end)
return 0;
lock_extent_bits(tree, start, end, 0, &cached_state);
wait_on_page_writeback(page);
clear_extent_bit(tree, start, end,
EXTENT_LOCKED | EXTENT_DIRTY | EXTENT_DELALLOC |
EXTENT_DO_ACCOUNTING,
1, 1, &cached_state, GFP_NOFS);
return 0;
}
/*
* a helper for releasepage, this tests for areas of the page that
* are locked or under IO and drops the related state bits if it is safe
* to drop the page.
*/
static int try_release_extent_state(struct extent_map_tree *map,
struct extent_io_tree *tree,
struct page *page, gfp_t mask)
{
u64 start = page_offset(page);
u64 end = start + PAGE_CACHE_SIZE - 1;
int ret = 1;
if (test_range_bit(tree, start, end,
EXTENT_IOBITS, 0, NULL))
ret = 0;
else {
if ((mask & GFP_NOFS) == GFP_NOFS)
mask = GFP_NOFS;
/*
* at this point we can safely clear everything except the
* locked bit and the nodatasum bit
*/
ret = clear_extent_bit(tree, start, end,
~(EXTENT_LOCKED | EXTENT_NODATASUM),
0, 0, NULL, mask);
/* if clear_extent_bit failed for enomem reasons,
* we can't allow the release to continue.
*/
if (ret < 0)
ret = 0;
else
ret = 1;
}
return ret;
}
/*
* a helper for releasepage. As long as there are no locked extents
* in the range corresponding to the page, both state records and extent
* map records are removed
*/
int try_release_extent_mapping(struct extent_map_tree *map,
struct extent_io_tree *tree, struct page *page,
gfp_t mask)
{
struct extent_map *em;
u64 start = page_offset(page);
u64 end = start + PAGE_CACHE_SIZE - 1;
if ((mask & __GFP_WAIT) &&
page->mapping->host->i_size > 16 * 1024 * 1024) {
u64 len;
while (start <= end) {
len = end - start + 1;
write_lock(&map->lock);
em = lookup_extent_mapping(map, start, len);
if (!em) {
write_unlock(&map->lock);
break;
}
if (test_bit(EXTENT_FLAG_PINNED, &em->flags) ||
em->start != start) {
write_unlock(&map->lock);
free_extent_map(em);
break;
}
if (!test_range_bit(tree, em->start,
extent_map_end(em) - 1,
EXTENT_LOCKED | EXTENT_WRITEBACK,
0, NULL)) {
remove_extent_mapping(map, em);
/* once for the rb tree */
free_extent_map(em);
}
start = extent_map_end(em);
write_unlock(&map->lock);
/* once for us */
free_extent_map(em);
}
}
return try_release_extent_state(map, tree, page, mask);
}
/*
* helper function for fiemap, which doesn't want to see any holes.
* This maps until we find something past 'last'
*/
static struct extent_map *get_extent_skip_holes(struct inode *inode,
u64 offset,
u64 last,
get_extent_t *get_extent)
{
u64 sectorsize = BTRFS_I(inode)->root->sectorsize;
struct extent_map *em;
u64 len;
if (offset >= last)
return NULL;
while(1) {
len = last - offset;
if (len == 0)
break;
len = ALIGN(len, sectorsize);
em = get_extent(inode, NULL, 0, offset, len, 0);
if (IS_ERR_OR_NULL(em))
return em;
/* if this isn't a hole return it */
if (!test_bit(EXTENT_FLAG_VACANCY, &em->flags) &&
em->block_start != EXTENT_MAP_HOLE) {
return em;
}
/* this is a hole, advance to the next extent */
offset = extent_map_end(em);
free_extent_map(em);
if (offset >= last)
break;
}
return NULL;
}
int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
__u64 start, __u64 len, get_extent_t *get_extent)
{
int ret = 0;
u64 off = start;
u64 max = start + len;
u32 flags = 0;
u32 found_type;
u64 last;
u64 last_for_get_extent = 0;
u64 disko = 0;
u64 isize = i_size_read(inode);
struct btrfs_key found_key;
struct extent_map *em = NULL;
struct extent_state *cached_state = NULL;
struct btrfs_path *path;
struct btrfs_file_extent_item *item;
int end = 0;
u64 em_start = 0;
u64 em_len = 0;
u64 em_end = 0;
unsigned long emflags;
if (len == 0)
return -EINVAL;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
path->leave_spinning = 1;
start = ALIGN(start, BTRFS_I(inode)->root->sectorsize);
len = ALIGN(len, BTRFS_I(inode)->root->sectorsize);
/*
* lookup the last file extent. We're not using i_size here
* because there might be preallocation past i_size
*/
ret = btrfs_lookup_file_extent(NULL, BTRFS_I(inode)->root,
path, btrfs_ino(inode), -1, 0);
if (ret < 0) {
btrfs_free_path(path);
return ret;
}
WARN_ON(!ret);
path->slots[0]--;
item = btrfs_item_ptr(path->nodes[0], path->slots[0],
struct btrfs_file_extent_item);
btrfs_item_key_to_cpu(path->nodes[0], &found_key, path->slots[0]);
found_type = btrfs_key_type(&found_key);
/* No extents, but there might be delalloc bits */
if (found_key.objectid != btrfs_ino(inode) ||
found_type != BTRFS_EXTENT_DATA_KEY) {
/* have to trust i_size as the end */
last = (u64)-1;
last_for_get_extent = isize;
} else {
/*
* remember the start of the last extent. There are a
* bunch of different factors that go into the length of the
* extent, so its much less complex to remember where it started
*/
last = found_key.offset;
last_for_get_extent = last + 1;
}
btrfs_free_path(path);
/*
* we might have some extents allocated but more delalloc past those
* extents. so, we trust isize unless the start of the last extent is
* beyond isize
*/
if (last < isize) {
last = (u64)-1;
last_for_get_extent = isize;
}
lock_extent_bits(&BTRFS_I(inode)->io_tree, start, start + len - 1, 0,
&cached_state);
em = get_extent_skip_holes(inode, start, last_for_get_extent,
get_extent);
if (!em)
goto out;
if (IS_ERR(em)) {
ret = PTR_ERR(em);
goto out;
}
while (!end) {
u64 offset_in_extent;
/* break if the extent we found is outside the range */
if (em->start >= max || extent_map_end(em) < off)
break;
/*
* get_extent may return an extent that starts before our
* requested range. We have to make sure the ranges
* we return to fiemap always move forward and don't
* overlap, so adjust the offsets here
*/
em_start = max(em->start, off);
/*
* record the offset from the start of the extent
* for adjusting the disk offset below
*/
offset_in_extent = em_start - em->start;
em_end = extent_map_end(em);
em_len = em_end - em_start;
emflags = em->flags;
disko = 0;
flags = 0;
/*
* bump off for our next call to get_extent
*/
off = extent_map_end(em);
if (off >= max)
end = 1;
if (em->block_start == EXTENT_MAP_LAST_BYTE) {
end = 1;
flags |= FIEMAP_EXTENT_LAST;
} else if (em->block_start == EXTENT_MAP_INLINE) {
flags |= (FIEMAP_EXTENT_DATA_INLINE |
FIEMAP_EXTENT_NOT_ALIGNED);
} else if (em->block_start == EXTENT_MAP_DELALLOC) {
flags |= (FIEMAP_EXTENT_DELALLOC |
FIEMAP_EXTENT_UNKNOWN);
} else {
disko = em->block_start + offset_in_extent;
}
if (test_bit(EXTENT_FLAG_COMPRESSED, &em->flags))
flags |= FIEMAP_EXTENT_ENCODED;
free_extent_map(em);
em = NULL;
if ((em_start >= last) || em_len == (u64)-1 ||
(last == (u64)-1 && isize <= em_end)) {
flags |= FIEMAP_EXTENT_LAST;
end = 1;
}
/* now scan forward to see if this is really the last extent. */
em = get_extent_skip_holes(inode, off, last_for_get_extent,
get_extent);
if (IS_ERR(em)) {
ret = PTR_ERR(em);
goto out;
}
if (!em) {
flags |= FIEMAP_EXTENT_LAST;
end = 1;
}
ret = fiemap_fill_next_extent(fieinfo, em_start, disko,
em_len, flags);
if (ret) {
if (ret == 1)
ret = 0;
goto out_free;
}
}
out_free:
free_extent_map(em);
out:
unlock_extent_cached(&BTRFS_I(inode)->io_tree, start, start + len - 1,
&cached_state, GFP_NOFS);
return ret;
}
static void __free_extent_buffer(struct extent_buffer *eb)
{
btrfs_leak_debug_del(&eb->leak_list);
kmem_cache_free(extent_buffer_cache, eb);
}
static struct extent_buffer *__alloc_extent_buffer(struct extent_io_tree *tree,
u64 start,
unsigned long len,
gfp_t mask)
{
struct extent_buffer *eb = NULL;
eb = kmem_cache_zalloc(extent_buffer_cache, mask);
if (eb == NULL)
return NULL;
eb->start = start;
eb->len = len;
eb->tree = tree;
eb->bflags = 0;
rwlock_init(&eb->lock);
atomic_set(&eb->write_locks, 0);
atomic_set(&eb->read_locks, 0);
atomic_set(&eb->blocking_readers, 0);
atomic_set(&eb->blocking_writers, 0);
atomic_set(&eb->spinning_readers, 0);
atomic_set(&eb->spinning_writers, 0);
eb->lock_nested = 0;
init_waitqueue_head(&eb->write_lock_wq);
init_waitqueue_head(&eb->read_lock_wq);
btrfs_leak_debug_add(&eb->leak_list, &buffers);
spin_lock_init(&eb->refs_lock);
atomic_set(&eb->refs, 1);
atomic_set(&eb->io_pages, 0);
/*
* Sanity checks, currently the maximum is 64k covered by 16x 4k pages
*/
BUILD_BUG_ON(BTRFS_MAX_METADATA_BLOCKSIZE
> MAX_INLINE_EXTENT_BUFFER_SIZE);
BUG_ON(len > MAX_INLINE_EXTENT_BUFFER_SIZE);
return eb;
}
struct extent_buffer *btrfs_clone_extent_buffer(struct extent_buffer *src)
{
unsigned long i;
struct page *p;
struct extent_buffer *new;
unsigned long num_pages = num_extent_pages(src->start, src->len);
new = __alloc_extent_buffer(NULL, src->start, src->len, GFP_ATOMIC);
if (new == NULL)
return NULL;
for (i = 0; i < num_pages; i++) {
p = alloc_page(GFP_ATOMIC);
BUG_ON(!p);
attach_extent_buffer_page(new, p);
WARN_ON(PageDirty(p));
SetPageUptodate(p);
new->pages[i] = p;
}
copy_extent_buffer(new, src, 0, 0, src->len);
set_bit(EXTENT_BUFFER_UPTODATE, &new->bflags);
set_bit(EXTENT_BUFFER_DUMMY, &new->bflags);
return new;
}
struct extent_buffer *alloc_dummy_extent_buffer(u64 start, unsigned long len)
{
struct extent_buffer *eb;
unsigned long num_pages = num_extent_pages(0, len);
unsigned long i;
eb = __alloc_extent_buffer(NULL, start, len, GFP_ATOMIC);
if (!eb)
return NULL;
for (i = 0; i < num_pages; i++) {
eb->pages[i] = alloc_page(GFP_ATOMIC);
if (!eb->pages[i])
goto err;
}
set_extent_buffer_uptodate(eb);
btrfs_set_header_nritems(eb, 0);
set_bit(EXTENT_BUFFER_DUMMY, &eb->bflags);
return eb;
err:
for (; i > 0; i--)
__free_page(eb->pages[i - 1]);
__free_extent_buffer(eb);
return NULL;
}
static int extent_buffer_under_io(struct extent_buffer *eb)
{
return (atomic_read(&eb->io_pages) ||
test_bit(EXTENT_BUFFER_WRITEBACK, &eb->bflags) ||
test_bit(EXTENT_BUFFER_DIRTY, &eb->bflags));
}
/*
* Helper for releasing extent buffer page.
*/
static void btrfs_release_extent_buffer_page(struct extent_buffer *eb,
unsigned long start_idx)
{
unsigned long index;
unsigned long num_pages;
struct page *page;
int mapped = !test_bit(EXTENT_BUFFER_DUMMY, &eb->bflags);
BUG_ON(extent_buffer_under_io(eb));
num_pages = num_extent_pages(eb->start, eb->len);
index = start_idx + num_pages;
if (start_idx >= index)
return;
do {
index--;
page = extent_buffer_page(eb, index);
if (page && mapped) {
spin_lock(&page->mapping->private_lock);
/*
* We do this since we'll remove the pages after we've
* removed the eb from the radix tree, so we could race
* and have this page now attached to the new eb. So
* only clear page_private if it's still connected to
* this eb.
*/
if (PagePrivate(page) &&
page->private == (unsigned long)eb) {
BUG_ON(test_bit(EXTENT_BUFFER_DIRTY, &eb->bflags));
BUG_ON(PageDirty(page));
BUG_ON(PageWriteback(page));
/*
* We need to make sure we haven't be attached
* to a new eb.
*/
ClearPagePrivate(page);
set_page_private(page, 0);
/* One for the page private */
page_cache_release(page);
}
spin_unlock(&page->mapping->private_lock);
}
if (page) {
/* One for when we alloced the page */
page_cache_release(page);
}
} while (index != start_idx);
}
/*
* Helper for releasing the extent buffer.
*/
static inline void btrfs_release_extent_buffer(struct extent_buffer *eb)
{
btrfs_release_extent_buffer_page(eb, 0);
__free_extent_buffer(eb);
}
static void check_buffer_tree_ref(struct extent_buffer *eb)
{
int refs;
/* the ref bit is tricky. We have to make sure it is set
* if we have the buffer dirty. Otherwise the
* code to free a buffer can end up dropping a dirty
* page
*
* Once the ref bit is set, it won't go away while the
* buffer is dirty or in writeback, and it also won't
* go away while we have the reference count on the
* eb bumped.
*
* We can't just set the ref bit without bumping the
* ref on the eb because free_extent_buffer might
* see the ref bit and try to clear it. If this happens
* free_extent_buffer might end up dropping our original
* ref by mistake and freeing the page before we are able
* to add one more ref.
*
* So bump the ref count first, then set the bit. If someone
* beat us to it, drop the ref we added.
*/
refs = atomic_read(&eb->refs);
if (refs >= 2 && test_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags))
return;
spin_lock(&eb->refs_lock);
if (!test_and_set_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags))
atomic_inc(&eb->refs);
spin_unlock(&eb->refs_lock);
}
static void mark_extent_buffer_accessed(struct extent_buffer *eb)
{
unsigned long num_pages, i;
check_buffer_tree_ref(eb);
num_pages = num_extent_pages(eb->start, eb->len);
for (i = 0; i < num_pages; i++) {
struct page *p = extent_buffer_page(eb, i);
mark_page_accessed(p);
}
}
struct extent_buffer *alloc_extent_buffer(struct extent_io_tree *tree,
u64 start, unsigned long len)
{
unsigned long num_pages = num_extent_pages(start, len);
unsigned long i;
unsigned long index = start >> PAGE_CACHE_SHIFT;
struct extent_buffer *eb;
struct extent_buffer *exists = NULL;
struct page *p;
struct address_space *mapping = tree->mapping;
int uptodate = 1;
int ret;
rcu_read_lock();
eb = radix_tree_lookup(&tree->buffer, start >> PAGE_CACHE_SHIFT);
if (eb && atomic_inc_not_zero(&eb->refs)) {
rcu_read_unlock();
mark_extent_buffer_accessed(eb);
return eb;
}
rcu_read_unlock();
eb = __alloc_extent_buffer(tree, start, len, GFP_NOFS);
if (!eb)
return NULL;
for (i = 0; i < num_pages; i++, index++) {
p = find_or_create_page(mapping, index, GFP_NOFS);
if (!p)
goto free_eb;
spin_lock(&mapping->private_lock);
if (PagePrivate(p)) {
/*
* We could have already allocated an eb for this page
* and attached one so lets see if we can get a ref on
* the existing eb, and if we can we know it's good and
* we can just return that one, else we know we can just
* overwrite page->private.
*/
exists = (struct extent_buffer *)p->private;
if (atomic_inc_not_zero(&exists->refs)) {
spin_unlock(&mapping->private_lock);
unlock_page(p);
page_cache_release(p);
mark_extent_buffer_accessed(exists);
goto free_eb;
}
/*
* Do this so attach doesn't complain and we need to
* drop the ref the old guy had.
*/
ClearPagePrivate(p);
WARN_ON(PageDirty(p));
page_cache_release(p);
}
attach_extent_buffer_page(eb, p);
spin_unlock(&mapping->private_lock);
WARN_ON(PageDirty(p));
mark_page_accessed(p);
eb->pages[i] = p;
if (!PageUptodate(p))
uptodate = 0;
/*
* see below about how we avoid a nasty race with release page
* and why we unlock later
*/
}
if (uptodate)
set_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags);
again:
ret = radix_tree_preload(GFP_NOFS & ~__GFP_HIGHMEM);
if (ret)
goto free_eb;
spin_lock(&tree->buffer_lock);
ret = radix_tree_insert(&tree->buffer, start >> PAGE_CACHE_SHIFT, eb);
if (ret == -EEXIST) {
exists = radix_tree_lookup(&tree->buffer,
start >> PAGE_CACHE_SHIFT);
if (!atomic_inc_not_zero(&exists->refs)) {
spin_unlock(&tree->buffer_lock);
radix_tree_preload_end();
exists = NULL;
goto again;
}
spin_unlock(&tree->buffer_lock);
radix_tree_preload_end();
mark_extent_buffer_accessed(exists);
goto free_eb;
}
/* add one reference for the tree */
check_buffer_tree_ref(eb);
spin_unlock(&tree->buffer_lock);
radix_tree_preload_end();
/*
* there is a race where release page may have
* tried to find this extent buffer in the radix
* but failed. It will tell the VM it is safe to
* reclaim the, and it will clear the page private bit.
* We must make sure to set the page private bit properly
* after the extent buffer is in the radix tree so
* it doesn't get lost
*/
SetPageChecked(eb->pages[0]);
for (i = 1; i < num_pages; i++) {
p = extent_buffer_page(eb, i);
ClearPageChecked(p);
unlock_page(p);
}
unlock_page(eb->pages[0]);
return eb;
free_eb:
for (i = 0; i < num_pages; i++) {
if (eb->pages[i])
unlock_page(eb->pages[i]);
}
WARN_ON(!atomic_dec_and_test(&eb->refs));
btrfs_release_extent_buffer(eb);
return exists;
}
struct extent_buffer *find_extent_buffer(struct extent_io_tree *tree,
u64 start, unsigned long len)
{
struct extent_buffer *eb;
rcu_read_lock();
eb = radix_tree_lookup(&tree->buffer, start >> PAGE_CACHE_SHIFT);
if (eb && atomic_inc_not_zero(&eb->refs)) {
rcu_read_unlock();
mark_extent_buffer_accessed(eb);
return eb;
}
rcu_read_unlock();
return NULL;
}
static inline void btrfs_release_extent_buffer_rcu(struct rcu_head *head)
{
struct extent_buffer *eb =
container_of(head, struct extent_buffer, rcu_head);
__free_extent_buffer(eb);
}
/* Expects to have eb->eb_lock already held */
static int release_extent_buffer(struct extent_buffer *eb)
{
WARN_ON(atomic_read(&eb->refs) == 0);
if (atomic_dec_and_test(&eb->refs)) {
if (test_bit(EXTENT_BUFFER_DUMMY, &eb->bflags)) {
spin_unlock(&eb->refs_lock);
} else {
struct extent_io_tree *tree = eb->tree;
spin_unlock(&eb->refs_lock);
spin_lock(&tree->buffer_lock);
radix_tree_delete(&tree->buffer,
eb->start >> PAGE_CACHE_SHIFT);
spin_unlock(&tree->buffer_lock);
}
/* Should be safe to release our pages at this point */
btrfs_release_extent_buffer_page(eb, 0);
call_rcu(&eb->rcu_head, btrfs_release_extent_buffer_rcu);
return 1;
}
spin_unlock(&eb->refs_lock);
return 0;
}
void free_extent_buffer(struct extent_buffer *eb)
{
int refs;
int old;
if (!eb)
return;
while (1) {
refs = atomic_read(&eb->refs);
if (refs <= 3)
break;
old = atomic_cmpxchg(&eb->refs, refs, refs - 1);
if (old == refs)
return;
}
spin_lock(&eb->refs_lock);
if (atomic_read(&eb->refs) == 2 &&
test_bit(EXTENT_BUFFER_DUMMY, &eb->bflags))
atomic_dec(&eb->refs);
if (atomic_read(&eb->refs) == 2 &&
test_bit(EXTENT_BUFFER_STALE, &eb->bflags) &&
!extent_buffer_under_io(eb) &&
test_and_clear_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags))
atomic_dec(&eb->refs);
/*
* I know this is terrible, but it's temporary until we stop tracking
* the uptodate bits and such for the extent buffers.
*/
release_extent_buffer(eb);
}
void free_extent_buffer_stale(struct extent_buffer *eb)
{
if (!eb)
return;
spin_lock(&eb->refs_lock);
set_bit(EXTENT_BUFFER_STALE, &eb->bflags);
if (atomic_read(&eb->refs) == 2 && !extent_buffer_under_io(eb) &&
test_and_clear_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags))
atomic_dec(&eb->refs);
release_extent_buffer(eb);
}
void clear_extent_buffer_dirty(struct extent_buffer *eb)
{
unsigned long i;
unsigned long num_pages;
struct page *page;
num_pages = num_extent_pages(eb->start, eb->len);
for (i = 0; i < num_pages; i++) {
page = extent_buffer_page(eb, i);
if (!PageDirty(page))
continue;
lock_page(page);
WARN_ON(!PagePrivate(page));
clear_page_dirty_for_io(page);
spin_lock_irq(&page->mapping->tree_lock);
if (!PageDirty(page)) {
radix_tree_tag_clear(&page->mapping->page_tree,
page_index(page),
PAGECACHE_TAG_DIRTY);
}
spin_unlock_irq(&page->mapping->tree_lock);
ClearPageError(page);
unlock_page(page);
}
WARN_ON(atomic_read(&eb->refs) == 0);
}
int set_extent_buffer_dirty(struct extent_buffer *eb)
{
unsigned long i;
unsigned long num_pages;
int was_dirty = 0;
check_buffer_tree_ref(eb);
was_dirty = test_and_set_bit(EXTENT_BUFFER_DIRTY, &eb->bflags);
num_pages = num_extent_pages(eb->start, eb->len);
WARN_ON(atomic_read(&eb->refs) == 0);
WARN_ON(!test_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags));
for (i = 0; i < num_pages; i++)
set_page_dirty(extent_buffer_page(eb, i));
return was_dirty;
}
int clear_extent_buffer_uptodate(struct extent_buffer *eb)
{
unsigned long i;
struct page *page;
unsigned long num_pages;
clear_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags);
num_pages = num_extent_pages(eb->start, eb->len);
for (i = 0; i < num_pages; i++) {
page = extent_buffer_page(eb, i);
if (page)
ClearPageUptodate(page);
}
return 0;
}
int set_extent_buffer_uptodate(struct extent_buffer *eb)
{
unsigned long i;
struct page *page;
unsigned long num_pages;
set_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags);
num_pages = num_extent_pages(eb->start, eb->len);
for (i = 0; i < num_pages; i++) {
page = extent_buffer_page(eb, i);
SetPageUptodate(page);
}
return 0;
}
int extent_buffer_uptodate(struct extent_buffer *eb)
{
return test_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags);
}
int read_extent_buffer_pages(struct extent_io_tree *tree,
struct extent_buffer *eb, u64 start, int wait,
get_extent_t *get_extent, int mirror_num)
{
unsigned long i;
unsigned long start_i;
struct page *page;
int err;
int ret = 0;
int locked_pages = 0;
int all_uptodate = 1;
unsigned long num_pages;
unsigned long num_reads = 0;
struct bio *bio = NULL;
unsigned long bio_flags = 0;
if (test_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags))
return 0;
if (start) {
WARN_ON(start < eb->start);
start_i = (start >> PAGE_CACHE_SHIFT) -
(eb->start >> PAGE_CACHE_SHIFT);
} else {
start_i = 0;
}
num_pages = num_extent_pages(eb->start, eb->len);
for (i = start_i; i < num_pages; i++) {
page = extent_buffer_page(eb, i);
if (wait == WAIT_NONE) {
if (!trylock_page(page))
goto unlock_exit;
} else {
lock_page(page);
}
locked_pages++;
if (!PageUptodate(page)) {
num_reads++;
all_uptodate = 0;
}
}
if (all_uptodate) {
if (start_i == 0)
set_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags);
goto unlock_exit;
}
clear_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
eb->read_mirror = 0;
atomic_set(&eb->io_pages, num_reads);
for (i = start_i; i < num_pages; i++) {
page = extent_buffer_page(eb, i);
if (!PageUptodate(page)) {
ClearPageError(page);
err = __extent_read_full_page(tree, page,
get_extent, &bio,
mirror_num, &bio_flags,
READ | REQ_META);
if (err)
ret = err;
} else {
unlock_page(page);
}
}
if (bio) {
err = submit_one_bio(READ | REQ_META, bio, mirror_num,
bio_flags);
if (err)
return err;
}
if (ret || wait != WAIT_COMPLETE)
return ret;
for (i = start_i; i < num_pages; i++) {
page = extent_buffer_page(eb, i);
wait_on_page_locked(page);
if (!PageUptodate(page))
ret = -EIO;
}
return ret;
unlock_exit:
i = start_i;
while (locked_pages > 0) {
page = extent_buffer_page(eb, i);
i++;
unlock_page(page);
locked_pages--;
}
return ret;
}
void read_extent_buffer(struct extent_buffer *eb, void *dstv,
unsigned long start,
unsigned long len)
{
size_t cur;
size_t offset;
struct page *page;
char *kaddr;
char *dst = (char *)dstv;
size_t start_offset = eb->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long i = (start_offset + start) >> PAGE_CACHE_SHIFT;
WARN_ON(start > eb->len);
WARN_ON(start + len > eb->start + eb->len);
offset = (start_offset + start) & ((unsigned long)PAGE_CACHE_SIZE - 1);
while (len > 0) {
page = extent_buffer_page(eb, i);
cur = min(len, (PAGE_CACHE_SIZE - offset));
kaddr = page_address(page);
memcpy(dst, kaddr + offset, cur);
dst += cur;
len -= cur;
offset = 0;
i++;
}
}
int map_private_extent_buffer(struct extent_buffer *eb, unsigned long start,
unsigned long min_len, char **map,
unsigned long *map_start,
unsigned long *map_len)
{
size_t offset = start & (PAGE_CACHE_SIZE - 1);
char *kaddr;
struct page *p;
size_t start_offset = eb->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long i = (start_offset + start) >> PAGE_CACHE_SHIFT;
unsigned long end_i = (start_offset + start + min_len - 1) >>
PAGE_CACHE_SHIFT;
if (i != end_i)
return -EINVAL;
if (i == 0) {
offset = start_offset;
*map_start = 0;
} else {
offset = 0;
*map_start = ((u64)i << PAGE_CACHE_SHIFT) - start_offset;
}
if (start + min_len > eb->len) {
WARN(1, KERN_ERR "btrfs bad mapping eb start %llu len %lu, "
"wanted %lu %lu\n", (unsigned long long)eb->start,
eb->len, start, min_len);
return -EINVAL;
}
p = extent_buffer_page(eb, i);
kaddr = page_address(p);
*map = kaddr + offset;
*map_len = PAGE_CACHE_SIZE - offset;
return 0;
}
int memcmp_extent_buffer(struct extent_buffer *eb, const void *ptrv,
unsigned long start,
unsigned long len)
{
size_t cur;
size_t offset;
struct page *page;
char *kaddr;
char *ptr = (char *)ptrv;
size_t start_offset = eb->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long i = (start_offset + start) >> PAGE_CACHE_SHIFT;
int ret = 0;
WARN_ON(start > eb->len);
WARN_ON(start + len > eb->start + eb->len);
offset = (start_offset + start) & ((unsigned long)PAGE_CACHE_SIZE - 1);
while (len > 0) {
page = extent_buffer_page(eb, i);
cur = min(len, (PAGE_CACHE_SIZE - offset));
kaddr = page_address(page);
ret = memcmp(ptr, kaddr + offset, cur);
if (ret)
break;
ptr += cur;
len -= cur;
offset = 0;
i++;
}
return ret;
}
void write_extent_buffer(struct extent_buffer *eb, const void *srcv,
unsigned long start, unsigned long len)
{
size_t cur;
size_t offset;
struct page *page;
char *kaddr;
char *src = (char *)srcv;
size_t start_offset = eb->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long i = (start_offset + start) >> PAGE_CACHE_SHIFT;
WARN_ON(start > eb->len);
WARN_ON(start + len > eb->start + eb->len);
offset = (start_offset + start) & ((unsigned long)PAGE_CACHE_SIZE - 1);
while (len > 0) {
page = extent_buffer_page(eb, i);
WARN_ON(!PageUptodate(page));
cur = min(len, PAGE_CACHE_SIZE - offset);
kaddr = page_address(page);
memcpy(kaddr + offset, src, cur);
src += cur;
len -= cur;
offset = 0;
i++;
}
}
void memset_extent_buffer(struct extent_buffer *eb, char c,
unsigned long start, unsigned long len)
{
size_t cur;
size_t offset;
struct page *page;
char *kaddr;
size_t start_offset = eb->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long i = (start_offset + start) >> PAGE_CACHE_SHIFT;
WARN_ON(start > eb->len);
WARN_ON(start + len > eb->start + eb->len);
offset = (start_offset + start) & ((unsigned long)PAGE_CACHE_SIZE - 1);
while (len > 0) {
page = extent_buffer_page(eb, i);
WARN_ON(!PageUptodate(page));
cur = min(len, PAGE_CACHE_SIZE - offset);
kaddr = page_address(page);
memset(kaddr + offset, c, cur);
len -= cur;
offset = 0;
i++;
}
}
void copy_extent_buffer(struct extent_buffer *dst, struct extent_buffer *src,
unsigned long dst_offset, unsigned long src_offset,
unsigned long len)
{
u64 dst_len = dst->len;
size_t cur;
size_t offset;
struct page *page;
char *kaddr;
size_t start_offset = dst->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long i = (start_offset + dst_offset) >> PAGE_CACHE_SHIFT;
WARN_ON(src->len != dst_len);
offset = (start_offset + dst_offset) &
((unsigned long)PAGE_CACHE_SIZE - 1);
while (len > 0) {
page = extent_buffer_page(dst, i);
WARN_ON(!PageUptodate(page));
cur = min(len, (unsigned long)(PAGE_CACHE_SIZE - offset));
kaddr = page_address(page);
read_extent_buffer(src, kaddr + offset, src_offset, cur);
src_offset += cur;
len -= cur;
offset = 0;
i++;
}
}
static void move_pages(struct page *dst_page, struct page *src_page,
unsigned long dst_off, unsigned long src_off,
unsigned long len)
{
char *dst_kaddr = page_address(dst_page);
if (dst_page == src_page) {
memmove(dst_kaddr + dst_off, dst_kaddr + src_off, len);
} else {
char *src_kaddr = page_address(src_page);
char *p = dst_kaddr + dst_off + len;
char *s = src_kaddr + src_off + len;
while (len--)
*--p = *--s;
}
}
static inline bool areas_overlap(unsigned long src, unsigned long dst, unsigned long len)
{
unsigned long distance = (src > dst) ? src - dst : dst - src;
return distance < len;
}
static void copy_pages(struct page *dst_page, struct page *src_page,
unsigned long dst_off, unsigned long src_off,
unsigned long len)
{
char *dst_kaddr = page_address(dst_page);
char *src_kaddr;
int must_memmove = 0;
if (dst_page != src_page) {
src_kaddr = page_address(src_page);
} else {
src_kaddr = dst_kaddr;
if (areas_overlap(src_off, dst_off, len))
must_memmove = 1;
}
if (must_memmove)
memmove(dst_kaddr + dst_off, src_kaddr + src_off, len);
else
memcpy(dst_kaddr + dst_off, src_kaddr + src_off, len);
}
void memcpy_extent_buffer(struct extent_buffer *dst, unsigned long dst_offset,
unsigned long src_offset, unsigned long len)
{
size_t cur;
size_t dst_off_in_page;
size_t src_off_in_page;
size_t start_offset = dst->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long dst_i;
unsigned long src_i;
if (src_offset + len > dst->len) {
printk(KERN_ERR "btrfs memmove bogus src_offset %lu move "
"len %lu dst len %lu\n", src_offset, len, dst->len);
BUG_ON(1);
}
if (dst_offset + len > dst->len) {
printk(KERN_ERR "btrfs memmove bogus dst_offset %lu move "
"len %lu dst len %lu\n", dst_offset, len, dst->len);
BUG_ON(1);
}
while (len > 0) {
dst_off_in_page = (start_offset + dst_offset) &
((unsigned long)PAGE_CACHE_SIZE - 1);
src_off_in_page = (start_offset + src_offset) &
((unsigned long)PAGE_CACHE_SIZE - 1);
dst_i = (start_offset + dst_offset) >> PAGE_CACHE_SHIFT;
src_i = (start_offset + src_offset) >> PAGE_CACHE_SHIFT;
cur = min(len, (unsigned long)(PAGE_CACHE_SIZE -
src_off_in_page));
cur = min_t(unsigned long, cur,
(unsigned long)(PAGE_CACHE_SIZE - dst_off_in_page));
copy_pages(extent_buffer_page(dst, dst_i),
extent_buffer_page(dst, src_i),
dst_off_in_page, src_off_in_page, cur);
src_offset += cur;
dst_offset += cur;
len -= cur;
}
}
void memmove_extent_buffer(struct extent_buffer *dst, unsigned long dst_offset,
unsigned long src_offset, unsigned long len)
{
size_t cur;
size_t dst_off_in_page;
size_t src_off_in_page;
unsigned long dst_end = dst_offset + len - 1;
unsigned long src_end = src_offset + len - 1;
size_t start_offset = dst->start & ((u64)PAGE_CACHE_SIZE - 1);
unsigned long dst_i;
unsigned long src_i;
if (src_offset + len > dst->len) {
printk(KERN_ERR "btrfs memmove bogus src_offset %lu move "
"len %lu len %lu\n", src_offset, len, dst->len);
BUG_ON(1);
}
if (dst_offset + len > dst->len) {
printk(KERN_ERR "btrfs memmove bogus dst_offset %lu move "
"len %lu len %lu\n", dst_offset, len, dst->len);
BUG_ON(1);
}
if (dst_offset < src_offset) {
memcpy_extent_buffer(dst, dst_offset, src_offset, len);
return;
}
while (len > 0) {
dst_i = (start_offset + dst_end) >> PAGE_CACHE_SHIFT;
src_i = (start_offset + src_end) >> PAGE_CACHE_SHIFT;
dst_off_in_page = (start_offset + dst_end) &
((unsigned long)PAGE_CACHE_SIZE - 1);
src_off_in_page = (start_offset + src_end) &
((unsigned long)PAGE_CACHE_SIZE - 1);
cur = min_t(unsigned long, len, src_off_in_page + 1);
cur = min(cur, dst_off_in_page + 1);
move_pages(extent_buffer_page(dst, dst_i),
extent_buffer_page(dst, src_i),
dst_off_in_page - cur + 1,
src_off_in_page - cur + 1, cur);
dst_end -= cur;
src_end -= cur;
len -= cur;
}
}
int try_release_extent_buffer(struct page *page)
{
struct extent_buffer *eb;
/*
* We need to make sure noboody is attaching this page to an eb right
* now.
*/
spin_lock(&page->mapping->private_lock);
if (!PagePrivate(page)) {
spin_unlock(&page->mapping->private_lock);
return 1;
}
eb = (struct extent_buffer *)page->private;
BUG_ON(!eb);
/*
* This is a little awful but should be ok, we need to make sure that
* the eb doesn't disappear out from under us while we're looking at
* this page.
*/
spin_lock(&eb->refs_lock);
if (atomic_read(&eb->refs) != 1 || extent_buffer_under_io(eb)) {
spin_unlock(&eb->refs_lock);
spin_unlock(&page->mapping->private_lock);
return 0;
}
spin_unlock(&page->mapping->private_lock);
/*
* If tree ref isn't set then we know the ref on this eb is a real ref,
* so just return, this page will likely be freed soon anyway.
*/
if (!test_and_clear_bit(EXTENT_BUFFER_TREE_REF, &eb->bflags)) {
spin_unlock(&eb->refs_lock);
return 0;
}
return release_extent_buffer(eb);
}
| gpl-2.0 |
cmenard/GB_Bullet | net/sched/sch_red.c | 941 | 8040 | /*
* net/sched/sch_red.c Random Early Detection queue.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Authors: Alexey Kuznetsov, <kuznet@ms2.inr.ac.ru>
*
* Changes:
* J Hadi Salim 980914: computation fixes
* Alexey Makarenko <makar@phoenix.kharkov.ua> 990814: qave on idle link was calculated incorrectly.
* J Hadi Salim 980816: ECN support
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/skbuff.h>
#include <net/pkt_sched.h>
#include <net/inet_ecn.h>
#include <net/red.h>
/* Parameters, settable by user:
-----------------------------
limit - bytes (must be > qth_max + burst)
Hard limit on queue length, should be chosen >qth_max
to allow packet bursts. This parameter does not
affect the algorithms behaviour and can be chosen
arbitrarily high (well, less than ram size)
Really, this limit will never be reached
if RED works correctly.
*/
struct red_sched_data
{
u32 limit; /* HARD maximal queue length */
unsigned char flags;
struct red_parms parms;
struct red_stats stats;
struct Qdisc *qdisc;
};
static inline int red_use_ecn(struct red_sched_data *q)
{
return q->flags & TC_RED_ECN;
}
static inline int red_use_harddrop(struct red_sched_data *q)
{
return q->flags & TC_RED_HARDDROP;
}
static int red_enqueue(struct sk_buff *skb, struct Qdisc* sch)
{
struct red_sched_data *q = qdisc_priv(sch);
struct Qdisc *child = q->qdisc;
int ret;
q->parms.qavg = red_calc_qavg(&q->parms, child->qstats.backlog);
if (red_is_idling(&q->parms))
red_end_of_idle_period(&q->parms);
switch (red_action(&q->parms, q->parms.qavg)) {
case RED_DONT_MARK:
break;
case RED_PROB_MARK:
sch->qstats.overlimits++;
if (!red_use_ecn(q) || !INET_ECN_set_ce(skb)) {
q->stats.prob_drop++;
goto congestion_drop;
}
q->stats.prob_mark++;
break;
case RED_HARD_MARK:
sch->qstats.overlimits++;
if (red_use_harddrop(q) || !red_use_ecn(q) ||
!INET_ECN_set_ce(skb)) {
q->stats.forced_drop++;
goto congestion_drop;
}
q->stats.forced_mark++;
break;
}
ret = qdisc_enqueue(skb, child);
if (likely(ret == NET_XMIT_SUCCESS)) {
sch->bstats.bytes += qdisc_pkt_len(skb);
sch->bstats.packets++;
sch->q.qlen++;
} else if (net_xmit_drop_count(ret)) {
q->stats.pdrop++;
sch->qstats.drops++;
}
return ret;
congestion_drop:
qdisc_drop(skb, sch);
return NET_XMIT_CN;
}
static struct sk_buff * red_dequeue(struct Qdisc* sch)
{
struct sk_buff *skb;
struct red_sched_data *q = qdisc_priv(sch);
struct Qdisc *child = q->qdisc;
skb = child->dequeue(child);
if (skb)
sch->q.qlen--;
else if (!red_is_idling(&q->parms))
red_start_of_idle_period(&q->parms);
return skb;
}
static struct sk_buff * red_peek(struct Qdisc* sch)
{
struct red_sched_data *q = qdisc_priv(sch);
struct Qdisc *child = q->qdisc;
return child->ops->peek(child);
}
static unsigned int red_drop(struct Qdisc* sch)
{
struct red_sched_data *q = qdisc_priv(sch);
struct Qdisc *child = q->qdisc;
unsigned int len;
if (child->ops->drop && (len = child->ops->drop(child)) > 0) {
q->stats.other++;
sch->qstats.drops++;
sch->q.qlen--;
return len;
}
if (!red_is_idling(&q->parms))
red_start_of_idle_period(&q->parms);
return 0;
}
static void red_reset(struct Qdisc* sch)
{
struct red_sched_data *q = qdisc_priv(sch);
qdisc_reset(q->qdisc);
sch->q.qlen = 0;
red_restart(&q->parms);
}
static void red_destroy(struct Qdisc *sch)
{
struct red_sched_data *q = qdisc_priv(sch);
qdisc_destroy(q->qdisc);
}
static const struct nla_policy red_policy[TCA_RED_MAX + 1] = {
[TCA_RED_PARMS] = { .len = sizeof(struct tc_red_qopt) },
[TCA_RED_STAB] = { .len = RED_STAB_SIZE },
};
static int red_change(struct Qdisc *sch, struct nlattr *opt)
{
struct red_sched_data *q = qdisc_priv(sch);
struct nlattr *tb[TCA_RED_MAX + 1];
struct tc_red_qopt *ctl;
struct Qdisc *child = NULL;
int err;
if (opt == NULL)
return -EINVAL;
err = nla_parse_nested(tb, TCA_RED_MAX, opt, red_policy);
if (err < 0)
return err;
if (tb[TCA_RED_PARMS] == NULL ||
tb[TCA_RED_STAB] == NULL)
return -EINVAL;
ctl = nla_data(tb[TCA_RED_PARMS]);
if (ctl->limit > 0) {
child = fifo_create_dflt(sch, &bfifo_qdisc_ops, ctl->limit);
if (IS_ERR(child))
return PTR_ERR(child);
}
sch_tree_lock(sch);
q->flags = ctl->flags;
q->limit = ctl->limit;
if (child) {
qdisc_tree_decrease_qlen(q->qdisc, q->qdisc->q.qlen);
qdisc_destroy(q->qdisc);
q->qdisc = child;
}
red_set_parms(&q->parms, ctl->qth_min, ctl->qth_max, ctl->Wlog,
ctl->Plog, ctl->Scell_log,
nla_data(tb[TCA_RED_STAB]));
if (skb_queue_empty(&sch->q))
red_end_of_idle_period(&q->parms);
sch_tree_unlock(sch);
return 0;
}
static int red_init(struct Qdisc* sch, struct nlattr *opt)
{
struct red_sched_data *q = qdisc_priv(sch);
q->qdisc = &noop_qdisc;
return red_change(sch, opt);
}
static int red_dump(struct Qdisc *sch, struct sk_buff *skb)
{
struct red_sched_data *q = qdisc_priv(sch);
struct nlattr *opts = NULL;
struct tc_red_qopt opt = {
.limit = q->limit,
.flags = q->flags,
.qth_min = q->parms.qth_min >> q->parms.Wlog,
.qth_max = q->parms.qth_max >> q->parms.Wlog,
.Wlog = q->parms.Wlog,
.Plog = q->parms.Plog,
.Scell_log = q->parms.Scell_log,
};
opts = nla_nest_start(skb, TCA_OPTIONS);
if (opts == NULL)
goto nla_put_failure;
NLA_PUT(skb, TCA_RED_PARMS, sizeof(opt), &opt);
return nla_nest_end(skb, opts);
nla_put_failure:
nla_nest_cancel(skb, opts);
return -EMSGSIZE;
}
static int red_dump_stats(struct Qdisc *sch, struct gnet_dump *d)
{
struct red_sched_data *q = qdisc_priv(sch);
struct tc_red_xstats st = {
.early = q->stats.prob_drop + q->stats.forced_drop,
.pdrop = q->stats.pdrop,
.other = q->stats.other,
.marked = q->stats.prob_mark + q->stats.forced_mark,
};
return gnet_stats_copy_app(d, &st, sizeof(st));
}
static int red_dump_class(struct Qdisc *sch, unsigned long cl,
struct sk_buff *skb, struct tcmsg *tcm)
{
struct red_sched_data *q = qdisc_priv(sch);
tcm->tcm_handle |= TC_H_MIN(1);
tcm->tcm_info = q->qdisc->handle;
return 0;
}
static int red_graft(struct Qdisc *sch, unsigned long arg, struct Qdisc *new,
struct Qdisc **old)
{
struct red_sched_data *q = qdisc_priv(sch);
if (new == NULL)
new = &noop_qdisc;
sch_tree_lock(sch);
*old = q->qdisc;
q->qdisc = new;
qdisc_tree_decrease_qlen(*old, (*old)->q.qlen);
qdisc_reset(*old);
sch_tree_unlock(sch);
return 0;
}
static struct Qdisc *red_leaf(struct Qdisc *sch, unsigned long arg)
{
struct red_sched_data *q = qdisc_priv(sch);
return q->qdisc;
}
static unsigned long red_get(struct Qdisc *sch, u32 classid)
{
return 1;
}
static void red_put(struct Qdisc *sch, unsigned long arg)
{
}
static void red_walk(struct Qdisc *sch, struct qdisc_walker *walker)
{
if (!walker->stop) {
if (walker->count >= walker->skip)
if (walker->fn(sch, 1, walker) < 0) {
walker->stop = 1;
return;
}
walker->count++;
}
}
static const struct Qdisc_class_ops red_class_ops = {
.graft = red_graft,
.leaf = red_leaf,
.get = red_get,
.put = red_put,
.walk = red_walk,
.dump = red_dump_class,
};
static struct Qdisc_ops red_qdisc_ops __read_mostly = {
.id = "red",
.priv_size = sizeof(struct red_sched_data),
.cl_ops = &red_class_ops,
.enqueue = red_enqueue,
.dequeue = red_dequeue,
.peek = red_peek,
.drop = red_drop,
.init = red_init,
.reset = red_reset,
.destroy = red_destroy,
.change = red_change,
.dump = red_dump,
.dump_stats = red_dump_stats,
.owner = THIS_MODULE,
};
static int __init red_module_init(void)
{
return register_qdisc(&red_qdisc_ops);
}
static void __exit red_module_exit(void)
{
unregister_qdisc(&red_qdisc_ops);
}
module_init(red_module_init)
module_exit(red_module_exit)
MODULE_LICENSE("GPL");
| gpl-2.0 |
kmobs/htc-kernel-pyramid | drivers/scsi/gdth_proc.c | 941 | 26885 | /* gdth_proc.c
* $Id: gdth_proc.c,v 1.43 2006/01/11 16:15:00 achim Exp $
*/
#include <linux/completion.h>
#include <linux/slab.h>
int gdth_proc_info(struct Scsi_Host *host, char *buffer,char **start,off_t offset,int length,
int inout)
{
gdth_ha_str *ha = shost_priv(host);
TRACE2(("gdth_proc_info() length %d offs %d inout %d\n",
length,(int)offset,inout));
if (inout)
return(gdth_set_info(buffer,length,host,ha));
else
return(gdth_get_info(buffer,start,offset,length,host,ha));
}
static int gdth_set_info(char *buffer,int length,struct Scsi_Host *host,
gdth_ha_str *ha)
{
int ret_val = -EINVAL;
TRACE2(("gdth_set_info() ha %d\n",ha->hanum,));
if (length >= 4) {
if (strncmp(buffer,"gdth",4) == 0) {
buffer += 5;
length -= 5;
ret_val = gdth_set_asc_info(host, buffer, length, ha);
}
}
return ret_val;
}
static int gdth_set_asc_info(struct Scsi_Host *host, char *buffer,
int length, gdth_ha_str *ha)
{
int orig_length, drive, wb_mode;
int i, found;
gdth_cmd_str gdtcmd;
gdth_cpar_str *pcpar;
u64 paddr;
char cmnd[MAX_COMMAND_SIZE];
memset(cmnd, 0xff, 12);
memset(&gdtcmd, 0, sizeof(gdth_cmd_str));
TRACE2(("gdth_set_asc_info() ha %d\n",ha->hanum));
orig_length = length + 5;
drive = -1;
wb_mode = 0;
found = FALSE;
if (length >= 5 && strncmp(buffer,"flush",5)==0) {
buffer += 6;
length -= 6;
if (length && *buffer>='0' && *buffer<='9') {
drive = (int)(*buffer-'0');
++buffer; --length;
if (length && *buffer>='0' && *buffer<='9') {
drive = drive*10 + (int)(*buffer-'0');
++buffer; --length;
}
printk("GDT: Flushing host drive %d .. ",drive);
} else {
printk("GDT: Flushing all host drives .. ");
}
for (i = 0; i < MAX_HDRIVES; ++i) {
if (ha->hdr[i].present) {
if (drive != -1 && i != drive)
continue;
found = TRUE;
gdtcmd.Service = CACHESERVICE;
gdtcmd.OpCode = GDT_FLUSH;
if (ha->cache_feat & GDT_64BIT) {
gdtcmd.u.cache64.DeviceNo = i;
gdtcmd.u.cache64.BlockNo = 1;
} else {
gdtcmd.u.cache.DeviceNo = i;
gdtcmd.u.cache.BlockNo = 1;
}
gdth_execute(host, &gdtcmd, cmnd, 30, NULL);
}
}
if (!found)
printk("\nNo host drive found !\n");
else
printk("Done.\n");
return(orig_length);
}
if (length >= 7 && strncmp(buffer,"wbp_off",7)==0) {
buffer += 8;
length -= 8;
printk("GDT: Disabling write back permanently .. ");
wb_mode = 1;
} else if (length >= 6 && strncmp(buffer,"wbp_on",6)==0) {
buffer += 7;
length -= 7;
printk("GDT: Enabling write back permanently .. ");
wb_mode = 2;
} else if (length >= 6 && strncmp(buffer,"wb_off",6)==0) {
buffer += 7;
length -= 7;
printk("GDT: Disabling write back commands .. ");
if (ha->cache_feat & GDT_WR_THROUGH) {
gdth_write_through = TRUE;
printk("Done.\n");
} else {
printk("Not supported !\n");
}
return(orig_length);
} else if (length >= 5 && strncmp(buffer,"wb_on",5)==0) {
buffer += 6;
length -= 6;
printk("GDT: Enabling write back commands .. ");
gdth_write_through = FALSE;
printk("Done.\n");
return(orig_length);
}
if (wb_mode) {
if (!gdth_ioctl_alloc(ha, sizeof(gdth_cpar_str), TRUE, &paddr))
return(-EBUSY);
pcpar = (gdth_cpar_str *)ha->pscratch;
memcpy( pcpar, &ha->cpar, sizeof(gdth_cpar_str) );
gdtcmd.Service = CACHESERVICE;
gdtcmd.OpCode = GDT_IOCTL;
gdtcmd.u.ioctl.p_param = paddr;
gdtcmd.u.ioctl.param_size = sizeof(gdth_cpar_str);
gdtcmd.u.ioctl.subfunc = CACHE_CONFIG;
gdtcmd.u.ioctl.channel = INVALID_CHANNEL;
pcpar->write_back = wb_mode==1 ? 0:1;
gdth_execute(host, &gdtcmd, cmnd, 30, NULL);
gdth_ioctl_free(ha, GDTH_SCRATCH, ha->pscratch, paddr);
printk("Done.\n");
return(orig_length);
}
printk("GDT: Unknown command: %s Length: %d\n",buffer,length);
return(-EINVAL);
}
static int gdth_get_info(char *buffer,char **start,off_t offset,int length,
struct Scsi_Host *host, gdth_ha_str *ha)
{
int size = 0,len = 0;
int hlen;
off_t begin = 0,pos = 0;
int id, i, j, k, sec, flag;
int no_mdrv = 0, drv_no, is_mirr;
u32 cnt;
u64 paddr;
int rc = -ENOMEM;
gdth_cmd_str *gdtcmd;
gdth_evt_str *estr;
char hrec[161];
struct timeval tv;
char *buf;
gdth_dskstat_str *pds;
gdth_diskinfo_str *pdi;
gdth_arrayinf_str *pai;
gdth_defcnt_str *pdef;
gdth_cdrinfo_str *pcdi;
gdth_hget_str *phg;
char cmnd[MAX_COMMAND_SIZE];
gdtcmd = kmalloc(sizeof(*gdtcmd), GFP_KERNEL);
estr = kmalloc(sizeof(*estr), GFP_KERNEL);
if (!gdtcmd || !estr)
goto free_fail;
memset(cmnd, 0xff, 12);
memset(gdtcmd, 0, sizeof(gdth_cmd_str));
TRACE2(("gdth_get_info() ha %d\n",ha->hanum));
/* request is i.e. "cat /proc/scsi/gdth/0" */
/* format: %-15s\t%-10s\t%-15s\t%s */
/* driver parameters */
size = sprintf(buffer+len,"Driver Parameters:\n");
len += size; pos = begin + len;
if (reserve_list[0] == 0xff)
strcpy(hrec, "--");
else {
hlen = sprintf(hrec, "%d", reserve_list[0]);
for (i = 1; i < MAX_RES_ARGS; i++) {
if (reserve_list[i] == 0xff)
break;
hlen += snprintf(hrec + hlen , 161 - hlen, ",%d", reserve_list[i]);
}
}
size = sprintf(buffer+len,
" reserve_mode: \t%d \treserve_list: \t%s\n",
reserve_mode, hrec);
len += size; pos = begin + len;
size = sprintf(buffer+len,
" max_ids: \t%-3d \thdr_channel: \t%d\n",
max_ids, hdr_channel);
len += size; pos = begin + len;
/* controller information */
size = sprintf(buffer+len,"\nDisk Array Controller Information:\n");
len += size; pos = begin + len;
strcpy(hrec, ha->binfo.type_string);
size = sprintf(buffer+len,
" Number: \t%d \tName: \t%s\n",
ha->hanum, hrec);
len += size; pos = begin + len;
if (ha->more_proc)
sprintf(hrec, "%d.%02d.%02d-%c%03X",
(u8)(ha->binfo.upd_fw_ver>>24),
(u8)(ha->binfo.upd_fw_ver>>16),
(u8)(ha->binfo.upd_fw_ver),
ha->bfeat.raid ? 'R':'N',
ha->binfo.upd_revision);
else
sprintf(hrec, "%d.%02d", (u8)(ha->cpar.version>>8),
(u8)(ha->cpar.version));
size = sprintf(buffer+len,
" Driver Ver.: \t%-10s\tFirmware Ver.: \t%s\n",
GDTH_VERSION_STR, hrec);
len += size; pos = begin + len;
if (ha->more_proc) {
/* more information: 1. about controller */
size = sprintf(buffer+len,
" Serial No.: \t0x%8X\tCache RAM size:\t%d KB\n",
ha->binfo.ser_no, ha->binfo.memsize / 1024);
len += size; pos = begin + len;
}
#ifdef GDTH_DMA_STATISTICS
/* controller statistics */
size = sprintf(buffer+len,"\nController Statistics:\n");
len += size; pos = begin + len;
size = sprintf(buffer+len,
" 32-bit DMA buffer:\t%lu\t64-bit DMA buffer:\t%lu\n",
ha->dma32_cnt, ha->dma64_cnt);
len += size; pos = begin + len;
#endif
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
if (ha->more_proc) {
/* more information: 2. about physical devices */
size = sprintf(buffer+len,"\nPhysical Devices:");
len += size; pos = begin + len;
flag = FALSE;
buf = gdth_ioctl_alloc(ha, GDTH_SCRATCH, FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < ha->bus_cnt; ++i) {
/* 2.a statistics (and retries/reassigns) */
TRACE2(("pdr_statistics() chn %d\n",i));
pds = (gdth_dskstat_str *)(buf + GDTH_SCRATCH/4);
gdtcmd->Service = CACHESERVICE;
gdtcmd->OpCode = GDT_IOCTL;
gdtcmd->u.ioctl.p_param = paddr + GDTH_SCRATCH/4;
gdtcmd->u.ioctl.param_size = 3*GDTH_SCRATCH/4;
gdtcmd->u.ioctl.subfunc = DSK_STATISTICS | L_CTRL_PATTERN;
gdtcmd->u.ioctl.channel = ha->raw[i].address | INVALID_CHANNEL;
pds->bid = ha->raw[i].local_no;
pds->first = 0;
pds->entries = ha->raw[i].pdev_cnt;
cnt = (3*GDTH_SCRATCH/4 - 5 * sizeof(u32)) /
sizeof(pds->list[0]);
if (pds->entries > cnt)
pds->entries = cnt;
if (gdth_execute(host, gdtcmd, cmnd, 30, NULL) != S_OK)
pds->count = 0;
/* other IOCTLs must fit into area GDTH_SCRATCH/4 */
for (j = 0; j < ha->raw[i].pdev_cnt; ++j) {
/* 2.b drive info */
TRACE2(("scsi_drv_info() chn %d dev %d\n",
i, ha->raw[i].id_list[j]));
pdi = (gdth_diskinfo_str *)buf;
gdtcmd->Service = CACHESERVICE;
gdtcmd->OpCode = GDT_IOCTL;
gdtcmd->u.ioctl.p_param = paddr;
gdtcmd->u.ioctl.param_size = sizeof(gdth_diskinfo_str);
gdtcmd->u.ioctl.subfunc = SCSI_DR_INFO | L_CTRL_PATTERN;
gdtcmd->u.ioctl.channel =
ha->raw[i].address | ha->raw[i].id_list[j];
if (gdth_execute(host, gdtcmd, cmnd, 30, NULL) == S_OK) {
strncpy(hrec,pdi->vendor,8);
strncpy(hrec+8,pdi->product,16);
strncpy(hrec+24,pdi->revision,4);
hrec[28] = 0;
size = sprintf(buffer+len,
"\n Chn/ID/LUN: \t%c/%02d/%d \tName: \t%s\n",
'A'+i,pdi->target_id,pdi->lun,hrec);
len += size; pos = begin + len;
flag = TRUE;
pdi->no_ldrive &= 0xffff;
if (pdi->no_ldrive == 0xffff)
strcpy(hrec,"--");
else
sprintf(hrec,"%d",pdi->no_ldrive);
size = sprintf(buffer+len,
" Capacity [MB]:\t%-6d \tTo Log. Drive: \t%s\n",
pdi->blkcnt/(1024*1024/pdi->blksize),
hrec);
len += size; pos = begin + len;
} else {
pdi->devtype = 0xff;
}
if (pdi->devtype == 0) {
/* search retries/reassigns */
for (k = 0; k < pds->count; ++k) {
if (pds->list[k].tid == pdi->target_id &&
pds->list[k].lun == pdi->lun) {
size = sprintf(buffer+len,
" Retries: \t%-6d \tReassigns: \t%d\n",
pds->list[k].retries,
pds->list[k].reassigns);
len += size; pos = begin + len;
break;
}
}
/* 2.c grown defects */
TRACE2(("scsi_drv_defcnt() chn %d dev %d\n",
i, ha->raw[i].id_list[j]));
pdef = (gdth_defcnt_str *)buf;
gdtcmd->Service = CACHESERVICE;
gdtcmd->OpCode = GDT_IOCTL;
gdtcmd->u.ioctl.p_param = paddr;
gdtcmd->u.ioctl.param_size = sizeof(gdth_defcnt_str);
gdtcmd->u.ioctl.subfunc = SCSI_DEF_CNT | L_CTRL_PATTERN;
gdtcmd->u.ioctl.channel =
ha->raw[i].address | ha->raw[i].id_list[j];
pdef->sddc_type = 0x08;
if (gdth_execute(host, gdtcmd, cmnd, 30, NULL) == S_OK) {
size = sprintf(buffer+len,
" Grown Defects:\t%d\n",
pdef->sddc_cnt);
len += size; pos = begin + len;
}
}
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
}
}
gdth_ioctl_free(ha, GDTH_SCRATCH, buf, paddr);
if (!flag) {
size = sprintf(buffer+len, "\n --\n");
len += size; pos = begin + len;
}
/* 3. about logical drives */
size = sprintf(buffer+len,"\nLogical Drives:");
len += size; pos = begin + len;
flag = FALSE;
buf = gdth_ioctl_alloc(ha, GDTH_SCRATCH, FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < MAX_LDRIVES; ++i) {
if (!ha->hdr[i].is_logdrv)
continue;
drv_no = i;
j = k = 0;
is_mirr = FALSE;
do {
/* 3.a log. drive info */
TRACE2(("cache_drv_info() drive no %d\n",drv_no));
pcdi = (gdth_cdrinfo_str *)buf;
gdtcmd->Service = CACHESERVICE;
gdtcmd->OpCode = GDT_IOCTL;
gdtcmd->u.ioctl.p_param = paddr;
gdtcmd->u.ioctl.param_size = sizeof(gdth_cdrinfo_str);
gdtcmd->u.ioctl.subfunc = CACHE_DRV_INFO;
gdtcmd->u.ioctl.channel = drv_no;
if (gdth_execute(host, gdtcmd, cmnd, 30, NULL) != S_OK)
break;
pcdi->ld_dtype >>= 16;
j++;
if (pcdi->ld_dtype > 2) {
strcpy(hrec, "missing");
} else if (pcdi->ld_error & 1) {
strcpy(hrec, "fault");
} else if (pcdi->ld_error & 2) {
strcpy(hrec, "invalid");
k++; j--;
} else {
strcpy(hrec, "ok");
}
if (drv_no == i) {
size = sprintf(buffer+len,
"\n Number: \t%-2d \tStatus: \t%s\n",
drv_no, hrec);
len += size; pos = begin + len;
flag = TRUE;
no_mdrv = pcdi->cd_ldcnt;
if (no_mdrv > 1 || pcdi->ld_slave != -1) {
is_mirr = TRUE;
strcpy(hrec, "RAID-1");
} else if (pcdi->ld_dtype == 0) {
strcpy(hrec, "Disk");
} else if (pcdi->ld_dtype == 1) {
strcpy(hrec, "RAID-0");
} else if (pcdi->ld_dtype == 2) {
strcpy(hrec, "Chain");
} else {
strcpy(hrec, "???");
}
size = sprintf(buffer+len,
" Capacity [MB]:\t%-6d \tType: \t%s\n",
pcdi->ld_blkcnt/(1024*1024/pcdi->ld_blksize),
hrec);
len += size; pos = begin + len;
} else {
size = sprintf(buffer+len,
" Slave Number: \t%-2d \tStatus: \t%s\n",
drv_no & 0x7fff, hrec);
len += size; pos = begin + len;
}
drv_no = pcdi->ld_slave;
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
} while (drv_no != -1);
if (is_mirr) {
size = sprintf(buffer+len,
" Missing Drv.: \t%-2d \tInvalid Drv.: \t%d\n",
no_mdrv - j - k, k);
len += size; pos = begin + len;
}
if (!ha->hdr[i].is_arraydrv)
strcpy(hrec, "--");
else
sprintf(hrec, "%d", ha->hdr[i].master_no);
size = sprintf(buffer+len,
" To Array Drv.:\t%s\n", hrec);
len += size; pos = begin + len;
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
}
gdth_ioctl_free(ha, GDTH_SCRATCH, buf, paddr);
if (!flag) {
size = sprintf(buffer+len, "\n --\n");
len += size; pos = begin + len;
}
/* 4. about array drives */
size = sprintf(buffer+len,"\nArray Drives:");
len += size; pos = begin + len;
flag = FALSE;
buf = gdth_ioctl_alloc(ha, GDTH_SCRATCH, FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < MAX_LDRIVES; ++i) {
if (!(ha->hdr[i].is_arraydrv && ha->hdr[i].is_master))
continue;
/* 4.a array drive info */
TRACE2(("array_info() drive no %d\n",i));
pai = (gdth_arrayinf_str *)buf;
gdtcmd->Service = CACHESERVICE;
gdtcmd->OpCode = GDT_IOCTL;
gdtcmd->u.ioctl.p_param = paddr;
gdtcmd->u.ioctl.param_size = sizeof(gdth_arrayinf_str);
gdtcmd->u.ioctl.subfunc = ARRAY_INFO | LA_CTRL_PATTERN;
gdtcmd->u.ioctl.channel = i;
if (gdth_execute(host, gdtcmd, cmnd, 30, NULL) == S_OK) {
if (pai->ai_state == 0)
strcpy(hrec, "idle");
else if (pai->ai_state == 2)
strcpy(hrec, "build");
else if (pai->ai_state == 4)
strcpy(hrec, "ready");
else if (pai->ai_state == 6)
strcpy(hrec, "fail");
else if (pai->ai_state == 8 || pai->ai_state == 10)
strcpy(hrec, "rebuild");
else
strcpy(hrec, "error");
if (pai->ai_ext_state & 0x10)
strcat(hrec, "/expand");
else if (pai->ai_ext_state & 0x1)
strcat(hrec, "/patch");
size = sprintf(buffer+len,
"\n Number: \t%-2d \tStatus: \t%s\n",
i,hrec);
len += size; pos = begin + len;
flag = TRUE;
if (pai->ai_type == 0)
strcpy(hrec, "RAID-0");
else if (pai->ai_type == 4)
strcpy(hrec, "RAID-4");
else if (pai->ai_type == 5)
strcpy(hrec, "RAID-5");
else
strcpy(hrec, "RAID-10");
size = sprintf(buffer+len,
" Capacity [MB]:\t%-6d \tType: \t%s\n",
pai->ai_size/(1024*1024/pai->ai_secsize),
hrec);
len += size; pos = begin + len;
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
}
}
gdth_ioctl_free(ha, GDTH_SCRATCH, buf, paddr);
if (!flag) {
size = sprintf(buffer+len, "\n --\n");
len += size; pos = begin + len;
}
/* 5. about host drives */
size = sprintf(buffer+len,"\nHost Drives:");
len += size; pos = begin + len;
flag = FALSE;
buf = gdth_ioctl_alloc(ha, sizeof(gdth_hget_str), FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < MAX_LDRIVES; ++i) {
if (!ha->hdr[i].is_logdrv ||
(ha->hdr[i].is_arraydrv && !ha->hdr[i].is_master))
continue;
/* 5.a get host drive list */
TRACE2(("host_get() drv_no %d\n",i));
phg = (gdth_hget_str *)buf;
gdtcmd->Service = CACHESERVICE;
gdtcmd->OpCode = GDT_IOCTL;
gdtcmd->u.ioctl.p_param = paddr;
gdtcmd->u.ioctl.param_size = sizeof(gdth_hget_str);
gdtcmd->u.ioctl.subfunc = HOST_GET | LA_CTRL_PATTERN;
gdtcmd->u.ioctl.channel = i;
phg->entries = MAX_HDRIVES;
phg->offset = GDTOFFSOF(gdth_hget_str, entry[0]);
if (gdth_execute(host, gdtcmd, cmnd, 30, NULL) == S_OK) {
ha->hdr[i].ldr_no = i;
ha->hdr[i].rw_attribs = 0;
ha->hdr[i].start_sec = 0;
} else {
for (j = 0; j < phg->entries; ++j) {
k = phg->entry[j].host_drive;
if (k >= MAX_LDRIVES)
continue;
ha->hdr[k].ldr_no = phg->entry[j].log_drive;
ha->hdr[k].rw_attribs = phg->entry[j].rw_attribs;
ha->hdr[k].start_sec = phg->entry[j].start_sec;
}
}
}
gdth_ioctl_free(ha, sizeof(gdth_hget_str), buf, paddr);
for (i = 0; i < MAX_HDRIVES; ++i) {
if (!(ha->hdr[i].present))
continue;
size = sprintf(buffer+len,
"\n Number: \t%-2d \tArr/Log. Drive:\t%d\n",
i, ha->hdr[i].ldr_no);
len += size; pos = begin + len;
flag = TRUE;
size = sprintf(buffer+len,
" Capacity [MB]:\t%-6d \tStart Sector: \t%d\n",
(u32)(ha->hdr[i].size/2048), ha->hdr[i].start_sec);
len += size; pos = begin + len;
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
}
if (!flag) {
size = sprintf(buffer+len, "\n --\n");
len += size; pos = begin + len;
}
}
/* controller events */
size = sprintf(buffer+len,"\nController Events:\n");
len += size; pos = begin + len;
for (id = -1;;) {
id = gdth_read_event(ha, id, estr);
if (estr->event_source == 0)
break;
if (estr->event_data.eu.driver.ionode == ha->hanum &&
estr->event_source == ES_ASYNC) {
gdth_log_event(&estr->event_data, hrec);
do_gettimeofday(&tv);
sec = (int)(tv.tv_sec - estr->first_stamp);
if (sec < 0) sec = 0;
size = sprintf(buffer+len," date- %02d:%02d:%02d\t%s\n",
sec/3600, sec%3600/60, sec%60, hrec);
len += size; pos = begin + len;
if (pos < offset) {
len = 0;
begin = pos;
}
if (pos > offset + length)
goto stop_output;
}
if (id == -1)
break;
}
stop_output:
*start = buffer +(offset-begin);
len -= (offset-begin);
if (len > length)
len = length;
TRACE2(("get_info() len %d pos %d begin %d offset %d length %d size %d\n",
len,(int)pos,(int)begin,(int)offset,length,size));
rc = len;
free_fail:
kfree(gdtcmd);
kfree(estr);
return rc;
}
static char *gdth_ioctl_alloc(gdth_ha_str *ha, int size, int scratch,
u64 *paddr)
{
unsigned long flags;
char *ret_val;
if (size == 0)
return NULL;
spin_lock_irqsave(&ha->smp_lock, flags);
if (!ha->scratch_busy && size <= GDTH_SCRATCH) {
ha->scratch_busy = TRUE;
ret_val = ha->pscratch;
*paddr = ha->scratch_phys;
} else if (scratch) {
ret_val = NULL;
} else {
dma_addr_t dma_addr;
ret_val = pci_alloc_consistent(ha->pdev, size, &dma_addr);
*paddr = dma_addr;
}
spin_unlock_irqrestore(&ha->smp_lock, flags);
return ret_val;
}
static void gdth_ioctl_free(gdth_ha_str *ha, int size, char *buf, u64 paddr)
{
unsigned long flags;
if (buf == ha->pscratch) {
spin_lock_irqsave(&ha->smp_lock, flags);
ha->scratch_busy = FALSE;
spin_unlock_irqrestore(&ha->smp_lock, flags);
} else {
pci_free_consistent(ha->pdev, size, buf, paddr);
}
}
#ifdef GDTH_IOCTL_PROC
static int gdth_ioctl_check_bin(gdth_ha_str *ha, u16 size)
{
unsigned long flags;
int ret_val;
spin_lock_irqsave(&ha->smp_lock, flags);
ret_val = FALSE;
if (ha->scratch_busy) {
if (((gdth_iord_str *)ha->pscratch)->size == (u32)size)
ret_val = TRUE;
}
spin_unlock_irqrestore(&ha->smp_lock, flags);
return ret_val;
}
#endif
static void gdth_wait_completion(gdth_ha_str *ha, int busnum, int id)
{
unsigned long flags;
int i;
Scsi_Cmnd *scp;
struct gdth_cmndinfo *cmndinfo;
u8 b, t;
spin_lock_irqsave(&ha->smp_lock, flags);
for (i = 0; i < GDTH_MAXCMDS; ++i) {
scp = ha->cmd_tab[i].cmnd;
cmndinfo = gdth_cmnd_priv(scp);
b = scp->device->channel;
t = scp->device->id;
if (!SPECIAL_SCP(scp) && t == (u8)id &&
b == (u8)busnum) {
cmndinfo->wait_for_completion = 0;
spin_unlock_irqrestore(&ha->smp_lock, flags);
while (!cmndinfo->wait_for_completion)
barrier();
spin_lock_irqsave(&ha->smp_lock, flags);
}
}
spin_unlock_irqrestore(&ha->smp_lock, flags);
}
| gpl-2.0 |
lfasnacht/linux-carambola2 | drivers/staging/ozwpan/ozusbsvc.c | 941 | 6682 | /* -----------------------------------------------------------------------------
* Copyright (c) 2011 Ozmo Inc
* Released under the GNU General Public License Version 2 (GPLv2).
*
* This file provides protocol independent part of the implementation of the USB
* service for a PD.
* The implementation of this service is split into two parts the first of which
* is protocol independent and the second contains protocol specific details.
* This split is to allow alternative protocols to be defined.
* The implementation of this service uses ozhcd.c to implement a USB HCD.
* -----------------------------------------------------------------------------
*/
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/sched.h>
#include <linux/netdevice.h>
#include <linux/errno.h>
#include <linux/input.h>
#include <asm/unaligned.h>
#include "ozdbg.h"
#include "ozprotocol.h"
#include "ozeltbuf.h"
#include "ozpd.h"
#include "ozproto.h"
#include "ozusbif.h"
#include "ozhcd.h"
#include "ozusbsvc.h"
/*
* This is called once when the driver is loaded to initialise the USB service.
* Context: process
*/
int oz_usb_init(void)
{
return oz_hcd_init();
}
/*
* This is called once when the driver is unloaded to terminate the USB service.
* Context: process
*/
void oz_usb_term(void)
{
oz_hcd_term();
}
/*
* This is called when the USB service is started or resumed for a PD.
* Context: softirq
*/
int oz_usb_start(struct oz_pd *pd, int resume)
{
int rc = 0;
struct oz_usb_ctx *usb_ctx;
struct oz_usb_ctx *old_ctx;
if (resume) {
oz_dbg(ON, "USB service resumed\n");
return 0;
}
oz_dbg(ON, "USB service started\n");
/* Create a USB context in case we need one. If we find the PD already
* has a USB context then we will destroy it.
*/
usb_ctx = kzalloc(sizeof(struct oz_usb_ctx), GFP_ATOMIC);
if (usb_ctx == NULL)
return -ENOMEM;
atomic_set(&usb_ctx->ref_count, 1);
usb_ctx->pd = pd;
usb_ctx->stopped = 0;
/* Install the USB context if the PD doesn't already have one.
* If it does already have one then destroy the one we have just
* created.
*/
spin_lock_bh(&pd->app_lock[OZ_APPID_USB]);
old_ctx = pd->app_ctx[OZ_APPID_USB];
if (old_ctx == NULL)
pd->app_ctx[OZ_APPID_USB] = usb_ctx;
oz_usb_get(pd->app_ctx[OZ_APPID_USB]);
spin_unlock_bh(&pd->app_lock[OZ_APPID_USB]);
if (old_ctx) {
oz_dbg(ON, "Already have USB context\n");
kfree(usb_ctx);
usb_ctx = old_ctx;
} else if (usb_ctx) {
/* Take a reference to the PD. This will be released when
* the USB context is destroyed.
*/
oz_pd_get(pd);
}
/* If we already had a USB context and had obtained a port from
* the USB HCD then just reset the port. If we didn't have a port
* then report the arrival to the USB HCD so we get one.
*/
if (usb_ctx->hport) {
oz_hcd_pd_reset(usb_ctx, usb_ctx->hport);
} else {
usb_ctx->hport = oz_hcd_pd_arrived(usb_ctx);
if (usb_ctx->hport == NULL) {
oz_dbg(ON, "USB hub returned null port\n");
spin_lock_bh(&pd->app_lock[OZ_APPID_USB]);
pd->app_ctx[OZ_APPID_USB] = NULL;
spin_unlock_bh(&pd->app_lock[OZ_APPID_USB]);
oz_usb_put(usb_ctx);
rc = -1;
}
}
oz_usb_put(usb_ctx);
return rc;
}
/*
* This is called when the USB service is stopped or paused for a PD.
* Context: softirq or process
*/
void oz_usb_stop(struct oz_pd *pd, int pause)
{
struct oz_usb_ctx *usb_ctx;
if (pause) {
oz_dbg(ON, "USB service paused\n");
return;
}
spin_lock_bh(&pd->app_lock[OZ_APPID_USB]);
usb_ctx = (struct oz_usb_ctx *) pd->app_ctx[OZ_APPID_USB];
pd->app_ctx[OZ_APPID_USB] = NULL;
spin_unlock_bh(&pd->app_lock[OZ_APPID_USB]);
if (usb_ctx) {
struct timespec ts, now;
getnstimeofday(&ts);
oz_dbg(ON, "USB service stopping...\n");
usb_ctx->stopped = 1;
/* At this point the reference count on the usb context should
* be 2 - one from when we created it and one from the hcd
* which claims a reference. Since stopped = 1 no one else
* should get in but someone may already be in. So wait
* until they leave but timeout after 1 second.
*/
while ((atomic_read(&usb_ctx->ref_count) > 2)) {
getnstimeofday(&now);
/*Approx 1 Sec. this is not perfect calculation*/
if (now.tv_sec != ts.tv_sec)
break;
}
oz_dbg(ON, "USB service stopped\n");
oz_hcd_pd_departed(usb_ctx->hport);
/* Release the reference taken in oz_usb_start.
*/
oz_usb_put(usb_ctx);
}
}
/*
* This increments the reference count of the context area for a specific PD.
* This ensures this context area does not disappear while still in use.
* Context: softirq
*/
void oz_usb_get(void *hpd)
{
struct oz_usb_ctx *usb_ctx = (struct oz_usb_ctx *)hpd;
atomic_inc(&usb_ctx->ref_count);
}
/*
* This decrements the reference count of the context area for a specific PD
* and destroys the context area if the reference count becomes zero.
* Context: irq or process
*/
void oz_usb_put(void *hpd)
{
struct oz_usb_ctx *usb_ctx = (struct oz_usb_ctx *)hpd;
if (atomic_dec_and_test(&usb_ctx->ref_count)) {
oz_dbg(ON, "Dealloc USB context\n");
oz_pd_put(usb_ctx->pd);
kfree(usb_ctx);
}
}
/*
* Context: softirq
*/
int oz_usb_heartbeat(struct oz_pd *pd)
{
struct oz_usb_ctx *usb_ctx;
int rc = 0;
spin_lock_bh(&pd->app_lock[OZ_APPID_USB]);
usb_ctx = (struct oz_usb_ctx *) pd->app_ctx[OZ_APPID_USB];
if (usb_ctx)
oz_usb_get(usb_ctx);
spin_unlock_bh(&pd->app_lock[OZ_APPID_USB]);
if (usb_ctx == NULL)
return rc;
if (usb_ctx->stopped)
goto done;
if (usb_ctx->hport)
if (oz_hcd_heartbeat(usb_ctx->hport))
rc = 1;
done:
oz_usb_put(usb_ctx);
return rc;
}
/*
* Context: softirq
*/
int oz_usb_stream_create(void *hpd, u8 ep_num)
{
struct oz_usb_ctx *usb_ctx = (struct oz_usb_ctx *)hpd;
struct oz_pd *pd = usb_ctx->pd;
oz_dbg(ON, "%s: (0x%x)\n", __func__, ep_num);
if (pd->mode & OZ_F_ISOC_NO_ELTS) {
oz_isoc_stream_create(pd, ep_num);
} else {
oz_pd_get(pd);
if (oz_elt_stream_create(&pd->elt_buff, ep_num,
4*pd->max_tx_size)) {
oz_pd_put(pd);
return -1;
}
}
return 0;
}
/*
* Context: softirq
*/
int oz_usb_stream_delete(void *hpd, u8 ep_num)
{
struct oz_usb_ctx *usb_ctx = (struct oz_usb_ctx *)hpd;
if (usb_ctx) {
struct oz_pd *pd = usb_ctx->pd;
if (pd) {
oz_dbg(ON, "%s: (0x%x)\n", __func__, ep_num);
if (pd->mode & OZ_F_ISOC_NO_ELTS) {
oz_isoc_stream_delete(pd, ep_num);
} else {
if (oz_elt_stream_delete(&pd->elt_buff, ep_num))
return -1;
oz_pd_put(pd);
}
}
}
return 0;
}
/*
* Context: softirq or process
*/
void oz_usb_request_heartbeat(void *hpd)
{
struct oz_usb_ctx *usb_ctx = (struct oz_usb_ctx *)hpd;
if (usb_ctx && usb_ctx->pd)
oz_pd_request_heartbeat(usb_ctx->pd);
}
| gpl-2.0 |
renesas/onekernel | drivers/media/video/upd64031a.c | 941 | 7600 | /*
* upd64031A - NEC Electronics Ghost Reduction for NTSC in Japan
*
* 2003 by T.Adachi <tadachi@tadachi-net.com>
* 2003 by Takeru KOMORIYA <komoriya@paken.org>
* 2006 by Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/slab.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv.h>
#include <media/upd64031a.h>
/* --------------------- read registers functions define -------------------- */
/* bit masks */
#define GR_MODE_MASK 0xc0
#define DIRECT_3DYCS_CONNECT_MASK 0xc0
#define SYNC_CIRCUIT_MASK 0xa0
/* -------------------------------------------------------------------------- */
MODULE_DESCRIPTION("uPD64031A driver");
MODULE_AUTHOR("T. Adachi, Takeru KOMORIYA, Hans Verkuil");
MODULE_LICENSE("GPL");
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-1)");
enum {
R00 = 0, R01, R02, R03, R04,
R05, R06, R07, R08, R09,
R0A, R0B, R0C, R0D, R0E, R0F,
/* unused registers
R10, R11, R12, R13, R14,
R15, R16, R17,
*/
TOT_REGS
};
struct upd64031a_state {
struct v4l2_subdev sd;
u8 regs[TOT_REGS];
u8 gr_mode;
u8 direct_3dycs_connect;
u8 ext_comp_sync;
u8 ext_vert_sync;
};
static inline struct upd64031a_state *to_state(struct v4l2_subdev *sd)
{
return container_of(sd, struct upd64031a_state, sd);
}
static u8 upd64031a_init[] = {
0x00, 0xb8, 0x48, 0xd2, 0xe6,
0x03, 0x10, 0x0b, 0xaf, 0x7f,
0x00, 0x00, 0x1d, 0x5e, 0x00,
0xd0
};
/* ------------------------------------------------------------------------ */
static u8 upd64031a_read(struct v4l2_subdev *sd, u8 reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 buf[2];
if (reg >= sizeof(buf))
return 0xff;
i2c_master_recv(client, buf, 2);
return buf[reg];
}
/* ------------------------------------------------------------------------ */
static void upd64031a_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 buf[2];
buf[0] = reg;
buf[1] = val;
v4l2_dbg(1, debug, sd, "write reg: %02X val: %02X\n", reg, val);
if (i2c_master_send(client, buf, 2) != 2)
v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val);
}
/* ------------------------------------------------------------------------ */
/* The input changed due to new input or channel changed */
static int upd64031a_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
{
struct upd64031a_state *state = to_state(sd);
u8 reg = state->regs[R00];
v4l2_dbg(1, debug, sd, "changed input or channel\n");
upd64031a_write(sd, R00, reg | 0x10);
upd64031a_write(sd, R00, reg & ~0x10);
return 0;
}
/* ------------------------------------------------------------------------ */
static int upd64031a_s_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct upd64031a_state *state = to_state(sd);
u8 r00, r05, r08;
state->gr_mode = (input & 3) << 6;
state->direct_3dycs_connect = (input & 0xc) << 4;
state->ext_comp_sync =
(input & UPD64031A_COMPOSITE_EXTERNAL) << 1;
state->ext_vert_sync =
(input & UPD64031A_VERTICAL_EXTERNAL) << 2;
r00 = (state->regs[R00] & ~GR_MODE_MASK) | state->gr_mode;
r05 = (state->regs[R00] & ~SYNC_CIRCUIT_MASK) |
state->ext_comp_sync | state->ext_vert_sync;
r08 = (state->regs[R08] & ~DIRECT_3DYCS_CONNECT_MASK) |
state->direct_3dycs_connect;
upd64031a_write(sd, R00, r00);
upd64031a_write(sd, R05, r05);
upd64031a_write(sd, R08, r08);
return upd64031a_s_frequency(sd, NULL);
}
static int upd64031a_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_UPD64031A, 0);
}
static int upd64031a_log_status(struct v4l2_subdev *sd)
{
v4l2_info(sd, "Status: SA00=0x%02x SA01=0x%02x\n",
upd64031a_read(sd, 0), upd64031a_read(sd, 1));
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int upd64031a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (!v4l2_chip_match_i2c_client(client, ®->match))
return -EINVAL;
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
reg->val = upd64031a_read(sd, reg->reg & 0xff);
reg->size = 1;
return 0;
}
static int upd64031a_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (!v4l2_chip_match_i2c_client(client, ®->match))
return -EINVAL;
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
upd64031a_write(sd, reg->reg & 0xff, reg->val & 0xff);
return 0;
}
#endif
/* ----------------------------------------------------------------------- */
static const struct v4l2_subdev_core_ops upd64031a_core_ops = {
.log_status = upd64031a_log_status,
.g_chip_ident = upd64031a_g_chip_ident,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.g_register = upd64031a_g_register,
.s_register = upd64031a_s_register,
#endif
};
static const struct v4l2_subdev_tuner_ops upd64031a_tuner_ops = {
.s_frequency = upd64031a_s_frequency,
};
static const struct v4l2_subdev_video_ops upd64031a_video_ops = {
.s_routing = upd64031a_s_routing,
};
static const struct v4l2_subdev_ops upd64031a_ops = {
.core = &upd64031a_core_ops,
.tuner = &upd64031a_tuner_ops,
.video = &upd64031a_video_ops,
};
/* ------------------------------------------------------------------------ */
/* i2c implementation */
static int upd64031a_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct upd64031a_state *state;
struct v4l2_subdev *sd;
int i;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -EIO;
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
state = kmalloc(sizeof(struct upd64031a_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
sd = &state->sd;
v4l2_i2c_subdev_init(sd, client, &upd64031a_ops);
memcpy(state->regs, upd64031a_init, sizeof(state->regs));
state->gr_mode = UPD64031A_GR_ON << 6;
state->direct_3dycs_connect = UPD64031A_3DYCS_COMPOSITE << 4;
state->ext_comp_sync = state->ext_vert_sync = 0;
for (i = 0; i < TOT_REGS; i++)
upd64031a_write(sd, i, state->regs[i]);
return 0;
}
static int upd64031a_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
v4l2_device_unregister_subdev(sd);
kfree(to_state(sd));
return 0;
}
/* ----------------------------------------------------------------------- */
static const struct i2c_device_id upd64031a_id[] = {
{ "upd64031a", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, upd64031a_id);
static struct v4l2_i2c_driver_data v4l2_i2c_data = {
.name = "upd64031a",
.probe = upd64031a_probe,
.remove = upd64031a_remove,
.id_table = upd64031a_id,
};
| gpl-2.0 |
cile381/android_kernel_m7 | arch/arm/mach-msm/pil-q6v5-lpass.c | 1197 | 5655 | /*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <mach/clk.h>
#include "peripheral-loader.h"
#include "pil-q6v5.h"
#include "scm-pas.h"
#define QDSP6SS_RST_EVB 0x010
#define PROXY_TIMEOUT_MS 10000
static int pil_lpass_enable_clks(struct q6v5_data *drv)
{
int ret;
ret = clk_reset(drv->core_clk, CLK_RESET_DEASSERT);
if (ret)
goto err_reset;
ret = clk_prepare_enable(drv->core_clk);
if (ret)
goto err_core_clk;
ret = clk_prepare_enable(drv->ahb_clk);
if (ret)
goto err_ahb_clk;
ret = clk_prepare_enable(drv->axi_clk);
if (ret)
goto err_axi_clk;
ret = clk_prepare_enable(drv->reg_clk);
if (ret)
goto err_reg_clk;
return 0;
err_reg_clk:
clk_disable_unprepare(drv->axi_clk);
err_axi_clk:
clk_disable_unprepare(drv->ahb_clk);
err_ahb_clk:
clk_disable_unprepare(drv->core_clk);
err_core_clk:
clk_reset(drv->core_clk, CLK_RESET_ASSERT);
err_reset:
return ret;
}
static void pil_lpass_disable_clks(struct q6v5_data *drv)
{
clk_disable_unprepare(drv->reg_clk);
clk_disable_unprepare(drv->axi_clk);
clk_disable_unprepare(drv->ahb_clk);
clk_disable_unprepare(drv->core_clk);
clk_reset(drv->core_clk, CLK_RESET_ASSERT);
}
static int pil_lpass_shutdown(struct pil_desc *pil)
{
struct q6v5_data *drv = dev_get_drvdata(pil->dev);
pil_q6v5_halt_axi_port(pil, drv->axi_halt_base);
/*
* If the shutdown function is called before the reset function, clocks
* will not be enabled yet. Enable them here so that register writes
* performed during the shutdown succeed.
*/
if (drv->is_booted == false)
pil_lpass_enable_clks(drv);
pil_q6v5_shutdown(pil);
pil_lpass_disable_clks(drv);
drv->is_booted = false;
return 0;
}
static int pil_lpass_reset(struct pil_desc *pil)
{
struct q6v5_data *drv = dev_get_drvdata(pil->dev);
int ret;
ret = pil_lpass_enable_clks(drv);
if (ret)
return ret;
/* Program Image Address */
writel_relaxed(((drv->start_addr >> 4) & 0x0FFFFFF0),
drv->reg_base + QDSP6SS_RST_EVB);
ret = pil_q6v5_reset(pil);
if (ret) {
pil_lpass_disable_clks(drv);
return ret;
}
drv->is_booted = true;
return 0;
}
static struct pil_reset_ops pil_lpass_ops = {
.init_image = pil_q6v5_init_image,
.proxy_vote = pil_q6v5_make_proxy_votes,
.proxy_unvote = pil_q6v5_remove_proxy_votes,
.auth_and_reset = pil_lpass_reset,
.shutdown = pil_lpass_shutdown,
};
static int pil_lpass_init_image_trusted(struct pil_desc *pil,
const u8 *metadata, size_t size)
{
return pas_init_image(PAS_Q6, metadata, size);
}
static int pil_lpass_reset_trusted(struct pil_desc *pil)
{
return pas_auth_and_reset(PAS_Q6);
}
static int pil_lpass_shutdown_trusted(struct pil_desc *pil)
{
return pas_shutdown(PAS_Q6);
}
static struct pil_reset_ops pil_lpass_ops_trusted = {
.init_image = pil_lpass_init_image_trusted,
.proxy_vote = pil_q6v5_make_proxy_votes,
.proxy_unvote = pil_q6v5_remove_proxy_votes,
.auth_and_reset = pil_lpass_reset_trusted,
.shutdown = pil_lpass_shutdown_trusted,
};
static int __devinit pil_lpass_driver_probe(struct platform_device *pdev)
{
struct q6v5_data *drv;
struct pil_desc *desc;
desc = pil_q6v5_init(pdev);
if (IS_ERR(desc))
return PTR_ERR(desc);
drv = platform_get_drvdata(pdev);
if (drv == NULL)
return -ENODEV;
desc->ops = &pil_lpass_ops;
desc->owner = THIS_MODULE;
desc->proxy_timeout = PROXY_TIMEOUT_MS;
drv->core_clk = devm_clk_get(&pdev->dev, "core_clk");
if (IS_ERR(drv->core_clk))
return PTR_ERR(drv->core_clk);
drv->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
if (IS_ERR(drv->ahb_clk))
return PTR_ERR(drv->ahb_clk);
drv->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
if (IS_ERR(drv->axi_clk))
return PTR_ERR(drv->axi_clk);
drv->reg_clk = devm_clk_get(&pdev->dev, "reg_clk");
if (IS_ERR(drv->reg_clk))
return PTR_ERR(drv->reg_clk);
if (pas_supported(PAS_Q6) > 0) {
desc->ops = &pil_lpass_ops_trusted;
dev_info(&pdev->dev, "using secure boot\n");
} else {
desc->ops = &pil_lpass_ops;
dev_info(&pdev->dev, "using non-secure boot\n");
}
drv->pil = msm_pil_register(desc);
if (IS_ERR(drv->pil))
return PTR_ERR(drv->pil);
return 0;
}
static int __devexit pil_lpass_driver_exit(struct platform_device *pdev)
{
struct q6v5_data *drv = platform_get_drvdata(pdev);
msm_pil_unregister(drv->pil);
return 0;
}
static struct of_device_id lpass_match_table[] = {
{ .compatible = "qcom,pil-q6v5-lpass" },
{}
};
static struct platform_driver pil_lpass_driver = {
.probe = pil_lpass_driver_probe,
.remove = __devexit_p(pil_lpass_driver_exit),
.driver = {
.name = "pil-q6v5-lpass",
.of_match_table = lpass_match_table,
.owner = THIS_MODULE,
},
};
static int __init pil_lpass_init(void)
{
return platform_driver_register(&pil_lpass_driver);
}
module_init(pil_lpass_init);
static void __exit pil_lpass_exit(void)
{
platform_driver_unregister(&pil_lpass_driver);
}
module_exit(pil_lpass_exit);
MODULE_DESCRIPTION("Support for booting low-power audio subsystems with QDSP6v5 (Hexagon) processors");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
chinaopenx/linux | sound/drivers/mpu401/mpu401_uart.c | 1197 | 16942 | /*
* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
* Routines for control of MPU-401 in UART mode
*
* MPU-401 supports UART mode which is not capable generate transmit
* interrupts thus output is done via polling. Without interrupt,
* input is done also via polling. Do not expect good performance.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* 13-03-2003:
* Added support for different kind of hardware I/O. Build in choices
* are port and mmio. For other kind of I/O, set mpu->read and
* mpu->write to your own I/O functions.
*
*/
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <sound/core.h>
#include <sound/mpu401.h>
MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
MODULE_DESCRIPTION("Routines for control of MPU-401 in UART mode");
MODULE_LICENSE("GPL");
static void snd_mpu401_uart_input_read(struct snd_mpu401 * mpu);
static void snd_mpu401_uart_output_write(struct snd_mpu401 * mpu);
/*
*/
#define snd_mpu401_input_avail(mpu) \
(!(mpu->read(mpu, MPU401C(mpu)) & MPU401_RX_EMPTY))
#define snd_mpu401_output_ready(mpu) \
(!(mpu->read(mpu, MPU401C(mpu)) & MPU401_TX_FULL))
/* Build in lowlevel io */
static void mpu401_write_port(struct snd_mpu401 *mpu, unsigned char data,
unsigned long addr)
{
outb(data, addr);
}
static unsigned char mpu401_read_port(struct snd_mpu401 *mpu,
unsigned long addr)
{
return inb(addr);
}
static void mpu401_write_mmio(struct snd_mpu401 *mpu, unsigned char data,
unsigned long addr)
{
writeb(data, (void __iomem *)addr);
}
static unsigned char mpu401_read_mmio(struct snd_mpu401 *mpu,
unsigned long addr)
{
return readb((void __iomem *)addr);
}
/* */
static void snd_mpu401_uart_clear_rx(struct snd_mpu401 *mpu)
{
int timeout = 100000;
for (; timeout > 0 && snd_mpu401_input_avail(mpu); timeout--)
mpu->read(mpu, MPU401D(mpu));
#ifdef CONFIG_SND_DEBUG
if (timeout <= 0)
snd_printk(KERN_ERR "cmd: clear rx timeout (status = 0x%x)\n",
mpu->read(mpu, MPU401C(mpu)));
#endif
}
static void uart_interrupt_tx(struct snd_mpu401 *mpu)
{
unsigned long flags;
if (test_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode) &&
test_bit(MPU401_MODE_BIT_OUTPUT_TRIGGER, &mpu->mode)) {
spin_lock_irqsave(&mpu->output_lock, flags);
snd_mpu401_uart_output_write(mpu);
spin_unlock_irqrestore(&mpu->output_lock, flags);
}
}
static void _snd_mpu401_uart_interrupt(struct snd_mpu401 *mpu)
{
unsigned long flags;
if (mpu->info_flags & MPU401_INFO_INPUT) {
spin_lock_irqsave(&mpu->input_lock, flags);
if (test_bit(MPU401_MODE_BIT_INPUT, &mpu->mode))
snd_mpu401_uart_input_read(mpu);
else
snd_mpu401_uart_clear_rx(mpu);
spin_unlock_irqrestore(&mpu->input_lock, flags);
}
if (! (mpu->info_flags & MPU401_INFO_TX_IRQ))
/* ok. for better Tx performance try do some output
when input is done */
uart_interrupt_tx(mpu);
}
/**
* snd_mpu401_uart_interrupt - generic MPU401-UART interrupt handler
* @irq: the irq number
* @dev_id: mpu401 instance
*
* Processes the interrupt for MPU401-UART i/o.
*
* Return: %IRQ_HANDLED if the interrupt was handled. %IRQ_NONE otherwise.
*/
irqreturn_t snd_mpu401_uart_interrupt(int irq, void *dev_id)
{
struct snd_mpu401 *mpu = dev_id;
if (mpu == NULL)
return IRQ_NONE;
_snd_mpu401_uart_interrupt(mpu);
return IRQ_HANDLED;
}
EXPORT_SYMBOL(snd_mpu401_uart_interrupt);
/**
* snd_mpu401_uart_interrupt_tx - generic MPU401-UART transmit irq handler
* @irq: the irq number
* @dev_id: mpu401 instance
*
* Processes the interrupt for MPU401-UART output.
*
* Return: %IRQ_HANDLED if the interrupt was handled. %IRQ_NONE otherwise.
*/
irqreturn_t snd_mpu401_uart_interrupt_tx(int irq, void *dev_id)
{
struct snd_mpu401 *mpu = dev_id;
if (mpu == NULL)
return IRQ_NONE;
uart_interrupt_tx(mpu);
return IRQ_HANDLED;
}
EXPORT_SYMBOL(snd_mpu401_uart_interrupt_tx);
/*
* timer callback
* reprogram the timer and call the interrupt job
*/
static void snd_mpu401_uart_timer(unsigned long data)
{
struct snd_mpu401 *mpu = (struct snd_mpu401 *)data;
unsigned long flags;
spin_lock_irqsave(&mpu->timer_lock, flags);
/*mpu->mode |= MPU401_MODE_TIMER;*/
mod_timer(&mpu->timer, 1 + jiffies);
spin_unlock_irqrestore(&mpu->timer_lock, flags);
if (mpu->rmidi)
_snd_mpu401_uart_interrupt(mpu);
}
/*
* initialize the timer callback if not programmed yet
*/
static void snd_mpu401_uart_add_timer (struct snd_mpu401 *mpu, int input)
{
unsigned long flags;
spin_lock_irqsave (&mpu->timer_lock, flags);
if (mpu->timer_invoked == 0) {
setup_timer(&mpu->timer, snd_mpu401_uart_timer,
(unsigned long)mpu);
mod_timer(&mpu->timer, 1 + jiffies);
}
mpu->timer_invoked |= input ? MPU401_MODE_INPUT_TIMER :
MPU401_MODE_OUTPUT_TIMER;
spin_unlock_irqrestore (&mpu->timer_lock, flags);
}
/*
* remove the timer callback if still active
*/
static void snd_mpu401_uart_remove_timer (struct snd_mpu401 *mpu, int input)
{
unsigned long flags;
spin_lock_irqsave (&mpu->timer_lock, flags);
if (mpu->timer_invoked) {
mpu->timer_invoked &= input ? ~MPU401_MODE_INPUT_TIMER :
~MPU401_MODE_OUTPUT_TIMER;
if (! mpu->timer_invoked)
del_timer(&mpu->timer);
}
spin_unlock_irqrestore (&mpu->timer_lock, flags);
}
/*
* send a UART command
* return zero if successful, non-zero for some errors
*/
static int snd_mpu401_uart_cmd(struct snd_mpu401 * mpu, unsigned char cmd,
int ack)
{
unsigned long flags;
int timeout, ok;
spin_lock_irqsave(&mpu->input_lock, flags);
if (mpu->hardware != MPU401_HW_TRID4DWAVE) {
mpu->write(mpu, 0x00, MPU401D(mpu));
/*snd_mpu401_uart_clear_rx(mpu);*/
}
/* ok. standard MPU-401 initialization */
if (mpu->hardware != MPU401_HW_SB) {
for (timeout = 1000; timeout > 0 &&
!snd_mpu401_output_ready(mpu); timeout--)
udelay(10);
#ifdef CONFIG_SND_DEBUG
if (!timeout)
snd_printk(KERN_ERR "cmd: tx timeout (status = 0x%x)\n",
mpu->read(mpu, MPU401C(mpu)));
#endif
}
mpu->write(mpu, cmd, MPU401C(mpu));
if (ack && !(mpu->info_flags & MPU401_INFO_NO_ACK)) {
ok = 0;
timeout = 10000;
while (!ok && timeout-- > 0) {
if (snd_mpu401_input_avail(mpu)) {
if (mpu->read(mpu, MPU401D(mpu)) == MPU401_ACK)
ok = 1;
}
}
if (!ok && mpu->read(mpu, MPU401D(mpu)) == MPU401_ACK)
ok = 1;
} else
ok = 1;
spin_unlock_irqrestore(&mpu->input_lock, flags);
if (!ok) {
snd_printk(KERN_ERR "cmd: 0x%x failed at 0x%lx "
"(status = 0x%x, data = 0x%x)\n", cmd, mpu->port,
mpu->read(mpu, MPU401C(mpu)),
mpu->read(mpu, MPU401D(mpu)));
return 1;
}
return 0;
}
static int snd_mpu401_do_reset(struct snd_mpu401 *mpu)
{
if (snd_mpu401_uart_cmd(mpu, MPU401_RESET, 1))
return -EIO;
if (snd_mpu401_uart_cmd(mpu, MPU401_ENTER_UART, 0))
return -EIO;
return 0;
}
/*
* input/output open/close - protected by open_mutex in rawmidi.c
*/
static int snd_mpu401_uart_input_open(struct snd_rawmidi_substream *substream)
{
struct snd_mpu401 *mpu;
int err;
mpu = substream->rmidi->private_data;
if (mpu->open_input && (err = mpu->open_input(mpu)) < 0)
return err;
if (! test_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode)) {
if (snd_mpu401_do_reset(mpu) < 0)
goto error_out;
}
mpu->substream_input = substream;
set_bit(MPU401_MODE_BIT_INPUT, &mpu->mode);
return 0;
error_out:
if (mpu->open_input && mpu->close_input)
mpu->close_input(mpu);
return -EIO;
}
static int snd_mpu401_uart_output_open(struct snd_rawmidi_substream *substream)
{
struct snd_mpu401 *mpu;
int err;
mpu = substream->rmidi->private_data;
if (mpu->open_output && (err = mpu->open_output(mpu)) < 0)
return err;
if (! test_bit(MPU401_MODE_BIT_INPUT, &mpu->mode)) {
if (snd_mpu401_do_reset(mpu) < 0)
goto error_out;
}
mpu->substream_output = substream;
set_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode);
return 0;
error_out:
if (mpu->open_output && mpu->close_output)
mpu->close_output(mpu);
return -EIO;
}
static int snd_mpu401_uart_input_close(struct snd_rawmidi_substream *substream)
{
struct snd_mpu401 *mpu;
int err = 0;
mpu = substream->rmidi->private_data;
clear_bit(MPU401_MODE_BIT_INPUT, &mpu->mode);
mpu->substream_input = NULL;
if (! test_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode))
err = snd_mpu401_uart_cmd(mpu, MPU401_RESET, 0);
if (mpu->close_input)
mpu->close_input(mpu);
if (err)
return -EIO;
return 0;
}
static int snd_mpu401_uart_output_close(struct snd_rawmidi_substream *substream)
{
struct snd_mpu401 *mpu;
int err = 0;
mpu = substream->rmidi->private_data;
clear_bit(MPU401_MODE_BIT_OUTPUT, &mpu->mode);
mpu->substream_output = NULL;
if (! test_bit(MPU401_MODE_BIT_INPUT, &mpu->mode))
err = snd_mpu401_uart_cmd(mpu, MPU401_RESET, 0);
if (mpu->close_output)
mpu->close_output(mpu);
if (err)
return -EIO;
return 0;
}
/*
* trigger input callback
*/
static void
snd_mpu401_uart_input_trigger(struct snd_rawmidi_substream *substream, int up)
{
unsigned long flags;
struct snd_mpu401 *mpu;
int max = 64;
mpu = substream->rmidi->private_data;
if (up) {
if (! test_and_set_bit(MPU401_MODE_BIT_INPUT_TRIGGER,
&mpu->mode)) {
/* first time - flush FIFO */
while (max-- > 0)
mpu->read(mpu, MPU401D(mpu));
if (mpu->info_flags & MPU401_INFO_USE_TIMER)
snd_mpu401_uart_add_timer(mpu, 1);
}
/* read data in advance */
spin_lock_irqsave(&mpu->input_lock, flags);
snd_mpu401_uart_input_read(mpu);
spin_unlock_irqrestore(&mpu->input_lock, flags);
} else {
if (mpu->info_flags & MPU401_INFO_USE_TIMER)
snd_mpu401_uart_remove_timer(mpu, 1);
clear_bit(MPU401_MODE_BIT_INPUT_TRIGGER, &mpu->mode);
}
}
/*
* transfer input pending data
* call with input_lock spinlock held
*/
static void snd_mpu401_uart_input_read(struct snd_mpu401 * mpu)
{
int max = 128;
unsigned char byte;
while (max-- > 0) {
if (! snd_mpu401_input_avail(mpu))
break; /* input not available */
byte = mpu->read(mpu, MPU401D(mpu));
if (test_bit(MPU401_MODE_BIT_INPUT_TRIGGER, &mpu->mode))
snd_rawmidi_receive(mpu->substream_input, &byte, 1);
}
}
/*
* Tx FIFO sizes:
* CS4237B - 16 bytes
* AudioDrive ES1688 - 12 bytes
* S3 SonicVibes - 8 bytes
* SoundBlaster AWE 64 - 2 bytes (ugly hardware)
*/
/*
* write output pending bytes
* call with output_lock spinlock held
*/
static void snd_mpu401_uart_output_write(struct snd_mpu401 * mpu)
{
unsigned char byte;
int max = 256;
do {
if (snd_rawmidi_transmit_peek(mpu->substream_output,
&byte, 1) == 1) {
/*
* Try twice because there is hardware that insists on
* setting the output busy bit after each write.
*/
if (!snd_mpu401_output_ready(mpu) &&
!snd_mpu401_output_ready(mpu))
break; /* Tx FIFO full - try again later */
mpu->write(mpu, byte, MPU401D(mpu));
snd_rawmidi_transmit_ack(mpu->substream_output, 1);
} else {
snd_mpu401_uart_remove_timer (mpu, 0);
break; /* no other data - leave the tx loop */
}
} while (--max > 0);
}
/*
* output trigger callback
*/
static void
snd_mpu401_uart_output_trigger(struct snd_rawmidi_substream *substream, int up)
{
unsigned long flags;
struct snd_mpu401 *mpu;
mpu = substream->rmidi->private_data;
if (up) {
set_bit(MPU401_MODE_BIT_OUTPUT_TRIGGER, &mpu->mode);
/* try to add the timer at each output trigger,
* since the output timer might have been removed in
* snd_mpu401_uart_output_write().
*/
if (! (mpu->info_flags & MPU401_INFO_TX_IRQ))
snd_mpu401_uart_add_timer(mpu, 0);
/* output pending data */
spin_lock_irqsave(&mpu->output_lock, flags);
snd_mpu401_uart_output_write(mpu);
spin_unlock_irqrestore(&mpu->output_lock, flags);
} else {
if (! (mpu->info_flags & MPU401_INFO_TX_IRQ))
snd_mpu401_uart_remove_timer(mpu, 0);
clear_bit(MPU401_MODE_BIT_OUTPUT_TRIGGER, &mpu->mode);
}
}
/*
*/
static struct snd_rawmidi_ops snd_mpu401_uart_output =
{
.open = snd_mpu401_uart_output_open,
.close = snd_mpu401_uart_output_close,
.trigger = snd_mpu401_uart_output_trigger,
};
static struct snd_rawmidi_ops snd_mpu401_uart_input =
{
.open = snd_mpu401_uart_input_open,
.close = snd_mpu401_uart_input_close,
.trigger = snd_mpu401_uart_input_trigger,
};
static void snd_mpu401_uart_free(struct snd_rawmidi *rmidi)
{
struct snd_mpu401 *mpu = rmidi->private_data;
if (mpu->irq >= 0)
free_irq(mpu->irq, (void *) mpu);
release_and_free_resource(mpu->res);
kfree(mpu);
}
/**
* snd_mpu401_uart_new - create an MPU401-UART instance
* @card: the card instance
* @device: the device index, zero-based
* @hardware: the hardware type, MPU401_HW_XXXX
* @port: the base address of MPU401 port
* @info_flags: bitflags MPU401_INFO_XXX
* @irq: the ISA irq number, -1 if not to be allocated
* @rrawmidi: the pointer to store the new rawmidi instance
*
* Creates a new MPU-401 instance.
*
* Note that the rawmidi instance is returned on the rrawmidi argument,
* not the mpu401 instance itself. To access to the mpu401 instance,
* cast from rawmidi->private_data (with struct snd_mpu401 magic-cast).
*
* Return: Zero if successful, or a negative error code.
*/
int snd_mpu401_uart_new(struct snd_card *card, int device,
unsigned short hardware,
unsigned long port,
unsigned int info_flags,
int irq,
struct snd_rawmidi ** rrawmidi)
{
struct snd_mpu401 *mpu;
struct snd_rawmidi *rmidi;
int in_enable, out_enable;
int err;
if (rrawmidi)
*rrawmidi = NULL;
if (! (info_flags & (MPU401_INFO_INPUT | MPU401_INFO_OUTPUT)))
info_flags |= MPU401_INFO_INPUT | MPU401_INFO_OUTPUT;
in_enable = (info_flags & MPU401_INFO_INPUT) ? 1 : 0;
out_enable = (info_flags & MPU401_INFO_OUTPUT) ? 1 : 0;
if ((err = snd_rawmidi_new(card, "MPU-401U", device,
out_enable, in_enable, &rmidi)) < 0)
return err;
mpu = kzalloc(sizeof(*mpu), GFP_KERNEL);
if (mpu == NULL) {
snd_printk(KERN_ERR "mpu401_uart: cannot allocate\n");
snd_device_free(card, rmidi);
return -ENOMEM;
}
rmidi->private_data = mpu;
rmidi->private_free = snd_mpu401_uart_free;
spin_lock_init(&mpu->input_lock);
spin_lock_init(&mpu->output_lock);
spin_lock_init(&mpu->timer_lock);
mpu->hardware = hardware;
mpu->irq = -1;
if (! (info_flags & MPU401_INFO_INTEGRATED)) {
int res_size = hardware == MPU401_HW_PC98II ? 4 : 2;
mpu->res = request_region(port, res_size, "MPU401 UART");
if (mpu->res == NULL) {
snd_printk(KERN_ERR "mpu401_uart: "
"unable to grab port 0x%lx size %d\n",
port, res_size);
snd_device_free(card, rmidi);
return -EBUSY;
}
}
if (info_flags & MPU401_INFO_MMIO) {
mpu->write = mpu401_write_mmio;
mpu->read = mpu401_read_mmio;
} else {
mpu->write = mpu401_write_port;
mpu->read = mpu401_read_port;
}
mpu->port = port;
if (hardware == MPU401_HW_PC98II)
mpu->cport = port + 2;
else
mpu->cport = port + 1;
if (irq >= 0) {
if (request_irq(irq, snd_mpu401_uart_interrupt, 0,
"MPU401 UART", (void *) mpu)) {
snd_printk(KERN_ERR "mpu401_uart: "
"unable to grab IRQ %d\n", irq);
snd_device_free(card, rmidi);
return -EBUSY;
}
}
if (irq < 0 && !(info_flags & MPU401_INFO_IRQ_HOOK))
info_flags |= MPU401_INFO_USE_TIMER;
mpu->info_flags = info_flags;
mpu->irq = irq;
if (card->shortname[0])
snprintf(rmidi->name, sizeof(rmidi->name), "%s MIDI",
card->shortname);
else
sprintf(rmidi->name, "MPU-401 MIDI %d-%d",card->number, device);
if (out_enable) {
snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
&snd_mpu401_uart_output);
rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT;
}
if (in_enable) {
snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
&snd_mpu401_uart_input);
rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
if (out_enable)
rmidi->info_flags |= SNDRV_RAWMIDI_INFO_DUPLEX;
}
mpu->rmidi = rmidi;
if (rrawmidi)
*rrawmidi = rmidi;
return 0;
}
EXPORT_SYMBOL(snd_mpu401_uart_new);
/*
* INIT part
*/
static int __init alsa_mpu401_uart_init(void)
{
return 0;
}
static void __exit alsa_mpu401_uart_exit(void)
{
}
module_init(alsa_mpu401_uart_init)
module_exit(alsa_mpu401_uart_exit)
| gpl-2.0 |
emceethemouth/kernel_android | net/rxrpc/af_rxrpc.c | 1453 | 21015 | /* AF_RXRPC implementation
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/net.h>
#include <linux/slab.h>
#include <linux/skbuff.h>
#include <linux/poll.h>
#include <linux/proc_fs.h>
#include <linux/key-type.h>
#include <net/net_namespace.h>
#include <net/sock.h>
#include <net/af_rxrpc.h>
#include "ar-internal.h"
MODULE_DESCRIPTION("RxRPC network protocol");
MODULE_AUTHOR("Red Hat, Inc.");
MODULE_LICENSE("GPL");
MODULE_ALIAS_NETPROTO(PF_RXRPC);
unsigned int rxrpc_debug; // = RXRPC_DEBUG_KPROTO;
module_param_named(debug, rxrpc_debug, uint, S_IWUSR | S_IRUGO);
MODULE_PARM_DESC(debug, "RxRPC debugging mask");
static int sysctl_rxrpc_max_qlen __read_mostly = 10;
static struct proto rxrpc_proto;
static const struct proto_ops rxrpc_rpc_ops;
/* local epoch for detecting local-end reset */
__be32 rxrpc_epoch;
/* current debugging ID */
atomic_t rxrpc_debug_id;
/* count of skbs currently in use */
atomic_t rxrpc_n_skbs;
struct workqueue_struct *rxrpc_workqueue;
static void rxrpc_sock_destructor(struct sock *);
/*
* see if an RxRPC socket is currently writable
*/
static inline int rxrpc_writable(struct sock *sk)
{
return atomic_read(&sk->sk_wmem_alloc) < (size_t) sk->sk_sndbuf;
}
/*
* wait for write bufferage to become available
*/
static void rxrpc_write_space(struct sock *sk)
{
_enter("%p", sk);
rcu_read_lock();
if (rxrpc_writable(sk)) {
struct socket_wq *wq = rcu_dereference(sk->sk_wq);
if (wq_has_sleeper(wq))
wake_up_interruptible(&wq->wait);
sk_wake_async(sk, SOCK_WAKE_SPACE, POLL_OUT);
}
rcu_read_unlock();
}
/*
* validate an RxRPC address
*/
static int rxrpc_validate_address(struct rxrpc_sock *rx,
struct sockaddr_rxrpc *srx,
int len)
{
if (len < sizeof(struct sockaddr_rxrpc))
return -EINVAL;
if (srx->srx_family != AF_RXRPC)
return -EAFNOSUPPORT;
if (srx->transport_type != SOCK_DGRAM)
return -ESOCKTNOSUPPORT;
len -= offsetof(struct sockaddr_rxrpc, transport);
if (srx->transport_len < sizeof(sa_family_t) ||
srx->transport_len > len)
return -EINVAL;
if (srx->transport.family != rx->proto)
return -EAFNOSUPPORT;
switch (srx->transport.family) {
case AF_INET:
_debug("INET: %x @ %pI4",
ntohs(srx->transport.sin.sin_port),
&srx->transport.sin.sin_addr);
if (srx->transport_len > 8)
memset((void *)&srx->transport + 8, 0,
srx->transport_len - 8);
break;
case AF_INET6:
default:
return -EAFNOSUPPORT;
}
return 0;
}
/*
* bind a local address to an RxRPC socket
*/
static int rxrpc_bind(struct socket *sock, struct sockaddr *saddr, int len)
{
struct sockaddr_rxrpc *srx = (struct sockaddr_rxrpc *) saddr;
struct sock *sk = sock->sk;
struct rxrpc_local *local;
struct rxrpc_sock *rx = rxrpc_sk(sk), *prx;
__be16 service_id;
int ret;
_enter("%p,%p,%d", rx, saddr, len);
ret = rxrpc_validate_address(rx, srx, len);
if (ret < 0)
goto error;
lock_sock(&rx->sk);
if (rx->sk.sk_state != RXRPC_UNCONNECTED) {
ret = -EINVAL;
goto error_unlock;
}
memcpy(&rx->srx, srx, sizeof(rx->srx));
/* find a local transport endpoint if we don't have one already */
local = rxrpc_lookup_local(&rx->srx);
if (IS_ERR(local)) {
ret = PTR_ERR(local);
goto error_unlock;
}
rx->local = local;
if (srx->srx_service) {
service_id = htons(srx->srx_service);
write_lock_bh(&local->services_lock);
list_for_each_entry(prx, &local->services, listen_link) {
if (prx->service_id == service_id)
goto service_in_use;
}
rx->service_id = service_id;
list_add_tail(&rx->listen_link, &local->services);
write_unlock_bh(&local->services_lock);
rx->sk.sk_state = RXRPC_SERVER_BOUND;
} else {
rx->sk.sk_state = RXRPC_CLIENT_BOUND;
}
release_sock(&rx->sk);
_leave(" = 0");
return 0;
service_in_use:
ret = -EADDRINUSE;
write_unlock_bh(&local->services_lock);
error_unlock:
release_sock(&rx->sk);
error:
_leave(" = %d", ret);
return ret;
}
/*
* set the number of pending calls permitted on a listening socket
*/
static int rxrpc_listen(struct socket *sock, int backlog)
{
struct sock *sk = sock->sk;
struct rxrpc_sock *rx = rxrpc_sk(sk);
int ret;
_enter("%p,%d", rx, backlog);
lock_sock(&rx->sk);
switch (rx->sk.sk_state) {
case RXRPC_UNCONNECTED:
ret = -EADDRNOTAVAIL;
break;
case RXRPC_CLIENT_BOUND:
case RXRPC_CLIENT_CONNECTED:
default:
ret = -EBUSY;
break;
case RXRPC_SERVER_BOUND:
ASSERT(rx->local != NULL);
sk->sk_max_ack_backlog = backlog;
rx->sk.sk_state = RXRPC_SERVER_LISTENING;
ret = 0;
break;
}
release_sock(&rx->sk);
_leave(" = %d", ret);
return ret;
}
/*
* find a transport by address
*/
static struct rxrpc_transport *rxrpc_name_to_transport(struct socket *sock,
struct sockaddr *addr,
int addr_len, int flags,
gfp_t gfp)
{
struct sockaddr_rxrpc *srx = (struct sockaddr_rxrpc *) addr;
struct rxrpc_transport *trans;
struct rxrpc_sock *rx = rxrpc_sk(sock->sk);
struct rxrpc_peer *peer;
_enter("%p,%p,%d,%d", rx, addr, addr_len, flags);
ASSERT(rx->local != NULL);
ASSERT(rx->sk.sk_state > RXRPC_UNCONNECTED);
if (rx->srx.transport_type != srx->transport_type)
return ERR_PTR(-ESOCKTNOSUPPORT);
if (rx->srx.transport.family != srx->transport.family)
return ERR_PTR(-EAFNOSUPPORT);
/* find a remote transport endpoint from the local one */
peer = rxrpc_get_peer(srx, gfp);
if (IS_ERR(peer))
return ERR_CAST(peer);
/* find a transport */
trans = rxrpc_get_transport(rx->local, peer, gfp);
rxrpc_put_peer(peer);
_leave(" = %p", trans);
return trans;
}
/**
* rxrpc_kernel_begin_call - Allow a kernel service to begin a call
* @sock: The socket on which to make the call
* @srx: The address of the peer to contact (defaults to socket setting)
* @key: The security context to use (defaults to socket setting)
* @user_call_ID: The ID to use
*
* Allow a kernel service to begin a call on the nominated socket. This just
* sets up all the internal tracking structures and allocates connection and
* call IDs as appropriate. The call to be used is returned.
*
* The default socket destination address and security may be overridden by
* supplying @srx and @key.
*/
struct rxrpc_call *rxrpc_kernel_begin_call(struct socket *sock,
struct sockaddr_rxrpc *srx,
struct key *key,
unsigned long user_call_ID,
gfp_t gfp)
{
struct rxrpc_conn_bundle *bundle;
struct rxrpc_transport *trans;
struct rxrpc_call *call;
struct rxrpc_sock *rx = rxrpc_sk(sock->sk);
__be16 service_id;
_enter(",,%x,%lx", key_serial(key), user_call_ID);
lock_sock(&rx->sk);
if (srx) {
trans = rxrpc_name_to_transport(sock, (struct sockaddr *) srx,
sizeof(*srx), 0, gfp);
if (IS_ERR(trans)) {
call = ERR_CAST(trans);
trans = NULL;
goto out_notrans;
}
} else {
trans = rx->trans;
if (!trans) {
call = ERR_PTR(-ENOTCONN);
goto out_notrans;
}
atomic_inc(&trans->usage);
}
service_id = rx->service_id;
if (srx)
service_id = htons(srx->srx_service);
if (!key)
key = rx->key;
if (key && !key->payload.data)
key = NULL; /* a no-security key */
bundle = rxrpc_get_bundle(rx, trans, key, service_id, gfp);
if (IS_ERR(bundle)) {
call = ERR_CAST(bundle);
goto out;
}
call = rxrpc_get_client_call(rx, trans, bundle, user_call_ID, true,
gfp);
rxrpc_put_bundle(trans, bundle);
out:
rxrpc_put_transport(trans);
out_notrans:
release_sock(&rx->sk);
_leave(" = %p", call);
return call;
}
EXPORT_SYMBOL(rxrpc_kernel_begin_call);
/**
* rxrpc_kernel_end_call - Allow a kernel service to end a call it was using
* @call: The call to end
*
* Allow a kernel service to end a call it was using. The call must be
* complete before this is called (the call should be aborted if necessary).
*/
void rxrpc_kernel_end_call(struct rxrpc_call *call)
{
_enter("%d{%d}", call->debug_id, atomic_read(&call->usage));
rxrpc_remove_user_ID(call->socket, call);
rxrpc_put_call(call);
}
EXPORT_SYMBOL(rxrpc_kernel_end_call);
/**
* rxrpc_kernel_intercept_rx_messages - Intercept received RxRPC messages
* @sock: The socket to intercept received messages on
* @interceptor: The function to pass the messages to
*
* Allow a kernel service to intercept messages heading for the Rx queue on an
* RxRPC socket. They get passed to the specified function instead.
* @interceptor should free the socket buffers it is given. @interceptor is
* called with the socket receive queue spinlock held and softirqs disabled -
* this ensures that the messages will be delivered in the right order.
*/
void rxrpc_kernel_intercept_rx_messages(struct socket *sock,
rxrpc_interceptor_t interceptor)
{
struct rxrpc_sock *rx = rxrpc_sk(sock->sk);
_enter("");
rx->interceptor = interceptor;
}
EXPORT_SYMBOL(rxrpc_kernel_intercept_rx_messages);
/*
* connect an RxRPC socket
* - this just targets it at a specific destination; no actual connection
* negotiation takes place
*/
static int rxrpc_connect(struct socket *sock, struct sockaddr *addr,
int addr_len, int flags)
{
struct sockaddr_rxrpc *srx = (struct sockaddr_rxrpc *) addr;
struct sock *sk = sock->sk;
struct rxrpc_transport *trans;
struct rxrpc_local *local;
struct rxrpc_sock *rx = rxrpc_sk(sk);
int ret;
_enter("%p,%p,%d,%d", rx, addr, addr_len, flags);
ret = rxrpc_validate_address(rx, srx, addr_len);
if (ret < 0) {
_leave(" = %d [bad addr]", ret);
return ret;
}
lock_sock(&rx->sk);
switch (rx->sk.sk_state) {
case RXRPC_UNCONNECTED:
/* find a local transport endpoint if we don't have one already */
ASSERTCMP(rx->local, ==, NULL);
rx->srx.srx_family = AF_RXRPC;
rx->srx.srx_service = 0;
rx->srx.transport_type = srx->transport_type;
rx->srx.transport_len = sizeof(sa_family_t);
rx->srx.transport.family = srx->transport.family;
local = rxrpc_lookup_local(&rx->srx);
if (IS_ERR(local)) {
release_sock(&rx->sk);
return PTR_ERR(local);
}
rx->local = local;
rx->sk.sk_state = RXRPC_CLIENT_BOUND;
case RXRPC_CLIENT_BOUND:
break;
case RXRPC_CLIENT_CONNECTED:
release_sock(&rx->sk);
return -EISCONN;
default:
release_sock(&rx->sk);
return -EBUSY; /* server sockets can't connect as well */
}
trans = rxrpc_name_to_transport(sock, addr, addr_len, flags,
GFP_KERNEL);
if (IS_ERR(trans)) {
release_sock(&rx->sk);
_leave(" = %ld", PTR_ERR(trans));
return PTR_ERR(trans);
}
rx->trans = trans;
rx->service_id = htons(srx->srx_service);
rx->sk.sk_state = RXRPC_CLIENT_CONNECTED;
release_sock(&rx->sk);
return 0;
}
/*
* send a message through an RxRPC socket
* - in a client this does a number of things:
* - finds/sets up a connection for the security specified (if any)
* - initiates a call (ID in control data)
* - ends the request phase of a call (if MSG_MORE is not set)
* - sends a call data packet
* - may send an abort (abort code in control data)
*/
static int rxrpc_sendmsg(struct kiocb *iocb, struct socket *sock,
struct msghdr *m, size_t len)
{
struct rxrpc_transport *trans;
struct rxrpc_sock *rx = rxrpc_sk(sock->sk);
int ret;
_enter(",{%d},,%zu", rx->sk.sk_state, len);
if (m->msg_flags & MSG_OOB)
return -EOPNOTSUPP;
if (m->msg_name) {
ret = rxrpc_validate_address(rx, m->msg_name, m->msg_namelen);
if (ret < 0) {
_leave(" = %d [bad addr]", ret);
return ret;
}
}
trans = NULL;
lock_sock(&rx->sk);
if (m->msg_name) {
ret = -EISCONN;
trans = rxrpc_name_to_transport(sock, m->msg_name,
m->msg_namelen, 0, GFP_KERNEL);
if (IS_ERR(trans)) {
ret = PTR_ERR(trans);
trans = NULL;
goto out;
}
} else {
trans = rx->trans;
if (trans)
atomic_inc(&trans->usage);
}
switch (rx->sk.sk_state) {
case RXRPC_SERVER_LISTENING:
if (!m->msg_name) {
ret = rxrpc_server_sendmsg(iocb, rx, m, len);
break;
}
case RXRPC_SERVER_BOUND:
case RXRPC_CLIENT_BOUND:
if (!m->msg_name) {
ret = -ENOTCONN;
break;
}
case RXRPC_CLIENT_CONNECTED:
ret = rxrpc_client_sendmsg(iocb, rx, trans, m, len);
break;
default:
ret = -ENOTCONN;
break;
}
out:
release_sock(&rx->sk);
if (trans)
rxrpc_put_transport(trans);
_leave(" = %d", ret);
return ret;
}
/*
* set RxRPC socket options
*/
static int rxrpc_setsockopt(struct socket *sock, int level, int optname,
char __user *optval, unsigned int optlen)
{
struct rxrpc_sock *rx = rxrpc_sk(sock->sk);
unsigned int min_sec_level;
int ret;
_enter(",%d,%d,,%d", level, optname, optlen);
lock_sock(&rx->sk);
ret = -EOPNOTSUPP;
if (level == SOL_RXRPC) {
switch (optname) {
case RXRPC_EXCLUSIVE_CONNECTION:
ret = -EINVAL;
if (optlen != 0)
goto error;
ret = -EISCONN;
if (rx->sk.sk_state != RXRPC_UNCONNECTED)
goto error;
set_bit(RXRPC_SOCK_EXCLUSIVE_CONN, &rx->flags);
goto success;
case RXRPC_SECURITY_KEY:
ret = -EINVAL;
if (rx->key)
goto error;
ret = -EISCONN;
if (rx->sk.sk_state != RXRPC_UNCONNECTED)
goto error;
ret = rxrpc_request_key(rx, optval, optlen);
goto error;
case RXRPC_SECURITY_KEYRING:
ret = -EINVAL;
if (rx->key)
goto error;
ret = -EISCONN;
if (rx->sk.sk_state != RXRPC_UNCONNECTED)
goto error;
ret = rxrpc_server_keyring(rx, optval, optlen);
goto error;
case RXRPC_MIN_SECURITY_LEVEL:
ret = -EINVAL;
if (optlen != sizeof(unsigned int))
goto error;
ret = -EISCONN;
if (rx->sk.sk_state != RXRPC_UNCONNECTED)
goto error;
ret = get_user(min_sec_level,
(unsigned int __user *) optval);
if (ret < 0)
goto error;
ret = -EINVAL;
if (min_sec_level > RXRPC_SECURITY_MAX)
goto error;
rx->min_sec_level = min_sec_level;
goto success;
default:
break;
}
}
success:
ret = 0;
error:
release_sock(&rx->sk);
return ret;
}
/*
* permit an RxRPC socket to be polled
*/
static unsigned int rxrpc_poll(struct file *file, struct socket *sock,
poll_table *wait)
{
unsigned int mask;
struct sock *sk = sock->sk;
sock_poll_wait(file, sk_sleep(sk), wait);
mask = 0;
/* the socket is readable if there are any messages waiting on the Rx
* queue */
if (!skb_queue_empty(&sk->sk_receive_queue))
mask |= POLLIN | POLLRDNORM;
/* the socket is writable if there is space to add new data to the
* socket; there is no guarantee that any particular call in progress
* on the socket may have space in the Tx ACK window */
if (rxrpc_writable(sk))
mask |= POLLOUT | POLLWRNORM;
return mask;
}
/*
* create an RxRPC socket
*/
static int rxrpc_create(struct net *net, struct socket *sock, int protocol,
int kern)
{
struct rxrpc_sock *rx;
struct sock *sk;
_enter("%p,%d", sock, protocol);
if (!net_eq(net, &init_net))
return -EAFNOSUPPORT;
/* we support transport protocol UDP only */
if (protocol != PF_INET)
return -EPROTONOSUPPORT;
if (sock->type != SOCK_DGRAM)
return -ESOCKTNOSUPPORT;
sock->ops = &rxrpc_rpc_ops;
sock->state = SS_UNCONNECTED;
sk = sk_alloc(net, PF_RXRPC, GFP_KERNEL, &rxrpc_proto);
if (!sk)
return -ENOMEM;
sock_init_data(sock, sk);
sk->sk_state = RXRPC_UNCONNECTED;
sk->sk_write_space = rxrpc_write_space;
sk->sk_max_ack_backlog = sysctl_rxrpc_max_qlen;
sk->sk_destruct = rxrpc_sock_destructor;
rx = rxrpc_sk(sk);
rx->proto = protocol;
rx->calls = RB_ROOT;
INIT_LIST_HEAD(&rx->listen_link);
INIT_LIST_HEAD(&rx->secureq);
INIT_LIST_HEAD(&rx->acceptq);
rwlock_init(&rx->call_lock);
memset(&rx->srx, 0, sizeof(rx->srx));
_leave(" = 0 [%p]", rx);
return 0;
}
/*
* RxRPC socket destructor
*/
static void rxrpc_sock_destructor(struct sock *sk)
{
_enter("%p", sk);
rxrpc_purge_queue(&sk->sk_receive_queue);
WARN_ON(atomic_read(&sk->sk_wmem_alloc));
WARN_ON(!sk_unhashed(sk));
WARN_ON(sk->sk_socket);
if (!sock_flag(sk, SOCK_DEAD)) {
printk("Attempt to release alive rxrpc socket: %p\n", sk);
return;
}
}
/*
* release an RxRPC socket
*/
static int rxrpc_release_sock(struct sock *sk)
{
struct rxrpc_sock *rx = rxrpc_sk(sk);
_enter("%p{%d,%d}", sk, sk->sk_state, atomic_read(&sk->sk_refcnt));
/* declare the socket closed for business */
sock_orphan(sk);
sk->sk_shutdown = SHUTDOWN_MASK;
spin_lock_bh(&sk->sk_receive_queue.lock);
sk->sk_state = RXRPC_CLOSE;
spin_unlock_bh(&sk->sk_receive_queue.lock);
ASSERTCMP(rx->listen_link.next, !=, LIST_POISON1);
if (!list_empty(&rx->listen_link)) {
write_lock_bh(&rx->local->services_lock);
list_del(&rx->listen_link);
write_unlock_bh(&rx->local->services_lock);
}
/* try to flush out this socket */
rxrpc_release_calls_on_socket(rx);
flush_workqueue(rxrpc_workqueue);
rxrpc_purge_queue(&sk->sk_receive_queue);
if (rx->conn) {
rxrpc_put_connection(rx->conn);
rx->conn = NULL;
}
if (rx->bundle) {
rxrpc_put_bundle(rx->trans, rx->bundle);
rx->bundle = NULL;
}
if (rx->trans) {
rxrpc_put_transport(rx->trans);
rx->trans = NULL;
}
if (rx->local) {
rxrpc_put_local(rx->local);
rx->local = NULL;
}
key_put(rx->key);
rx->key = NULL;
key_put(rx->securities);
rx->securities = NULL;
sock_put(sk);
_leave(" = 0");
return 0;
}
/*
* release an RxRPC BSD socket on close() or equivalent
*/
static int rxrpc_release(struct socket *sock)
{
struct sock *sk = sock->sk;
_enter("%p{%p}", sock, sk);
if (!sk)
return 0;
sock->sk = NULL;
return rxrpc_release_sock(sk);
}
/*
* RxRPC network protocol
*/
static const struct proto_ops rxrpc_rpc_ops = {
.family = PF_UNIX,
.owner = THIS_MODULE,
.release = rxrpc_release,
.bind = rxrpc_bind,
.connect = rxrpc_connect,
.socketpair = sock_no_socketpair,
.accept = sock_no_accept,
.getname = sock_no_getname,
.poll = rxrpc_poll,
.ioctl = sock_no_ioctl,
.listen = rxrpc_listen,
.shutdown = sock_no_shutdown,
.setsockopt = rxrpc_setsockopt,
.getsockopt = sock_no_getsockopt,
.sendmsg = rxrpc_sendmsg,
.recvmsg = rxrpc_recvmsg,
.mmap = sock_no_mmap,
.sendpage = sock_no_sendpage,
};
static struct proto rxrpc_proto = {
.name = "RXRPC",
.owner = THIS_MODULE,
.obj_size = sizeof(struct rxrpc_sock),
.max_header = sizeof(struct rxrpc_header),
};
static const struct net_proto_family rxrpc_family_ops = {
.family = PF_RXRPC,
.create = rxrpc_create,
.owner = THIS_MODULE,
};
/*
* initialise and register the RxRPC protocol
*/
static int __init af_rxrpc_init(void)
{
int ret = -1;
BUILD_BUG_ON(sizeof(struct rxrpc_skb_priv) > FIELD_SIZEOF(struct sk_buff, cb));
rxrpc_epoch = htonl(get_seconds());
ret = -ENOMEM;
rxrpc_call_jar = kmem_cache_create(
"rxrpc_call_jar", sizeof(struct rxrpc_call), 0,
SLAB_HWCACHE_ALIGN, NULL);
if (!rxrpc_call_jar) {
printk(KERN_NOTICE "RxRPC: Failed to allocate call jar\n");
goto error_call_jar;
}
rxrpc_workqueue = alloc_workqueue("krxrpcd", 0, 1);
if (!rxrpc_workqueue) {
printk(KERN_NOTICE "RxRPC: Failed to allocate work queue\n");
goto error_work_queue;
}
ret = proto_register(&rxrpc_proto, 1);
if (ret < 0) {
printk(KERN_CRIT "RxRPC: Cannot register protocol\n");
goto error_proto;
}
ret = sock_register(&rxrpc_family_ops);
if (ret < 0) {
printk(KERN_CRIT "RxRPC: Cannot register socket family\n");
goto error_sock;
}
ret = register_key_type(&key_type_rxrpc);
if (ret < 0) {
printk(KERN_CRIT "RxRPC: Cannot register client key type\n");
goto error_key_type;
}
ret = register_key_type(&key_type_rxrpc_s);
if (ret < 0) {
printk(KERN_CRIT "RxRPC: Cannot register server key type\n");
goto error_key_type_s;
}
#ifdef CONFIG_PROC_FS
proc_create("rxrpc_calls", 0, init_net.proc_net, &rxrpc_call_seq_fops);
proc_create("rxrpc_conns", 0, init_net.proc_net,
&rxrpc_connection_seq_fops);
#endif
return 0;
error_key_type_s:
unregister_key_type(&key_type_rxrpc);
error_key_type:
sock_unregister(PF_RXRPC);
error_sock:
proto_unregister(&rxrpc_proto);
error_proto:
destroy_workqueue(rxrpc_workqueue);
error_work_queue:
kmem_cache_destroy(rxrpc_call_jar);
error_call_jar:
return ret;
}
/*
* unregister the RxRPC protocol
*/
static void __exit af_rxrpc_exit(void)
{
_enter("");
unregister_key_type(&key_type_rxrpc_s);
unregister_key_type(&key_type_rxrpc);
sock_unregister(PF_RXRPC);
proto_unregister(&rxrpc_proto);
rxrpc_destroy_all_calls();
rxrpc_destroy_all_connections();
rxrpc_destroy_all_transports();
rxrpc_destroy_all_peers();
rxrpc_destroy_all_locals();
ASSERTCMP(atomic_read(&rxrpc_n_skbs), ==, 0);
_debug("flush scheduled work");
flush_workqueue(rxrpc_workqueue);
remove_proc_entry("rxrpc_conns", init_net.proc_net);
remove_proc_entry("rxrpc_calls", init_net.proc_net);
destroy_workqueue(rxrpc_workqueue);
kmem_cache_destroy(rxrpc_call_jar);
_leave("");
}
module_init(af_rxrpc_init);
module_exit(af_rxrpc_exit);
| gpl-2.0 |
koying/buildroot-linux-kernel-m3-pivos | drivers/net/skfp/pmf.c | 1453 | 40556 | /******************************************************************************
*
* (C)Copyright 1998,1999 SysKonnect,
* a business unit of Schneider & Koch & Co. Datensysteme GmbH.
*
* See the file "skfddi.c" for further information.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* The information in this file is provided "AS IS" without warranty.
*
******************************************************************************/
/*
Parameter Management Frame processing for SMT 7.2
*/
#include "h/types.h"
#include "h/fddi.h"
#include "h/smc.h"
#include "h/smt_p.h"
#define KERNEL
#include "h/smtstate.h"
#ifndef SLIM_SMT
#ifndef lint
static const char ID_sccs[] = "@(#)pmf.c 1.37 97/08/04 (C) SK " ;
#endif
static int smt_authorize(struct s_smc *smc, struct smt_header *sm);
static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm);
static const struct s_p_tab* smt_get_ptab(u_short para);
static int smt_mib_phys(struct s_smc *smc);
static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
int local, int set);
void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
int index, int local);
static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
int set, int local);
static int port_to_mib(struct s_smc *smc, int p);
#define MOFFSS(e) offsetof(struct fddi_mib, e)
#define MOFFMS(e) offsetof(struct fddi_mib_m, e)
#define MOFFAS(e) offsetof(struct fddi_mib_a, e)
#define MOFFPS(e) offsetof(struct fddi_mib_p, e)
#define AC_G 0x01 /* Get */
#define AC_GR 0x02 /* Get/Set */
#define AC_S 0x04 /* Set */
#define AC_NA 0x08
#define AC_GROUP 0x10 /* Group */
#define MS2BCLK(x) ((x)*12500L)
/*
F LFag (byte)
B byte
S u_short 16 bit
C Counter 32 bit
L Long 32 bit
T Timer_2 32 bit
P TimeStamp ;
A LongAddress (6 byte)
E Enum 16 bit
R ResId 16 Bit
*/
static const struct s_p_tab {
u_short p_num ; /* parameter code */
u_char p_access ; /* access rights */
u_short p_offset ; /* offset in mib */
char p_swap[3] ; /* format string */
} p_tab[] = {
/* StationIdGrp */
{ SMT_P100A,AC_GROUP } ,
{ SMT_P100B,AC_G, MOFFSS(fddiSMTStationId), "8" } ,
{ SMT_P100D,AC_G, MOFFSS(fddiSMTOpVersionId), "S" } ,
{ SMT_P100E,AC_G, MOFFSS(fddiSMTHiVersionId), "S" } ,
{ SMT_P100F,AC_G, MOFFSS(fddiSMTLoVersionId), "S" } ,
{ SMT_P1010,AC_G, MOFFSS(fddiSMTManufacturerData), "D" } ,
{ SMT_P1011,AC_GR, MOFFSS(fddiSMTUserData), "D" } ,
{ SMT_P1012,AC_G, MOFFSS(fddiSMTMIBVersionId), "S" } ,
/* StationConfigGrp */
{ SMT_P1014,AC_GROUP } ,
{ SMT_P1015,AC_G, MOFFSS(fddiSMTMac_Ct), "B" } ,
{ SMT_P1016,AC_G, MOFFSS(fddiSMTNonMaster_Ct), "B" } ,
{ SMT_P1017,AC_G, MOFFSS(fddiSMTMaster_Ct), "B" } ,
{ SMT_P1018,AC_G, MOFFSS(fddiSMTAvailablePaths), "B" } ,
{ SMT_P1019,AC_G, MOFFSS(fddiSMTConfigCapabilities),"S" } ,
{ SMT_P101A,AC_GR, MOFFSS(fddiSMTConfigPolicy), "wS" } ,
{ SMT_P101B,AC_GR, MOFFSS(fddiSMTConnectionPolicy),"wS" } ,
{ SMT_P101D,AC_GR, MOFFSS(fddiSMTTT_Notify), "wS" } ,
{ SMT_P101E,AC_GR, MOFFSS(fddiSMTStatRptPolicy), "bB" } ,
{ SMT_P101F,AC_GR, MOFFSS(fddiSMTTrace_MaxExpiration),"lL" } ,
{ SMT_P1020,AC_G, MOFFSS(fddiSMTPORTIndexes), "II" } ,
{ SMT_P1021,AC_G, MOFFSS(fddiSMTMACIndexes), "I" } ,
{ SMT_P1022,AC_G, MOFFSS(fddiSMTBypassPresent), "F" } ,
/* StatusGrp */
{ SMT_P1028,AC_GROUP } ,
{ SMT_P1029,AC_G, MOFFSS(fddiSMTECMState), "E" } ,
{ SMT_P102A,AC_G, MOFFSS(fddiSMTCF_State), "E" } ,
{ SMT_P102C,AC_G, MOFFSS(fddiSMTRemoteDisconnectFlag),"F" } ,
{ SMT_P102D,AC_G, MOFFSS(fddiSMTStationStatus), "E" } ,
{ SMT_P102E,AC_G, MOFFSS(fddiSMTPeerWrapFlag), "F" } ,
/* MIBOperationGrp */
{ SMT_P1032,AC_GROUP } ,
{ SMT_P1033,AC_G, MOFFSS(fddiSMTTimeStamp),"P" } ,
{ SMT_P1034,AC_G, MOFFSS(fddiSMTTransitionTimeStamp),"P" } ,
/* NOTE : SMT_P1035 is already swapped ! SMT_P_SETCOUNT */
{ SMT_P1035,AC_G, MOFFSS(fddiSMTSetCount),"4P" } ,
{ SMT_P1036,AC_G, MOFFSS(fddiSMTLastSetStationId),"8" } ,
{ SMT_P103C,AC_S, 0, "wS" } ,
/*
* PRIVATE EXTENSIONS
* only accessible locally to get/set passwd
*/
{ SMT_P10F0,AC_GR, MOFFSS(fddiPRPMFPasswd), "8" } ,
{ SMT_P10F1,AC_GR, MOFFSS(fddiPRPMFStation), "8" } ,
#ifdef ESS
{ SMT_P10F2,AC_GR, MOFFSS(fddiESSPayload), "lL" } ,
{ SMT_P10F3,AC_GR, MOFFSS(fddiESSOverhead), "lL" } ,
{ SMT_P10F4,AC_GR, MOFFSS(fddiESSMaxTNeg), "lL" } ,
{ SMT_P10F5,AC_GR, MOFFSS(fddiESSMinSegmentSize), "lL" } ,
{ SMT_P10F6,AC_GR, MOFFSS(fddiESSCategory), "lL" } ,
{ SMT_P10F7,AC_GR, MOFFSS(fddiESSSynchTxMode), "wS" } ,
#endif
#ifdef SBA
{ SMT_P10F8,AC_GR, MOFFSS(fddiSBACommand), "bF" } ,
{ SMT_P10F9,AC_GR, MOFFSS(fddiSBAAvailable), "bF" } ,
#endif
/* MAC Attributes */
{ SMT_P200A,AC_GROUP } ,
{ SMT_P200B,AC_G, MOFFMS(fddiMACFrameStatusFunctions),"S" } ,
{ SMT_P200D,AC_G, MOFFMS(fddiMACT_MaxCapabilitiy),"T" } ,
{ SMT_P200E,AC_G, MOFFMS(fddiMACTVXCapabilitiy),"T" } ,
/* ConfigGrp */
{ SMT_P2014,AC_GROUP } ,
{ SMT_P2016,AC_G, MOFFMS(fddiMACAvailablePaths), "B" } ,
{ SMT_P2017,AC_G, MOFFMS(fddiMACCurrentPath), "S" } ,
{ SMT_P2018,AC_G, MOFFMS(fddiMACUpstreamNbr), "A" } ,
{ SMT_P2019,AC_G, MOFFMS(fddiMACDownstreamNbr), "A" } ,
{ SMT_P201A,AC_G, MOFFMS(fddiMACOldUpstreamNbr), "A" } ,
{ SMT_P201B,AC_G, MOFFMS(fddiMACOldDownstreamNbr),"A" } ,
{ SMT_P201D,AC_G, MOFFMS(fddiMACDupAddressTest), "E" } ,
{ SMT_P2020,AC_GR, MOFFMS(fddiMACRequestedPaths), "wS" } ,
{ SMT_P2021,AC_G, MOFFMS(fddiMACDownstreamPORTType),"E" } ,
{ SMT_P2022,AC_G, MOFFMS(fddiMACIndex), "S" } ,
/* AddressGrp */
{ SMT_P2028,AC_GROUP } ,
{ SMT_P2029,AC_G, MOFFMS(fddiMACSMTAddress), "A" } ,
/* OperationGrp */
{ SMT_P2032,AC_GROUP } ,
{ SMT_P2033,AC_G, MOFFMS(fddiMACT_Req), "T" } ,
{ SMT_P2034,AC_G, MOFFMS(fddiMACT_Neg), "T" } ,
{ SMT_P2035,AC_G, MOFFMS(fddiMACT_Max), "T" } ,
{ SMT_P2036,AC_G, MOFFMS(fddiMACTvxValue), "T" } ,
{ SMT_P2038,AC_G, MOFFMS(fddiMACT_Pri0), "T" } ,
{ SMT_P2039,AC_G, MOFFMS(fddiMACT_Pri1), "T" } ,
{ SMT_P203A,AC_G, MOFFMS(fddiMACT_Pri2), "T" } ,
{ SMT_P203B,AC_G, MOFFMS(fddiMACT_Pri3), "T" } ,
{ SMT_P203C,AC_G, MOFFMS(fddiMACT_Pri4), "T" } ,
{ SMT_P203D,AC_G, MOFFMS(fddiMACT_Pri5), "T" } ,
{ SMT_P203E,AC_G, MOFFMS(fddiMACT_Pri6), "T" } ,
/* CountersGrp */
{ SMT_P2046,AC_GROUP } ,
{ SMT_P2047,AC_G, MOFFMS(fddiMACFrame_Ct), "C" } ,
{ SMT_P2048,AC_G, MOFFMS(fddiMACCopied_Ct), "C" } ,
{ SMT_P2049,AC_G, MOFFMS(fddiMACTransmit_Ct), "C" } ,
{ SMT_P204A,AC_G, MOFFMS(fddiMACToken_Ct), "C" } ,
{ SMT_P2051,AC_G, MOFFMS(fddiMACError_Ct), "C" } ,
{ SMT_P2052,AC_G, MOFFMS(fddiMACLost_Ct), "C" } ,
{ SMT_P2053,AC_G, MOFFMS(fddiMACTvxExpired_Ct), "C" } ,
{ SMT_P2054,AC_G, MOFFMS(fddiMACNotCopied_Ct), "C" } ,
{ SMT_P2056,AC_G, MOFFMS(fddiMACRingOp_Ct), "C" } ,
/* FrameErrorConditionGrp */
{ SMT_P205A,AC_GROUP } ,
{ SMT_P205F,AC_GR, MOFFMS(fddiMACFrameErrorThreshold),"wS" } ,
{ SMT_P2060,AC_G, MOFFMS(fddiMACFrameErrorRatio), "S" } ,
/* NotCopiedConditionGrp */
{ SMT_P2064,AC_GROUP } ,
{ SMT_P2067,AC_GR, MOFFMS(fddiMACNotCopiedThreshold),"wS" } ,
{ SMT_P2069,AC_G, MOFFMS(fddiMACNotCopiedRatio), "S" } ,
/* StatusGrp */
{ SMT_P206E,AC_GROUP } ,
{ SMT_P206F,AC_G, MOFFMS(fddiMACRMTState), "S" } ,
{ SMT_P2070,AC_G, MOFFMS(fddiMACDA_Flag), "F" } ,
{ SMT_P2071,AC_G, MOFFMS(fddiMACUNDA_Flag), "F" } ,
{ SMT_P2072,AC_G, MOFFMS(fddiMACFrameErrorFlag), "F" } ,
{ SMT_P2073,AC_G, MOFFMS(fddiMACNotCopiedFlag), "F" } ,
{ SMT_P2074,AC_G, MOFFMS(fddiMACMA_UnitdataAvailable),"F" } ,
{ SMT_P2075,AC_G, MOFFMS(fddiMACHardwarePresent), "F" } ,
{ SMT_P2076,AC_GR, MOFFMS(fddiMACMA_UnitdataEnable),"bF" } ,
/*
* PRIVATE EXTENSIONS
* only accessible locally to get/set TMIN
*/
{ SMT_P20F0,AC_NA } ,
{ SMT_P20F1,AC_GR, MOFFMS(fddiMACT_Min), "lT" } ,
/* Path Attributes */
/*
* DON't swap 320B,320F,3210: they are already swapped in swap_para()
*/
{ SMT_P320A,AC_GROUP } ,
{ SMT_P320B,AC_G, MOFFAS(fddiPATHIndex), "r" } ,
{ SMT_P320F,AC_GR, MOFFAS(fddiPATHSbaPayload), "l4" } ,
{ SMT_P3210,AC_GR, MOFFAS(fddiPATHSbaOverhead), "l4" } ,
/* fddiPATHConfiguration */
{ SMT_P3212,AC_G, 0, "" } ,
{ SMT_P3213,AC_GR, MOFFAS(fddiPATHT_Rmode), "lT" } ,
{ SMT_P3214,AC_GR, MOFFAS(fddiPATHSbaAvailable), "lL" } ,
{ SMT_P3215,AC_GR, MOFFAS(fddiPATHTVXLowerBound), "lT" } ,
{ SMT_P3216,AC_GR, MOFFAS(fddiPATHT_MaxLowerBound),"lT" } ,
{ SMT_P3217,AC_GR, MOFFAS(fddiPATHMaxT_Req), "lT" } ,
/* Port Attributes */
/* ConfigGrp */
{ SMT_P400A,AC_GROUP } ,
{ SMT_P400C,AC_G, MOFFPS(fddiPORTMy_Type), "E" } ,
{ SMT_P400D,AC_G, MOFFPS(fddiPORTNeighborType), "E" } ,
{ SMT_P400E,AC_GR, MOFFPS(fddiPORTConnectionPolicies),"bB" } ,
{ SMT_P400F,AC_G, MOFFPS(fddiPORTMacIndicated), "2" } ,
{ SMT_P4010,AC_G, MOFFPS(fddiPORTCurrentPath), "E" } ,
{ SMT_P4011,AC_GR, MOFFPS(fddiPORTRequestedPaths), "l4" } ,
{ SMT_P4012,AC_G, MOFFPS(fddiPORTMACPlacement), "S" } ,
{ SMT_P4013,AC_G, MOFFPS(fddiPORTAvailablePaths), "B" } ,
{ SMT_P4016,AC_G, MOFFPS(fddiPORTPMDClass), "E" } ,
{ SMT_P4017,AC_G, MOFFPS(fddiPORTConnectionCapabilities), "B"} ,
{ SMT_P401D,AC_G, MOFFPS(fddiPORTIndex), "R" } ,
/* OperationGrp */
{ SMT_P401E,AC_GROUP } ,
{ SMT_P401F,AC_GR, MOFFPS(fddiPORTMaint_LS), "wE" } ,
{ SMT_P4021,AC_G, MOFFPS(fddiPORTBS_Flag), "F" } ,
{ SMT_P4022,AC_G, MOFFPS(fddiPORTPC_LS), "E" } ,
/* ErrorCtrsGrp */
{ SMT_P4028,AC_GROUP } ,
{ SMT_P4029,AC_G, MOFFPS(fddiPORTEBError_Ct), "C" } ,
{ SMT_P402A,AC_G, MOFFPS(fddiPORTLCTFail_Ct), "C" } ,
/* LerGrp */
{ SMT_P4032,AC_GROUP } ,
{ SMT_P4033,AC_G, MOFFPS(fddiPORTLer_Estimate), "F" } ,
{ SMT_P4034,AC_G, MOFFPS(fddiPORTLem_Reject_Ct), "C" } ,
{ SMT_P4035,AC_G, MOFFPS(fddiPORTLem_Ct), "C" } ,
{ SMT_P403A,AC_GR, MOFFPS(fddiPORTLer_Cutoff), "bB" } ,
{ SMT_P403B,AC_GR, MOFFPS(fddiPORTLer_Alarm), "bB" } ,
/* StatusGrp */
{ SMT_P403C,AC_GROUP } ,
{ SMT_P403D,AC_G, MOFFPS(fddiPORTConnectState), "E" } ,
{ SMT_P403E,AC_G, MOFFPS(fddiPORTPCMStateX), "E" } ,
{ SMT_P403F,AC_G, MOFFPS(fddiPORTPC_Withhold), "E" } ,
{ SMT_P4040,AC_G, MOFFPS(fddiPORTLerFlag), "F" } ,
{ SMT_P4041,AC_G, MOFFPS(fddiPORTHardwarePresent),"F" } ,
{ SMT_P4046,AC_S, 0, "wS" } ,
{ 0, AC_GROUP } ,
{ 0 }
} ;
void smt_pmf_received_pack(struct s_smc *smc, SMbuf *mb, int local)
{
struct smt_header *sm ;
SMbuf *reply ;
sm = smtod(mb,struct smt_header *) ;
DB_SMT("SMT: processing PMF frame at %x len %d\n",sm,mb->sm_len) ;
#ifdef DEBUG
dump_smt(smc,sm,"PMF Received") ;
#endif
/*
* Start the watchdog: It may be a long, long packet and
* maybe the watchdog occurs ...
*/
smt_start_watchdog(smc) ;
if (sm->smt_class == SMT_PMF_GET ||
sm->smt_class == SMT_PMF_SET) {
reply = smt_build_pmf_response(smc,sm,
sm->smt_class == SMT_PMF_SET,local) ;
if (reply) {
sm = smtod(reply,struct smt_header *) ;
#ifdef DEBUG
dump_smt(smc,sm,"PMF Reply") ;
#endif
smt_send_frame(smc,reply,FC_SMT_INFO,local) ;
}
}
}
static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
int set, int local)
{
SMbuf *mb ;
struct smt_header *smt ;
struct smt_para *pa ;
struct smt_p_reason *res ;
const struct s_p_tab *pt ;
int len ;
int index ;
int idx_end ;
int error ;
int range ;
SK_LOC_DECL(struct s_pcon,pcon) ;
SK_LOC_DECL(struct s_pcon,set_pcon) ;
/*
* build SMT header
*/
if (!(mb = smt_get_mbuf(smc)))
return(mb) ;
smt = smtod(mb, struct smt_header *) ;
smt->smt_dest = req->smt_source ; /* DA == source of request */
smt->smt_class = req->smt_class ; /* same class (GET/SET) */
smt->smt_type = SMT_REPLY ;
smt->smt_version = SMT_VID_2 ;
smt->smt_tid = req->smt_tid ; /* same TID */
smt->smt_pad = 0 ;
smt->smt_len = 0 ;
/*
* setup parameter status
*/
pcon.pc_len = SMT_MAX_INFO_LEN ; /* max para length */
pcon.pc_err = 0 ; /* no error */
pcon.pc_badset = 0 ; /* no bad set count */
pcon.pc_p = (void *) (smt + 1) ; /* paras start here */
/*
* check authoriziation and set count
*/
error = 0 ;
if (set) {
if (!local && smt_authorize(smc,req))
error = SMT_RDF_AUTHOR ;
else if (smt_check_set_count(smc,req))
pcon.pc_badset = SMT_RDF_BADSET ;
}
/*
* add reason code and all mandatory parameters
*/
res = (struct smt_p_reason *) pcon.pc_p ;
smt_add_para(smc,&pcon,(u_short) SMT_P_REASON,0,0) ;
smt_add_para(smc,&pcon,(u_short) SMT_P1033,0,0) ;
/* update 1035 and 1036 later if set */
set_pcon = pcon ;
smt_add_para(smc,&pcon,(u_short) SMT_P1035,0,0) ;
smt_add_para(smc,&pcon,(u_short) SMT_P1036,0,0) ;
pcon.pc_err = error ;
len = req->smt_len ;
pa = (struct smt_para *) (req + 1) ;
/*
* process list of paras
*/
while (!pcon.pc_err && len > 0 ) {
if (((u_short)len < pa->p_len + PARA_LEN) || (pa->p_len & 3)) {
pcon.pc_err = SMT_RDF_LENGTH ;
break ;
}
if (((range = (pa->p_type & 0xf000)) == 0x2000) ||
range == 0x3000 || range == 0x4000) {
/*
* get index for PART,MAC ad PATH group
*/
index = *((u_char *)pa + PARA_LEN + 3) ;/* index */
idx_end = index ;
if (!set && (pa->p_len != 4)) {
pcon.pc_err = SMT_RDF_LENGTH ;
break ;
}
if (!index && !set) {
switch (range) {
case 0x2000 :
index = INDEX_MAC ;
idx_end = index - 1 + NUMMACS ;
break ;
case 0x3000 :
index = INDEX_PATH ;
idx_end = index - 1 + NUMPATHS ;
break ;
case 0x4000 :
index = INDEX_PORT ;
idx_end = index - 1 + NUMPHYS ;
#ifndef CONCENTRATOR
if (smc->s.sas == SMT_SAS)
idx_end = INDEX_PORT ;
#endif
break ;
}
}
}
else {
/*
* smt group has no index
*/
if (!set && (pa->p_len != 0)) {
pcon.pc_err = SMT_RDF_LENGTH ;
break ;
}
index = 0 ;
idx_end = 0 ;
}
while (index <= idx_end) {
/*
* if group
* add all paras of group
*/
pt = smt_get_ptab(pa->p_type) ;
if (pt && pt->p_access == AC_GROUP && !set) {
pt++ ;
while (pt->p_access == AC_G ||
pt->p_access == AC_GR) {
smt_add_para(smc,&pcon,pt->p_num,
index,local);
pt++ ;
}
}
/*
* ignore
* AUTHORIZATION in get/set
* SET COUNT in set
*/
else if (pa->p_type != SMT_P_AUTHOR &&
(!set || (pa->p_type != SMT_P1035))) {
int st ;
if (pcon.pc_badset) {
smt_add_para(smc,&pcon,pa->p_type,
index,local) ;
}
else if (set) {
st = smt_set_para(smc,pa,index,local,1);
/*
* return para even if error
*/
smt_add_para(smc,&pcon,pa->p_type,
index,local) ;
pcon.pc_err = st ;
}
else {
if (pt && pt->p_access == AC_S) {
pcon.pc_err =
SMT_RDF_ILLEGAL ;
}
smt_add_para(smc,&pcon,pa->p_type,
index,local) ;
}
}
if (pcon.pc_err)
break ;
index++ ;
}
len -= pa->p_len + PARA_LEN ;
pa = (struct smt_para *) ((char *)pa + pa->p_len + PARA_LEN) ;
}
smt->smt_len = SMT_MAX_INFO_LEN - pcon.pc_len ;
mb->sm_len = smt->smt_len + sizeof(struct smt_header) ;
/* update reason code */
res->rdf_reason = pcon.pc_badset ? pcon.pc_badset :
pcon.pc_err ? pcon.pc_err : SMT_RDF_SUCCESS ;
if (set && (res->rdf_reason == SMT_RDF_SUCCESS)) {
/*
* increment set count
* set time stamp
* store station id of last set
*/
smc->mib.fddiSMTSetCount.count++ ;
smt_set_timestamp(smc,smc->mib.fddiSMTSetCount.timestamp) ;
smc->mib.fddiSMTLastSetStationId = req->smt_sid ;
smt_add_para(smc,&set_pcon,(u_short) SMT_P1035,0,0) ;
smt_add_para(smc,&set_pcon,(u_short) SMT_P1036,0,0) ;
}
return(mb) ;
}
static int smt_authorize(struct s_smc *smc, struct smt_header *sm)
{
struct smt_para *pa ;
int i ;
char *p ;
/*
* check source station id if not zero
*/
p = (char *) &smc->mib.fddiPRPMFStation ;
for (i = 0 ; i < 8 && !p[i] ; i++)
;
if (i != 8) {
if (memcmp((char *) &sm->smt_sid,
(char *) &smc->mib.fddiPRPMFStation,8))
return(1) ;
}
/*
* check authoriziation parameter if passwd not zero
*/
p = (char *) smc->mib.fddiPRPMFPasswd ;
for (i = 0 ; i < 8 && !p[i] ; i++)
;
if (i != 8) {
pa = (struct smt_para *) sm_to_para(smc,sm,SMT_P_AUTHOR) ;
if (!pa)
return(1) ;
if (pa->p_len != 8)
return(1) ;
if (memcmp((char *)(pa+1),(char *)smc->mib.fddiPRPMFPasswd,8))
return(1) ;
}
return(0) ;
}
static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm)
{
struct smt_para *pa ;
struct smt_p_setcount *sc ;
pa = (struct smt_para *) sm_to_para(smc,sm,SMT_P1035) ;
if (pa) {
sc = (struct smt_p_setcount *) pa ;
if ((smc->mib.fddiSMTSetCount.count != sc->count) ||
memcmp((char *) smc->mib.fddiSMTSetCount.timestamp,
(char *)sc->timestamp,8))
return(1) ;
}
return(0) ;
}
void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
int index, int local)
{
struct smt_para *pa ;
const struct s_p_tab *pt ;
struct fddi_mib_m *mib_m = NULL;
struct fddi_mib_p *mib_p = NULL;
int len ;
int plen ;
char *from ;
char *to ;
const char *swap ;
char c ;
int range ;
char *mib_addr ;
int mac ;
int path ;
int port ;
int sp_len ;
/*
* skip if error
*/
if (pcon->pc_err)
return ;
/*
* actions don't have a value
*/
pt = smt_get_ptab(para) ;
if (pt && pt->p_access == AC_S)
return ;
to = (char *) (pcon->pc_p) ; /* destination pointer */
len = pcon->pc_len ; /* free space */
plen = len ; /* remember start length */
pa = (struct smt_para *) to ; /* type/length pointer */
to += PARA_LEN ; /* skip smt_para */
len -= PARA_LEN ;
/*
* set index if required
*/
if (((range = (para & 0xf000)) == 0x2000) ||
range == 0x3000 || range == 0x4000) {
if (len < 4)
goto wrong_error ;
to[0] = 0 ;
to[1] = 0 ;
to[2] = 0 ;
to[3] = index ;
len -= 4 ;
to += 4 ;
}
mac = index - INDEX_MAC ;
path = index - INDEX_PATH ;
port = index - INDEX_PORT ;
/*
* get pointer to mib
*/
switch (range) {
case 0x1000 :
default :
mib_addr = (char *) (&smc->mib) ;
break ;
case 0x2000 :
if (mac < 0 || mac >= NUMMACS) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
mib_addr = (char *) (&smc->mib.m[mac]) ;
mib_m = (struct fddi_mib_m *) mib_addr ;
break ;
case 0x3000 :
if (path < 0 || path >= NUMPATHS) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
mib_addr = (char *) (&smc->mib.a[path]) ;
break ;
case 0x4000 :
if (port < 0 || port >= smt_mib_phys(smc)) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
mib_addr = (char *) (&smc->mib.p[port_to_mib(smc,port)]) ;
mib_p = (struct fddi_mib_p *) mib_addr ;
break ;
}
/*
* check special paras
*/
swap = NULL;
switch (para) {
case SMT_P10F0 :
case SMT_P10F1 :
#ifdef ESS
case SMT_P10F2 :
case SMT_P10F3 :
case SMT_P10F4 :
case SMT_P10F5 :
case SMT_P10F6 :
case SMT_P10F7 :
#endif
#ifdef SBA
case SMT_P10F8 :
case SMT_P10F9 :
#endif
case SMT_P20F1 :
if (!local) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
break ;
case SMT_P2034 :
case SMT_P2046 :
case SMT_P2047 :
case SMT_P204A :
case SMT_P2051 :
case SMT_P2052 :
mac_update_counter(smc) ;
break ;
case SMT_P4022:
mib_p->fddiPORTPC_LS = LS2MIB(
sm_pm_get_ls(smc,port_to_mib(smc,port))) ;
break ;
case SMT_P_REASON :
* (u_long *) to = 0 ;
sp_len = 4 ;
goto sp_done ;
case SMT_P1033 : /* time stamp */
smt_set_timestamp(smc,smc->mib.fddiSMTTimeStamp) ;
break ;
case SMT_P1020: /* port indexes */
#if NUMPHYS == 12
swap = "IIIIIIIIIIII" ;
#else
#if NUMPHYS == 2
if (smc->s.sas == SMT_SAS)
swap = "I" ;
else
swap = "II" ;
#else
#if NUMPHYS == 24
swap = "IIIIIIIIIIIIIIIIIIIIIIII" ;
#else
????
#endif
#endif
#endif
break ;
case SMT_P3212 :
{
sp_len = cem_build_path(smc,to,path) ;
goto sp_done ;
}
case SMT_P1048 : /* peer wrap condition */
{
struct smt_p_1048 *sp ;
sp = (struct smt_p_1048 *) to ;
sp->p1048_flag = smc->mib.fddiSMTPeerWrapFlag ;
sp->p1048_cf_state = smc->mib.fddiSMTCF_State ;
sp_len = sizeof(struct smt_p_1048) ;
goto sp_done ;
}
case SMT_P208C :
{
struct smt_p_208c *sp ;
sp = (struct smt_p_208c *) to ;
sp->p208c_flag =
smc->mib.m[MAC0].fddiMACDuplicateAddressCond ;
sp->p208c_dupcondition =
(mib_m->fddiMACDA_Flag ? SMT_ST_MY_DUPA : 0) |
(mib_m->fddiMACUNDA_Flag ? SMT_ST_UNA_DUPA : 0);
sp->p208c_fddilong =
mib_m->fddiMACSMTAddress ;
sp->p208c_fddiunalong =
mib_m->fddiMACUpstreamNbr ;
sp->p208c_pad = 0 ;
sp_len = sizeof(struct smt_p_208c) ;
goto sp_done ;
}
case SMT_P208D : /* frame error condition */
{
struct smt_p_208d *sp ;
sp = (struct smt_p_208d *) to ;
sp->p208d_flag =
mib_m->fddiMACFrameErrorFlag ;
sp->p208d_frame_ct =
mib_m->fddiMACFrame_Ct ;
sp->p208d_error_ct =
mib_m->fddiMACError_Ct ;
sp->p208d_lost_ct =
mib_m->fddiMACLost_Ct ;
sp->p208d_ratio =
mib_m->fddiMACFrameErrorRatio ;
sp_len = sizeof(struct smt_p_208d) ;
goto sp_done ;
}
case SMT_P208E : /* not copied condition */
{
struct smt_p_208e *sp ;
sp = (struct smt_p_208e *) to ;
sp->p208e_flag =
mib_m->fddiMACNotCopiedFlag ;
sp->p208e_not_copied =
mib_m->fddiMACNotCopied_Ct ;
sp->p208e_copied =
mib_m->fddiMACCopied_Ct ;
sp->p208e_not_copied_ratio =
mib_m->fddiMACNotCopiedRatio ;
sp_len = sizeof(struct smt_p_208e) ;
goto sp_done ;
}
case SMT_P208F : /* neighbor change event */
{
struct smt_p_208f *sp ;
sp = (struct smt_p_208f *) to ;
sp->p208f_multiple =
mib_m->fddiMACMultiple_N ;
sp->p208f_nacondition =
mib_m->fddiMACDuplicateAddressCond ;
sp->p208f_old_una =
mib_m->fddiMACOldUpstreamNbr ;
sp->p208f_new_una =
mib_m->fddiMACUpstreamNbr ;
sp->p208f_old_dna =
mib_m->fddiMACOldDownstreamNbr ;
sp->p208f_new_dna =
mib_m->fddiMACDownstreamNbr ;
sp->p208f_curren_path =
mib_m->fddiMACCurrentPath ;
sp->p208f_smt_address =
mib_m->fddiMACSMTAddress ;
sp_len = sizeof(struct smt_p_208f) ;
goto sp_done ;
}
case SMT_P2090 :
{
struct smt_p_2090 *sp ;
sp = (struct smt_p_2090 *) to ;
sp->p2090_multiple =
mib_m->fddiMACMultiple_P ;
sp->p2090_availablepaths =
mib_m->fddiMACAvailablePaths ;
sp->p2090_currentpath =
mib_m->fddiMACCurrentPath ;
sp->p2090_requestedpaths =
mib_m->fddiMACRequestedPaths ;
sp_len = sizeof(struct smt_p_2090) ;
goto sp_done ;
}
case SMT_P4050 :
{
struct smt_p_4050 *sp ;
sp = (struct smt_p_4050 *) to ;
sp->p4050_flag =
mib_p->fddiPORTLerFlag ;
sp->p4050_pad = 0 ;
sp->p4050_cutoff =
mib_p->fddiPORTLer_Cutoff ;
sp->p4050_alarm =
mib_p->fddiPORTLer_Alarm ;
sp->p4050_estimate =
mib_p->fddiPORTLer_Estimate ;
sp->p4050_reject_ct =
mib_p->fddiPORTLem_Reject_Ct ;
sp->p4050_ct =
mib_p->fddiPORTLem_Ct ;
sp_len = sizeof(struct smt_p_4050) ;
goto sp_done ;
}
case SMT_P4051 :
{
struct smt_p_4051 *sp ;
sp = (struct smt_p_4051 *) to ;
sp->p4051_multiple =
mib_p->fddiPORTMultiple_U ;
sp->p4051_porttype =
mib_p->fddiPORTMy_Type ;
sp->p4051_connectstate =
mib_p->fddiPORTConnectState ;
sp->p4051_pc_neighbor =
mib_p->fddiPORTNeighborType ;
sp->p4051_pc_withhold =
mib_p->fddiPORTPC_Withhold ;
sp_len = sizeof(struct smt_p_4051) ;
goto sp_done ;
}
case SMT_P4052 :
{
struct smt_p_4052 *sp ;
sp = (struct smt_p_4052 *) to ;
sp->p4052_flag =
mib_p->fddiPORTEB_Condition ;
sp->p4052_eberrorcount =
mib_p->fddiPORTEBError_Ct ;
sp_len = sizeof(struct smt_p_4052) ;
goto sp_done ;
}
case SMT_P4053 :
{
struct smt_p_4053 *sp ;
sp = (struct smt_p_4053 *) to ;
sp->p4053_multiple =
mib_p->fddiPORTMultiple_P ;
sp->p4053_availablepaths =
mib_p->fddiPORTAvailablePaths ;
sp->p4053_currentpath =
mib_p->fddiPORTCurrentPath ;
memcpy( (char *) &sp->p4053_requestedpaths,
(char *) mib_p->fddiPORTRequestedPaths,4) ;
sp->p4053_mytype =
mib_p->fddiPORTMy_Type ;
sp->p4053_neighbortype =
mib_p->fddiPORTNeighborType ;
sp_len = sizeof(struct smt_p_4053) ;
goto sp_done ;
}
default :
break ;
}
/*
* in table ?
*/
if (!pt) {
pcon->pc_err = (para & 0xff00) ? SMT_RDF_NOPARAM :
SMT_RDF_ILLEGAL ;
return ;
}
/*
* check access rights
*/
switch (pt->p_access) {
case AC_G :
case AC_GR :
break ;
default :
pcon->pc_err = SMT_RDF_ILLEGAL ;
return ;
}
from = mib_addr + pt->p_offset ;
if (!swap)
swap = pt->p_swap ; /* pointer to swap string */
/*
* copy values
*/
while ((c = *swap++)) {
switch(c) {
case 'b' :
case 'w' :
case 'l' :
break ;
case 'S' :
case 'E' :
case 'R' :
case 'r' :
if (len < 4)
goto len_error ;
to[0] = 0 ;
to[1] = 0 ;
#ifdef LITTLE_ENDIAN
if (c == 'r') {
to[2] = *from++ ;
to[3] = *from++ ;
}
else {
to[3] = *from++ ;
to[2] = *from++ ;
}
#else
to[2] = *from++ ;
to[3] = *from++ ;
#endif
to += 4 ;
len -= 4 ;
break ;
case 'I' : /* for SET of port indexes */
if (len < 2)
goto len_error ;
#ifdef LITTLE_ENDIAN
to[1] = *from++ ;
to[0] = *from++ ;
#else
to[0] = *from++ ;
to[1] = *from++ ;
#endif
to += 2 ;
len -= 2 ;
break ;
case 'F' :
case 'B' :
if (len < 4)
goto len_error ;
len -= 4 ;
to[0] = 0 ;
to[1] = 0 ;
to[2] = 0 ;
to[3] = *from++ ;
to += 4 ;
break ;
case 'C' :
case 'T' :
case 'L' :
if (len < 4)
goto len_error ;
#ifdef LITTLE_ENDIAN
to[3] = *from++ ;
to[2] = *from++ ;
to[1] = *from++ ;
to[0] = *from++ ;
#else
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
#endif
len -= 4 ;
to += 4 ;
break ;
case '2' : /* PortMacIndicated */
if (len < 4)
goto len_error ;
to[0] = 0 ;
to[1] = 0 ;
to[2] = *from++ ;
to[3] = *from++ ;
len -= 4 ;
to += 4 ;
break ;
case '4' :
if (len < 4)
goto len_error ;
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
len -= 4 ;
to += 4 ;
break ;
case 'A' :
if (len < 8)
goto len_error ;
to[0] = 0 ;
to[1] = 0 ;
memcpy((char *) to+2,(char *) from,6) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case '8' :
if (len < 8)
goto len_error ;
memcpy((char *) to,(char *) from,8) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case 'D' :
if (len < 32)
goto len_error ;
memcpy((char *) to,(char *) from,32) ;
to += 32 ;
from += 32 ;
len -= 32 ;
break ;
case 'P' : /* timestamp is NOT swapped */
if (len < 8)
goto len_error ;
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
to[4] = *from++ ;
to[5] = *from++ ;
to[6] = *from++ ;
to[7] = *from++ ;
to += 8 ;
len -= 8 ;
break ;
default :
SMT_PANIC(smc,SMT_E0119, SMT_E0119_MSG) ;
break ;
}
}
done:
/*
* make it even (in case of 'I' encoding)
* note: len is DECREMENTED
*/
if (len & 3) {
to[0] = 0 ;
to[1] = 0 ;
to += 4 - (len & 3 ) ;
len = len & ~ 3 ;
}
/* set type and length */
pa->p_type = para ;
pa->p_len = plen - len - PARA_LEN ;
/* return values */
pcon->pc_p = (void *) to ;
pcon->pc_len = len ;
return ;
sp_done:
len -= sp_len ;
to += sp_len ;
goto done ;
len_error:
/* parameter does not fit in frame */
pcon->pc_err = SMT_RDF_TOOLONG ;
return ;
wrong_error:
pcon->pc_err = SMT_RDF_LENGTH ;
}
/*
* set parameter
*/
static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
int local, int set)
{
#define IFSET(x) if (set) (x)
const struct s_p_tab *pt ;
int len ;
char *from ;
char *to ;
const char *swap ;
char c ;
char *mib_addr ;
struct fddi_mib *mib ;
struct fddi_mib_m *mib_m = NULL;
struct fddi_mib_a *mib_a = NULL;
struct fddi_mib_p *mib_p = NULL;
int mac ;
int path ;
int port ;
SK_LOC_DECL(u_char,byte_val) ;
SK_LOC_DECL(u_short,word_val) ;
SK_LOC_DECL(u_long,long_val) ;
mac = index - INDEX_MAC ;
path = index - INDEX_PATH ;
port = index - INDEX_PORT ;
len = pa->p_len ;
from = (char *) (pa + 1 ) ;
mib = &smc->mib ;
switch (pa->p_type & 0xf000) {
case 0x1000 :
default :
mib_addr = (char *) mib ;
break ;
case 0x2000 :
if (mac < 0 || mac >= NUMMACS) {
return(SMT_RDF_NOPARAM) ;
}
mib_m = &smc->mib.m[mac] ;
mib_addr = (char *) mib_m ;
from += 4 ; /* skip index */
len -= 4 ;
break ;
case 0x3000 :
if (path < 0 || path >= NUMPATHS) {
return(SMT_RDF_NOPARAM) ;
}
mib_a = &smc->mib.a[path] ;
mib_addr = (char *) mib_a ;
from += 4 ; /* skip index */
len -= 4 ;
break ;
case 0x4000 :
if (port < 0 || port >= smt_mib_phys(smc)) {
return(SMT_RDF_NOPARAM) ;
}
mib_p = &smc->mib.p[port_to_mib(smc,port)] ;
mib_addr = (char *) mib_p ;
from += 4 ; /* skip index */
len -= 4 ;
break ;
}
switch (pa->p_type) {
case SMT_P10F0 :
case SMT_P10F1 :
#ifdef ESS
case SMT_P10F2 :
case SMT_P10F3 :
case SMT_P10F4 :
case SMT_P10F5 :
case SMT_P10F6 :
case SMT_P10F7 :
#endif
#ifdef SBA
case SMT_P10F8 :
case SMT_P10F9 :
#endif
case SMT_P20F1 :
if (!local) {
return(SMT_RDF_NOPARAM) ;
}
break ;
}
pt = smt_get_ptab(pa->p_type) ;
if (!pt) {
return( (pa->p_type & 0xff00) ? SMT_RDF_NOPARAM :
SMT_RDF_ILLEGAL ) ;
}
switch (pt->p_access) {
case AC_GR :
case AC_S :
break ;
default :
return(SMT_RDF_ILLEGAL) ;
}
to = mib_addr + pt->p_offset ;
swap = pt->p_swap ; /* pointer to swap string */
while (swap && (c = *swap++)) {
switch(c) {
case 'b' :
to = (char *) &byte_val ;
break ;
case 'w' :
to = (char *) &word_val ;
break ;
case 'l' :
to = (char *) &long_val ;
break ;
case 'S' :
case 'E' :
case 'R' :
case 'r' :
if (len < 4) {
goto len_error ;
}
if (from[0] | from[1])
goto val_error ;
#ifdef LITTLE_ENDIAN
if (c == 'r') {
to[0] = from[2] ;
to[1] = from[3] ;
}
else {
to[1] = from[2] ;
to[0] = from[3] ;
}
#else
to[0] = from[2] ;
to[1] = from[3] ;
#endif
from += 4 ;
to += 2 ;
len -= 4 ;
break ;
case 'F' :
case 'B' :
if (len < 4) {
goto len_error ;
}
if (from[0] | from[1] | from[2])
goto val_error ;
to[0] = from[3] ;
len -= 4 ;
from += 4 ;
to += 4 ;
break ;
case 'C' :
case 'T' :
case 'L' :
if (len < 4) {
goto len_error ;
}
#ifdef LITTLE_ENDIAN
to[3] = *from++ ;
to[2] = *from++ ;
to[1] = *from++ ;
to[0] = *from++ ;
#else
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
#endif
len -= 4 ;
to += 4 ;
break ;
case 'A' :
if (len < 8)
goto len_error ;
if (set)
memcpy((char *) to,(char *) from+2,6) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case '4' :
if (len < 4)
goto len_error ;
if (set)
memcpy((char *) to,(char *) from,4) ;
to += 4 ;
from += 4 ;
len -= 4 ;
break ;
case '8' :
if (len < 8)
goto len_error ;
if (set)
memcpy((char *) to,(char *) from,8) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case 'D' :
if (len < 32)
goto len_error ;
if (set)
memcpy((char *) to,(char *) from,32) ;
to += 32 ;
from += 32 ;
len -= 32 ;
break ;
case 'P' : /* timestamp is NOT swapped */
if (set) {
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
to[4] = *from++ ;
to[5] = *from++ ;
to[6] = *from++ ;
to[7] = *from++ ;
}
to += 8 ;
len -= 8 ;
break ;
default :
SMT_PANIC(smc,SMT_E0120, SMT_E0120_MSG) ;
return(SMT_RDF_ILLEGAL) ;
}
}
/*
* actions and internal updates
*/
switch (pa->p_type) {
case SMT_P101A: /* fddiSMTConfigPolicy */
if (word_val & ~1)
goto val_error ;
IFSET(mib->fddiSMTConfigPolicy = word_val) ;
break ;
case SMT_P101B : /* fddiSMTConnectionPolicy */
if (!(word_val & POLICY_MM))
goto val_error ;
IFSET(mib->fddiSMTConnectionPolicy = word_val) ;
break ;
case SMT_P101D : /* fddiSMTTT_Notify */
if (word_val < 2 || word_val > 30)
goto val_error ;
IFSET(mib->fddiSMTTT_Notify = word_val) ;
break ;
case SMT_P101E : /* fddiSMTStatRptPolicy */
if (byte_val & ~1)
goto val_error ;
IFSET(mib->fddiSMTStatRptPolicy = byte_val) ;
break ;
case SMT_P101F : /* fddiSMTTrace_MaxExpiration */
/*
* note: lower limit trace_max = 6.001773... s
* NO upper limit
*/
if (long_val < (long)0x478bf51L)
goto val_error ;
IFSET(mib->fddiSMTTrace_MaxExpiration = long_val) ;
break ;
#ifdef ESS
case SMT_P10F2 : /* fddiESSPayload */
if (long_val > 1562)
goto val_error ;
if (set && smc->mib.fddiESSPayload != long_val) {
smc->ess.raf_act_timer_poll = TRUE ;
smc->mib.fddiESSPayload = long_val ;
}
break ;
case SMT_P10F3 : /* fddiESSOverhead */
if (long_val < 50 || long_val > 5000)
goto val_error ;
if (set && smc->mib.fddiESSPayload &&
smc->mib.fddiESSOverhead != long_val) {
smc->ess.raf_act_timer_poll = TRUE ;
smc->mib.fddiESSOverhead = long_val ;
}
break ;
case SMT_P10F4 : /* fddiESSMaxTNeg */
if (long_val > -MS2BCLK(5) || long_val < -MS2BCLK(165))
goto val_error ;
IFSET(mib->fddiESSMaxTNeg = long_val) ;
break ;
case SMT_P10F5 : /* fddiESSMinSegmentSize */
if (long_val < 1 || long_val > 4478)
goto val_error ;
IFSET(mib->fddiESSMinSegmentSize = long_val) ;
break ;
case SMT_P10F6 : /* fddiESSCategory */
if ((long_val & 0xffff) != 1)
goto val_error ;
IFSET(mib->fddiESSCategory = long_val) ;
break ;
case SMT_P10F7 : /* fddiESSSyncTxMode */
if (word_val > 1)
goto val_error ;
IFSET(mib->fddiESSSynchTxMode = word_val) ;
break ;
#endif
#ifdef SBA
case SMT_P10F8 : /* fddiSBACommand */
if (byte_val != SB_STOP && byte_val != SB_START)
goto val_error ;
IFSET(mib->fddiSBACommand = byte_val) ;
break ;
case SMT_P10F9 : /* fddiSBAAvailable */
if (byte_val > 100)
goto val_error ;
IFSET(mib->fddiSBAAvailable = byte_val) ;
break ;
#endif
case SMT_P2020 : /* fddiMACRequestedPaths */
if ((word_val & (MIB_P_PATH_PRIM_PREFER |
MIB_P_PATH_PRIM_ALTER)) == 0 )
goto val_error ;
IFSET(mib_m->fddiMACRequestedPaths = word_val) ;
break ;
case SMT_P205F : /* fddiMACFrameErrorThreshold */
/* 0 .. ffff acceptable */
IFSET(mib_m->fddiMACFrameErrorThreshold = word_val) ;
break ;
case SMT_P2067 : /* fddiMACNotCopiedThreshold */
/* 0 .. ffff acceptable */
IFSET(mib_m->fddiMACNotCopiedThreshold = word_val) ;
break ;
case SMT_P2076: /* fddiMACMA_UnitdataEnable */
if (byte_val & ~1)
goto val_error ;
if (set) {
mib_m->fddiMACMA_UnitdataEnable = byte_val ;
queue_event(smc,EVENT_RMT,RM_ENABLE_FLAG) ;
}
break ;
case SMT_P20F1 : /* fddiMACT_Min */
IFSET(mib_m->fddiMACT_Min = long_val) ;
break ;
case SMT_P320F :
if (long_val > 1562)
goto val_error ;
IFSET(mib_a->fddiPATHSbaPayload = long_val) ;
#ifdef ESS
if (set)
ess_para_change(smc) ;
#endif
break ;
case SMT_P3210 :
if (long_val > 5000)
goto val_error ;
if (long_val != 0 && mib_a->fddiPATHSbaPayload == 0)
goto val_error ;
IFSET(mib_a->fddiPATHSbaOverhead = long_val) ;
#ifdef ESS
if (set)
ess_para_change(smc) ;
#endif
break ;
case SMT_P3213: /* fddiPATHT_Rmode */
/* no limit :
* 0 .. 343.597 => 0 .. 2e32 * 80nS
*/
if (set) {
mib_a->fddiPATHT_Rmode = long_val ;
rtm_set_timer(smc) ;
}
break ;
case SMT_P3214 : /* fddiPATHSbaAvailable */
if (long_val > 0x00BEBC20L)
goto val_error ;
#ifdef SBA
if (set && mib->fddiSBACommand == SB_STOP)
goto val_error ;
#endif
IFSET(mib_a->fddiPATHSbaAvailable = long_val) ;
break ;
case SMT_P3215 : /* fddiPATHTVXLowerBound */
IFSET(mib_a->fddiPATHTVXLowerBound = long_val) ;
goto change_mac_para ;
case SMT_P3216 : /* fddiPATHT_MaxLowerBound */
IFSET(mib_a->fddiPATHT_MaxLowerBound = long_val) ;
goto change_mac_para ;
case SMT_P3217 : /* fddiPATHMaxT_Req */
IFSET(mib_a->fddiPATHMaxT_Req = long_val) ;
change_mac_para:
if (set && smt_set_mac_opvalues(smc)) {
RS_SET(smc,RS_EVENT) ;
smc->sm.please_reconnect = 1 ;
queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
}
break ;
case SMT_P400E : /* fddiPORTConnectionPolicies */
if (byte_val > 1)
goto val_error ;
IFSET(mib_p->fddiPORTConnectionPolicies = byte_val) ;
break ;
case SMT_P4011 : /* fddiPORTRequestedPaths */
/* all 3*8 bits allowed */
IFSET(memcpy((char *)mib_p->fddiPORTRequestedPaths,
(char *)&long_val,4)) ;
break ;
case SMT_P401F: /* fddiPORTMaint_LS */
if (word_val > 4)
goto val_error ;
IFSET(mib_p->fddiPORTMaint_LS = word_val) ;
break ;
case SMT_P403A : /* fddiPORTLer_Cutoff */
if (byte_val < 4 || byte_val > 15)
goto val_error ;
IFSET(mib_p->fddiPORTLer_Cutoff = byte_val) ;
break ;
case SMT_P403B : /* fddiPORTLer_Alarm */
if (byte_val < 4 || byte_val > 15)
goto val_error ;
IFSET(mib_p->fddiPORTLer_Alarm = byte_val) ;
break ;
/*
* Actions
*/
case SMT_P103C : /* fddiSMTStationAction */
if (smt_action(smc,SMT_STATION_ACTION, (int) word_val, 0))
goto val_error ;
break ;
case SMT_P4046: /* fddiPORTAction */
if (smt_action(smc,SMT_PORT_ACTION, (int) word_val,
port_to_mib(smc,port)))
goto val_error ;
break ;
default :
break ;
}
return(0) ;
val_error:
/* parameter value in frame is out of range */
return(SMT_RDF_RANGE) ;
len_error:
/* parameter value in frame is too short */
return(SMT_RDF_LENGTH) ;
#if 0
no_author_error:
/* parameter not setable, because the SBA is not active
* Please note: we give the return code 'not authorizeed
* because SBA denied is not a valid return code in the
* PMF protocol.
*/
return(SMT_RDF_AUTHOR) ;
#endif
}
static const struct s_p_tab *smt_get_ptab(u_short para)
{
const struct s_p_tab *pt ;
for (pt = p_tab ; pt->p_num && pt->p_num != para ; pt++)
;
return(pt->p_num ? pt : NULL) ;
}
static int smt_mib_phys(struct s_smc *smc)
{
#ifdef CONCENTRATOR
SK_UNUSED(smc) ;
return(NUMPHYS) ;
#else
if (smc->s.sas == SMT_SAS)
return(1) ;
return(NUMPHYS) ;
#endif
}
static int port_to_mib(struct s_smc *smc, int p)
{
#ifdef CONCENTRATOR
SK_UNUSED(smc) ;
return(p) ;
#else
if (smc->s.sas == SMT_SAS)
return(PS) ;
return(p) ;
#endif
}
#ifdef DEBUG
#ifndef BOOT
void dump_smt(struct s_smc *smc, struct smt_header *sm, char *text)
{
int len ;
struct smt_para *pa ;
char *c ;
int n ;
int nn ;
#ifdef LITTLE_ENDIAN
int smtlen ;
#endif
SK_UNUSED(smc) ;
#ifdef DEBUG_BRD
if (smc->debug.d_smtf < 2)
#else
if (debug.d_smtf < 2)
#endif
return ;
#ifdef LITTLE_ENDIAN
smtlen = sm->smt_len + sizeof(struct smt_header) ;
#endif
printf("SMT Frame [%s]:\nDA ",text) ;
dump_hex((char *) &sm->smt_dest,6) ;
printf("\tSA ") ;
dump_hex((char *) &sm->smt_source,6) ;
printf(" Class %x Type %x Version %x\n",
sm->smt_class,sm->smt_type,sm->smt_version) ;
printf("TID %lx\t\tSID ",sm->smt_tid) ;
dump_hex((char *) &sm->smt_sid,8) ;
printf(" LEN %x\n",sm->smt_len) ;
len = sm->smt_len ;
pa = (struct smt_para *) (sm + 1) ;
while (len > 0 ) {
int plen ;
#ifdef UNIX
printf("TYPE %x LEN %x VALUE\t",pa->p_type,pa->p_len) ;
#else
printf("TYPE %04x LEN %2x VALUE\t",pa->p_type,pa->p_len) ;
#endif
n = pa->p_len ;
if ( (n < 0 ) || (n > (int)(len - PARA_LEN))) {
n = len - PARA_LEN ;
printf(" BAD LENGTH\n") ;
break ;
}
#ifdef LITTLE_ENDIAN
smt_swap_para(sm,smtlen,0) ;
#endif
if (n < 24) {
dump_hex((char *)(pa+1),(int) n) ;
printf("\n") ;
}
else {
int first = 0 ;
c = (char *)(pa+1) ;
dump_hex(c,16) ;
printf("\n") ;
n -= 16 ;
c += 16 ;
while (n > 0) {
nn = (n > 16) ? 16 : n ;
if (n > 64) {
if (first == 0)
printf("\t\t\t...\n") ;
first = 1 ;
}
else {
printf("\t\t\t") ;
dump_hex(c,nn) ;
printf("\n") ;
}
n -= nn ;
c += 16 ;
}
}
#ifdef LITTLE_ENDIAN
smt_swap_para(sm,smtlen,1) ;
#endif
plen = (pa->p_len + PARA_LEN + 3) & ~3 ;
len -= plen ;
pa = (struct smt_para *)((char *)pa + plen) ;
}
printf("-------------------------------------------------\n\n") ;
}
void dump_hex(char *p, int len)
{
int n = 0 ;
while (len--) {
n++ ;
#ifdef UNIX
printf("%x%s",*p++ & 0xff,len ? ( (n & 7) ? " " : "-") : "") ;
#else
printf("%02x%s",*p++ & 0xff,len ? ( (n & 7) ? " " : "-") : "") ;
#endif
}
}
#endif /* no BOOT */
#endif /* DEBUG */
#endif /* no SLIM_SMT */
| gpl-2.0 |
MikePach/stock_kernel_lge_l2s | drivers/usb/serial/garmin_gps.c | 1709 | 40896 | /*
* Garmin GPS driver
*
* Copyright (C) 2006-2011 Hermann Kneissel herkne@gmx.de
*
* The latest version of the driver can be found at
* http://sourceforge.net/projects/garmin-gps/
*
* This driver has been derived from v2.1 of the visor driver.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/tty_flip.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <asm/atomic.h>
#include <linux/usb.h>
#include <linux/usb/serial.h>
/* the mode to be set when the port ist opened */
static int initial_mode = 1;
/* debug flag */
static int debug;
#define GARMIN_VENDOR_ID 0x091E
/*
* Version Information
*/
#define VERSION_MAJOR 0
#define VERSION_MINOR 36
#define _STR(s) #s
#define _DRIVER_VERSION(a, b) "v" _STR(a) "." _STR(b)
#define DRIVER_VERSION _DRIVER_VERSION(VERSION_MAJOR, VERSION_MINOR)
#define DRIVER_AUTHOR "hermann kneissel"
#define DRIVER_DESC "garmin gps driver"
/* error codes returned by the driver */
#define EINVPKT 1000 /* invalid packet structure */
/* size of the header of a packet using the usb protocol */
#define GARMIN_PKTHDR_LENGTH 12
/* max. possible size of a packet using the serial protocol */
#define MAX_SERIAL_PKT_SIZ (3 + 255 + 3)
/* max. possible size of a packet with worst case stuffing */
#define MAX_SERIAL_PKT_SIZ_STUFFED (MAX_SERIAL_PKT_SIZ + 256)
/* size of a buffer able to hold a complete (no stuffing) packet
* (the document protocol does not contain packets with a larger
* size, but in theory a packet may be 64k+12 bytes - if in
* later protocol versions larger packet sizes occur, this value
* should be increased accordingly, so the input buffer is always
* large enough the store a complete packet inclusive header) */
#define GPS_IN_BUFSIZ (GARMIN_PKTHDR_LENGTH+MAX_SERIAL_PKT_SIZ)
/* size of a buffer able to hold a complete (incl. stuffing) packet */
#define GPS_OUT_BUFSIZ (GARMIN_PKTHDR_LENGTH+MAX_SERIAL_PKT_SIZ_STUFFED)
/* where to place the packet id of a serial packet, so we can
* prepend the usb-packet header without the need to move the
* packets data */
#define GSP_INITIAL_OFFSET (GARMIN_PKTHDR_LENGTH-2)
/* max. size of incoming private packets (header+1 param) */
#define PRIVPKTSIZ (GARMIN_PKTHDR_LENGTH+4)
#define GARMIN_LAYERID_TRANSPORT 0
#define GARMIN_LAYERID_APPL 20
/* our own layer-id to use for some control mechanisms */
#define GARMIN_LAYERID_PRIVATE 0x01106E4B
#define GARMIN_PKTID_PVT_DATA 51
#define GARMIN_PKTID_L001_COMMAND_DATA 10
#define CMND_ABORT_TRANSFER 0
/* packet ids used in private layer */
#define PRIV_PKTID_SET_DEBUG 1
#define PRIV_PKTID_SET_MODE 2
#define PRIV_PKTID_INFO_REQ 3
#define PRIV_PKTID_INFO_RESP 4
#define PRIV_PKTID_RESET_REQ 5
#define PRIV_PKTID_SET_DEF_MODE 6
#define ETX 0x03
#define DLE 0x10
#define ACK 0x06
#define NAK 0x15
/* structure used to queue incoming packets */
struct garmin_packet {
struct list_head list;
int seq;
/* the real size of the data array, always > 0 */
int size;
__u8 data[1];
};
/* structure used to keep the current state of the driver */
struct garmin_data {
__u8 state;
__u16 flags;
__u8 mode;
__u8 count;
__u8 pkt_id;
__u32 serial_num;
struct timer_list timer;
struct usb_serial_port *port;
int seq_counter;
int insize;
int outsize;
__u8 inbuffer [GPS_IN_BUFSIZ]; /* tty -> usb */
__u8 outbuffer[GPS_OUT_BUFSIZ]; /* usb -> tty */
__u8 privpkt[4*6];
spinlock_t lock;
struct list_head pktlist;
};
#define STATE_NEW 0
#define STATE_INITIAL_DELAY 1
#define STATE_TIMEOUT 2
#define STATE_SESSION_REQ1 3
#define STATE_SESSION_REQ2 4
#define STATE_ACTIVE 5
#define STATE_RESET 8
#define STATE_DISCONNECTED 9
#define STATE_WAIT_TTY_ACK 10
#define STATE_GSP_WAIT_DATA 11
#define MODE_NATIVE 0
#define MODE_GARMIN_SERIAL 1
/* Flags used in garmin_data.flags: */
#define FLAGS_SESSION_REPLY_MASK 0x00C0
#define FLAGS_SESSION_REPLY1_SEEN 0x0080
#define FLAGS_SESSION_REPLY2_SEEN 0x0040
#define FLAGS_BULK_IN_ACTIVE 0x0020
#define FLAGS_BULK_IN_RESTART 0x0010
#define FLAGS_THROTTLED 0x0008
#define APP_REQ_SEEN 0x0004
#define APP_RESP_SEEN 0x0002
#define CLEAR_HALT_REQUIRED 0x0001
#define FLAGS_QUEUING 0x0100
#define FLAGS_DROP_DATA 0x0800
#define FLAGS_GSP_SKIP 0x1000
#define FLAGS_GSP_DLESEEN 0x2000
/* function prototypes */
static int gsp_next_packet(struct garmin_data *garmin_data_p);
static int garmin_write_bulk(struct usb_serial_port *port,
const unsigned char *buf, int count,
int dismiss_ack);
/* some special packets to be send or received */
static unsigned char const GARMIN_START_SESSION_REQ[]
= { 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0 };
static unsigned char const GARMIN_START_SESSION_REPLY[]
= { 0, 0, 0, 0, 6, 0, 0, 0, 4, 0, 0, 0 };
static unsigned char const GARMIN_BULK_IN_AVAIL_REPLY[]
= { 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0 };
static unsigned char const GARMIN_APP_LAYER_REPLY[]
= { 0x14, 0, 0, 0 };
static unsigned char const GARMIN_START_PVT_REQ[]
= { 20, 0, 0, 0, 10, 0, 0, 0, 2, 0, 0, 0, 49, 0 };
static unsigned char const GARMIN_STOP_PVT_REQ[]
= { 20, 0, 0, 0, 10, 0, 0, 0, 2, 0, 0, 0, 50, 0 };
static unsigned char const GARMIN_STOP_TRANSFER_REQ[]
= { 20, 0, 0, 0, 10, 0, 0, 0, 2, 0, 0, 0, 0, 0 };
static unsigned char const GARMIN_STOP_TRANSFER_REQ_V2[]
= { 20, 0, 0, 0, 10, 0, 0, 0, 1, 0, 0, 0, 0 };
static unsigned char const PRIVATE_REQ[]
= { 0x4B, 0x6E, 0x10, 0x01, 0xFF, 0, 0, 0, 0xFF, 0, 0, 0 };
static const struct usb_device_id id_table[] = {
/* the same device id seems to be used by all
usb enabled GPS devices */
{ USB_DEVICE(GARMIN_VENDOR_ID, 3) },
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, id_table);
static struct usb_driver garmin_driver = {
.name = "garmin_gps",
.probe = usb_serial_probe,
.disconnect = usb_serial_disconnect,
.id_table = id_table,
.no_dynamic_id = 1,
};
static inline int getLayerId(const __u8 *usbPacket)
{
return __le32_to_cpup((__le32 *)(usbPacket));
}
static inline int getPacketId(const __u8 *usbPacket)
{
return __le32_to_cpup((__le32 *)(usbPacket+4));
}
static inline int getDataLength(const __u8 *usbPacket)
{
return __le32_to_cpup((__le32 *)(usbPacket+8));
}
/*
* check if the usb-packet in buf contains an abort-transfer command.
* (if yes, all queued data will be dropped)
*/
static inline int isAbortTrfCmnd(const unsigned char *buf)
{
if (0 == memcmp(buf, GARMIN_STOP_TRANSFER_REQ,
sizeof(GARMIN_STOP_TRANSFER_REQ)) ||
0 == memcmp(buf, GARMIN_STOP_TRANSFER_REQ_V2,
sizeof(GARMIN_STOP_TRANSFER_REQ_V2)))
return 1;
else
return 0;
}
static void send_to_tty(struct usb_serial_port *port,
char *data, unsigned int actual_length)
{
struct tty_struct *tty = tty_port_tty_get(&port->port);
if (tty && actual_length) {
usb_serial_debug_data(debug, &port->dev,
__func__, actual_length, data);
tty_insert_flip_string(tty, data, actual_length);
tty_flip_buffer_push(tty);
}
tty_kref_put(tty);
}
/******************************************************************************
* packet queue handling
******************************************************************************/
/*
* queue a received (usb-)packet for later processing
*/
static int pkt_add(struct garmin_data *garmin_data_p,
unsigned char *data, unsigned int data_length)
{
int state = 0;
int result = 0;
unsigned long flags;
struct garmin_packet *pkt;
/* process only packets containg data ... */
if (data_length) {
pkt = kmalloc(sizeof(struct garmin_packet)+data_length,
GFP_ATOMIC);
if (pkt == NULL) {
dev_err(&garmin_data_p->port->dev, "out of memory\n");
return 0;
}
pkt->size = data_length;
memcpy(pkt->data, data, data_length);
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= FLAGS_QUEUING;
result = list_empty(&garmin_data_p->pktlist);
pkt->seq = garmin_data_p->seq_counter++;
list_add_tail(&pkt->list, &garmin_data_p->pktlist);
state = garmin_data_p->state;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
dbg("%s - added: pkt: %d - %d bytes",
__func__, pkt->seq, data_length);
/* in serial mode, if someone is waiting for data from
the device, convert and send the next packet to tty. */
if (result && (state == STATE_GSP_WAIT_DATA))
gsp_next_packet(garmin_data_p);
}
return result;
}
/* get the next pending packet */
static struct garmin_packet *pkt_pop(struct garmin_data *garmin_data_p)
{
unsigned long flags;
struct garmin_packet *result = NULL;
spin_lock_irqsave(&garmin_data_p->lock, flags);
if (!list_empty(&garmin_data_p->pktlist)) {
result = (struct garmin_packet *)garmin_data_p->pktlist.next;
list_del(&result->list);
}
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
return result;
}
/* free up all queued data */
static void pkt_clear(struct garmin_data *garmin_data_p)
{
unsigned long flags;
struct garmin_packet *result = NULL;
dbg("%s", __func__);
spin_lock_irqsave(&garmin_data_p->lock, flags);
while (!list_empty(&garmin_data_p->pktlist)) {
result = (struct garmin_packet *)garmin_data_p->pktlist.next;
list_del(&result->list);
kfree(result);
}
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
}
/******************************************************************************
* garmin serial protocol handling handling
******************************************************************************/
/* send an ack packet back to the tty */
static int gsp_send_ack(struct garmin_data *garmin_data_p, __u8 pkt_id)
{
__u8 pkt[10];
__u8 cksum = 0;
__u8 *ptr = pkt;
unsigned l = 0;
dbg("%s - pkt-id: 0x%X.", __func__, 0xFF & pkt_id);
*ptr++ = DLE;
*ptr++ = ACK;
cksum += ACK;
*ptr++ = 2;
cksum += 2;
*ptr++ = pkt_id;
cksum += pkt_id;
if (pkt_id == DLE)
*ptr++ = DLE;
*ptr++ = 0;
*ptr++ = 0xFF & (-cksum);
*ptr++ = DLE;
*ptr++ = ETX;
l = ptr-pkt;
send_to_tty(garmin_data_p->port, pkt, l);
return 0;
}
/*
* called for a complete packet received from tty layer
*
* the complete packet (pktid ... cksum) is in garmin_data_p->inbuf starting
* at GSP_INITIAL_OFFSET.
*
* count - number of bytes in the input buffer including space reserved for
* the usb header: GSP_INITIAL_OFFSET + number of bytes in packet
* (including pkt-id, data-length a. cksum)
*/
static int gsp_rec_packet(struct garmin_data *garmin_data_p, int count)
{
unsigned long flags;
const __u8 *recpkt = garmin_data_p->inbuffer+GSP_INITIAL_OFFSET;
__le32 *usbdata = (__le32 *) garmin_data_p->inbuffer;
int cksum = 0;
int n = 0;
int pktid = recpkt[0];
int size = recpkt[1];
usb_serial_debug_data(debug, &garmin_data_p->port->dev,
__func__, count-GSP_INITIAL_OFFSET, recpkt);
if (size != (count-GSP_INITIAL_OFFSET-3)) {
dbg("%s - invalid size, expected %d bytes, got %d",
__func__, size, (count-GSP_INITIAL_OFFSET-3));
return -EINVPKT;
}
cksum += *recpkt++;
cksum += *recpkt++;
/* sanity check, remove after test ... */
if ((__u8 *)&(usbdata[3]) != recpkt) {
dbg("%s - ptr mismatch %p - %p",
__func__, &(usbdata[4]), recpkt);
return -EINVPKT;
}
while (n < size) {
cksum += *recpkt++;
n++;
}
if ((0xff & (cksum + *recpkt)) != 0) {
dbg("%s - invalid checksum, expected %02x, got %02x",
__func__, 0xff & -cksum, 0xff & *recpkt);
return -EINVPKT;
}
usbdata[0] = __cpu_to_le32(GARMIN_LAYERID_APPL);
usbdata[1] = __cpu_to_le32(pktid);
usbdata[2] = __cpu_to_le32(size);
garmin_write_bulk(garmin_data_p->port, garmin_data_p->inbuffer,
GARMIN_PKTHDR_LENGTH+size, 0);
/* if this was an abort-transfer command, flush all
queued data. */
if (isAbortTrfCmnd(garmin_data_p->inbuffer)) {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= FLAGS_DROP_DATA;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
pkt_clear(garmin_data_p);
}
return count;
}
/*
* Called for data received from tty
*
* buf contains the data read, it may span more than one packet or even
* incomplete packets
*
* input record should be a serial-record, but it may not be complete.
* Copy it into our local buffer, until an etx is seen (or an error
* occurs).
* Once the record is complete, convert into a usb packet and send it
* to the bulk pipe, send an ack back to the tty.
*
* If the input is an ack, just send the last queued packet to the
* tty layer.
*
* if the input is an abort command, drop all queued data.
*/
static int gsp_receive(struct garmin_data *garmin_data_p,
const unsigned char *buf, int count)
{
unsigned long flags;
int offs = 0;
int ack_or_nak_seen = 0;
__u8 *dest;
int size;
/* dleSeen: set if last byte read was a DLE */
int dleSeen;
/* skip: if set, skip incoming data until possible start of
* new packet
*/
int skip;
__u8 data;
spin_lock_irqsave(&garmin_data_p->lock, flags);
dest = garmin_data_p->inbuffer;
size = garmin_data_p->insize;
dleSeen = garmin_data_p->flags & FLAGS_GSP_DLESEEN;
skip = garmin_data_p->flags & FLAGS_GSP_SKIP;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
/* dbg("%s - dle=%d skip=%d size=%d count=%d",
__func__, dleSeen, skip, size, count); */
if (size == 0)
size = GSP_INITIAL_OFFSET;
while (offs < count) {
data = *(buf+offs);
offs++;
if (data == DLE) {
if (skip) { /* start of a new pkt */
skip = 0;
size = GSP_INITIAL_OFFSET;
dleSeen = 1;
} else if (dleSeen) {
dest[size++] = data;
dleSeen = 0;
} else {
dleSeen = 1;
}
} else if (data == ETX) {
if (dleSeen) {
/* packet complete */
data = dest[GSP_INITIAL_OFFSET];
if (data == ACK) {
ack_or_nak_seen = ACK;
dbg("ACK packet complete.");
} else if (data == NAK) {
ack_or_nak_seen = NAK;
dbg("NAK packet complete.");
} else {
dbg("packet complete - id=0x%X.",
0xFF & data);
gsp_rec_packet(garmin_data_p, size);
}
skip = 1;
size = GSP_INITIAL_OFFSET;
dleSeen = 0;
} else {
dest[size++] = data;
}
} else if (!skip) {
if (dleSeen) {
size = GSP_INITIAL_OFFSET;
dleSeen = 0;
}
dest[size++] = data;
}
if (size >= GPS_IN_BUFSIZ) {
dbg("%s - packet too large.", __func__);
skip = 1;
size = GSP_INITIAL_OFFSET;
dleSeen = 0;
}
}
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->insize = size;
/* copy flags back to structure */
if (skip)
garmin_data_p->flags |= FLAGS_GSP_SKIP;
else
garmin_data_p->flags &= ~FLAGS_GSP_SKIP;
if (dleSeen)
garmin_data_p->flags |= FLAGS_GSP_DLESEEN;
else
garmin_data_p->flags &= ~FLAGS_GSP_DLESEEN;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
if (ack_or_nak_seen) {
if (gsp_next_packet(garmin_data_p) > 0)
garmin_data_p->state = STATE_ACTIVE;
else
garmin_data_p->state = STATE_GSP_WAIT_DATA;
}
return count;
}
/*
* Sends a usb packet to the tty
*
* Assumes, that all packages and at an usb-packet boundary.
*
* return <0 on error, 0 if packet is incomplete or > 0 if packet was sent
*/
static int gsp_send(struct garmin_data *garmin_data_p,
const unsigned char *buf, int count)
{
const unsigned char *src;
unsigned char *dst;
int pktid = 0;
int datalen = 0;
int cksum = 0;
int i = 0;
int k;
dbg("%s - state %d - %d bytes.", __func__,
garmin_data_p->state, count);
k = garmin_data_p->outsize;
if ((k+count) > GPS_OUT_BUFSIZ) {
dbg("packet too large");
garmin_data_p->outsize = 0;
return -4;
}
memcpy(garmin_data_p->outbuffer+k, buf, count);
k += count;
garmin_data_p->outsize = k;
if (k >= GARMIN_PKTHDR_LENGTH) {
pktid = getPacketId(garmin_data_p->outbuffer);
datalen = getDataLength(garmin_data_p->outbuffer);
i = GARMIN_PKTHDR_LENGTH + datalen;
if (k < i)
return 0;
} else {
return 0;
}
dbg("%s - %d bytes in buffer, %d bytes in pkt.", __func__, k, i);
/* garmin_data_p->outbuffer now contains a complete packet */
usb_serial_debug_data(debug, &garmin_data_p->port->dev,
__func__, k, garmin_data_p->outbuffer);
garmin_data_p->outsize = 0;
if (GARMIN_LAYERID_APPL != getLayerId(garmin_data_p->outbuffer)) {
dbg("not an application packet (%d)",
getLayerId(garmin_data_p->outbuffer));
return -1;
}
if (pktid > 255) {
dbg("packet-id %d too large", pktid);
return -2;
}
if (datalen > 255) {
dbg("packet-size %d too large", datalen);
return -3;
}
/* the serial protocol should be able to handle this packet */
k = 0;
src = garmin_data_p->outbuffer+GARMIN_PKTHDR_LENGTH;
for (i = 0; i < datalen; i++) {
if (*src++ == DLE)
k++;
}
src = garmin_data_p->outbuffer+GARMIN_PKTHDR_LENGTH;
if (k > (GARMIN_PKTHDR_LENGTH-2)) {
/* can't add stuffing DLEs in place, move data to end
of buffer ... */
dst = garmin_data_p->outbuffer+GPS_OUT_BUFSIZ-datalen;
memcpy(dst, src, datalen);
src = dst;
}
dst = garmin_data_p->outbuffer;
*dst++ = DLE;
*dst++ = pktid;
cksum += pktid;
*dst++ = datalen;
cksum += datalen;
if (datalen == DLE)
*dst++ = DLE;
for (i = 0; i < datalen; i++) {
__u8 c = *src++;
*dst++ = c;
cksum += c;
if (c == DLE)
*dst++ = DLE;
}
cksum = 0xFF & -cksum;
*dst++ = cksum;
if (cksum == DLE)
*dst++ = DLE;
*dst++ = DLE;
*dst++ = ETX;
i = dst-garmin_data_p->outbuffer;
send_to_tty(garmin_data_p->port, garmin_data_p->outbuffer, i);
garmin_data_p->pkt_id = pktid;
garmin_data_p->state = STATE_WAIT_TTY_ACK;
return i;
}
/*
* Process the next pending data packet - if there is one
*/
static int gsp_next_packet(struct garmin_data *garmin_data_p)
{
int result = 0;
struct garmin_packet *pkt = NULL;
while ((pkt = pkt_pop(garmin_data_p)) != NULL) {
dbg("%s - next pkt: %d", __func__, pkt->seq);
result = gsp_send(garmin_data_p, pkt->data, pkt->size);
if (result > 0) {
kfree(pkt);
return result;
}
kfree(pkt);
}
return result;
}
/******************************************************************************
* garmin native mode
******************************************************************************/
/*
* Called for data received from tty
*
* The input data is expected to be in garmin usb-packet format.
*
* buf contains the data read, it may span more than one packet
* or even incomplete packets
*/
static int nat_receive(struct garmin_data *garmin_data_p,
const unsigned char *buf, int count)
{
unsigned long flags;
__u8 *dest;
int offs = 0;
int result = count;
int len;
while (offs < count) {
/* if buffer contains header, copy rest of data */
if (garmin_data_p->insize >= GARMIN_PKTHDR_LENGTH)
len = GARMIN_PKTHDR_LENGTH
+getDataLength(garmin_data_p->inbuffer);
else
len = GARMIN_PKTHDR_LENGTH;
if (len >= GPS_IN_BUFSIZ) {
/* seems to be an invalid packet, ignore rest
of input */
dbg("%s - packet size too large: %d", __func__, len);
garmin_data_p->insize = 0;
count = 0;
result = -EINVPKT;
} else {
len -= garmin_data_p->insize;
if (len > (count-offs))
len = (count-offs);
if (len > 0) {
dest = garmin_data_p->inbuffer
+ garmin_data_p->insize;
memcpy(dest, buf+offs, len);
garmin_data_p->insize += len;
offs += len;
}
}
/* do we have a complete packet ? */
if (garmin_data_p->insize >= GARMIN_PKTHDR_LENGTH) {
len = GARMIN_PKTHDR_LENGTH+
getDataLength(garmin_data_p->inbuffer);
if (garmin_data_p->insize >= len) {
garmin_write_bulk(garmin_data_p->port,
garmin_data_p->inbuffer,
len, 0);
garmin_data_p->insize = 0;
/* if this was an abort-transfer command,
flush all queued data. */
if (isAbortTrfCmnd(garmin_data_p->inbuffer)) {
spin_lock_irqsave(&garmin_data_p->lock,
flags);
garmin_data_p->flags |= FLAGS_DROP_DATA;
spin_unlock_irqrestore(
&garmin_data_p->lock, flags);
pkt_clear(garmin_data_p);
}
}
}
}
return result;
}
/******************************************************************************
* private packets
******************************************************************************/
static void priv_status_resp(struct usb_serial_port *port)
{
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
__le32 *pkt = (__le32 *)garmin_data_p->privpkt;
pkt[0] = __cpu_to_le32(GARMIN_LAYERID_PRIVATE);
pkt[1] = __cpu_to_le32(PRIV_PKTID_INFO_RESP);
pkt[2] = __cpu_to_le32(12);
pkt[3] = __cpu_to_le32(VERSION_MAJOR << 16 | VERSION_MINOR);
pkt[4] = __cpu_to_le32(garmin_data_p->mode);
pkt[5] = __cpu_to_le32(garmin_data_p->serial_num);
send_to_tty(port, (__u8 *)pkt, 6 * 4);
}
/******************************************************************************
* Garmin specific driver functions
******************************************************************************/
static int process_resetdev_request(struct usb_serial_port *port)
{
unsigned long flags;
int status;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags &= ~(CLEAR_HALT_REQUIRED);
garmin_data_p->state = STATE_RESET;
garmin_data_p->serial_num = 0;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
usb_kill_urb(port->interrupt_in_urb);
dbg("%s - usb_reset_device", __func__);
status = usb_reset_device(port->serial->dev);
if (status)
dbg("%s - usb_reset_device failed: %d",
__func__, status);
return status;
}
/*
* clear all cached data
*/
static int garmin_clear(struct garmin_data *garmin_data_p)
{
unsigned long flags;
int status = 0;
/* flush all queued data */
pkt_clear(garmin_data_p);
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->insize = 0;
garmin_data_p->outsize = 0;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
return status;
}
static int garmin_init_session(struct usb_serial_port *port)
{
struct usb_serial *serial = port->serial;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
int status = 0;
int i = 0;
if (status == 0) {
usb_kill_urb(port->interrupt_in_urb);
dbg("%s - adding interrupt input", __func__);
port->interrupt_in_urb->dev = serial->dev;
status = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
if (status)
dev_err(&serial->dev->dev,
"%s - failed submitting interrupt urb, error %d\n",
__func__, status);
}
/*
* using the initialization method from gpsbabel. See comments in
* gpsbabel/jeeps/gpslibusb.c gusb_reset_toggles()
*/
if (status == 0) {
dbg("%s - starting session ...", __func__);
garmin_data_p->state = STATE_ACTIVE;
for (i = 0; i < 3; i++) {
status = garmin_write_bulk(port,
GARMIN_START_SESSION_REQ,
sizeof(GARMIN_START_SESSION_REQ), 0);
if (status < 0)
break;
}
if (status > 0)
status = 0;
}
return status;
}
static int garmin_open(struct tty_struct *tty, struct usb_serial_port *port)
{
unsigned long flags;
int status = 0;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
dbg("%s - port %d", __func__, port->number);
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->mode = initial_mode;
garmin_data_p->count = 0;
garmin_data_p->flags &= FLAGS_SESSION_REPLY1_SEEN;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
/* shutdown any bulk reads that might be going on */
usb_kill_urb(port->write_urb);
usb_kill_urb(port->read_urb);
if (garmin_data_p->state == STATE_RESET)
status = garmin_init_session(port);
garmin_data_p->state = STATE_ACTIVE;
return status;
}
static void garmin_close(struct usb_serial_port *port)
{
struct usb_serial *serial = port->serial;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
dbg("%s - port %d - mode=%d state=%d flags=0x%X", __func__,
port->number, garmin_data_p->mode,
garmin_data_p->state, garmin_data_p->flags);
if (!serial)
return;
mutex_lock(&port->serial->disc_mutex);
if (!port->serial->disconnected)
garmin_clear(garmin_data_p);
/* shutdown our urbs */
usb_kill_urb(port->read_urb);
usb_kill_urb(port->write_urb);
/* keep reset state so we know that we must start a new session */
if (garmin_data_p->state != STATE_RESET)
garmin_data_p->state = STATE_DISCONNECTED;
mutex_unlock(&port->serial->disc_mutex);
}
static void garmin_write_bulk_callback(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
if (port) {
struct garmin_data *garmin_data_p =
usb_get_serial_port_data(port);
dbg("%s - port %d", __func__, port->number);
if (GARMIN_LAYERID_APPL == getLayerId(urb->transfer_buffer)) {
if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
gsp_send_ack(garmin_data_p,
((__u8 *)urb->transfer_buffer)[4]);
}
}
usb_serial_port_softint(port);
}
/* Ignore errors that resulted from garmin_write_bulk with
dismiss_ack = 1 */
/* free up the transfer buffer, as usb_free_urb() does not do this */
kfree(urb->transfer_buffer);
}
static int garmin_write_bulk(struct usb_serial_port *port,
const unsigned char *buf, int count,
int dismiss_ack)
{
unsigned long flags;
struct usb_serial *serial = port->serial;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
struct urb *urb;
unsigned char *buffer;
int status;
dbg("%s - port %d, state %d", __func__, port->number,
garmin_data_p->state);
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags &= ~FLAGS_DROP_DATA;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
buffer = kmalloc(count, GFP_ATOMIC);
if (!buffer) {
dev_err(&port->dev, "out of memory\n");
return -ENOMEM;
}
urb = usb_alloc_urb(0, GFP_ATOMIC);
if (!urb) {
dev_err(&port->dev, "no more free urbs\n");
kfree(buffer);
return -ENOMEM;
}
memcpy(buffer, buf, count);
usb_serial_debug_data(debug, &port->dev, __func__, count, buffer);
usb_fill_bulk_urb(urb, serial->dev,
usb_sndbulkpipe(serial->dev,
port->bulk_out_endpointAddress),
buffer, count,
garmin_write_bulk_callback,
dismiss_ack ? NULL : port);
urb->transfer_flags |= URB_ZERO_PACKET;
if (GARMIN_LAYERID_APPL == getLayerId(buffer)) {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= APP_REQ_SEEN;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
pkt_clear(garmin_data_p);
garmin_data_p->state = STATE_GSP_WAIT_DATA;
}
}
/* send it down the pipe */
status = usb_submit_urb(urb, GFP_ATOMIC);
if (status) {
dev_err(&port->dev,
"%s - usb_submit_urb(write bulk) failed with status = %d\n",
__func__, status);
count = status;
}
/* we are done with this urb, so let the host driver
* really free it when it is finished with it */
usb_free_urb(urb);
return count;
}
static int garmin_write(struct tty_struct *tty, struct usb_serial_port *port,
const unsigned char *buf, int count)
{
int pktid, pktsiz, len;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
__le32 *privpkt = (__le32 *)garmin_data_p->privpkt;
usb_serial_debug_data(debug, &port->dev, __func__, count, buf);
if (garmin_data_p->state == STATE_RESET)
return -EIO;
/* check for our private packets */
if (count >= GARMIN_PKTHDR_LENGTH) {
len = PRIVPKTSIZ;
if (count < len)
len = count;
memcpy(garmin_data_p->privpkt, buf, len);
pktsiz = getDataLength(garmin_data_p->privpkt);
pktid = getPacketId(garmin_data_p->privpkt);
if (count == (GARMIN_PKTHDR_LENGTH+pktsiz)
&& GARMIN_LAYERID_PRIVATE ==
getLayerId(garmin_data_p->privpkt)) {
dbg("%s - processing private request %d",
__func__, pktid);
/* drop all unfinished transfers */
garmin_clear(garmin_data_p);
switch (pktid) {
case PRIV_PKTID_SET_DEBUG:
if (pktsiz != 4)
return -EINVPKT;
debug = __le32_to_cpu(privpkt[3]);
dbg("%s - debug level set to 0x%X",
__func__, debug);
break;
case PRIV_PKTID_SET_MODE:
if (pktsiz != 4)
return -EINVPKT;
garmin_data_p->mode = __le32_to_cpu(privpkt[3]);
dbg("%s - mode set to %d",
__func__, garmin_data_p->mode);
break;
case PRIV_PKTID_INFO_REQ:
priv_status_resp(port);
break;
case PRIV_PKTID_RESET_REQ:
process_resetdev_request(port);
break;
case PRIV_PKTID_SET_DEF_MODE:
if (pktsiz != 4)
return -EINVPKT;
initial_mode = __le32_to_cpu(privpkt[3]);
dbg("%s - initial_mode set to %d",
__func__,
garmin_data_p->mode);
break;
}
return count;
}
}
if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
return gsp_receive(garmin_data_p, buf, count);
} else { /* MODE_NATIVE */
return nat_receive(garmin_data_p, buf, count);
}
}
static int garmin_write_room(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
/*
* Report back the bytes currently available in the output buffer.
*/
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
return GPS_OUT_BUFSIZ-garmin_data_p->outsize;
}
static void garmin_read_process(struct garmin_data *garmin_data_p,
unsigned char *data, unsigned data_length,
int bulk_data)
{
unsigned long flags;
if (garmin_data_p->flags & FLAGS_DROP_DATA) {
/* abort-transfer cmd is actice */
dbg("%s - pkt dropped", __func__);
} else if (garmin_data_p->state != STATE_DISCONNECTED &&
garmin_data_p->state != STATE_RESET) {
/* if throttling is active or postprecessing is required
put the received data in the input queue, otherwise
send it directly to the tty port */
if (garmin_data_p->flags & FLAGS_QUEUING) {
pkt_add(garmin_data_p, data, data_length);
} else if (bulk_data ||
getLayerId(data) == GARMIN_LAYERID_APPL) {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= APP_RESP_SEEN;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
pkt_add(garmin_data_p, data, data_length);
} else {
send_to_tty(garmin_data_p->port, data,
data_length);
}
}
/* ignore system layer packets ... */
}
}
static void garmin_read_bulk_callback(struct urb *urb)
{
unsigned long flags;
struct usb_serial_port *port = urb->context;
struct usb_serial *serial = port->serial;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
unsigned char *data = urb->transfer_buffer;
int status = urb->status;
int retval;
dbg("%s - port %d", __func__, port->number);
if (!serial) {
dbg("%s - bad serial pointer, exiting", __func__);
return;
}
if (status) {
dbg("%s - nonzero read bulk status received: %d",
__func__, status);
return;
}
usb_serial_debug_data(debug, &port->dev,
__func__, urb->actual_length, data);
garmin_read_process(garmin_data_p, data, urb->actual_length, 1);
if (urb->actual_length == 0 &&
0 != (garmin_data_p->flags & FLAGS_BULK_IN_RESTART)) {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags &= ~FLAGS_BULK_IN_RESTART;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
retval = usb_submit_urb(port->read_urb, GFP_ATOMIC);
if (retval)
dev_err(&port->dev,
"%s - failed resubmitting read urb, error %d\n",
__func__, retval);
} else if (urb->actual_length > 0) {
/* Continue trying to read until nothing more is received */
if (0 == (garmin_data_p->flags & FLAGS_THROTTLED)) {
retval = usb_submit_urb(port->read_urb, GFP_ATOMIC);
if (retval)
dev_err(&port->dev,
"%s - failed resubmitting read urb, "
"error %d\n", __func__, retval);
}
} else {
dbg("%s - end of bulk data", __func__);
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags &= ~FLAGS_BULK_IN_ACTIVE;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
}
}
static void garmin_read_int_callback(struct urb *urb)
{
unsigned long flags;
int retval;
struct usb_serial_port *port = urb->context;
struct usb_serial *serial = port->serial;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
unsigned char *data = urb->transfer_buffer;
int status = urb->status;
switch (status) {
case 0:
/* success */
break;
case -ECONNRESET:
case -ENOENT:
case -ESHUTDOWN:
/* this urb is terminated, clean up */
dbg("%s - urb shutting down with status: %d",
__func__, status);
return;
default:
dbg("%s - nonzero urb status received: %d",
__func__, status);
return;
}
usb_serial_debug_data(debug, &port->dev, __func__,
urb->actual_length, urb->transfer_buffer);
if (urb->actual_length == sizeof(GARMIN_BULK_IN_AVAIL_REPLY) &&
0 == memcmp(data, GARMIN_BULK_IN_AVAIL_REPLY,
sizeof(GARMIN_BULK_IN_AVAIL_REPLY))) {
dbg("%s - bulk data available.", __func__);
if (0 == (garmin_data_p->flags & FLAGS_BULK_IN_ACTIVE)) {
/* bulk data available */
usb_fill_bulk_urb(port->read_urb, serial->dev,
usb_rcvbulkpipe(serial->dev,
port->bulk_in_endpointAddress),
port->read_urb->transfer_buffer,
port->read_urb->transfer_buffer_length,
garmin_read_bulk_callback, port);
retval = usb_submit_urb(port->read_urb, GFP_ATOMIC);
if (retval) {
dev_err(&port->dev,
"%s - failed submitting read urb, error %d\n",
__func__, retval);
} else {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= FLAGS_BULK_IN_ACTIVE;
spin_unlock_irqrestore(&garmin_data_p->lock,
flags);
}
} else {
/* bulk-in transfer still active */
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= FLAGS_BULK_IN_RESTART;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
}
} else if (urb->actual_length == (4+sizeof(GARMIN_START_SESSION_REPLY))
&& 0 == memcmp(data, GARMIN_START_SESSION_REPLY,
sizeof(GARMIN_START_SESSION_REPLY))) {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= FLAGS_SESSION_REPLY1_SEEN;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
/* save the serial number */
garmin_data_p->serial_num = __le32_to_cpup(
(__le32 *)(data+GARMIN_PKTHDR_LENGTH));
dbg("%s - start-of-session reply seen - serial %u.",
__func__, garmin_data_p->serial_num);
}
garmin_read_process(garmin_data_p, data, urb->actual_length, 0);
port->interrupt_in_urb->dev = port->serial->dev;
retval = usb_submit_urb(urb, GFP_ATOMIC);
if (retval)
dev_err(&urb->dev->dev,
"%s - Error %d submitting interrupt urb\n",
__func__, retval);
}
/*
* Sends the next queued packt to the tty port (garmin native mode only)
* and then sets a timer to call itself again until all queued data
* is sent.
*/
static int garmin_flush_queue(struct garmin_data *garmin_data_p)
{
unsigned long flags;
struct garmin_packet *pkt;
if ((garmin_data_p->flags & FLAGS_THROTTLED) == 0) {
pkt = pkt_pop(garmin_data_p);
if (pkt != NULL) {
send_to_tty(garmin_data_p->port, pkt->data, pkt->size);
kfree(pkt);
mod_timer(&garmin_data_p->timer, (1)+jiffies);
} else {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags &= ~FLAGS_QUEUING;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
}
}
return 0;
}
static void garmin_throttle(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
dbg("%s - port %d", __func__, port->number);
/* set flag, data received will be put into a queue
for later processing */
spin_lock_irq(&garmin_data_p->lock);
garmin_data_p->flags |= FLAGS_QUEUING|FLAGS_THROTTLED;
spin_unlock_irq(&garmin_data_p->lock);
}
static void garmin_unthrottle(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
int status;
dbg("%s - port %d", __func__, port->number);
spin_lock_irq(&garmin_data_p->lock);
garmin_data_p->flags &= ~FLAGS_THROTTLED;
spin_unlock_irq(&garmin_data_p->lock);
/* in native mode send queued data to tty, in
serial mode nothing needs to be done here */
if (garmin_data_p->mode == MODE_NATIVE)
garmin_flush_queue(garmin_data_p);
if (0 != (garmin_data_p->flags & FLAGS_BULK_IN_ACTIVE)) {
status = usb_submit_urb(port->read_urb, GFP_KERNEL);
if (status)
dev_err(&port->dev,
"%s - failed resubmitting read urb, error %d\n",
__func__, status);
}
}
/*
* The timer is currently only used to send queued packets to
* the tty in cases where the protocol provides no own handshaking
* to initiate the transfer.
*/
static void timeout_handler(unsigned long data)
{
struct garmin_data *garmin_data_p = (struct garmin_data *) data;
/* send the next queued packet to the tty port */
if (garmin_data_p->mode == MODE_NATIVE)
if (garmin_data_p->flags & FLAGS_QUEUING)
garmin_flush_queue(garmin_data_p);
}
static int garmin_attach(struct usb_serial *serial)
{
int status = 0;
struct usb_serial_port *port = serial->port[0];
struct garmin_data *garmin_data_p = NULL;
dbg("%s", __func__);
garmin_data_p = kzalloc(sizeof(struct garmin_data), GFP_KERNEL);
if (garmin_data_p == NULL) {
dev_err(&port->dev, "%s - Out of memory\n", __func__);
return -ENOMEM;
}
init_timer(&garmin_data_p->timer);
spin_lock_init(&garmin_data_p->lock);
INIT_LIST_HEAD(&garmin_data_p->pktlist);
/* garmin_data_p->timer.expires = jiffies + session_timeout; */
garmin_data_p->timer.data = (unsigned long)garmin_data_p;
garmin_data_p->timer.function = timeout_handler;
garmin_data_p->port = port;
garmin_data_p->state = 0;
garmin_data_p->flags = 0;
garmin_data_p->count = 0;
usb_set_serial_port_data(port, garmin_data_p);
status = garmin_init_session(port);
return status;
}
static void garmin_disconnect(struct usb_serial *serial)
{
struct usb_serial_port *port = serial->port[0];
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
dbg("%s", __func__);
usb_kill_urb(port->interrupt_in_urb);
del_timer_sync(&garmin_data_p->timer);
}
static void garmin_release(struct usb_serial *serial)
{
struct usb_serial_port *port = serial->port[0];
struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
dbg("%s", __func__);
kfree(garmin_data_p);
}
/* All of the device info needed */
static struct usb_serial_driver garmin_device = {
.driver = {
.owner = THIS_MODULE,
.name = "garmin_gps",
},
.description = "Garmin GPS usb/tty",
.usb_driver = &garmin_driver,
.id_table = id_table,
.num_ports = 1,
.open = garmin_open,
.close = garmin_close,
.throttle = garmin_throttle,
.unthrottle = garmin_unthrottle,
.attach = garmin_attach,
.disconnect = garmin_disconnect,
.release = garmin_release,
.write = garmin_write,
.write_room = garmin_write_room,
.write_bulk_callback = garmin_write_bulk_callback,
.read_bulk_callback = garmin_read_bulk_callback,
.read_int_callback = garmin_read_int_callback,
};
static int __init garmin_init(void)
{
int retval;
retval = usb_serial_register(&garmin_device);
if (retval)
goto failed_garmin_register;
retval = usb_register(&garmin_driver);
if (retval)
goto failed_usb_register;
printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_VERSION ":"
DRIVER_DESC "\n");
return 0;
failed_usb_register:
usb_serial_deregister(&garmin_device);
failed_garmin_register:
return retval;
}
static void __exit garmin_exit(void)
{
usb_deregister(&garmin_driver);
usb_serial_deregister(&garmin_device);
}
module_init(garmin_init);
module_exit(garmin_exit);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
module_param(debug, bool, S_IWUSR | S_IRUGO);
MODULE_PARM_DESC(debug, "Debug enabled or not");
module_param(initial_mode, int, S_IRUGO);
MODULE_PARM_DESC(initial_mode, "Initial mode");
| gpl-2.0 |
MassStash/htc_pme_kernel_sense_6.0 | drivers/video/backlight/ipaq_micro_bl.c | 1965 | 2173 | /*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* iPAQ microcontroller backlight support
* Author : Linus Walleij <linus.walleij@linaro.org>
*/
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/mfd/ipaq-micro.h>
#include <linux/module.h>
#include <linux/platform_device.h>
static int micro_bl_update_status(struct backlight_device *bd)
{
struct ipaq_micro *micro = dev_get_drvdata(&bd->dev);
int intensity = bd->props.brightness;
struct ipaq_micro_msg msg = {
.id = MSG_BACKLIGHT,
.tx_len = 3,
};
if (bd->props.power != FB_BLANK_UNBLANK)
intensity = 0;
if (bd->props.state & (BL_CORE_FBBLANK | BL_CORE_SUSPENDED))
intensity = 0;
/*
* Message format:
* Byte 0: backlight instance (usually 1)
* Byte 1: on/off
* Byte 2: intensity, 0-255
*/
msg.tx_data[0] = 0x01;
msg.tx_data[1] = intensity > 0 ? 1 : 0;
msg.tx_data[2] = intensity;
return ipaq_micro_tx_msg_sync(micro, &msg);
}
static const struct backlight_ops micro_bl_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = micro_bl_update_status,
};
static struct backlight_properties micro_bl_props = {
.type = BACKLIGHT_RAW,
.max_brightness = 255,
.power = FB_BLANK_UNBLANK,
.brightness = 64,
};
static int micro_backlight_probe(struct platform_device *pdev)
{
struct backlight_device *bd;
struct ipaq_micro *micro = dev_get_drvdata(pdev->dev.parent);
bd = devm_backlight_device_register(&pdev->dev, "ipaq-micro-backlight",
&pdev->dev, micro, µ_bl_ops,
µ_bl_props);
if (IS_ERR(bd))
return PTR_ERR(bd);
platform_set_drvdata(pdev, bd);
backlight_update_status(bd);
return 0;
}
static struct platform_driver micro_backlight_device_driver = {
.driver = {
.name = "ipaq-micro-backlight",
},
.probe = micro_backlight_probe,
};
module_platform_driver(micro_backlight_device_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("driver for iPAQ Atmel micro backlight");
MODULE_ALIAS("platform:ipaq-micro-backlight");
| gpl-2.0 |
simone201/neak-gs3-jb2 | fs/cifs/smbencrypt.c | 2477 | 9856 | /*
Unix SMB/Netbios implementation.
Version 1.9.
SMB parameters and setup
Copyright (C) Andrew Tridgell 1992-2000
Copyright (C) Luke Kenneth Casson Leighton 1996-2000
Modified by Jeremy Allison 1995.
Copyright (C) Andrew Bartlett <abartlet@samba.org> 2002-2003
Modified by Steve French (sfrench@us.ibm.com) 2002-2003
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/random.h>
#include "cifs_unicode.h"
#include "cifspdu.h"
#include "cifsglob.h"
#include "cifs_debug.h"
#include "cifsproto.h"
#ifndef false
#define false 0
#endif
#ifndef true
#define true 1
#endif
/* following came from the other byteorder.h to avoid include conflicts */
#define CVAL(buf,pos) (((unsigned char *)(buf))[pos])
#define SSVALX(buf,pos,val) (CVAL(buf,pos)=(val)&0xFF,CVAL(buf,pos+1)=(val)>>8)
#define SSVAL(buf,pos,val) SSVALX((buf),(pos),((__u16)(val)))
static void
str_to_key(unsigned char *str, unsigned char *key)
{
int i;
key[0] = str[0] >> 1;
key[1] = ((str[0] & 0x01) << 6) | (str[1] >> 2);
key[2] = ((str[1] & 0x03) << 5) | (str[2] >> 3);
key[3] = ((str[2] & 0x07) << 4) | (str[3] >> 4);
key[4] = ((str[3] & 0x0F) << 3) | (str[4] >> 5);
key[5] = ((str[4] & 0x1F) << 2) | (str[5] >> 6);
key[6] = ((str[5] & 0x3F) << 1) | (str[6] >> 7);
key[7] = str[6] & 0x7F;
for (i = 0; i < 8; i++)
key[i] = (key[i] << 1);
}
static int
smbhash(unsigned char *out, const unsigned char *in, unsigned char *key)
{
int rc;
unsigned char key2[8];
struct crypto_blkcipher *tfm_des;
struct scatterlist sgin, sgout;
struct blkcipher_desc desc;
str_to_key(key, key2);
tfm_des = crypto_alloc_blkcipher("ecb(des)", 0, CRYPTO_ALG_ASYNC);
if (IS_ERR(tfm_des)) {
rc = PTR_ERR(tfm_des);
cERROR(1, "could not allocate des crypto API\n");
goto smbhash_err;
}
desc.tfm = tfm_des;
crypto_blkcipher_setkey(tfm_des, key2, 8);
sg_init_one(&sgin, in, 8);
sg_init_one(&sgout, out, 8);
rc = crypto_blkcipher_encrypt(&desc, &sgout, &sgin, 8);
if (rc)
cERROR(1, "could not encrypt crypt key rc: %d\n", rc);
crypto_free_blkcipher(tfm_des);
smbhash_err:
return rc;
}
static int
E_P16(unsigned char *p14, unsigned char *p16)
{
int rc;
unsigned char sp8[8] =
{ 0x4b, 0x47, 0x53, 0x21, 0x40, 0x23, 0x24, 0x25 };
rc = smbhash(p16, sp8, p14);
if (rc)
return rc;
rc = smbhash(p16 + 8, sp8, p14 + 7);
return rc;
}
static int
E_P24(unsigned char *p21, const unsigned char *c8, unsigned char *p24)
{
int rc;
rc = smbhash(p24, c8, p21);
if (rc)
return rc;
rc = smbhash(p24 + 8, c8, p21 + 7);
if (rc)
return rc;
rc = smbhash(p24 + 16, c8, p21 + 14);
return rc;
}
/* produce a md4 message digest from data of length n bytes */
int
mdfour(unsigned char *md4_hash, unsigned char *link_str, int link_len)
{
int rc;
unsigned int size;
struct crypto_shash *md4;
struct sdesc *sdescmd4;
md4 = crypto_alloc_shash("md4", 0, 0);
if (IS_ERR(md4)) {
rc = PTR_ERR(md4);
cERROR(1, "%s: Crypto md4 allocation error %d\n", __func__, rc);
return rc;
}
size = sizeof(struct shash_desc) + crypto_shash_descsize(md4);
sdescmd4 = kmalloc(size, GFP_KERNEL);
if (!sdescmd4) {
rc = -ENOMEM;
cERROR(1, "%s: Memory allocation failure\n", __func__);
goto mdfour_err;
}
sdescmd4->shash.tfm = md4;
sdescmd4->shash.flags = 0x0;
rc = crypto_shash_init(&sdescmd4->shash);
if (rc) {
cERROR(1, "%s: Could not init md4 shash\n", __func__);
goto mdfour_err;
}
crypto_shash_update(&sdescmd4->shash, link_str, link_len);
rc = crypto_shash_final(&sdescmd4->shash, md4_hash);
mdfour_err:
crypto_free_shash(md4);
kfree(sdescmd4);
return rc;
}
/*
This implements the X/Open SMB password encryption
It takes a password, a 8 byte "crypt key" and puts 24 bytes of
encrypted password into p24 */
/* Note that password must be uppercased and null terminated */
int
SMBencrypt(unsigned char *passwd, const unsigned char *c8, unsigned char *p24)
{
int rc;
unsigned char p14[14], p16[16], p21[21];
memset(p14, '\0', 14);
memset(p16, '\0', 16);
memset(p21, '\0', 21);
memcpy(p14, passwd, 14);
rc = E_P16(p14, p16);
if (rc)
return rc;
memcpy(p21, p16, 16);
rc = E_P24(p21, c8, p24);
return rc;
}
/* Routines for Windows NT MD4 Hash functions. */
static int
_my_wcslen(__u16 *str)
{
int len = 0;
while (*str++ != 0)
len++;
return len;
}
/*
* Convert a string into an NT UNICODE string.
* Note that regardless of processor type
* this must be in intel (little-endian)
* format.
*/
static int
_my_mbstowcs(__u16 *dst, const unsigned char *src, int len)
{ /* BB not a very good conversion routine - change/fix */
int i;
__u16 val;
for (i = 0; i < len; i++) {
val = *src;
SSVAL(dst, 0, val);
dst++;
src++;
if (val == 0)
break;
}
return i;
}
/*
* Creates the MD4 Hash of the users password in NT UNICODE.
*/
int
E_md4hash(const unsigned char *passwd, unsigned char *p16)
{
int rc;
int len;
__u16 wpwd[129];
/* Password cannot be longer than 128 characters */
if (passwd) {
len = strlen((char *) passwd);
if (len > 128)
len = 128;
/* Password must be converted to NT unicode */
_my_mbstowcs(wpwd, passwd, len);
} else
len = 0;
wpwd[len] = 0; /* Ensure string is null terminated */
/* Calculate length in bytes */
len = _my_wcslen(wpwd) * sizeof(__u16);
rc = mdfour(p16, (unsigned char *) wpwd, len);
memset(wpwd, 0, 129 * 2);
return rc;
}
#if 0 /* currently unused */
/* Does both the NT and LM owfs of a user's password */
static void
nt_lm_owf_gen(char *pwd, unsigned char nt_p16[16], unsigned char p16[16])
{
char passwd[514];
memset(passwd, '\0', 514);
if (strlen(pwd) < 513)
strcpy(passwd, pwd);
else
memcpy(passwd, pwd, 512);
/* Calculate the MD4 hash (NT compatible) of the password */
memset(nt_p16, '\0', 16);
E_md4hash(passwd, nt_p16);
/* Mangle the passwords into Lanman format */
passwd[14] = '\0';
/* strupper(passwd); */
/* Calculate the SMB (lanman) hash functions of the password */
memset(p16, '\0', 16);
E_P16((unsigned char *) passwd, (unsigned char *) p16);
/* clear out local copy of user's password (just being paranoid). */
memset(passwd, '\0', sizeof(passwd));
}
#endif
/* Does the NTLMv2 owfs of a user's password */
#if 0 /* function not needed yet - but will be soon */
static void
ntv2_owf_gen(const unsigned char owf[16], const char *user_n,
const char *domain_n, unsigned char kr_buf[16],
const struct nls_table *nls_codepage)
{
wchar_t *user_u;
wchar_t *dom_u;
int user_l, domain_l;
struct HMACMD5Context ctx;
/* might as well do one alloc to hold both (user_u and dom_u) */
user_u = kmalloc(2048 * sizeof(wchar_t), GFP_KERNEL);
if (user_u == NULL)
return;
dom_u = user_u + 1024;
/* push_ucs2(NULL, user_u, user_n, (user_l+1)*2,
STR_UNICODE|STR_NOALIGN|STR_TERMINATE|STR_UPPER);
push_ucs2(NULL, dom_u, domain_n, (domain_l+1)*2,
STR_UNICODE|STR_NOALIGN|STR_TERMINATE|STR_UPPER); */
/* BB user and domain may need to be uppercased */
user_l = cifs_strtoUCS(user_u, user_n, 511, nls_codepage);
domain_l = cifs_strtoUCS(dom_u, domain_n, 511, nls_codepage);
user_l++; /* trailing null */
domain_l++;
hmac_md5_init_limK_to_64(owf, 16, &ctx);
hmac_md5_update((const unsigned char *) user_u, user_l * 2, &ctx);
hmac_md5_update((const unsigned char *) dom_u, domain_l * 2, &ctx);
hmac_md5_final(kr_buf, &ctx);
kfree(user_u);
}
#endif
/* Does the des encryption from the FIRST 8 BYTES of the NT or LM MD4 hash. */
#if 0 /* currently unused */
static void
NTLMSSPOWFencrypt(unsigned char passwd[8],
unsigned char *ntlmchalresp, unsigned char p24[24])
{
unsigned char p21[21];
memset(p21, '\0', 21);
memcpy(p21, passwd, 8);
memset(p21 + 8, 0xbd, 8);
E_P24(p21, ntlmchalresp, p24);
}
#endif
/* Does the NT MD4 hash then des encryption. */
int
SMBNTencrypt(unsigned char *passwd, unsigned char *c8, unsigned char *p24)
{
int rc;
unsigned char p16[16], p21[21];
memset(p16, '\0', 16);
memset(p21, '\0', 21);
rc = E_md4hash(passwd, p16);
if (rc) {
cFYI(1, "%s Can't generate NT hash, error: %d", __func__, rc);
return rc;
}
memcpy(p21, p16, 16);
rc = E_P24(p21, c8, p24);
return rc;
}
/* Does the md5 encryption from the NT hash for NTLMv2. */
/* These routines will be needed later */
#if 0
static void
SMBOWFencrypt_ntv2(const unsigned char kr[16],
const struct data_blob *srv_chal,
const struct data_blob *cli_chal, unsigned char resp_buf[16])
{
struct HMACMD5Context ctx;
hmac_md5_init_limK_to_64(kr, 16, &ctx);
hmac_md5_update(srv_chal->data, srv_chal->length, &ctx);
hmac_md5_update(cli_chal->data, cli_chal->length, &ctx);
hmac_md5_final(resp_buf, &ctx);
}
static void
SMBsesskeygen_ntv2(const unsigned char kr[16],
const unsigned char *nt_resp, __u8 sess_key[16])
{
struct HMACMD5Context ctx;
hmac_md5_init_limK_to_64(kr, 16, &ctx);
hmac_md5_update(nt_resp, 16, &ctx);
hmac_md5_final((unsigned char *) sess_key, &ctx);
}
static void
SMBsesskeygen_ntv1(const unsigned char kr[16],
const unsigned char *nt_resp, __u8 sess_key[16])
{
mdfour((unsigned char *) sess_key, (unsigned char *) kr, 16);
}
#endif
| gpl-2.0 |
andyvand/android_kernel_samsung_crespo | arch/powerpc/platforms/pasemi/setup.c | 2733 | 10989 | /*
* Copyright (C) 2006-2007 PA Semi, Inc
*
* Authors: Kip Walker, PA Semi
* Olof Johansson, PA Semi
*
* Maintained by: Olof Johansson <olof@lixom.net>
*
* Based on arch/powerpc/platforms/maple/setup.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/console.h>
#include <linux/pci.h>
#include <linux/of_platform.h>
#include <linux/gfp.h>
#include <asm/prom.h>
#include <asm/system.h>
#include <asm/iommu.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>
#include <asm/time.h>
#include <asm/mmu.h>
#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/ds.h>
#include "pasemi.h"
/* SDC reset register, must be pre-mapped at reset time */
static void __iomem *reset_reg;
/* Various error status registers, must be pre-mapped at MCE time */
#define MAX_MCE_REGS 32
struct mce_regs {
char *name;
void __iomem *addr;
};
static struct mce_regs mce_regs[MAX_MCE_REGS];
static int num_mce_regs;
static int nmi_virq = NO_IRQ;
static void pas_restart(char *cmd)
{
/* Need to put others cpu in hold loop so they're not sleeping */
smp_send_stop();
udelay(10000);
printk("Restarting...\n");
while (1)
out_le32(reset_reg, 0x6000000);
}
#ifdef CONFIG_SMP
static arch_spinlock_t timebase_lock;
static unsigned long timebase;
static void __devinit pas_give_timebase(void)
{
unsigned long flags;
local_irq_save(flags);
hard_irq_disable();
arch_spin_lock(&timebase_lock);
mtspr(SPRN_TBCTL, TBCTL_FREEZE);
isync();
timebase = get_tb();
arch_spin_unlock(&timebase_lock);
while (timebase)
barrier();
mtspr(SPRN_TBCTL, TBCTL_RESTART);
local_irq_restore(flags);
}
static void __devinit pas_take_timebase(void)
{
while (!timebase)
smp_rmb();
arch_spin_lock(&timebase_lock);
set_tb(timebase >> 32, timebase & 0xffffffff);
timebase = 0;
arch_spin_unlock(&timebase_lock);
}
struct smp_ops_t pas_smp_ops = {
.probe = smp_mpic_probe,
.message_pass = smp_mpic_message_pass,
.kick_cpu = smp_generic_kick_cpu,
.setup_cpu = smp_mpic_setup_cpu,
.give_timebase = pas_give_timebase,
.take_timebase = pas_take_timebase,
};
#endif /* CONFIG_SMP */
void __init pas_setup_arch(void)
{
#ifdef CONFIG_SMP
/* Setup SMP callback */
smp_ops = &pas_smp_ops;
#endif
/* Lookup PCI hosts */
pas_pci_init();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
/* Remap SDC register for doing reset */
/* XXXOJN This should maybe come out of the device tree */
reset_reg = ioremap(0xfc101100, 4);
}
static int __init pas_setup_mce_regs(void)
{
struct pci_dev *dev;
int reg;
/* Remap various SoC status registers for use by the MCE handler */
reg = 0;
dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
while (dev && reg < MAX_MCE_REGS) {
mce_regs[reg].name = kasprintf(GFP_KERNEL,
"mc%d_mcdebug_errsta", reg);
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
reg++;
}
dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
if (dev && reg+4 < MAX_MCE_REGS) {
mce_regs[reg].name = "iobdbg_IntStatus1";
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
reg++;
mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
reg++;
mce_regs[reg].name = "iobiom_IntStatus";
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
reg++;
mce_regs[reg].name = "iobiom_IntDbgReg";
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
reg++;
}
dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
if (dev && reg+2 < MAX_MCE_REGS) {
mce_regs[reg].name = "l2csts_IntStatus";
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
reg++;
mce_regs[reg].name = "l2csts_Cnt";
mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
reg++;
}
num_mce_regs = reg;
return 0;
}
machine_device_initcall(pasemi, pas_setup_mce_regs);
static __init void pas_init_IRQ(void)
{
struct device_node *np;
struct device_node *root, *mpic_node;
unsigned long openpic_addr;
const unsigned int *opprop;
int naddr, opplen;
int mpic_flags;
const unsigned int *nmiprop;
struct mpic *mpic;
mpic_node = NULL;
for_each_node_by_type(np, "interrupt-controller")
if (of_device_is_compatible(np, "open-pic")) {
mpic_node = np;
break;
}
if (!mpic_node)
for_each_node_by_type(np, "open-pic") {
mpic_node = np;
break;
}
if (!mpic_node) {
printk(KERN_ERR
"Failed to locate the MPIC interrupt controller\n");
return;
}
/* Find address list in /platform-open-pic */
root = of_find_node_by_path("/");
naddr = of_n_addr_cells(root);
opprop = of_get_property(root, "platform-open-pic", &opplen);
if (!opprop) {
printk(KERN_ERR "No platform-open-pic property.\n");
of_node_put(root);
return;
}
openpic_addr = of_read_number(opprop, naddr);
printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
if (nmiprop)
mpic_flags |= MPIC_ENABLE_MCK;
mpic = mpic_alloc(mpic_node, openpic_addr,
mpic_flags, 0, 0, "PASEMI-OPIC");
BUG_ON(!mpic);
mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
mpic_init(mpic);
/* The NMI/MCK source needs to be prio 15 */
if (nmiprop) {
nmi_virq = irq_create_mapping(NULL, *nmiprop);
mpic_irq_set_priority(nmi_virq, 15);
irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
mpic_unmask_irq(irq_get_irq_data(nmi_virq));
}
of_node_put(mpic_node);
of_node_put(root);
}
static void __init pas_progress(char *s, unsigned short hex)
{
printk("[%04x] : %s\n", hex, s ? s : "");
}
static int pas_machine_check_handler(struct pt_regs *regs)
{
int cpu = smp_processor_id();
unsigned long srr0, srr1, dsisr;
int dump_slb = 0;
int i;
srr0 = regs->nip;
srr1 = regs->msr;
if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
printk(KERN_ERR "NMI delivered\n");
debugger(regs);
mpic_end_irq(irq_get_irq_data(nmi_virq));
goto out;
}
dsisr = mfspr(SPRN_DSISR);
printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
mfspr(SPRN_PA6T_MER));
printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
mfspr(SPRN_PA6T_DER));
printk(KERN_ERR "Cause:\n");
if (srr1 & 0x200000)
printk(KERN_ERR "Signalled by SDC\n");
if (srr1 & 0x100000) {
printk(KERN_ERR "Load/Store detected error:\n");
if (dsisr & 0x8000)
printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
if (dsisr & 0x4000)
printk(KERN_ERR "LSU snoop response error\n");
if (dsisr & 0x2000) {
printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
dump_slb = 1;
}
if (dsisr & 0x1000)
printk(KERN_ERR "Recoverable Duptags\n");
if (dsisr & 0x800)
printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
if (dsisr & 0x400)
printk(KERN_ERR "TLB parity error count overflow\n");
}
if (srr1 & 0x80000)
printk(KERN_ERR "Bus Error\n");
if (srr1 & 0x40000) {
printk(KERN_ERR "I-side SLB multiple hit\n");
dump_slb = 1;
}
if (srr1 & 0x20000)
printk(KERN_ERR "I-cache parity error hit\n");
if (num_mce_regs == 0)
printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
else
printk(KERN_ERR "SoC debug registers:\n");
for (i = 0; i < num_mce_regs; i++)
printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
in_le32(mce_regs[i].addr));
if (dump_slb) {
unsigned long e, v;
int i;
printk(KERN_ERR "slb contents:\n");
for (i = 0; i < mmu_slb_size; i++) {
asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
}
}
out:
/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
return !!(srr1 & 0x2);
}
static void __init pas_init_early(void)
{
iommu_init_early_pasemi();
}
#ifdef CONFIG_PCMCIA
static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
void *data)
{
struct device *dev = data;
struct device *parent;
struct pcmcia_device *pdev = to_pcmcia_dev(dev);
/* We are only intereted in device addition */
if (action != BUS_NOTIFY_ADD_DEVICE)
return 0;
parent = pdev->socket->dev.parent;
/* We know electra_cf devices will always have of_node set, since
* electra_cf is an of_platform driver.
*/
if (!parent->of_node)
return 0;
if (!of_device_is_compatible(parent->of_node, "electra-cf"))
return 0;
/* We use the direct ops for localbus */
dev->archdata.dma_ops = &dma_direct_ops;
return 0;
}
static struct notifier_block pcmcia_notifier = {
.notifier_call = pcmcia_notify,
};
static inline void pasemi_pcmcia_init(void)
{
extern struct bus_type pcmcia_bus_type;
bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
}
#else
static inline void pasemi_pcmcia_init(void)
{
}
#endif
static struct of_device_id pasemi_bus_ids[] = {
/* Unfortunately needed for legacy firmwares */
{ .type = "localbus", },
{ .type = "sdc", },
/* These are the proper entries, which newer firmware uses */
{ .compatible = "pasemi,localbus", },
{ .compatible = "pasemi,sdc", },
{},
};
static int __init pasemi_publish_devices(void)
{
pasemi_pcmcia_init();
/* Publish OF platform devices for SDC and other non-PCI devices */
of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
return 0;
}
machine_device_initcall(pasemi, pasemi_publish_devices);
/*
* Called very early, MMU is off, device-tree isn't unflattened
*/
static int __init pas_probe(void)
{
unsigned long root = of_get_flat_dt_root();
if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
!of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
return 0;
hpte_init_native();
alloc_iobmap_l2();
return 1;
}
define_machine(pasemi) {
.name = "PA Semi PWRficient",
.probe = pas_probe,
.setup_arch = pas_setup_arch,
.init_early = pas_init_early,
.init_IRQ = pas_init_IRQ,
.get_irq = mpic_get_irq,
.restart = pas_restart,
.get_boot_time = pas_get_boot_time,
.calibrate_decr = generic_calibrate_decr,
.progress = pas_progress,
.machine_check_exception = pas_machine_check_handler,
};
| gpl-2.0 |
dragonpt/Kernel_3.4.67_KK_Wiko_DarkMoon | arch/mips/alchemy/common/dbdma.c | 4781 | 32266 | /*
*
* BRIEF MODULE DESCRIPTION
* The Descriptor Based DMA channel manager that first appeared
* on the Au1550. I started with dma.c, but I think all that is
* left is this initial comment :-)
*
* Copyright 2004 Embedded Edge, LLC
* dan@embeddededge.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/syscore_ops.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
/*
* The Descriptor Based DMA supports up to 16 channels.
*
* There are 32 devices defined. We keep an internal structure
* of devices using these channels, along with additional
* information.
*
* We allocate the descriptors and allow access to them through various
* functions. The drivers allocate the data buffers and assign them
* to the descriptors.
*/
static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
/* I couldn't find a macro that did this... */
#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
static dbdma_global_t *dbdma_gptr =
(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
static int dbdma_initialized;
static dbdev_tab_t *dbdev_tab;
static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
/* UARTS */
{ AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
{ AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
{ AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
{ AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
/* EXT DMA */
{ AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
/* USB DEV */
{ AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
/* PSCs */
{ AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
{ AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
/* MAC 0 */
{ AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
/* MAC 1 */
{ AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
{ AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
{ AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
{ AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
{ AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
{ AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
{ AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
{ AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
{ AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
{ AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
{ AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
{ AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
{ AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
{ AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
{ AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
{ AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
{ AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
{ AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
{ AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
{ AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
{ AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
{ AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
{ AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
/* 32 predefined plus 32 custom */
#define DBDEV_TAB_SIZE 64
static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
static dbdev_tab_t *find_dbdev_id(u32 id)
{
int i;
dbdev_tab_t *p;
for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
p = &dbdev_tab[i];
if (p->dev_id == id)
return p;
}
return NULL;
}
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
{
return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
}
EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
{
u32 ret = 0;
dbdev_tab_t *p;
static u16 new_id = 0x1000;
p = find_dbdev_id(~0);
if (NULL != p) {
memcpy(p, dev, sizeof(dbdev_tab_t));
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
ret = p->dev_id;
new_id++;
#if 0
printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
p->dev_id, p->dev_flags, p->dev_physaddr);
#endif
}
return ret;
}
EXPORT_SYMBOL(au1xxx_ddma_add_device);
void au1xxx_ddma_del_device(u32 devid)
{
dbdev_tab_t *p = find_dbdev_id(devid);
if (p != NULL) {
memset(p, 0, sizeof(dbdev_tab_t));
p->dev_id = ~0;
}
}
EXPORT_SYMBOL(au1xxx_ddma_del_device);
/* Allocate a channel and return a non-zero descriptor if successful. */
u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
void (*callback)(int, void *), void *callparam)
{
unsigned long flags;
u32 used, chan;
u32 dcp;
int i;
dbdev_tab_t *stp, *dtp;
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
/*
* We do the intialization on the first channel allocation.
* We have to wait because of the interrupt handler initialization
* which can't be done successfully during board set up.
*/
if (!dbdma_initialized)
return 0;
stp = find_dbdev_id(srcid);
if (stp == NULL)
return 0;
dtp = find_dbdev_id(destid);
if (dtp == NULL)
return 0;
used = 0;
/* Check to see if we can get both channels. */
spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
(stp->dev_flags & DEV_FLAGS_ANYUSE)) {
/* Got source */
stp->dev_flags |= DEV_FLAGS_INUSE;
if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
(dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
/* Got destination */
dtp->dev_flags |= DEV_FLAGS_INUSE;
} else {
/* Can't get dest. Release src. */
stp->dev_flags &= ~DEV_FLAGS_INUSE;
used++;
}
} else
used++;
spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
if (used)
return 0;
/* Let's see if we can allocate a channel for it. */
ctp = NULL;
chan = 0;
spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
for (i = 0; i < NUM_DBDMA_CHANS; i++)
if (chan_tab_ptr[i] == NULL) {
/*
* If kmalloc fails, it is caught below same
* as a channel not available.
*/
ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
chan_tab_ptr[i] = ctp;
break;
}
spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
if (ctp != NULL) {
memset(ctp, 0, sizeof(chan_tab_t));
ctp->chan_index = chan = i;
dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
dcp += (0x0100 * chan);
ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
cp = (au1x_dma_chan_t *)dcp;
ctp->chan_src = stp;
ctp->chan_dest = dtp;
ctp->chan_callback = callback;
ctp->chan_callparam = callparam;
/* Initialize channel configuration. */
i = 0;
if (stp->dev_intlevel)
i |= DDMA_CFG_SED;
if (stp->dev_intpolarity)
i |= DDMA_CFG_SP;
if (dtp->dev_intlevel)
i |= DDMA_CFG_DED;
if (dtp->dev_intpolarity)
i |= DDMA_CFG_DP;
if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
(dtp->dev_flags & DEV_FLAGS_SYNC))
i |= DDMA_CFG_SYNC;
cp->ddma_cfg = i;
au_sync();
/*
* Return a non-zero value that can be used to find the channel
* information in subsequent operations.
*/
return (u32)(&chan_tab_ptr[chan]);
}
/* Release devices */
stp->dev_flags &= ~DEV_FLAGS_INUSE;
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
return 0;
}
EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
/*
* Set the device width if source or destination is a FIFO.
* Should be 8, 16, or 32 bits.
*/
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
{
u32 rv;
chan_tab_t *ctp;
dbdev_tab_t *stp, *dtp;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
rv = 0;
if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
rv = stp->dev_devwidth;
stp->dev_devwidth = bits;
}
if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
rv = dtp->dev_devwidth;
dtp->dev_devwidth = bits;
}
return rv;
}
EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
/* Allocate a descriptor ring, initializing as much as possible. */
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
{
int i;
u32 desc_base, srcid, destid;
u32 cmd0, cmd1, src1, dest1;
u32 src0, dest0;
chan_tab_t *ctp;
dbdev_tab_t *stp, *dtp;
au1x_ddma_desc_t *dp;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
/*
* The descriptors must be 32-byte aligned. There is a
* possibility the allocation will give us such an address,
* and if we try that first we are likely to not waste larger
* slabs of memory.
*/
desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
GFP_KERNEL|GFP_DMA);
if (desc_base == 0)
return 0;
if (desc_base & 0x1f) {
/*
* Lost....do it again, allocate extra, and round
* the address base.
*/
kfree((const void *)desc_base);
i = entries * sizeof(au1x_ddma_desc_t);
i += (sizeof(au1x_ddma_desc_t) - 1);
desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
if (desc_base == 0)
return 0;
ctp->cdb_membase = desc_base;
desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
} else
ctp->cdb_membase = desc_base;
dp = (au1x_ddma_desc_t *)desc_base;
/* Keep track of the base descriptor. */
ctp->chan_desc_base = dp;
/* Initialize the rings with as much information as we know. */
srcid = stp->dev_id;
destid = dtp->dev_id;
cmd0 = cmd1 = src1 = dest1 = 0;
src0 = dest0 = 0;
cmd0 |= DSCR_CMD0_SID(srcid);
cmd0 |= DSCR_CMD0_DID(destid);
cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
/* Is it mem to mem transfer? */
if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
(DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
(DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
cmd0 |= DSCR_CMD0_MEM;
switch (stp->dev_devwidth) {
case 8:
cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
break;
case 16:
cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
break;
case 32:
default:
cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
break;
}
switch (dtp->dev_devwidth) {
case 8:
cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
break;
case 16:
cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
break;
case 32:
default:
cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
break;
}
/*
* If the device is marked as an in/out FIFO, ensure it is
* set non-coherent.
*/
if (stp->dev_flags & DEV_FLAGS_IN)
cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
if (dtp->dev_flags & DEV_FLAGS_OUT)
cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
/*
* Set up source1. For now, assume no stride and increment.
* A channel attribute update can change this later.
*/
switch (stp->dev_tsize) {
case 1:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
break;
case 2:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
break;
case 4:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
break;
case 8:
default:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
break;
}
/* If source input is FIFO, set static address. */
if (stp->dev_flags & DEV_FLAGS_IN) {
if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
else
src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
}
if (stp->dev_physaddr)
src0 = stp->dev_physaddr;
/*
* Set up dest1. For now, assume no stride and increment.
* A channel attribute update can change this later.
*/
switch (dtp->dev_tsize) {
case 1:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
break;
case 2:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
break;
case 4:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
break;
case 8:
default:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
break;
}
/* If destination output is FIFO, set static address. */
if (dtp->dev_flags & DEV_FLAGS_OUT) {
if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
else
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
}
if (dtp->dev_physaddr)
dest0 = dtp->dev_physaddr;
#if 0
printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
"source1:%x dest0:%x dest1:%x\n",
dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
src1, dest0, dest1);
#endif
for (i = 0; i < entries; i++) {
dp->dscr_cmd0 = cmd0;
dp->dscr_cmd1 = cmd1;
dp->dscr_source0 = src0;
dp->dscr_source1 = src1;
dp->dscr_dest0 = dest0;
dp->dscr_dest1 = dest1;
dp->dscr_stat = 0;
dp->sw_context = 0;
dp->sw_status = 0;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
dp++;
}
/* Make last descrptor point to the first. */
dp--;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
return (u32)ctp->chan_desc_base;
}
EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
/*
* Put a source buffer into the DMA ring.
* This updates the source pointer and byte count. Normally used
* for memory to fifo transfers.
*/
u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *(chan_tab_t **)chanid;
/*
* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/*
* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer address and byte count. */
dp->dscr_source0 = buf & ~0UL;
dp->dscr_cmd1 = nbytes;
/* Check flags */
if (flags & DDMA_FLAGS_IE)
dp->dscr_cmd0 |= DSCR_CMD0_IE;
if (flags & DDMA_FLAGS_NOIE)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
/*
* There is an errata on the Au1200/Au1550 parts that could result
* in "stale" data being DMA'ed. It has to do with the snoop logic on
* the cache eviction buffer. DMA_NONCOHERENT is on by default for
* these parts. If it is fixed in the future, these dma_cache_inv will
* just be nothing more than empty macros. See io.h.
*/
dma_cache_wback_inv((unsigned long)buf, nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return nbytes;
}
EXPORT_SYMBOL(au1xxx_dbdma_put_source);
/* Put a destination buffer into the DMA ring.
* This updates the destination pointer and byte count. Normally used
* to place an empty buffer into the ring for fifo to memory transfers.
*/
u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
/* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer address and byte count */
/* Check flags */
if (flags & DDMA_FLAGS_IE)
dp->dscr_cmd0 |= DSCR_CMD0_IE;
if (flags & DDMA_FLAGS_NOIE)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_dest0 = buf & ~0UL;
dp->dscr_cmd1 = nbytes;
#if 0
printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
#endif
/*
* There is an errata on the Au1200/Au1550 parts that could result in
* "stale" data being DMA'ed. It has to do with the snoop logic on the
* cache eviction buffer. DMA_NONCOHERENT is on by default for these
* parts. If it is fixed in the future, these dma_cache_inv will just
* be nothing more than empty macros. See io.h.
*/
dma_cache_inv((unsigned long)buf, nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return nbytes;
}
EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
/*
* Get a destination buffer into the DMA ring.
* Normally used to get a full buffer from the ring during fifo
* to memory transfers. This does not set the valid bit, you will
* have to put another destination buffer to keep the DMA going.
*/
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
u32 rv;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/*
* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->get_ptr;
/*
* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Return buffer address and byte count. */
*buf = (void *)(phys_to_virt(dp->dscr_dest0));
*nbytes = dp->dscr_cmd1;
rv = dp->dscr_stat;
/* Get next descriptor pointer. */
ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return rv;
}
EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
void au1xxx_dbdma_stop(u32 chanid)
{
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
int halt_timeout = 0;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
au_sync();
while (!(cp->ddma_stat & DDMA_STAT_H)) {
udelay(1);
halt_timeout++;
if (halt_timeout > 100) {
printk(KERN_WARNING "warning: DMA channel won't halt\n");
break;
}
}
/* clear current desc valid and doorbell */
cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
au_sync();
}
EXPORT_SYMBOL(au1xxx_dbdma_stop);
/*
* Start using the current descriptor pointer. If the DBDMA encounters
* a non-valid descriptor, it will stop. In this case, we can just
* continue by adding a buffer to the list and starting again.
*/
void au1xxx_dbdma_start(u32 chanid)
{
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
au_sync();
cp->ddma_dbell = 0;
au_sync();
}
EXPORT_SYMBOL(au1xxx_dbdma_start);
void au1xxx_dbdma_reset(u32 chanid)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
au1xxx_dbdma_stop(chanid);
ctp = *((chan_tab_t **)chanid);
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
/* Run through the descriptors and reset the valid indicator. */
dp = ctp->chan_desc_base;
do {
dp->dscr_cmd0 &= ~DSCR_CMD0_V;
/*
* Reset our software status -- this is used to determine
* if a descriptor is in use by upper level software. Since
* posting can reset 'V' bit.
*/
dp->sw_status = 0;
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
} while (dp != ctp->chan_desc_base);
}
EXPORT_SYMBOL(au1xxx_dbdma_reset);
u32 au1xxx_get_dma_residue(u32 chanid)
{
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
u32 rv;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
/* This is only valid if the channel is stopped. */
rv = cp->ddma_bytecnt;
au_sync();
return rv;
}
EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
void au1xxx_dbdma_chan_free(u32 chanid)
{
chan_tab_t *ctp;
dbdev_tab_t *stp, *dtp;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
au1xxx_dbdma_stop(chanid);
kfree((void *)ctp->cdb_membase);
stp->dev_flags &= ~DEV_FLAGS_INUSE;
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
chan_tab_ptr[ctp->chan_index] = NULL;
kfree(ctp);
}
EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
{
u32 intstat;
u32 chan_index;
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
au1x_dma_chan_t *cp;
intstat = dbdma_gptr->ddma_intstat;
au_sync();
chan_index = __ffs(intstat);
ctp = chan_tab_ptr[chan_index];
cp = ctp->chan_ptr;
dp = ctp->cur_ptr;
/* Reset interrupt. */
cp->ddma_irq = 0;
au_sync();
if (ctp->chan_callback)
ctp->chan_callback(irq, ctp->chan_callparam);
ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
return IRQ_RETVAL(1);
}
void au1xxx_dbdma_dump(u32 chanid)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
dbdev_tab_t *stp, *dtp;
au1x_dma_chan_t *cp;
u32 i = 0;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
cp = ctp->chan_ptr;
printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
(u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
dtp - dbdev_tab);
printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
(u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
(u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
cp->ddma_bytecnt);
/* Run through the descriptors */
dp = ctp->chan_desc_base;
do {
printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
dp->dscr_source0, dp->dscr_source1,
dp->dscr_dest0, dp->dscr_dest1);
printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
dp->dscr_stat, dp->dscr_nxtptr);
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
} while (dp != ctp->chan_desc_base);
}
/* Put a descriptor into the DMA ring.
* This updates the source/destination pointers and byte count.
*/
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
u32 nbytes = 0;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/*
* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/*
* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer addresses and byte count. */
dp->dscr_dest0 = dscr->dscr_dest0;
dp->dscr_source0 = dscr->dscr_source0;
dp->dscr_dest1 = dscr->dscr_dest1;
dp->dscr_source1 = dscr->dscr_source1;
dp->dscr_cmd1 = dscr->dscr_cmd1;
nbytes = dscr->dscr_cmd1;
/* Allow the caller to specifiy if an interrupt is generated */
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return nbytes;
}
static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
static int alchemy_dbdma_suspend(void)
{
int i;
void __iomem *addr;
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
/* save channel configurations */
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
/* halt channel */
__raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
wmb();
while (!(__raw_readl(addr + 0x14) & 1))
wmb();
addr += 0x100; /* next channel base */
}
/* disable channel interrupts */
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
__raw_writel(0, addr + 0x0c);
wmb();
return 0;
}
static void alchemy_dbdma_resume(void)
{
int i;
void __iomem *addr;
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
__raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
__raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
__raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
__raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
/* restore channel configurations */
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
__raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
__raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
__raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
__raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
__raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
__raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
wmb();
addr += 0x100; /* next channel base */
}
}
static struct syscore_ops alchemy_dbdma_syscore_ops = {
.suspend = alchemy_dbdma_suspend,
.resume = alchemy_dbdma_resume,
};
static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
{
int ret;
dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);
if (!dbdev_tab)
return -ENOMEM;
memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
dbdev_tab[ret].dev_id = ~0;
dbdma_gptr->ddma_config = 0;
dbdma_gptr->ddma_throttle = 0;
dbdma_gptr->ddma_inten = 0xffff;
au_sync();
ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
if (ret)
printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
else {
dbdma_initialized = 1;
register_syscore_ops(&alchemy_dbdma_syscore_ops);
}
return ret;
}
static int __init alchemy_dbdma_init(void)
{
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1550:
return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
case ALCHEMY_CPU_AU1200:
return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
case ALCHEMY_CPU_AU1300:
return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
}
return 0;
}
subsys_initcall(alchemy_dbdma_init);
| gpl-2.0 |
xjljian/android_kernel_huawei_msm8226 | tools/perf/builtin-top.c | 4781 | 34913 | /*
* builtin-top.c
*
* Builtin top command: Display a continuously updated profile of
* any workload, CPU or specific PID.
*
* Copyright (C) 2008, Red Hat Inc, Ingo Molnar <mingo@redhat.com>
* 2011, Red Hat Inc, Arnaldo Carvalho de Melo <acme@redhat.com>
*
* Improvements and fixes by:
*
* Arjan van de Ven <arjan@linux.intel.com>
* Yanmin Zhang <yanmin.zhang@intel.com>
* Wu Fengguang <fengguang.wu@intel.com>
* Mike Galbraith <efault@gmx.de>
* Paul Mackerras <paulus@samba.org>
*
* Released under the GPL v2. (and only v2, not any later version)
*/
#include "builtin.h"
#include "perf.h"
#include "util/annotate.h"
#include "util/cache.h"
#include "util/color.h"
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/session.h"
#include "util/symbol.h"
#include "util/thread.h"
#include "util/thread_map.h"
#include "util/top.h"
#include "util/util.h"
#include <linux/rbtree.h>
#include "util/parse-options.h"
#include "util/parse-events.h"
#include "util/cpumap.h"
#include "util/xyarray.h"
#include "util/sort.h"
#include "util/debug.h"
#include <assert.h>
#include <elf.h>
#include <fcntl.h>
#include <stdio.h>
#include <termios.h>
#include <unistd.h>
#include <inttypes.h>
#include <errno.h>
#include <time.h>
#include <sched.h>
#include <sys/syscall.h>
#include <sys/ioctl.h>
#include <sys/poll.h>
#include <sys/prctl.h>
#include <sys/wait.h>
#include <sys/uio.h>
#include <sys/utsname.h>
#include <sys/mman.h>
#include <linux/unistd.h>
#include <linux/types.h>
void get_term_dimensions(struct winsize *ws)
{
char *s = getenv("LINES");
if (s != NULL) {
ws->ws_row = atoi(s);
s = getenv("COLUMNS");
if (s != NULL) {
ws->ws_col = atoi(s);
if (ws->ws_row && ws->ws_col)
return;
}
}
#ifdef TIOCGWINSZ
if (ioctl(1, TIOCGWINSZ, ws) == 0 &&
ws->ws_row && ws->ws_col)
return;
#endif
ws->ws_row = 25;
ws->ws_col = 80;
}
static void perf_top__update_print_entries(struct perf_top *top)
{
if (top->print_entries > 9)
top->print_entries -= 9;
}
static void perf_top__sig_winch(int sig __used, siginfo_t *info __used, void *arg)
{
struct perf_top *top = arg;
get_term_dimensions(&top->winsize);
if (!top->print_entries
|| (top->print_entries+4) > top->winsize.ws_row) {
top->print_entries = top->winsize.ws_row;
} else {
top->print_entries += 4;
top->winsize.ws_row = top->print_entries;
}
perf_top__update_print_entries(top);
}
static int perf_top__parse_source(struct perf_top *top, struct hist_entry *he)
{
struct symbol *sym;
struct annotation *notes;
struct map *map;
int err = -1;
if (!he || !he->ms.sym)
return -1;
sym = he->ms.sym;
map = he->ms.map;
/*
* We can't annotate with just /proc/kallsyms
*/
if (map->dso->symtab_type == SYMTAB__KALLSYMS) {
pr_err("Can't annotate %s: No vmlinux file was found in the "
"path\n", sym->name);
sleep(1);
return -1;
}
notes = symbol__annotation(sym);
if (notes->src != NULL) {
pthread_mutex_lock(¬es->lock);
goto out_assign;
}
pthread_mutex_lock(¬es->lock);
if (symbol__alloc_hist(sym) < 0) {
pthread_mutex_unlock(¬es->lock);
pr_err("Not enough memory for annotating '%s' symbol!\n",
sym->name);
sleep(1);
return err;
}
err = symbol__annotate(sym, map, 0);
if (err == 0) {
out_assign:
top->sym_filter_entry = he;
}
pthread_mutex_unlock(¬es->lock);
return err;
}
static void __zero_source_counters(struct hist_entry *he)
{
struct symbol *sym = he->ms.sym;
symbol__annotate_zero_histograms(sym);
}
static void ui__warn_map_erange(struct map *map, struct symbol *sym, u64 ip)
{
struct utsname uts;
int err = uname(&uts);
ui__warning("Out of bounds address found:\n\n"
"Addr: %" PRIx64 "\n"
"DSO: %s %c\n"
"Map: %" PRIx64 "-%" PRIx64 "\n"
"Symbol: %" PRIx64 "-%" PRIx64 " %c %s\n"
"Arch: %s\n"
"Kernel: %s\n"
"Tools: %s\n\n"
"Not all samples will be on the annotation output.\n\n"
"Please report to linux-kernel@vger.kernel.org\n",
ip, map->dso->long_name, dso__symtab_origin(map->dso),
map->start, map->end, sym->start, sym->end,
sym->binding == STB_GLOBAL ? 'g' :
sym->binding == STB_LOCAL ? 'l' : 'w', sym->name,
err ? "[unknown]" : uts.machine,
err ? "[unknown]" : uts.release, perf_version_string);
if (use_browser <= 0)
sleep(5);
map->erange_warned = true;
}
static void perf_top__record_precise_ip(struct perf_top *top,
struct hist_entry *he,
int counter, u64 ip)
{
struct annotation *notes;
struct symbol *sym;
int err;
if (he == NULL || he->ms.sym == NULL ||
((top->sym_filter_entry == NULL ||
top->sym_filter_entry->ms.sym != he->ms.sym) && use_browser != 1))
return;
sym = he->ms.sym;
notes = symbol__annotation(sym);
if (pthread_mutex_trylock(¬es->lock))
return;
if (notes->src == NULL && symbol__alloc_hist(sym) < 0) {
pthread_mutex_unlock(¬es->lock);
pr_err("Not enough memory for annotating '%s' symbol!\n",
sym->name);
sleep(1);
return;
}
ip = he->ms.map->map_ip(he->ms.map, ip);
err = symbol__inc_addr_samples(sym, he->ms.map, counter, ip);
pthread_mutex_unlock(¬es->lock);
if (err == -ERANGE && !he->ms.map->erange_warned)
ui__warn_map_erange(he->ms.map, sym, ip);
}
static void perf_top__show_details(struct perf_top *top)
{
struct hist_entry *he = top->sym_filter_entry;
struct annotation *notes;
struct symbol *symbol;
int more;
if (!he)
return;
symbol = he->ms.sym;
notes = symbol__annotation(symbol);
pthread_mutex_lock(¬es->lock);
if (notes->src == NULL)
goto out_unlock;
printf("Showing %s for %s\n", event_name(top->sym_evsel), symbol->name);
printf(" Events Pcnt (>=%d%%)\n", top->sym_pcnt_filter);
more = symbol__annotate_printf(symbol, he->ms.map, top->sym_evsel->idx,
0, top->sym_pcnt_filter, top->print_entries, 4);
if (top->zero)
symbol__annotate_zero_histogram(symbol, top->sym_evsel->idx);
else
symbol__annotate_decay_histogram(symbol, top->sym_evsel->idx);
if (more != 0)
printf("%d lines not displayed, maybe increase display entries [e]\n", more);
out_unlock:
pthread_mutex_unlock(¬es->lock);
}
static const char CONSOLE_CLEAR[] = "[H[2J";
static struct hist_entry *perf_evsel__add_hist_entry(struct perf_evsel *evsel,
struct addr_location *al,
struct perf_sample *sample)
{
struct hist_entry *he;
he = __hists__add_entry(&evsel->hists, al, NULL, sample->period);
if (he == NULL)
return NULL;
hists__inc_nr_events(&evsel->hists, PERF_RECORD_SAMPLE);
return he;
}
static void perf_top__print_sym_table(struct perf_top *top)
{
char bf[160];
int printed = 0;
const int win_width = top->winsize.ws_col - 1;
puts(CONSOLE_CLEAR);
perf_top__header_snprintf(top, bf, sizeof(bf));
printf("%s\n", bf);
perf_top__reset_sample_counters(top);
printf("%-*.*s\n", win_width, win_width, graph_dotted_line);
if (top->sym_evsel->hists.stats.nr_lost_warned !=
top->sym_evsel->hists.stats.nr_events[PERF_RECORD_LOST]) {
top->sym_evsel->hists.stats.nr_lost_warned =
top->sym_evsel->hists.stats.nr_events[PERF_RECORD_LOST];
color_fprintf(stdout, PERF_COLOR_RED,
"WARNING: LOST %d chunks, Check IO/CPU overload",
top->sym_evsel->hists.stats.nr_lost_warned);
++printed;
}
if (top->sym_filter_entry) {
perf_top__show_details(top);
return;
}
hists__collapse_resort_threaded(&top->sym_evsel->hists);
hists__output_resort_threaded(&top->sym_evsel->hists);
hists__decay_entries_threaded(&top->sym_evsel->hists,
top->hide_user_symbols,
top->hide_kernel_symbols);
hists__output_recalc_col_len(&top->sym_evsel->hists,
top->winsize.ws_row - 3);
putchar('\n');
hists__fprintf(&top->sym_evsel->hists, NULL, false, false,
top->winsize.ws_row - 4 - printed, win_width, stdout);
}
static void prompt_integer(int *target, const char *msg)
{
char *buf = malloc(0), *p;
size_t dummy = 0;
int tmp;
fprintf(stdout, "\n%s: ", msg);
if (getline(&buf, &dummy, stdin) < 0)
return;
p = strchr(buf, '\n');
if (p)
*p = 0;
p = buf;
while(*p) {
if (!isdigit(*p))
goto out_free;
p++;
}
tmp = strtoul(buf, NULL, 10);
*target = tmp;
out_free:
free(buf);
}
static void prompt_percent(int *target, const char *msg)
{
int tmp = 0;
prompt_integer(&tmp, msg);
if (tmp >= 0 && tmp <= 100)
*target = tmp;
}
static void perf_top__prompt_symbol(struct perf_top *top, const char *msg)
{
char *buf = malloc(0), *p;
struct hist_entry *syme = top->sym_filter_entry, *n, *found = NULL;
struct rb_node *next;
size_t dummy = 0;
/* zero counters of active symbol */
if (syme) {
__zero_source_counters(syme);
top->sym_filter_entry = NULL;
}
fprintf(stdout, "\n%s: ", msg);
if (getline(&buf, &dummy, stdin) < 0)
goto out_free;
p = strchr(buf, '\n');
if (p)
*p = 0;
next = rb_first(&top->sym_evsel->hists.entries);
while (next) {
n = rb_entry(next, struct hist_entry, rb_node);
if (n->ms.sym && !strcmp(buf, n->ms.sym->name)) {
found = n;
break;
}
next = rb_next(&n->rb_node);
}
if (!found) {
fprintf(stderr, "Sorry, %s is not active.\n", buf);
sleep(1);
} else
perf_top__parse_source(top, found);
out_free:
free(buf);
}
static void perf_top__print_mapped_keys(struct perf_top *top)
{
char *name = NULL;
if (top->sym_filter_entry) {
struct symbol *sym = top->sym_filter_entry->ms.sym;
name = sym->name;
}
fprintf(stdout, "\nMapped keys:\n");
fprintf(stdout, "\t[d] display refresh delay. \t(%d)\n", top->delay_secs);
fprintf(stdout, "\t[e] display entries (lines). \t(%d)\n", top->print_entries);
if (top->evlist->nr_entries > 1)
fprintf(stdout, "\t[E] active event counter. \t(%s)\n", event_name(top->sym_evsel));
fprintf(stdout, "\t[f] profile display filter (count). \t(%d)\n", top->count_filter);
fprintf(stdout, "\t[F] annotate display filter (percent). \t(%d%%)\n", top->sym_pcnt_filter);
fprintf(stdout, "\t[s] annotate symbol. \t(%s)\n", name?: "NULL");
fprintf(stdout, "\t[S] stop annotation.\n");
fprintf(stdout,
"\t[K] hide kernel_symbols symbols. \t(%s)\n",
top->hide_kernel_symbols ? "yes" : "no");
fprintf(stdout,
"\t[U] hide user symbols. \t(%s)\n",
top->hide_user_symbols ? "yes" : "no");
fprintf(stdout, "\t[z] toggle sample zeroing. \t(%d)\n", top->zero ? 1 : 0);
fprintf(stdout, "\t[qQ] quit.\n");
}
static int perf_top__key_mapped(struct perf_top *top, int c)
{
switch (c) {
case 'd':
case 'e':
case 'f':
case 'z':
case 'q':
case 'Q':
case 'K':
case 'U':
case 'F':
case 's':
case 'S':
return 1;
case 'E':
return top->evlist->nr_entries > 1 ? 1 : 0;
default:
break;
}
return 0;
}
static void perf_top__handle_keypress(struct perf_top *top, int c)
{
if (!perf_top__key_mapped(top, c)) {
struct pollfd stdin_poll = { .fd = 0, .events = POLLIN };
struct termios tc, save;
perf_top__print_mapped_keys(top);
fprintf(stdout, "\nEnter selection, or unmapped key to continue: ");
fflush(stdout);
tcgetattr(0, &save);
tc = save;
tc.c_lflag &= ~(ICANON | ECHO);
tc.c_cc[VMIN] = 0;
tc.c_cc[VTIME] = 0;
tcsetattr(0, TCSANOW, &tc);
poll(&stdin_poll, 1, -1);
c = getc(stdin);
tcsetattr(0, TCSAFLUSH, &save);
if (!perf_top__key_mapped(top, c))
return;
}
switch (c) {
case 'd':
prompt_integer(&top->delay_secs, "Enter display delay");
if (top->delay_secs < 1)
top->delay_secs = 1;
break;
case 'e':
prompt_integer(&top->print_entries, "Enter display entries (lines)");
if (top->print_entries == 0) {
struct sigaction act = {
.sa_sigaction = perf_top__sig_winch,
.sa_flags = SA_SIGINFO,
};
perf_top__sig_winch(SIGWINCH, NULL, top);
sigaction(SIGWINCH, &act, NULL);
} else {
perf_top__sig_winch(SIGWINCH, NULL, top);
signal(SIGWINCH, SIG_DFL);
}
break;
case 'E':
if (top->evlist->nr_entries > 1) {
/* Select 0 as the default event: */
int counter = 0;
fprintf(stderr, "\nAvailable events:");
list_for_each_entry(top->sym_evsel, &top->evlist->entries, node)
fprintf(stderr, "\n\t%d %s", top->sym_evsel->idx, event_name(top->sym_evsel));
prompt_integer(&counter, "Enter details event counter");
if (counter >= top->evlist->nr_entries) {
top->sym_evsel = list_entry(top->evlist->entries.next, struct perf_evsel, node);
fprintf(stderr, "Sorry, no such event, using %s.\n", event_name(top->sym_evsel));
sleep(1);
break;
}
list_for_each_entry(top->sym_evsel, &top->evlist->entries, node)
if (top->sym_evsel->idx == counter)
break;
} else
top->sym_evsel = list_entry(top->evlist->entries.next, struct perf_evsel, node);
break;
case 'f':
prompt_integer(&top->count_filter, "Enter display event count filter");
break;
case 'F':
prompt_percent(&top->sym_pcnt_filter,
"Enter details display event filter (percent)");
break;
case 'K':
top->hide_kernel_symbols = !top->hide_kernel_symbols;
break;
case 'q':
case 'Q':
printf("exiting.\n");
if (top->dump_symtab)
perf_session__fprintf_dsos(top->session, stderr);
exit(0);
case 's':
perf_top__prompt_symbol(top, "Enter details symbol");
break;
case 'S':
if (!top->sym_filter_entry)
break;
else {
struct hist_entry *syme = top->sym_filter_entry;
top->sym_filter_entry = NULL;
__zero_source_counters(syme);
}
break;
case 'U':
top->hide_user_symbols = !top->hide_user_symbols;
break;
case 'z':
top->zero = !top->zero;
break;
default:
break;
}
}
static void perf_top__sort_new_samples(void *arg)
{
struct perf_top *t = arg;
perf_top__reset_sample_counters(t);
if (t->evlist->selected != NULL)
t->sym_evsel = t->evlist->selected;
hists__collapse_resort_threaded(&t->sym_evsel->hists);
hists__output_resort_threaded(&t->sym_evsel->hists);
hists__decay_entries_threaded(&t->sym_evsel->hists,
t->hide_user_symbols,
t->hide_kernel_symbols);
}
static void *display_thread_tui(void *arg)
{
struct perf_evsel *pos;
struct perf_top *top = arg;
const char *help = "For a higher level overview, try: perf top --sort comm,dso";
perf_top__sort_new_samples(top);
/*
* Initialize the uid_filter_str, in the future the TUI will allow
* Zooming in/out UIDs. For now juse use whatever the user passed
* via --uid.
*/
list_for_each_entry(pos, &top->evlist->entries, node)
pos->hists.uid_filter_str = top->uid_str;
perf_evlist__tui_browse_hists(top->evlist, help,
perf_top__sort_new_samples,
top, top->delay_secs);
exit_browser(0);
exit(0);
return NULL;
}
static void *display_thread(void *arg)
{
struct pollfd stdin_poll = { .fd = 0, .events = POLLIN };
struct termios tc, save;
struct perf_top *top = arg;
int delay_msecs, c;
tcgetattr(0, &save);
tc = save;
tc.c_lflag &= ~(ICANON | ECHO);
tc.c_cc[VMIN] = 0;
tc.c_cc[VTIME] = 0;
pthread__unblock_sigwinch();
repeat:
delay_msecs = top->delay_secs * 1000;
tcsetattr(0, TCSANOW, &tc);
/* trash return*/
getc(stdin);
while (1) {
perf_top__print_sym_table(top);
/*
* Either timeout expired or we got an EINTR due to SIGWINCH,
* refresh screen in both cases.
*/
switch (poll(&stdin_poll, 1, delay_msecs)) {
case 0:
continue;
case -1:
if (errno == EINTR)
continue;
/* Fall trhu */
default:
goto process_hotkey;
}
}
process_hotkey:
c = getc(stdin);
tcsetattr(0, TCSAFLUSH, &save);
perf_top__handle_keypress(top, c);
goto repeat;
return NULL;
}
/* Tag samples to be skipped. */
static const char *skip_symbols[] = {
"intel_idle",
"default_idle",
"native_safe_halt",
"cpu_idle",
"enter_idle",
"exit_idle",
"mwait_idle",
"mwait_idle_with_hints",
"poll_idle",
"ppc64_runlatch_off",
"pseries_dedicated_idle_sleep",
NULL
};
static int symbol_filter(struct map *map __used, struct symbol *sym)
{
const char *name = sym->name;
int i;
/*
* ppc64 uses function descriptors and appends a '.' to the
* start of every instruction address. Remove it.
*/
if (name[0] == '.')
name++;
if (!strcmp(name, "_text") ||
!strcmp(name, "_etext") ||
!strcmp(name, "_sinittext") ||
!strncmp("init_module", name, 11) ||
!strncmp("cleanup_module", name, 14) ||
strstr(name, "_text_start") ||
strstr(name, "_text_end"))
return 1;
for (i = 0; skip_symbols[i]; i++) {
if (!strcmp(skip_symbols[i], name)) {
sym->ignore = true;
break;
}
}
return 0;
}
static void perf_event__process_sample(struct perf_tool *tool,
const union perf_event *event,
struct perf_evsel *evsel,
struct perf_sample *sample,
struct machine *machine)
{
struct perf_top *top = container_of(tool, struct perf_top, tool);
struct symbol *parent = NULL;
u64 ip = event->ip.ip;
struct addr_location al;
int err;
if (!machine && perf_guest) {
pr_err("Can't find guest [%d]'s kernel information\n",
event->ip.pid);
return;
}
if (!machine) {
pr_err("%u unprocessable samples recorded.",
top->session->hists.stats.nr_unprocessable_samples++);
return;
}
if (event->header.misc & PERF_RECORD_MISC_EXACT_IP)
top->exact_samples++;
if (perf_event__preprocess_sample(event, machine, &al, sample,
symbol_filter) < 0 ||
al.filtered)
return;
if (!top->kptr_restrict_warned &&
symbol_conf.kptr_restrict &&
al.cpumode == PERF_RECORD_MISC_KERNEL) {
ui__warning(
"Kernel address maps (/proc/{kallsyms,modules}) are restricted.\n\n"
"Check /proc/sys/kernel/kptr_restrict.\n\n"
"Kernel%s samples will not be resolved.\n",
!RB_EMPTY_ROOT(&al.map->dso->symbols[MAP__FUNCTION]) ?
" modules" : "");
if (use_browser <= 0)
sleep(5);
top->kptr_restrict_warned = true;
}
if (al.sym == NULL) {
const char *msg = "Kernel samples will not be resolved.\n";
/*
* As we do lazy loading of symtabs we only will know if the
* specified vmlinux file is invalid when we actually have a
* hit in kernel space and then try to load it. So if we get
* here and there are _no_ symbols in the DSO backing the
* kernel map, bail out.
*
* We may never get here, for instance, if we use -K/
* --hide-kernel-symbols, even if the user specifies an
* invalid --vmlinux ;-)
*/
if (!top->kptr_restrict_warned && !top->vmlinux_warned &&
al.map == machine->vmlinux_maps[MAP__FUNCTION] &&
RB_EMPTY_ROOT(&al.map->dso->symbols[MAP__FUNCTION])) {
if (symbol_conf.vmlinux_name) {
ui__warning("The %s file can't be used.\n%s",
symbol_conf.vmlinux_name, msg);
} else {
ui__warning("A vmlinux file was not found.\n%s",
msg);
}
if (use_browser <= 0)
sleep(5);
top->vmlinux_warned = true;
}
}
if (al.sym == NULL || !al.sym->ignore) {
struct hist_entry *he;
if ((sort__has_parent || symbol_conf.use_callchain) &&
sample->callchain) {
err = machine__resolve_callchain(machine, evsel, al.thread,
sample->callchain, &parent);
if (err)
return;
}
he = perf_evsel__add_hist_entry(evsel, &al, sample);
if (he == NULL) {
pr_err("Problem incrementing symbol period, skipping event\n");
return;
}
if (symbol_conf.use_callchain) {
err = callchain_append(he->callchain, &evsel->hists.callchain_cursor,
sample->period);
if (err)
return;
}
if (top->sort_has_symbols)
perf_top__record_precise_ip(top, he, evsel->idx, ip);
}
return;
}
static void perf_top__mmap_read_idx(struct perf_top *top, int idx)
{
struct perf_sample sample;
struct perf_evsel *evsel;
struct perf_session *session = top->session;
union perf_event *event;
struct machine *machine;
u8 origin;
int ret;
while ((event = perf_evlist__mmap_read(top->evlist, idx)) != NULL) {
ret = perf_session__parse_sample(session, event, &sample);
if (ret) {
pr_err("Can't parse sample, err = %d\n", ret);
continue;
}
evsel = perf_evlist__id2evsel(session->evlist, sample.id);
assert(evsel != NULL);
origin = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK;
if (event->header.type == PERF_RECORD_SAMPLE)
++top->samples;
switch (origin) {
case PERF_RECORD_MISC_USER:
++top->us_samples;
if (top->hide_user_symbols)
continue;
machine = perf_session__find_host_machine(session);
break;
case PERF_RECORD_MISC_KERNEL:
++top->kernel_samples;
if (top->hide_kernel_symbols)
continue;
machine = perf_session__find_host_machine(session);
break;
case PERF_RECORD_MISC_GUEST_KERNEL:
++top->guest_kernel_samples;
machine = perf_session__find_machine(session, event->ip.pid);
break;
case PERF_RECORD_MISC_GUEST_USER:
++top->guest_us_samples;
/*
* TODO: we don't process guest user from host side
* except simple counting.
*/
/* Fall thru */
default:
continue;
}
if (event->header.type == PERF_RECORD_SAMPLE) {
perf_event__process_sample(&top->tool, event, evsel,
&sample, machine);
} else if (event->header.type < PERF_RECORD_MAX) {
hists__inc_nr_events(&evsel->hists, event->header.type);
perf_event__process(&top->tool, event, &sample, machine);
} else
++session->hists.stats.nr_unknown_events;
}
}
static void perf_top__mmap_read(struct perf_top *top)
{
int i;
for (i = 0; i < top->evlist->nr_mmaps; i++)
perf_top__mmap_read_idx(top, i);
}
static void perf_top__start_counters(struct perf_top *top)
{
struct perf_evsel *counter, *first;
struct perf_evlist *evlist = top->evlist;
first = list_entry(evlist->entries.next, struct perf_evsel, node);
list_for_each_entry(counter, &evlist->entries, node) {
struct perf_event_attr *attr = &counter->attr;
struct xyarray *group_fd = NULL;
if (top->group && counter != first)
group_fd = first->fd;
attr->sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_TID;
if (top->freq) {
attr->sample_type |= PERF_SAMPLE_PERIOD;
attr->freq = 1;
attr->sample_freq = top->freq;
}
if (evlist->nr_entries > 1) {
attr->sample_type |= PERF_SAMPLE_ID;
attr->read_format |= PERF_FORMAT_ID;
}
if (symbol_conf.use_callchain)
attr->sample_type |= PERF_SAMPLE_CALLCHAIN;
attr->mmap = 1;
attr->comm = 1;
attr->inherit = top->inherit;
fallback_missing_features:
if (top->exclude_guest_missing)
attr->exclude_guest = attr->exclude_host = 0;
retry_sample_id:
attr->sample_id_all = top->sample_id_all_missing ? 0 : 1;
try_again:
if (perf_evsel__open(counter, top->evlist->cpus,
top->evlist->threads, top->group,
group_fd) < 0) {
int err = errno;
if (err == EPERM || err == EACCES) {
ui__error_paranoid();
goto out_err;
} else if (err == EINVAL) {
if (!top->exclude_guest_missing &&
(attr->exclude_guest || attr->exclude_host)) {
pr_debug("Old kernel, cannot exclude "
"guest or host samples.\n");
top->exclude_guest_missing = true;
goto fallback_missing_features;
} else if (!top->sample_id_all_missing) {
/*
* Old kernel, no attr->sample_id_type_all field
*/
top->sample_id_all_missing = true;
goto retry_sample_id;
}
}
/*
* If it's cycles then fall back to hrtimer
* based cpu-clock-tick sw counter, which
* is always available even if no PMU support:
*/
if (attr->type == PERF_TYPE_HARDWARE &&
attr->config == PERF_COUNT_HW_CPU_CYCLES) {
if (verbose)
ui__warning("Cycles event not supported,\n"
"trying to fall back to cpu-clock-ticks\n");
attr->type = PERF_TYPE_SOFTWARE;
attr->config = PERF_COUNT_SW_CPU_CLOCK;
goto try_again;
}
if (err == ENOENT) {
ui__warning("The %s event is not supported.\n",
event_name(counter));
goto out_err;
} else if (err == EMFILE) {
ui__warning("Too many events are opened.\n"
"Try again after reducing the number of events\n");
goto out_err;
}
ui__warning("The sys_perf_event_open() syscall "
"returned with %d (%s). /bin/dmesg "
"may provide additional information.\n"
"No CONFIG_PERF_EVENTS=y kernel support "
"configured?\n", err, strerror(err));
goto out_err;
}
}
if (perf_evlist__mmap(evlist, top->mmap_pages, false) < 0) {
ui__warning("Failed to mmap with %d (%s)\n",
errno, strerror(errno));
goto out_err;
}
return;
out_err:
exit_browser(0);
exit(0);
}
static int perf_top__setup_sample_type(struct perf_top *top)
{
if (!top->sort_has_symbols) {
if (symbol_conf.use_callchain) {
ui__warning("Selected -g but \"sym\" not present in --sort/-s.");
return -EINVAL;
}
} else if (!top->dont_use_callchains && callchain_param.mode != CHAIN_NONE) {
if (callchain_register_param(&callchain_param) < 0) {
ui__warning("Can't register callchain params.\n");
return -EINVAL;
}
}
return 0;
}
static int __cmd_top(struct perf_top *top)
{
pthread_t thread;
int ret;
/*
* FIXME: perf_session__new should allow passing a O_MMAP, so that all this
* mmap reading, etc is encapsulated in it. Use O_WRONLY for now.
*/
top->session = perf_session__new(NULL, O_WRONLY, false, false, NULL);
if (top->session == NULL)
return -ENOMEM;
ret = perf_top__setup_sample_type(top);
if (ret)
goto out_delete;
if (top->target_tid || top->uid != UINT_MAX)
perf_event__synthesize_thread_map(&top->tool, top->evlist->threads,
perf_event__process,
&top->session->host_machine);
else
perf_event__synthesize_threads(&top->tool, perf_event__process,
&top->session->host_machine);
perf_top__start_counters(top);
top->session->evlist = top->evlist;
perf_session__update_sample_type(top->session);
/* Wait for a minimal set of events before starting the snapshot */
poll(top->evlist->pollfd, top->evlist->nr_fds, 100);
perf_top__mmap_read(top);
if (pthread_create(&thread, NULL, (use_browser > 0 ? display_thread_tui :
display_thread), top)) {
printf("Could not create display thread.\n");
exit(-1);
}
if (top->realtime_prio) {
struct sched_param param;
param.sched_priority = top->realtime_prio;
if (sched_setscheduler(0, SCHED_FIFO, ¶m)) {
printf("Could not set realtime priority.\n");
exit(-1);
}
}
while (1) {
u64 hits = top->samples;
perf_top__mmap_read(top);
if (hits == top->samples)
ret = poll(top->evlist->pollfd, top->evlist->nr_fds, 100);
}
out_delete:
perf_session__delete(top->session);
top->session = NULL;
return 0;
}
static int
parse_callchain_opt(const struct option *opt, const char *arg, int unset)
{
struct perf_top *top = (struct perf_top *)opt->value;
char *tok, *tok2;
char *endptr;
/*
* --no-call-graph
*/
if (unset) {
top->dont_use_callchains = true;
return 0;
}
symbol_conf.use_callchain = true;
if (!arg)
return 0;
tok = strtok((char *)arg, ",");
if (!tok)
return -1;
/* get the output mode */
if (!strncmp(tok, "graph", strlen(arg)))
callchain_param.mode = CHAIN_GRAPH_ABS;
else if (!strncmp(tok, "flat", strlen(arg)))
callchain_param.mode = CHAIN_FLAT;
else if (!strncmp(tok, "fractal", strlen(arg)))
callchain_param.mode = CHAIN_GRAPH_REL;
else if (!strncmp(tok, "none", strlen(arg))) {
callchain_param.mode = CHAIN_NONE;
symbol_conf.use_callchain = false;
return 0;
} else
return -1;
/* get the min percentage */
tok = strtok(NULL, ",");
if (!tok)
goto setup;
callchain_param.min_percent = strtod(tok, &endptr);
if (tok == endptr)
return -1;
/* get the print limit */
tok2 = strtok(NULL, ",");
if (!tok2)
goto setup;
if (tok2[0] != 'c') {
callchain_param.print_limit = strtod(tok2, &endptr);
tok2 = strtok(NULL, ",");
if (!tok2)
goto setup;
}
/* get the call chain order */
if (!strcmp(tok2, "caller"))
callchain_param.order = ORDER_CALLER;
else if (!strcmp(tok2, "callee"))
callchain_param.order = ORDER_CALLEE;
else
return -1;
setup:
if (callchain_register_param(&callchain_param) < 0) {
fprintf(stderr, "Can't register callchain params\n");
return -1;
}
return 0;
}
static const char * const top_usage[] = {
"perf top [<options>]",
NULL
};
int cmd_top(int argc, const char **argv, const char *prefix __used)
{
struct perf_evsel *pos;
int status = -ENOMEM;
struct perf_top top = {
.count_filter = 5,
.delay_secs = 2,
.uid = UINT_MAX,
.freq = 1000, /* 1 KHz */
.mmap_pages = 128,
.sym_pcnt_filter = 5,
};
char callchain_default_opt[] = "fractal,0.5,callee";
const struct option options[] = {
OPT_CALLBACK('e', "event", &top.evlist, "event",
"event selector. use 'perf list' to list available events",
parse_events_option),
OPT_INTEGER('c', "count", &top.default_interval,
"event period to sample"),
OPT_STRING('p', "pid", &top.target_pid, "pid",
"profile events on existing process id"),
OPT_STRING('t', "tid", &top.target_tid, "tid",
"profile events on existing thread id"),
OPT_BOOLEAN('a', "all-cpus", &top.system_wide,
"system-wide collection from all CPUs"),
OPT_STRING('C', "cpu", &top.cpu_list, "cpu",
"list of cpus to monitor"),
OPT_STRING('k', "vmlinux", &symbol_conf.vmlinux_name,
"file", "vmlinux pathname"),
OPT_BOOLEAN('K', "hide_kernel_symbols", &top.hide_kernel_symbols,
"hide kernel symbols"),
OPT_UINTEGER('m', "mmap-pages", &top.mmap_pages, "number of mmap data pages"),
OPT_INTEGER('r', "realtime", &top.realtime_prio,
"collect data with this RT SCHED_FIFO priority"),
OPT_INTEGER('d', "delay", &top.delay_secs,
"number of seconds to delay between refreshes"),
OPT_BOOLEAN('D', "dump-symtab", &top.dump_symtab,
"dump the symbol table used for profiling"),
OPT_INTEGER('f', "count-filter", &top.count_filter,
"only display functions with more events than this"),
OPT_BOOLEAN('g', "group", &top.group,
"put the counters into a counter group"),
OPT_BOOLEAN('i', "inherit", &top.inherit,
"child tasks inherit counters"),
OPT_STRING(0, "sym-annotate", &top.sym_filter, "symbol name",
"symbol to annotate"),
OPT_BOOLEAN('z', "zero", &top.zero,
"zero history across updates"),
OPT_INTEGER('F', "freq", &top.freq,
"profile at this frequency"),
OPT_INTEGER('E', "entries", &top.print_entries,
"display this many functions"),
OPT_BOOLEAN('U', "hide_user_symbols", &top.hide_user_symbols,
"hide user symbols"),
OPT_BOOLEAN(0, "tui", &top.use_tui, "Use the TUI interface"),
OPT_BOOLEAN(0, "stdio", &top.use_stdio, "Use the stdio interface"),
OPT_INCR('v', "verbose", &verbose,
"be more verbose (show counter open errors, etc)"),
OPT_STRING('s', "sort", &sort_order, "key[,key2...]",
"sort by key(s): pid, comm, dso, symbol, parent"),
OPT_BOOLEAN('n', "show-nr-samples", &symbol_conf.show_nr_samples,
"Show a column with the number of samples"),
OPT_CALLBACK_DEFAULT('G', "call-graph", &top, "output_type,min_percent, call_order",
"Display callchains using output_type (graph, flat, fractal, or none), min percent threshold and callchain order. "
"Default: fractal,0.5,callee", &parse_callchain_opt,
callchain_default_opt),
OPT_BOOLEAN(0, "show-total-period", &symbol_conf.show_total_period,
"Show a column with the sum of periods"),
OPT_STRING(0, "dsos", &symbol_conf.dso_list_str, "dso[,dso...]",
"only consider symbols in these dsos"),
OPT_STRING(0, "comms", &symbol_conf.comm_list_str, "comm[,comm...]",
"only consider symbols in these comms"),
OPT_STRING(0, "symbols", &symbol_conf.sym_list_str, "symbol[,symbol...]",
"only consider these symbols"),
OPT_BOOLEAN(0, "source", &symbol_conf.annotate_src,
"Interleave source code with assembly code (default)"),
OPT_BOOLEAN(0, "asm-raw", &symbol_conf.annotate_asm_raw,
"Display raw encoding of assembly instructions (default)"),
OPT_STRING('M', "disassembler-style", &disassembler_style, "disassembler style",
"Specify disassembler style (e.g. -M intel for intel syntax)"),
OPT_STRING('u', "uid", &top.uid_str, "user", "user to profile"),
OPT_END()
};
top.evlist = perf_evlist__new(NULL, NULL);
if (top.evlist == NULL)
return -ENOMEM;
symbol_conf.exclude_other = false;
argc = parse_options(argc, argv, options, top_usage, 0);
if (argc)
usage_with_options(top_usage, options);
if (sort_order == default_sort_order)
sort_order = "dso,symbol";
setup_sorting(top_usage, options);
if (top.use_stdio)
use_browser = 0;
else if (top.use_tui)
use_browser = 1;
setup_browser(false);
top.uid = parse_target_uid(top.uid_str, top.target_tid, top.target_pid);
if (top.uid_str != NULL && top.uid == UINT_MAX - 1)
goto out_delete_evlist;
/* CPU and PID are mutually exclusive */
if (top.target_tid && top.cpu_list) {
printf("WARNING: PID switch overriding CPU\n");
sleep(1);
top.cpu_list = NULL;
}
if (top.target_pid)
top.target_tid = top.target_pid;
if (perf_evlist__create_maps(top.evlist, top.target_pid,
top.target_tid, top.uid, top.cpu_list) < 0)
usage_with_options(top_usage, options);
if (!top.evlist->nr_entries &&
perf_evlist__add_default(top.evlist) < 0) {
pr_err("Not enough memory for event selector list\n");
return -ENOMEM;
}
symbol_conf.nr_events = top.evlist->nr_entries;
if (top.delay_secs < 1)
top.delay_secs = 1;
/*
* User specified count overrides default frequency.
*/
if (top.default_interval)
top.freq = 0;
else if (top.freq) {
top.default_interval = top.freq;
} else {
fprintf(stderr, "frequency and count are zero, aborting\n");
exit(EXIT_FAILURE);
}
list_for_each_entry(pos, &top.evlist->entries, node) {
/*
* Fill in the ones not specifically initialized via -c:
*/
if (!pos->attr.sample_period)
pos->attr.sample_period = top.default_interval;
}
top.sym_evsel = list_entry(top.evlist->entries.next, struct perf_evsel, node);
symbol_conf.priv_size = sizeof(struct annotation);
symbol_conf.try_vmlinux_path = (symbol_conf.vmlinux_name == NULL);
if (symbol__init() < 0)
return -1;
sort_entry__setup_elide(&sort_dso, symbol_conf.dso_list, "dso", stdout);
sort_entry__setup_elide(&sort_comm, symbol_conf.comm_list, "comm", stdout);
sort_entry__setup_elide(&sort_sym, symbol_conf.sym_list, "symbol", stdout);
/*
* Avoid annotation data structures overhead when symbols aren't on the
* sort list.
*/
top.sort_has_symbols = sort_sym.list.next != NULL;
get_term_dimensions(&top.winsize);
if (top.print_entries == 0) {
struct sigaction act = {
.sa_sigaction = perf_top__sig_winch,
.sa_flags = SA_SIGINFO,
};
perf_top__update_print_entries(&top);
sigaction(SIGWINCH, &act, NULL);
}
status = __cmd_top(&top);
out_delete_evlist:
perf_evlist__delete(top.evlist);
return status;
}
| gpl-2.0 |
Euphoria-OS-Legacy/android_kernel_oneplus_msm8974 | arch/mips/alchemy/common/dbdma.c | 4781 | 32266 | /*
*
* BRIEF MODULE DESCRIPTION
* The Descriptor Based DMA channel manager that first appeared
* on the Au1550. I started with dma.c, but I think all that is
* left is this initial comment :-)
*
* Copyright 2004 Embedded Edge, LLC
* dan@embeddededge.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/syscore_ops.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
/*
* The Descriptor Based DMA supports up to 16 channels.
*
* There are 32 devices defined. We keep an internal structure
* of devices using these channels, along with additional
* information.
*
* We allocate the descriptors and allow access to them through various
* functions. The drivers allocate the data buffers and assign them
* to the descriptors.
*/
static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
/* I couldn't find a macro that did this... */
#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
static dbdma_global_t *dbdma_gptr =
(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
static int dbdma_initialized;
static dbdev_tab_t *dbdev_tab;
static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
/* UARTS */
{ AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
{ AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
{ AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
{ AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
/* EXT DMA */
{ AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
/* USB DEV */
{ AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
{ AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
/* PSCs */
{ AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
{ AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
{ AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
/* MAC 0 */
{ AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
/* MAC 1 */
{ AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
{ AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
{ AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
{ AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
{ AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
{ AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
{ AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
{ AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
{ AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
{ AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
{ AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
{ AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
{ AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
{ AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
{ AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
{ AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
{ AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
{ AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
{ AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
{ AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
{ AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
{ AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
{ AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
{ AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
{ AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
{ AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
{ AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
{ AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
{ AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
/* 32 predefined plus 32 custom */
#define DBDEV_TAB_SIZE 64
static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
static dbdev_tab_t *find_dbdev_id(u32 id)
{
int i;
dbdev_tab_t *p;
for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
p = &dbdev_tab[i];
if (p->dev_id == id)
return p;
}
return NULL;
}
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
{
return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
}
EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
{
u32 ret = 0;
dbdev_tab_t *p;
static u16 new_id = 0x1000;
p = find_dbdev_id(~0);
if (NULL != p) {
memcpy(p, dev, sizeof(dbdev_tab_t));
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
ret = p->dev_id;
new_id++;
#if 0
printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
p->dev_id, p->dev_flags, p->dev_physaddr);
#endif
}
return ret;
}
EXPORT_SYMBOL(au1xxx_ddma_add_device);
void au1xxx_ddma_del_device(u32 devid)
{
dbdev_tab_t *p = find_dbdev_id(devid);
if (p != NULL) {
memset(p, 0, sizeof(dbdev_tab_t));
p->dev_id = ~0;
}
}
EXPORT_SYMBOL(au1xxx_ddma_del_device);
/* Allocate a channel and return a non-zero descriptor if successful. */
u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
void (*callback)(int, void *), void *callparam)
{
unsigned long flags;
u32 used, chan;
u32 dcp;
int i;
dbdev_tab_t *stp, *dtp;
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
/*
* We do the intialization on the first channel allocation.
* We have to wait because of the interrupt handler initialization
* which can't be done successfully during board set up.
*/
if (!dbdma_initialized)
return 0;
stp = find_dbdev_id(srcid);
if (stp == NULL)
return 0;
dtp = find_dbdev_id(destid);
if (dtp == NULL)
return 0;
used = 0;
/* Check to see if we can get both channels. */
spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
(stp->dev_flags & DEV_FLAGS_ANYUSE)) {
/* Got source */
stp->dev_flags |= DEV_FLAGS_INUSE;
if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
(dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
/* Got destination */
dtp->dev_flags |= DEV_FLAGS_INUSE;
} else {
/* Can't get dest. Release src. */
stp->dev_flags &= ~DEV_FLAGS_INUSE;
used++;
}
} else
used++;
spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
if (used)
return 0;
/* Let's see if we can allocate a channel for it. */
ctp = NULL;
chan = 0;
spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
for (i = 0; i < NUM_DBDMA_CHANS; i++)
if (chan_tab_ptr[i] == NULL) {
/*
* If kmalloc fails, it is caught below same
* as a channel not available.
*/
ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
chan_tab_ptr[i] = ctp;
break;
}
spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
if (ctp != NULL) {
memset(ctp, 0, sizeof(chan_tab_t));
ctp->chan_index = chan = i;
dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
dcp += (0x0100 * chan);
ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
cp = (au1x_dma_chan_t *)dcp;
ctp->chan_src = stp;
ctp->chan_dest = dtp;
ctp->chan_callback = callback;
ctp->chan_callparam = callparam;
/* Initialize channel configuration. */
i = 0;
if (stp->dev_intlevel)
i |= DDMA_CFG_SED;
if (stp->dev_intpolarity)
i |= DDMA_CFG_SP;
if (dtp->dev_intlevel)
i |= DDMA_CFG_DED;
if (dtp->dev_intpolarity)
i |= DDMA_CFG_DP;
if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
(dtp->dev_flags & DEV_FLAGS_SYNC))
i |= DDMA_CFG_SYNC;
cp->ddma_cfg = i;
au_sync();
/*
* Return a non-zero value that can be used to find the channel
* information in subsequent operations.
*/
return (u32)(&chan_tab_ptr[chan]);
}
/* Release devices */
stp->dev_flags &= ~DEV_FLAGS_INUSE;
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
return 0;
}
EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
/*
* Set the device width if source or destination is a FIFO.
* Should be 8, 16, or 32 bits.
*/
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
{
u32 rv;
chan_tab_t *ctp;
dbdev_tab_t *stp, *dtp;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
rv = 0;
if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
rv = stp->dev_devwidth;
stp->dev_devwidth = bits;
}
if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
rv = dtp->dev_devwidth;
dtp->dev_devwidth = bits;
}
return rv;
}
EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
/* Allocate a descriptor ring, initializing as much as possible. */
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
{
int i;
u32 desc_base, srcid, destid;
u32 cmd0, cmd1, src1, dest1;
u32 src0, dest0;
chan_tab_t *ctp;
dbdev_tab_t *stp, *dtp;
au1x_ddma_desc_t *dp;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
/*
* The descriptors must be 32-byte aligned. There is a
* possibility the allocation will give us such an address,
* and if we try that first we are likely to not waste larger
* slabs of memory.
*/
desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
GFP_KERNEL|GFP_DMA);
if (desc_base == 0)
return 0;
if (desc_base & 0x1f) {
/*
* Lost....do it again, allocate extra, and round
* the address base.
*/
kfree((const void *)desc_base);
i = entries * sizeof(au1x_ddma_desc_t);
i += (sizeof(au1x_ddma_desc_t) - 1);
desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
if (desc_base == 0)
return 0;
ctp->cdb_membase = desc_base;
desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
} else
ctp->cdb_membase = desc_base;
dp = (au1x_ddma_desc_t *)desc_base;
/* Keep track of the base descriptor. */
ctp->chan_desc_base = dp;
/* Initialize the rings with as much information as we know. */
srcid = stp->dev_id;
destid = dtp->dev_id;
cmd0 = cmd1 = src1 = dest1 = 0;
src0 = dest0 = 0;
cmd0 |= DSCR_CMD0_SID(srcid);
cmd0 |= DSCR_CMD0_DID(destid);
cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
/* Is it mem to mem transfer? */
if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
(DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
(DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
cmd0 |= DSCR_CMD0_MEM;
switch (stp->dev_devwidth) {
case 8:
cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
break;
case 16:
cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
break;
case 32:
default:
cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
break;
}
switch (dtp->dev_devwidth) {
case 8:
cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
break;
case 16:
cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
break;
case 32:
default:
cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
break;
}
/*
* If the device is marked as an in/out FIFO, ensure it is
* set non-coherent.
*/
if (stp->dev_flags & DEV_FLAGS_IN)
cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
if (dtp->dev_flags & DEV_FLAGS_OUT)
cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
/*
* Set up source1. For now, assume no stride and increment.
* A channel attribute update can change this later.
*/
switch (stp->dev_tsize) {
case 1:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
break;
case 2:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
break;
case 4:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
break;
case 8:
default:
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
break;
}
/* If source input is FIFO, set static address. */
if (stp->dev_flags & DEV_FLAGS_IN) {
if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
else
src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
}
if (stp->dev_physaddr)
src0 = stp->dev_physaddr;
/*
* Set up dest1. For now, assume no stride and increment.
* A channel attribute update can change this later.
*/
switch (dtp->dev_tsize) {
case 1:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
break;
case 2:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
break;
case 4:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
break;
case 8:
default:
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
break;
}
/* If destination output is FIFO, set static address. */
if (dtp->dev_flags & DEV_FLAGS_OUT) {
if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
else
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
}
if (dtp->dev_physaddr)
dest0 = dtp->dev_physaddr;
#if 0
printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
"source1:%x dest0:%x dest1:%x\n",
dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
src1, dest0, dest1);
#endif
for (i = 0; i < entries; i++) {
dp->dscr_cmd0 = cmd0;
dp->dscr_cmd1 = cmd1;
dp->dscr_source0 = src0;
dp->dscr_source1 = src1;
dp->dscr_dest0 = dest0;
dp->dscr_dest1 = dest1;
dp->dscr_stat = 0;
dp->sw_context = 0;
dp->sw_status = 0;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
dp++;
}
/* Make last descrptor point to the first. */
dp--;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
return (u32)ctp->chan_desc_base;
}
EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
/*
* Put a source buffer into the DMA ring.
* This updates the source pointer and byte count. Normally used
* for memory to fifo transfers.
*/
u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *(chan_tab_t **)chanid;
/*
* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/*
* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer address and byte count. */
dp->dscr_source0 = buf & ~0UL;
dp->dscr_cmd1 = nbytes;
/* Check flags */
if (flags & DDMA_FLAGS_IE)
dp->dscr_cmd0 |= DSCR_CMD0_IE;
if (flags & DDMA_FLAGS_NOIE)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
/*
* There is an errata on the Au1200/Au1550 parts that could result
* in "stale" data being DMA'ed. It has to do with the snoop logic on
* the cache eviction buffer. DMA_NONCOHERENT is on by default for
* these parts. If it is fixed in the future, these dma_cache_inv will
* just be nothing more than empty macros. See io.h.
*/
dma_cache_wback_inv((unsigned long)buf, nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return nbytes;
}
EXPORT_SYMBOL(au1xxx_dbdma_put_source);
/* Put a destination buffer into the DMA ring.
* This updates the destination pointer and byte count. Normally used
* to place an empty buffer into the ring for fifo to memory transfers.
*/
u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
/* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer address and byte count */
/* Check flags */
if (flags & DDMA_FLAGS_IE)
dp->dscr_cmd0 |= DSCR_CMD0_IE;
if (flags & DDMA_FLAGS_NOIE)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_dest0 = buf & ~0UL;
dp->dscr_cmd1 = nbytes;
#if 0
printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
#endif
/*
* There is an errata on the Au1200/Au1550 parts that could result in
* "stale" data being DMA'ed. It has to do with the snoop logic on the
* cache eviction buffer. DMA_NONCOHERENT is on by default for these
* parts. If it is fixed in the future, these dma_cache_inv will just
* be nothing more than empty macros. See io.h.
*/
dma_cache_inv((unsigned long)buf, nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return nbytes;
}
EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
/*
* Get a destination buffer into the DMA ring.
* Normally used to get a full buffer from the ring during fifo
* to memory transfers. This does not set the valid bit, you will
* have to put another destination buffer to keep the DMA going.
*/
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
u32 rv;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/*
* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->get_ptr;
/*
* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Return buffer address and byte count. */
*buf = (void *)(phys_to_virt(dp->dscr_dest0));
*nbytes = dp->dscr_cmd1;
rv = dp->dscr_stat;
/* Get next descriptor pointer. */
ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return rv;
}
EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
void au1xxx_dbdma_stop(u32 chanid)
{
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
int halt_timeout = 0;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
au_sync();
while (!(cp->ddma_stat & DDMA_STAT_H)) {
udelay(1);
halt_timeout++;
if (halt_timeout > 100) {
printk(KERN_WARNING "warning: DMA channel won't halt\n");
break;
}
}
/* clear current desc valid and doorbell */
cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
au_sync();
}
EXPORT_SYMBOL(au1xxx_dbdma_stop);
/*
* Start using the current descriptor pointer. If the DBDMA encounters
* a non-valid descriptor, it will stop. In this case, we can just
* continue by adding a buffer to the list and starting again.
*/
void au1xxx_dbdma_start(u32 chanid)
{
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
au_sync();
cp->ddma_dbell = 0;
au_sync();
}
EXPORT_SYMBOL(au1xxx_dbdma_start);
void au1xxx_dbdma_reset(u32 chanid)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
au1xxx_dbdma_stop(chanid);
ctp = *((chan_tab_t **)chanid);
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
/* Run through the descriptors and reset the valid indicator. */
dp = ctp->chan_desc_base;
do {
dp->dscr_cmd0 &= ~DSCR_CMD0_V;
/*
* Reset our software status -- this is used to determine
* if a descriptor is in use by upper level software. Since
* posting can reset 'V' bit.
*/
dp->sw_status = 0;
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
} while (dp != ctp->chan_desc_base);
}
EXPORT_SYMBOL(au1xxx_dbdma_reset);
u32 au1xxx_get_dma_residue(u32 chanid)
{
chan_tab_t *ctp;
au1x_dma_chan_t *cp;
u32 rv;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
/* This is only valid if the channel is stopped. */
rv = cp->ddma_bytecnt;
au_sync();
return rv;
}
EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
void au1xxx_dbdma_chan_free(u32 chanid)
{
chan_tab_t *ctp;
dbdev_tab_t *stp, *dtp;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
au1xxx_dbdma_stop(chanid);
kfree((void *)ctp->cdb_membase);
stp->dev_flags &= ~DEV_FLAGS_INUSE;
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
chan_tab_ptr[ctp->chan_index] = NULL;
kfree(ctp);
}
EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
{
u32 intstat;
u32 chan_index;
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
au1x_dma_chan_t *cp;
intstat = dbdma_gptr->ddma_intstat;
au_sync();
chan_index = __ffs(intstat);
ctp = chan_tab_ptr[chan_index];
cp = ctp->chan_ptr;
dp = ctp->cur_ptr;
/* Reset interrupt. */
cp->ddma_irq = 0;
au_sync();
if (ctp->chan_callback)
ctp->chan_callback(irq, ctp->chan_callparam);
ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
return IRQ_RETVAL(1);
}
void au1xxx_dbdma_dump(u32 chanid)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
dbdev_tab_t *stp, *dtp;
au1x_dma_chan_t *cp;
u32 i = 0;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
dtp = ctp->chan_dest;
cp = ctp->chan_ptr;
printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
(u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
dtp - dbdev_tab);
printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
(u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
(u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
cp->ddma_bytecnt);
/* Run through the descriptors */
dp = ctp->chan_desc_base;
do {
printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
dp->dscr_source0, dp->dscr_source1,
dp->dscr_dest0, dp->dscr_dest1);
printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
dp->dscr_stat, dp->dscr_nxtptr);
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
} while (dp != ctp->chan_desc_base);
}
/* Put a descriptor into the DMA ring.
* This updates the source/destination pointers and byte count.
*/
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
u32 nbytes = 0;
/*
* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/*
* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/*
* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer addresses and byte count. */
dp->dscr_dest0 = dscr->dscr_dest0;
dp->dscr_source0 = dscr->dscr_source0;
dp->dscr_dest1 = dscr->dscr_dest1;
dp->dscr_source1 = dscr->dscr_source1;
dp->dscr_cmd1 = dscr->dscr_cmd1;
nbytes = dscr->dscr_cmd1;
/* Allow the caller to specifiy if an interrupt is generated */
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer. */
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* Return something non-zero. */
return nbytes;
}
static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
static int alchemy_dbdma_suspend(void)
{
int i;
void __iomem *addr;
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
/* save channel configurations */
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
/* halt channel */
__raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
wmb();
while (!(__raw_readl(addr + 0x14) & 1))
wmb();
addr += 0x100; /* next channel base */
}
/* disable channel interrupts */
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
__raw_writel(0, addr + 0x0c);
wmb();
return 0;
}
static void alchemy_dbdma_resume(void)
{
int i;
void __iomem *addr;
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
__raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
__raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
__raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
__raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
/* restore channel configurations */
addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
__raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
__raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
__raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
__raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
__raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
__raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
wmb();
addr += 0x100; /* next channel base */
}
}
static struct syscore_ops alchemy_dbdma_syscore_ops = {
.suspend = alchemy_dbdma_suspend,
.resume = alchemy_dbdma_resume,
};
static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
{
int ret;
dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);
if (!dbdev_tab)
return -ENOMEM;
memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
dbdev_tab[ret].dev_id = ~0;
dbdma_gptr->ddma_config = 0;
dbdma_gptr->ddma_throttle = 0;
dbdma_gptr->ddma_inten = 0xffff;
au_sync();
ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
if (ret)
printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
else {
dbdma_initialized = 1;
register_syscore_ops(&alchemy_dbdma_syscore_ops);
}
return ret;
}
static int __init alchemy_dbdma_init(void)
{
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1550:
return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
case ALCHEMY_CPU_AU1200:
return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
case ALCHEMY_CPU_AU1300:
return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
}
return 0;
}
subsys_initcall(alchemy_dbdma_init);
| gpl-2.0 |
Split-Screen/android_kernel_lge_g3 | arch/arm/mach-mxs/devices/amba-duart.c | 4781 | 1050 | /*
* Copyright (C) 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <asm/irq.h>
#include <mach/mx23.h>
#include <mach/mx28.h>
#include <mach/devices-common.h>
#define MXS_AMBA_DUART_DEVICE(name, soc) \
const struct amba_device name##_device __initconst = { \
.dev = { \
.init_name = "duart", \
}, \
.res = { \
.start = soc ## _DUART_BASE_ADDR, \
.end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \
.flags = IORESOURCE_MEM, \
}, \
.irq = {soc ## _INT_DUART}, \
}
#ifdef CONFIG_SOC_IMX23
MXS_AMBA_DUART_DEVICE(mx23_duart, MX23);
#endif
#ifdef CONFIG_SOC_IMX28
MXS_AMBA_DUART_DEVICE(mx28_duart, MX28);
#endif
int __init mxs_add_duart(const struct amba_device *dev)
{
return mxs_add_amba_device(dev);
}
| gpl-2.0 |
davidmueller13/L900_3.4_Experiment | arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c | 4781 | 12155 | /***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/*
* Functions for XAUI initialization, configuration,
* and monitoring.
*
*/
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-config.h>
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-pko-defs.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsxx-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
int __cvmx_helper_xaui_enumerate(int interface)
{
union cvmx_gmxx_hg2_control gmx_hg2_control;
/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
if (gmx_hg2_control.s.hg2tx_en)
return 16;
else
return 1;
}
/**
* Probe a XAUI interface and determine the number of ports
* connected to it. The XAUI interface should still be down
* after this call.
*
* @interface: Interface to probe
*
* Returns Number of ports on the interface. Zero to disable.
*/
int __cvmx_helper_xaui_probe(int interface)
{
int i;
union cvmx_gmxx_inf_mode mode;
/*
* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
* interface needs to be enabled before IPD otherwise per port
* backpressure may not work properly.
*/
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
mode.s.en = 1;
cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
__cvmx_helper_setup_gmx(interface, 1);
/*
* Setup PKO to support 16 ports for HiGig2 virtual
* ports. We're pointing all of the PKO packet ports for this
* interface to the XAUI. This allows us to use HiGig2
* backpressure per port.
*/
for (i = 0; i < 16; i++) {
union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
pko_mem_port_ptrs.u64 = 0;
/*
* We set each PKO port to have equal priority in a
* round robin fashion.
*/
pko_mem_port_ptrs.s.static_p = 0;
pko_mem_port_ptrs.s.qos_mask = 0xff;
/* All PKO ports map to the same XAUI hardware port */
pko_mem_port_ptrs.s.eid = interface * 4;
pko_mem_port_ptrs.s.pid = interface * 16 + i;
cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
}
return __cvmx_helper_xaui_enumerate(interface);
}
/**
* Bringup and enable a XAUI interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
*
* @interface: Interface to bring up
*
* Returns Zero on success, negative on failure
*/
int __cvmx_helper_xaui_enable(int interface)
{
union cvmx_gmxx_prtx_cfg gmx_cfg;
union cvmx_pcsxx_control1_reg xauiCtl;
union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
union cvmx_gmxx_tx_int_en gmx_tx_int_en;
union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
/* (1) Interface has already been enabled. */
/* (2) Disable GMX. */
xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
xauiMiscCtl.s.gmxeno = 1;
cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
/* (3) Disable GMX and PCSX interrupts. */
gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
/* (4) Bring up the PCSX and GMX reconciliation layer. */
/* (4)a Set polarity and lane swapping. */
/* (4)b */
gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
/* Enable better IFG packing and improves performance */
gmxXauiTxCtl.s.dic_en = 1;
gmxXauiTxCtl.s.uni_en = 0;
cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
/* (4)c Aply reset sequence */
xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
xauiCtl.s.lo_pwr = 0;
xauiCtl.s.reset = 1;
cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
/* Wait for PCS to come out of reset */
if (CVMX_WAIT_FOR_FIELD64
(CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
reset, ==, 0, 10000))
return -1;
/* Wait for PCS to be aligned */
if (CVMX_WAIT_FOR_FIELD64
(CVMX_PCSXX_10GBX_STATUS_REG(interface),
union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
return -1;
/* Wait for RX to be ready */
if (CVMX_WAIT_FOR_FIELD64
(CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
status, ==, 0, 10000))
return -1;
/* (6) Configure GMX */
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
gmx_cfg.s.en = 0;
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
/* Wait for GMX RX to be idle */
if (CVMX_WAIT_FOR_FIELD64
(CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
rx_idle, ==, 1, 10000))
return -1;
/* Wait for GMX TX to be idle */
if (CVMX_WAIT_FOR_FIELD64
(CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
tx_idle, ==, 1, 10000))
return -1;
/* GMX configure */
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
gmx_cfg.s.speed = 1;
gmx_cfg.s.speed_msb = 0;
gmx_cfg.s.slottime = 1;
cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
/* (7) Clear out any error state */
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
/* Wait for receive link */
if (CVMX_WAIT_FOR_FIELD64
(CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
rcv_lnk, ==, 1, 10000))
return -1;
if (CVMX_WAIT_FOR_FIELD64
(CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
xmtflt, ==, 0, 10000))
return -1;
if (CVMX_WAIT_FOR_FIELD64
(CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
rcvflt, ==, 0, 10000))
return -1;
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
/* (8) Enable packet reception */
xauiMiscCtl.s.gmxeno = 0;
cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
gmx_cfg.s.en = 1;
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
__cvmx_interrupt_gmxx_enable(interface);
return 0;
}
/**
* Return the link state of an IPD/PKO port as returned by
* auto negotiation. The result of this function may not match
* Octeon's link config if auto negotiation has changed since
* the last call to cvmx_helper_link_set().
*
* @ipd_port: IPD/PKO port to query
*
* Returns Link state
*/
cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
{
int interface = cvmx_helper_get_interface_num(ipd_port);
union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
cvmx_helper_link_info_t result;
gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
pcsxx_status1_reg.u64 =
cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
result.u64 = 0;
/* Only return a link if both RX and TX are happy */
if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
(pcsxx_status1_reg.s.rcv_lnk == 1)) {
result.s.link_up = 1;
result.s.full_duplex = 1;
result.s.speed = 10000;
} else {
/* Disable GMX and PCSX interrupts. */
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
}
return result;
}
/**
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get(). It is normally best to use
* cvmx_helper_link_autoconf() instead.
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state
*
* Returns Zero on success, negative on failure
*/
int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
{
int interface = cvmx_helper_get_interface_num(ipd_port);
union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
/* If the link shouldn't be up, then just return */
if (!link_info.s.link_up)
return 0;
/* Do nothing if both RX and TX are happy */
if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
return 0;
/* Bring the link up */
return __cvmx_helper_xaui_enable(interface);
}
/**
* Configure a port for internal and/or external loopback. Internal loopback
* causes packets sent by the port to be received by Octeon. External loopback
* causes packets received from the wire to sent out again.
*
* @ipd_port: IPD/PKO port to loopback.
* @enable_internal:
* Non zero if you want internal loopback
* @enable_external:
* Non zero if you want external loopback
*
* Returns Zero on success, negative on failure.
*/
extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
int enable_internal,
int enable_external)
{
int interface = cvmx_helper_get_interface_num(ipd_port);
union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
/* Set the internal loop */
pcsxx_control1_reg.u64 =
cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
pcsxx_control1_reg.s.loopbck1 = enable_internal;
cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
pcsxx_control1_reg.u64);
/* Set the external loop */
gmxx_xaui_ext_loopback.u64 =
cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
gmxx_xaui_ext_loopback.s.en = enable_external;
cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
gmxx_xaui_ext_loopback.u64);
/* Take the link through a reset */
return __cvmx_helper_xaui_enable(interface);
}
| gpl-2.0 |
hudayou/goldfish | arch/mips/kernel/cevt-ds1287.c | 4781 | 2853 | /*
* DS1287 clockevent driver
*
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/irq.h>
#include <asm/time.h>
int ds1287_timer_state(void)
{
return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
}
int ds1287_set_base_clock(unsigned int hz)
{
u8 rate;
switch (hz) {
case 128:
rate = 0x9;
break;
case 256:
rate = 0x8;
break;
case 1024:
rate = 0x6;
break;
default:
return -EINVAL;
}
CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
return 0;
}
static int ds1287_set_next_event(unsigned long delta,
struct clock_event_device *evt)
{
return -EINVAL;
}
static void ds1287_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u8 val;
spin_lock(&rtc_lock);
val = CMOS_READ(RTC_REG_B);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
val |= RTC_PIE;
break;
default:
val &= ~RTC_PIE;
break;
}
CMOS_WRITE(val, RTC_REG_B);
spin_unlock(&rtc_lock);
}
static void ds1287_event_handler(struct clock_event_device *dev)
{
}
static struct clock_event_device ds1287_clockevent = {
.name = "ds1287",
.features = CLOCK_EVT_FEAT_PERIODIC,
.set_next_event = ds1287_set_next_event,
.set_mode = ds1287_set_mode,
.event_handler = ds1287_event_handler,
};
static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
{
struct clock_event_device *cd = &ds1287_clockevent;
/* Ack the RTC interrupt. */
CMOS_READ(RTC_REG_C);
cd->event_handler(cd);
return IRQ_HANDLED;
}
static struct irqaction ds1287_irqaction = {
.handler = ds1287_interrupt,
.flags = IRQF_PERCPU | IRQF_TIMER,
.name = "ds1287",
};
int __init ds1287_clockevent_init(int irq)
{
struct clock_event_device *cd;
cd = &ds1287_clockevent;
cd->rating = 100;
cd->irq = irq;
clockevent_set_clock(cd, 32768);
cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
cd->cpumask = cpumask_of(0);
clockevents_register_device(&ds1287_clockevent);
return setup_irq(irq, &ds1287_irqaction);
}
| gpl-2.0 |
Red--Code/mt6589_kernel_3.4.67 | fs/ext3/file.c | 7341 | 2155 | /*
* linux/fs/ext3/file.c
*
* Copyright (C) 1992, 1993, 1994, 1995
* Remy Card (card@masi.ibp.fr)
* Laboratoire MASI - Institut Blaise Pascal
* Universite Pierre et Marie Curie (Paris VI)
*
* from
*
* linux/fs/minix/file.c
*
* Copyright (C) 1991, 1992 Linus Torvalds
*
* ext3 fs regular file handling primitives
*
* 64-bit file support on 64-bit platforms by Jakub Jelinek
* (jj@sunsite.ms.mff.cuni.cz)
*/
#include <linux/quotaops.h>
#include "ext3.h"
#include "xattr.h"
#include "acl.h"
/*
* Called when an inode is released. Note that this is different
* from ext3_file_open: open gets called at every open, but release
* gets called only when /all/ the files are closed.
*/
static int ext3_release_file (struct inode * inode, struct file * filp)
{
if (ext3_test_inode_state(inode, EXT3_STATE_FLUSH_ON_CLOSE)) {
filemap_flush(inode->i_mapping);
ext3_clear_inode_state(inode, EXT3_STATE_FLUSH_ON_CLOSE);
}
/* if we are the last writer on the inode, drop the block reservation */
if ((filp->f_mode & FMODE_WRITE) &&
(atomic_read(&inode->i_writecount) == 1))
{
mutex_lock(&EXT3_I(inode)->truncate_mutex);
ext3_discard_reservation(inode);
mutex_unlock(&EXT3_I(inode)->truncate_mutex);
}
if (is_dx(inode) && filp->private_data)
ext3_htree_free_dir_info(filp->private_data);
return 0;
}
const struct file_operations ext3_file_operations = {
.llseek = generic_file_llseek,
.read = do_sync_read,
.write = do_sync_write,
.aio_read = generic_file_aio_read,
.aio_write = generic_file_aio_write,
.unlocked_ioctl = ext3_ioctl,
#ifdef CONFIG_COMPAT
.compat_ioctl = ext3_compat_ioctl,
#endif
.mmap = generic_file_mmap,
.open = dquot_file_open,
.release = ext3_release_file,
.fsync = ext3_sync_file,
.splice_read = generic_file_splice_read,
.splice_write = generic_file_splice_write,
};
const struct inode_operations ext3_file_inode_operations = {
.setattr = ext3_setattr,
#ifdef CONFIG_EXT3_FS_XATTR
.setxattr = generic_setxattr,
.getxattr = generic_getxattr,
.listxattr = ext3_listxattr,
.removexattr = generic_removexattr,
#endif
.get_acl = ext3_get_acl,
.fiemap = ext3_fiemap,
};
| gpl-2.0 |
superr/android_kernel_502_falcon | drivers/infiniband/hw/qib/qib_keys.c | 7853 | 9139 | /*
* Copyright (c) 2006, 2007, 2009 QLogic Corporation. All rights reserved.
* Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "qib.h"
/**
* qib_alloc_lkey - allocate an lkey
* @rkt: lkey table in which to allocate the lkey
* @mr: memory region that this lkey protects
*
* Returns 1 if successful, otherwise returns 0.
*/
int qib_alloc_lkey(struct qib_lkey_table *rkt, struct qib_mregion *mr)
{
unsigned long flags;
u32 r;
u32 n;
int ret;
spin_lock_irqsave(&rkt->lock, flags);
/* Find the next available LKEY */
r = rkt->next;
n = r;
for (;;) {
if (rkt->table[r] == NULL)
break;
r = (r + 1) & (rkt->max - 1);
if (r == n) {
spin_unlock_irqrestore(&rkt->lock, flags);
ret = 0;
goto bail;
}
}
rkt->next = (r + 1) & (rkt->max - 1);
/*
* Make sure lkey is never zero which is reserved to indicate an
* unrestricted LKEY.
*/
rkt->gen++;
mr->lkey = (r << (32 - ib_qib_lkey_table_size)) |
((((1 << (24 - ib_qib_lkey_table_size)) - 1) & rkt->gen)
<< 8);
if (mr->lkey == 0) {
mr->lkey |= 1 << 8;
rkt->gen++;
}
rkt->table[r] = mr;
spin_unlock_irqrestore(&rkt->lock, flags);
ret = 1;
bail:
return ret;
}
/**
* qib_free_lkey - free an lkey
* @rkt: table from which to free the lkey
* @lkey: lkey id to free
*/
int qib_free_lkey(struct qib_ibdev *dev, struct qib_mregion *mr)
{
unsigned long flags;
u32 lkey = mr->lkey;
u32 r;
int ret;
spin_lock_irqsave(&dev->lk_table.lock, flags);
if (lkey == 0) {
if (dev->dma_mr && dev->dma_mr == mr) {
ret = atomic_read(&dev->dma_mr->refcount);
if (!ret)
dev->dma_mr = NULL;
} else
ret = 0;
} else {
r = lkey >> (32 - ib_qib_lkey_table_size);
ret = atomic_read(&dev->lk_table.table[r]->refcount);
if (!ret)
dev->lk_table.table[r] = NULL;
}
spin_unlock_irqrestore(&dev->lk_table.lock, flags);
if (ret)
ret = -EBUSY;
return ret;
}
/**
* qib_lkey_ok - check IB SGE for validity and initialize
* @rkt: table containing lkey to check SGE against
* @isge: outgoing internal SGE
* @sge: SGE to check
* @acc: access flags
*
* Return 1 if valid and successful, otherwise returns 0.
*
* Check the IB SGE for validity and initialize our internal version
* of it.
*/
int qib_lkey_ok(struct qib_lkey_table *rkt, struct qib_pd *pd,
struct qib_sge *isge, struct ib_sge *sge, int acc)
{
struct qib_mregion *mr;
unsigned n, m;
size_t off;
unsigned long flags;
/*
* We use LKEY == zero for kernel virtual addresses
* (see qib_get_dma_mr and qib_dma.c).
*/
spin_lock_irqsave(&rkt->lock, flags);
if (sge->lkey == 0) {
struct qib_ibdev *dev = to_idev(pd->ibpd.device);
if (pd->user)
goto bail;
if (!dev->dma_mr)
goto bail;
atomic_inc(&dev->dma_mr->refcount);
spin_unlock_irqrestore(&rkt->lock, flags);
isge->mr = dev->dma_mr;
isge->vaddr = (void *) sge->addr;
isge->length = sge->length;
isge->sge_length = sge->length;
isge->m = 0;
isge->n = 0;
goto ok;
}
mr = rkt->table[(sge->lkey >> (32 - ib_qib_lkey_table_size))];
if (unlikely(mr == NULL || mr->lkey != sge->lkey ||
mr->pd != &pd->ibpd))
goto bail;
off = sge->addr - mr->user_base;
if (unlikely(sge->addr < mr->user_base ||
off + sge->length > mr->length ||
(mr->access_flags & acc) != acc))
goto bail;
atomic_inc(&mr->refcount);
spin_unlock_irqrestore(&rkt->lock, flags);
off += mr->offset;
if (mr->page_shift) {
/*
page sizes are uniform power of 2 so no loop is necessary
entries_spanned_by_off is the number of times the loop below
would have executed.
*/
size_t entries_spanned_by_off;
entries_spanned_by_off = off >> mr->page_shift;
off -= (entries_spanned_by_off << mr->page_shift);
m = entries_spanned_by_off/QIB_SEGSZ;
n = entries_spanned_by_off%QIB_SEGSZ;
} else {
m = 0;
n = 0;
while (off >= mr->map[m]->segs[n].length) {
off -= mr->map[m]->segs[n].length;
n++;
if (n >= QIB_SEGSZ) {
m++;
n = 0;
}
}
}
isge->mr = mr;
isge->vaddr = mr->map[m]->segs[n].vaddr + off;
isge->length = mr->map[m]->segs[n].length - off;
isge->sge_length = sge->length;
isge->m = m;
isge->n = n;
ok:
return 1;
bail:
spin_unlock_irqrestore(&rkt->lock, flags);
return 0;
}
/**
* qib_rkey_ok - check the IB virtual address, length, and RKEY
* @dev: infiniband device
* @ss: SGE state
* @len: length of data
* @vaddr: virtual address to place data
* @rkey: rkey to check
* @acc: access flags
*
* Return 1 if successful, otherwise 0.
*/
int qib_rkey_ok(struct qib_qp *qp, struct qib_sge *sge,
u32 len, u64 vaddr, u32 rkey, int acc)
{
struct qib_lkey_table *rkt = &to_idev(qp->ibqp.device)->lk_table;
struct qib_mregion *mr;
unsigned n, m;
size_t off;
unsigned long flags;
/*
* We use RKEY == zero for kernel virtual addresses
* (see qib_get_dma_mr and qib_dma.c).
*/
spin_lock_irqsave(&rkt->lock, flags);
if (rkey == 0) {
struct qib_pd *pd = to_ipd(qp->ibqp.pd);
struct qib_ibdev *dev = to_idev(pd->ibpd.device);
if (pd->user)
goto bail;
if (!dev->dma_mr)
goto bail;
atomic_inc(&dev->dma_mr->refcount);
spin_unlock_irqrestore(&rkt->lock, flags);
sge->mr = dev->dma_mr;
sge->vaddr = (void *) vaddr;
sge->length = len;
sge->sge_length = len;
sge->m = 0;
sge->n = 0;
goto ok;
}
mr = rkt->table[(rkey >> (32 - ib_qib_lkey_table_size))];
if (unlikely(mr == NULL || mr->lkey != rkey || qp->ibqp.pd != mr->pd))
goto bail;
off = vaddr - mr->iova;
if (unlikely(vaddr < mr->iova || off + len > mr->length ||
(mr->access_flags & acc) == 0))
goto bail;
atomic_inc(&mr->refcount);
spin_unlock_irqrestore(&rkt->lock, flags);
off += mr->offset;
if (mr->page_shift) {
/*
page sizes are uniform power of 2 so no loop is necessary
entries_spanned_by_off is the number of times the loop below
would have executed.
*/
size_t entries_spanned_by_off;
entries_spanned_by_off = off >> mr->page_shift;
off -= (entries_spanned_by_off << mr->page_shift);
m = entries_spanned_by_off/QIB_SEGSZ;
n = entries_spanned_by_off%QIB_SEGSZ;
} else {
m = 0;
n = 0;
while (off >= mr->map[m]->segs[n].length) {
off -= mr->map[m]->segs[n].length;
n++;
if (n >= QIB_SEGSZ) {
m++;
n = 0;
}
}
}
sge->mr = mr;
sge->vaddr = mr->map[m]->segs[n].vaddr + off;
sge->length = mr->map[m]->segs[n].length - off;
sge->sge_length = len;
sge->m = m;
sge->n = n;
ok:
return 1;
bail:
spin_unlock_irqrestore(&rkt->lock, flags);
return 0;
}
/*
* Initialize the memory region specified by the work reqeust.
*/
int qib_fast_reg_mr(struct qib_qp *qp, struct ib_send_wr *wr)
{
struct qib_lkey_table *rkt = &to_idev(qp->ibqp.device)->lk_table;
struct qib_pd *pd = to_ipd(qp->ibqp.pd);
struct qib_mregion *mr;
u32 rkey = wr->wr.fast_reg.rkey;
unsigned i, n, m;
int ret = -EINVAL;
unsigned long flags;
u64 *page_list;
size_t ps;
spin_lock_irqsave(&rkt->lock, flags);
if (pd->user || rkey == 0)
goto bail;
mr = rkt->table[(rkey >> (32 - ib_qib_lkey_table_size))];
if (unlikely(mr == NULL || qp->ibqp.pd != mr->pd))
goto bail;
if (wr->wr.fast_reg.page_list_len > mr->max_segs)
goto bail;
ps = 1UL << wr->wr.fast_reg.page_shift;
if (wr->wr.fast_reg.length > ps * wr->wr.fast_reg.page_list_len)
goto bail;
mr->user_base = wr->wr.fast_reg.iova_start;
mr->iova = wr->wr.fast_reg.iova_start;
mr->lkey = rkey;
mr->length = wr->wr.fast_reg.length;
mr->access_flags = wr->wr.fast_reg.access_flags;
page_list = wr->wr.fast_reg.page_list->page_list;
m = 0;
n = 0;
for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
mr->map[m]->segs[n].vaddr = (void *) page_list[i];
mr->map[m]->segs[n].length = ps;
if (++n == QIB_SEGSZ) {
m++;
n = 0;
}
}
ret = 0;
bail:
spin_unlock_irqrestore(&rkt->lock, flags);
return ret;
}
| gpl-2.0 |
skeevy420/android_kernel_lge_d850 | drivers/message/i2o/driver.c | 10413 | 9593 | /*
* Functions to handle I2O drivers (OSMs) and I2O bus type for sysfs
*
* Copyright (C) 2004 Markus Lidel <Markus.Lidel@shadowconnect.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Fixes/additions:
* Markus Lidel <Markus.Lidel@shadowconnect.com>
* initial version.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/rwsem.h>
#include <linux/i2o.h>
#include <linux/workqueue.h>
#include <linux/string.h>
#include <linux/slab.h>
#include "core.h"
#define OSM_NAME "i2o"
/* max_drivers - Maximum I2O drivers (OSMs) which could be registered */
static unsigned int i2o_max_drivers = I2O_MAX_DRIVERS;
module_param_named(max_drivers, i2o_max_drivers, uint, 0);
MODULE_PARM_DESC(max_drivers, "maximum number of OSM's to support");
/* I2O drivers lock and array */
static spinlock_t i2o_drivers_lock;
static struct i2o_driver **i2o_drivers;
/**
* i2o_bus_match - Tell if I2O device class id matches the class ids of the I2O driver (OSM)
* @dev: device which should be verified
* @drv: the driver to match against
*
* Used by the bus to check if the driver wants to handle the device.
*
* Returns 1 if the class ids of the driver match the class id of the
* device, otherwise 0.
*/
static int i2o_bus_match(struct device *dev, struct device_driver *drv)
{
struct i2o_device *i2o_dev = to_i2o_device(dev);
struct i2o_driver *i2o_drv = to_i2o_driver(drv);
struct i2o_class_id *ids = i2o_drv->classes;
if (ids)
while (ids->class_id != I2O_CLASS_END) {
if (ids->class_id == i2o_dev->lct_data.class_id)
return 1;
ids++;
}
return 0;
};
/* I2O bus type */
struct bus_type i2o_bus_type = {
.name = "i2o",
.match = i2o_bus_match,
.dev_attrs = i2o_device_attrs
};
/**
* i2o_driver_register - Register a I2O driver (OSM) in the I2O core
* @drv: I2O driver which should be registered
*
* Registers the OSM drv in the I2O core and creates an event queues if
* necessary.
*
* Returns 0 on success or negative error code on failure.
*/
int i2o_driver_register(struct i2o_driver *drv)
{
struct i2o_controller *c;
int i;
int rc = 0;
unsigned long flags;
osm_debug("Register driver %s\n", drv->name);
if (drv->event) {
drv->event_queue = alloc_workqueue(drv->name,
WQ_MEM_RECLAIM, 1);
if (!drv->event_queue) {
osm_err("Could not initialize event queue for driver "
"%s\n", drv->name);
return -EFAULT;
}
osm_debug("Event queue initialized for driver %s\n", drv->name);
} else
drv->event_queue = NULL;
drv->driver.name = drv->name;
drv->driver.bus = &i2o_bus_type;
spin_lock_irqsave(&i2o_drivers_lock, flags);
for (i = 0; i2o_drivers[i]; i++)
if (i >= i2o_max_drivers) {
osm_err("too many drivers registered, increase "
"max_drivers\n");
spin_unlock_irqrestore(&i2o_drivers_lock, flags);
return -EFAULT;
}
drv->context = i;
i2o_drivers[i] = drv;
spin_unlock_irqrestore(&i2o_drivers_lock, flags);
osm_debug("driver %s gets context id %d\n", drv->name, drv->context);
list_for_each_entry(c, &i2o_controllers, list) {
struct i2o_device *i2o_dev;
i2o_driver_notify_controller_add(drv, c);
list_for_each_entry(i2o_dev, &c->devices, list)
i2o_driver_notify_device_add(drv, i2o_dev);
}
rc = driver_register(&drv->driver);
if (rc) {
if (drv->event) {
destroy_workqueue(drv->event_queue);
drv->event_queue = NULL;
}
}
return rc;
};
/**
* i2o_driver_unregister - Unregister a I2O driver (OSM) from the I2O core
* @drv: I2O driver which should be unregistered
*
* Unregisters the OSM drv from the I2O core and cleanup event queues if
* necessary.
*/
void i2o_driver_unregister(struct i2o_driver *drv)
{
struct i2o_controller *c;
unsigned long flags;
osm_debug("unregister driver %s\n", drv->name);
driver_unregister(&drv->driver);
list_for_each_entry(c, &i2o_controllers, list) {
struct i2o_device *i2o_dev;
list_for_each_entry(i2o_dev, &c->devices, list)
i2o_driver_notify_device_remove(drv, i2o_dev);
i2o_driver_notify_controller_remove(drv, c);
}
spin_lock_irqsave(&i2o_drivers_lock, flags);
i2o_drivers[drv->context] = NULL;
spin_unlock_irqrestore(&i2o_drivers_lock, flags);
if (drv->event_queue) {
destroy_workqueue(drv->event_queue);
drv->event_queue = NULL;
osm_debug("event queue removed for %s\n", drv->name);
}
};
/**
* i2o_driver_dispatch - dispatch an I2O reply message
* @c: I2O controller of the message
* @m: I2O message number
*
* The reply is delivered to the driver from which the original message
* was. This function is only called from interrupt context.
*
* Returns 0 on success and the message should not be flushed. Returns > 0
* on success and if the message should be flushed afterwords. Returns
* negative error code on failure (the message will be flushed too).
*/
int i2o_driver_dispatch(struct i2o_controller *c, u32 m)
{
struct i2o_driver *drv;
struct i2o_message *msg = i2o_msg_out_to_virt(c, m);
u32 context = le32_to_cpu(msg->u.s.icntxt);
unsigned long flags;
if (unlikely(context >= i2o_max_drivers)) {
osm_warn("%s: Spurious reply to unknown driver %d\n", c->name,
context);
return -EIO;
}
spin_lock_irqsave(&i2o_drivers_lock, flags);
drv = i2o_drivers[context];
spin_unlock_irqrestore(&i2o_drivers_lock, flags);
if (unlikely(!drv)) {
osm_warn("%s: Spurious reply to unknown driver %d\n", c->name,
context);
return -EIO;
}
if ((le32_to_cpu(msg->u.head[1]) >> 24) == I2O_CMD_UTIL_EVT_REGISTER) {
struct i2o_device *dev, *tmp;
struct i2o_event *evt;
u16 size;
u16 tid = le32_to_cpu(msg->u.head[1]) & 0xfff;
osm_debug("event received from device %d\n", tid);
if (!drv->event)
return -EIO;
/* cut of header from message size (in 32-bit words) */
size = (le32_to_cpu(msg->u.head[0]) >> 16) - 5;
evt = kzalloc(size * 4 + sizeof(*evt), GFP_ATOMIC);
if (!evt)
return -ENOMEM;
evt->size = size;
evt->tcntxt = le32_to_cpu(msg->u.s.tcntxt);
evt->event_indicator = le32_to_cpu(msg->body[0]);
memcpy(&evt->data, &msg->body[1], size * 4);
list_for_each_entry_safe(dev, tmp, &c->devices, list)
if (dev->lct_data.tid == tid) {
evt->i2o_dev = dev;
break;
}
INIT_WORK(&evt->work, drv->event);
queue_work(drv->event_queue, &evt->work);
return 1;
}
if (unlikely(!drv->reply)) {
osm_debug("%s: Reply to driver %s, but no reply function"
" defined!\n", c->name, drv->name);
return -EIO;
}
return drv->reply(c, m, msg);
}
/**
* i2o_driver_notify_controller_add_all - Send notify of added controller
* @c: newly added controller
*
* Send notifications to all registered drivers that a new controller was
* added.
*/
void i2o_driver_notify_controller_add_all(struct i2o_controller *c)
{
int i;
struct i2o_driver *drv;
for (i = 0; i < i2o_max_drivers; i++) {
drv = i2o_drivers[i];
if (drv)
i2o_driver_notify_controller_add(drv, c);
}
}
/**
* i2o_driver_notify_controller_remove_all - Send notify of removed controller
* @c: controller that is being removed
*
* Send notifications to all registered drivers that a controller was
* removed.
*/
void i2o_driver_notify_controller_remove_all(struct i2o_controller *c)
{
int i;
struct i2o_driver *drv;
for (i = 0; i < i2o_max_drivers; i++) {
drv = i2o_drivers[i];
if (drv)
i2o_driver_notify_controller_remove(drv, c);
}
}
/**
* i2o_driver_notify_device_add_all - Send notify of added device
* @i2o_dev: newly added I2O device
*
* Send notifications to all registered drivers that a device was added.
*/
void i2o_driver_notify_device_add_all(struct i2o_device *i2o_dev)
{
int i;
struct i2o_driver *drv;
for (i = 0; i < i2o_max_drivers; i++) {
drv = i2o_drivers[i];
if (drv)
i2o_driver_notify_device_add(drv, i2o_dev);
}
}
/**
* i2o_driver_notify_device_remove_all - Send notify of removed device
* @i2o_dev: device that is being removed
*
* Send notifications to all registered drivers that a device was removed.
*/
void i2o_driver_notify_device_remove_all(struct i2o_device *i2o_dev)
{
int i;
struct i2o_driver *drv;
for (i = 0; i < i2o_max_drivers; i++) {
drv = i2o_drivers[i];
if (drv)
i2o_driver_notify_device_remove(drv, i2o_dev);
}
}
/**
* i2o_driver_init - initialize I2O drivers (OSMs)
*
* Registers the I2O bus and allocate memory for the array of OSMs.
*
* Returns 0 on success or negative error code on failure.
*/
int __init i2o_driver_init(void)
{
int rc = 0;
spin_lock_init(&i2o_drivers_lock);
if ((i2o_max_drivers < 2) || (i2o_max_drivers > 64)) {
osm_warn("max_drivers set to %d, but must be >=2 and <= 64\n",
i2o_max_drivers);
i2o_max_drivers = I2O_MAX_DRIVERS;
}
osm_info("max drivers = %d\n", i2o_max_drivers);
i2o_drivers =
kcalloc(i2o_max_drivers, sizeof(*i2o_drivers), GFP_KERNEL);
if (!i2o_drivers)
return -ENOMEM;
rc = bus_register(&i2o_bus_type);
if (rc < 0)
kfree(i2o_drivers);
return rc;
};
/**
* i2o_driver_exit - clean up I2O drivers (OSMs)
*
* Unregisters the I2O bus and frees driver array.
*/
void i2o_driver_exit(void)
{
bus_unregister(&i2o_bus_type);
kfree(i2o_drivers);
};
EXPORT_SYMBOL(i2o_driver_register);
EXPORT_SYMBOL(i2o_driver_unregister);
EXPORT_SYMBOL(i2o_driver_notify_controller_add_all);
EXPORT_SYMBOL(i2o_driver_notify_controller_remove_all);
EXPORT_SYMBOL(i2o_driver_notify_device_add_all);
EXPORT_SYMBOL(i2o_driver_notify_device_remove_all);
| gpl-2.0 |
thoemy/enru-3.1.10-g517147e | drivers/net/pptp.c | 430 | 16937 | /*
* Point-to-Point Tunneling Protocol for Linux
*
* Authors: Dmitry Kozlov <xeb@mail.ru>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#include <linux/string.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/net.h>
#include <linux/skbuff.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/ppp_channel.h>
#include <linux/ppp_defs.h>
#include <linux/if_pppox.h>
#include <linux/if_ppp.h>
#include <linux/notifier.h>
#include <linux/file.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/netfilter.h>
#include <linux/netfilter_ipv4.h>
#include <linux/rcupdate.h>
#include <linux/spinlock.h>
#include <net/sock.h>
#include <net/protocol.h>
#include <net/ip.h>
#include <net/icmp.h>
#include <net/route.h>
#include <net/gre.h>
#include <linux/uaccess.h>
#define PPTP_DRIVER_VERSION "0.8.5"
#define MAX_CALLID 65535
static DECLARE_BITMAP(callid_bitmap, MAX_CALLID + 1);
static struct pppox_sock **callid_sock;
static DEFINE_SPINLOCK(chan_lock);
static struct proto pptp_sk_proto __read_mostly;
static const struct ppp_channel_ops pptp_chan_ops;
static const struct proto_ops pptp_ops;
#define PPP_LCP_ECHOREQ 0x09
#define PPP_LCP_ECHOREP 0x0A
#define SC_RCV_BITS (SC_RCV_B7_1|SC_RCV_B7_0|SC_RCV_ODDP|SC_RCV_EVNP)
#define MISSING_WINDOW 20
#define WRAPPED(curseq, lastseq)\
((((curseq) & 0xffffff00) == 0) &&\
(((lastseq) & 0xffffff00) == 0xffffff00))
#define PPTP_GRE_PROTO 0x880B
#define PPTP_GRE_VER 0x1
#define PPTP_GRE_FLAG_C 0x80
#define PPTP_GRE_FLAG_R 0x40
#define PPTP_GRE_FLAG_K 0x20
#define PPTP_GRE_FLAG_S 0x10
#define PPTP_GRE_FLAG_A 0x80
#define PPTP_GRE_IS_C(f) ((f)&PPTP_GRE_FLAG_C)
#define PPTP_GRE_IS_R(f) ((f)&PPTP_GRE_FLAG_R)
#define PPTP_GRE_IS_K(f) ((f)&PPTP_GRE_FLAG_K)
#define PPTP_GRE_IS_S(f) ((f)&PPTP_GRE_FLAG_S)
#define PPTP_GRE_IS_A(f) ((f)&PPTP_GRE_FLAG_A)
#define PPTP_HEADER_OVERHEAD (2+sizeof(struct pptp_gre_header))
struct pptp_gre_header {
u8 flags;
u8 ver;
u16 protocol;
u16 payload_len;
u16 call_id;
u32 seq;
u32 ack;
} __packed;
static struct pppox_sock *lookup_chan(u16 call_id, __be32 s_addr)
{
struct pppox_sock *sock;
struct pptp_opt *opt;
rcu_read_lock();
sock = rcu_dereference(callid_sock[call_id]);
if (sock) {
opt = &sock->proto.pptp;
if (opt->dst_addr.sin_addr.s_addr != s_addr)
sock = NULL;
else
sock_hold(sk_pppox(sock));
}
rcu_read_unlock();
return sock;
}
static int lookup_chan_dst(u16 call_id, __be32 d_addr)
{
struct pppox_sock *sock;
struct pptp_opt *opt;
int i;
rcu_read_lock();
for (i = find_next_bit(callid_bitmap, MAX_CALLID, 1); i < MAX_CALLID;
i = find_next_bit(callid_bitmap, MAX_CALLID, i + 1)) {
sock = rcu_dereference(callid_sock[i]);
if (!sock)
continue;
opt = &sock->proto.pptp;
if (opt->dst_addr.call_id == call_id &&
opt->dst_addr.sin_addr.s_addr == d_addr)
break;
}
rcu_read_unlock();
return i < MAX_CALLID;
}
static int add_chan(struct pppox_sock *sock)
{
static int call_id;
spin_lock(&chan_lock);
if (!sock->proto.pptp.src_addr.call_id) {
call_id = find_next_zero_bit(callid_bitmap, MAX_CALLID, call_id + 1);
if (call_id == MAX_CALLID) {
call_id = find_next_zero_bit(callid_bitmap, MAX_CALLID, 1);
if (call_id == MAX_CALLID)
goto out_err;
}
sock->proto.pptp.src_addr.call_id = call_id;
} else if (test_bit(sock->proto.pptp.src_addr.call_id, callid_bitmap))
goto out_err;
set_bit(sock->proto.pptp.src_addr.call_id, callid_bitmap);
rcu_assign_pointer(callid_sock[sock->proto.pptp.src_addr.call_id], sock);
spin_unlock(&chan_lock);
return 0;
out_err:
spin_unlock(&chan_lock);
return -1;
}
static void del_chan(struct pppox_sock *sock)
{
spin_lock(&chan_lock);
clear_bit(sock->proto.pptp.src_addr.call_id, callid_bitmap);
rcu_assign_pointer(callid_sock[sock->proto.pptp.src_addr.call_id], NULL);
spin_unlock(&chan_lock);
synchronize_rcu();
}
static int pptp_xmit(struct ppp_channel *chan, struct sk_buff *skb)
{
struct sock *sk = (struct sock *) chan->private;
struct pppox_sock *po = pppox_sk(sk);
struct pptp_opt *opt = &po->proto.pptp;
struct pptp_gre_header *hdr;
unsigned int header_len = sizeof(*hdr);
struct flowi4 fl4;
int islcp;
int len;
unsigned char *data;
__u32 seq_recv;
struct rtable *rt;
struct net_device *tdev;
struct iphdr *iph;
int max_headroom;
if (sk_pppox(po)->sk_state & PPPOX_DEAD)
goto tx_error;
rt = ip_route_output_ports(&init_net, &fl4, NULL,
opt->dst_addr.sin_addr.s_addr,
opt->src_addr.sin_addr.s_addr,
0, 0, IPPROTO_GRE,
RT_TOS(0), 0);
if (IS_ERR(rt))
goto tx_error;
tdev = rt->dst.dev;
max_headroom = LL_RESERVED_SPACE(tdev) + sizeof(*iph) + sizeof(*hdr) + 2;
if (skb_headroom(skb) < max_headroom || skb_cloned(skb) || skb_shared(skb)) {
struct sk_buff *new_skb = skb_realloc_headroom(skb, max_headroom);
if (!new_skb) {
ip_rt_put(rt);
goto tx_error;
}
if (skb->sk)
skb_set_owner_w(new_skb, skb->sk);
kfree_skb(skb);
skb = new_skb;
}
data = skb->data;
islcp = ((data[0] << 8) + data[1]) == PPP_LCP && 1 <= data[2] && data[2] <= 7;
/* compress protocol field */
if ((opt->ppp_flags & SC_COMP_PROT) && data[0] == 0 && !islcp)
skb_pull(skb, 1);
/* Put in the address/control bytes if necessary */
if ((opt->ppp_flags & SC_COMP_AC) == 0 || islcp) {
data = skb_push(skb, 2);
data[0] = PPP_ALLSTATIONS;
data[1] = PPP_UI;
}
len = skb->len;
seq_recv = opt->seq_recv;
if (opt->ack_sent == seq_recv)
header_len -= sizeof(hdr->ack);
/* Push down and install GRE header */
skb_push(skb, header_len);
hdr = (struct pptp_gre_header *)(skb->data);
hdr->flags = PPTP_GRE_FLAG_K;
hdr->ver = PPTP_GRE_VER;
hdr->protocol = htons(PPTP_GRE_PROTO);
hdr->call_id = htons(opt->dst_addr.call_id);
hdr->flags |= PPTP_GRE_FLAG_S;
hdr->seq = htonl(++opt->seq_sent);
if (opt->ack_sent != seq_recv) {
/* send ack with this message */
hdr->ver |= PPTP_GRE_FLAG_A;
hdr->ack = htonl(seq_recv);
opt->ack_sent = seq_recv;
}
hdr->payload_len = htons(len);
/* Push down and install the IP header. */
skb_reset_transport_header(skb);
skb_push(skb, sizeof(*iph));
skb_reset_network_header(skb);
memset(&(IPCB(skb)->opt), 0, sizeof(IPCB(skb)->opt));
IPCB(skb)->flags &= ~(IPSKB_XFRM_TUNNEL_SIZE | IPSKB_XFRM_TRANSFORMED | IPSKB_REROUTED);
iph = ip_hdr(skb);
iph->version = 4;
iph->ihl = sizeof(struct iphdr) >> 2;
if (ip_dont_fragment(sk, &rt->dst))
iph->frag_off = htons(IP_DF);
else
iph->frag_off = 0;
iph->protocol = IPPROTO_GRE;
iph->tos = 0;
iph->daddr = fl4.daddr;
iph->saddr = fl4.saddr;
iph->ttl = ip4_dst_hoplimit(&rt->dst);
iph->tot_len = htons(skb->len);
skb_dst_drop(skb);
skb_dst_set(skb, &rt->dst);
nf_reset(skb);
skb->ip_summed = CHECKSUM_NONE;
ip_select_ident(iph, &rt->dst, NULL);
ip_send_check(iph);
ip_local_out(skb);
return 1;
tx_error:
kfree_skb(skb);
return 1;
}
static int pptp_rcv_core(struct sock *sk, struct sk_buff *skb)
{
struct pppox_sock *po = pppox_sk(sk);
struct pptp_opt *opt = &po->proto.pptp;
int headersize, payload_len, seq;
__u8 *payload;
struct pptp_gre_header *header;
if (!(sk->sk_state & PPPOX_CONNECTED)) {
if (sock_queue_rcv_skb(sk, skb))
goto drop;
return NET_RX_SUCCESS;
}
header = (struct pptp_gre_header *)(skb->data);
headersize = sizeof(*header);
/* test if acknowledgement present */
if (PPTP_GRE_IS_A(header->ver)) {
__u32 ack;
if (!pskb_may_pull(skb, headersize))
goto drop;
header = (struct pptp_gre_header *)(skb->data);
/* ack in different place if S = 0 */
ack = PPTP_GRE_IS_S(header->flags) ? header->ack : header->seq;
ack = ntohl(ack);
if (ack > opt->ack_recv)
opt->ack_recv = ack;
/* also handle sequence number wrap-around */
if (WRAPPED(ack, opt->ack_recv))
opt->ack_recv = ack;
} else {
headersize -= sizeof(header->ack);
}
/* test if payload present */
if (!PPTP_GRE_IS_S(header->flags))
goto drop;
payload_len = ntohs(header->payload_len);
seq = ntohl(header->seq);
/* check for incomplete packet (length smaller than expected) */
if (!pskb_may_pull(skb, headersize + payload_len))
goto drop;
payload = skb->data + headersize;
/* check for expected sequence number */
if (seq < opt->seq_recv + 1 || WRAPPED(opt->seq_recv, seq)) {
if ((payload[0] == PPP_ALLSTATIONS) && (payload[1] == PPP_UI) &&
(PPP_PROTOCOL(payload) == PPP_LCP) &&
((payload[4] == PPP_LCP_ECHOREQ) || (payload[4] == PPP_LCP_ECHOREP)))
goto allow_packet;
} else {
opt->seq_recv = seq;
allow_packet:
skb_pull(skb, headersize);
if (payload[0] == PPP_ALLSTATIONS && payload[1] == PPP_UI) {
/* chop off address/control */
if (skb->len < 3)
goto drop;
skb_pull(skb, 2);
}
if ((*skb->data) & 1) {
/* protocol is compressed */
skb_push(skb, 1)[0] = 0;
}
skb->ip_summed = CHECKSUM_NONE;
skb_set_network_header(skb, skb->head-skb->data);
ppp_input(&po->chan, skb);
return NET_RX_SUCCESS;
}
drop:
kfree_skb(skb);
return NET_RX_DROP;
}
static int pptp_rcv(struct sk_buff *skb)
{
struct pppox_sock *po;
struct pptp_gre_header *header;
struct iphdr *iph;
if (skb->pkt_type != PACKET_HOST)
goto drop;
if (!pskb_may_pull(skb, 12))
goto drop;
iph = ip_hdr(skb);
header = (struct pptp_gre_header *)skb->data;
if (ntohs(header->protocol) != PPTP_GRE_PROTO || /* PPTP-GRE protocol for PPTP */
PPTP_GRE_IS_C(header->flags) || /* flag C should be clear */
PPTP_GRE_IS_R(header->flags) || /* flag R should be clear */
!PPTP_GRE_IS_K(header->flags) || /* flag K should be set */
(header->flags&0xF) != 0) /* routing and recursion ctrl = 0 */
/* if invalid, discard this packet */
goto drop;
po = lookup_chan(htons(header->call_id), iph->saddr);
if (po) {
skb_dst_drop(skb);
nf_reset(skb);
return sk_receive_skb(sk_pppox(po), skb, 0);
}
drop:
kfree_skb(skb);
return NET_RX_DROP;
}
static int pptp_bind(struct socket *sock, struct sockaddr *uservaddr,
int sockaddr_len)
{
struct sock *sk = sock->sk;
struct sockaddr_pppox *sp = (struct sockaddr_pppox *) uservaddr;
struct pppox_sock *po = pppox_sk(sk);
struct pptp_opt *opt = &po->proto.pptp;
int error = 0;
lock_sock(sk);
opt->src_addr = sp->sa_addr.pptp;
if (add_chan(po))
error = -EBUSY;
release_sock(sk);
return error;
}
static int pptp_connect(struct socket *sock, struct sockaddr *uservaddr,
int sockaddr_len, int flags)
{
struct sock *sk = sock->sk;
struct sockaddr_pppox *sp = (struct sockaddr_pppox *) uservaddr;
struct pppox_sock *po = pppox_sk(sk);
struct pptp_opt *opt = &po->proto.pptp;
struct rtable *rt;
struct flowi4 fl4;
int error = 0;
if (sp->sa_protocol != PX_PROTO_PPTP)
return -EINVAL;
if (lookup_chan_dst(sp->sa_addr.pptp.call_id, sp->sa_addr.pptp.sin_addr.s_addr))
return -EALREADY;
lock_sock(sk);
/* Check for already bound sockets */
if (sk->sk_state & PPPOX_CONNECTED) {
error = -EBUSY;
goto end;
}
/* Check for already disconnected sockets, on attempts to disconnect */
if (sk->sk_state & PPPOX_DEAD) {
error = -EALREADY;
goto end;
}
if (!opt->src_addr.sin_addr.s_addr || !sp->sa_addr.pptp.sin_addr.s_addr) {
error = -EINVAL;
goto end;
}
po->chan.private = sk;
po->chan.ops = &pptp_chan_ops;
rt = ip_route_output_ports(&init_net, &fl4, sk,
opt->dst_addr.sin_addr.s_addr,
opt->src_addr.sin_addr.s_addr,
0, 0,
IPPROTO_GRE, RT_CONN_FLAGS(sk), 0);
if (IS_ERR(rt)) {
error = -EHOSTUNREACH;
goto end;
}
sk_setup_caps(sk, &rt->dst);
po->chan.mtu = dst_mtu(&rt->dst);
if (!po->chan.mtu)
po->chan.mtu = PPP_MTU;
ip_rt_put(rt);
po->chan.mtu -= PPTP_HEADER_OVERHEAD;
po->chan.hdrlen = 2 + sizeof(struct pptp_gre_header);
error = ppp_register_channel(&po->chan);
if (error) {
pr_err("PPTP: failed to register PPP channel (%d)\n", error);
goto end;
}
opt->dst_addr = sp->sa_addr.pptp;
sk->sk_state = PPPOX_CONNECTED;
end:
release_sock(sk);
return error;
}
static int pptp_getname(struct socket *sock, struct sockaddr *uaddr,
int *usockaddr_len, int peer)
{
int len = sizeof(struct sockaddr_pppox);
struct sockaddr_pppox sp;
sp.sa_family = AF_PPPOX;
sp.sa_protocol = PX_PROTO_PPTP;
sp.sa_addr.pptp = pppox_sk(sock->sk)->proto.pptp.src_addr;
memcpy(uaddr, &sp, len);
*usockaddr_len = len;
return 0;
}
static int pptp_release(struct socket *sock)
{
struct sock *sk = sock->sk;
struct pppox_sock *po;
struct pptp_opt *opt;
int error = 0;
if (!sk)
return 0;
lock_sock(sk);
if (sock_flag(sk, SOCK_DEAD)) {
release_sock(sk);
return -EBADF;
}
po = pppox_sk(sk);
opt = &po->proto.pptp;
del_chan(po);
pppox_unbind_sock(sk);
sk->sk_state = PPPOX_DEAD;
sock_orphan(sk);
sock->sk = NULL;
release_sock(sk);
sock_put(sk);
return error;
}
static void pptp_sock_destruct(struct sock *sk)
{
if (!(sk->sk_state & PPPOX_DEAD)) {
del_chan(pppox_sk(sk));
pppox_unbind_sock(sk);
}
skb_queue_purge(&sk->sk_receive_queue);
}
static int pptp_create(struct net *net, struct socket *sock)
{
int error = -ENOMEM;
struct sock *sk;
struct pppox_sock *po;
struct pptp_opt *opt;
sk = sk_alloc(net, PF_PPPOX, GFP_KERNEL, &pptp_sk_proto);
if (!sk)
goto out;
sock_init_data(sock, sk);
sock->state = SS_UNCONNECTED;
sock->ops = &pptp_ops;
sk->sk_backlog_rcv = pptp_rcv_core;
sk->sk_state = PPPOX_NONE;
sk->sk_type = SOCK_STREAM;
sk->sk_family = PF_PPPOX;
sk->sk_protocol = PX_PROTO_PPTP;
sk->sk_destruct = pptp_sock_destruct;
po = pppox_sk(sk);
opt = &po->proto.pptp;
opt->seq_sent = 0; opt->seq_recv = 0;
opt->ack_recv = 0; opt->ack_sent = 0;
error = 0;
out:
return error;
}
static int pptp_ppp_ioctl(struct ppp_channel *chan, unsigned int cmd,
unsigned long arg)
{
struct sock *sk = (struct sock *) chan->private;
struct pppox_sock *po = pppox_sk(sk);
struct pptp_opt *opt = &po->proto.pptp;
void __user *argp = (void __user *)arg;
int __user *p = argp;
int err, val;
err = -EFAULT;
switch (cmd) {
case PPPIOCGFLAGS:
val = opt->ppp_flags;
if (put_user(val, p))
break;
err = 0;
break;
case PPPIOCSFLAGS:
if (get_user(val, p))
break;
opt->ppp_flags = val & ~SC_RCV_BITS;
err = 0;
break;
default:
err = -ENOTTY;
}
return err;
}
static const struct ppp_channel_ops pptp_chan_ops = {
.start_xmit = pptp_xmit,
.ioctl = pptp_ppp_ioctl,
};
static struct proto pptp_sk_proto __read_mostly = {
.name = "PPTP",
.owner = THIS_MODULE,
.obj_size = sizeof(struct pppox_sock),
};
static const struct proto_ops pptp_ops = {
.family = AF_PPPOX,
.owner = THIS_MODULE,
.release = pptp_release,
.bind = pptp_bind,
.connect = pptp_connect,
.socketpair = sock_no_socketpair,
.accept = sock_no_accept,
.getname = pptp_getname,
.poll = sock_no_poll,
.listen = sock_no_listen,
.shutdown = sock_no_shutdown,
.setsockopt = sock_no_setsockopt,
.getsockopt = sock_no_getsockopt,
.sendmsg = sock_no_sendmsg,
.recvmsg = sock_no_recvmsg,
.mmap = sock_no_mmap,
.ioctl = pppox_ioctl,
};
static const struct pppox_proto pppox_pptp_proto = {
.create = pptp_create,
.owner = THIS_MODULE,
};
static const struct gre_protocol gre_pptp_protocol = {
.handler = pptp_rcv,
};
static int __init pptp_init_module(void)
{
int err = 0;
pr_info("PPTP driver version " PPTP_DRIVER_VERSION "\n");
callid_sock = vzalloc((MAX_CALLID + 1) * sizeof(void *));
if (!callid_sock) {
pr_err("PPTP: cann't allocate memory\n");
return -ENOMEM;
}
err = gre_add_protocol(&gre_pptp_protocol, GREPROTO_PPTP);
if (err) {
pr_err("PPTP: can't add gre protocol\n");
goto out_mem_free;
}
err = proto_register(&pptp_sk_proto, 0);
if (err) {
pr_err("PPTP: can't register sk_proto\n");
goto out_gre_del_protocol;
}
err = register_pppox_proto(PX_PROTO_PPTP, &pppox_pptp_proto);
if (err) {
pr_err("PPTP: can't register pppox_proto\n");
goto out_unregister_sk_proto;
}
return 0;
out_unregister_sk_proto:
proto_unregister(&pptp_sk_proto);
out_gre_del_protocol:
gre_del_protocol(&gre_pptp_protocol, GREPROTO_PPTP);
out_mem_free:
vfree(callid_sock);
return err;
}
static void __exit pptp_exit_module(void)
{
unregister_pppox_proto(PX_PROTO_PPTP);
proto_unregister(&pptp_sk_proto);
gre_del_protocol(&gre_pptp_protocol, GREPROTO_PPTP);
vfree(callid_sock);
}
module_init(pptp_init_module);
module_exit(pptp_exit_module);
MODULE_DESCRIPTION("Point-to-Point Tunneling Protocol");
MODULE_AUTHOR("D. Kozlov (xeb@mail.ru)");
MODULE_LICENSE("GPL");
| gpl-2.0 |
networkimprov/linux | drivers/clocksource/em_sti.c | 430 | 9914 | /*
* Emma Mobile Timer Support - STI
*
* Copyright (C) 2012 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/slab.h>
#include <linux/module.h>
enum { USER_CLOCKSOURCE, USER_CLOCKEVENT, USER_NR };
struct em_sti_priv {
void __iomem *base;
struct clk *clk;
struct platform_device *pdev;
unsigned int active[USER_NR];
unsigned long rate;
raw_spinlock_t lock;
struct clock_event_device ced;
struct clocksource cs;
};
#define STI_CONTROL 0x00
#define STI_COMPA_H 0x10
#define STI_COMPA_L 0x14
#define STI_COMPB_H 0x18
#define STI_COMPB_L 0x1c
#define STI_COUNT_H 0x20
#define STI_COUNT_L 0x24
#define STI_COUNT_RAW_H 0x28
#define STI_COUNT_RAW_L 0x2c
#define STI_SET_H 0x30
#define STI_SET_L 0x34
#define STI_INTSTATUS 0x40
#define STI_INTRAWSTATUS 0x44
#define STI_INTENSET 0x48
#define STI_INTENCLR 0x4c
#define STI_INTFFCLR 0x50
static inline unsigned long em_sti_read(struct em_sti_priv *p, int offs)
{
return ioread32(p->base + offs);
}
static inline void em_sti_write(struct em_sti_priv *p, int offs,
unsigned long value)
{
iowrite32(value, p->base + offs);
}
static int em_sti_enable(struct em_sti_priv *p)
{
int ret;
/* enable clock */
ret = clk_enable(p->clk);
if (ret) {
dev_err(&p->pdev->dev, "cannot enable clock\n");
return ret;
}
/* configure channel, periodic mode and maximum timeout */
p->rate = clk_get_rate(p->clk);
/* reset the counter */
em_sti_write(p, STI_SET_H, 0x40000000);
em_sti_write(p, STI_SET_L, 0x00000000);
/* mask and clear pending interrupts */
em_sti_write(p, STI_INTENCLR, 3);
em_sti_write(p, STI_INTFFCLR, 3);
/* enable updates of counter registers */
em_sti_write(p, STI_CONTROL, 1);
return 0;
}
static void em_sti_disable(struct em_sti_priv *p)
{
/* mask interrupts */
em_sti_write(p, STI_INTENCLR, 3);
/* stop clock */
clk_disable(p->clk);
}
static cycle_t em_sti_count(struct em_sti_priv *p)
{
cycle_t ticks;
unsigned long flags;
/* the STI hardware buffers the 48-bit count, but to
* break it out into two 32-bit access the registers
* must be accessed in a certain order.
* Always read STI_COUNT_H before STI_COUNT_L.
*/
raw_spin_lock_irqsave(&p->lock, flags);
ticks = (cycle_t)(em_sti_read(p, STI_COUNT_H) & 0xffff) << 32;
ticks |= em_sti_read(p, STI_COUNT_L);
raw_spin_unlock_irqrestore(&p->lock, flags);
return ticks;
}
static cycle_t em_sti_set_next(struct em_sti_priv *p, cycle_t next)
{
unsigned long flags;
raw_spin_lock_irqsave(&p->lock, flags);
/* mask compare A interrupt */
em_sti_write(p, STI_INTENCLR, 1);
/* update compare A value */
em_sti_write(p, STI_COMPA_H, next >> 32);
em_sti_write(p, STI_COMPA_L, next & 0xffffffff);
/* clear compare A interrupt source */
em_sti_write(p, STI_INTFFCLR, 1);
/* unmask compare A interrupt */
em_sti_write(p, STI_INTENSET, 1);
raw_spin_unlock_irqrestore(&p->lock, flags);
return next;
}
static irqreturn_t em_sti_interrupt(int irq, void *dev_id)
{
struct em_sti_priv *p = dev_id;
p->ced.event_handler(&p->ced);
return IRQ_HANDLED;
}
static int em_sti_start(struct em_sti_priv *p, unsigned int user)
{
unsigned long flags;
int used_before;
int ret = 0;
raw_spin_lock_irqsave(&p->lock, flags);
used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
if (!used_before)
ret = em_sti_enable(p);
if (!ret)
p->active[user] = 1;
raw_spin_unlock_irqrestore(&p->lock, flags);
return ret;
}
static void em_sti_stop(struct em_sti_priv *p, unsigned int user)
{
unsigned long flags;
int used_before, used_after;
raw_spin_lock_irqsave(&p->lock, flags);
used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
p->active[user] = 0;
used_after = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
if (used_before && !used_after)
em_sti_disable(p);
raw_spin_unlock_irqrestore(&p->lock, flags);
}
static struct em_sti_priv *cs_to_em_sti(struct clocksource *cs)
{
return container_of(cs, struct em_sti_priv, cs);
}
static cycle_t em_sti_clocksource_read(struct clocksource *cs)
{
return em_sti_count(cs_to_em_sti(cs));
}
static int em_sti_clocksource_enable(struct clocksource *cs)
{
int ret;
struct em_sti_priv *p = cs_to_em_sti(cs);
ret = em_sti_start(p, USER_CLOCKSOURCE);
if (!ret)
__clocksource_updatefreq_hz(cs, p->rate);
return ret;
}
static void em_sti_clocksource_disable(struct clocksource *cs)
{
em_sti_stop(cs_to_em_sti(cs), USER_CLOCKSOURCE);
}
static void em_sti_clocksource_resume(struct clocksource *cs)
{
em_sti_clocksource_enable(cs);
}
static int em_sti_register_clocksource(struct em_sti_priv *p)
{
struct clocksource *cs = &p->cs;
memset(cs, 0, sizeof(*cs));
cs->name = dev_name(&p->pdev->dev);
cs->rating = 200;
cs->read = em_sti_clocksource_read;
cs->enable = em_sti_clocksource_enable;
cs->disable = em_sti_clocksource_disable;
cs->suspend = em_sti_clocksource_disable;
cs->resume = em_sti_clocksource_resume;
cs->mask = CLOCKSOURCE_MASK(48);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
dev_info(&p->pdev->dev, "used as clock source\n");
/* Register with dummy 1 Hz value, gets updated in ->enable() */
clocksource_register_hz(cs, 1);
return 0;
}
static struct em_sti_priv *ced_to_em_sti(struct clock_event_device *ced)
{
return container_of(ced, struct em_sti_priv, ced);
}
static void em_sti_clock_event_mode(enum clock_event_mode mode,
struct clock_event_device *ced)
{
struct em_sti_priv *p = ced_to_em_sti(ced);
/* deal with old setting first */
switch (ced->mode) {
case CLOCK_EVT_MODE_ONESHOT:
em_sti_stop(p, USER_CLOCKEVENT);
break;
default:
break;
}
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
dev_info(&p->pdev->dev, "used for oneshot clock events\n");
em_sti_start(p, USER_CLOCKEVENT);
clockevents_config(&p->ced, p->rate);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
em_sti_stop(p, USER_CLOCKEVENT);
break;
default:
break;
}
}
static int em_sti_clock_event_next(unsigned long delta,
struct clock_event_device *ced)
{
struct em_sti_priv *p = ced_to_em_sti(ced);
cycle_t next;
int safe;
next = em_sti_set_next(p, em_sti_count(p) + delta);
safe = em_sti_count(p) < (next - 1);
return !safe;
}
static void em_sti_register_clockevent(struct em_sti_priv *p)
{
struct clock_event_device *ced = &p->ced;
memset(ced, 0, sizeof(*ced));
ced->name = dev_name(&p->pdev->dev);
ced->features = CLOCK_EVT_FEAT_ONESHOT;
ced->rating = 200;
ced->cpumask = cpumask_of(0);
ced->set_next_event = em_sti_clock_event_next;
ced->set_mode = em_sti_clock_event_mode;
dev_info(&p->pdev->dev, "used for clock events\n");
/* Register with dummy 1 Hz value, gets updated in ->set_mode() */
clockevents_config_and_register(ced, 1, 2, 0xffffffff);
}
static int em_sti_probe(struct platform_device *pdev)
{
struct em_sti_priv *p;
struct resource *res;
int irq, ret;
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (p == NULL) {
dev_err(&pdev->dev, "failed to allocate driver data\n");
ret = -ENOMEM;
goto err0;
}
p->pdev = pdev;
platform_set_drvdata(pdev, p);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get I/O memory\n");
ret = -EINVAL;
goto err0;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to get irq\n");
ret = -EINVAL;
goto err0;
}
/* map memory, let base point to the STI instance */
p->base = ioremap_nocache(res->start, resource_size(res));
if (p->base == NULL) {
dev_err(&pdev->dev, "failed to remap I/O memory\n");
ret = -ENXIO;
goto err0;
}
/* get hold of clock */
p->clk = clk_get(&pdev->dev, "sclk");
if (IS_ERR(p->clk)) {
dev_err(&pdev->dev, "cannot get clock\n");
ret = PTR_ERR(p->clk);
goto err1;
}
if (request_irq(irq, em_sti_interrupt,
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
dev_name(&pdev->dev), p)) {
dev_err(&pdev->dev, "failed to request low IRQ\n");
ret = -ENOENT;
goto err2;
}
raw_spin_lock_init(&p->lock);
em_sti_register_clockevent(p);
em_sti_register_clocksource(p);
return 0;
err2:
clk_put(p->clk);
err1:
iounmap(p->base);
err0:
kfree(p);
return ret;
}
static int em_sti_remove(struct platform_device *pdev)
{
return -EBUSY; /* cannot unregister clockevent and clocksource */
}
static const struct of_device_id em_sti_dt_ids[] = {
{ .compatible = "renesas,em-sti", },
{},
};
MODULE_DEVICE_TABLE(of, em_sti_dt_ids);
static struct platform_driver em_sti_device_driver = {
.probe = em_sti_probe,
.remove = em_sti_remove,
.driver = {
.name = "em_sti",
.of_match_table = em_sti_dt_ids,
}
};
static int __init em_sti_init(void)
{
return platform_driver_register(&em_sti_device_driver);
}
static void __exit em_sti_exit(void)
{
platform_driver_unregister(&em_sti_device_driver);
}
subsys_initcall(em_sti_init);
module_exit(em_sti_exit);
MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
oppo-source/R7f-4.4-kernel-source | fs/file_table.c | 686 | 12674 | /*
* linux/fs/file_table.c
*
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
*/
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/file.h>
#include <linux/fdtable.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/security.h>
#include <linux/eventpoll.h>
#include <linux/rcupdate.h>
#include <linux/mount.h>
#include <linux/capability.h>
#include <linux/cdev.h>
#include <linux/fsnotify.h>
#include <linux/sysctl.h>
#include <linux/lglock.h>
#include <linux/percpu_counter.h>
#include <linux/percpu.h>
#include <linux/hardirq.h>
#include <linux/task_work.h>
#include <linux/ima.h>
#include <linux/atomic.h>
#include "internal.h"
/* sysctl tunables... */
struct files_stat_struct files_stat = {
.max_files = NR_FILE
};
DEFINE_STATIC_LGLOCK(files_lglock);
/* SLAB cache for file structures */
static struct kmem_cache *filp_cachep __read_mostly;
static struct percpu_counter nr_files __cacheline_aligned_in_smp;
static void file_free_rcu(struct rcu_head *head)
{
struct file *f = container_of(head, struct file, f_u.fu_rcuhead);
put_cred(f->f_cred);
kmem_cache_free(filp_cachep, f);
}
static inline void file_free(struct file *f)
{
percpu_counter_dec(&nr_files);
file_check_state(f);
call_rcu(&f->f_u.fu_rcuhead, file_free_rcu);
}
/*
* Return the total number of open files in the system
*/
static long get_nr_files(void)
{
return percpu_counter_read_positive(&nr_files);
}
/*
* Return the maximum number of open files in the system
*/
unsigned long get_max_files(void)
{
return files_stat.max_files;
}
EXPORT_SYMBOL_GPL(get_max_files);
/*
* Handle nr_files sysctl
*/
#if defined(CONFIG_SYSCTL) && defined(CONFIG_PROC_FS)
int proc_nr_files(ctl_table *table, int write,
void __user *buffer, size_t *lenp, loff_t *ppos)
{
files_stat.nr_files = get_nr_files();
return proc_doulongvec_minmax(table, write, buffer, lenp, ppos);
}
#else
int proc_nr_files(ctl_table *table, int write,
void __user *buffer, size_t *lenp, loff_t *ppos)
{
return -ENOSYS;
}
#endif
/* Find an unused file structure and return a pointer to it.
* Returns an error pointer if some error happend e.g. we over file
* structures limit, run out of memory or operation is not permitted.
*
* Be very careful using this. You are responsible for
* getting write access to any mount that you might assign
* to this filp, if it is opened for write. If this is not
* done, you will imbalance int the mount's writer count
* and a warning at __fput() time.
*/
struct file *get_empty_filp(void)
{
const struct cred *cred = current_cred();
static long old_max;
struct file *f;
int error;
/*
* Privileged users can go above max_files
*/
if (get_nr_files() >= files_stat.max_files && !capable(CAP_SYS_ADMIN)) {
/*
* percpu_counters are inaccurate. Do an expensive check before
* we go and fail.
*/
if (percpu_counter_sum_positive(&nr_files) >= files_stat.max_files)
goto over;
}
f = kmem_cache_zalloc(filp_cachep, GFP_KERNEL);
if (unlikely(!f))
return ERR_PTR(-ENOMEM);
percpu_counter_inc(&nr_files);
f->f_cred = get_cred(cred);
error = security_file_alloc(f);
if (unlikely(error)) {
file_free(f);
return ERR_PTR(error);
}
INIT_LIST_HEAD(&f->f_u.fu_list);
atomic_long_set(&f->f_count, 1);
rwlock_init(&f->f_owner.lock);
spin_lock_init(&f->f_lock);
eventpoll_init_file(f);
/* f->f_version: 0 */
return f;
over:
/* Ran out of filps - report that */
if (get_nr_files() > old_max) {
pr_info("VFS: file-max limit %lu reached\n", get_max_files());
old_max = get_nr_files();
}
return ERR_PTR(-ENFILE);
}
/**
* alloc_file - allocate and initialize a 'struct file'
* @mnt: the vfsmount on which the file will reside
* @dentry: the dentry representing the new file
* @mode: the mode with which the new file will be opened
* @fop: the 'struct file_operations' for the new file
*
* Use this instead of get_empty_filp() to get a new
* 'struct file'. Do so because of the same initialization
* pitfalls reasons listed for init_file(). This is a
* preferred interface to using init_file().
*
* If all the callers of init_file() are eliminated, its
* code should be moved into this function.
*/
struct file *alloc_file(struct path *path, fmode_t mode,
const struct file_operations *fop)
{
struct file *file;
file = get_empty_filp();
if (IS_ERR(file))
return file;
file->f_path = *path;
file->f_inode = path->dentry->d_inode;
file->f_mapping = path->dentry->d_inode->i_mapping;
file->f_mode = mode;
file->f_op = fop;
/*
* These mounts don't really matter in practice
* for r/o bind mounts. They aren't userspace-
* visible. We do this for consistency, and so
* that we can do debugging checks at __fput()
*/
if ((mode & FMODE_WRITE) && !special_file(path->dentry->d_inode->i_mode)) {
file_take_write(file);
WARN_ON(mnt_clone_write(path->mnt));
}
if ((mode & (FMODE_READ | FMODE_WRITE)) == FMODE_READ)
i_readcount_inc(path->dentry->d_inode);
return file;
}
EXPORT_SYMBOL(alloc_file);
/**
* drop_file_write_access - give up ability to write to a file
* @file: the file to which we will stop writing
*
* This is a central place which will give up the ability
* to write to @file, along with access to write through
* its vfsmount.
*/
static void drop_file_write_access(struct file *file)
{
struct vfsmount *mnt = file->f_path.mnt;
struct dentry *dentry = file->f_path.dentry;
struct inode *inode = dentry->d_inode;
put_write_access(inode);
if (special_file(inode->i_mode))
return;
if (file_check_writeable(file) != 0)
return;
__mnt_drop_write(mnt);
file_release_write(file);
}
/* the real guts of fput() - releasing the last reference to file
*/
static void __fput(struct file *file)
{
struct dentry *dentry = file->f_path.dentry;
struct vfsmount *mnt = file->f_path.mnt;
struct inode *inode = dentry->d_inode;
might_sleep();
fsnotify_close(file);
/*
* The function eventpoll_release() should be the first called
* in the file cleanup chain.
*/
eventpoll_release(file);
locks_remove_flock(file);
if (unlikely(file->f_flags & FASYNC)) {
if (file->f_op && file->f_op->fasync)
file->f_op->fasync(-1, file, 0);
}
ima_file_free(file);
if (file->f_op && file->f_op->release)
file->f_op->release(inode, file);
security_file_free(file);
if (unlikely(S_ISCHR(inode->i_mode) && inode->i_cdev != NULL &&
!(file->f_mode & FMODE_PATH))) {
cdev_put(inode->i_cdev);
}
fops_put(file->f_op);
put_pid(file->f_owner.pid);
if ((file->f_mode & (FMODE_READ | FMODE_WRITE)) == FMODE_READ)
i_readcount_dec(inode);
if (file->f_mode & FMODE_WRITE)
drop_file_write_access(file);
file->f_path.dentry = NULL;
file->f_path.mnt = NULL;
file->f_inode = NULL;
file_free(file);
dput(dentry);
mntput(mnt);
}
static DEFINE_SPINLOCK(delayed_fput_lock);
static LIST_HEAD(delayed_fput_list);
static void delayed_fput(struct work_struct *unused)
{
LIST_HEAD(head);
spin_lock_irq(&delayed_fput_lock);
list_splice_init(&delayed_fput_list, &head);
spin_unlock_irq(&delayed_fput_lock);
while (!list_empty(&head)) {
struct file *f = list_first_entry(&head, struct file, f_u.fu_list);
list_del_init(&f->f_u.fu_list);
__fput(f);
}
}
static void ____fput(struct callback_head *work)
{
__fput(container_of(work, struct file, f_u.fu_rcuhead));
}
/*
* If kernel thread really needs to have the final fput() it has done
* to complete, call this. The only user right now is the boot - we
* *do* need to make sure our writes to binaries on initramfs has
* not left us with opened struct file waiting for __fput() - execve()
* won't work without that. Please, don't add more callers without
* very good reasons; in particular, never call that with locks
* held and never call that from a thread that might need to do
* some work on any kind of umount.
*/
void flush_delayed_fput(void)
{
delayed_fput(NULL);
}
static DECLARE_WORK(delayed_fput_work, delayed_fput);
void fput(struct file *file)
{
if (atomic_long_dec_and_test(&file->f_count)) {
struct task_struct *task = current;
unsigned long flags;
file_sb_list_del(file);
if (likely(!in_interrupt() && !(task->flags & PF_KTHREAD))) {
init_task_work(&file->f_u.fu_rcuhead, ____fput);
if (!task_work_add(task, &file->f_u.fu_rcuhead, true))
return;
}
spin_lock_irqsave(&delayed_fput_lock, flags);
list_add(&file->f_u.fu_list, &delayed_fput_list);
schedule_work(&delayed_fput_work);
spin_unlock_irqrestore(&delayed_fput_lock, flags);
}
}
/*
* synchronous analog of fput(); for kernel threads that might be needed
* in some umount() (and thus can't use flush_delayed_fput() without
* risking deadlocks), need to wait for completion of __fput() and know
* for this specific struct file it won't involve anything that would
* need them. Use only if you really need it - at the very least,
* don't blindly convert fput() by kernel thread to that.
*/
void __fput_sync(struct file *file)
{
if (atomic_long_dec_and_test(&file->f_count)) {
struct task_struct *task = current;
file_sb_list_del(file);
BUG_ON(!(task->flags & PF_KTHREAD));
__fput(file);
}
}
EXPORT_SYMBOL(fput);
void put_filp(struct file *file)
{
if (atomic_long_dec_and_test(&file->f_count)) {
security_file_free(file);
file_sb_list_del(file);
file_free(file);
}
}
static inline int file_list_cpu(struct file *file)
{
#ifdef CONFIG_SMP
return file->f_sb_list_cpu;
#else
return smp_processor_id();
#endif
}
/* helper for file_sb_list_add to reduce ifdefs */
static inline void __file_sb_list_add(struct file *file, struct super_block *sb)
{
struct list_head *list;
#ifdef CONFIG_SMP
int cpu;
cpu = smp_processor_id();
file->f_sb_list_cpu = cpu;
list = per_cpu_ptr(sb->s_files, cpu);
#else
list = &sb->s_files;
#endif
list_add(&file->f_u.fu_list, list);
}
/**
* file_sb_list_add - add a file to the sb's file list
* @file: file to add
* @sb: sb to add it to
*
* Use this function to associate a file with the superblock of the inode it
* refers to.
*/
void file_sb_list_add(struct file *file, struct super_block *sb)
{
lg_local_lock(&files_lglock);
__file_sb_list_add(file, sb);
lg_local_unlock(&files_lglock);
}
/**
* file_sb_list_del - remove a file from the sb's file list
* @file: file to remove
* @sb: sb to remove it from
*
* Use this function to remove a file from its superblock.
*/
void file_sb_list_del(struct file *file)
{
if (!list_empty(&file->f_u.fu_list)) {
lg_local_lock_cpu(&files_lglock, file_list_cpu(file));
list_del_init(&file->f_u.fu_list);
lg_local_unlock_cpu(&files_lglock, file_list_cpu(file));
}
}
#ifdef CONFIG_SMP
/*
* These macros iterate all files on all CPUs for a given superblock.
* files_lglock must be held globally.
*/
#define do_file_list_for_each_entry(__sb, __file) \
{ \
int i; \
for_each_possible_cpu(i) { \
struct list_head *list; \
list = per_cpu_ptr((__sb)->s_files, i); \
list_for_each_entry((__file), list, f_u.fu_list)
#define while_file_list_for_each_entry \
} \
}
#else
#define do_file_list_for_each_entry(__sb, __file) \
{ \
struct list_head *list; \
list = &(sb)->s_files; \
list_for_each_entry((__file), list, f_u.fu_list)
#define while_file_list_for_each_entry \
}
#endif
/**
* mark_files_ro - mark all files read-only
* @sb: superblock in question
*
* All files are marked read-only. We don't care about pending
* delete files so this should be used in 'force' mode only.
*/
void mark_files_ro(struct super_block *sb)
{
struct file *f;
lg_global_lock(&files_lglock);
do_file_list_for_each_entry(sb, f) {
if (!S_ISREG(file_inode(f)->i_mode))
continue;
if (!file_count(f))
continue;
if (!(f->f_mode & FMODE_WRITE))
continue;
spin_lock(&f->f_lock);
f->f_mode &= ~FMODE_WRITE;
spin_unlock(&f->f_lock);
if (file_check_writeable(f) != 0)
continue;
__mnt_drop_write(f->f_path.mnt);
file_release_write(f);
} while_file_list_for_each_entry;
lg_global_unlock(&files_lglock);
}
void __init files_init(unsigned long mempages)
{
unsigned long n;
filp_cachep = kmem_cache_create("filp", sizeof(struct file), 0,
SLAB_HWCACHE_ALIGN | SLAB_PANIC, NULL);
/*
* One file with associated inode and dcache is very roughly 1K.
* Per default don't use more than 10% of our memory for files.
*/
n = (mempages * (PAGE_SIZE / 1024)) / 10;
files_stat.max_files = max_t(unsigned long, n, NR_FILE);
files_defer_init();
lg_lock_init(&files_lglock, "files_lglock");
percpu_counter_init(&nr_files, 0);
}
| gpl-2.0 |
sandy-harris/random.gcm | fs/nfs/nfs3xdr.c | 686 | 56217 | /*
* linux/fs/nfs/nfs3xdr.c
*
* XDR functions to encode/decode NFSv3 RPC arguments and results.
*
* Copyright (C) 1996, 1997 Olaf Kirch
*/
#include <linux/param.h>
#include <linux/time.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/in.h>
#include <linux/pagemap.h>
#include <linux/proc_fs.h>
#include <linux/kdev_t.h>
#include <linux/sunrpc/clnt.h>
#include <linux/nfs.h>
#include <linux/nfs3.h>
#include <linux/nfs_fs.h>
#include <linux/nfsacl.h>
#include "internal.h"
#define NFSDBG_FACILITY NFSDBG_XDR
/* Mapping from NFS error code to "errno" error code. */
#define errno_NFSERR_IO EIO
/*
* Declare the space requirements for NFS arguments and replies as
* number of 32bit-words
*/
#define NFS3_fhandle_sz (1+16)
#define NFS3_fh_sz (NFS3_fhandle_sz) /* shorthand */
#define NFS3_sattr_sz (15)
#define NFS3_filename_sz (1+(NFS3_MAXNAMLEN>>2))
#define NFS3_path_sz (1+(NFS3_MAXPATHLEN>>2))
#define NFS3_fattr_sz (21)
#define NFS3_cookieverf_sz (NFS3_COOKIEVERFSIZE>>2)
#define NFS3_wcc_attr_sz (6)
#define NFS3_pre_op_attr_sz (1+NFS3_wcc_attr_sz)
#define NFS3_post_op_attr_sz (1+NFS3_fattr_sz)
#define NFS3_wcc_data_sz (NFS3_pre_op_attr_sz+NFS3_post_op_attr_sz)
#define NFS3_diropargs_sz (NFS3_fh_sz+NFS3_filename_sz)
#define NFS3_getattrargs_sz (NFS3_fh_sz)
#define NFS3_setattrargs_sz (NFS3_fh_sz+NFS3_sattr_sz+3)
#define NFS3_lookupargs_sz (NFS3_fh_sz+NFS3_filename_sz)
#define NFS3_accessargs_sz (NFS3_fh_sz+1)
#define NFS3_readlinkargs_sz (NFS3_fh_sz)
#define NFS3_readargs_sz (NFS3_fh_sz+3)
#define NFS3_writeargs_sz (NFS3_fh_sz+5)
#define NFS3_createargs_sz (NFS3_diropargs_sz+NFS3_sattr_sz)
#define NFS3_mkdirargs_sz (NFS3_diropargs_sz+NFS3_sattr_sz)
#define NFS3_symlinkargs_sz (NFS3_diropargs_sz+1+NFS3_sattr_sz)
#define NFS3_mknodargs_sz (NFS3_diropargs_sz+2+NFS3_sattr_sz)
#define NFS3_removeargs_sz (NFS3_fh_sz+NFS3_filename_sz)
#define NFS3_renameargs_sz (NFS3_diropargs_sz+NFS3_diropargs_sz)
#define NFS3_linkargs_sz (NFS3_fh_sz+NFS3_diropargs_sz)
#define NFS3_readdirargs_sz (NFS3_fh_sz+NFS3_cookieverf_sz+3)
#define NFS3_readdirplusargs_sz (NFS3_fh_sz+NFS3_cookieverf_sz+4)
#define NFS3_commitargs_sz (NFS3_fh_sz+3)
#define NFS3_getattrres_sz (1+NFS3_fattr_sz)
#define NFS3_setattrres_sz (1+NFS3_wcc_data_sz)
#define NFS3_removeres_sz (NFS3_setattrres_sz)
#define NFS3_lookupres_sz (1+NFS3_fh_sz+(2 * NFS3_post_op_attr_sz))
#define NFS3_accessres_sz (1+NFS3_post_op_attr_sz+1)
#define NFS3_readlinkres_sz (1+NFS3_post_op_attr_sz+1)
#define NFS3_readres_sz (1+NFS3_post_op_attr_sz+3)
#define NFS3_writeres_sz (1+NFS3_wcc_data_sz+4)
#define NFS3_createres_sz (1+NFS3_fh_sz+NFS3_post_op_attr_sz+NFS3_wcc_data_sz)
#define NFS3_renameres_sz (1+(2 * NFS3_wcc_data_sz))
#define NFS3_linkres_sz (1+NFS3_post_op_attr_sz+NFS3_wcc_data_sz)
#define NFS3_readdirres_sz (1+NFS3_post_op_attr_sz+2)
#define NFS3_fsstatres_sz (1+NFS3_post_op_attr_sz+13)
#define NFS3_fsinfores_sz (1+NFS3_post_op_attr_sz+12)
#define NFS3_pathconfres_sz (1+NFS3_post_op_attr_sz+6)
#define NFS3_commitres_sz (1+NFS3_wcc_data_sz+2)
#define ACL3_getaclargs_sz (NFS3_fh_sz+1)
#define ACL3_setaclargs_sz (NFS3_fh_sz+1+ \
XDR_QUADLEN(NFS_ACL_INLINE_BUFSIZE))
#define ACL3_getaclres_sz (1+NFS3_post_op_attr_sz+1+ \
XDR_QUADLEN(NFS_ACL_INLINE_BUFSIZE))
#define ACL3_setaclres_sz (1+NFS3_post_op_attr_sz)
static int nfs3_stat_to_errno(enum nfs_stat);
/*
* Map file type to S_IFMT bits
*/
static const umode_t nfs_type2fmt[] = {
[NF3BAD] = 0,
[NF3REG] = S_IFREG,
[NF3DIR] = S_IFDIR,
[NF3BLK] = S_IFBLK,
[NF3CHR] = S_IFCHR,
[NF3LNK] = S_IFLNK,
[NF3SOCK] = S_IFSOCK,
[NF3FIFO] = S_IFIFO,
};
/*
* While encoding arguments, set up the reply buffer in advance to
* receive reply data directly into the page cache.
*/
static void prepare_reply_buffer(struct rpc_rqst *req, struct page **pages,
unsigned int base, unsigned int len,
unsigned int bufsize)
{
struct rpc_auth *auth = req->rq_cred->cr_auth;
unsigned int replen;
replen = RPC_REPHDRSIZE + auth->au_rslack + bufsize;
xdr_inline_pages(&req->rq_rcv_buf, replen << 2, pages, base, len);
}
/*
* Handle decode buffer overflows out-of-line.
*/
static void print_overflow_msg(const char *func, const struct xdr_stream *xdr)
{
dprintk("NFS: %s prematurely hit the end of our receive buffer. "
"Remaining buffer length is %tu words.\n",
func, xdr->end - xdr->p);
}
/*
* Encode/decode NFSv3 basic data types
*
* Basic NFSv3 data types are defined in section 2.5 of RFC 1813:
* "NFS Version 3 Protocol Specification".
*
* Not all basic data types have their own encoding and decoding
* functions. For run-time efficiency, some data types are encoded
* or decoded inline.
*/
static void encode_uint32(struct xdr_stream *xdr, u32 value)
{
__be32 *p = xdr_reserve_space(xdr, 4);
*p = cpu_to_be32(value);
}
static int decode_uint32(struct xdr_stream *xdr, u32 *value)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
*value = be32_to_cpup(p);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static int decode_uint64(struct xdr_stream *xdr, u64 *value)
{
__be32 *p;
p = xdr_inline_decode(xdr, 8);
if (unlikely(p == NULL))
goto out_overflow;
xdr_decode_hyper(p, value);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* fileid3
*
* typedef uint64 fileid3;
*/
static __be32 *xdr_decode_fileid3(__be32 *p, u64 *fileid)
{
return xdr_decode_hyper(p, fileid);
}
static int decode_fileid3(struct xdr_stream *xdr, u64 *fileid)
{
return decode_uint64(xdr, fileid);
}
/*
* filename3
*
* typedef string filename3<>;
*/
static void encode_filename3(struct xdr_stream *xdr,
const char *name, u32 length)
{
__be32 *p;
WARN_ON_ONCE(length > NFS3_MAXNAMLEN);
p = xdr_reserve_space(xdr, 4 + length);
xdr_encode_opaque(p, name, length);
}
static int decode_inline_filename3(struct xdr_stream *xdr,
const char **name, u32 *length)
{
__be32 *p;
u32 count;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
count = be32_to_cpup(p);
if (count > NFS3_MAXNAMLEN)
goto out_nametoolong;
p = xdr_inline_decode(xdr, count);
if (unlikely(p == NULL))
goto out_overflow;
*name = (const char *)p;
*length = count;
return 0;
out_nametoolong:
dprintk("NFS: returned filename too long: %u\n", count);
return -ENAMETOOLONG;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* nfspath3
*
* typedef string nfspath3<>;
*/
static void encode_nfspath3(struct xdr_stream *xdr, struct page **pages,
const u32 length)
{
encode_uint32(xdr, length);
xdr_write_pages(xdr, pages, 0, length);
}
static int decode_nfspath3(struct xdr_stream *xdr)
{
u32 recvd, count;
__be32 *p;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
count = be32_to_cpup(p);
if (unlikely(count >= xdr->buf->page_len || count > NFS3_MAXPATHLEN))
goto out_nametoolong;
recvd = xdr_read_pages(xdr, count);
if (unlikely(count > recvd))
goto out_cheating;
xdr_terminate_string(xdr->buf, count);
return 0;
out_nametoolong:
dprintk("NFS: returned pathname too long: %u\n", count);
return -ENAMETOOLONG;
out_cheating:
dprintk("NFS: server cheating in pathname result: "
"count %u > recvd %u\n", count, recvd);
return -EIO;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* cookie3
*
* typedef uint64 cookie3
*/
static __be32 *xdr_encode_cookie3(__be32 *p, u64 cookie)
{
return xdr_encode_hyper(p, cookie);
}
static int decode_cookie3(struct xdr_stream *xdr, u64 *cookie)
{
return decode_uint64(xdr, cookie);
}
/*
* cookieverf3
*
* typedef opaque cookieverf3[NFS3_COOKIEVERFSIZE];
*/
static __be32 *xdr_encode_cookieverf3(__be32 *p, const __be32 *verifier)
{
memcpy(p, verifier, NFS3_COOKIEVERFSIZE);
return p + XDR_QUADLEN(NFS3_COOKIEVERFSIZE);
}
static int decode_cookieverf3(struct xdr_stream *xdr, __be32 *verifier)
{
__be32 *p;
p = xdr_inline_decode(xdr, NFS3_COOKIEVERFSIZE);
if (unlikely(p == NULL))
goto out_overflow;
memcpy(verifier, p, NFS3_COOKIEVERFSIZE);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* createverf3
*
* typedef opaque createverf3[NFS3_CREATEVERFSIZE];
*/
static void encode_createverf3(struct xdr_stream *xdr, const __be32 *verifier)
{
__be32 *p;
p = xdr_reserve_space(xdr, NFS3_CREATEVERFSIZE);
memcpy(p, verifier, NFS3_CREATEVERFSIZE);
}
static int decode_writeverf3(struct xdr_stream *xdr, struct nfs_write_verifier *verifier)
{
__be32 *p;
p = xdr_inline_decode(xdr, NFS3_WRITEVERFSIZE);
if (unlikely(p == NULL))
goto out_overflow;
memcpy(verifier->data, p, NFS3_WRITEVERFSIZE);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* size3
*
* typedef uint64 size3;
*/
static __be32 *xdr_decode_size3(__be32 *p, u64 *size)
{
return xdr_decode_hyper(p, size);
}
/*
* nfsstat3
*
* enum nfsstat3 {
* NFS3_OK = 0,
* ...
* }
*/
#define NFS3_OK NFS_OK
static int decode_nfsstat3(struct xdr_stream *xdr, enum nfs_stat *status)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
*status = be32_to_cpup(p);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* ftype3
*
* enum ftype3 {
* NF3REG = 1,
* NF3DIR = 2,
* NF3BLK = 3,
* NF3CHR = 4,
* NF3LNK = 5,
* NF3SOCK = 6,
* NF3FIFO = 7
* };
*/
static void encode_ftype3(struct xdr_stream *xdr, const u32 type)
{
encode_uint32(xdr, type);
}
static __be32 *xdr_decode_ftype3(__be32 *p, umode_t *mode)
{
u32 type;
type = be32_to_cpup(p++);
if (type > NF3FIFO)
type = NF3NON;
*mode = nfs_type2fmt[type];
return p;
}
/*
* specdata3
*
* struct specdata3 {
* uint32 specdata1;
* uint32 specdata2;
* };
*/
static void encode_specdata3(struct xdr_stream *xdr, const dev_t rdev)
{
__be32 *p;
p = xdr_reserve_space(xdr, 8);
*p++ = cpu_to_be32(MAJOR(rdev));
*p = cpu_to_be32(MINOR(rdev));
}
static __be32 *xdr_decode_specdata3(__be32 *p, dev_t *rdev)
{
unsigned int major, minor;
major = be32_to_cpup(p++);
minor = be32_to_cpup(p++);
*rdev = MKDEV(major, minor);
if (MAJOR(*rdev) != major || MINOR(*rdev) != minor)
*rdev = 0;
return p;
}
/*
* nfs_fh3
*
* struct nfs_fh3 {
* opaque data<NFS3_FHSIZE>;
* };
*/
static void encode_nfs_fh3(struct xdr_stream *xdr, const struct nfs_fh *fh)
{
__be32 *p;
WARN_ON_ONCE(fh->size > NFS3_FHSIZE);
p = xdr_reserve_space(xdr, 4 + fh->size);
xdr_encode_opaque(p, fh->data, fh->size);
}
static int decode_nfs_fh3(struct xdr_stream *xdr, struct nfs_fh *fh)
{
u32 length;
__be32 *p;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
length = be32_to_cpup(p++);
if (unlikely(length > NFS3_FHSIZE))
goto out_toobig;
p = xdr_inline_decode(xdr, length);
if (unlikely(p == NULL))
goto out_overflow;
fh->size = length;
memcpy(fh->data, p, length);
return 0;
out_toobig:
dprintk("NFS: file handle size (%u) too big\n", length);
return -E2BIG;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static void zero_nfs_fh3(struct nfs_fh *fh)
{
memset(fh, 0, sizeof(*fh));
}
/*
* nfstime3
*
* struct nfstime3 {
* uint32 seconds;
* uint32 nseconds;
* };
*/
static __be32 *xdr_encode_nfstime3(__be32 *p, const struct timespec *timep)
{
*p++ = cpu_to_be32(timep->tv_sec);
*p++ = cpu_to_be32(timep->tv_nsec);
return p;
}
static __be32 *xdr_decode_nfstime3(__be32 *p, struct timespec *timep)
{
timep->tv_sec = be32_to_cpup(p++);
timep->tv_nsec = be32_to_cpup(p++);
return p;
}
/*
* sattr3
*
* enum time_how {
* DONT_CHANGE = 0,
* SET_TO_SERVER_TIME = 1,
* SET_TO_CLIENT_TIME = 2
* };
*
* union set_mode3 switch (bool set_it) {
* case TRUE:
* mode3 mode;
* default:
* void;
* };
*
* union set_uid3 switch (bool set_it) {
* case TRUE:
* uid3 uid;
* default:
* void;
* };
*
* union set_gid3 switch (bool set_it) {
* case TRUE:
* gid3 gid;
* default:
* void;
* };
*
* union set_size3 switch (bool set_it) {
* case TRUE:
* size3 size;
* default:
* void;
* };
*
* union set_atime switch (time_how set_it) {
* case SET_TO_CLIENT_TIME:
* nfstime3 atime;
* default:
* void;
* };
*
* union set_mtime switch (time_how set_it) {
* case SET_TO_CLIENT_TIME:
* nfstime3 mtime;
* default:
* void;
* };
*
* struct sattr3 {
* set_mode3 mode;
* set_uid3 uid;
* set_gid3 gid;
* set_size3 size;
* set_atime atime;
* set_mtime mtime;
* };
*/
static void encode_sattr3(struct xdr_stream *xdr, const struct iattr *attr)
{
u32 nbytes;
__be32 *p;
/*
* In order to make only a single xdr_reserve_space() call,
* pre-compute the total number of bytes to be reserved.
* Six boolean values, one for each set_foo field, are always
* present in the encoded result, so start there.
*/
nbytes = 6 * 4;
if (attr->ia_valid & ATTR_MODE)
nbytes += 4;
if (attr->ia_valid & ATTR_UID)
nbytes += 4;
if (attr->ia_valid & ATTR_GID)
nbytes += 4;
if (attr->ia_valid & ATTR_SIZE)
nbytes += 8;
if (attr->ia_valid & ATTR_ATIME_SET)
nbytes += 8;
if (attr->ia_valid & ATTR_MTIME_SET)
nbytes += 8;
p = xdr_reserve_space(xdr, nbytes);
if (attr->ia_valid & ATTR_MODE) {
*p++ = xdr_one;
*p++ = cpu_to_be32(attr->ia_mode & S_IALLUGO);
} else
*p++ = xdr_zero;
if (attr->ia_valid & ATTR_UID) {
*p++ = xdr_one;
*p++ = cpu_to_be32(from_kuid(&init_user_ns, attr->ia_uid));
} else
*p++ = xdr_zero;
if (attr->ia_valid & ATTR_GID) {
*p++ = xdr_one;
*p++ = cpu_to_be32(from_kgid(&init_user_ns, attr->ia_gid));
} else
*p++ = xdr_zero;
if (attr->ia_valid & ATTR_SIZE) {
*p++ = xdr_one;
p = xdr_encode_hyper(p, (u64)attr->ia_size);
} else
*p++ = xdr_zero;
if (attr->ia_valid & ATTR_ATIME_SET) {
*p++ = xdr_two;
p = xdr_encode_nfstime3(p, &attr->ia_atime);
} else if (attr->ia_valid & ATTR_ATIME) {
*p++ = xdr_one;
} else
*p++ = xdr_zero;
if (attr->ia_valid & ATTR_MTIME_SET) {
*p++ = xdr_two;
xdr_encode_nfstime3(p, &attr->ia_mtime);
} else if (attr->ia_valid & ATTR_MTIME) {
*p = xdr_one;
} else
*p = xdr_zero;
}
/*
* fattr3
*
* struct fattr3 {
* ftype3 type;
* mode3 mode;
* uint32 nlink;
* uid3 uid;
* gid3 gid;
* size3 size;
* size3 used;
* specdata3 rdev;
* uint64 fsid;
* fileid3 fileid;
* nfstime3 atime;
* nfstime3 mtime;
* nfstime3 ctime;
* };
*/
static int decode_fattr3(struct xdr_stream *xdr, struct nfs_fattr *fattr)
{
umode_t fmode;
__be32 *p;
p = xdr_inline_decode(xdr, NFS3_fattr_sz << 2);
if (unlikely(p == NULL))
goto out_overflow;
p = xdr_decode_ftype3(p, &fmode);
fattr->mode = (be32_to_cpup(p++) & ~S_IFMT) | fmode;
fattr->nlink = be32_to_cpup(p++);
fattr->uid = make_kuid(&init_user_ns, be32_to_cpup(p++));
if (!uid_valid(fattr->uid))
goto out_uid;
fattr->gid = make_kgid(&init_user_ns, be32_to_cpup(p++));
if (!gid_valid(fattr->gid))
goto out_gid;
p = xdr_decode_size3(p, &fattr->size);
p = xdr_decode_size3(p, &fattr->du.nfs3.used);
p = xdr_decode_specdata3(p, &fattr->rdev);
p = xdr_decode_hyper(p, &fattr->fsid.major);
fattr->fsid.minor = 0;
p = xdr_decode_fileid3(p, &fattr->fileid);
p = xdr_decode_nfstime3(p, &fattr->atime);
p = xdr_decode_nfstime3(p, &fattr->mtime);
xdr_decode_nfstime3(p, &fattr->ctime);
fattr->change_attr = nfs_timespec_to_change_attr(&fattr->ctime);
fattr->valid |= NFS_ATTR_FATTR_V3;
return 0;
out_uid:
dprintk("NFS: returned invalid uid\n");
return -EINVAL;
out_gid:
dprintk("NFS: returned invalid gid\n");
return -EINVAL;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* post_op_attr
*
* union post_op_attr switch (bool attributes_follow) {
* case TRUE:
* fattr3 attributes;
* case FALSE:
* void;
* };
*/
static int decode_post_op_attr(struct xdr_stream *xdr, struct nfs_fattr *fattr)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
if (*p != xdr_zero)
return decode_fattr3(xdr, fattr);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* wcc_attr
* struct wcc_attr {
* size3 size;
* nfstime3 mtime;
* nfstime3 ctime;
* };
*/
static int decode_wcc_attr(struct xdr_stream *xdr, struct nfs_fattr *fattr)
{
__be32 *p;
p = xdr_inline_decode(xdr, NFS3_wcc_attr_sz << 2);
if (unlikely(p == NULL))
goto out_overflow;
fattr->valid |= NFS_ATTR_FATTR_PRESIZE
| NFS_ATTR_FATTR_PRECHANGE
| NFS_ATTR_FATTR_PREMTIME
| NFS_ATTR_FATTR_PRECTIME;
p = xdr_decode_size3(p, &fattr->pre_size);
p = xdr_decode_nfstime3(p, &fattr->pre_mtime);
xdr_decode_nfstime3(p, &fattr->pre_ctime);
fattr->pre_change_attr = nfs_timespec_to_change_attr(&fattr->pre_ctime);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* pre_op_attr
* union pre_op_attr switch (bool attributes_follow) {
* case TRUE:
* wcc_attr attributes;
* case FALSE:
* void;
* };
*
* wcc_data
*
* struct wcc_data {
* pre_op_attr before;
* post_op_attr after;
* };
*/
static int decode_pre_op_attr(struct xdr_stream *xdr, struct nfs_fattr *fattr)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
if (*p != xdr_zero)
return decode_wcc_attr(xdr, fattr);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static int decode_wcc_data(struct xdr_stream *xdr, struct nfs_fattr *fattr)
{
int error;
error = decode_pre_op_attr(xdr, fattr);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, fattr);
out:
return error;
}
/*
* post_op_fh3
*
* union post_op_fh3 switch (bool handle_follows) {
* case TRUE:
* nfs_fh3 handle;
* case FALSE:
* void;
* };
*/
static int decode_post_op_fh3(struct xdr_stream *xdr, struct nfs_fh *fh)
{
__be32 *p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
if (*p != xdr_zero)
return decode_nfs_fh3(xdr, fh);
zero_nfs_fh3(fh);
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
/*
* diropargs3
*
* struct diropargs3 {
* nfs_fh3 dir;
* filename3 name;
* };
*/
static void encode_diropargs3(struct xdr_stream *xdr, const struct nfs_fh *fh,
const char *name, u32 length)
{
encode_nfs_fh3(xdr, fh);
encode_filename3(xdr, name, length);
}
/*
* NFSv3 XDR encode functions
*
* NFSv3 argument types are defined in section 3.3 of RFC 1813:
* "NFS Version 3 Protocol Specification".
*/
/*
* 3.3.1 GETATTR3args
*
* struct GETATTR3args {
* nfs_fh3 object;
* };
*/
static void nfs3_xdr_enc_getattr3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs_fh *fh)
{
encode_nfs_fh3(xdr, fh);
}
/*
* 3.3.2 SETATTR3args
*
* union sattrguard3 switch (bool check) {
* case TRUE:
* nfstime3 obj_ctime;
* case FALSE:
* void;
* };
*
* struct SETATTR3args {
* nfs_fh3 object;
* sattr3 new_attributes;
* sattrguard3 guard;
* };
*/
static void encode_sattrguard3(struct xdr_stream *xdr,
const struct nfs3_sattrargs *args)
{
__be32 *p;
if (args->guard) {
p = xdr_reserve_space(xdr, 4 + 8);
*p++ = xdr_one;
xdr_encode_nfstime3(p, &args->guardtime);
} else {
p = xdr_reserve_space(xdr, 4);
*p = xdr_zero;
}
}
static void nfs3_xdr_enc_setattr3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_sattrargs *args)
{
encode_nfs_fh3(xdr, args->fh);
encode_sattr3(xdr, args->sattr);
encode_sattrguard3(xdr, args);
}
/*
* 3.3.3 LOOKUP3args
*
* struct LOOKUP3args {
* diropargs3 what;
* };
*/
static void nfs3_xdr_enc_lookup3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_diropargs *args)
{
encode_diropargs3(xdr, args->fh, args->name, args->len);
}
/*
* 3.3.4 ACCESS3args
*
* struct ACCESS3args {
* nfs_fh3 object;
* uint32 access;
* };
*/
static void encode_access3args(struct xdr_stream *xdr,
const struct nfs3_accessargs *args)
{
encode_nfs_fh3(xdr, args->fh);
encode_uint32(xdr, args->access);
}
static void nfs3_xdr_enc_access3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_accessargs *args)
{
encode_access3args(xdr, args);
}
/*
* 3.3.5 READLINK3args
*
* struct READLINK3args {
* nfs_fh3 symlink;
* };
*/
static void nfs3_xdr_enc_readlink3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_readlinkargs *args)
{
encode_nfs_fh3(xdr, args->fh);
prepare_reply_buffer(req, args->pages, args->pgbase,
args->pglen, NFS3_readlinkres_sz);
}
/*
* 3.3.6 READ3args
*
* struct READ3args {
* nfs_fh3 file;
* offset3 offset;
* count3 count;
* };
*/
static void encode_read3args(struct xdr_stream *xdr,
const struct nfs_pgio_args *args)
{
__be32 *p;
encode_nfs_fh3(xdr, args->fh);
p = xdr_reserve_space(xdr, 8 + 4);
p = xdr_encode_hyper(p, args->offset);
*p = cpu_to_be32(args->count);
}
static void nfs3_xdr_enc_read3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs_pgio_args *args)
{
encode_read3args(xdr, args);
prepare_reply_buffer(req, args->pages, args->pgbase,
args->count, NFS3_readres_sz);
req->rq_rcv_buf.flags |= XDRBUF_READ;
}
/*
* 3.3.7 WRITE3args
*
* enum stable_how {
* UNSTABLE = 0,
* DATA_SYNC = 1,
* FILE_SYNC = 2
* };
*
* struct WRITE3args {
* nfs_fh3 file;
* offset3 offset;
* count3 count;
* stable_how stable;
* opaque data<>;
* };
*/
static void encode_write3args(struct xdr_stream *xdr,
const struct nfs_pgio_args *args)
{
__be32 *p;
encode_nfs_fh3(xdr, args->fh);
p = xdr_reserve_space(xdr, 8 + 4 + 4 + 4);
p = xdr_encode_hyper(p, args->offset);
*p++ = cpu_to_be32(args->count);
*p++ = cpu_to_be32(args->stable);
*p = cpu_to_be32(args->count);
xdr_write_pages(xdr, args->pages, args->pgbase, args->count);
}
static void nfs3_xdr_enc_write3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs_pgio_args *args)
{
encode_write3args(xdr, args);
xdr->buf->flags |= XDRBUF_WRITE;
}
/*
* 3.3.8 CREATE3args
*
* enum createmode3 {
* UNCHECKED = 0,
* GUARDED = 1,
* EXCLUSIVE = 2
* };
*
* union createhow3 switch (createmode3 mode) {
* case UNCHECKED:
* case GUARDED:
* sattr3 obj_attributes;
* case EXCLUSIVE:
* createverf3 verf;
* };
*
* struct CREATE3args {
* diropargs3 where;
* createhow3 how;
* };
*/
static void encode_createhow3(struct xdr_stream *xdr,
const struct nfs3_createargs *args)
{
encode_uint32(xdr, args->createmode);
switch (args->createmode) {
case NFS3_CREATE_UNCHECKED:
case NFS3_CREATE_GUARDED:
encode_sattr3(xdr, args->sattr);
break;
case NFS3_CREATE_EXCLUSIVE:
encode_createverf3(xdr, args->verifier);
break;
default:
BUG();
}
}
static void nfs3_xdr_enc_create3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_createargs *args)
{
encode_diropargs3(xdr, args->fh, args->name, args->len);
encode_createhow3(xdr, args);
}
/*
* 3.3.9 MKDIR3args
*
* struct MKDIR3args {
* diropargs3 where;
* sattr3 attributes;
* };
*/
static void nfs3_xdr_enc_mkdir3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_mkdirargs *args)
{
encode_diropargs3(xdr, args->fh, args->name, args->len);
encode_sattr3(xdr, args->sattr);
}
/*
* 3.3.10 SYMLINK3args
*
* struct symlinkdata3 {
* sattr3 symlink_attributes;
* nfspath3 symlink_data;
* };
*
* struct SYMLINK3args {
* diropargs3 where;
* symlinkdata3 symlink;
* };
*/
static void encode_symlinkdata3(struct xdr_stream *xdr,
const struct nfs3_symlinkargs *args)
{
encode_sattr3(xdr, args->sattr);
encode_nfspath3(xdr, args->pages, args->pathlen);
}
static void nfs3_xdr_enc_symlink3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_symlinkargs *args)
{
encode_diropargs3(xdr, args->fromfh, args->fromname, args->fromlen);
encode_symlinkdata3(xdr, args);
xdr->buf->flags |= XDRBUF_WRITE;
}
/*
* 3.3.11 MKNOD3args
*
* struct devicedata3 {
* sattr3 dev_attributes;
* specdata3 spec;
* };
*
* union mknoddata3 switch (ftype3 type) {
* case NF3CHR:
* case NF3BLK:
* devicedata3 device;
* case NF3SOCK:
* case NF3FIFO:
* sattr3 pipe_attributes;
* default:
* void;
* };
*
* struct MKNOD3args {
* diropargs3 where;
* mknoddata3 what;
* };
*/
static void encode_devicedata3(struct xdr_stream *xdr,
const struct nfs3_mknodargs *args)
{
encode_sattr3(xdr, args->sattr);
encode_specdata3(xdr, args->rdev);
}
static void encode_mknoddata3(struct xdr_stream *xdr,
const struct nfs3_mknodargs *args)
{
encode_ftype3(xdr, args->type);
switch (args->type) {
case NF3CHR:
case NF3BLK:
encode_devicedata3(xdr, args);
break;
case NF3SOCK:
case NF3FIFO:
encode_sattr3(xdr, args->sattr);
break;
case NF3REG:
case NF3DIR:
break;
default:
BUG();
}
}
static void nfs3_xdr_enc_mknod3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_mknodargs *args)
{
encode_diropargs3(xdr, args->fh, args->name, args->len);
encode_mknoddata3(xdr, args);
}
/*
* 3.3.12 REMOVE3args
*
* struct REMOVE3args {
* diropargs3 object;
* };
*/
static void nfs3_xdr_enc_remove3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs_removeargs *args)
{
encode_diropargs3(xdr, args->fh, args->name.name, args->name.len);
}
/*
* 3.3.14 RENAME3args
*
* struct RENAME3args {
* diropargs3 from;
* diropargs3 to;
* };
*/
static void nfs3_xdr_enc_rename3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs_renameargs *args)
{
const struct qstr *old = args->old_name;
const struct qstr *new = args->new_name;
encode_diropargs3(xdr, args->old_dir, old->name, old->len);
encode_diropargs3(xdr, args->new_dir, new->name, new->len);
}
/*
* 3.3.15 LINK3args
*
* struct LINK3args {
* nfs_fh3 file;
* diropargs3 link;
* };
*/
static void nfs3_xdr_enc_link3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_linkargs *args)
{
encode_nfs_fh3(xdr, args->fromfh);
encode_diropargs3(xdr, args->tofh, args->toname, args->tolen);
}
/*
* 3.3.16 READDIR3args
*
* struct READDIR3args {
* nfs_fh3 dir;
* cookie3 cookie;
* cookieverf3 cookieverf;
* count3 count;
* };
*/
static void encode_readdir3args(struct xdr_stream *xdr,
const struct nfs3_readdirargs *args)
{
__be32 *p;
encode_nfs_fh3(xdr, args->fh);
p = xdr_reserve_space(xdr, 8 + NFS3_COOKIEVERFSIZE + 4);
p = xdr_encode_cookie3(p, args->cookie);
p = xdr_encode_cookieverf3(p, args->verf);
*p = cpu_to_be32(args->count);
}
static void nfs3_xdr_enc_readdir3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_readdirargs *args)
{
encode_readdir3args(xdr, args);
prepare_reply_buffer(req, args->pages, 0,
args->count, NFS3_readdirres_sz);
}
/*
* 3.3.17 READDIRPLUS3args
*
* struct READDIRPLUS3args {
* nfs_fh3 dir;
* cookie3 cookie;
* cookieverf3 cookieverf;
* count3 dircount;
* count3 maxcount;
* };
*/
static void encode_readdirplus3args(struct xdr_stream *xdr,
const struct nfs3_readdirargs *args)
{
__be32 *p;
encode_nfs_fh3(xdr, args->fh);
p = xdr_reserve_space(xdr, 8 + NFS3_COOKIEVERFSIZE + 4 + 4);
p = xdr_encode_cookie3(p, args->cookie);
p = xdr_encode_cookieverf3(p, args->verf);
/*
* readdirplus: need dircount + buffer size.
* We just make sure we make dircount big enough
*/
*p++ = cpu_to_be32(args->count >> 3);
*p = cpu_to_be32(args->count);
}
static void nfs3_xdr_enc_readdirplus3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_readdirargs *args)
{
encode_readdirplus3args(xdr, args);
prepare_reply_buffer(req, args->pages, 0,
args->count, NFS3_readdirres_sz);
}
/*
* 3.3.21 COMMIT3args
*
* struct COMMIT3args {
* nfs_fh3 file;
* offset3 offset;
* count3 count;
* };
*/
static void encode_commit3args(struct xdr_stream *xdr,
const struct nfs_commitargs *args)
{
__be32 *p;
encode_nfs_fh3(xdr, args->fh);
p = xdr_reserve_space(xdr, 8 + 4);
p = xdr_encode_hyper(p, args->offset);
*p = cpu_to_be32(args->count);
}
static void nfs3_xdr_enc_commit3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs_commitargs *args)
{
encode_commit3args(xdr, args);
}
#ifdef CONFIG_NFS_V3_ACL
static void nfs3_xdr_enc_getacl3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_getaclargs *args)
{
encode_nfs_fh3(xdr, args->fh);
encode_uint32(xdr, args->mask);
if (args->mask & (NFS_ACL | NFS_DFACL))
prepare_reply_buffer(req, args->pages, 0,
NFSACL_MAXPAGES << PAGE_SHIFT,
ACL3_getaclres_sz);
}
static void nfs3_xdr_enc_setacl3args(struct rpc_rqst *req,
struct xdr_stream *xdr,
const struct nfs3_setaclargs *args)
{
unsigned int base;
int error;
encode_nfs_fh3(xdr, NFS_FH(args->inode));
encode_uint32(xdr, args->mask);
base = req->rq_slen;
if (args->npages != 0)
xdr_write_pages(xdr, args->pages, 0, args->len);
else
xdr_reserve_space(xdr, args->len);
error = nfsacl_encode(xdr->buf, base, args->inode,
(args->mask & NFS_ACL) ?
args->acl_access : NULL, 1, 0);
/* FIXME: this is just broken */
BUG_ON(error < 0);
error = nfsacl_encode(xdr->buf, base + error, args->inode,
(args->mask & NFS_DFACL) ?
args->acl_default : NULL, 1,
NFS_ACL_DEFAULT);
BUG_ON(error < 0);
}
#endif /* CONFIG_NFS_V3_ACL */
/*
* NFSv3 XDR decode functions
*
* NFSv3 result types are defined in section 3.3 of RFC 1813:
* "NFS Version 3 Protocol Specification".
*/
/*
* 3.3.1 GETATTR3res
*
* struct GETATTR3resok {
* fattr3 obj_attributes;
* };
*
* union GETATTR3res switch (nfsstat3 status) {
* case NFS3_OK:
* GETATTR3resok resok;
* default:
* void;
* };
*/
static int nfs3_xdr_dec_getattr3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_fattr *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_fattr3(xdr, result);
out:
return error;
out_default:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.2 SETATTR3res
*
* struct SETATTR3resok {
* wcc_data obj_wcc;
* };
*
* struct SETATTR3resfail {
* wcc_data obj_wcc;
* };
*
* union SETATTR3res switch (nfsstat3 status) {
* case NFS3_OK:
* SETATTR3resok resok;
* default:
* SETATTR3resfail resfail;
* };
*/
static int nfs3_xdr_dec_setattr3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_fattr *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.3 LOOKUP3res
*
* struct LOOKUP3resok {
* nfs_fh3 object;
* post_op_attr obj_attributes;
* post_op_attr dir_attributes;
* };
*
* struct LOOKUP3resfail {
* post_op_attr dir_attributes;
* };
*
* union LOOKUP3res switch (nfsstat3 status) {
* case NFS3_OK:
* LOOKUP3resok resok;
* default:
* LOOKUP3resfail resfail;
* };
*/
static int nfs3_xdr_dec_lookup3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs3_diropres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_nfs_fh3(xdr, result->fh);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->dir_attr);
out:
return error;
out_default:
error = decode_post_op_attr(xdr, result->dir_attr);
if (unlikely(error))
goto out;
return nfs3_stat_to_errno(status);
}
/*
* 3.3.4 ACCESS3res
*
* struct ACCESS3resok {
* post_op_attr obj_attributes;
* uint32 access;
* };
*
* struct ACCESS3resfail {
* post_op_attr obj_attributes;
* };
*
* union ACCESS3res switch (nfsstat3 status) {
* case NFS3_OK:
* ACCESS3resok resok;
* default:
* ACCESS3resfail resfail;
* };
*/
static int nfs3_xdr_dec_access3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs3_accessres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_uint32(xdr, &result->access);
out:
return error;
out_default:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.5 READLINK3res
*
* struct READLINK3resok {
* post_op_attr symlink_attributes;
* nfspath3 data;
* };
*
* struct READLINK3resfail {
* post_op_attr symlink_attributes;
* };
*
* union READLINK3res switch (nfsstat3 status) {
* case NFS3_OK:
* READLINK3resok resok;
* default:
* READLINK3resfail resfail;
* };
*/
static int nfs3_xdr_dec_readlink3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_fattr *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_nfspath3(xdr);
out:
return error;
out_default:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.6 READ3res
*
* struct READ3resok {
* post_op_attr file_attributes;
* count3 count;
* bool eof;
* opaque data<>;
* };
*
* struct READ3resfail {
* post_op_attr file_attributes;
* };
*
* union READ3res switch (nfsstat3 status) {
* case NFS3_OK:
* READ3resok resok;
* default:
* READ3resfail resfail;
* };
*/
static int decode_read3resok(struct xdr_stream *xdr,
struct nfs_pgio_res *result)
{
u32 eof, count, ocount, recvd;
__be32 *p;
p = xdr_inline_decode(xdr, 4 + 4 + 4);
if (unlikely(p == NULL))
goto out_overflow;
count = be32_to_cpup(p++);
eof = be32_to_cpup(p++);
ocount = be32_to_cpup(p++);
if (unlikely(ocount != count))
goto out_mismatch;
recvd = xdr_read_pages(xdr, count);
if (unlikely(count > recvd))
goto out_cheating;
out:
result->eof = eof;
result->count = count;
return count;
out_mismatch:
dprintk("NFS: READ count doesn't match length of opaque: "
"count %u != ocount %u\n", count, ocount);
return -EIO;
out_cheating:
dprintk("NFS: server cheating in read result: "
"count %u > recvd %u\n", count, recvd);
count = recvd;
eof = 0;
goto out;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static int nfs3_xdr_dec_read3res(struct rpc_rqst *req, struct xdr_stream *xdr,
struct nfs_pgio_res *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
result->op_status = status;
if (status != NFS3_OK)
goto out_status;
error = decode_read3resok(xdr, result);
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.7 WRITE3res
*
* enum stable_how {
* UNSTABLE = 0,
* DATA_SYNC = 1,
* FILE_SYNC = 2
* };
*
* struct WRITE3resok {
* wcc_data file_wcc;
* count3 count;
* stable_how committed;
* writeverf3 verf;
* };
*
* struct WRITE3resfail {
* wcc_data file_wcc;
* };
*
* union WRITE3res switch (nfsstat3 status) {
* case NFS3_OK:
* WRITE3resok resok;
* default:
* WRITE3resfail resfail;
* };
*/
static int decode_write3resok(struct xdr_stream *xdr,
struct nfs_pgio_res *result)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4 + 4);
if (unlikely(p == NULL))
goto out_overflow;
result->count = be32_to_cpup(p++);
result->verf->committed = be32_to_cpup(p++);
if (unlikely(result->verf->committed > NFS_FILE_SYNC))
goto out_badvalue;
if (decode_writeverf3(xdr, &result->verf->verifier))
goto out_eio;
return result->count;
out_badvalue:
dprintk("NFS: bad stable_how value: %u\n", result->verf->committed);
return -EIO;
out_overflow:
print_overflow_msg(__func__, xdr);
out_eio:
return -EIO;
}
static int nfs3_xdr_dec_write3res(struct rpc_rqst *req, struct xdr_stream *xdr,
struct nfs_pgio_res *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result->fattr);
if (unlikely(error))
goto out;
result->op_status = status;
if (status != NFS3_OK)
goto out_status;
error = decode_write3resok(xdr, result);
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.8 CREATE3res
*
* struct CREATE3resok {
* post_op_fh3 obj;
* post_op_attr obj_attributes;
* wcc_data dir_wcc;
* };
*
* struct CREATE3resfail {
* wcc_data dir_wcc;
* };
*
* union CREATE3res switch (nfsstat3 status) {
* case NFS3_OK:
* CREATE3resok resok;
* default:
* CREATE3resfail resfail;
* };
*/
static int decode_create3resok(struct xdr_stream *xdr,
struct nfs3_diropres *result)
{
int error;
error = decode_post_op_fh3(xdr, result->fh);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
/* The server isn't required to return a file handle.
* If it didn't, force the client to perform a LOOKUP
* to determine the correct file handle and attribute
* values for the new object. */
if (result->fh->size == 0)
result->fattr->valid = 0;
error = decode_wcc_data(xdr, result->dir_attr);
out:
return error;
}
static int nfs3_xdr_dec_create3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs3_diropres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_create3resok(xdr, result);
out:
return error;
out_default:
error = decode_wcc_data(xdr, result->dir_attr);
if (unlikely(error))
goto out;
return nfs3_stat_to_errno(status);
}
/*
* 3.3.12 REMOVE3res
*
* struct REMOVE3resok {
* wcc_data dir_wcc;
* };
*
* struct REMOVE3resfail {
* wcc_data dir_wcc;
* };
*
* union REMOVE3res switch (nfsstat3 status) {
* case NFS3_OK:
* REMOVE3resok resok;
* default:
* REMOVE3resfail resfail;
* };
*/
static int nfs3_xdr_dec_remove3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_removeres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result->dir_attr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.14 RENAME3res
*
* struct RENAME3resok {
* wcc_data fromdir_wcc;
* wcc_data todir_wcc;
* };
*
* struct RENAME3resfail {
* wcc_data fromdir_wcc;
* wcc_data todir_wcc;
* };
*
* union RENAME3res switch (nfsstat3 status) {
* case NFS3_OK:
* RENAME3resok resok;
* default:
* RENAME3resfail resfail;
* };
*/
static int nfs3_xdr_dec_rename3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_renameres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result->old_fattr);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result->new_fattr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.15 LINK3res
*
* struct LINK3resok {
* post_op_attr file_attributes;
* wcc_data linkdir_wcc;
* };
*
* struct LINK3resfail {
* post_op_attr file_attributes;
* wcc_data linkdir_wcc;
* };
*
* union LINK3res switch (nfsstat3 status) {
* case NFS3_OK:
* LINK3resok resok;
* default:
* LINK3resfail resfail;
* };
*/
static int nfs3_xdr_dec_link3res(struct rpc_rqst *req, struct xdr_stream *xdr,
struct nfs3_linkres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result->dir_attr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/**
* nfs3_decode_dirent - Decode a single NFSv3 directory entry stored in
* the local page cache
* @xdr: XDR stream where entry resides
* @entry: buffer to fill in with entry data
* @plus: boolean indicating whether this should be a readdirplus entry
*
* Returns zero if successful, otherwise a negative errno value is
* returned.
*
* This function is not invoked during READDIR reply decoding, but
* rather whenever an application invokes the getdents(2) system call
* on a directory already in our cache.
*
* 3.3.16 entry3
*
* struct entry3 {
* fileid3 fileid;
* filename3 name;
* cookie3 cookie;
* fhandle3 filehandle;
* post_op_attr3 attributes;
* entry3 *nextentry;
* };
*
* 3.3.17 entryplus3
* struct entryplus3 {
* fileid3 fileid;
* filename3 name;
* cookie3 cookie;
* post_op_attr name_attributes;
* post_op_fh3 name_handle;
* entryplus3 *nextentry;
* };
*/
int nfs3_decode_dirent(struct xdr_stream *xdr, struct nfs_entry *entry,
int plus)
{
struct nfs_entry old = *entry;
__be32 *p;
int error;
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
if (*p == xdr_zero) {
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
if (*p == xdr_zero)
return -EAGAIN;
entry->eof = 1;
return -EBADCOOKIE;
}
error = decode_fileid3(xdr, &entry->ino);
if (unlikely(error))
return error;
error = decode_inline_filename3(xdr, &entry->name, &entry->len);
if (unlikely(error))
return error;
entry->prev_cookie = entry->cookie;
error = decode_cookie3(xdr, &entry->cookie);
if (unlikely(error))
return error;
entry->d_type = DT_UNKNOWN;
if (plus) {
entry->fattr->valid = 0;
error = decode_post_op_attr(xdr, entry->fattr);
if (unlikely(error))
return error;
if (entry->fattr->valid & NFS_ATTR_FATTR_V3)
entry->d_type = nfs_umode_to_dtype(entry->fattr->mode);
if (entry->fattr->fileid != entry->ino) {
entry->fattr->mounted_on_fileid = entry->ino;
entry->fattr->valid |= NFS_ATTR_FATTR_MOUNTED_ON_FILEID;
}
/* In fact, a post_op_fh3: */
p = xdr_inline_decode(xdr, 4);
if (unlikely(p == NULL))
goto out_overflow;
if (*p != xdr_zero) {
error = decode_nfs_fh3(xdr, entry->fh);
if (unlikely(error)) {
if (error == -E2BIG)
goto out_truncated;
return error;
}
} else
zero_nfs_fh3(entry->fh);
}
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EAGAIN;
out_truncated:
dprintk("NFS: directory entry contains invalid file handle\n");
*entry = old;
return -EAGAIN;
}
/*
* 3.3.16 READDIR3res
*
* struct dirlist3 {
* entry3 *entries;
* bool eof;
* };
*
* struct READDIR3resok {
* post_op_attr dir_attributes;
* cookieverf3 cookieverf;
* dirlist3 reply;
* };
*
* struct READDIR3resfail {
* post_op_attr dir_attributes;
* };
*
* union READDIR3res switch (nfsstat3 status) {
* case NFS3_OK:
* READDIR3resok resok;
* default:
* READDIR3resfail resfail;
* };
*
* Read the directory contents into the page cache, but otherwise
* don't touch them. The actual decoding is done by nfs3_decode_entry()
* during subsequent nfs_readdir() calls.
*/
static int decode_dirlist3(struct xdr_stream *xdr)
{
return xdr_read_pages(xdr, xdr->buf->page_len);
}
static int decode_readdir3resok(struct xdr_stream *xdr,
struct nfs3_readdirres *result)
{
int error;
error = decode_post_op_attr(xdr, result->dir_attr);
if (unlikely(error))
goto out;
/* XXX: do we need to check if result->verf != NULL ? */
error = decode_cookieverf3(xdr, result->verf);
if (unlikely(error))
goto out;
error = decode_dirlist3(xdr);
out:
return error;
}
static int nfs3_xdr_dec_readdir3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs3_readdirres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_readdir3resok(xdr, result);
out:
return error;
out_default:
error = decode_post_op_attr(xdr, result->dir_attr);
if (unlikely(error))
goto out;
return nfs3_stat_to_errno(status);
}
/*
* 3.3.18 FSSTAT3res
*
* struct FSSTAT3resok {
* post_op_attr obj_attributes;
* size3 tbytes;
* size3 fbytes;
* size3 abytes;
* size3 tfiles;
* size3 ffiles;
* size3 afiles;
* uint32 invarsec;
* };
*
* struct FSSTAT3resfail {
* post_op_attr obj_attributes;
* };
*
* union FSSTAT3res switch (nfsstat3 status) {
* case NFS3_OK:
* FSSTAT3resok resok;
* default:
* FSSTAT3resfail resfail;
* };
*/
static int decode_fsstat3resok(struct xdr_stream *xdr,
struct nfs_fsstat *result)
{
__be32 *p;
p = xdr_inline_decode(xdr, 8 * 6 + 4);
if (unlikely(p == NULL))
goto out_overflow;
p = xdr_decode_size3(p, &result->tbytes);
p = xdr_decode_size3(p, &result->fbytes);
p = xdr_decode_size3(p, &result->abytes);
p = xdr_decode_size3(p, &result->tfiles);
p = xdr_decode_size3(p, &result->ffiles);
xdr_decode_size3(p, &result->afiles);
/* ignore invarsec */
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static int nfs3_xdr_dec_fsstat3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_fsstat *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
error = decode_fsstat3resok(xdr, result);
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.19 FSINFO3res
*
* struct FSINFO3resok {
* post_op_attr obj_attributes;
* uint32 rtmax;
* uint32 rtpref;
* uint32 rtmult;
* uint32 wtmax;
* uint32 wtpref;
* uint32 wtmult;
* uint32 dtpref;
* size3 maxfilesize;
* nfstime3 time_delta;
* uint32 properties;
* };
*
* struct FSINFO3resfail {
* post_op_attr obj_attributes;
* };
*
* union FSINFO3res switch (nfsstat3 status) {
* case NFS3_OK:
* FSINFO3resok resok;
* default:
* FSINFO3resfail resfail;
* };
*/
static int decode_fsinfo3resok(struct xdr_stream *xdr,
struct nfs_fsinfo *result)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4 * 7 + 8 + 8 + 4);
if (unlikely(p == NULL))
goto out_overflow;
result->rtmax = be32_to_cpup(p++);
result->rtpref = be32_to_cpup(p++);
result->rtmult = be32_to_cpup(p++);
result->wtmax = be32_to_cpup(p++);
result->wtpref = be32_to_cpup(p++);
result->wtmult = be32_to_cpup(p++);
result->dtpref = be32_to_cpup(p++);
p = xdr_decode_size3(p, &result->maxfilesize);
xdr_decode_nfstime3(p, &result->time_delta);
/* ignore properties */
result->lease_time = 0;
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static int nfs3_xdr_dec_fsinfo3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_fsinfo *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
error = decode_fsinfo3resok(xdr, result);
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.20 PATHCONF3res
*
* struct PATHCONF3resok {
* post_op_attr obj_attributes;
* uint32 linkmax;
* uint32 name_max;
* bool no_trunc;
* bool chown_restricted;
* bool case_insensitive;
* bool case_preserving;
* };
*
* struct PATHCONF3resfail {
* post_op_attr obj_attributes;
* };
*
* union PATHCONF3res switch (nfsstat3 status) {
* case NFS3_OK:
* PATHCONF3resok resok;
* default:
* PATHCONF3resfail resfail;
* };
*/
static int decode_pathconf3resok(struct xdr_stream *xdr,
struct nfs_pathconf *result)
{
__be32 *p;
p = xdr_inline_decode(xdr, 4 * 6);
if (unlikely(p == NULL))
goto out_overflow;
result->max_link = be32_to_cpup(p++);
result->max_namelen = be32_to_cpup(p);
/* ignore remaining fields */
return 0;
out_overflow:
print_overflow_msg(__func__, xdr);
return -EIO;
}
static int nfs3_xdr_dec_pathconf3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_pathconf *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_status;
error = decode_pathconf3resok(xdr, result);
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
/*
* 3.3.21 COMMIT3res
*
* struct COMMIT3resok {
* wcc_data file_wcc;
* writeverf3 verf;
* };
*
* struct COMMIT3resfail {
* wcc_data file_wcc;
* };
*
* union COMMIT3res switch (nfsstat3 status) {
* case NFS3_OK:
* COMMIT3resok resok;
* default:
* COMMIT3resfail resfail;
* };
*/
static int nfs3_xdr_dec_commit3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_commitres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
error = decode_wcc_data(xdr, result->fattr);
if (unlikely(error))
goto out;
result->op_status = status;
if (status != NFS3_OK)
goto out_status;
error = decode_writeverf3(xdr, &result->verf->verifier);
out:
return error;
out_status:
return nfs3_stat_to_errno(status);
}
#ifdef CONFIG_NFS_V3_ACL
static inline int decode_getacl3resok(struct xdr_stream *xdr,
struct nfs3_getaclres *result)
{
struct posix_acl **acl;
unsigned int *aclcnt;
size_t hdrlen;
int error;
error = decode_post_op_attr(xdr, result->fattr);
if (unlikely(error))
goto out;
error = decode_uint32(xdr, &result->mask);
if (unlikely(error))
goto out;
error = -EINVAL;
if (result->mask & ~(NFS_ACL|NFS_ACLCNT|NFS_DFACL|NFS_DFACLCNT))
goto out;
hdrlen = xdr_stream_pos(xdr);
acl = NULL;
if (result->mask & NFS_ACL)
acl = &result->acl_access;
aclcnt = NULL;
if (result->mask & NFS_ACLCNT)
aclcnt = &result->acl_access_count;
error = nfsacl_decode(xdr->buf, hdrlen, aclcnt, acl);
if (unlikely(error <= 0))
goto out;
acl = NULL;
if (result->mask & NFS_DFACL)
acl = &result->acl_default;
aclcnt = NULL;
if (result->mask & NFS_DFACLCNT)
aclcnt = &result->acl_default_count;
error = nfsacl_decode(xdr->buf, hdrlen + error, aclcnt, acl);
if (unlikely(error <= 0))
return error;
error = 0;
out:
return error;
}
static int nfs3_xdr_dec_getacl3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs3_getaclres *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_getacl3resok(xdr, result);
out:
return error;
out_default:
return nfs3_stat_to_errno(status);
}
static int nfs3_xdr_dec_setacl3res(struct rpc_rqst *req,
struct xdr_stream *xdr,
struct nfs_fattr *result)
{
enum nfs_stat status;
int error;
error = decode_nfsstat3(xdr, &status);
if (unlikely(error))
goto out;
if (status != NFS3_OK)
goto out_default;
error = decode_post_op_attr(xdr, result);
out:
return error;
out_default:
return nfs3_stat_to_errno(status);
}
#endif /* CONFIG_NFS_V3_ACL */
/*
* We need to translate between nfs status return values and
* the local errno values which may not be the same.
*/
static const struct {
int stat;
int errno;
} nfs_errtbl[] = {
{ NFS_OK, 0 },
{ NFSERR_PERM, -EPERM },
{ NFSERR_NOENT, -ENOENT },
{ NFSERR_IO, -errno_NFSERR_IO},
{ NFSERR_NXIO, -ENXIO },
/* { NFSERR_EAGAIN, -EAGAIN }, */
{ NFSERR_ACCES, -EACCES },
{ NFSERR_EXIST, -EEXIST },
{ NFSERR_XDEV, -EXDEV },
{ NFSERR_NODEV, -ENODEV },
{ NFSERR_NOTDIR, -ENOTDIR },
{ NFSERR_ISDIR, -EISDIR },
{ NFSERR_INVAL, -EINVAL },
{ NFSERR_FBIG, -EFBIG },
{ NFSERR_NOSPC, -ENOSPC },
{ NFSERR_ROFS, -EROFS },
{ NFSERR_MLINK, -EMLINK },
{ NFSERR_NAMETOOLONG, -ENAMETOOLONG },
{ NFSERR_NOTEMPTY, -ENOTEMPTY },
{ NFSERR_DQUOT, -EDQUOT },
{ NFSERR_STALE, -ESTALE },
{ NFSERR_REMOTE, -EREMOTE },
#ifdef EWFLUSH
{ NFSERR_WFLUSH, -EWFLUSH },
#endif
{ NFSERR_BADHANDLE, -EBADHANDLE },
{ NFSERR_NOT_SYNC, -ENOTSYNC },
{ NFSERR_BAD_COOKIE, -EBADCOOKIE },
{ NFSERR_NOTSUPP, -ENOTSUPP },
{ NFSERR_TOOSMALL, -ETOOSMALL },
{ NFSERR_SERVERFAULT, -EREMOTEIO },
{ NFSERR_BADTYPE, -EBADTYPE },
{ NFSERR_JUKEBOX, -EJUKEBOX },
{ -1, -EIO }
};
/**
* nfs3_stat_to_errno - convert an NFS status code to a local errno
* @status: NFS status code to convert
*
* Returns a local errno value, or -EIO if the NFS status code is
* not recognized. This function is used jointly by NFSv2 and NFSv3.
*/
static int nfs3_stat_to_errno(enum nfs_stat status)
{
int i;
for (i = 0; nfs_errtbl[i].stat != -1; i++) {
if (nfs_errtbl[i].stat == (int)status)
return nfs_errtbl[i].errno;
}
dprintk("NFS: Unrecognized nfs status value: %u\n", status);
return nfs_errtbl[i].errno;
}
#define PROC(proc, argtype, restype, timer) \
[NFS3PROC_##proc] = { \
.p_proc = NFS3PROC_##proc, \
.p_encode = (kxdreproc_t)nfs3_xdr_enc_##argtype##3args, \
.p_decode = (kxdrdproc_t)nfs3_xdr_dec_##restype##3res, \
.p_arglen = NFS3_##argtype##args_sz, \
.p_replen = NFS3_##restype##res_sz, \
.p_timer = timer, \
.p_statidx = NFS3PROC_##proc, \
.p_name = #proc, \
}
struct rpc_procinfo nfs3_procedures[] = {
PROC(GETATTR, getattr, getattr, 1),
PROC(SETATTR, setattr, setattr, 0),
PROC(LOOKUP, lookup, lookup, 2),
PROC(ACCESS, access, access, 1),
PROC(READLINK, readlink, readlink, 3),
PROC(READ, read, read, 3),
PROC(WRITE, write, write, 4),
PROC(CREATE, create, create, 0),
PROC(MKDIR, mkdir, create, 0),
PROC(SYMLINK, symlink, create, 0),
PROC(MKNOD, mknod, create, 0),
PROC(REMOVE, remove, remove, 0),
PROC(RMDIR, lookup, setattr, 0),
PROC(RENAME, rename, rename, 0),
PROC(LINK, link, link, 0),
PROC(READDIR, readdir, readdir, 3),
PROC(READDIRPLUS, readdirplus, readdir, 3),
PROC(FSSTAT, getattr, fsstat, 0),
PROC(FSINFO, getattr, fsinfo, 0),
PROC(PATHCONF, getattr, pathconf, 0),
PROC(COMMIT, commit, commit, 5),
};
const struct rpc_version nfs_version3 = {
.number = 3,
.nrprocs = ARRAY_SIZE(nfs3_procedures),
.procs = nfs3_procedures
};
#ifdef CONFIG_NFS_V3_ACL
static struct rpc_procinfo nfs3_acl_procedures[] = {
[ACLPROC3_GETACL] = {
.p_proc = ACLPROC3_GETACL,
.p_encode = (kxdreproc_t)nfs3_xdr_enc_getacl3args,
.p_decode = (kxdrdproc_t)nfs3_xdr_dec_getacl3res,
.p_arglen = ACL3_getaclargs_sz,
.p_replen = ACL3_getaclres_sz,
.p_timer = 1,
.p_name = "GETACL",
},
[ACLPROC3_SETACL] = {
.p_proc = ACLPROC3_SETACL,
.p_encode = (kxdreproc_t)nfs3_xdr_enc_setacl3args,
.p_decode = (kxdrdproc_t)nfs3_xdr_dec_setacl3res,
.p_arglen = ACL3_setaclargs_sz,
.p_replen = ACL3_setaclres_sz,
.p_timer = 0,
.p_name = "SETACL",
},
};
const struct rpc_version nfsacl_version3 = {
.number = 3,
.nrprocs = sizeof(nfs3_acl_procedures)/
sizeof(nfs3_acl_procedures[0]),
.procs = nfs3_acl_procedures,
};
#endif /* CONFIG_NFS_V3_ACL */
| gpl-2.0 |
y10g/lge-kernel-startablet-l06c | arch/mips/pmc-sierra/yosemite/smp.c | 1198 | 4300 | #include <linux/linkage.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <asm/pmon.h>
#include <asm/titan_dep.h>
#include <asm/time.h>
#define LAUNCHSTACK_SIZE 256
static __cpuinitdata arch_spinlock_t launch_lock = __ARCH_SPIN_LOCK_UNLOCKED;
static unsigned long secondary_sp __cpuinitdata;
static unsigned long secondary_gp __cpuinitdata;
static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
__attribute__((aligned(2 * sizeof(long))));
static void __init prom_smp_bootstrap(void)
{
local_irq_disable();
while (arch_spin_is_locked(&launch_lock));
__asm__ __volatile__(
" move $sp, %0 \n"
" move $gp, %1 \n"
" j smp_bootstrap \n"
:
: "r" (secondary_sp), "r" (secondary_gp));
}
/*
* PMON is a fragile beast. It'll blow up once the mappings it's littering
* right into the middle of KSEG3 are blown away so we have to grab the slave
* core early and keep it in a waiting loop.
*/
void __init prom_grab_secondary(void)
{
arch_spin_lock(&launch_lock);
pmon_cpustart(1, &prom_smp_bootstrap,
launchstack + LAUNCHSTACK_SIZE, 0);
}
void titan_mailbox_irq(void)
{
int cpu = smp_processor_id();
unsigned long status;
switch (cpu) {
case 0:
status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
if (status & 0x2)
smp_call_function_interrupt();
break;
case 1:
status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
if (status & 0x2)
smp_call_function_interrupt();
break;
}
}
/*
* Send inter-processor interrupt
*/
static void yos_send_ipi_single(int cpu, unsigned int action)
{
/*
* Generate an INTMSG so that it can be sent over to the
* destination CPU. The INTMSG will put the STATUS bits
* based on the action desired. An alternative strategy
* is to write to the Interrupt Set register, read the
* Interrupt Status register and clear the Interrupt
* Clear register. The latter is preffered.
*/
switch (action) {
case SMP_RESCHEDULE_YOURSELF:
if (cpu == 1)
OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
else
OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
break;
case SMP_CALL_FUNCTION:
if (cpu == 1)
OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
else
OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
break;
}
}
static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
{
unsigned int i;
for_each_cpu(i, mask)
yos_send_ipi_single(i, action);
}
/*
* After we've done initial boot, this function is called to allow the
* board code to clean up state, if needed
*/
static void __cpuinit yos_init_secondary(void)
{
set_c0_status(ST0_CO | ST0_IE | ST0_IM);
}
static void __cpuinit yos_smp_finish(void)
{
}
/* Hook for after all CPUs are online */
static void yos_cpus_done(void)
{
}
/*
* Firmware CPU startup hook
* Complicated by PMON's weird interface which tries to minimic the UNIX fork.
* It launches the next * available CPU and copies some information on the
* stack so the first thing we do is throw away that stuff and load useful
* values into the registers ...
*/
static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
{
unsigned long gp = (unsigned long) task_thread_info(idle);
unsigned long sp = __KSTK_TOS(idle);
secondary_sp = sp;
secondary_gp = gp;
arch_spin_unlock(&launch_lock);
}
/*
* Detect available CPUs, populate cpu_possible_map before smp_init
*
* We don't want to start the secondary CPU yet nor do we have a nice probing
* feature in PMON so we just assume presence of the secondary core.
*/
static void __init yos_smp_setup(void)
{
int i;
cpus_clear(cpu_possible_map);
for (i = 0; i < 2; i++) {
cpu_set(i, cpu_possible_map);
__cpu_number_map[i] = i;
__cpu_logical_map[i] = i;
}
}
static void __init yos_prepare_cpus(unsigned int max_cpus)
{
/*
* Be paranoid. Enable the IPI only if we're really about to go SMP.
*/
if (cpus_weight(cpu_possible_map))
set_c0_status(STATUSF_IP5);
}
struct plat_smp_ops yos_smp_ops = {
.send_ipi_single = yos_send_ipi_single,
.send_ipi_mask = yos_send_ipi_mask,
.init_secondary = yos_init_secondary,
.smp_finish = yos_smp_finish,
.cpus_done = yos_cpus_done,
.boot_secondary = yos_boot_secondary,
.smp_setup = yos_smp_setup,
.prepare_cpus = yos_prepare_cpus,
};
| gpl-2.0 |
BruceBushby/linux-4.1 | drivers/mtd/maps/sc520cdp.c | 1710 | 9149 | /* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform
*
* Copyright (C) 2001 Sysgo Real-Time Solutions GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
*
* The SC520CDP is an evaluation board for the Elan SC520 processor available
* from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
* and up to 512 KiB of 8-bit DIL Flash ROM.
* For details see http://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/concat.h>
/*
** The Embedded Systems BIOS decodes the first FLASH starting at
** 0x8400000. This is a *terrible* place for it because accessing
** the flash at this location causes the A22 address line to be high
** (that's what 0x8400000 binary's ought to be). But this is the highest
** order address line on the raw flash devices themselves!!
** This causes the top HALF of the flash to be accessed first. Beyond
** the physical limits of the flash, the flash chip aliases over (to
** 0x880000 which causes the bottom half to be accessed. This splits the
** flash into two and inverts it! If you then try to access this from another
** program that does NOT do this insanity, then you *will* access the
** first half of the flash, but not find what you expect there. That
** stuff is in the *second* half! Similarly, the address used by the
** BIOS for the second FLASH bank is also quite a bad choice.
** If REPROGRAM_PAR is defined below (the default), then this driver will
** choose more useful addresses for the FLASH banks by reprogramming the
** responsible PARxx registers in the SC520's MMCR region. This will
** cause the settings to be incompatible with the BIOS's settings, which
** shouldn't be a problem since you are running Linux, (i.e. the BIOS is
** not much use anyway). However, if you need to be compatible with
** the BIOS for some reason, just undefine REPROGRAM_PAR.
*/
#define REPROGRAM_PAR
#ifdef REPROGRAM_PAR
/* These are the addresses we want.. */
#define WINDOW_ADDR_0 0x08800000
#define WINDOW_ADDR_1 0x09000000
#define WINDOW_ADDR_2 0x09800000
/* .. and these are the addresses the BIOS gives us */
#define WINDOW_ADDR_0_BIOS 0x08400000
#define WINDOW_ADDR_1_BIOS 0x08c00000
#define WINDOW_ADDR_2_BIOS 0x09400000
#else
#define WINDOW_ADDR_0 0x08400000
#define WINDOW_ADDR_1 0x08C00000
#define WINDOW_ADDR_2 0x09400000
#endif
#define WINDOW_SIZE_0 0x00800000
#define WINDOW_SIZE_1 0x00800000
#define WINDOW_SIZE_2 0x00080000
static struct map_info sc520cdp_map[] = {
{
.name = "SC520CDP Flash Bank #0",
.size = WINDOW_SIZE_0,
.bankwidth = 4,
.phys = WINDOW_ADDR_0
},
{
.name = "SC520CDP Flash Bank #1",
.size = WINDOW_SIZE_1,
.bankwidth = 4,
.phys = WINDOW_ADDR_1
},
{
.name = "SC520CDP DIL Flash",
.size = WINDOW_SIZE_2,
.bankwidth = 1,
.phys = WINDOW_ADDR_2
},
};
#define NUM_FLASH_BANKS ARRAY_SIZE(sc520cdp_map)
static struct mtd_info *mymtd[NUM_FLASH_BANKS];
static struct mtd_info *merged_mtd;
#ifdef REPROGRAM_PAR
/*
** The SC520 MMCR (memory mapped control register) region resides
** at 0xFFFEF000. The 16 Programmable Address Region (PAR) registers
** are at offset 0x88 in the MMCR:
*/
#define SC520_MMCR_BASE 0xFFFEF000
#define SC520_MMCR_EXTENT 0x1000
#define SC520_PAR(x) ((0x88/sizeof(unsigned long)) + (x))
#define NUM_SC520_PAR 16 /* total number of PAR registers */
/*
** The highest three bits in a PAR register determine what target
** device is controlled by this PAR. Here, only ROMCS? and BOOTCS
** devices are of interest.
*/
#define SC520_PAR_BOOTCS (0x4<<29)
#define SC520_PAR_ROMCS0 (0x5<<29)
#define SC520_PAR_ROMCS1 (0x6<<29)
#define SC520_PAR_TRGDEV (0x7<<29)
/*
** Bits 28 thru 26 determine some attributes for the
** region controlled by the PAR. (We only use non-cacheable)
*/
#define SC520_PAR_WRPROT (1<<26) /* write protected */
#define SC520_PAR_NOCACHE (1<<27) /* non-cacheable */
#define SC520_PAR_NOEXEC (1<<28) /* code execution denied */
/*
** Bit 25 determines the granularity: 4K or 64K
*/
#define SC520_PAR_PG_SIZ4 (0<<25)
#define SC520_PAR_PG_SIZ64 (1<<25)
/*
** Build a value to be written into a PAR register.
** We only need ROM entries, 64K page size:
*/
#define SC520_PAR_ENTRY(trgdev, address, size) \
((trgdev) | SC520_PAR_NOCACHE | SC520_PAR_PG_SIZ64 | \
(address) >> 16 | (((size) >> 16) - 1) << 14)
struct sc520_par_table
{
unsigned long trgdev;
unsigned long new_par;
unsigned long default_address;
};
static const struct sc520_par_table par_table[NUM_FLASH_BANKS] =
{
{ /* Flash Bank #0: selected by ROMCS0 */
SC520_PAR_ROMCS0,
SC520_PAR_ENTRY(SC520_PAR_ROMCS0, WINDOW_ADDR_0, WINDOW_SIZE_0),
WINDOW_ADDR_0_BIOS
},
{ /* Flash Bank #1: selected by ROMCS1 */
SC520_PAR_ROMCS1,
SC520_PAR_ENTRY(SC520_PAR_ROMCS1, WINDOW_ADDR_1, WINDOW_SIZE_1),
WINDOW_ADDR_1_BIOS
},
{ /* DIL (BIOS) Flash: selected by BOOTCS */
SC520_PAR_BOOTCS,
SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2),
WINDOW_ADDR_2_BIOS
}
};
static void sc520cdp_setup_par(void)
{
unsigned long __iomem *mmcr;
unsigned long mmcr_val;
int i, j;
/* map in SC520's MMCR area */
mmcr = ioremap_nocache(SC520_MMCR_BASE, SC520_MMCR_EXTENT);
if(!mmcr) { /* ioremap_nocache failed: skip the PAR reprogramming */
/* force physical address fields to BIOS defaults: */
for(i = 0; i < NUM_FLASH_BANKS; i++)
sc520cdp_map[i].phys = par_table[i].default_address;
return;
}
/*
** Find the PARxx registers that are responsible for activating
** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a
** new value from the table.
*/
for(i = 0; i < NUM_FLASH_BANKS; i++) { /* for each par_table entry */
for(j = 0; j < NUM_SC520_PAR; j++) { /* for each PAR register */
mmcr_val = readl(&mmcr[SC520_PAR(j)]);
/* if target device field matches, reprogram the PAR */
if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev)
{
writel(par_table[i].new_par, &mmcr[SC520_PAR(j)]);
break;
}
}
if(j == NUM_SC520_PAR)
{ /* no matching PAR found: try default BIOS address */
printk(KERN_NOTICE "Could not find PAR responsible for %s\n",
sc520cdp_map[i].name);
printk(KERN_NOTICE "Trying default address 0x%lx\n",
par_table[i].default_address);
sc520cdp_map[i].phys = par_table[i].default_address;
}
}
iounmap(mmcr);
}
#endif
static int __init init_sc520cdp(void)
{
int i, devices_found = 0;
#ifdef REPROGRAM_PAR
/* reprogram PAR registers so flash appears at the desired addresses */
sc520cdp_setup_par();
#endif
for (i = 0; i < NUM_FLASH_BANKS; i++) {
printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",
(unsigned long long)sc520cdp_map[i].size,
(unsigned long long)sc520cdp_map[i].phys);
sc520cdp_map[i].virt = ioremap_nocache(sc520cdp_map[i].phys, sc520cdp_map[i].size);
if (!sc520cdp_map[i].virt) {
printk("Failed to ioremap_nocache\n");
return -EIO;
}
simple_map_init(&sc520cdp_map[i]);
mymtd[i] = do_map_probe("cfi_probe", &sc520cdp_map[i]);
if(!mymtd[i])
mymtd[i] = do_map_probe("jedec_probe", &sc520cdp_map[i]);
if(!mymtd[i])
mymtd[i] = do_map_probe("map_rom", &sc520cdp_map[i]);
if (mymtd[i]) {
mymtd[i]->owner = THIS_MODULE;
++devices_found;
}
else {
iounmap(sc520cdp_map[i].virt);
}
}
if(devices_found >= 2) {
/* Combine the two flash banks into a single MTD device & register it: */
merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");
if(merged_mtd)
mtd_device_register(merged_mtd, NULL, 0);
}
if(devices_found == 3) /* register the third (DIL-Flash) device */
mtd_device_register(mymtd[2], NULL, 0);
return(devices_found ? 0 : -ENXIO);
}
static void __exit cleanup_sc520cdp(void)
{
int i;
if (merged_mtd) {
mtd_device_unregister(merged_mtd);
mtd_concat_destroy(merged_mtd);
}
if (mymtd[2])
mtd_device_unregister(mymtd[2]);
for (i = 0; i < NUM_FLASH_BANKS; i++) {
if (mymtd[i])
map_destroy(mymtd[i]);
if (sc520cdp_map[i].virt) {
iounmap(sc520cdp_map[i].virt);
sc520cdp_map[i].virt = NULL;
}
}
}
module_init(init_sc520cdp);
module_exit(cleanup_sc520cdp);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
MODULE_DESCRIPTION("MTD map driver for AMD SC520 Customer Development Platform");
| gpl-2.0 |
nik124seleznev/ZC500TG | drivers/video/fbdev/aty/radeon_backlight.c | 1966 | 6117 | /*
* Backlight code for ATI Radeon based graphic cards
*
* Copyright (c) 2000 Ani Joshi <ajoshi@kernel.crashing.org>
* Copyright (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Copyright (c) 2006 Michael Hanselmann <linux-kernel@hansmi.ch>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "radeonfb.h"
#include <linux/backlight.h>
#include <linux/slab.h>
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#define MAX_RADEON_LEVEL 0xFF
struct radeon_bl_privdata {
struct radeonfb_info *rinfo;
uint8_t negative;
};
static int radeon_bl_get_level_brightness(struct radeon_bl_privdata *pdata,
int level)
{
int rlevel;
/* Get and convert the value */
/* No locking of bl_curve since we read a single value */
rlevel = pdata->rinfo->info->bl_curve[level] *
FB_BACKLIGHT_MAX / MAX_RADEON_LEVEL;
if (rlevel < 0)
rlevel = 0;
else if (rlevel > MAX_RADEON_LEVEL)
rlevel = MAX_RADEON_LEVEL;
if (pdata->negative)
rlevel = MAX_RADEON_LEVEL - rlevel;
return rlevel;
}
static int radeon_bl_update_status(struct backlight_device *bd)
{
struct radeon_bl_privdata *pdata = bl_get_data(bd);
struct radeonfb_info *rinfo = pdata->rinfo;
u32 lvds_gen_cntl, tmpPixclksCntl;
int level;
if (rinfo->mon1_type != MT_LCD)
return 0;
/* We turn off the LCD completely instead of just dimming the
* backlight. This provides some greater power saving and the display
* is useless without backlight anyway.
*/
if (bd->props.power != FB_BLANK_UNBLANK ||
bd->props.fb_blank != FB_BLANK_UNBLANK)
level = 0;
else
level = bd->props.brightness;
del_timer_sync(&rinfo->lvds_timer);
radeon_engine_idle();
lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
if (level > 0) {
lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
lvds_gen_cntl |=
(radeon_bl_get_level_brightness(pdata, level) <<
LVDS_BL_MOD_LEVEL_SHIFT);
lvds_gen_cntl |= LVDS_ON;
lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
mod_timer(&rinfo->lvds_timer,
jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
} else {
lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
lvds_gen_cntl |=
(radeon_bl_get_level_brightness(pdata, level) <<
LVDS_BL_MOD_LEVEL_SHIFT);
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
}
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
& LVDS_STATE_MASK;
} else {
/* Asic bug, when turning off LVDS_ON, we have to make sure
RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
*/
tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
if (rinfo->is_mobility || rinfo->is_IGP)
OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
lvds_gen_cntl |= (radeon_bl_get_level_brightness(pdata, 0) <<
LVDS_BL_MOD_LEVEL_SHIFT);
lvds_gen_cntl |= LVDS_DISPLAY_DIS;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
udelay(100);
lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
lvds_gen_cntl &= ~(LVDS_DIGON);
rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
mod_timer(&rinfo->lvds_timer,
jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
if (rinfo->is_mobility || rinfo->is_IGP)
OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
}
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
return 0;
}
static const struct backlight_ops radeon_bl_data = {
.update_status = radeon_bl_update_status,
};
void radeonfb_bl_init(struct radeonfb_info *rinfo)
{
struct backlight_properties props;
struct backlight_device *bd;
struct radeon_bl_privdata *pdata;
char name[12];
if (rinfo->mon1_type != MT_LCD)
return;
#ifdef CONFIG_PMAC_BACKLIGHT
if (!pmac_has_backlight_type("ati") &&
!pmac_has_backlight_type("mnca"))
return;
#endif
pdata = kmalloc(sizeof(struct radeon_bl_privdata), GFP_KERNEL);
if (!pdata) {
printk("radeonfb: Memory allocation failed\n");
goto error;
}
snprintf(name, sizeof(name), "radeonbl%d", rinfo->info->node);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
bd = backlight_device_register(name, rinfo->info->dev, pdata,
&radeon_bl_data, &props);
if (IS_ERR(bd)) {
rinfo->info->bl_dev = NULL;
printk("radeonfb: Backlight registration failed\n");
goto error;
}
pdata->rinfo = rinfo;
/* Pardon me for that hack... maybe some day we can figure out in what
* direction backlight should work on a given panel?
*/
pdata->negative =
(rinfo->family != CHIP_FAMILY_RV200 &&
rinfo->family != CHIP_FAMILY_RV250 &&
rinfo->family != CHIP_FAMILY_RV280 &&
rinfo->family != CHIP_FAMILY_RV350);
#ifdef CONFIG_PMAC_BACKLIGHT
pdata->negative = pdata->negative ||
of_machine_is_compatible("PowerBook4,3") ||
of_machine_is_compatible("PowerBook6,3") ||
of_machine_is_compatible("PowerBook6,5");
#endif
rinfo->info->bl_dev = bd;
fb_bl_default_curve(rinfo->info, 0,
63 * FB_BACKLIGHT_MAX / MAX_RADEON_LEVEL,
217 * FB_BACKLIGHT_MAX / MAX_RADEON_LEVEL);
bd->props.brightness = bd->props.max_brightness;
bd->props.power = FB_BLANK_UNBLANK;
backlight_update_status(bd);
printk("radeonfb: Backlight initialized (%s)\n", name);
return;
error:
kfree(pdata);
return;
}
void radeonfb_bl_exit(struct radeonfb_info *rinfo)
{
struct backlight_device *bd = rinfo->info->bl_dev;
if (bd) {
struct radeon_bl_privdata *pdata;
pdata = bl_get_data(bd);
backlight_device_unregister(bd);
kfree(pdata);
rinfo->info->bl_dev = NULL;
printk("radeonfb: Backlight unloaded\n");
}
}
| gpl-2.0 |
again4you/linux | drivers/video/backlight/lv5207lp.c | 1966 | 4360 | /*
* Sanyo LV5207LP LED Driver
*
* Copyright (C) 2013 Ideas on board SPRL
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/platform_data/lv5207lp.h>
#include <linux/slab.h>
#define LV5207LP_CTRL1 0x00
#define LV5207LP_CPSW (1 << 7)
#define LV5207LP_SCTEN (1 << 6)
#define LV5207LP_C10 (1 << 5)
#define LV5207LP_CKSW (1 << 4)
#define LV5207LP_RSW (1 << 3)
#define LV5207LP_GSW (1 << 2)
#define LV5207LP_BSW (1 << 1)
#define LV5207LP_CTRL2 0x01
#define LV5207LP_MSW (1 << 7)
#define LV5207LP_MLED4 (1 << 6)
#define LV5207LP_RED 0x02
#define LV5207LP_GREEN 0x03
#define LV5207LP_BLUE 0x04
#define LV5207LP_MAX_BRIGHTNESS 32
struct lv5207lp {
struct i2c_client *client;
struct backlight_device *backlight;
struct lv5207lp_platform_data *pdata;
};
static int lv5207lp_write(struct lv5207lp *lv, u8 reg, u8 data)
{
return i2c_smbus_write_byte_data(lv->client, reg, data);
}
static int lv5207lp_backlight_update_status(struct backlight_device *backlight)
{
struct lv5207lp *lv = bl_get_data(backlight);
int brightness = backlight->props.brightness;
if (backlight->props.power != FB_BLANK_UNBLANK ||
backlight->props.fb_blank != FB_BLANK_UNBLANK ||
backlight->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
brightness = 0;
if (brightness) {
lv5207lp_write(lv, LV5207LP_CTRL1,
LV5207LP_CPSW | LV5207LP_C10 | LV5207LP_CKSW);
lv5207lp_write(lv, LV5207LP_CTRL2,
LV5207LP_MSW | LV5207LP_MLED4 |
(brightness - 1));
} else {
lv5207lp_write(lv, LV5207LP_CTRL1, 0);
lv5207lp_write(lv, LV5207LP_CTRL2, 0);
}
return 0;
}
static int lv5207lp_backlight_check_fb(struct backlight_device *backlight,
struct fb_info *info)
{
struct lv5207lp *lv = bl_get_data(backlight);
return lv->pdata->fbdev == NULL || lv->pdata->fbdev == info->dev;
}
static const struct backlight_ops lv5207lp_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = lv5207lp_backlight_update_status,
.check_fb = lv5207lp_backlight_check_fb,
};
static int lv5207lp_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct lv5207lp_platform_data *pdata = dev_get_platdata(&client->dev);
struct backlight_device *backlight;
struct backlight_properties props;
struct lv5207lp *lv;
if (pdata == NULL) {
dev_err(&client->dev, "No platform data supplied\n");
return -EINVAL;
}
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_warn(&client->dev,
"I2C adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
return -EIO;
}
lv = devm_kzalloc(&client->dev, sizeof(*lv), GFP_KERNEL);
if (!lv)
return -ENOMEM;
lv->client = client;
lv->pdata = pdata;
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = min_t(unsigned int, pdata->max_value,
LV5207LP_MAX_BRIGHTNESS);
props.brightness = clamp_t(unsigned int, pdata->def_value, 0,
props.max_brightness);
backlight = devm_backlight_device_register(&client->dev,
dev_name(&client->dev), &lv->client->dev,
lv, &lv5207lp_backlight_ops, &props);
if (IS_ERR(backlight)) {
dev_err(&client->dev, "failed to register backlight\n");
return PTR_ERR(backlight);
}
backlight_update_status(backlight);
i2c_set_clientdata(client, backlight);
return 0;
}
static int lv5207lp_remove(struct i2c_client *client)
{
struct backlight_device *backlight = i2c_get_clientdata(client);
backlight->props.brightness = 0;
backlight_update_status(backlight);
return 0;
}
static const struct i2c_device_id lv5207lp_ids[] = {
{ "lv5207lp", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lv5207lp_ids);
static struct i2c_driver lv5207lp_driver = {
.driver = {
.name = "lv5207lp",
},
.probe = lv5207lp_probe,
.remove = lv5207lp_remove,
.id_table = lv5207lp_ids,
};
module_i2c_driver(lv5207lp_driver);
MODULE_DESCRIPTION("Sanyo LV5207LP Backlight Driver");
MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
MODULE_LICENSE("GPL");
| gpl-2.0 |
TeamRegular/android_kernel_lge_msm8992 | net/bluetooth/cmtp/core.c | 2222 | 10632 | /*
CMTP implementation for Linux Bluetooth stack (BlueZ).
Copyright (C) 2002-2003 Marcel Holtmann <marcel@holtmann.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 2 as
published by the Free Software Foundation;
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS.
IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) AND AUTHOR(S) BE LIABLE FOR ANY
CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PATENTS,
COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS, RELATING TO USE OF THIS
SOFTWARE IS DISCLAIMED.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/poll.h>
#include <linux/fcntl.h>
#include <linux/freezer.h>
#include <linux/skbuff.h>
#include <linux/socket.h>
#include <linux/ioctl.h>
#include <linux/file.h>
#include <linux/init.h>
#include <linux/kthread.h>
#include <net/sock.h>
#include <linux/isdn/capilli.h>
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/l2cap.h>
#include "cmtp.h"
#define VERSION "1.0"
static DECLARE_RWSEM(cmtp_session_sem);
static LIST_HEAD(cmtp_session_list);
static struct cmtp_session *__cmtp_get_session(bdaddr_t *bdaddr)
{
struct cmtp_session *session;
BT_DBG("");
list_for_each_entry(session, &cmtp_session_list, list)
if (!bacmp(bdaddr, &session->bdaddr))
return session;
return NULL;
}
static void __cmtp_link_session(struct cmtp_session *session)
{
list_add(&session->list, &cmtp_session_list);
}
static void __cmtp_unlink_session(struct cmtp_session *session)
{
list_del(&session->list);
}
static void __cmtp_copy_session(struct cmtp_session *session, struct cmtp_conninfo *ci)
{
memset(ci, 0, sizeof(*ci));
bacpy(&ci->bdaddr, &session->bdaddr);
ci->flags = session->flags;
ci->state = session->state;
ci->num = session->num;
}
static inline int cmtp_alloc_block_id(struct cmtp_session *session)
{
int i, id = -1;
for (i = 0; i < 16; i++)
if (!test_and_set_bit(i, &session->blockids)) {
id = i;
break;
}
return id;
}
static inline void cmtp_free_block_id(struct cmtp_session *session, int id)
{
clear_bit(id, &session->blockids);
}
static inline void cmtp_add_msgpart(struct cmtp_session *session, int id, const unsigned char *buf, int count)
{
struct sk_buff *skb = session->reassembly[id], *nskb;
int size;
BT_DBG("session %p buf %p count %d", session, buf, count);
size = (skb) ? skb->len + count : count;
nskb = alloc_skb(size, GFP_ATOMIC);
if (!nskb) {
BT_ERR("Can't allocate memory for CAPI message");
return;
}
if (skb && (skb->len > 0))
skb_copy_from_linear_data(skb, skb_put(nskb, skb->len), skb->len);
memcpy(skb_put(nskb, count), buf, count);
session->reassembly[id] = nskb;
kfree_skb(skb);
}
static inline int cmtp_recv_frame(struct cmtp_session *session, struct sk_buff *skb)
{
__u8 hdr, hdrlen, id;
__u16 len;
BT_DBG("session %p skb %p len %d", session, skb, skb->len);
while (skb->len > 0) {
hdr = skb->data[0];
switch (hdr & 0xc0) {
case 0x40:
hdrlen = 2;
len = skb->data[1];
break;
case 0x80:
hdrlen = 3;
len = skb->data[1] | (skb->data[2] << 8);
break;
default:
hdrlen = 1;
len = 0;
break;
}
id = (hdr & 0x3c) >> 2;
BT_DBG("hdr 0x%02x hdrlen %d len %d id %d", hdr, hdrlen, len, id);
if (hdrlen + len > skb->len) {
BT_ERR("Wrong size or header information in CMTP frame");
break;
}
if (len == 0) {
skb_pull(skb, hdrlen);
continue;
}
switch (hdr & 0x03) {
case 0x00:
cmtp_add_msgpart(session, id, skb->data + hdrlen, len);
cmtp_recv_capimsg(session, session->reassembly[id]);
session->reassembly[id] = NULL;
break;
case 0x01:
cmtp_add_msgpart(session, id, skb->data + hdrlen, len);
break;
default:
if (session->reassembly[id] != NULL)
kfree_skb(session->reassembly[id]);
session->reassembly[id] = NULL;
break;
}
skb_pull(skb, hdrlen + len);
}
kfree_skb(skb);
return 0;
}
static int cmtp_send_frame(struct cmtp_session *session, unsigned char *data, int len)
{
struct socket *sock = session->sock;
struct kvec iv = { data, len };
struct msghdr msg;
BT_DBG("session %p data %p len %d", session, data, len);
if (!len)
return 0;
memset(&msg, 0, sizeof(msg));
return kernel_sendmsg(sock, &msg, &iv, 1, len);
}
static void cmtp_process_transmit(struct cmtp_session *session)
{
struct sk_buff *skb, *nskb;
unsigned char *hdr;
unsigned int size, tail;
BT_DBG("session %p", session);
nskb = alloc_skb(session->mtu, GFP_ATOMIC);
if (!nskb) {
BT_ERR("Can't allocate memory for new frame");
return;
}
while ((skb = skb_dequeue(&session->transmit))) {
struct cmtp_scb *scb = (void *) skb->cb;
tail = session->mtu - nskb->len;
if (tail < 5) {
cmtp_send_frame(session, nskb->data, nskb->len);
skb_trim(nskb, 0);
tail = session->mtu;
}
size = min_t(uint, ((tail < 258) ? (tail - 2) : (tail - 3)), skb->len);
if (scb->id < 0) {
scb->id = cmtp_alloc_block_id(session);
if (scb->id < 0) {
skb_queue_head(&session->transmit, skb);
break;
}
}
if (size < 256) {
hdr = skb_put(nskb, 2);
hdr[0] = 0x40
| ((scb->id << 2) & 0x3c)
| ((skb->len == size) ? 0x00 : 0x01);
hdr[1] = size;
} else {
hdr = skb_put(nskb, 3);
hdr[0] = 0x80
| ((scb->id << 2) & 0x3c)
| ((skb->len == size) ? 0x00 : 0x01);
hdr[1] = size & 0xff;
hdr[2] = size >> 8;
}
skb_copy_from_linear_data(skb, skb_put(nskb, size), size);
skb_pull(skb, size);
if (skb->len > 0) {
skb_queue_head(&session->transmit, skb);
} else {
cmtp_free_block_id(session, scb->id);
if (scb->data) {
cmtp_send_frame(session, nskb->data, nskb->len);
skb_trim(nskb, 0);
}
kfree_skb(skb);
}
}
cmtp_send_frame(session, nskb->data, nskb->len);
kfree_skb(nskb);
}
static int cmtp_session(void *arg)
{
struct cmtp_session *session = arg;
struct sock *sk = session->sock->sk;
struct sk_buff *skb;
wait_queue_t wait;
BT_DBG("session %p", session);
set_user_nice(current, -15);
init_waitqueue_entry(&wait, current);
add_wait_queue(sk_sleep(sk), &wait);
while (1) {
set_current_state(TASK_INTERRUPTIBLE);
if (atomic_read(&session->terminate))
break;
if (sk->sk_state != BT_CONNECTED)
break;
while ((skb = skb_dequeue(&sk->sk_receive_queue))) {
skb_orphan(skb);
if (!skb_linearize(skb))
cmtp_recv_frame(session, skb);
else
kfree_skb(skb);
}
cmtp_process_transmit(session);
schedule();
}
__set_current_state(TASK_RUNNING);
remove_wait_queue(sk_sleep(sk), &wait);
down_write(&cmtp_session_sem);
if (!(session->flags & (1 << CMTP_LOOPBACK)))
cmtp_detach_device(session);
fput(session->sock->file);
__cmtp_unlink_session(session);
up_write(&cmtp_session_sem);
kfree(session);
module_put_and_exit(0);
return 0;
}
int cmtp_add_connection(struct cmtp_connadd_req *req, struct socket *sock)
{
struct cmtp_session *session, *s;
int i, err;
BT_DBG("");
session = kzalloc(sizeof(struct cmtp_session), GFP_KERNEL);
if (!session)
return -ENOMEM;
down_write(&cmtp_session_sem);
s = __cmtp_get_session(&bt_sk(sock->sk)->dst);
if (s && s->state == BT_CONNECTED) {
err = -EEXIST;
goto failed;
}
bacpy(&session->bdaddr, &bt_sk(sock->sk)->dst);
session->mtu = min_t(uint, l2cap_pi(sock->sk)->chan->omtu,
l2cap_pi(sock->sk)->chan->imtu);
BT_DBG("mtu %d", session->mtu);
sprintf(session->name, "%pMR", &bt_sk(sock->sk)->dst);
session->sock = sock;
session->state = BT_CONFIG;
init_waitqueue_head(&session->wait);
session->msgnum = CMTP_INITIAL_MSGNUM;
INIT_LIST_HEAD(&session->applications);
skb_queue_head_init(&session->transmit);
for (i = 0; i < 16; i++)
session->reassembly[i] = NULL;
session->flags = req->flags;
__cmtp_link_session(session);
__module_get(THIS_MODULE);
session->task = kthread_run(cmtp_session, session, "kcmtpd_ctr_%d",
session->num);
if (IS_ERR(session->task)) {
module_put(THIS_MODULE);
err = PTR_ERR(session->task);
goto unlink;
}
if (!(session->flags & (1 << CMTP_LOOPBACK))) {
err = cmtp_attach_device(session);
if (err < 0) {
atomic_inc(&session->terminate);
wake_up_process(session->task);
up_write(&cmtp_session_sem);
return err;
}
}
up_write(&cmtp_session_sem);
return 0;
unlink:
__cmtp_unlink_session(session);
failed:
up_write(&cmtp_session_sem);
kfree(session);
return err;
}
int cmtp_del_connection(struct cmtp_conndel_req *req)
{
struct cmtp_session *session;
int err = 0;
BT_DBG("");
down_read(&cmtp_session_sem);
session = __cmtp_get_session(&req->bdaddr);
if (session) {
/* Flush the transmit queue */
skb_queue_purge(&session->transmit);
/* Stop session thread */
atomic_inc(&session->terminate);
wake_up_process(session->task);
} else
err = -ENOENT;
up_read(&cmtp_session_sem);
return err;
}
int cmtp_get_connlist(struct cmtp_connlist_req *req)
{
struct cmtp_session *session;
int err = 0, n = 0;
BT_DBG("");
down_read(&cmtp_session_sem);
list_for_each_entry(session, &cmtp_session_list, list) {
struct cmtp_conninfo ci;
__cmtp_copy_session(session, &ci);
if (copy_to_user(req->ci, &ci, sizeof(ci))) {
err = -EFAULT;
break;
}
if (++n >= req->cnum)
break;
req->ci++;
}
req->cnum = n;
up_read(&cmtp_session_sem);
return err;
}
int cmtp_get_conninfo(struct cmtp_conninfo *ci)
{
struct cmtp_session *session;
int err = 0;
down_read(&cmtp_session_sem);
session = __cmtp_get_session(&ci->bdaddr);
if (session)
__cmtp_copy_session(session, ci);
else
err = -ENOENT;
up_read(&cmtp_session_sem);
return err;
}
static int __init cmtp_init(void)
{
BT_INFO("CMTP (CAPI Emulation) ver %s", VERSION);
cmtp_init_sockets();
return 0;
}
static void __exit cmtp_exit(void)
{
cmtp_cleanup_sockets();
}
module_init(cmtp_init);
module_exit(cmtp_exit);
MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
MODULE_DESCRIPTION("Bluetooth CMTP ver " VERSION);
MODULE_VERSION(VERSION);
MODULE_LICENSE("GPL");
MODULE_ALIAS("bt-proto-5");
| gpl-2.0 |
TeamEOS/kernel_htc_flounder | net/bluetooth/cmtp/core.c | 2222 | 10632 | /*
CMTP implementation for Linux Bluetooth stack (BlueZ).
Copyright (C) 2002-2003 Marcel Holtmann <marcel@holtmann.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 2 as
published by the Free Software Foundation;
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS.
IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) AND AUTHOR(S) BE LIABLE FOR ANY
CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PATENTS,
COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS, RELATING TO USE OF THIS
SOFTWARE IS DISCLAIMED.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/poll.h>
#include <linux/fcntl.h>
#include <linux/freezer.h>
#include <linux/skbuff.h>
#include <linux/socket.h>
#include <linux/ioctl.h>
#include <linux/file.h>
#include <linux/init.h>
#include <linux/kthread.h>
#include <net/sock.h>
#include <linux/isdn/capilli.h>
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/l2cap.h>
#include "cmtp.h"
#define VERSION "1.0"
static DECLARE_RWSEM(cmtp_session_sem);
static LIST_HEAD(cmtp_session_list);
static struct cmtp_session *__cmtp_get_session(bdaddr_t *bdaddr)
{
struct cmtp_session *session;
BT_DBG("");
list_for_each_entry(session, &cmtp_session_list, list)
if (!bacmp(bdaddr, &session->bdaddr))
return session;
return NULL;
}
static void __cmtp_link_session(struct cmtp_session *session)
{
list_add(&session->list, &cmtp_session_list);
}
static void __cmtp_unlink_session(struct cmtp_session *session)
{
list_del(&session->list);
}
static void __cmtp_copy_session(struct cmtp_session *session, struct cmtp_conninfo *ci)
{
memset(ci, 0, sizeof(*ci));
bacpy(&ci->bdaddr, &session->bdaddr);
ci->flags = session->flags;
ci->state = session->state;
ci->num = session->num;
}
static inline int cmtp_alloc_block_id(struct cmtp_session *session)
{
int i, id = -1;
for (i = 0; i < 16; i++)
if (!test_and_set_bit(i, &session->blockids)) {
id = i;
break;
}
return id;
}
static inline void cmtp_free_block_id(struct cmtp_session *session, int id)
{
clear_bit(id, &session->blockids);
}
static inline void cmtp_add_msgpart(struct cmtp_session *session, int id, const unsigned char *buf, int count)
{
struct sk_buff *skb = session->reassembly[id], *nskb;
int size;
BT_DBG("session %p buf %p count %d", session, buf, count);
size = (skb) ? skb->len + count : count;
nskb = alloc_skb(size, GFP_ATOMIC);
if (!nskb) {
BT_ERR("Can't allocate memory for CAPI message");
return;
}
if (skb && (skb->len > 0))
skb_copy_from_linear_data(skb, skb_put(nskb, skb->len), skb->len);
memcpy(skb_put(nskb, count), buf, count);
session->reassembly[id] = nskb;
kfree_skb(skb);
}
static inline int cmtp_recv_frame(struct cmtp_session *session, struct sk_buff *skb)
{
__u8 hdr, hdrlen, id;
__u16 len;
BT_DBG("session %p skb %p len %d", session, skb, skb->len);
while (skb->len > 0) {
hdr = skb->data[0];
switch (hdr & 0xc0) {
case 0x40:
hdrlen = 2;
len = skb->data[1];
break;
case 0x80:
hdrlen = 3;
len = skb->data[1] | (skb->data[2] << 8);
break;
default:
hdrlen = 1;
len = 0;
break;
}
id = (hdr & 0x3c) >> 2;
BT_DBG("hdr 0x%02x hdrlen %d len %d id %d", hdr, hdrlen, len, id);
if (hdrlen + len > skb->len) {
BT_ERR("Wrong size or header information in CMTP frame");
break;
}
if (len == 0) {
skb_pull(skb, hdrlen);
continue;
}
switch (hdr & 0x03) {
case 0x00:
cmtp_add_msgpart(session, id, skb->data + hdrlen, len);
cmtp_recv_capimsg(session, session->reassembly[id]);
session->reassembly[id] = NULL;
break;
case 0x01:
cmtp_add_msgpart(session, id, skb->data + hdrlen, len);
break;
default:
if (session->reassembly[id] != NULL)
kfree_skb(session->reassembly[id]);
session->reassembly[id] = NULL;
break;
}
skb_pull(skb, hdrlen + len);
}
kfree_skb(skb);
return 0;
}
static int cmtp_send_frame(struct cmtp_session *session, unsigned char *data, int len)
{
struct socket *sock = session->sock;
struct kvec iv = { data, len };
struct msghdr msg;
BT_DBG("session %p data %p len %d", session, data, len);
if (!len)
return 0;
memset(&msg, 0, sizeof(msg));
return kernel_sendmsg(sock, &msg, &iv, 1, len);
}
static void cmtp_process_transmit(struct cmtp_session *session)
{
struct sk_buff *skb, *nskb;
unsigned char *hdr;
unsigned int size, tail;
BT_DBG("session %p", session);
nskb = alloc_skb(session->mtu, GFP_ATOMIC);
if (!nskb) {
BT_ERR("Can't allocate memory for new frame");
return;
}
while ((skb = skb_dequeue(&session->transmit))) {
struct cmtp_scb *scb = (void *) skb->cb;
tail = session->mtu - nskb->len;
if (tail < 5) {
cmtp_send_frame(session, nskb->data, nskb->len);
skb_trim(nskb, 0);
tail = session->mtu;
}
size = min_t(uint, ((tail < 258) ? (tail - 2) : (tail - 3)), skb->len);
if (scb->id < 0) {
scb->id = cmtp_alloc_block_id(session);
if (scb->id < 0) {
skb_queue_head(&session->transmit, skb);
break;
}
}
if (size < 256) {
hdr = skb_put(nskb, 2);
hdr[0] = 0x40
| ((scb->id << 2) & 0x3c)
| ((skb->len == size) ? 0x00 : 0x01);
hdr[1] = size;
} else {
hdr = skb_put(nskb, 3);
hdr[0] = 0x80
| ((scb->id << 2) & 0x3c)
| ((skb->len == size) ? 0x00 : 0x01);
hdr[1] = size & 0xff;
hdr[2] = size >> 8;
}
skb_copy_from_linear_data(skb, skb_put(nskb, size), size);
skb_pull(skb, size);
if (skb->len > 0) {
skb_queue_head(&session->transmit, skb);
} else {
cmtp_free_block_id(session, scb->id);
if (scb->data) {
cmtp_send_frame(session, nskb->data, nskb->len);
skb_trim(nskb, 0);
}
kfree_skb(skb);
}
}
cmtp_send_frame(session, nskb->data, nskb->len);
kfree_skb(nskb);
}
static int cmtp_session(void *arg)
{
struct cmtp_session *session = arg;
struct sock *sk = session->sock->sk;
struct sk_buff *skb;
wait_queue_t wait;
BT_DBG("session %p", session);
set_user_nice(current, -15);
init_waitqueue_entry(&wait, current);
add_wait_queue(sk_sleep(sk), &wait);
while (1) {
set_current_state(TASK_INTERRUPTIBLE);
if (atomic_read(&session->terminate))
break;
if (sk->sk_state != BT_CONNECTED)
break;
while ((skb = skb_dequeue(&sk->sk_receive_queue))) {
skb_orphan(skb);
if (!skb_linearize(skb))
cmtp_recv_frame(session, skb);
else
kfree_skb(skb);
}
cmtp_process_transmit(session);
schedule();
}
__set_current_state(TASK_RUNNING);
remove_wait_queue(sk_sleep(sk), &wait);
down_write(&cmtp_session_sem);
if (!(session->flags & (1 << CMTP_LOOPBACK)))
cmtp_detach_device(session);
fput(session->sock->file);
__cmtp_unlink_session(session);
up_write(&cmtp_session_sem);
kfree(session);
module_put_and_exit(0);
return 0;
}
int cmtp_add_connection(struct cmtp_connadd_req *req, struct socket *sock)
{
struct cmtp_session *session, *s;
int i, err;
BT_DBG("");
session = kzalloc(sizeof(struct cmtp_session), GFP_KERNEL);
if (!session)
return -ENOMEM;
down_write(&cmtp_session_sem);
s = __cmtp_get_session(&bt_sk(sock->sk)->dst);
if (s && s->state == BT_CONNECTED) {
err = -EEXIST;
goto failed;
}
bacpy(&session->bdaddr, &bt_sk(sock->sk)->dst);
session->mtu = min_t(uint, l2cap_pi(sock->sk)->chan->omtu,
l2cap_pi(sock->sk)->chan->imtu);
BT_DBG("mtu %d", session->mtu);
sprintf(session->name, "%pMR", &bt_sk(sock->sk)->dst);
session->sock = sock;
session->state = BT_CONFIG;
init_waitqueue_head(&session->wait);
session->msgnum = CMTP_INITIAL_MSGNUM;
INIT_LIST_HEAD(&session->applications);
skb_queue_head_init(&session->transmit);
for (i = 0; i < 16; i++)
session->reassembly[i] = NULL;
session->flags = req->flags;
__cmtp_link_session(session);
__module_get(THIS_MODULE);
session->task = kthread_run(cmtp_session, session, "kcmtpd_ctr_%d",
session->num);
if (IS_ERR(session->task)) {
module_put(THIS_MODULE);
err = PTR_ERR(session->task);
goto unlink;
}
if (!(session->flags & (1 << CMTP_LOOPBACK))) {
err = cmtp_attach_device(session);
if (err < 0) {
atomic_inc(&session->terminate);
wake_up_process(session->task);
up_write(&cmtp_session_sem);
return err;
}
}
up_write(&cmtp_session_sem);
return 0;
unlink:
__cmtp_unlink_session(session);
failed:
up_write(&cmtp_session_sem);
kfree(session);
return err;
}
int cmtp_del_connection(struct cmtp_conndel_req *req)
{
struct cmtp_session *session;
int err = 0;
BT_DBG("");
down_read(&cmtp_session_sem);
session = __cmtp_get_session(&req->bdaddr);
if (session) {
/* Flush the transmit queue */
skb_queue_purge(&session->transmit);
/* Stop session thread */
atomic_inc(&session->terminate);
wake_up_process(session->task);
} else
err = -ENOENT;
up_read(&cmtp_session_sem);
return err;
}
int cmtp_get_connlist(struct cmtp_connlist_req *req)
{
struct cmtp_session *session;
int err = 0, n = 0;
BT_DBG("");
down_read(&cmtp_session_sem);
list_for_each_entry(session, &cmtp_session_list, list) {
struct cmtp_conninfo ci;
__cmtp_copy_session(session, &ci);
if (copy_to_user(req->ci, &ci, sizeof(ci))) {
err = -EFAULT;
break;
}
if (++n >= req->cnum)
break;
req->ci++;
}
req->cnum = n;
up_read(&cmtp_session_sem);
return err;
}
int cmtp_get_conninfo(struct cmtp_conninfo *ci)
{
struct cmtp_session *session;
int err = 0;
down_read(&cmtp_session_sem);
session = __cmtp_get_session(&ci->bdaddr);
if (session)
__cmtp_copy_session(session, ci);
else
err = -ENOENT;
up_read(&cmtp_session_sem);
return err;
}
static int __init cmtp_init(void)
{
BT_INFO("CMTP (CAPI Emulation) ver %s", VERSION);
cmtp_init_sockets();
return 0;
}
static void __exit cmtp_exit(void)
{
cmtp_cleanup_sockets();
}
module_init(cmtp_init);
module_exit(cmtp_exit);
MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
MODULE_DESCRIPTION("Bluetooth CMTP ver " VERSION);
MODULE_VERSION(VERSION);
MODULE_LICENSE("GPL");
MODULE_ALIAS("bt-proto-5");
| gpl-2.0 |
googyanas/GoogyMax-S6 | drivers/staging/tidspbridge/core/msg_sm.c | 2734 | 15312 | /*
* msg_sm.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implements upper edge functions for Bridge message module.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/types.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
/* ----------------------------------- OS Adaptation Layer */
#include <dspbridge/sync.h>
/* ----------------------------------- Platform Manager */
#include <dspbridge/dev.h>
/* ----------------------------------- Others */
#include <dspbridge/io_sm.h>
/* ----------------------------------- This */
#include <_msg_sm.h>
#include <dspbridge/dspmsg.h>
/* ----------------------------------- Function Prototypes */
static int add_new_msg(struct list_head *msg_list);
static void delete_msg_mgr(struct msg_mgr *hmsg_mgr);
static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 num_to_dsp);
static void free_msg_list(struct list_head *msg_list);
/*
* ======== bridge_msg_create ========
* Create an object to manage message queues. Only one of these objects
* can exist per device object.
*/
int bridge_msg_create(struct msg_mgr **msg_man,
struct dev_object *hdev_obj,
msg_onexit msg_callback)
{
struct msg_mgr *msg_mgr_obj;
struct io_mgr *hio_mgr;
int status = 0;
if (!msg_man || !msg_callback || !hdev_obj)
return -EFAULT;
dev_get_io_mgr(hdev_obj, &hio_mgr);
if (!hio_mgr)
return -EFAULT;
*msg_man = NULL;
/* Allocate msg_ctrl manager object */
msg_mgr_obj = kzalloc(sizeof(struct msg_mgr), GFP_KERNEL);
if (!msg_mgr_obj)
return -ENOMEM;
msg_mgr_obj->on_exit = msg_callback;
msg_mgr_obj->iomgr = hio_mgr;
/* List of MSG_QUEUEs */
INIT_LIST_HEAD(&msg_mgr_obj->queue_list);
/*
* Queues of message frames for messages to the DSP. Message
* frames will only be added to the free queue when a
* msg_queue object is created.
*/
INIT_LIST_HEAD(&msg_mgr_obj->msg_free_list);
INIT_LIST_HEAD(&msg_mgr_obj->msg_used_list);
spin_lock_init(&msg_mgr_obj->msg_mgr_lock);
/*
* Create an event to be used by bridge_msg_put() in waiting
* for an available free frame from the message manager.
*/
msg_mgr_obj->sync_event =
kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_mgr_obj->sync_event) {
kfree(msg_mgr_obj);
return -ENOMEM;
}
sync_init_event(msg_mgr_obj->sync_event);
*msg_man = msg_mgr_obj;
return status;
}
/*
* ======== bridge_msg_create_queue ========
* Create a msg_queue for sending/receiving messages to/from a node
* on the DSP.
*/
int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, struct msg_queue **msgq,
u32 msgq_id, u32 max_msgs, void *arg)
{
u32 i;
u32 num_allocated = 0;
struct msg_queue *msg_q;
int status = 0;
if (!hmsg_mgr || msgq == NULL)
return -EFAULT;
*msgq = NULL;
/* Allocate msg_queue object */
msg_q = kzalloc(sizeof(struct msg_queue), GFP_KERNEL);
if (!msg_q)
return -ENOMEM;
msg_q->max_msgs = max_msgs;
msg_q->msg_mgr = hmsg_mgr;
msg_q->arg = arg; /* Node handle */
msg_q->msgq_id = msgq_id; /* Node env (not valid yet) */
/* Queues of Message frames for messages from the DSP */
INIT_LIST_HEAD(&msg_q->msg_free_list);
INIT_LIST_HEAD(&msg_q->msg_used_list);
/* Create event that will be signalled when a message from
* the DSP is available. */
msg_q->sync_event = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_event) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_event);
/* Create a notification list for message ready notification. */
msg_q->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL);
if (!msg_q->ntfy_obj) {
status = -ENOMEM;
goto out_err;
}
ntfy_init(msg_q->ntfy_obj);
/* Create events that will be used to synchronize cleanup
* when the object is deleted. sync_done will be set to
* unblock threads in MSG_Put() or MSG_Get(). sync_done_ack
* will be set by the unblocked thread to signal that it
* is unblocked and will no longer reference the object. */
msg_q->sync_done = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_done) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_done);
msg_q->sync_done_ack = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_done_ack) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_done_ack);
/* Enter critical section */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* Initialize message frames and put in appropriate queues */
for (i = 0; i < max_msgs && !status; i++) {
status = add_new_msg(&hmsg_mgr->msg_free_list);
if (!status) {
num_allocated++;
status = add_new_msg(&msg_q->msg_free_list);
}
}
if (status) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
goto out_err;
}
list_add_tail(&msg_q->list_elem, &hmsg_mgr->queue_list);
*msgq = msg_q;
/* Signal that free frames are now available */
if (!list_empty(&hmsg_mgr->msg_free_list))
sync_set_event(hmsg_mgr->sync_event);
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
out_err:
delete_msg_queue(msg_q, num_allocated);
return status;
}
/*
* ======== bridge_msg_delete ========
* Delete a msg_ctrl manager allocated in bridge_msg_create().
*/
void bridge_msg_delete(struct msg_mgr *hmsg_mgr)
{
delete_msg_mgr(hmsg_mgr);
}
/*
* ======== bridge_msg_delete_queue ========
* Delete a msg_ctrl queue allocated in bridge_msg_create_queue.
*/
void bridge_msg_delete_queue(struct msg_queue *msg_queue_obj)
{
struct msg_mgr *hmsg_mgr;
u32 io_msg_pend;
if (!msg_queue_obj || !msg_queue_obj->msg_mgr)
return;
hmsg_mgr = msg_queue_obj->msg_mgr;
msg_queue_obj->done = true;
/* Unblock all threads blocked in MSG_Get() or MSG_Put(). */
io_msg_pend = msg_queue_obj->io_msg_pend;
while (io_msg_pend) {
/* Unblock thread */
sync_set_event(msg_queue_obj->sync_done);
/* Wait for acknowledgement */
sync_wait_on_event(msg_queue_obj->sync_done_ack, SYNC_INFINITE);
io_msg_pend = msg_queue_obj->io_msg_pend;
}
/* Remove message queue from hmsg_mgr->queue_list */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
list_del(&msg_queue_obj->list_elem);
/* Free the message queue object */
delete_msg_queue(msg_queue_obj, msg_queue_obj->max_msgs);
if (list_empty(&hmsg_mgr->msg_free_list))
sync_reset_event(hmsg_mgr->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
}
/*
* ======== bridge_msg_get ========
* Get a message from a msg_ctrl queue.
*/
int bridge_msg_get(struct msg_queue *msg_queue_obj,
struct dsp_msg *pmsg, u32 utimeout)
{
struct msg_frame *msg_frame_obj;
struct msg_mgr *hmsg_mgr;
struct sync_object *syncs[2];
u32 index;
int status = 0;
if (!msg_queue_obj || pmsg == NULL)
return -ENOMEM;
hmsg_mgr = msg_queue_obj->msg_mgr;
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* If a message is already there, get it */
if (!list_empty(&msg_queue_obj->msg_used_list)) {
msg_frame_obj = list_first_entry(&msg_queue_obj->msg_used_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
*pmsg = msg_frame_obj->msg_data.msg;
list_add_tail(&msg_frame_obj->list_elem,
&msg_queue_obj->msg_free_list);
if (list_empty(&msg_queue_obj->msg_used_list))
sync_reset_event(msg_queue_obj->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
}
if (msg_queue_obj->done) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EPERM;
}
msg_queue_obj->io_msg_pend++;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Wait til message is available, timeout, or done. We don't
* have to schedule the DPC, since the DSP will send messages
* when they are available.
*/
syncs[0] = msg_queue_obj->sync_event;
syncs[1] = msg_queue_obj->sync_done;
status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index);
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
if (msg_queue_obj->done) {
msg_queue_obj->io_msg_pend--;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Signal that we're not going to access msg_queue_obj
* anymore, so it can be deleted.
*/
sync_set_event(msg_queue_obj->sync_done_ack);
return -EPERM;
}
if (!status && !list_empty(&msg_queue_obj->msg_used_list)) {
/* Get msg from used list */
msg_frame_obj = list_first_entry(&msg_queue_obj->msg_used_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
/* Copy message into pmsg and put frame on the free list */
*pmsg = msg_frame_obj->msg_data.msg;
list_add_tail(&msg_frame_obj->list_elem,
&msg_queue_obj->msg_free_list);
}
msg_queue_obj->io_msg_pend--;
/* Reset the event if there are still queued messages */
if (!list_empty(&msg_queue_obj->msg_used_list))
sync_set_event(msg_queue_obj->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return status;
}
/*
* ======== bridge_msg_put ========
* Put a message onto a msg_ctrl queue.
*/
int bridge_msg_put(struct msg_queue *msg_queue_obj,
const struct dsp_msg *pmsg, u32 utimeout)
{
struct msg_frame *msg_frame_obj;
struct msg_mgr *hmsg_mgr;
struct sync_object *syncs[2];
u32 index;
int status;
if (!msg_queue_obj || !pmsg || !msg_queue_obj->msg_mgr)
return -EFAULT;
hmsg_mgr = msg_queue_obj->msg_mgr;
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* If a message frame is available, use it */
if (!list_empty(&hmsg_mgr->msg_free_list)) {
msg_frame_obj = list_first_entry(&hmsg_mgr->msg_free_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
msg_frame_obj->msg_data.msg = *pmsg;
msg_frame_obj->msg_data.msgq_id =
msg_queue_obj->msgq_id;
list_add_tail(&msg_frame_obj->list_elem,
&hmsg_mgr->msg_used_list);
hmsg_mgr->msgs_pending++;
if (list_empty(&hmsg_mgr->msg_free_list))
sync_reset_event(hmsg_mgr->sync_event);
/* Release critical section before scheduling DPC */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/* Schedule a DPC, to do the actual data transfer: */
iosm_schedule(hmsg_mgr->iomgr);
return 0;
}
if (msg_queue_obj->done) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EPERM;
}
msg_queue_obj->io_msg_pend++;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/* Wait til a free message frame is available, timeout, or done */
syncs[0] = hmsg_mgr->sync_event;
syncs[1] = msg_queue_obj->sync_done;
status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index);
if (status)
return status;
/* Enter critical section */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
if (msg_queue_obj->done) {
msg_queue_obj->io_msg_pend--;
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Signal that we're not going to access msg_queue_obj
* anymore, so it can be deleted.
*/
sync_set_event(msg_queue_obj->sync_done_ack);
return -EPERM;
}
if (list_empty(&hmsg_mgr->msg_free_list)) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EFAULT;
}
/* Get msg from free list */
msg_frame_obj = list_first_entry(&hmsg_mgr->msg_free_list,
struct msg_frame, list_elem);
/*
* Copy message into pmsg and put frame on the
* used list.
*/
list_del(&msg_frame_obj->list_elem);
msg_frame_obj->msg_data.msg = *pmsg;
msg_frame_obj->msg_data.msgq_id = msg_queue_obj->msgq_id;
list_add_tail(&msg_frame_obj->list_elem, &hmsg_mgr->msg_used_list);
hmsg_mgr->msgs_pending++;
/*
* Schedule a DPC, to do the actual
* data transfer.
*/
iosm_schedule(hmsg_mgr->iomgr);
msg_queue_obj->io_msg_pend--;
/* Reset event if there are still frames available */
if (!list_empty(&hmsg_mgr->msg_free_list))
sync_set_event(hmsg_mgr->sync_event);
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
}
/*
* ======== bridge_msg_register_notify ========
*/
int bridge_msg_register_notify(struct msg_queue *msg_queue_obj,
u32 event_mask, u32 notify_type,
struct dsp_notification *hnotification)
{
int status = 0;
if (!msg_queue_obj || !hnotification) {
status = -ENOMEM;
goto func_end;
}
if (!(event_mask == DSP_NODEMESSAGEREADY || event_mask == 0)) {
status = -EPERM;
goto func_end;
}
if (notify_type != DSP_SIGNALEVENT) {
status = -EBADR;
goto func_end;
}
if (event_mask)
status = ntfy_register(msg_queue_obj->ntfy_obj, hnotification,
event_mask, notify_type);
else
status = ntfy_unregister(msg_queue_obj->ntfy_obj,
hnotification);
if (status == -EINVAL) {
/* Not registered. Ok, since we couldn't have known. Node
* notifications are split between node state change handled
* by NODE, and message ready handled by msg_ctrl. */
status = 0;
}
func_end:
return status;
}
/*
* ======== bridge_msg_set_queue_id ========
*/
void bridge_msg_set_queue_id(struct msg_queue *msg_queue_obj, u32 msgq_id)
{
/*
* A message queue must be created when a node is allocated,
* so that node_register_notify() can be called before the node
* is created. Since we don't know the node environment until the
* node is created, we need this function to set msg_queue_obj->msgq_id
* to the node environment, after the node is created.
*/
if (msg_queue_obj)
msg_queue_obj->msgq_id = msgq_id;
}
/*
* ======== add_new_msg ========
* Must be called in message manager critical section.
*/
static int add_new_msg(struct list_head *msg_list)
{
struct msg_frame *pmsg;
pmsg = kzalloc(sizeof(struct msg_frame), GFP_ATOMIC);
if (!pmsg)
return -ENOMEM;
list_add_tail(&pmsg->list_elem, msg_list);
return 0;
}
/*
* ======== delete_msg_mgr ========
*/
static void delete_msg_mgr(struct msg_mgr *hmsg_mgr)
{
if (!hmsg_mgr)
return;
/* FIXME: free elements from queue_list? */
free_msg_list(&hmsg_mgr->msg_free_list);
free_msg_list(&hmsg_mgr->msg_used_list);
kfree(hmsg_mgr->sync_event);
kfree(hmsg_mgr);
}
/*
* ======== delete_msg_queue ========
*/
static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 num_to_dsp)
{
struct msg_mgr *hmsg_mgr;
struct msg_frame *pmsg, *tmp;
u32 i;
if (!msg_queue_obj || !msg_queue_obj->msg_mgr)
return;
hmsg_mgr = msg_queue_obj->msg_mgr;
/* Pull off num_to_dsp message frames from Msg manager and free */
i = 0;
list_for_each_entry_safe(pmsg, tmp, &hmsg_mgr->msg_free_list,
list_elem) {
list_del(&pmsg->list_elem);
kfree(pmsg);
if (i++ >= num_to_dsp)
break;
}
free_msg_list(&msg_queue_obj->msg_free_list);
free_msg_list(&msg_queue_obj->msg_used_list);
if (msg_queue_obj->ntfy_obj) {
ntfy_delete(msg_queue_obj->ntfy_obj);
kfree(msg_queue_obj->ntfy_obj);
}
kfree(msg_queue_obj->sync_event);
kfree(msg_queue_obj->sync_done);
kfree(msg_queue_obj->sync_done_ack);
kfree(msg_queue_obj);
}
/*
* ======== free_msg_list ========
*/
static void free_msg_list(struct list_head *msg_list)
{
struct msg_frame *pmsg, *tmp;
if (!msg_list)
return;
list_for_each_entry_safe(pmsg, tmp, msg_list, list_elem) {
list_del(&pmsg->list_elem);
kfree(pmsg);
}
}
| gpl-2.0 |
drod2169/Linux-3.12.x | drivers/staging/tidspbridge/core/msg_sm.c | 2734 | 15312 | /*
* msg_sm.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implements upper edge functions for Bridge message module.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/types.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
/* ----------------------------------- OS Adaptation Layer */
#include <dspbridge/sync.h>
/* ----------------------------------- Platform Manager */
#include <dspbridge/dev.h>
/* ----------------------------------- Others */
#include <dspbridge/io_sm.h>
/* ----------------------------------- This */
#include <_msg_sm.h>
#include <dspbridge/dspmsg.h>
/* ----------------------------------- Function Prototypes */
static int add_new_msg(struct list_head *msg_list);
static void delete_msg_mgr(struct msg_mgr *hmsg_mgr);
static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 num_to_dsp);
static void free_msg_list(struct list_head *msg_list);
/*
* ======== bridge_msg_create ========
* Create an object to manage message queues. Only one of these objects
* can exist per device object.
*/
int bridge_msg_create(struct msg_mgr **msg_man,
struct dev_object *hdev_obj,
msg_onexit msg_callback)
{
struct msg_mgr *msg_mgr_obj;
struct io_mgr *hio_mgr;
int status = 0;
if (!msg_man || !msg_callback || !hdev_obj)
return -EFAULT;
dev_get_io_mgr(hdev_obj, &hio_mgr);
if (!hio_mgr)
return -EFAULT;
*msg_man = NULL;
/* Allocate msg_ctrl manager object */
msg_mgr_obj = kzalloc(sizeof(struct msg_mgr), GFP_KERNEL);
if (!msg_mgr_obj)
return -ENOMEM;
msg_mgr_obj->on_exit = msg_callback;
msg_mgr_obj->iomgr = hio_mgr;
/* List of MSG_QUEUEs */
INIT_LIST_HEAD(&msg_mgr_obj->queue_list);
/*
* Queues of message frames for messages to the DSP. Message
* frames will only be added to the free queue when a
* msg_queue object is created.
*/
INIT_LIST_HEAD(&msg_mgr_obj->msg_free_list);
INIT_LIST_HEAD(&msg_mgr_obj->msg_used_list);
spin_lock_init(&msg_mgr_obj->msg_mgr_lock);
/*
* Create an event to be used by bridge_msg_put() in waiting
* for an available free frame from the message manager.
*/
msg_mgr_obj->sync_event =
kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_mgr_obj->sync_event) {
kfree(msg_mgr_obj);
return -ENOMEM;
}
sync_init_event(msg_mgr_obj->sync_event);
*msg_man = msg_mgr_obj;
return status;
}
/*
* ======== bridge_msg_create_queue ========
* Create a msg_queue for sending/receiving messages to/from a node
* on the DSP.
*/
int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, struct msg_queue **msgq,
u32 msgq_id, u32 max_msgs, void *arg)
{
u32 i;
u32 num_allocated = 0;
struct msg_queue *msg_q;
int status = 0;
if (!hmsg_mgr || msgq == NULL)
return -EFAULT;
*msgq = NULL;
/* Allocate msg_queue object */
msg_q = kzalloc(sizeof(struct msg_queue), GFP_KERNEL);
if (!msg_q)
return -ENOMEM;
msg_q->max_msgs = max_msgs;
msg_q->msg_mgr = hmsg_mgr;
msg_q->arg = arg; /* Node handle */
msg_q->msgq_id = msgq_id; /* Node env (not valid yet) */
/* Queues of Message frames for messages from the DSP */
INIT_LIST_HEAD(&msg_q->msg_free_list);
INIT_LIST_HEAD(&msg_q->msg_used_list);
/* Create event that will be signalled when a message from
* the DSP is available. */
msg_q->sync_event = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_event) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_event);
/* Create a notification list for message ready notification. */
msg_q->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL);
if (!msg_q->ntfy_obj) {
status = -ENOMEM;
goto out_err;
}
ntfy_init(msg_q->ntfy_obj);
/* Create events that will be used to synchronize cleanup
* when the object is deleted. sync_done will be set to
* unblock threads in MSG_Put() or MSG_Get(). sync_done_ack
* will be set by the unblocked thread to signal that it
* is unblocked and will no longer reference the object. */
msg_q->sync_done = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_done) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_done);
msg_q->sync_done_ack = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_done_ack) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_done_ack);
/* Enter critical section */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* Initialize message frames and put in appropriate queues */
for (i = 0; i < max_msgs && !status; i++) {
status = add_new_msg(&hmsg_mgr->msg_free_list);
if (!status) {
num_allocated++;
status = add_new_msg(&msg_q->msg_free_list);
}
}
if (status) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
goto out_err;
}
list_add_tail(&msg_q->list_elem, &hmsg_mgr->queue_list);
*msgq = msg_q;
/* Signal that free frames are now available */
if (!list_empty(&hmsg_mgr->msg_free_list))
sync_set_event(hmsg_mgr->sync_event);
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
out_err:
delete_msg_queue(msg_q, num_allocated);
return status;
}
/*
* ======== bridge_msg_delete ========
* Delete a msg_ctrl manager allocated in bridge_msg_create().
*/
void bridge_msg_delete(struct msg_mgr *hmsg_mgr)
{
delete_msg_mgr(hmsg_mgr);
}
/*
* ======== bridge_msg_delete_queue ========
* Delete a msg_ctrl queue allocated in bridge_msg_create_queue.
*/
void bridge_msg_delete_queue(struct msg_queue *msg_queue_obj)
{
struct msg_mgr *hmsg_mgr;
u32 io_msg_pend;
if (!msg_queue_obj || !msg_queue_obj->msg_mgr)
return;
hmsg_mgr = msg_queue_obj->msg_mgr;
msg_queue_obj->done = true;
/* Unblock all threads blocked in MSG_Get() or MSG_Put(). */
io_msg_pend = msg_queue_obj->io_msg_pend;
while (io_msg_pend) {
/* Unblock thread */
sync_set_event(msg_queue_obj->sync_done);
/* Wait for acknowledgement */
sync_wait_on_event(msg_queue_obj->sync_done_ack, SYNC_INFINITE);
io_msg_pend = msg_queue_obj->io_msg_pend;
}
/* Remove message queue from hmsg_mgr->queue_list */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
list_del(&msg_queue_obj->list_elem);
/* Free the message queue object */
delete_msg_queue(msg_queue_obj, msg_queue_obj->max_msgs);
if (list_empty(&hmsg_mgr->msg_free_list))
sync_reset_event(hmsg_mgr->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
}
/*
* ======== bridge_msg_get ========
* Get a message from a msg_ctrl queue.
*/
int bridge_msg_get(struct msg_queue *msg_queue_obj,
struct dsp_msg *pmsg, u32 utimeout)
{
struct msg_frame *msg_frame_obj;
struct msg_mgr *hmsg_mgr;
struct sync_object *syncs[2];
u32 index;
int status = 0;
if (!msg_queue_obj || pmsg == NULL)
return -ENOMEM;
hmsg_mgr = msg_queue_obj->msg_mgr;
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* If a message is already there, get it */
if (!list_empty(&msg_queue_obj->msg_used_list)) {
msg_frame_obj = list_first_entry(&msg_queue_obj->msg_used_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
*pmsg = msg_frame_obj->msg_data.msg;
list_add_tail(&msg_frame_obj->list_elem,
&msg_queue_obj->msg_free_list);
if (list_empty(&msg_queue_obj->msg_used_list))
sync_reset_event(msg_queue_obj->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
}
if (msg_queue_obj->done) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EPERM;
}
msg_queue_obj->io_msg_pend++;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Wait til message is available, timeout, or done. We don't
* have to schedule the DPC, since the DSP will send messages
* when they are available.
*/
syncs[0] = msg_queue_obj->sync_event;
syncs[1] = msg_queue_obj->sync_done;
status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index);
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
if (msg_queue_obj->done) {
msg_queue_obj->io_msg_pend--;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Signal that we're not going to access msg_queue_obj
* anymore, so it can be deleted.
*/
sync_set_event(msg_queue_obj->sync_done_ack);
return -EPERM;
}
if (!status && !list_empty(&msg_queue_obj->msg_used_list)) {
/* Get msg from used list */
msg_frame_obj = list_first_entry(&msg_queue_obj->msg_used_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
/* Copy message into pmsg and put frame on the free list */
*pmsg = msg_frame_obj->msg_data.msg;
list_add_tail(&msg_frame_obj->list_elem,
&msg_queue_obj->msg_free_list);
}
msg_queue_obj->io_msg_pend--;
/* Reset the event if there are still queued messages */
if (!list_empty(&msg_queue_obj->msg_used_list))
sync_set_event(msg_queue_obj->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return status;
}
/*
* ======== bridge_msg_put ========
* Put a message onto a msg_ctrl queue.
*/
int bridge_msg_put(struct msg_queue *msg_queue_obj,
const struct dsp_msg *pmsg, u32 utimeout)
{
struct msg_frame *msg_frame_obj;
struct msg_mgr *hmsg_mgr;
struct sync_object *syncs[2];
u32 index;
int status;
if (!msg_queue_obj || !pmsg || !msg_queue_obj->msg_mgr)
return -EFAULT;
hmsg_mgr = msg_queue_obj->msg_mgr;
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* If a message frame is available, use it */
if (!list_empty(&hmsg_mgr->msg_free_list)) {
msg_frame_obj = list_first_entry(&hmsg_mgr->msg_free_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
msg_frame_obj->msg_data.msg = *pmsg;
msg_frame_obj->msg_data.msgq_id =
msg_queue_obj->msgq_id;
list_add_tail(&msg_frame_obj->list_elem,
&hmsg_mgr->msg_used_list);
hmsg_mgr->msgs_pending++;
if (list_empty(&hmsg_mgr->msg_free_list))
sync_reset_event(hmsg_mgr->sync_event);
/* Release critical section before scheduling DPC */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/* Schedule a DPC, to do the actual data transfer: */
iosm_schedule(hmsg_mgr->iomgr);
return 0;
}
if (msg_queue_obj->done) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EPERM;
}
msg_queue_obj->io_msg_pend++;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/* Wait til a free message frame is available, timeout, or done */
syncs[0] = hmsg_mgr->sync_event;
syncs[1] = msg_queue_obj->sync_done;
status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index);
if (status)
return status;
/* Enter critical section */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
if (msg_queue_obj->done) {
msg_queue_obj->io_msg_pend--;
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Signal that we're not going to access msg_queue_obj
* anymore, so it can be deleted.
*/
sync_set_event(msg_queue_obj->sync_done_ack);
return -EPERM;
}
if (list_empty(&hmsg_mgr->msg_free_list)) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EFAULT;
}
/* Get msg from free list */
msg_frame_obj = list_first_entry(&hmsg_mgr->msg_free_list,
struct msg_frame, list_elem);
/*
* Copy message into pmsg and put frame on the
* used list.
*/
list_del(&msg_frame_obj->list_elem);
msg_frame_obj->msg_data.msg = *pmsg;
msg_frame_obj->msg_data.msgq_id = msg_queue_obj->msgq_id;
list_add_tail(&msg_frame_obj->list_elem, &hmsg_mgr->msg_used_list);
hmsg_mgr->msgs_pending++;
/*
* Schedule a DPC, to do the actual
* data transfer.
*/
iosm_schedule(hmsg_mgr->iomgr);
msg_queue_obj->io_msg_pend--;
/* Reset event if there are still frames available */
if (!list_empty(&hmsg_mgr->msg_free_list))
sync_set_event(hmsg_mgr->sync_event);
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
}
/*
* ======== bridge_msg_register_notify ========
*/
int bridge_msg_register_notify(struct msg_queue *msg_queue_obj,
u32 event_mask, u32 notify_type,
struct dsp_notification *hnotification)
{
int status = 0;
if (!msg_queue_obj || !hnotification) {
status = -ENOMEM;
goto func_end;
}
if (!(event_mask == DSP_NODEMESSAGEREADY || event_mask == 0)) {
status = -EPERM;
goto func_end;
}
if (notify_type != DSP_SIGNALEVENT) {
status = -EBADR;
goto func_end;
}
if (event_mask)
status = ntfy_register(msg_queue_obj->ntfy_obj, hnotification,
event_mask, notify_type);
else
status = ntfy_unregister(msg_queue_obj->ntfy_obj,
hnotification);
if (status == -EINVAL) {
/* Not registered. Ok, since we couldn't have known. Node
* notifications are split between node state change handled
* by NODE, and message ready handled by msg_ctrl. */
status = 0;
}
func_end:
return status;
}
/*
* ======== bridge_msg_set_queue_id ========
*/
void bridge_msg_set_queue_id(struct msg_queue *msg_queue_obj, u32 msgq_id)
{
/*
* A message queue must be created when a node is allocated,
* so that node_register_notify() can be called before the node
* is created. Since we don't know the node environment until the
* node is created, we need this function to set msg_queue_obj->msgq_id
* to the node environment, after the node is created.
*/
if (msg_queue_obj)
msg_queue_obj->msgq_id = msgq_id;
}
/*
* ======== add_new_msg ========
* Must be called in message manager critical section.
*/
static int add_new_msg(struct list_head *msg_list)
{
struct msg_frame *pmsg;
pmsg = kzalloc(sizeof(struct msg_frame), GFP_ATOMIC);
if (!pmsg)
return -ENOMEM;
list_add_tail(&pmsg->list_elem, msg_list);
return 0;
}
/*
* ======== delete_msg_mgr ========
*/
static void delete_msg_mgr(struct msg_mgr *hmsg_mgr)
{
if (!hmsg_mgr)
return;
/* FIXME: free elements from queue_list? */
free_msg_list(&hmsg_mgr->msg_free_list);
free_msg_list(&hmsg_mgr->msg_used_list);
kfree(hmsg_mgr->sync_event);
kfree(hmsg_mgr);
}
/*
* ======== delete_msg_queue ========
*/
static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 num_to_dsp)
{
struct msg_mgr *hmsg_mgr;
struct msg_frame *pmsg, *tmp;
u32 i;
if (!msg_queue_obj || !msg_queue_obj->msg_mgr)
return;
hmsg_mgr = msg_queue_obj->msg_mgr;
/* Pull off num_to_dsp message frames from Msg manager and free */
i = 0;
list_for_each_entry_safe(pmsg, tmp, &hmsg_mgr->msg_free_list,
list_elem) {
list_del(&pmsg->list_elem);
kfree(pmsg);
if (i++ >= num_to_dsp)
break;
}
free_msg_list(&msg_queue_obj->msg_free_list);
free_msg_list(&msg_queue_obj->msg_used_list);
if (msg_queue_obj->ntfy_obj) {
ntfy_delete(msg_queue_obj->ntfy_obj);
kfree(msg_queue_obj->ntfy_obj);
}
kfree(msg_queue_obj->sync_event);
kfree(msg_queue_obj->sync_done);
kfree(msg_queue_obj->sync_done_ack);
kfree(msg_queue_obj);
}
/*
* ======== free_msg_list ========
*/
static void free_msg_list(struct list_head *msg_list)
{
struct msg_frame *pmsg, *tmp;
if (!msg_list)
return;
list_for_each_entry_safe(pmsg, tmp, msg_list, list_elem) {
list_del(&pmsg->list_elem);
kfree(pmsg);
}
}
| gpl-2.0 |
houzhenggang/bcm63xx-next | arch/arm/mach-at91/leds.c | 2734 | 1900 | /*
* LED driver for Atmel AT91-based boards.
*
* Copyright (C) SAN People (Pty) Ltd
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include "board.h"
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_NEW_LEDS)
/*
* New cross-platform LED support.
*/
static struct gpio_led_platform_data led_data;
static struct platform_device at91_gpio_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &led_data,
};
void __init at91_gpio_leds(struct gpio_led *leds, int nr)
{
int i;
if (!nr)
return;
for (i = 0; i < nr; i++)
at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
led_data.leds = leds;
led_data.num_leds = nr;
platform_device_register(&at91_gpio_leds_device);
}
#else
void __init at91_gpio_leds(struct gpio_led *leds, int nr) {}
#endif
/* ------------------------------------------------------------------------- */
#if defined (CONFIG_LEDS_ATMEL_PWM)
/*
* PWM Leds
*/
static struct gpio_led_platform_data pwm_led_data;
static struct platform_device at91_pwm_leds_device = {
.name = "leds-atmel-pwm",
.id = -1,
.dev.platform_data = &pwm_led_data,
};
void __init at91_pwm_leds(struct gpio_led *leds, int nr)
{
int i;
u32 pwm_mask = 0;
if (!nr)
return;
for (i = 0; i < nr; i++)
pwm_mask |= (1 << leds[i].gpio);
pwm_led_data.leds = leds;
pwm_led_data.num_leds = nr;
at91_add_device_pwm(pwm_mask);
platform_device_register(&at91_pwm_leds_device);
}
#else
void __init at91_pwm_leds(struct gpio_led *leds, int nr){}
#endif
| gpl-2.0 |
cmenard/T889_Kernel | arch/sh/boards/board-espt.c | 2734 | 2601 | /*
* Data Technology Inc. ESPT-GIGA board suport
*
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
* Copyright (C) 2008, 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <asm/machvec.h>
#include <asm/sizes.h>
#include <asm/sh_eth.h>
/* NOR Flash */
static struct mtd_partition espt_nor_flash_partitions[] = {
{
.name = "U-Boot",
.offset = 0,
.size = (2 * SZ_128K),
.mask_flags = MTD_WRITEABLE, /* Read-only */
}, {
.name = "Linux-Kernel",
.offset = MTDPART_OFS_APPEND,
.size = (20 * SZ_128K),
}, {
.name = "Root Filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data espt_nor_flash_data = {
.width = 2,
.parts = espt_nor_flash_partitions,
.nr_parts = ARRAY_SIZE(espt_nor_flash_partitions),
};
static struct resource espt_nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0,
.end = SZ_8M - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device espt_nor_flash_device = {
.name = "physmap-flash",
.resource = espt_nor_flash_resources,
.num_resources = ARRAY_SIZE(espt_nor_flash_resources),
.dev = {
.platform_data = &espt_nor_flash_data,
},
};
/* SH-Ether */
static struct resource sh_eth_resources[] = {
{
.start = 0xFEE00800, /* use eth1 */
.end = 0xFEE00F7C - 1,
.flags = IORESOURCE_MEM,
}, {
.start = 0xFEE01800, /* TSU */
.end = 0xFEE01FFF,
.flags = IORESOURCE_MEM,
}, {
.start = 57, /* irq number */
.flags = IORESOURCE_IRQ,
},
};
static struct sh_eth_plat_data sh7763_eth_pdata = {
.phy = 0,
.edmac_endian = EDMAC_LITTLE_ENDIAN,
.register_type = SH_ETH_REG_GIGABIT,
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct platform_device espt_eth_device = {
.name = "sh-eth",
.resource = sh_eth_resources,
.num_resources = ARRAY_SIZE(sh_eth_resources),
.dev = {
.platform_data = &sh7763_eth_pdata,
},
};
static struct platform_device *espt_devices[] __initdata = {
&espt_nor_flash_device,
&espt_eth_device,
};
static int __init espt_devices_setup(void)
{
return platform_add_devices(espt_devices,
ARRAY_SIZE(espt_devices));
}
device_initcall(espt_devices_setup);
static struct sh_machine_vector mv_espt __initmv = {
.mv_name = "ESPT-GIGA",
};
| gpl-2.0 |
TheYorickable/tf300t_jb_kernel | drivers/scsi/lpfc/lpfc_scsi.c | 2734 | 120221 | /*******************************************************************
* This file is part of the Emulex Linux Device Driver for *
* Fibre Channel Host Bus Adapters. *
* Copyright (C) 2004-2011 Emulex. All rights reserved. *
* EMULEX and SLI are trademarks of Emulex. *
* www.emulex.com *
* Portions Copyright (C) 2004-2005 Christoph Hellwig *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of version 2 of the GNU General *
* Public License as published by the Free Software Foundation. *
* This program is distributed in the hope that it will be useful. *
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
* TO BE LEGALLY INVALID. See the GNU General Public License for *
* more details, a copy of which can be found in the file COPYING *
* included with this package. *
*******************************************************************/
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/unaligned.h>
#include <scsi/scsi.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_eh.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_tcq.h>
#include <scsi/scsi_transport_fc.h>
#include "lpfc_version.h"
#include "lpfc_hw4.h"
#include "lpfc_hw.h"
#include "lpfc_sli.h"
#include "lpfc_sli4.h"
#include "lpfc_nl.h"
#include "lpfc_disc.h"
#include "lpfc_scsi.h"
#include "lpfc.h"
#include "lpfc_logmsg.h"
#include "lpfc_crtn.h"
#include "lpfc_vport.h"
#define LPFC_RESET_WAIT 2
#define LPFC_ABORT_WAIT 2
int _dump_buf_done;
static char *dif_op_str[] = {
"SCSI_PROT_NORMAL",
"SCSI_PROT_READ_INSERT",
"SCSI_PROT_WRITE_STRIP",
"SCSI_PROT_READ_STRIP",
"SCSI_PROT_WRITE_INSERT",
"SCSI_PROT_READ_PASS",
"SCSI_PROT_WRITE_PASS",
};
static void
lpfc_release_scsi_buf_s4(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb);
static void
lpfc_release_scsi_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb);
static void
lpfc_debug_save_data(struct lpfc_hba *phba, struct scsi_cmnd *cmnd)
{
void *src, *dst;
struct scatterlist *sgde = scsi_sglist(cmnd);
if (!_dump_buf_data) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9050 BLKGRD: ERROR %s _dump_buf_data is NULL\n",
__func__);
return;
}
if (!sgde) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9051 BLKGRD: ERROR: data scatterlist is null\n");
return;
}
dst = (void *) _dump_buf_data;
while (sgde) {
src = sg_virt(sgde);
memcpy(dst, src, sgde->length);
dst += sgde->length;
sgde = sg_next(sgde);
}
}
static void
lpfc_debug_save_dif(struct lpfc_hba *phba, struct scsi_cmnd *cmnd)
{
void *src, *dst;
struct scatterlist *sgde = scsi_prot_sglist(cmnd);
if (!_dump_buf_dif) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9052 BLKGRD: ERROR %s _dump_buf_data is NULL\n",
__func__);
return;
}
if (!sgde) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9053 BLKGRD: ERROR: prot scatterlist is null\n");
return;
}
dst = _dump_buf_dif;
while (sgde) {
src = sg_virt(sgde);
memcpy(dst, src, sgde->length);
dst += sgde->length;
sgde = sg_next(sgde);
}
}
/**
* lpfc_sli4_set_rsp_sgl_last - Set the last bit in the response sge.
* @phba: Pointer to HBA object.
* @lpfc_cmd: lpfc scsi command object pointer.
*
* This function is called from the lpfc_prep_task_mgmt_cmd function to
* set the last bit in the response sge entry.
**/
static void
lpfc_sli4_set_rsp_sgl_last(struct lpfc_hba *phba,
struct lpfc_scsi_buf *lpfc_cmd)
{
struct sli4_sge *sgl = (struct sli4_sge *)lpfc_cmd->fcp_bpl;
if (sgl) {
sgl += 1;
sgl->word2 = le32_to_cpu(sgl->word2);
bf_set(lpfc_sli4_sge_last, sgl, 1);
sgl->word2 = cpu_to_le32(sgl->word2);
}
}
/**
* lpfc_update_stats - Update statistical data for the command completion
* @phba: Pointer to HBA object.
* @lpfc_cmd: lpfc scsi command object pointer.
*
* This function is called when there is a command completion and this
* function updates the statistical data for the command completion.
**/
static void
lpfc_update_stats(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd)
{
struct lpfc_rport_data *rdata = lpfc_cmd->rdata;
struct lpfc_nodelist *pnode = rdata->pnode;
struct scsi_cmnd *cmd = lpfc_cmd->pCmd;
unsigned long flags;
struct Scsi_Host *shost = cmd->device->host;
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
unsigned long latency;
int i;
if (cmd->result)
return;
latency = jiffies_to_msecs((long)jiffies - (long)lpfc_cmd->start_time);
spin_lock_irqsave(shost->host_lock, flags);
if (!vport->stat_data_enabled ||
vport->stat_data_blocked ||
!pnode ||
!pnode->lat_data ||
(phba->bucket_type == LPFC_NO_BUCKET)) {
spin_unlock_irqrestore(shost->host_lock, flags);
return;
}
if (phba->bucket_type == LPFC_LINEAR_BUCKET) {
i = (latency + phba->bucket_step - 1 - phba->bucket_base)/
phba->bucket_step;
/* check array subscript bounds */
if (i < 0)
i = 0;
else if (i >= LPFC_MAX_BUCKET_COUNT)
i = LPFC_MAX_BUCKET_COUNT - 1;
} else {
for (i = 0; i < LPFC_MAX_BUCKET_COUNT-1; i++)
if (latency <= (phba->bucket_base +
((1<<i)*phba->bucket_step)))
break;
}
pnode->lat_data[i].cmd_count++;
spin_unlock_irqrestore(shost->host_lock, flags);
}
/**
* lpfc_send_sdev_queuedepth_change_event - Posts a queuedepth change event
* @phba: Pointer to HBA context object.
* @vport: Pointer to vport object.
* @ndlp: Pointer to FC node associated with the target.
* @lun: Lun number of the scsi device.
* @old_val: Old value of the queue depth.
* @new_val: New value of the queue depth.
*
* This function sends an event to the mgmt application indicating
* there is a change in the scsi device queue depth.
**/
static void
lpfc_send_sdev_queuedepth_change_event(struct lpfc_hba *phba,
struct lpfc_vport *vport,
struct lpfc_nodelist *ndlp,
uint32_t lun,
uint32_t old_val,
uint32_t new_val)
{
struct lpfc_fast_path_event *fast_path_evt;
unsigned long flags;
fast_path_evt = lpfc_alloc_fast_evt(phba);
if (!fast_path_evt)
return;
fast_path_evt->un.queue_depth_evt.scsi_event.event_type =
FC_REG_SCSI_EVENT;
fast_path_evt->un.queue_depth_evt.scsi_event.subcategory =
LPFC_EVENT_VARQUEDEPTH;
/* Report all luns with change in queue depth */
fast_path_evt->un.queue_depth_evt.scsi_event.lun = lun;
if (ndlp && NLP_CHK_NODE_ACT(ndlp)) {
memcpy(&fast_path_evt->un.queue_depth_evt.scsi_event.wwpn,
&ndlp->nlp_portname, sizeof(struct lpfc_name));
memcpy(&fast_path_evt->un.queue_depth_evt.scsi_event.wwnn,
&ndlp->nlp_nodename, sizeof(struct lpfc_name));
}
fast_path_evt->un.queue_depth_evt.oldval = old_val;
fast_path_evt->un.queue_depth_evt.newval = new_val;
fast_path_evt->vport = vport;
fast_path_evt->work_evt.evt = LPFC_EVT_FASTPATH_MGMT_EVT;
spin_lock_irqsave(&phba->hbalock, flags);
list_add_tail(&fast_path_evt->work_evt.evt_listp, &phba->work_list);
spin_unlock_irqrestore(&phba->hbalock, flags);
lpfc_worker_wake_up(phba);
return;
}
/**
* lpfc_change_queue_depth - Alter scsi device queue depth
* @sdev: Pointer the scsi device on which to change the queue depth.
* @qdepth: New queue depth to set the sdev to.
* @reason: The reason for the queue depth change.
*
* This function is called by the midlayer and the LLD to alter the queue
* depth for a scsi device. This function sets the queue depth to the new
* value and sends an event out to log the queue depth change.
**/
int
lpfc_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
{
struct lpfc_vport *vport = (struct lpfc_vport *) sdev->host->hostdata;
struct lpfc_hba *phba = vport->phba;
struct lpfc_rport_data *rdata;
unsigned long new_queue_depth, old_queue_depth;
old_queue_depth = sdev->queue_depth;
scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
new_queue_depth = sdev->queue_depth;
rdata = sdev->hostdata;
if (rdata)
lpfc_send_sdev_queuedepth_change_event(phba, vport,
rdata->pnode, sdev->lun,
old_queue_depth,
new_queue_depth);
return sdev->queue_depth;
}
/**
* lpfc_rampdown_queue_depth - Post RAMP_DOWN_QUEUE event to worker thread
* @phba: The Hba for which this call is being executed.
*
* This routine is called when there is resource error in driver or firmware.
* This routine posts WORKER_RAMP_DOWN_QUEUE event for @phba. This routine
* posts at most 1 event each second. This routine wakes up worker thread of
* @phba to process WORKER_RAM_DOWN_EVENT event.
*
* This routine should be called with no lock held.
**/
void
lpfc_rampdown_queue_depth(struct lpfc_hba *phba)
{
unsigned long flags;
uint32_t evt_posted;
spin_lock_irqsave(&phba->hbalock, flags);
atomic_inc(&phba->num_rsrc_err);
phba->last_rsrc_error_time = jiffies;
if ((phba->last_ramp_down_time + QUEUE_RAMP_DOWN_INTERVAL) > jiffies) {
spin_unlock_irqrestore(&phba->hbalock, flags);
return;
}
phba->last_ramp_down_time = jiffies;
spin_unlock_irqrestore(&phba->hbalock, flags);
spin_lock_irqsave(&phba->pport->work_port_lock, flags);
evt_posted = phba->pport->work_port_events & WORKER_RAMP_DOWN_QUEUE;
if (!evt_posted)
phba->pport->work_port_events |= WORKER_RAMP_DOWN_QUEUE;
spin_unlock_irqrestore(&phba->pport->work_port_lock, flags);
if (!evt_posted)
lpfc_worker_wake_up(phba);
return;
}
/**
* lpfc_rampup_queue_depth - Post RAMP_UP_QUEUE event for worker thread
* @phba: The Hba for which this call is being executed.
*
* This routine post WORKER_RAMP_UP_QUEUE event for @phba vport. This routine
* post at most 1 event every 5 minute after last_ramp_up_time or
* last_rsrc_error_time. This routine wakes up worker thread of @phba
* to process WORKER_RAM_DOWN_EVENT event.
*
* This routine should be called with no lock held.
**/
static inline void
lpfc_rampup_queue_depth(struct lpfc_vport *vport,
uint32_t queue_depth)
{
unsigned long flags;
struct lpfc_hba *phba = vport->phba;
uint32_t evt_posted;
atomic_inc(&phba->num_cmd_success);
if (vport->cfg_lun_queue_depth <= queue_depth)
return;
spin_lock_irqsave(&phba->hbalock, flags);
if (time_before(jiffies,
phba->last_ramp_up_time + QUEUE_RAMP_UP_INTERVAL) ||
time_before(jiffies,
phba->last_rsrc_error_time + QUEUE_RAMP_UP_INTERVAL)) {
spin_unlock_irqrestore(&phba->hbalock, flags);
return;
}
phba->last_ramp_up_time = jiffies;
spin_unlock_irqrestore(&phba->hbalock, flags);
spin_lock_irqsave(&phba->pport->work_port_lock, flags);
evt_posted = phba->pport->work_port_events & WORKER_RAMP_UP_QUEUE;
if (!evt_posted)
phba->pport->work_port_events |= WORKER_RAMP_UP_QUEUE;
spin_unlock_irqrestore(&phba->pport->work_port_lock, flags);
if (!evt_posted)
lpfc_worker_wake_up(phba);
return;
}
/**
* lpfc_ramp_down_queue_handler - WORKER_RAMP_DOWN_QUEUE event handler
* @phba: The Hba for which this call is being executed.
*
* This routine is called to process WORKER_RAMP_DOWN_QUEUE event for worker
* thread.This routine reduces queue depth for all scsi device on each vport
* associated with @phba.
**/
void
lpfc_ramp_down_queue_handler(struct lpfc_hba *phba)
{
struct lpfc_vport **vports;
struct Scsi_Host *shost;
struct scsi_device *sdev;
unsigned long new_queue_depth;
unsigned long num_rsrc_err, num_cmd_success;
int i;
num_rsrc_err = atomic_read(&phba->num_rsrc_err);
num_cmd_success = atomic_read(&phba->num_cmd_success);
vports = lpfc_create_vport_work_array(phba);
if (vports != NULL)
for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
shost = lpfc_shost_from_vport(vports[i]);
shost_for_each_device(sdev, shost) {
new_queue_depth =
sdev->queue_depth * num_rsrc_err /
(num_rsrc_err + num_cmd_success);
if (!new_queue_depth)
new_queue_depth = sdev->queue_depth - 1;
else
new_queue_depth = sdev->queue_depth -
new_queue_depth;
lpfc_change_queue_depth(sdev, new_queue_depth,
SCSI_QDEPTH_DEFAULT);
}
}
lpfc_destroy_vport_work_array(phba, vports);
atomic_set(&phba->num_rsrc_err, 0);
atomic_set(&phba->num_cmd_success, 0);
}
/**
* lpfc_ramp_up_queue_handler - WORKER_RAMP_UP_QUEUE event handler
* @phba: The Hba for which this call is being executed.
*
* This routine is called to process WORKER_RAMP_UP_QUEUE event for worker
* thread.This routine increases queue depth for all scsi device on each vport
* associated with @phba by 1. This routine also sets @phba num_rsrc_err and
* num_cmd_success to zero.
**/
void
lpfc_ramp_up_queue_handler(struct lpfc_hba *phba)
{
struct lpfc_vport **vports;
struct Scsi_Host *shost;
struct scsi_device *sdev;
int i;
vports = lpfc_create_vport_work_array(phba);
if (vports != NULL)
for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
shost = lpfc_shost_from_vport(vports[i]);
shost_for_each_device(sdev, shost) {
if (vports[i]->cfg_lun_queue_depth <=
sdev->queue_depth)
continue;
lpfc_change_queue_depth(sdev,
sdev->queue_depth+1,
SCSI_QDEPTH_RAMP_UP);
}
}
lpfc_destroy_vport_work_array(phba, vports);
atomic_set(&phba->num_rsrc_err, 0);
atomic_set(&phba->num_cmd_success, 0);
}
/**
* lpfc_scsi_dev_block - set all scsi hosts to block state
* @phba: Pointer to HBA context object.
*
* This function walks vport list and set each SCSI host to block state
* by invoking fc_remote_port_delete() routine. This function is invoked
* with EEH when device's PCI slot has been permanently disabled.
**/
void
lpfc_scsi_dev_block(struct lpfc_hba *phba)
{
struct lpfc_vport **vports;
struct Scsi_Host *shost;
struct scsi_device *sdev;
struct fc_rport *rport;
int i;
vports = lpfc_create_vport_work_array(phba);
if (vports != NULL)
for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
shost = lpfc_shost_from_vport(vports[i]);
shost_for_each_device(sdev, shost) {
rport = starget_to_rport(scsi_target(sdev));
fc_remote_port_delete(rport);
}
}
lpfc_destroy_vport_work_array(phba, vports);
}
/**
* lpfc_new_scsi_buf_s3 - Scsi buffer allocator for HBA with SLI3 IF spec
* @vport: The virtual port for which this call being executed.
* @num_to_allocate: The requested number of buffers to allocate.
*
* This routine allocates a scsi buffer for device with SLI-3 interface spec,
* the scsi buffer contains all the necessary information needed to initiate
* a SCSI I/O. The non-DMAable buffer region contains information to build
* the IOCB. The DMAable region contains memory for the FCP CMND, FCP RSP,
* and the initial BPL. In addition to allocating memory, the FCP CMND and
* FCP RSP BDEs are setup in the BPL and the BPL BDE is setup in the IOCB.
*
* Return codes:
* int - number of scsi buffers that were allocated.
* 0 = failure, less than num_to_alloc is a partial failure.
**/
static int
lpfc_new_scsi_buf_s3(struct lpfc_vport *vport, int num_to_alloc)
{
struct lpfc_hba *phba = vport->phba;
struct lpfc_scsi_buf *psb;
struct ulp_bde64 *bpl;
IOCB_t *iocb;
dma_addr_t pdma_phys_fcp_cmd;
dma_addr_t pdma_phys_fcp_rsp;
dma_addr_t pdma_phys_bpl;
uint16_t iotag;
int bcnt;
for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
psb = kzalloc(sizeof(struct lpfc_scsi_buf), GFP_KERNEL);
if (!psb)
break;
/*
* Get memory from the pci pool to map the virt space to pci
* bus space for an I/O. The DMA buffer includes space for the
* struct fcp_cmnd, struct fcp_rsp and the number of bde's
* necessary to support the sg_tablesize.
*/
psb->data = pci_pool_alloc(phba->lpfc_scsi_dma_buf_pool,
GFP_KERNEL, &psb->dma_handle);
if (!psb->data) {
kfree(psb);
break;
}
/* Initialize virtual ptrs to dma_buf region. */
memset(psb->data, 0, phba->cfg_sg_dma_buf_size);
/* Allocate iotag for psb->cur_iocbq. */
iotag = lpfc_sli_next_iotag(phba, &psb->cur_iocbq);
if (iotag == 0) {
pci_pool_free(phba->lpfc_scsi_dma_buf_pool,
psb->data, psb->dma_handle);
kfree(psb);
break;
}
psb->cur_iocbq.iocb_flag |= LPFC_IO_FCP;
psb->fcp_cmnd = psb->data;
psb->fcp_rsp = psb->data + sizeof(struct fcp_cmnd);
psb->fcp_bpl = psb->data + sizeof(struct fcp_cmnd) +
sizeof(struct fcp_rsp);
/* Initialize local short-hand pointers. */
bpl = psb->fcp_bpl;
pdma_phys_fcp_cmd = psb->dma_handle;
pdma_phys_fcp_rsp = psb->dma_handle + sizeof(struct fcp_cmnd);
pdma_phys_bpl = psb->dma_handle + sizeof(struct fcp_cmnd) +
sizeof(struct fcp_rsp);
/*
* The first two bdes are the FCP_CMD and FCP_RSP. The balance
* are sg list bdes. Initialize the first two and leave the
* rest for queuecommand.
*/
bpl[0].addrHigh = le32_to_cpu(putPaddrHigh(pdma_phys_fcp_cmd));
bpl[0].addrLow = le32_to_cpu(putPaddrLow(pdma_phys_fcp_cmd));
bpl[0].tus.f.bdeSize = sizeof(struct fcp_cmnd);
bpl[0].tus.f.bdeFlags = BUFF_TYPE_BDE_64;
bpl[0].tus.w = le32_to_cpu(bpl[0].tus.w);
/* Setup the physical region for the FCP RSP */
bpl[1].addrHigh = le32_to_cpu(putPaddrHigh(pdma_phys_fcp_rsp));
bpl[1].addrLow = le32_to_cpu(putPaddrLow(pdma_phys_fcp_rsp));
bpl[1].tus.f.bdeSize = sizeof(struct fcp_rsp);
bpl[1].tus.f.bdeFlags = BUFF_TYPE_BDE_64;
bpl[1].tus.w = le32_to_cpu(bpl[1].tus.w);
/*
* Since the IOCB for the FCP I/O is built into this
* lpfc_scsi_buf, initialize it with all known data now.
*/
iocb = &psb->cur_iocbq.iocb;
iocb->un.fcpi64.bdl.ulpIoTag32 = 0;
if ((phba->sli_rev == 3) &&
!(phba->sli3_options & LPFC_SLI3_BG_ENABLED)) {
/* fill in immediate fcp command BDE */
iocb->un.fcpi64.bdl.bdeFlags = BUFF_TYPE_BDE_IMMED;
iocb->un.fcpi64.bdl.bdeSize = sizeof(struct fcp_cmnd);
iocb->un.fcpi64.bdl.addrLow = offsetof(IOCB_t,
unsli3.fcp_ext.icd);
iocb->un.fcpi64.bdl.addrHigh = 0;
iocb->ulpBdeCount = 0;
iocb->ulpLe = 0;
/* fill in response BDE */
iocb->unsli3.fcp_ext.rbde.tus.f.bdeFlags =
BUFF_TYPE_BDE_64;
iocb->unsli3.fcp_ext.rbde.tus.f.bdeSize =
sizeof(struct fcp_rsp);
iocb->unsli3.fcp_ext.rbde.addrLow =
putPaddrLow(pdma_phys_fcp_rsp);
iocb->unsli3.fcp_ext.rbde.addrHigh =
putPaddrHigh(pdma_phys_fcp_rsp);
} else {
iocb->un.fcpi64.bdl.bdeFlags = BUFF_TYPE_BLP_64;
iocb->un.fcpi64.bdl.bdeSize =
(2 * sizeof(struct ulp_bde64));
iocb->un.fcpi64.bdl.addrLow =
putPaddrLow(pdma_phys_bpl);
iocb->un.fcpi64.bdl.addrHigh =
putPaddrHigh(pdma_phys_bpl);
iocb->ulpBdeCount = 1;
iocb->ulpLe = 1;
}
iocb->ulpClass = CLASS3;
psb->status = IOSTAT_SUCCESS;
/* Put it back into the SCSI buffer list */
psb->cur_iocbq.context1 = psb;
lpfc_release_scsi_buf_s3(phba, psb);
}
return bcnt;
}
/**
* lpfc_sli4_vport_delete_fcp_xri_aborted -Remove all ndlp references for vport
* @vport: pointer to lpfc vport data structure.
*
* This routine is invoked by the vport cleanup for deletions and the cleanup
* for an ndlp on removal.
**/
void
lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *vport)
{
struct lpfc_hba *phba = vport->phba;
struct lpfc_scsi_buf *psb, *next_psb;
unsigned long iflag = 0;
spin_lock_irqsave(&phba->hbalock, iflag);
spin_lock(&phba->sli4_hba.abts_scsi_buf_list_lock);
list_for_each_entry_safe(psb, next_psb,
&phba->sli4_hba.lpfc_abts_scsi_buf_list, list) {
if (psb->rdata && psb->rdata->pnode
&& psb->rdata->pnode->vport == vport)
psb->rdata = NULL;
}
spin_unlock(&phba->sli4_hba.abts_scsi_buf_list_lock);
spin_unlock_irqrestore(&phba->hbalock, iflag);
}
/**
* lpfc_sli4_fcp_xri_aborted - Fast-path process of fcp xri abort
* @phba: pointer to lpfc hba data structure.
* @axri: pointer to the fcp xri abort wcqe structure.
*
* This routine is invoked by the worker thread to process a SLI4 fast-path
* FCP aborted xri.
**/
void
lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *phba,
struct sli4_wcqe_xri_aborted *axri)
{
uint16_t xri = bf_get(lpfc_wcqe_xa_xri, axri);
uint16_t rxid = bf_get(lpfc_wcqe_xa_remote_xid, axri);
struct lpfc_scsi_buf *psb, *next_psb;
unsigned long iflag = 0;
struct lpfc_iocbq *iocbq;
int i;
struct lpfc_nodelist *ndlp;
int rrq_empty = 0;
struct lpfc_sli_ring *pring = &phba->sli.ring[LPFC_ELS_RING];
spin_lock_irqsave(&phba->hbalock, iflag);
spin_lock(&phba->sli4_hba.abts_scsi_buf_list_lock);
list_for_each_entry_safe(psb, next_psb,
&phba->sli4_hba.lpfc_abts_scsi_buf_list, list) {
if (psb->cur_iocbq.sli4_xritag == xri) {
list_del(&psb->list);
psb->exch_busy = 0;
psb->status = IOSTAT_SUCCESS;
spin_unlock(
&phba->sli4_hba.abts_scsi_buf_list_lock);
if (psb->rdata && psb->rdata->pnode)
ndlp = psb->rdata->pnode;
else
ndlp = NULL;
rrq_empty = list_empty(&phba->active_rrq_list);
spin_unlock_irqrestore(&phba->hbalock, iflag);
if (ndlp)
lpfc_set_rrq_active(phba, ndlp, xri, rxid, 1);
lpfc_release_scsi_buf_s4(phba, psb);
if (rrq_empty)
lpfc_worker_wake_up(phba);
return;
}
}
spin_unlock(&phba->sli4_hba.abts_scsi_buf_list_lock);
for (i = 1; i <= phba->sli.last_iotag; i++) {
iocbq = phba->sli.iocbq_lookup[i];
if (!(iocbq->iocb_flag & LPFC_IO_FCP) ||
(iocbq->iocb_flag & LPFC_IO_LIBDFC))
continue;
if (iocbq->sli4_xritag != xri)
continue;
psb = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq);
psb->exch_busy = 0;
spin_unlock_irqrestore(&phba->hbalock, iflag);
if (pring->txq_cnt)
lpfc_worker_wake_up(phba);
return;
}
spin_unlock_irqrestore(&phba->hbalock, iflag);
}
/**
* lpfc_sli4_repost_scsi_sgl_list - Repsot the Scsi buffers sgl pages as block
* @phba: pointer to lpfc hba data structure.
*
* This routine walks the list of scsi buffers that have been allocated and
* repost them to the HBA by using SGL block post. This is needed after a
* pci_function_reset/warm_start or start. The lpfc_hba_down_post_s4 routine
* is responsible for moving all scsi buffers on the lpfc_abts_scsi_sgl_list
* to the lpfc_scsi_buf_list. If the repost fails, reject all scsi buffers.
*
* Returns: 0 = success, non-zero failure.
**/
int
lpfc_sli4_repost_scsi_sgl_list(struct lpfc_hba *phba)
{
struct lpfc_scsi_buf *psb;
int index, status, bcnt = 0, rcnt = 0, rc = 0;
LIST_HEAD(sblist);
for (index = 0; index < phba->sli4_hba.scsi_xri_cnt; index++) {
psb = phba->sli4_hba.lpfc_scsi_psb_array[index];
if (psb) {
/* Remove from SCSI buffer list */
list_del(&psb->list);
/* Add it to a local SCSI buffer list */
list_add_tail(&psb->list, &sblist);
if (++rcnt == LPFC_NEMBED_MBOX_SGL_CNT) {
bcnt = rcnt;
rcnt = 0;
}
} else
/* A hole present in the XRI array, need to skip */
bcnt = rcnt;
if (index == phba->sli4_hba.scsi_xri_cnt - 1)
/* End of XRI array for SCSI buffer, complete */
bcnt = rcnt;
/* Continue until collect up to a nembed page worth of sgls */
if (bcnt == 0)
continue;
/* Now, post the SCSI buffer list sgls as a block */
if (!phba->sli4_hba.extents_in_use)
status = lpfc_sli4_post_scsi_sgl_block(phba,
&sblist,
bcnt);
else
status = lpfc_sli4_post_scsi_sgl_blk_ext(phba,
&sblist,
bcnt);
/* Reset SCSI buffer count for next round of posting */
bcnt = 0;
while (!list_empty(&sblist)) {
list_remove_head(&sblist, psb, struct lpfc_scsi_buf,
list);
if (status) {
/* Put this back on the abort scsi list */
psb->exch_busy = 1;
rc++;
} else {
psb->exch_busy = 0;
psb->status = IOSTAT_SUCCESS;
}
/* Put it back into the SCSI buffer list */
lpfc_release_scsi_buf_s4(phba, psb);
}
}
return rc;
}
/**
* lpfc_new_scsi_buf_s4 - Scsi buffer allocator for HBA with SLI4 IF spec
* @vport: The virtual port for which this call being executed.
* @num_to_allocate: The requested number of buffers to allocate.
*
* This routine allocates a scsi buffer for device with SLI-4 interface spec,
* the scsi buffer contains all the necessary information needed to initiate
* a SCSI I/O.
*
* Return codes:
* int - number of scsi buffers that were allocated.
* 0 = failure, less than num_to_alloc is a partial failure.
**/
static int
lpfc_new_scsi_buf_s4(struct lpfc_vport *vport, int num_to_alloc)
{
struct lpfc_hba *phba = vport->phba;
struct lpfc_scsi_buf *psb;
struct sli4_sge *sgl;
IOCB_t *iocb;
dma_addr_t pdma_phys_fcp_cmd;
dma_addr_t pdma_phys_fcp_rsp;
dma_addr_t pdma_phys_bpl, pdma_phys_bpl1;
uint16_t iotag, last_xritag = NO_XRI, lxri = 0;
int status = 0, index;
int bcnt;
int non_sequential_xri = 0;
LIST_HEAD(sblist);
for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
psb = kzalloc(sizeof(struct lpfc_scsi_buf), GFP_KERNEL);
if (!psb)
break;
/*
* Get memory from the pci pool to map the virt space to pci bus
* space for an I/O. The DMA buffer includes space for the
* struct fcp_cmnd, struct fcp_rsp and the number of bde's
* necessary to support the sg_tablesize.
*/
psb->data = pci_pool_alloc(phba->lpfc_scsi_dma_buf_pool,
GFP_KERNEL, &psb->dma_handle);
if (!psb->data) {
kfree(psb);
break;
}
/* Initialize virtual ptrs to dma_buf region. */
memset(psb->data, 0, phba->cfg_sg_dma_buf_size);
/* Allocate iotag for psb->cur_iocbq. */
iotag = lpfc_sli_next_iotag(phba, &psb->cur_iocbq);
if (iotag == 0) {
pci_pool_free(phba->lpfc_scsi_dma_buf_pool,
psb->data, psb->dma_handle);
kfree(psb);
break;
}
lxri = lpfc_sli4_next_xritag(phba);
if (lxri == NO_XRI) {
pci_pool_free(phba->lpfc_scsi_dma_buf_pool,
psb->data, psb->dma_handle);
kfree(psb);
break;
}
psb->cur_iocbq.sli4_lxritag = lxri;
psb->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
if (last_xritag != NO_XRI
&& psb->cur_iocbq.sli4_xritag != (last_xritag+1)) {
non_sequential_xri = 1;
} else
list_add_tail(&psb->list, &sblist);
last_xritag = psb->cur_iocbq.sli4_xritag;
index = phba->sli4_hba.scsi_xri_cnt++;
psb->cur_iocbq.iocb_flag |= LPFC_IO_FCP;
psb->fcp_bpl = psb->data;
psb->fcp_cmnd = (psb->data + phba->cfg_sg_dma_buf_size)
- (sizeof(struct fcp_cmnd) + sizeof(struct fcp_rsp));
psb->fcp_rsp = (struct fcp_rsp *)((uint8_t *)psb->fcp_cmnd +
sizeof(struct fcp_cmnd));
/* Initialize local short-hand pointers. */
sgl = (struct sli4_sge *)psb->fcp_bpl;
pdma_phys_bpl = psb->dma_handle;
pdma_phys_fcp_cmd =
(psb->dma_handle + phba->cfg_sg_dma_buf_size)
- (sizeof(struct fcp_cmnd) + sizeof(struct fcp_rsp));
pdma_phys_fcp_rsp = pdma_phys_fcp_cmd + sizeof(struct fcp_cmnd);
/*
* The first two bdes are the FCP_CMD and FCP_RSP. The balance
* are sg list bdes. Initialize the first two and leave the
* rest for queuecommand.
*/
sgl->addr_hi = cpu_to_le32(putPaddrHigh(pdma_phys_fcp_cmd));
sgl->addr_lo = cpu_to_le32(putPaddrLow(pdma_phys_fcp_cmd));
sgl->word2 = le32_to_cpu(sgl->word2);
bf_set(lpfc_sli4_sge_last, sgl, 0);
sgl->word2 = cpu_to_le32(sgl->word2);
sgl->sge_len = cpu_to_le32(sizeof(struct fcp_cmnd));
sgl++;
/* Setup the physical region for the FCP RSP */
sgl->addr_hi = cpu_to_le32(putPaddrHigh(pdma_phys_fcp_rsp));
sgl->addr_lo = cpu_to_le32(putPaddrLow(pdma_phys_fcp_rsp));
sgl->word2 = le32_to_cpu(sgl->word2);
bf_set(lpfc_sli4_sge_last, sgl, 1);
sgl->word2 = cpu_to_le32(sgl->word2);
sgl->sge_len = cpu_to_le32(sizeof(struct fcp_rsp));
/*
* Since the IOCB for the FCP I/O is built into this
* lpfc_scsi_buf, initialize it with all known data now.
*/
iocb = &psb->cur_iocbq.iocb;
iocb->un.fcpi64.bdl.ulpIoTag32 = 0;
iocb->un.fcpi64.bdl.bdeFlags = BUFF_TYPE_BDE_64;
/* setting the BLP size to 2 * sizeof BDE may not be correct.
* We are setting the bpl to point to out sgl. An sgl's
* entries are 16 bytes, a bpl entries are 12 bytes.
*/
iocb->un.fcpi64.bdl.bdeSize = sizeof(struct fcp_cmnd);
iocb->un.fcpi64.bdl.addrLow = putPaddrLow(pdma_phys_fcp_cmd);
iocb->un.fcpi64.bdl.addrHigh = putPaddrHigh(pdma_phys_fcp_cmd);
iocb->ulpBdeCount = 1;
iocb->ulpLe = 1;
iocb->ulpClass = CLASS3;
psb->cur_iocbq.context1 = psb;
if (phba->cfg_sg_dma_buf_size > SGL_PAGE_SIZE)
pdma_phys_bpl1 = pdma_phys_bpl + SGL_PAGE_SIZE;
else
pdma_phys_bpl1 = 0;
psb->dma_phys_bpl = pdma_phys_bpl;
phba->sli4_hba.lpfc_scsi_psb_array[index] = psb;
if (non_sequential_xri) {
status = lpfc_sli4_post_sgl(phba, pdma_phys_bpl,
pdma_phys_bpl1,
psb->cur_iocbq.sli4_xritag);
if (status) {
/* Put this back on the abort scsi list */
psb->exch_busy = 1;
} else {
psb->exch_busy = 0;
psb->status = IOSTAT_SUCCESS;
}
/* Put it back into the SCSI buffer list */
lpfc_release_scsi_buf_s4(phba, psb);
break;
}
}
if (bcnt) {
if (!phba->sli4_hba.extents_in_use)
status = lpfc_sli4_post_scsi_sgl_block(phba,
&sblist,
bcnt);
else
status = lpfc_sli4_post_scsi_sgl_blk_ext(phba,
&sblist,
bcnt);
if (status) {
lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
"3021 SCSI SGL post error %d\n",
status);
bcnt = 0;
}
/* Reset SCSI buffer count for next round of posting */
while (!list_empty(&sblist)) {
list_remove_head(&sblist, psb, struct lpfc_scsi_buf,
list);
if (status) {
/* Put this back on the abort scsi list */
psb->exch_busy = 1;
} else {
psb->exch_busy = 0;
psb->status = IOSTAT_SUCCESS;
}
/* Put it back into the SCSI buffer list */
lpfc_release_scsi_buf_s4(phba, psb);
}
}
return bcnt + non_sequential_xri;
}
/**
* lpfc_new_scsi_buf - Wrapper funciton for scsi buffer allocator
* @vport: The virtual port for which this call being executed.
* @num_to_allocate: The requested number of buffers to allocate.
*
* This routine wraps the actual SCSI buffer allocator function pointer from
* the lpfc_hba struct.
*
* Return codes:
* int - number of scsi buffers that were allocated.
* 0 = failure, less than num_to_alloc is a partial failure.
**/
static inline int
lpfc_new_scsi_buf(struct lpfc_vport *vport, int num_to_alloc)
{
return vport->phba->lpfc_new_scsi_buf(vport, num_to_alloc);
}
/**
* lpfc_get_scsi_buf_s3 - Get a scsi buffer from lpfc_scsi_buf_list of the HBA
* @phba: The HBA for which this call is being executed.
*
* This routine removes a scsi buffer from head of @phba lpfc_scsi_buf_list list
* and returns to caller.
*
* Return codes:
* NULL - Error
* Pointer to lpfc_scsi_buf - Success
**/
static struct lpfc_scsi_buf*
lpfc_get_scsi_buf_s3(struct lpfc_hba *phba, struct lpfc_nodelist *ndlp)
{
struct lpfc_scsi_buf * lpfc_cmd = NULL;
struct list_head *scsi_buf_list = &phba->lpfc_scsi_buf_list;
unsigned long iflag = 0;
spin_lock_irqsave(&phba->scsi_buf_list_lock, iflag);
list_remove_head(scsi_buf_list, lpfc_cmd, struct lpfc_scsi_buf, list);
if (lpfc_cmd) {
lpfc_cmd->seg_cnt = 0;
lpfc_cmd->nonsg_phys = 0;
lpfc_cmd->prot_seg_cnt = 0;
}
spin_unlock_irqrestore(&phba->scsi_buf_list_lock, iflag);
return lpfc_cmd;
}
/**
* lpfc_get_scsi_buf_s4 - Get a scsi buffer from lpfc_scsi_buf_list of the HBA
* @phba: The HBA for which this call is being executed.
*
* This routine removes a scsi buffer from head of @phba lpfc_scsi_buf_list list
* and returns to caller.
*
* Return codes:
* NULL - Error
* Pointer to lpfc_scsi_buf - Success
**/
static struct lpfc_scsi_buf*
lpfc_get_scsi_buf_s4(struct lpfc_hba *phba, struct lpfc_nodelist *ndlp)
{
struct lpfc_scsi_buf *lpfc_cmd ;
unsigned long iflag = 0;
int found = 0;
spin_lock_irqsave(&phba->scsi_buf_list_lock, iflag);
list_for_each_entry(lpfc_cmd, &phba->lpfc_scsi_buf_list,
list) {
if (lpfc_test_rrq_active(phba, ndlp,
lpfc_cmd->cur_iocbq.sli4_xritag))
continue;
list_del(&lpfc_cmd->list);
found = 1;
lpfc_cmd->seg_cnt = 0;
lpfc_cmd->nonsg_phys = 0;
lpfc_cmd->prot_seg_cnt = 0;
break;
}
spin_unlock_irqrestore(&phba->scsi_buf_list_lock,
iflag);
if (!found)
return NULL;
else
return lpfc_cmd;
}
/**
* lpfc_get_scsi_buf - Get a scsi buffer from lpfc_scsi_buf_list of the HBA
* @phba: The HBA for which this call is being executed.
*
* This routine removes a scsi buffer from head of @phba lpfc_scsi_buf_list list
* and returns to caller.
*
* Return codes:
* NULL - Error
* Pointer to lpfc_scsi_buf - Success
**/
static struct lpfc_scsi_buf*
lpfc_get_scsi_buf(struct lpfc_hba *phba, struct lpfc_nodelist *ndlp)
{
return phba->lpfc_get_scsi_buf(phba, ndlp);
}
/**
* lpfc_release_scsi_buf - Return a scsi buffer back to hba scsi buf list
* @phba: The Hba for which this call is being executed.
* @psb: The scsi buffer which is being released.
*
* This routine releases @psb scsi buffer by adding it to tail of @phba
* lpfc_scsi_buf_list list.
**/
static void
lpfc_release_scsi_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
{
unsigned long iflag = 0;
spin_lock_irqsave(&phba->scsi_buf_list_lock, iflag);
psb->pCmd = NULL;
list_add_tail(&psb->list, &phba->lpfc_scsi_buf_list);
spin_unlock_irqrestore(&phba->scsi_buf_list_lock, iflag);
}
/**
* lpfc_release_scsi_buf_s4: Return a scsi buffer back to hba scsi buf list.
* @phba: The Hba for which this call is being executed.
* @psb: The scsi buffer which is being released.
*
* This routine releases @psb scsi buffer by adding it to tail of @phba
* lpfc_scsi_buf_list list. For SLI4 XRI's are tied to the scsi buffer
* and cannot be reused for at least RA_TOV amount of time if it was
* aborted.
**/
static void
lpfc_release_scsi_buf_s4(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
{
unsigned long iflag = 0;
if (psb->exch_busy) {
spin_lock_irqsave(&phba->sli4_hba.abts_scsi_buf_list_lock,
iflag);
psb->pCmd = NULL;
list_add_tail(&psb->list,
&phba->sli4_hba.lpfc_abts_scsi_buf_list);
spin_unlock_irqrestore(&phba->sli4_hba.abts_scsi_buf_list_lock,
iflag);
} else {
spin_lock_irqsave(&phba->scsi_buf_list_lock, iflag);
psb->pCmd = NULL;
list_add_tail(&psb->list, &phba->lpfc_scsi_buf_list);
spin_unlock_irqrestore(&phba->scsi_buf_list_lock, iflag);
}
}
/**
* lpfc_release_scsi_buf: Return a scsi buffer back to hba scsi buf list.
* @phba: The Hba for which this call is being executed.
* @psb: The scsi buffer which is being released.
*
* This routine releases @psb scsi buffer by adding it to tail of @phba
* lpfc_scsi_buf_list list.
**/
static void
lpfc_release_scsi_buf(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
{
phba->lpfc_release_scsi_buf(phba, psb);
}
/**
* lpfc_scsi_prep_dma_buf_s3 - DMA mapping for scsi buffer to SLI3 IF spec
* @phba: The Hba for which this call is being executed.
* @lpfc_cmd: The scsi buffer which is going to be mapped.
*
* This routine does the pci dma mapping for scatter-gather list of scsi cmnd
* field of @lpfc_cmd for device with SLI-3 interface spec. This routine scans
* through sg elements and format the bdea. This routine also initializes all
* IOCB fields which are dependent on scsi command request buffer.
*
* Return codes:
* 1 - Error
* 0 - Success
**/
static int
lpfc_scsi_prep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd)
{
struct scsi_cmnd *scsi_cmnd = lpfc_cmd->pCmd;
struct scatterlist *sgel = NULL;
struct fcp_cmnd *fcp_cmnd = lpfc_cmd->fcp_cmnd;
struct ulp_bde64 *bpl = lpfc_cmd->fcp_bpl;
struct lpfc_iocbq *iocbq = &lpfc_cmd->cur_iocbq;
IOCB_t *iocb_cmd = &lpfc_cmd->cur_iocbq.iocb;
struct ulp_bde64 *data_bde = iocb_cmd->unsli3.fcp_ext.dbde;
dma_addr_t physaddr;
uint32_t num_bde = 0;
int nseg, datadir = scsi_cmnd->sc_data_direction;
/*
* There are three possibilities here - use scatter-gather segment, use
* the single mapping, or neither. Start the lpfc command prep by
* bumping the bpl beyond the fcp_cmnd and fcp_rsp regions to the first
* data bde entry.
*/
bpl += 2;
if (scsi_sg_count(scsi_cmnd)) {
/*
* The driver stores the segment count returned from pci_map_sg
* because this a count of dma-mappings used to map the use_sg
* pages. They are not guaranteed to be the same for those
* architectures that implement an IOMMU.
*/
nseg = dma_map_sg(&phba->pcidev->dev, scsi_sglist(scsi_cmnd),
scsi_sg_count(scsi_cmnd), datadir);
if (unlikely(!nseg))
return 1;
lpfc_cmd->seg_cnt = nseg;
if (lpfc_cmd->seg_cnt > phba->cfg_sg_seg_cnt) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9064 BLKGRD: %s: Too many sg segments from "
"dma_map_sg. Config %d, seg_cnt %d\n",
__func__, phba->cfg_sg_seg_cnt,
lpfc_cmd->seg_cnt);
scsi_dma_unmap(scsi_cmnd);
return 1;
}
/*
* The driver established a maximum scatter-gather segment count
* during probe that limits the number of sg elements in any
* single scsi command. Just run through the seg_cnt and format
* the bde's.
* When using SLI-3 the driver will try to fit all the BDEs into
* the IOCB. If it can't then the BDEs get added to a BPL as it
* does for SLI-2 mode.
*/
scsi_for_each_sg(scsi_cmnd, sgel, nseg, num_bde) {
physaddr = sg_dma_address(sgel);
if (phba->sli_rev == 3 &&
!(phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
!(iocbq->iocb_flag & DSS_SECURITY_OP) &&
nseg <= LPFC_EXT_DATA_BDE_COUNT) {
data_bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64;
data_bde->tus.f.bdeSize = sg_dma_len(sgel);
data_bde->addrLow = putPaddrLow(physaddr);
data_bde->addrHigh = putPaddrHigh(physaddr);
data_bde++;
} else {
bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64;
bpl->tus.f.bdeSize = sg_dma_len(sgel);
bpl->tus.w = le32_to_cpu(bpl->tus.w);
bpl->addrLow =
le32_to_cpu(putPaddrLow(physaddr));
bpl->addrHigh =
le32_to_cpu(putPaddrHigh(physaddr));
bpl++;
}
}
}
/*
* Finish initializing those IOCB fields that are dependent on the
* scsi_cmnd request_buffer. Note that for SLI-2 the bdeSize is
* explicitly reinitialized and for SLI-3 the extended bde count is
* explicitly reinitialized since all iocb memory resources are reused.
*/
if (phba->sli_rev == 3 &&
!(phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
!(iocbq->iocb_flag & DSS_SECURITY_OP)) {
if (num_bde > LPFC_EXT_DATA_BDE_COUNT) {
/*
* The extended IOCB format can only fit 3 BDE or a BPL.
* This I/O has more than 3 BDE so the 1st data bde will
* be a BPL that is filled in here.
*/
physaddr = lpfc_cmd->dma_handle;
data_bde->tus.f.bdeFlags = BUFF_TYPE_BLP_64;
data_bde->tus.f.bdeSize = (num_bde *
sizeof(struct ulp_bde64));
physaddr += (sizeof(struct fcp_cmnd) +
sizeof(struct fcp_rsp) +
(2 * sizeof(struct ulp_bde64)));
data_bde->addrHigh = putPaddrHigh(physaddr);
data_bde->addrLow = putPaddrLow(physaddr);
/* ebde count includes the response bde and data bpl */
iocb_cmd->unsli3.fcp_ext.ebde_count = 2;
} else {
/* ebde count includes the response bde and data bdes */
iocb_cmd->unsli3.fcp_ext.ebde_count = (num_bde + 1);
}
} else {
iocb_cmd->un.fcpi64.bdl.bdeSize =
((num_bde + 2) * sizeof(struct ulp_bde64));
iocb_cmd->unsli3.fcp_ext.ebde_count = (num_bde + 1);
}
fcp_cmnd->fcpDl = cpu_to_be32(scsi_bufflen(scsi_cmnd));
/*
* Due to difference in data length between DIF/non-DIF paths,
* we need to set word 4 of IOCB here
*/
iocb_cmd->un.fcpi.fcpi_parm = scsi_bufflen(scsi_cmnd);
return 0;
}
/*
* Given a scsi cmnd, determine the BlockGuard opcodes to be used with it
* @sc: The SCSI command to examine
* @txopt: (out) BlockGuard operation for transmitted data
* @rxopt: (out) BlockGuard operation for received data
*
* Returns: zero on success; non-zero if tx and/or rx op cannot be determined
*
*/
static int
lpfc_sc_to_bg_opcodes(struct lpfc_hba *phba, struct scsi_cmnd *sc,
uint8_t *txop, uint8_t *rxop)
{
uint8_t guard_type = scsi_host_get_guard(sc->device->host);
uint8_t ret = 0;
if (guard_type == SHOST_DIX_GUARD_IP) {
switch (scsi_get_prot_op(sc)) {
case SCSI_PROT_READ_INSERT:
case SCSI_PROT_WRITE_STRIP:
*txop = BG_OP_IN_CSUM_OUT_NODIF;
*rxop = BG_OP_IN_NODIF_OUT_CSUM;
break;
case SCSI_PROT_READ_STRIP:
case SCSI_PROT_WRITE_INSERT:
*txop = BG_OP_IN_NODIF_OUT_CRC;
*rxop = BG_OP_IN_CRC_OUT_NODIF;
break;
case SCSI_PROT_READ_PASS:
case SCSI_PROT_WRITE_PASS:
*txop = BG_OP_IN_CSUM_OUT_CRC;
*rxop = BG_OP_IN_CRC_OUT_CSUM;
break;
case SCSI_PROT_NORMAL:
default:
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9063 BLKGRD: Bad op/guard:%d/IP combination\n",
scsi_get_prot_op(sc));
ret = 1;
break;
}
} else {
switch (scsi_get_prot_op(sc)) {
case SCSI_PROT_READ_STRIP:
case SCSI_PROT_WRITE_INSERT:
*txop = BG_OP_IN_NODIF_OUT_CRC;
*rxop = BG_OP_IN_CRC_OUT_NODIF;
break;
case SCSI_PROT_READ_PASS:
case SCSI_PROT_WRITE_PASS:
*txop = BG_OP_IN_CRC_OUT_CRC;
*rxop = BG_OP_IN_CRC_OUT_CRC;
break;
case SCSI_PROT_READ_INSERT:
case SCSI_PROT_WRITE_STRIP:
*txop = BG_OP_IN_CRC_OUT_NODIF;
*rxop = BG_OP_IN_NODIF_OUT_CRC;
break;
case SCSI_PROT_NORMAL:
default:
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9075 BLKGRD: Bad op/guard:%d/CRC combination\n",
scsi_get_prot_op(sc));
ret = 1;
break;
}
}
return ret;
}
struct scsi_dif_tuple {
__be16 guard_tag; /* Checksum */
__be16 app_tag; /* Opaque storage */
__be32 ref_tag; /* Target LBA or indirect LBA */
};
static inline unsigned
lpfc_cmd_blksize(struct scsi_cmnd *sc)
{
return sc->device->sector_size;
}
/*
* This function sets up buffer list for protection groups of
* type LPFC_PG_TYPE_NO_DIF
*
* This is usually used when the HBA is instructed to generate
* DIFs and insert them into data stream (or strip DIF from
* incoming data stream)
*
* The buffer list consists of just one protection group described
* below:
* +-------------------------+
* start of prot group --> | PDE_5 |
* +-------------------------+
* | PDE_6 |
* +-------------------------+
* | Data BDE |
* +-------------------------+
* |more Data BDE's ... (opt)|
* +-------------------------+
*
* @sc: pointer to scsi command we're working on
* @bpl: pointer to buffer list for protection groups
* @datacnt: number of segments of data that have been dma mapped
*
* Note: Data s/g buffers have been dma mapped
*/
static int
lpfc_bg_setup_bpl(struct lpfc_hba *phba, struct scsi_cmnd *sc,
struct ulp_bde64 *bpl, int datasegcnt)
{
struct scatterlist *sgde = NULL; /* s/g data entry */
struct lpfc_pde5 *pde5 = NULL;
struct lpfc_pde6 *pde6 = NULL;
dma_addr_t physaddr;
int i = 0, num_bde = 0, status;
int datadir = sc->sc_data_direction;
uint32_t reftag;
unsigned blksize;
uint8_t txop, rxop;
status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop);
if (status)
goto out;
/* extract some info from the scsi command for pde*/
blksize = lpfc_cmd_blksize(sc);
reftag = scsi_get_lba(sc) & 0xffffffff;
/* setup PDE5 with what we have */
pde5 = (struct lpfc_pde5 *) bpl;
memset(pde5, 0, sizeof(struct lpfc_pde5));
bf_set(pde5_type, pde5, LPFC_PDE5_DESCRIPTOR);
/* Endianness conversion if necessary for PDE5 */
pde5->word0 = cpu_to_le32(pde5->word0);
pde5->reftag = cpu_to_le32(reftag);
/* advance bpl and increment bde count */
num_bde++;
bpl++;
pde6 = (struct lpfc_pde6 *) bpl;
/* setup PDE6 with the rest of the info */
memset(pde6, 0, sizeof(struct lpfc_pde6));
bf_set(pde6_type, pde6, LPFC_PDE6_DESCRIPTOR);
bf_set(pde6_optx, pde6, txop);
bf_set(pde6_oprx, pde6, rxop);
if (datadir == DMA_FROM_DEVICE) {
bf_set(pde6_ce, pde6, 1);
bf_set(pde6_re, pde6, 1);
}
bf_set(pde6_ai, pde6, 1);
bf_set(pde6_ae, pde6, 0);
bf_set(pde6_apptagval, pde6, 0);
/* Endianness conversion if necessary for PDE6 */
pde6->word0 = cpu_to_le32(pde6->word0);
pde6->word1 = cpu_to_le32(pde6->word1);
pde6->word2 = cpu_to_le32(pde6->word2);
/* advance bpl and increment bde count */
num_bde++;
bpl++;
/* assumption: caller has already run dma_map_sg on command data */
scsi_for_each_sg(sc, sgde, datasegcnt, i) {
physaddr = sg_dma_address(sgde);
bpl->addrLow = le32_to_cpu(putPaddrLow(physaddr));
bpl->addrHigh = le32_to_cpu(putPaddrHigh(physaddr));
bpl->tus.f.bdeSize = sg_dma_len(sgde);
if (datadir == DMA_TO_DEVICE)
bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64;
else
bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64I;
bpl->tus.w = le32_to_cpu(bpl->tus.w);
bpl++;
num_bde++;
}
out:
return num_bde;
}
/*
* This function sets up buffer list for protection groups of
* type LPFC_PG_TYPE_DIF_BUF
*
* This is usually used when DIFs are in their own buffers,
* separate from the data. The HBA can then by instructed
* to place the DIFs in the outgoing stream. For read operations,
* The HBA could extract the DIFs and place it in DIF buffers.
*
* The buffer list for this type consists of one or more of the
* protection groups described below:
* +-------------------------+
* start of first prot group --> | PDE_5 |
* +-------------------------+
* | PDE_6 |
* +-------------------------+
* | PDE_7 (Prot BDE) |
* +-------------------------+
* | Data BDE |
* +-------------------------+
* |more Data BDE's ... (opt)|
* +-------------------------+
* start of new prot group --> | PDE_5 |
* +-------------------------+
* | ... |
* +-------------------------+
*
* @sc: pointer to scsi command we're working on
* @bpl: pointer to buffer list for protection groups
* @datacnt: number of segments of data that have been dma mapped
* @protcnt: number of segment of protection data that have been dma mapped
*
* Note: It is assumed that both data and protection s/g buffers have been
* mapped for DMA
*/
static int
lpfc_bg_setup_bpl_prot(struct lpfc_hba *phba, struct scsi_cmnd *sc,
struct ulp_bde64 *bpl, int datacnt, int protcnt)
{
struct scatterlist *sgde = NULL; /* s/g data entry */
struct scatterlist *sgpe = NULL; /* s/g prot entry */
struct lpfc_pde5 *pde5 = NULL;
struct lpfc_pde6 *pde6 = NULL;
struct lpfc_pde7 *pde7 = NULL;
dma_addr_t dataphysaddr, protphysaddr;
unsigned short curr_data = 0, curr_prot = 0;
unsigned int split_offset;
unsigned int protgroup_len, protgroup_offset = 0, protgroup_remainder;
unsigned int protgrp_blks, protgrp_bytes;
unsigned int remainder, subtotal;
int status;
int datadir = sc->sc_data_direction;
unsigned char pgdone = 0, alldone = 0;
unsigned blksize;
uint32_t reftag;
uint8_t txop, rxop;
int num_bde = 0;
sgpe = scsi_prot_sglist(sc);
sgde = scsi_sglist(sc);
if (!sgpe || !sgde) {
lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
"9020 Invalid s/g entry: data=0x%p prot=0x%p\n",
sgpe, sgde);
return 0;
}
status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop);
if (status)
goto out;
/* extract some info from the scsi command */
blksize = lpfc_cmd_blksize(sc);
reftag = scsi_get_lba(sc) & 0xffffffff;
split_offset = 0;
do {
/* setup PDE5 with what we have */
pde5 = (struct lpfc_pde5 *) bpl;
memset(pde5, 0, sizeof(struct lpfc_pde5));
bf_set(pde5_type, pde5, LPFC_PDE5_DESCRIPTOR);
/* Endianness conversion if necessary for PDE5 */
pde5->word0 = cpu_to_le32(pde5->word0);
pde5->reftag = cpu_to_le32(reftag);
/* advance bpl and increment bde count */
num_bde++;
bpl++;
pde6 = (struct lpfc_pde6 *) bpl;
/* setup PDE6 with the rest of the info */
memset(pde6, 0, sizeof(struct lpfc_pde6));
bf_set(pde6_type, pde6, LPFC_PDE6_DESCRIPTOR);
bf_set(pde6_optx, pde6, txop);
bf_set(pde6_oprx, pde6, rxop);
bf_set(pde6_ce, pde6, 1);
bf_set(pde6_re, pde6, 1);
bf_set(pde6_ai, pde6, 1);
bf_set(pde6_ae, pde6, 0);
bf_set(pde6_apptagval, pde6, 0);
/* Endianness conversion if necessary for PDE6 */
pde6->word0 = cpu_to_le32(pde6->word0);
pde6->word1 = cpu_to_le32(pde6->word1);
pde6->word2 = cpu_to_le32(pde6->word2);
/* advance bpl and increment bde count */
num_bde++;
bpl++;
/* setup the first BDE that points to protection buffer */
protphysaddr = sg_dma_address(sgpe) + protgroup_offset;
protgroup_len = sg_dma_len(sgpe) - protgroup_offset;
/* must be integer multiple of the DIF block length */
BUG_ON(protgroup_len % 8);
pde7 = (struct lpfc_pde7 *) bpl;
memset(pde7, 0, sizeof(struct lpfc_pde7));
bf_set(pde7_type, pde7, LPFC_PDE7_DESCRIPTOR);
pde7->addrHigh = le32_to_cpu(putPaddrHigh(protphysaddr));
pde7->addrLow = le32_to_cpu(putPaddrLow(protphysaddr));
protgrp_blks = protgroup_len / 8;
protgrp_bytes = protgrp_blks * blksize;
/* check if this pde is crossing the 4K boundary; if so split */
if ((pde7->addrLow & 0xfff) + protgroup_len > 0x1000) {
protgroup_remainder = 0x1000 - (pde7->addrLow & 0xfff);
protgroup_offset += protgroup_remainder;
protgrp_blks = protgroup_remainder / 8;
protgrp_bytes = protgrp_blks * blksize;
} else {
protgroup_offset = 0;
curr_prot++;
}
num_bde++;
/* setup BDE's for data blocks associated with DIF data */
pgdone = 0;
subtotal = 0; /* total bytes processed for current prot grp */
while (!pgdone) {
if (!sgde) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9065 BLKGRD:%s Invalid data segment\n",
__func__);
return 0;
}
bpl++;
dataphysaddr = sg_dma_address(sgde) + split_offset;
bpl->addrLow = le32_to_cpu(putPaddrLow(dataphysaddr));
bpl->addrHigh = le32_to_cpu(putPaddrHigh(dataphysaddr));
remainder = sg_dma_len(sgde) - split_offset;
if ((subtotal + remainder) <= protgrp_bytes) {
/* we can use this whole buffer */
bpl->tus.f.bdeSize = remainder;
split_offset = 0;
if ((subtotal + remainder) == protgrp_bytes)
pgdone = 1;
} else {
/* must split this buffer with next prot grp */
bpl->tus.f.bdeSize = protgrp_bytes - subtotal;
split_offset += bpl->tus.f.bdeSize;
}
subtotal += bpl->tus.f.bdeSize;
if (datadir == DMA_TO_DEVICE)
bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64;
else
bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64I;
bpl->tus.w = le32_to_cpu(bpl->tus.w);
num_bde++;
curr_data++;
if (split_offset)
break;
/* Move to the next s/g segment if possible */
sgde = sg_next(sgde);
}
if (protgroup_offset) {
/* update the reference tag */
reftag += protgrp_blks;
bpl++;
continue;
}
/* are we done ? */
if (curr_prot == protcnt) {
alldone = 1;
} else if (curr_prot < protcnt) {
/* advance to next prot buffer */
sgpe = sg_next(sgpe);
bpl++;
/* update the reference tag */
reftag += protgrp_blks;
} else {
/* if we're here, we have a bug */
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9054 BLKGRD: bug in %s\n", __func__);
}
} while (!alldone);
out:
return num_bde;
}
/*
* Given a SCSI command that supports DIF, determine composition of protection
* groups involved in setting up buffer lists
*
* Returns:
* for DIF (for both read and write)
* */
static int
lpfc_prot_group_type(struct lpfc_hba *phba, struct scsi_cmnd *sc)
{
int ret = LPFC_PG_TYPE_INVALID;
unsigned char op = scsi_get_prot_op(sc);
switch (op) {
case SCSI_PROT_READ_STRIP:
case SCSI_PROT_WRITE_INSERT:
ret = LPFC_PG_TYPE_NO_DIF;
break;
case SCSI_PROT_READ_INSERT:
case SCSI_PROT_WRITE_STRIP:
case SCSI_PROT_READ_PASS:
case SCSI_PROT_WRITE_PASS:
ret = LPFC_PG_TYPE_DIF_BUF;
break;
default:
lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
"9021 Unsupported protection op:%d\n", op);
break;
}
return ret;
}
/*
* This is the protection/DIF aware version of
* lpfc_scsi_prep_dma_buf(). It may be a good idea to combine the
* two functions eventually, but for now, it's here
*/
static int
lpfc_bg_scsi_prep_dma_buf(struct lpfc_hba *phba,
struct lpfc_scsi_buf *lpfc_cmd)
{
struct scsi_cmnd *scsi_cmnd = lpfc_cmd->pCmd;
struct fcp_cmnd *fcp_cmnd = lpfc_cmd->fcp_cmnd;
struct ulp_bde64 *bpl = lpfc_cmd->fcp_bpl;
IOCB_t *iocb_cmd = &lpfc_cmd->cur_iocbq.iocb;
uint32_t num_bde = 0;
int datasegcnt, protsegcnt, datadir = scsi_cmnd->sc_data_direction;
int prot_group_type = 0;
int diflen, fcpdl;
unsigned blksize;
/*
* Start the lpfc command prep by bumping the bpl beyond fcp_cmnd
* fcp_rsp regions to the first data bde entry
*/
bpl += 2;
if (scsi_sg_count(scsi_cmnd)) {
/*
* The driver stores the segment count returned from pci_map_sg
* because this a count of dma-mappings used to map the use_sg
* pages. They are not guaranteed to be the same for those
* architectures that implement an IOMMU.
*/
datasegcnt = dma_map_sg(&phba->pcidev->dev,
scsi_sglist(scsi_cmnd),
scsi_sg_count(scsi_cmnd), datadir);
if (unlikely(!datasegcnt))
return 1;
lpfc_cmd->seg_cnt = datasegcnt;
if (lpfc_cmd->seg_cnt > phba->cfg_sg_seg_cnt) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9067 BLKGRD: %s: Too many sg segments"
" from dma_map_sg. Config %d, seg_cnt"
" %d\n",
__func__, phba->cfg_sg_seg_cnt,
lpfc_cmd->seg_cnt);
scsi_dma_unmap(scsi_cmnd);
return 1;
}
prot_group_type = lpfc_prot_group_type(phba, scsi_cmnd);
switch (prot_group_type) {
case LPFC_PG_TYPE_NO_DIF:
num_bde = lpfc_bg_setup_bpl(phba, scsi_cmnd, bpl,
datasegcnt);
/* we should have 2 or more entries in buffer list */
if (num_bde < 2)
goto err;
break;
case LPFC_PG_TYPE_DIF_BUF:{
/*
* This type indicates that protection buffers are
* passed to the driver, so that needs to be prepared
* for DMA
*/
protsegcnt = dma_map_sg(&phba->pcidev->dev,
scsi_prot_sglist(scsi_cmnd),
scsi_prot_sg_count(scsi_cmnd), datadir);
if (unlikely(!protsegcnt)) {
scsi_dma_unmap(scsi_cmnd);
return 1;
}
lpfc_cmd->prot_seg_cnt = protsegcnt;
if (lpfc_cmd->prot_seg_cnt
> phba->cfg_prot_sg_seg_cnt) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9068 BLKGRD: %s: Too many prot sg "
"segments from dma_map_sg. Config %d,"
"prot_seg_cnt %d\n", __func__,
phba->cfg_prot_sg_seg_cnt,
lpfc_cmd->prot_seg_cnt);
dma_unmap_sg(&phba->pcidev->dev,
scsi_prot_sglist(scsi_cmnd),
scsi_prot_sg_count(scsi_cmnd),
datadir);
scsi_dma_unmap(scsi_cmnd);
return 1;
}
num_bde = lpfc_bg_setup_bpl_prot(phba, scsi_cmnd, bpl,
datasegcnt, protsegcnt);
/* we should have 3 or more entries in buffer list */
if (num_bde < 3)
goto err;
break;
}
case LPFC_PG_TYPE_INVALID:
default:
lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
"9022 Unexpected protection group %i\n",
prot_group_type);
return 1;
}
}
/*
* Finish initializing those IOCB fields that are dependent on the
* scsi_cmnd request_buffer. Note that the bdeSize is explicitly
* reinitialized since all iocb memory resources are used many times
* for transmit, receive, and continuation bpl's.
*/
iocb_cmd->un.fcpi64.bdl.bdeSize = (2 * sizeof(struct ulp_bde64));
iocb_cmd->un.fcpi64.bdl.bdeSize += (num_bde * sizeof(struct ulp_bde64));
iocb_cmd->ulpBdeCount = 1;
iocb_cmd->ulpLe = 1;
fcpdl = scsi_bufflen(scsi_cmnd);
if (scsi_get_prot_type(scsi_cmnd) == SCSI_PROT_DIF_TYPE1) {
/*
* We are in DIF Type 1 mode
* Every data block has a 8 byte DIF (trailer)
* attached to it. Must ajust FCP data length
*/
blksize = lpfc_cmd_blksize(scsi_cmnd);
diflen = (fcpdl / blksize) * 8;
fcpdl += diflen;
}
fcp_cmnd->fcpDl = be32_to_cpu(fcpdl);
/*
* Due to difference in data length between DIF/non-DIF paths,
* we need to set word 4 of IOCB here
*/
iocb_cmd->un.fcpi.fcpi_parm = fcpdl;
return 0;
err:
lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
"9023 Could not setup all needed BDE's"
"prot_group_type=%d, num_bde=%d\n",
prot_group_type, num_bde);
return 1;
}
/*
* This function checks for BlockGuard errors detected by
* the HBA. In case of errors, the ASC/ASCQ fields in the
* sense buffer will be set accordingly, paired with
* ILLEGAL_REQUEST to signal to the kernel that the HBA
* detected corruption.
*
* Returns:
* 0 - No error found
* 1 - BlockGuard error found
* -1 - Internal error (bad profile, ...etc)
*/
static int
lpfc_parse_bg_err(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd,
struct lpfc_iocbq *pIocbOut)
{
struct scsi_cmnd *cmd = lpfc_cmd->pCmd;
struct sli3_bg_fields *bgf = &pIocbOut->iocb.unsli3.sli3_bg;
int ret = 0;
uint32_t bghm = bgf->bghm;
uint32_t bgstat = bgf->bgstat;
uint64_t failing_sector = 0;
lpfc_printf_log(phba, KERN_ERR, LOG_BG, "9069 BLKGRD: BG ERROR in cmd"
" 0x%x lba 0x%llx blk cnt 0x%x "
"bgstat=0x%x bghm=0x%x\n",
cmd->cmnd[0], (unsigned long long)scsi_get_lba(cmd),
blk_rq_sectors(cmd->request), bgstat, bghm);
spin_lock(&_dump_buf_lock);
if (!_dump_buf_done) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG, "9070 BLKGRD: Saving"
" Data for %u blocks to debugfs\n",
(cmd->cmnd[7] << 8 | cmd->cmnd[8]));
lpfc_debug_save_data(phba, cmd);
/* If we have a prot sgl, save the DIF buffer */
if (lpfc_prot_group_type(phba, cmd) ==
LPFC_PG_TYPE_DIF_BUF) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG, "9071 BLKGRD: "
"Saving DIF for %u blocks to debugfs\n",
(cmd->cmnd[7] << 8 | cmd->cmnd[8]));
lpfc_debug_save_dif(phba, cmd);
}
_dump_buf_done = 1;
}
spin_unlock(&_dump_buf_lock);
if (lpfc_bgs_get_invalid_prof(bgstat)) {
cmd->result = ScsiResult(DID_ERROR, 0);
lpfc_printf_log(phba, KERN_ERR, LOG_BG, "9072 BLKGRD: Invalid"
" BlockGuard profile. bgstat:0x%x\n",
bgstat);
ret = (-1);
goto out;
}
if (lpfc_bgs_get_uninit_dif_block(bgstat)) {
cmd->result = ScsiResult(DID_ERROR, 0);
lpfc_printf_log(phba, KERN_ERR, LOG_BG, "9073 BLKGRD: "
"Invalid BlockGuard DIF Block. bgstat:0x%x\n",
bgstat);
ret = (-1);
goto out;
}
if (lpfc_bgs_get_guard_err(bgstat)) {
ret = 1;
scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
0x10, 0x1);
cmd->result = DRIVER_SENSE << 24
| ScsiResult(DID_ABORT, SAM_STAT_CHECK_CONDITION);
phba->bg_guard_err_cnt++;
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9055 BLKGRD: guard_tag error\n");
}
if (lpfc_bgs_get_reftag_err(bgstat)) {
ret = 1;
scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
0x10, 0x3);
cmd->result = DRIVER_SENSE << 24
| ScsiResult(DID_ABORT, SAM_STAT_CHECK_CONDITION);
phba->bg_reftag_err_cnt++;
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9056 BLKGRD: ref_tag error\n");
}
if (lpfc_bgs_get_apptag_err(bgstat)) {
ret = 1;
scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
0x10, 0x2);
cmd->result = DRIVER_SENSE << 24
| ScsiResult(DID_ABORT, SAM_STAT_CHECK_CONDITION);
phba->bg_apptag_err_cnt++;
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9061 BLKGRD: app_tag error\n");
}
if (lpfc_bgs_get_hi_water_mark_present(bgstat)) {
/*
* setup sense data descriptor 0 per SPC-4 as an information
* field, and put the failing LBA in it.
* This code assumes there was also a guard/app/ref tag error
* indication.
*/
cmd->sense_buffer[7] = 0xc; /* Additional sense length */
cmd->sense_buffer[8] = 0; /* Information descriptor type */
cmd->sense_buffer[9] = 0xa; /* Additional descriptor length */
cmd->sense_buffer[10] = 0x80; /* Validity bit */
bghm /= cmd->device->sector_size;
failing_sector = scsi_get_lba(cmd);
failing_sector += bghm;
/* Descriptor Information */
put_unaligned_be64(failing_sector, &cmd->sense_buffer[12]);
}
if (!ret) {
/* No error was reported - problem in FW? */
cmd->result = ScsiResult(DID_ERROR, 0);
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9057 BLKGRD: no errors reported!\n");
}
out:
return ret;
}
/**
* lpfc_scsi_prep_dma_buf_s4 - DMA mapping for scsi buffer to SLI4 IF spec
* @phba: The Hba for which this call is being executed.
* @lpfc_cmd: The scsi buffer which is going to be mapped.
*
* This routine does the pci dma mapping for scatter-gather list of scsi cmnd
* field of @lpfc_cmd for device with SLI-4 interface spec.
*
* Return codes:
* 1 - Error
* 0 - Success
**/
static int
lpfc_scsi_prep_dma_buf_s4(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd)
{
struct scsi_cmnd *scsi_cmnd = lpfc_cmd->pCmd;
struct scatterlist *sgel = NULL;
struct fcp_cmnd *fcp_cmnd = lpfc_cmd->fcp_cmnd;
struct sli4_sge *sgl = (struct sli4_sge *)lpfc_cmd->fcp_bpl;
struct sli4_sge *first_data_sgl;
IOCB_t *iocb_cmd = &lpfc_cmd->cur_iocbq.iocb;
dma_addr_t physaddr;
uint32_t num_bde = 0;
uint32_t dma_len;
uint32_t dma_offset = 0;
int nseg;
struct ulp_bde64 *bde;
/*
* There are three possibilities here - use scatter-gather segment, use
* the single mapping, or neither. Start the lpfc command prep by
* bumping the bpl beyond the fcp_cmnd and fcp_rsp regions to the first
* data bde entry.
*/
if (scsi_sg_count(scsi_cmnd)) {
/*
* The driver stores the segment count returned from pci_map_sg
* because this a count of dma-mappings used to map the use_sg
* pages. They are not guaranteed to be the same for those
* architectures that implement an IOMMU.
*/
nseg = scsi_dma_map(scsi_cmnd);
if (unlikely(!nseg))
return 1;
sgl += 1;
/* clear the last flag in the fcp_rsp map entry */
sgl->word2 = le32_to_cpu(sgl->word2);
bf_set(lpfc_sli4_sge_last, sgl, 0);
sgl->word2 = cpu_to_le32(sgl->word2);
sgl += 1;
first_data_sgl = sgl;
lpfc_cmd->seg_cnt = nseg;
if (lpfc_cmd->seg_cnt > phba->cfg_sg_seg_cnt) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG, "9074 BLKGRD:"
" %s: Too many sg segments from "
"dma_map_sg. Config %d, seg_cnt %d\n",
__func__, phba->cfg_sg_seg_cnt,
lpfc_cmd->seg_cnt);
scsi_dma_unmap(scsi_cmnd);
return 1;
}
/*
* The driver established a maximum scatter-gather segment count
* during probe that limits the number of sg elements in any
* single scsi command. Just run through the seg_cnt and format
* the sge's.
* When using SLI-3 the driver will try to fit all the BDEs into
* the IOCB. If it can't then the BDEs get added to a BPL as it
* does for SLI-2 mode.
*/
scsi_for_each_sg(scsi_cmnd, sgel, nseg, num_bde) {
physaddr = sg_dma_address(sgel);
dma_len = sg_dma_len(sgel);
sgl->addr_lo = cpu_to_le32(putPaddrLow(physaddr));
sgl->addr_hi = cpu_to_le32(putPaddrHigh(physaddr));
sgl->word2 = le32_to_cpu(sgl->word2);
if ((num_bde + 1) == nseg)
bf_set(lpfc_sli4_sge_last, sgl, 1);
else
bf_set(lpfc_sli4_sge_last, sgl, 0);
bf_set(lpfc_sli4_sge_offset, sgl, dma_offset);
sgl->word2 = cpu_to_le32(sgl->word2);
sgl->sge_len = cpu_to_le32(dma_len);
dma_offset += dma_len;
sgl++;
}
/* setup the performance hint (first data BDE) if enabled */
if (phba->sli3_options & LPFC_SLI4_PERFH_ENABLED) {
bde = (struct ulp_bde64 *)
&(iocb_cmd->unsli3.sli3Words[5]);
bde->addrLow = first_data_sgl->addr_lo;
bde->addrHigh = first_data_sgl->addr_hi;
bde->tus.f.bdeSize =
le32_to_cpu(first_data_sgl->sge_len);
bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64;
bde->tus.w = cpu_to_le32(bde->tus.w);
}
} else {
sgl += 1;
/* clear the last flag in the fcp_rsp map entry */
sgl->word2 = le32_to_cpu(sgl->word2);
bf_set(lpfc_sli4_sge_last, sgl, 1);
sgl->word2 = cpu_to_le32(sgl->word2);
}
/*
* Finish initializing those IOCB fields that are dependent on the
* scsi_cmnd request_buffer. Note that for SLI-2 the bdeSize is
* explicitly reinitialized.
* all iocb memory resources are reused.
*/
fcp_cmnd->fcpDl = cpu_to_be32(scsi_bufflen(scsi_cmnd));
/*
* Due to difference in data length between DIF/non-DIF paths,
* we need to set word 4 of IOCB here
*/
iocb_cmd->un.fcpi.fcpi_parm = scsi_bufflen(scsi_cmnd);
return 0;
}
/**
* lpfc_scsi_prep_dma_buf - Wrapper function for DMA mapping of scsi buffer
* @phba: The Hba for which this call is being executed.
* @lpfc_cmd: The scsi buffer which is going to be mapped.
*
* This routine wraps the actual DMA mapping function pointer from the
* lpfc_hba struct.
*
* Return codes:
* 1 - Error
* 0 - Success
**/
static inline int
lpfc_scsi_prep_dma_buf(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd)
{
return phba->lpfc_scsi_prep_dma_buf(phba, lpfc_cmd);
}
/**
* lpfc_send_scsi_error_event - Posts an event when there is SCSI error
* @phba: Pointer to hba context object.
* @vport: Pointer to vport object.
* @lpfc_cmd: Pointer to lpfc scsi command which reported the error.
* @rsp_iocb: Pointer to response iocb object which reported error.
*
* This function posts an event when there is a SCSI command reporting
* error from the scsi device.
**/
static void
lpfc_send_scsi_error_event(struct lpfc_hba *phba, struct lpfc_vport *vport,
struct lpfc_scsi_buf *lpfc_cmd, struct lpfc_iocbq *rsp_iocb) {
struct scsi_cmnd *cmnd = lpfc_cmd->pCmd;
struct fcp_rsp *fcprsp = lpfc_cmd->fcp_rsp;
uint32_t resp_info = fcprsp->rspStatus2;
uint32_t scsi_status = fcprsp->rspStatus3;
uint32_t fcpi_parm = rsp_iocb->iocb.un.fcpi.fcpi_parm;
struct lpfc_fast_path_event *fast_path_evt = NULL;
struct lpfc_nodelist *pnode = lpfc_cmd->rdata->pnode;
unsigned long flags;
if (!pnode || !NLP_CHK_NODE_ACT(pnode))
return;
/* If there is queuefull or busy condition send a scsi event */
if ((cmnd->result == SAM_STAT_TASK_SET_FULL) ||
(cmnd->result == SAM_STAT_BUSY)) {
fast_path_evt = lpfc_alloc_fast_evt(phba);
if (!fast_path_evt)
return;
fast_path_evt->un.scsi_evt.event_type =
FC_REG_SCSI_EVENT;
fast_path_evt->un.scsi_evt.subcategory =
(cmnd->result == SAM_STAT_TASK_SET_FULL) ?
LPFC_EVENT_QFULL : LPFC_EVENT_DEVBSY;
fast_path_evt->un.scsi_evt.lun = cmnd->device->lun;
memcpy(&fast_path_evt->un.scsi_evt.wwpn,
&pnode->nlp_portname, sizeof(struct lpfc_name));
memcpy(&fast_path_evt->un.scsi_evt.wwnn,
&pnode->nlp_nodename, sizeof(struct lpfc_name));
} else if ((resp_info & SNS_LEN_VALID) && fcprsp->rspSnsLen &&
((cmnd->cmnd[0] == READ_10) || (cmnd->cmnd[0] == WRITE_10))) {
fast_path_evt = lpfc_alloc_fast_evt(phba);
if (!fast_path_evt)
return;
fast_path_evt->un.check_cond_evt.scsi_event.event_type =
FC_REG_SCSI_EVENT;
fast_path_evt->un.check_cond_evt.scsi_event.subcategory =
LPFC_EVENT_CHECK_COND;
fast_path_evt->un.check_cond_evt.scsi_event.lun =
cmnd->device->lun;
memcpy(&fast_path_evt->un.check_cond_evt.scsi_event.wwpn,
&pnode->nlp_portname, sizeof(struct lpfc_name));
memcpy(&fast_path_evt->un.check_cond_evt.scsi_event.wwnn,
&pnode->nlp_nodename, sizeof(struct lpfc_name));
fast_path_evt->un.check_cond_evt.sense_key =
cmnd->sense_buffer[2] & 0xf;
fast_path_evt->un.check_cond_evt.asc = cmnd->sense_buffer[12];
fast_path_evt->un.check_cond_evt.ascq = cmnd->sense_buffer[13];
} else if ((cmnd->sc_data_direction == DMA_FROM_DEVICE) &&
fcpi_parm &&
((be32_to_cpu(fcprsp->rspResId) != fcpi_parm) ||
((scsi_status == SAM_STAT_GOOD) &&
!(resp_info & (RESID_UNDER | RESID_OVER))))) {
/*
* If status is good or resid does not match with fcp_param and
* there is valid fcpi_parm, then there is a read_check error
*/
fast_path_evt = lpfc_alloc_fast_evt(phba);
if (!fast_path_evt)
return;
fast_path_evt->un.read_check_error.header.event_type =
FC_REG_FABRIC_EVENT;
fast_path_evt->un.read_check_error.header.subcategory =
LPFC_EVENT_FCPRDCHKERR;
memcpy(&fast_path_evt->un.read_check_error.header.wwpn,
&pnode->nlp_portname, sizeof(struct lpfc_name));
memcpy(&fast_path_evt->un.read_check_error.header.wwnn,
&pnode->nlp_nodename, sizeof(struct lpfc_name));
fast_path_evt->un.read_check_error.lun = cmnd->device->lun;
fast_path_evt->un.read_check_error.opcode = cmnd->cmnd[0];
fast_path_evt->un.read_check_error.fcpiparam =
fcpi_parm;
} else
return;
fast_path_evt->vport = vport;
spin_lock_irqsave(&phba->hbalock, flags);
list_add_tail(&fast_path_evt->work_evt.evt_listp, &phba->work_list);
spin_unlock_irqrestore(&phba->hbalock, flags);
lpfc_worker_wake_up(phba);
return;
}
/**
* lpfc_scsi_unprep_dma_buf - Un-map DMA mapping of SG-list for dev
* @phba: The HBA for which this call is being executed.
* @psb: The scsi buffer which is going to be un-mapped.
*
* This routine does DMA un-mapping of scatter gather list of scsi command
* field of @lpfc_cmd for device with SLI-3 interface spec.
**/
static void
lpfc_scsi_unprep_dma_buf(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
{
/*
* There are only two special cases to consider. (1) the scsi command
* requested scatter-gather usage or (2) the scsi command allocated
* a request buffer, but did not request use_sg. There is a third
* case, but it does not require resource deallocation.
*/
if (psb->seg_cnt > 0)
scsi_dma_unmap(psb->pCmd);
if (psb->prot_seg_cnt > 0)
dma_unmap_sg(&phba->pcidev->dev, scsi_prot_sglist(psb->pCmd),
scsi_prot_sg_count(psb->pCmd),
psb->pCmd->sc_data_direction);
}
/**
* lpfc_handler_fcp_err - FCP response handler
* @vport: The virtual port for which this call is being executed.
* @lpfc_cmd: Pointer to lpfc_scsi_buf data structure.
* @rsp_iocb: The response IOCB which contains FCP error.
*
* This routine is called to process response IOCB with status field
* IOSTAT_FCP_RSP_ERROR. This routine sets result field of scsi command
* based upon SCSI and FCP error.
**/
static void
lpfc_handle_fcp_err(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
struct lpfc_iocbq *rsp_iocb)
{
struct scsi_cmnd *cmnd = lpfc_cmd->pCmd;
struct fcp_cmnd *fcpcmd = lpfc_cmd->fcp_cmnd;
struct fcp_rsp *fcprsp = lpfc_cmd->fcp_rsp;
uint32_t fcpi_parm = rsp_iocb->iocb.un.fcpi.fcpi_parm;
uint32_t resp_info = fcprsp->rspStatus2;
uint32_t scsi_status = fcprsp->rspStatus3;
uint32_t *lp;
uint32_t host_status = DID_OK;
uint32_t rsplen = 0;
uint32_t logit = LOG_FCP | LOG_FCP_ERROR;
/*
* If this is a task management command, there is no
* scsi packet associated with this lpfc_cmd. The driver
* consumes it.
*/
if (fcpcmd->fcpCntl2) {
scsi_status = 0;
goto out;
}
if (resp_info & RSP_LEN_VALID) {
rsplen = be32_to_cpu(fcprsp->rspRspLen);
if (rsplen != 0 && rsplen != 4 && rsplen != 8) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"2719 Invalid response length: "
"tgt x%x lun x%x cmnd x%x rsplen x%x\n",
cmnd->device->id,
cmnd->device->lun, cmnd->cmnd[0],
rsplen);
host_status = DID_ERROR;
goto out;
}
if (fcprsp->rspInfo3 != RSP_NO_FAILURE) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"2757 Protocol failure detected during "
"processing of FCP I/O op: "
"tgt x%x lun x%x cmnd x%x rspInfo3 x%x\n",
cmnd->device->id,
cmnd->device->lun, cmnd->cmnd[0],
fcprsp->rspInfo3);
host_status = DID_ERROR;
goto out;
}
}
if ((resp_info & SNS_LEN_VALID) && fcprsp->rspSnsLen) {
uint32_t snslen = be32_to_cpu(fcprsp->rspSnsLen);
if (snslen > SCSI_SENSE_BUFFERSIZE)
snslen = SCSI_SENSE_BUFFERSIZE;
if (resp_info & RSP_LEN_VALID)
rsplen = be32_to_cpu(fcprsp->rspRspLen);
memcpy(cmnd->sense_buffer, &fcprsp->rspInfo0 + rsplen, snslen);
}
lp = (uint32_t *)cmnd->sense_buffer;
if (!scsi_status && (resp_info & RESID_UNDER))
logit = LOG_FCP;
lpfc_printf_vlog(vport, KERN_WARNING, logit,
"9024 FCP command x%x failed: x%x SNS x%x x%x "
"Data: x%x x%x x%x x%x x%x\n",
cmnd->cmnd[0], scsi_status,
be32_to_cpu(*lp), be32_to_cpu(*(lp + 3)), resp_info,
be32_to_cpu(fcprsp->rspResId),
be32_to_cpu(fcprsp->rspSnsLen),
be32_to_cpu(fcprsp->rspRspLen),
fcprsp->rspInfo3);
scsi_set_resid(cmnd, 0);
if (resp_info & RESID_UNDER) {
scsi_set_resid(cmnd, be32_to_cpu(fcprsp->rspResId));
lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
"9025 FCP Read Underrun, expected %d, "
"residual %d Data: x%x x%x x%x\n",
be32_to_cpu(fcpcmd->fcpDl),
scsi_get_resid(cmnd), fcpi_parm, cmnd->cmnd[0],
cmnd->underflow);
/*
* If there is an under run check if under run reported by
* storage array is same as the under run reported by HBA.
* If this is not same, there is a dropped frame.
*/
if ((cmnd->sc_data_direction == DMA_FROM_DEVICE) &&
fcpi_parm &&
(scsi_get_resid(cmnd) != fcpi_parm)) {
lpfc_printf_vlog(vport, KERN_WARNING,
LOG_FCP | LOG_FCP_ERROR,
"9026 FCP Read Check Error "
"and Underrun Data: x%x x%x x%x x%x\n",
be32_to_cpu(fcpcmd->fcpDl),
scsi_get_resid(cmnd), fcpi_parm,
cmnd->cmnd[0]);
scsi_set_resid(cmnd, scsi_bufflen(cmnd));
host_status = DID_ERROR;
}
/*
* The cmnd->underflow is the minimum number of bytes that must
* be transferred for this command. Provided a sense condition
* is not present, make sure the actual amount transferred is at
* least the underflow value or fail.
*/
if (!(resp_info & SNS_LEN_VALID) &&
(scsi_status == SAM_STAT_GOOD) &&
(scsi_bufflen(cmnd) - scsi_get_resid(cmnd)
< cmnd->underflow)) {
lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
"9027 FCP command x%x residual "
"underrun converted to error "
"Data: x%x x%x x%x\n",
cmnd->cmnd[0], scsi_bufflen(cmnd),
scsi_get_resid(cmnd), cmnd->underflow);
host_status = DID_ERROR;
}
} else if (resp_info & RESID_OVER) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"9028 FCP command x%x residual overrun error. "
"Data: x%x x%x\n", cmnd->cmnd[0],
scsi_bufflen(cmnd), scsi_get_resid(cmnd));
host_status = DID_ERROR;
/*
* Check SLI validation that all the transfer was actually done
* (fcpi_parm should be zero). Apply check only to reads.
*/
} else if (fcpi_parm && (cmnd->sc_data_direction == DMA_FROM_DEVICE)) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP | LOG_FCP_ERROR,
"9029 FCP Read Check Error Data: "
"x%x x%x x%x x%x x%x\n",
be32_to_cpu(fcpcmd->fcpDl),
be32_to_cpu(fcprsp->rspResId),
fcpi_parm, cmnd->cmnd[0], scsi_status);
switch (scsi_status) {
case SAM_STAT_GOOD:
case SAM_STAT_CHECK_CONDITION:
/* Fabric dropped a data frame. Fail any successful
* command in which we detected dropped frames.
* A status of good or some check conditions could
* be considered a successful command.
*/
host_status = DID_ERROR;
break;
}
scsi_set_resid(cmnd, scsi_bufflen(cmnd));
}
out:
cmnd->result = ScsiResult(host_status, scsi_status);
lpfc_send_scsi_error_event(vport->phba, vport, lpfc_cmd, rsp_iocb);
}
/**
* lpfc_scsi_cmd_iocb_cmpl - Scsi cmnd IOCB completion routine
* @phba: The Hba for which this call is being executed.
* @pIocbIn: The command IOCBQ for the scsi cmnd.
* @pIocbOut: The response IOCBQ for the scsi cmnd.
*
* This routine assigns scsi command result by looking into response IOCB
* status field appropriately. This routine handles QUEUE FULL condition as
* well by ramping down device queue depth.
**/
static void
lpfc_scsi_cmd_iocb_cmpl(struct lpfc_hba *phba, struct lpfc_iocbq *pIocbIn,
struct lpfc_iocbq *pIocbOut)
{
struct lpfc_scsi_buf *lpfc_cmd =
(struct lpfc_scsi_buf *) pIocbIn->context1;
struct lpfc_vport *vport = pIocbIn->vport;
struct lpfc_rport_data *rdata = lpfc_cmd->rdata;
struct lpfc_nodelist *pnode = rdata->pnode;
struct scsi_cmnd *cmd;
int result;
struct scsi_device *tmp_sdev;
int depth;
unsigned long flags;
struct lpfc_fast_path_event *fast_path_evt;
struct Scsi_Host *shost;
uint32_t queue_depth, scsi_id;
/* Sanity check on return of outstanding command */
if (!(lpfc_cmd->pCmd))
return;
cmd = lpfc_cmd->pCmd;
shost = cmd->device->host;
lpfc_cmd->result = pIocbOut->iocb.un.ulpWord[4];
lpfc_cmd->status = pIocbOut->iocb.ulpStatus;
/* pick up SLI4 exhange busy status from HBA */
lpfc_cmd->exch_busy = pIocbOut->iocb_flag & LPFC_EXCHANGE_BUSY;
if (pnode && NLP_CHK_NODE_ACT(pnode))
atomic_dec(&pnode->cmd_pending);
if (lpfc_cmd->status) {
if (lpfc_cmd->status == IOSTAT_LOCAL_REJECT &&
(lpfc_cmd->result & IOERR_DRVR_MASK))
lpfc_cmd->status = IOSTAT_DRIVER_REJECT;
else if (lpfc_cmd->status >= IOSTAT_CNT)
lpfc_cmd->status = IOSTAT_DEFAULT;
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"9030 FCP cmd x%x failed <%d/%d> "
"status: x%x result: x%x Data: x%x x%x\n",
cmd->cmnd[0],
cmd->device ? cmd->device->id : 0xffff,
cmd->device ? cmd->device->lun : 0xffff,
lpfc_cmd->status, lpfc_cmd->result,
pIocbOut->iocb.ulpContext,
lpfc_cmd->cur_iocbq.iocb.ulpIoTag);
switch (lpfc_cmd->status) {
case IOSTAT_FCP_RSP_ERROR:
/* Call FCP RSP handler to determine result */
lpfc_handle_fcp_err(vport, lpfc_cmd, pIocbOut);
break;
case IOSTAT_NPORT_BSY:
case IOSTAT_FABRIC_BSY:
cmd->result = ScsiResult(DID_TRANSPORT_DISRUPTED, 0);
fast_path_evt = lpfc_alloc_fast_evt(phba);
if (!fast_path_evt)
break;
fast_path_evt->un.fabric_evt.event_type =
FC_REG_FABRIC_EVENT;
fast_path_evt->un.fabric_evt.subcategory =
(lpfc_cmd->status == IOSTAT_NPORT_BSY) ?
LPFC_EVENT_PORT_BUSY : LPFC_EVENT_FABRIC_BUSY;
if (pnode && NLP_CHK_NODE_ACT(pnode)) {
memcpy(&fast_path_evt->un.fabric_evt.wwpn,
&pnode->nlp_portname,
sizeof(struct lpfc_name));
memcpy(&fast_path_evt->un.fabric_evt.wwnn,
&pnode->nlp_nodename,
sizeof(struct lpfc_name));
}
fast_path_evt->vport = vport;
fast_path_evt->work_evt.evt =
LPFC_EVT_FASTPATH_MGMT_EVT;
spin_lock_irqsave(&phba->hbalock, flags);
list_add_tail(&fast_path_evt->work_evt.evt_listp,
&phba->work_list);
spin_unlock_irqrestore(&phba->hbalock, flags);
lpfc_worker_wake_up(phba);
break;
case IOSTAT_LOCAL_REJECT:
case IOSTAT_REMOTE_STOP:
if (lpfc_cmd->result == IOERR_ELXSEC_KEY_UNWRAP_ERROR ||
lpfc_cmd->result ==
IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR ||
lpfc_cmd->result == IOERR_ELXSEC_CRYPTO_ERROR ||
lpfc_cmd->result ==
IOERR_ELXSEC_CRYPTO_COMPARE_ERROR) {
cmd->result = ScsiResult(DID_NO_CONNECT, 0);
break;
}
if (lpfc_cmd->result == IOERR_INVALID_RPI ||
lpfc_cmd->result == IOERR_NO_RESOURCES ||
lpfc_cmd->result == IOERR_ABORT_REQUESTED ||
lpfc_cmd->result == IOERR_SLER_CMD_RCV_FAILURE) {
cmd->result = ScsiResult(DID_REQUEUE, 0);
break;
}
if ((lpfc_cmd->result == IOERR_RX_DMA_FAILED ||
lpfc_cmd->result == IOERR_TX_DMA_FAILED) &&
pIocbOut->iocb.unsli3.sli3_bg.bgstat) {
if (scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
/*
* This is a response for a BG enabled
* cmd. Parse BG error
*/
lpfc_parse_bg_err(phba, lpfc_cmd,
pIocbOut);
break;
} else {
lpfc_printf_vlog(vport, KERN_WARNING,
LOG_BG,
"9031 non-zero BGSTAT "
"on unprotected cmd\n");
}
}
if ((lpfc_cmd->status == IOSTAT_REMOTE_STOP)
&& (phba->sli_rev == LPFC_SLI_REV4)
&& (pnode && NLP_CHK_NODE_ACT(pnode))) {
/* This IO was aborted by the target, we don't
* know the rxid and because we did not send the
* ABTS we cannot generate and RRQ.
*/
lpfc_set_rrq_active(phba, pnode,
lpfc_cmd->cur_iocbq.sli4_xritag,
0, 0);
}
/* else: fall through */
default:
cmd->result = ScsiResult(DID_ERROR, 0);
break;
}
if (!pnode || !NLP_CHK_NODE_ACT(pnode)
|| (pnode->nlp_state != NLP_STE_MAPPED_NODE))
cmd->result = ScsiResult(DID_TRANSPORT_DISRUPTED,
SAM_STAT_BUSY);
} else
cmd->result = ScsiResult(DID_OK, 0);
if (cmd->result || lpfc_cmd->fcp_rsp->rspSnsLen) {
uint32_t *lp = (uint32_t *)cmd->sense_buffer;
lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
"0710 Iodone <%d/%d> cmd %p, error "
"x%x SNS x%x x%x Data: x%x x%x\n",
cmd->device->id, cmd->device->lun, cmd,
cmd->result, *lp, *(lp + 3), cmd->retries,
scsi_get_resid(cmd));
}
lpfc_update_stats(phba, lpfc_cmd);
result = cmd->result;
if (vport->cfg_max_scsicmpl_time &&
time_after(jiffies, lpfc_cmd->start_time +
msecs_to_jiffies(vport->cfg_max_scsicmpl_time))) {
spin_lock_irqsave(shost->host_lock, flags);
if (pnode && NLP_CHK_NODE_ACT(pnode)) {
if (pnode->cmd_qdepth >
atomic_read(&pnode->cmd_pending) &&
(atomic_read(&pnode->cmd_pending) >
LPFC_MIN_TGT_QDEPTH) &&
((cmd->cmnd[0] == READ_10) ||
(cmd->cmnd[0] == WRITE_10)))
pnode->cmd_qdepth =
atomic_read(&pnode->cmd_pending);
pnode->last_change_time = jiffies;
}
spin_unlock_irqrestore(shost->host_lock, flags);
} else if (pnode && NLP_CHK_NODE_ACT(pnode)) {
if ((pnode->cmd_qdepth < vport->cfg_tgt_queue_depth) &&
time_after(jiffies, pnode->last_change_time +
msecs_to_jiffies(LPFC_TGTQ_INTERVAL))) {
spin_lock_irqsave(shost->host_lock, flags);
depth = pnode->cmd_qdepth * LPFC_TGTQ_RAMPUP_PCENT
/ 100;
depth = depth ? depth : 1;
pnode->cmd_qdepth += depth;
if (pnode->cmd_qdepth > vport->cfg_tgt_queue_depth)
pnode->cmd_qdepth = vport->cfg_tgt_queue_depth;
pnode->last_change_time = jiffies;
spin_unlock_irqrestore(shost->host_lock, flags);
}
}
lpfc_scsi_unprep_dma_buf(phba, lpfc_cmd);
/* The sdev is not guaranteed to be valid post scsi_done upcall. */
queue_depth = cmd->device->queue_depth;
scsi_id = cmd->device->id;
cmd->scsi_done(cmd);
if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
/*
* If there is a thread waiting for command completion
* wake up the thread.
*/
spin_lock_irqsave(shost->host_lock, flags);
lpfc_cmd->pCmd = NULL;
if (lpfc_cmd->waitq)
wake_up(lpfc_cmd->waitq);
spin_unlock_irqrestore(shost->host_lock, flags);
lpfc_release_scsi_buf(phba, lpfc_cmd);
return;
}
if (!result)
lpfc_rampup_queue_depth(vport, queue_depth);
/*
* Check for queue full. If the lun is reporting queue full, then
* back off the lun queue depth to prevent target overloads.
*/
if (result == SAM_STAT_TASK_SET_FULL && pnode &&
NLP_CHK_NODE_ACT(pnode)) {
shost_for_each_device(tmp_sdev, shost) {
if (tmp_sdev->id != scsi_id)
continue;
depth = scsi_track_queue_full(tmp_sdev,
tmp_sdev->queue_depth-1);
if (depth <= 0)
continue;
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"0711 detected queue full - lun queue "
"depth adjusted to %d.\n", depth);
lpfc_send_sdev_queuedepth_change_event(phba, vport,
pnode,
tmp_sdev->lun,
depth+1, depth);
}
}
/*
* If there is a thread waiting for command completion
* wake up the thread.
*/
spin_lock_irqsave(shost->host_lock, flags);
lpfc_cmd->pCmd = NULL;
if (lpfc_cmd->waitq)
wake_up(lpfc_cmd->waitq);
spin_unlock_irqrestore(shost->host_lock, flags);
lpfc_release_scsi_buf(phba, lpfc_cmd);
}
/**
* lpfc_fcpcmd_to_iocb - copy the fcp_cmd data into the IOCB
* @data: A pointer to the immediate command data portion of the IOCB.
* @fcp_cmnd: The FCP Command that is provided by the SCSI layer.
*
* The routine copies the entire FCP command from @fcp_cmnd to @data while
* byte swapping the data to big endian format for transmission on the wire.
**/
static void
lpfc_fcpcmd_to_iocb(uint8_t *data, struct fcp_cmnd *fcp_cmnd)
{
int i, j;
for (i = 0, j = 0; i < sizeof(struct fcp_cmnd);
i += sizeof(uint32_t), j++) {
((uint32_t *)data)[j] = cpu_to_be32(((uint32_t *)fcp_cmnd)[j]);
}
}
/**
* lpfc_scsi_prep_cmnd - Wrapper func for convert scsi cmnd to FCP info unit
* @vport: The virtual port for which this call is being executed.
* @lpfc_cmd: The scsi command which needs to send.
* @pnode: Pointer to lpfc_nodelist.
*
* This routine initializes fcp_cmnd and iocb data structure from scsi command
* to transfer for device with SLI3 interface spec.
**/
static void
lpfc_scsi_prep_cmnd(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
struct lpfc_nodelist *pnode)
{
struct lpfc_hba *phba = vport->phba;
struct scsi_cmnd *scsi_cmnd = lpfc_cmd->pCmd;
struct fcp_cmnd *fcp_cmnd = lpfc_cmd->fcp_cmnd;
IOCB_t *iocb_cmd = &lpfc_cmd->cur_iocbq.iocb;
struct lpfc_iocbq *piocbq = &(lpfc_cmd->cur_iocbq);
int datadir = scsi_cmnd->sc_data_direction;
char tag[2];
if (!pnode || !NLP_CHK_NODE_ACT(pnode))
return;
lpfc_cmd->fcp_rsp->rspSnsLen = 0;
/* clear task management bits */
lpfc_cmd->fcp_cmnd->fcpCntl2 = 0;
int_to_scsilun(lpfc_cmd->pCmd->device->lun,
&lpfc_cmd->fcp_cmnd->fcp_lun);
memcpy(&fcp_cmnd->fcpCdb[0], scsi_cmnd->cmnd, 16);
if (scsi_populate_tag_msg(scsi_cmnd, tag)) {
switch (tag[0]) {
case HEAD_OF_QUEUE_TAG:
fcp_cmnd->fcpCntl1 = HEAD_OF_Q;
break;
case ORDERED_QUEUE_TAG:
fcp_cmnd->fcpCntl1 = ORDERED_Q;
break;
default:
fcp_cmnd->fcpCntl1 = SIMPLE_Q;
break;
}
} else
fcp_cmnd->fcpCntl1 = 0;
/*
* There are three possibilities here - use scatter-gather segment, use
* the single mapping, or neither. Start the lpfc command prep by
* bumping the bpl beyond the fcp_cmnd and fcp_rsp regions to the first
* data bde entry.
*/
if (scsi_sg_count(scsi_cmnd)) {
if (datadir == DMA_TO_DEVICE) {
iocb_cmd->ulpCommand = CMD_FCP_IWRITE64_CR;
if (phba->sli_rev < LPFC_SLI_REV4) {
iocb_cmd->un.fcpi.fcpi_parm = 0;
iocb_cmd->ulpPU = 0;
} else
iocb_cmd->ulpPU = PARM_READ_CHECK;
fcp_cmnd->fcpCntl3 = WRITE_DATA;
phba->fc4OutputRequests++;
} else {
iocb_cmd->ulpCommand = CMD_FCP_IREAD64_CR;
iocb_cmd->ulpPU = PARM_READ_CHECK;
fcp_cmnd->fcpCntl3 = READ_DATA;
phba->fc4InputRequests++;
}
} else {
iocb_cmd->ulpCommand = CMD_FCP_ICMND64_CR;
iocb_cmd->un.fcpi.fcpi_parm = 0;
iocb_cmd->ulpPU = 0;
fcp_cmnd->fcpCntl3 = 0;
phba->fc4ControlRequests++;
}
if (phba->sli_rev == 3 &&
!(phba->sli3_options & LPFC_SLI3_BG_ENABLED))
lpfc_fcpcmd_to_iocb(iocb_cmd->unsli3.fcp_ext.icd, fcp_cmnd);
/*
* Finish initializing those IOCB fields that are independent
* of the scsi_cmnd request_buffer
*/
piocbq->iocb.ulpContext = pnode->nlp_rpi;
if (phba->sli_rev == LPFC_SLI_REV4)
piocbq->iocb.ulpContext =
phba->sli4_hba.rpi_ids[pnode->nlp_rpi];
if (pnode->nlp_fcp_info & NLP_FCP_2_DEVICE)
piocbq->iocb.ulpFCP2Rcvy = 1;
else
piocbq->iocb.ulpFCP2Rcvy = 0;
piocbq->iocb.ulpClass = (pnode->nlp_fcp_info & 0x0f);
piocbq->context1 = lpfc_cmd;
piocbq->iocb_cmpl = lpfc_scsi_cmd_iocb_cmpl;
piocbq->iocb.ulpTimeout = lpfc_cmd->timeout;
piocbq->vport = vport;
}
/**
* lpfc_scsi_prep_task_mgmt_cmd - Convert SLI3 scsi TM cmd to FCP info unit
* @vport: The virtual port for which this call is being executed.
* @lpfc_cmd: Pointer to lpfc_scsi_buf data structure.
* @lun: Logical unit number.
* @task_mgmt_cmd: SCSI task management command.
*
* This routine creates FCP information unit corresponding to @task_mgmt_cmd
* for device with SLI-3 interface spec.
*
* Return codes:
* 0 - Error
* 1 - Success
**/
static int
lpfc_scsi_prep_task_mgmt_cmd(struct lpfc_vport *vport,
struct lpfc_scsi_buf *lpfc_cmd,
unsigned int lun,
uint8_t task_mgmt_cmd)
{
struct lpfc_iocbq *piocbq;
IOCB_t *piocb;
struct fcp_cmnd *fcp_cmnd;
struct lpfc_rport_data *rdata = lpfc_cmd->rdata;
struct lpfc_nodelist *ndlp = rdata->pnode;
if (!ndlp || !NLP_CHK_NODE_ACT(ndlp) ||
ndlp->nlp_state != NLP_STE_MAPPED_NODE)
return 0;
piocbq = &(lpfc_cmd->cur_iocbq);
piocbq->vport = vport;
piocb = &piocbq->iocb;
fcp_cmnd = lpfc_cmd->fcp_cmnd;
/* Clear out any old data in the FCP command area */
memset(fcp_cmnd, 0, sizeof(struct fcp_cmnd));
int_to_scsilun(lun, &fcp_cmnd->fcp_lun);
fcp_cmnd->fcpCntl2 = task_mgmt_cmd;
if (vport->phba->sli_rev == 3 &&
!(vport->phba->sli3_options & LPFC_SLI3_BG_ENABLED))
lpfc_fcpcmd_to_iocb(piocb->unsli3.fcp_ext.icd, fcp_cmnd);
piocb->ulpCommand = CMD_FCP_ICMND64_CR;
piocb->ulpContext = ndlp->nlp_rpi;
if (vport->phba->sli_rev == LPFC_SLI_REV4) {
piocb->ulpContext =
vport->phba->sli4_hba.rpi_ids[ndlp->nlp_rpi];
}
if (ndlp->nlp_fcp_info & NLP_FCP_2_DEVICE) {
piocb->ulpFCP2Rcvy = 1;
}
piocb->ulpClass = (ndlp->nlp_fcp_info & 0x0f);
/* ulpTimeout is only one byte */
if (lpfc_cmd->timeout > 0xff) {
/*
* Do not timeout the command at the firmware level.
* The driver will provide the timeout mechanism.
*/
piocb->ulpTimeout = 0;
} else
piocb->ulpTimeout = lpfc_cmd->timeout;
if (vport->phba->sli_rev == LPFC_SLI_REV4)
lpfc_sli4_set_rsp_sgl_last(vport->phba, lpfc_cmd);
return 1;
}
/**
* lpfc_scsi_api_table_setup - Set up scsi api function jump table
* @phba: The hba struct for which this call is being executed.
* @dev_grp: The HBA PCI-Device group number.
*
* This routine sets up the SCSI interface API function jump table in @phba
* struct.
* Returns: 0 - success, -ENODEV - failure.
**/
int
lpfc_scsi_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
{
phba->lpfc_scsi_unprep_dma_buf = lpfc_scsi_unprep_dma_buf;
phba->lpfc_scsi_prep_cmnd = lpfc_scsi_prep_cmnd;
switch (dev_grp) {
case LPFC_PCI_DEV_LP:
phba->lpfc_new_scsi_buf = lpfc_new_scsi_buf_s3;
phba->lpfc_scsi_prep_dma_buf = lpfc_scsi_prep_dma_buf_s3;
phba->lpfc_release_scsi_buf = lpfc_release_scsi_buf_s3;
phba->lpfc_get_scsi_buf = lpfc_get_scsi_buf_s3;
break;
case LPFC_PCI_DEV_OC:
phba->lpfc_new_scsi_buf = lpfc_new_scsi_buf_s4;
phba->lpfc_scsi_prep_dma_buf = lpfc_scsi_prep_dma_buf_s4;
phba->lpfc_release_scsi_buf = lpfc_release_scsi_buf_s4;
phba->lpfc_get_scsi_buf = lpfc_get_scsi_buf_s4;
break;
default:
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"1418 Invalid HBA PCI-device group: 0x%x\n",
dev_grp);
return -ENODEV;
break;
}
phba->lpfc_rampdown_queue_depth = lpfc_rampdown_queue_depth;
phba->lpfc_scsi_cmd_iocb_cmpl = lpfc_scsi_cmd_iocb_cmpl;
return 0;
}
/**
* lpfc_taskmgmt_def_cmpl - IOCB completion routine for task management command
* @phba: The Hba for which this call is being executed.
* @cmdiocbq: Pointer to lpfc_iocbq data structure.
* @rspiocbq: Pointer to lpfc_iocbq data structure.
*
* This routine is IOCB completion routine for device reset and target reset
* routine. This routine release scsi buffer associated with lpfc_cmd.
**/
static void
lpfc_tskmgmt_def_cmpl(struct lpfc_hba *phba,
struct lpfc_iocbq *cmdiocbq,
struct lpfc_iocbq *rspiocbq)
{
struct lpfc_scsi_buf *lpfc_cmd =
(struct lpfc_scsi_buf *) cmdiocbq->context1;
if (lpfc_cmd)
lpfc_release_scsi_buf(phba, lpfc_cmd);
return;
}
/**
* lpfc_info - Info entry point of scsi_host_template data structure
* @host: The scsi host for which this call is being executed.
*
* This routine provides module information about hba.
*
* Reutrn code:
* Pointer to char - Success.
**/
const char *
lpfc_info(struct Scsi_Host *host)
{
struct lpfc_vport *vport = (struct lpfc_vport *) host->hostdata;
struct lpfc_hba *phba = vport->phba;
int len;
static char lpfcinfobuf[384];
memset(lpfcinfobuf,0,384);
if (phba && phba->pcidev){
strncpy(lpfcinfobuf, phba->ModelDesc, 256);
len = strlen(lpfcinfobuf);
snprintf(lpfcinfobuf + len,
384-len,
" on PCI bus %02x device %02x irq %d",
phba->pcidev->bus->number,
phba->pcidev->devfn,
phba->pcidev->irq);
len = strlen(lpfcinfobuf);
if (phba->Port[0]) {
snprintf(lpfcinfobuf + len,
384-len,
" port %s",
phba->Port);
}
len = strlen(lpfcinfobuf);
if (phba->sli4_hba.link_state.logical_speed) {
snprintf(lpfcinfobuf + len,
384-len,
" Logical Link Speed: %d Mbps",
phba->sli4_hba.link_state.logical_speed * 10);
}
}
return lpfcinfobuf;
}
/**
* lpfc_poll_rearm_time - Routine to modify fcp_poll timer of hba
* @phba: The Hba for which this call is being executed.
*
* This routine modifies fcp_poll_timer field of @phba by cfg_poll_tmo.
* The default value of cfg_poll_tmo is 10 milliseconds.
**/
static __inline__ void lpfc_poll_rearm_timer(struct lpfc_hba * phba)
{
unsigned long poll_tmo_expires =
(jiffies + msecs_to_jiffies(phba->cfg_poll_tmo));
if (phba->sli.ring[LPFC_FCP_RING].txcmplq_cnt)
mod_timer(&phba->fcp_poll_timer,
poll_tmo_expires);
}
/**
* lpfc_poll_start_timer - Routine to start fcp_poll_timer of HBA
* @phba: The Hba for which this call is being executed.
*
* This routine starts the fcp_poll_timer of @phba.
**/
void lpfc_poll_start_timer(struct lpfc_hba * phba)
{
lpfc_poll_rearm_timer(phba);
}
/**
* lpfc_poll_timeout - Restart polling timer
* @ptr: Map to lpfc_hba data structure pointer.
*
* This routine restarts fcp_poll timer, when FCP ring polling is enable
* and FCP Ring interrupt is disable.
**/
void lpfc_poll_timeout(unsigned long ptr)
{
struct lpfc_hba *phba = (struct lpfc_hba *) ptr;
if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
lpfc_sli_handle_fast_ring_event(phba,
&phba->sli.ring[LPFC_FCP_RING], HA_R0RE_REQ);
if (phba->cfg_poll & DISABLE_FCP_RING_INT)
lpfc_poll_rearm_timer(phba);
}
}
/**
* lpfc_queuecommand - scsi_host_template queuecommand entry point
* @cmnd: Pointer to scsi_cmnd data structure.
* @done: Pointer to done routine.
*
* Driver registers this routine to scsi midlayer to submit a @cmd to process.
* This routine prepares an IOCB from scsi command and provides to firmware.
* The @done callback is invoked after driver finished processing the command.
*
* Return value :
* 0 - Success
* SCSI_MLQUEUE_HOST_BUSY - Block all devices served by this host temporarily.
**/
static int
lpfc_queuecommand_lck(struct scsi_cmnd *cmnd, void (*done) (struct scsi_cmnd *))
{
struct Scsi_Host *shost = cmnd->device->host;
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
struct lpfc_rport_data *rdata = cmnd->device->hostdata;
struct lpfc_nodelist *ndlp;
struct lpfc_scsi_buf *lpfc_cmd;
struct fc_rport *rport = starget_to_rport(scsi_target(cmnd->device));
int err;
err = fc_remote_port_chkready(rport);
if (err) {
cmnd->result = err;
goto out_fail_command;
}
ndlp = rdata->pnode;
if (!(phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
scsi_get_prot_op(cmnd) != SCSI_PROT_NORMAL) {
lpfc_printf_log(phba, KERN_ERR, LOG_BG,
"9058 BLKGRD: ERROR: rcvd protected cmd:%02x"
" op:%02x str=%s without registering for"
" BlockGuard - Rejecting command\n",
cmnd->cmnd[0], scsi_get_prot_op(cmnd),
dif_op_str[scsi_get_prot_op(cmnd)]);
goto out_fail_command;
}
/*
* Catch race where our node has transitioned, but the
* transport is still transitioning.
*/
if (!ndlp || !NLP_CHK_NODE_ACT(ndlp)) {
cmnd->result = ScsiResult(DID_IMM_RETRY, 0);
goto out_fail_command;
}
if (atomic_read(&ndlp->cmd_pending) >= ndlp->cmd_qdepth)
goto out_tgt_busy;
lpfc_cmd = lpfc_get_scsi_buf(phba, ndlp);
if (lpfc_cmd == NULL) {
lpfc_rampdown_queue_depth(phba);
lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
"0707 driver's buffer pool is empty, "
"IO busied\n");
goto out_host_busy;
}
/*
* Store the midlayer's command structure for the completion phase
* and complete the command initialization.
*/
lpfc_cmd->pCmd = cmnd;
lpfc_cmd->rdata = rdata;
lpfc_cmd->timeout = 0;
lpfc_cmd->start_time = jiffies;
cmnd->host_scribble = (unsigned char *)lpfc_cmd;
cmnd->scsi_done = done;
if (scsi_get_prot_op(cmnd) != SCSI_PROT_NORMAL) {
if (vport->phba->cfg_enable_bg) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9033 BLKGRD: rcvd protected cmd:%02x op:%02x "
"str=%s\n",
cmnd->cmnd[0], scsi_get_prot_op(cmnd),
dif_op_str[scsi_get_prot_op(cmnd)]);
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9034 BLKGRD: CDB: %02x %02x %02x %02x %02x "
"%02x %02x %02x %02x %02x\n",
cmnd->cmnd[0], cmnd->cmnd[1], cmnd->cmnd[2],
cmnd->cmnd[3], cmnd->cmnd[4], cmnd->cmnd[5],
cmnd->cmnd[6], cmnd->cmnd[7], cmnd->cmnd[8],
cmnd->cmnd[9]);
if (cmnd->cmnd[0] == READ_10)
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9035 BLKGRD: READ @ sector %llu, "
"count %u\n",
(unsigned long long)scsi_get_lba(cmnd),
blk_rq_sectors(cmnd->request));
else if (cmnd->cmnd[0] == WRITE_10)
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9036 BLKGRD: WRITE @ sector %llu, "
"count %u cmd=%p\n",
(unsigned long long)scsi_get_lba(cmnd),
blk_rq_sectors(cmnd->request),
cmnd);
}
err = lpfc_bg_scsi_prep_dma_buf(phba, lpfc_cmd);
} else {
if (vport->phba->cfg_enable_bg) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9038 BLKGRD: rcvd unprotected cmd:"
"%02x op:%02x str=%s\n",
cmnd->cmnd[0], scsi_get_prot_op(cmnd),
dif_op_str[scsi_get_prot_op(cmnd)]);
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9039 BLKGRD: CDB: %02x %02x %02x "
"%02x %02x %02x %02x %02x %02x %02x\n",
cmnd->cmnd[0], cmnd->cmnd[1],
cmnd->cmnd[2], cmnd->cmnd[3],
cmnd->cmnd[4], cmnd->cmnd[5],
cmnd->cmnd[6], cmnd->cmnd[7],
cmnd->cmnd[8], cmnd->cmnd[9]);
if (cmnd->cmnd[0] == READ_10)
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9040 dbg: READ @ sector %llu, "
"count %u\n",
(unsigned long long)scsi_get_lba(cmnd),
blk_rq_sectors(cmnd->request));
else if (cmnd->cmnd[0] == WRITE_10)
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9041 dbg: WRITE @ sector %llu, "
"count %u cmd=%p\n",
(unsigned long long)scsi_get_lba(cmnd),
blk_rq_sectors(cmnd->request), cmnd);
else
lpfc_printf_vlog(vport, KERN_WARNING, LOG_BG,
"9042 dbg: parser not implemented\n");
}
err = lpfc_scsi_prep_dma_buf(phba, lpfc_cmd);
}
if (err)
goto out_host_busy_free_buf;
lpfc_scsi_prep_cmnd(vport, lpfc_cmd, ndlp);
atomic_inc(&ndlp->cmd_pending);
err = lpfc_sli_issue_iocb(phba, LPFC_FCP_RING,
&lpfc_cmd->cur_iocbq, SLI_IOCB_RET_IOCB);
if (err) {
atomic_dec(&ndlp->cmd_pending);
goto out_host_busy_free_buf;
}
if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
spin_unlock(shost->host_lock);
lpfc_sli_handle_fast_ring_event(phba,
&phba->sli.ring[LPFC_FCP_RING], HA_R0RE_REQ);
spin_lock(shost->host_lock);
if (phba->cfg_poll & DISABLE_FCP_RING_INT)
lpfc_poll_rearm_timer(phba);
}
return 0;
out_host_busy_free_buf:
lpfc_scsi_unprep_dma_buf(phba, lpfc_cmd);
lpfc_release_scsi_buf(phba, lpfc_cmd);
out_host_busy:
return SCSI_MLQUEUE_HOST_BUSY;
out_tgt_busy:
return SCSI_MLQUEUE_TARGET_BUSY;
out_fail_command:
done(cmnd);
return 0;
}
static DEF_SCSI_QCMD(lpfc_queuecommand)
/**
* lpfc_abort_handler - scsi_host_template eh_abort_handler entry point
* @cmnd: Pointer to scsi_cmnd data structure.
*
* This routine aborts @cmnd pending in base driver.
*
* Return code :
* 0x2003 - Error
* 0x2002 - Success
**/
static int
lpfc_abort_handler(struct scsi_cmnd *cmnd)
{
struct Scsi_Host *shost = cmnd->device->host;
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
struct lpfc_iocbq *iocb;
struct lpfc_iocbq *abtsiocb;
struct lpfc_scsi_buf *lpfc_cmd;
IOCB_t *cmd, *icmd;
int ret = SUCCESS;
DECLARE_WAIT_QUEUE_HEAD_ONSTACK(waitq);
ret = fc_block_scsi_eh(cmnd);
if (ret)
return ret;
lpfc_cmd = (struct lpfc_scsi_buf *)cmnd->host_scribble;
if (!lpfc_cmd) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"2873 SCSI Layer I/O Abort Request IO CMPL Status "
"x%x ID %d LUN %d\n",
ret, cmnd->device->id, cmnd->device->lun);
return SUCCESS;
}
/*
* If pCmd field of the corresponding lpfc_scsi_buf structure
* points to a different SCSI command, then the driver has
* already completed this command, but the midlayer did not
* see the completion before the eh fired. Just return
* SUCCESS.
*/
iocb = &lpfc_cmd->cur_iocbq;
if (lpfc_cmd->pCmd != cmnd)
goto out;
BUG_ON(iocb->context1 != lpfc_cmd);
abtsiocb = lpfc_sli_get_iocbq(phba);
if (abtsiocb == NULL) {
ret = FAILED;
goto out;
}
/*
* The scsi command can not be in txq and it is in flight because the
* pCmd is still pointig at the SCSI command we have to abort. There
* is no need to search the txcmplq. Just send an abort to the FW.
*/
cmd = &iocb->iocb;
icmd = &abtsiocb->iocb;
icmd->un.acxri.abortType = ABORT_TYPE_ABTS;
icmd->un.acxri.abortContextTag = cmd->ulpContext;
if (phba->sli_rev == LPFC_SLI_REV4)
icmd->un.acxri.abortIoTag = iocb->sli4_xritag;
else
icmd->un.acxri.abortIoTag = cmd->ulpIoTag;
icmd->ulpLe = 1;
icmd->ulpClass = cmd->ulpClass;
/* ABTS WQE must go to the same WQ as the WQE to be aborted */
abtsiocb->fcp_wqidx = iocb->fcp_wqidx;
abtsiocb->iocb_flag |= LPFC_USE_FCPWQIDX;
if (lpfc_is_link_up(phba))
icmd->ulpCommand = CMD_ABORT_XRI_CN;
else
icmd->ulpCommand = CMD_CLOSE_XRI_CN;
abtsiocb->iocb_cmpl = lpfc_sli_abort_fcp_cmpl;
abtsiocb->vport = vport;
if (lpfc_sli_issue_iocb(phba, LPFC_FCP_RING, abtsiocb, 0) ==
IOCB_ERROR) {
lpfc_sli_release_iocbq(phba, abtsiocb);
ret = FAILED;
goto out;
}
if (phba->cfg_poll & DISABLE_FCP_RING_INT)
lpfc_sli_handle_fast_ring_event(phba,
&phba->sli.ring[LPFC_FCP_RING], HA_R0RE_REQ);
lpfc_cmd->waitq = &waitq;
/* Wait for abort to complete */
wait_event_timeout(waitq,
(lpfc_cmd->pCmd != cmnd),
(2*vport->cfg_devloss_tmo*HZ));
spin_lock_irq(shost->host_lock);
lpfc_cmd->waitq = NULL;
spin_unlock_irq(shost->host_lock);
if (lpfc_cmd->pCmd == cmnd) {
ret = FAILED;
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0748 abort handler timed out waiting "
"for abort to complete: ret %#x, ID %d, "
"LUN %d\n",
ret, cmnd->device->id, cmnd->device->lun);
}
out:
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"0749 SCSI Layer I/O Abort Request Status x%x ID %d "
"LUN %d\n", ret, cmnd->device->id,
cmnd->device->lun);
return ret;
}
static char *
lpfc_taskmgmt_name(uint8_t task_mgmt_cmd)
{
switch (task_mgmt_cmd) {
case FCP_ABORT_TASK_SET:
return "ABORT_TASK_SET";
case FCP_CLEAR_TASK_SET:
return "FCP_CLEAR_TASK_SET";
case FCP_BUS_RESET:
return "FCP_BUS_RESET";
case FCP_LUN_RESET:
return "FCP_LUN_RESET";
case FCP_TARGET_RESET:
return "FCP_TARGET_RESET";
case FCP_CLEAR_ACA:
return "FCP_CLEAR_ACA";
case FCP_TERMINATE_TASK:
return "FCP_TERMINATE_TASK";
default:
return "unknown";
}
}
/**
* lpfc_send_taskmgmt - Generic SCSI Task Mgmt Handler
* @vport: The virtual port for which this call is being executed.
* @rdata: Pointer to remote port local data
* @tgt_id: Target ID of remote device.
* @lun_id: Lun number for the TMF
* @task_mgmt_cmd: type of TMF to send
*
* This routine builds and sends a TMF (SCSI Task Mgmt Function) to
* a remote port.
*
* Return Code:
* 0x2003 - Error
* 0x2002 - Success.
**/
static int
lpfc_send_taskmgmt(struct lpfc_vport *vport, struct lpfc_rport_data *rdata,
unsigned tgt_id, unsigned int lun_id,
uint8_t task_mgmt_cmd)
{
struct lpfc_hba *phba = vport->phba;
struct lpfc_scsi_buf *lpfc_cmd;
struct lpfc_iocbq *iocbq;
struct lpfc_iocbq *iocbqrsp;
struct lpfc_nodelist *pnode = rdata->pnode;
int ret;
int status;
if (!pnode || !NLP_CHK_NODE_ACT(pnode))
return FAILED;
lpfc_cmd = lpfc_get_scsi_buf(phba, rdata->pnode);
if (lpfc_cmd == NULL)
return FAILED;
lpfc_cmd->timeout = 60;
lpfc_cmd->rdata = rdata;
status = lpfc_scsi_prep_task_mgmt_cmd(vport, lpfc_cmd, lun_id,
task_mgmt_cmd);
if (!status) {
lpfc_release_scsi_buf(phba, lpfc_cmd);
return FAILED;
}
iocbq = &lpfc_cmd->cur_iocbq;
iocbqrsp = lpfc_sli_get_iocbq(phba);
if (iocbqrsp == NULL) {
lpfc_release_scsi_buf(phba, lpfc_cmd);
return FAILED;
}
lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
"0702 Issue %s to TGT %d LUN %d "
"rpi x%x nlp_flag x%x Data: x%x x%x\n",
lpfc_taskmgmt_name(task_mgmt_cmd), tgt_id, lun_id,
pnode->nlp_rpi, pnode->nlp_flag, iocbq->sli4_xritag,
iocbq->iocb_flag);
status = lpfc_sli_issue_iocb_wait(phba, LPFC_FCP_RING,
iocbq, iocbqrsp, lpfc_cmd->timeout);
if (status != IOCB_SUCCESS) {
if (status == IOCB_TIMEDOUT) {
iocbq->iocb_cmpl = lpfc_tskmgmt_def_cmpl;
ret = TIMEOUT_ERROR;
} else
ret = FAILED;
lpfc_cmd->status = IOSTAT_DRIVER_REJECT;
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0727 TMF %s to TGT %d LUN %d failed (%d, %d) "
"iocb_flag x%x\n",
lpfc_taskmgmt_name(task_mgmt_cmd),
tgt_id, lun_id, iocbqrsp->iocb.ulpStatus,
iocbqrsp->iocb.un.ulpWord[4],
iocbq->iocb_flag);
} else if (status == IOCB_BUSY)
ret = FAILED;
else
ret = SUCCESS;
lpfc_sli_release_iocbq(phba, iocbqrsp);
if (ret != TIMEOUT_ERROR)
lpfc_release_scsi_buf(phba, lpfc_cmd);
return ret;
}
/**
* lpfc_chk_tgt_mapped -
* @vport: The virtual port to check on
* @cmnd: Pointer to scsi_cmnd data structure.
*
* This routine delays until the scsi target (aka rport) for the
* command exists (is present and logged in) or we declare it non-existent.
*
* Return code :
* 0x2003 - Error
* 0x2002 - Success
**/
static int
lpfc_chk_tgt_mapped(struct lpfc_vport *vport, struct scsi_cmnd *cmnd)
{
struct lpfc_rport_data *rdata = cmnd->device->hostdata;
struct lpfc_nodelist *pnode;
unsigned long later;
if (!rdata) {
lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
"0797 Tgt Map rport failure: rdata x%p\n", rdata);
return FAILED;
}
pnode = rdata->pnode;
/*
* If target is not in a MAPPED state, delay until
* target is rediscovered or devloss timeout expires.
*/
later = msecs_to_jiffies(2 * vport->cfg_devloss_tmo * 1000) + jiffies;
while (time_after(later, jiffies)) {
if (!pnode || !NLP_CHK_NODE_ACT(pnode))
return FAILED;
if (pnode->nlp_state == NLP_STE_MAPPED_NODE)
return SUCCESS;
schedule_timeout_uninterruptible(msecs_to_jiffies(500));
rdata = cmnd->device->hostdata;
if (!rdata)
return FAILED;
pnode = rdata->pnode;
}
if (!pnode || !NLP_CHK_NODE_ACT(pnode) ||
(pnode->nlp_state != NLP_STE_MAPPED_NODE))
return FAILED;
return SUCCESS;
}
/**
* lpfc_reset_flush_io_context -
* @vport: The virtual port (scsi_host) for the flush context
* @tgt_id: If aborting by Target contect - specifies the target id
* @lun_id: If aborting by Lun context - specifies the lun id
* @context: specifies the context level to flush at.
*
* After a reset condition via TMF, we need to flush orphaned i/o
* contexts from the adapter. This routine aborts any contexts
* outstanding, then waits for their completions. The wait is
* bounded by devloss_tmo though.
*
* Return code :
* 0x2003 - Error
* 0x2002 - Success
**/
static int
lpfc_reset_flush_io_context(struct lpfc_vport *vport, uint16_t tgt_id,
uint64_t lun_id, lpfc_ctx_cmd context)
{
struct lpfc_hba *phba = vport->phba;
unsigned long later;
int cnt;
cnt = lpfc_sli_sum_iocb(vport, tgt_id, lun_id, context);
if (cnt)
lpfc_sli_abort_iocb(vport, &phba->sli.ring[phba->sli.fcp_ring],
tgt_id, lun_id, context);
later = msecs_to_jiffies(2 * vport->cfg_devloss_tmo * 1000) + jiffies;
while (time_after(later, jiffies) && cnt) {
schedule_timeout_uninterruptible(msecs_to_jiffies(20));
cnt = lpfc_sli_sum_iocb(vport, tgt_id, lun_id, context);
}
if (cnt) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0724 I/O flush failure for context %s : cnt x%x\n",
((context == LPFC_CTX_LUN) ? "LUN" :
((context == LPFC_CTX_TGT) ? "TGT" :
((context == LPFC_CTX_HOST) ? "HOST" : "Unknown"))),
cnt);
return FAILED;
}
return SUCCESS;
}
/**
* lpfc_device_reset_handler - scsi_host_template eh_device_reset entry point
* @cmnd: Pointer to scsi_cmnd data structure.
*
* This routine does a device reset by sending a LUN_RESET task management
* command.
*
* Return code :
* 0x2003 - Error
* 0x2002 - Success
**/
static int
lpfc_device_reset_handler(struct scsi_cmnd *cmnd)
{
struct Scsi_Host *shost = cmnd->device->host;
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_rport_data *rdata = cmnd->device->hostdata;
struct lpfc_nodelist *pnode;
unsigned tgt_id = cmnd->device->id;
unsigned int lun_id = cmnd->device->lun;
struct lpfc_scsi_event_header scsi_event;
int status;
if (!rdata) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0798 Device Reset rport failure: rdata x%p\n", rdata);
return FAILED;
}
pnode = rdata->pnode;
status = fc_block_scsi_eh(cmnd);
if (status)
return status;
status = lpfc_chk_tgt_mapped(vport, cmnd);
if (status == FAILED) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0721 Device Reset rport failure: rdata x%p\n", rdata);
return FAILED;
}
scsi_event.event_type = FC_REG_SCSI_EVENT;
scsi_event.subcategory = LPFC_EVENT_LUNRESET;
scsi_event.lun = lun_id;
memcpy(scsi_event.wwpn, &pnode->nlp_portname, sizeof(struct lpfc_name));
memcpy(scsi_event.wwnn, &pnode->nlp_nodename, sizeof(struct lpfc_name));
fc_host_post_vendor_event(shost, fc_get_event_number(),
sizeof(scsi_event), (char *)&scsi_event, LPFC_NL_VENDOR_ID);
status = lpfc_send_taskmgmt(vport, rdata, tgt_id, lun_id,
FCP_LUN_RESET);
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0713 SCSI layer issued Device Reset (%d, %d) "
"return x%x\n", tgt_id, lun_id, status);
/*
* We have to clean up i/o as : they may be orphaned by the TMF;
* or if the TMF failed, they may be in an indeterminate state.
* So, continue on.
* We will report success if all the i/o aborts successfully.
*/
status = lpfc_reset_flush_io_context(vport, tgt_id, lun_id,
LPFC_CTX_LUN);
return status;
}
/**
* lpfc_target_reset_handler - scsi_host_template eh_target_reset entry point
* @cmnd: Pointer to scsi_cmnd data structure.
*
* This routine does a target reset by sending a TARGET_RESET task management
* command.
*
* Return code :
* 0x2003 - Error
* 0x2002 - Success
**/
static int
lpfc_target_reset_handler(struct scsi_cmnd *cmnd)
{
struct Scsi_Host *shost = cmnd->device->host;
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_rport_data *rdata = cmnd->device->hostdata;
struct lpfc_nodelist *pnode;
unsigned tgt_id = cmnd->device->id;
unsigned int lun_id = cmnd->device->lun;
struct lpfc_scsi_event_header scsi_event;
int status;
if (!rdata) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0799 Target Reset rport failure: rdata x%p\n", rdata);
return FAILED;
}
pnode = rdata->pnode;
status = fc_block_scsi_eh(cmnd);
if (status)
return status;
status = lpfc_chk_tgt_mapped(vport, cmnd);
if (status == FAILED) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0722 Target Reset rport failure: rdata x%p\n", rdata);
return FAILED;
}
scsi_event.event_type = FC_REG_SCSI_EVENT;
scsi_event.subcategory = LPFC_EVENT_TGTRESET;
scsi_event.lun = 0;
memcpy(scsi_event.wwpn, &pnode->nlp_portname, sizeof(struct lpfc_name));
memcpy(scsi_event.wwnn, &pnode->nlp_nodename, sizeof(struct lpfc_name));
fc_host_post_vendor_event(shost, fc_get_event_number(),
sizeof(scsi_event), (char *)&scsi_event, LPFC_NL_VENDOR_ID);
status = lpfc_send_taskmgmt(vport, rdata, tgt_id, lun_id,
FCP_TARGET_RESET);
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0723 SCSI layer issued Target Reset (%d, %d) "
"return x%x\n", tgt_id, lun_id, status);
/*
* We have to clean up i/o as : they may be orphaned by the TMF;
* or if the TMF failed, they may be in an indeterminate state.
* So, continue on.
* We will report success if all the i/o aborts successfully.
*/
status = lpfc_reset_flush_io_context(vport, tgt_id, lun_id,
LPFC_CTX_TGT);
return status;
}
/**
* lpfc_bus_reset_handler - scsi_host_template eh_bus_reset_handler entry point
* @cmnd: Pointer to scsi_cmnd data structure.
*
* This routine does target reset to all targets on @cmnd->device->host.
* This emulates Parallel SCSI Bus Reset Semantics.
*
* Return code :
* 0x2003 - Error
* 0x2002 - Success
**/
static int
lpfc_bus_reset_handler(struct scsi_cmnd *cmnd)
{
struct Scsi_Host *shost = cmnd->device->host;
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_nodelist *ndlp = NULL;
struct lpfc_scsi_event_header scsi_event;
int match;
int ret = SUCCESS, status, i;
scsi_event.event_type = FC_REG_SCSI_EVENT;
scsi_event.subcategory = LPFC_EVENT_BUSRESET;
scsi_event.lun = 0;
memcpy(scsi_event.wwpn, &vport->fc_portname, sizeof(struct lpfc_name));
memcpy(scsi_event.wwnn, &vport->fc_nodename, sizeof(struct lpfc_name));
fc_host_post_vendor_event(shost, fc_get_event_number(),
sizeof(scsi_event), (char *)&scsi_event, LPFC_NL_VENDOR_ID);
ret = fc_block_scsi_eh(cmnd);
if (ret)
return ret;
/*
* Since the driver manages a single bus device, reset all
* targets known to the driver. Should any target reset
* fail, this routine returns failure to the midlayer.
*/
for (i = 0; i < LPFC_MAX_TARGET; i++) {
/* Search for mapped node by target ID */
match = 0;
spin_lock_irq(shost->host_lock);
list_for_each_entry(ndlp, &vport->fc_nodes, nlp_listp) {
if (!NLP_CHK_NODE_ACT(ndlp))
continue;
if (ndlp->nlp_state == NLP_STE_MAPPED_NODE &&
ndlp->nlp_sid == i &&
ndlp->rport) {
match = 1;
break;
}
}
spin_unlock_irq(shost->host_lock);
if (!match)
continue;
status = lpfc_send_taskmgmt(vport, ndlp->rport->dd_data,
i, 0, FCP_TARGET_RESET);
if (status != SUCCESS) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0700 Bus Reset on target %d failed\n",
i);
ret = FAILED;
}
}
/*
* We have to clean up i/o as : they may be orphaned by the TMFs
* above; or if any of the TMFs failed, they may be in an
* indeterminate state.
* We will report success if all the i/o aborts successfully.
*/
status = lpfc_reset_flush_io_context(vport, 0, 0, LPFC_CTX_HOST);
if (status != SUCCESS)
ret = FAILED;
lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
"0714 SCSI layer issued Bus Reset Data: x%x\n", ret);
return ret;
}
/**
* lpfc_slave_alloc - scsi_host_template slave_alloc entry point
* @sdev: Pointer to scsi_device.
*
* This routine populates the cmds_per_lun count + 2 scsi_bufs into this host's
* globally available list of scsi buffers. This routine also makes sure scsi
* buffer is not allocated more than HBA limit conveyed to midlayer. This list
* of scsi buffer exists for the lifetime of the driver.
*
* Return codes:
* non-0 - Error
* 0 - Success
**/
static int
lpfc_slave_alloc(struct scsi_device *sdev)
{
struct lpfc_vport *vport = (struct lpfc_vport *) sdev->host->hostdata;
struct lpfc_hba *phba = vport->phba;
struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
uint32_t total = 0;
uint32_t num_to_alloc = 0;
int num_allocated = 0;
uint32_t sdev_cnt;
if (!rport || fc_remote_port_chkready(rport))
return -ENXIO;
sdev->hostdata = rport->dd_data;
sdev_cnt = atomic_inc_return(&phba->sdev_cnt);
/*
* Populate the cmds_per_lun count scsi_bufs into this host's globally
* available list of scsi buffers. Don't allocate more than the
* HBA limit conveyed to the midlayer via the host structure. The
* formula accounts for the lun_queue_depth + error handlers + 1
* extra. This list of scsi bufs exists for the lifetime of the driver.
*/
total = phba->total_scsi_bufs;
num_to_alloc = vport->cfg_lun_queue_depth + 2;
/* If allocated buffers are enough do nothing */
if ((sdev_cnt * (vport->cfg_lun_queue_depth + 2)) < total)
return 0;
/* Allow some exchanges to be available always to complete discovery */
if (total >= phba->cfg_hba_queue_depth - LPFC_DISC_IOCB_BUFF_COUNT ) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"0704 At limitation of %d preallocated "
"command buffers\n", total);
return 0;
/* Allow some exchanges to be available always to complete discovery */
} else if (total + num_to_alloc >
phba->cfg_hba_queue_depth - LPFC_DISC_IOCB_BUFF_COUNT ) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"0705 Allocation request of %d "
"command buffers will exceed max of %d. "
"Reducing allocation request to %d.\n",
num_to_alloc, phba->cfg_hba_queue_depth,
(phba->cfg_hba_queue_depth - total));
num_to_alloc = phba->cfg_hba_queue_depth - total;
}
num_allocated = lpfc_new_scsi_buf(vport, num_to_alloc);
if (num_to_alloc != num_allocated) {
lpfc_printf_vlog(vport, KERN_WARNING, LOG_FCP,
"0708 Allocation request of %d "
"command buffers did not succeed. "
"Allocated %d buffers.\n",
num_to_alloc, num_allocated);
}
if (num_allocated > 0)
phba->total_scsi_bufs += num_allocated;
return 0;
}
/**
* lpfc_slave_configure - scsi_host_template slave_configure entry point
* @sdev: Pointer to scsi_device.
*
* This routine configures following items
* - Tag command queuing support for @sdev if supported.
* - Enable SLI polling for fcp ring if ENABLE_FCP_RING_POLLING flag is set.
*
* Return codes:
* 0 - Success
**/
static int
lpfc_slave_configure(struct scsi_device *sdev)
{
struct lpfc_vport *vport = (struct lpfc_vport *) sdev->host->hostdata;
struct lpfc_hba *phba = vport->phba;
if (sdev->tagged_supported)
scsi_activate_tcq(sdev, vport->cfg_lun_queue_depth);
else
scsi_deactivate_tcq(sdev, vport->cfg_lun_queue_depth);
if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
lpfc_sli_handle_fast_ring_event(phba,
&phba->sli.ring[LPFC_FCP_RING], HA_R0RE_REQ);
if (phba->cfg_poll & DISABLE_FCP_RING_INT)
lpfc_poll_rearm_timer(phba);
}
return 0;
}
/**
* lpfc_slave_destroy - slave_destroy entry point of SHT data structure
* @sdev: Pointer to scsi_device.
*
* This routine sets @sdev hostatdata filed to null.
**/
static void
lpfc_slave_destroy(struct scsi_device *sdev)
{
struct lpfc_vport *vport = (struct lpfc_vport *) sdev->host->hostdata;
struct lpfc_hba *phba = vport->phba;
atomic_dec(&phba->sdev_cnt);
sdev->hostdata = NULL;
return;
}
struct scsi_host_template lpfc_template = {
.module = THIS_MODULE,
.name = LPFC_DRIVER_NAME,
.info = lpfc_info,
.queuecommand = lpfc_queuecommand,
.eh_abort_handler = lpfc_abort_handler,
.eh_device_reset_handler = lpfc_device_reset_handler,
.eh_target_reset_handler = lpfc_target_reset_handler,
.eh_bus_reset_handler = lpfc_bus_reset_handler,
.slave_alloc = lpfc_slave_alloc,
.slave_configure = lpfc_slave_configure,
.slave_destroy = lpfc_slave_destroy,
.scan_finished = lpfc_scan_finished,
.this_id = -1,
.sg_tablesize = LPFC_DEFAULT_SG_SEG_CNT,
.cmd_per_lun = LPFC_CMD_PER_LUN,
.use_clustering = ENABLE_CLUSTERING,
.shost_attrs = lpfc_hba_attrs,
.max_sectors = 0xFFFF,
.vendor_id = LPFC_NL_VENDOR_ID,
.change_queue_depth = lpfc_change_queue_depth,
};
struct scsi_host_template lpfc_vport_template = {
.module = THIS_MODULE,
.name = LPFC_DRIVER_NAME,
.info = lpfc_info,
.queuecommand = lpfc_queuecommand,
.eh_abort_handler = lpfc_abort_handler,
.eh_device_reset_handler = lpfc_device_reset_handler,
.eh_target_reset_handler = lpfc_target_reset_handler,
.eh_bus_reset_handler = lpfc_bus_reset_handler,
.slave_alloc = lpfc_slave_alloc,
.slave_configure = lpfc_slave_configure,
.slave_destroy = lpfc_slave_destroy,
.scan_finished = lpfc_scan_finished,
.this_id = -1,
.sg_tablesize = LPFC_DEFAULT_SG_SEG_CNT,
.cmd_per_lun = LPFC_CMD_PER_LUN,
.use_clustering = ENABLE_CLUSTERING,
.shost_attrs = lpfc_vport_attrs,
.max_sectors = 0xFFFF,
.change_queue_depth = lpfc_change_queue_depth,
};
| gpl-2.0 |
aicjofs/android_kernel_lge_v500_20d_f2fs | drivers/hv/ring_buffer.c | 4270 | 11214 | /*
*
* Copyright (c) 2009, Microsoft Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
* K. Y. Srinivasan <kys@microsoft.com>
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/hyperv.h>
#include "hyperv_vmbus.h"
/* #defines */
/* Amount of space to write to */
#define BYTES_AVAIL_TO_WRITE(r, w, z) \
((w) >= (r)) ? ((z) - ((w) - (r))) : ((r) - (w))
/*
*
* hv_get_ringbuffer_availbytes()
*
* Get number of bytes available to read and to write to
* for the specified ring buffer
*/
static inline void
hv_get_ringbuffer_availbytes(struct hv_ring_buffer_info *rbi,
u32 *read, u32 *write)
{
u32 read_loc, write_loc;
smp_read_barrier_depends();
/* Capture the read/write indices before they changed */
read_loc = rbi->ring_buffer->read_index;
write_loc = rbi->ring_buffer->write_index;
*write = BYTES_AVAIL_TO_WRITE(read_loc, write_loc, rbi->ring_datasize);
*read = rbi->ring_datasize - *write;
}
/*
* hv_get_next_write_location()
*
* Get the next write location for the specified ring buffer
*
*/
static inline u32
hv_get_next_write_location(struct hv_ring_buffer_info *ring_info)
{
u32 next = ring_info->ring_buffer->write_index;
return next;
}
/*
* hv_set_next_write_location()
*
* Set the next write location for the specified ring buffer
*
*/
static inline void
hv_set_next_write_location(struct hv_ring_buffer_info *ring_info,
u32 next_write_location)
{
ring_info->ring_buffer->write_index = next_write_location;
}
/*
* hv_get_next_read_location()
*
* Get the next read location for the specified ring buffer
*/
static inline u32
hv_get_next_read_location(struct hv_ring_buffer_info *ring_info)
{
u32 next = ring_info->ring_buffer->read_index;
return next;
}
/*
* hv_get_next_readlocation_withoffset()
*
* Get the next read location + offset for the specified ring buffer.
* This allows the caller to skip
*/
static inline u32
hv_get_next_readlocation_withoffset(struct hv_ring_buffer_info *ring_info,
u32 offset)
{
u32 next = ring_info->ring_buffer->read_index;
next += offset;
next %= ring_info->ring_datasize;
return next;
}
/*
*
* hv_set_next_read_location()
*
* Set the next read location for the specified ring buffer
*
*/
static inline void
hv_set_next_read_location(struct hv_ring_buffer_info *ring_info,
u32 next_read_location)
{
ring_info->ring_buffer->read_index = next_read_location;
}
/*
*
* hv_get_ring_buffer()
*
* Get the start of the ring buffer
*/
static inline void *
hv_get_ring_buffer(struct hv_ring_buffer_info *ring_info)
{
return (void *)ring_info->ring_buffer->buffer;
}
/*
*
* hv_get_ring_buffersize()
*
* Get the size of the ring buffer
*/
static inline u32
hv_get_ring_buffersize(struct hv_ring_buffer_info *ring_info)
{
return ring_info->ring_datasize;
}
/*
*
* hv_get_ring_bufferindices()
*
* Get the read and write indices as u64 of the specified ring buffer
*
*/
static inline u64
hv_get_ring_bufferindices(struct hv_ring_buffer_info *ring_info)
{
return (u64)ring_info->ring_buffer->write_index << 32;
}
/*
*
* hv_copyfrom_ringbuffer()
*
* Helper routine to copy to source from ring buffer.
* Assume there is enough room. Handles wrap-around in src case only!!
*
*/
static u32 hv_copyfrom_ringbuffer(
struct hv_ring_buffer_info *ring_info,
void *dest,
u32 destlen,
u32 start_read_offset)
{
void *ring_buffer = hv_get_ring_buffer(ring_info);
u32 ring_buffer_size = hv_get_ring_buffersize(ring_info);
u32 frag_len;
/* wrap-around detected at the src */
if (destlen > ring_buffer_size - start_read_offset) {
frag_len = ring_buffer_size - start_read_offset;
memcpy(dest, ring_buffer + start_read_offset, frag_len);
memcpy(dest + frag_len, ring_buffer, destlen - frag_len);
} else
memcpy(dest, ring_buffer + start_read_offset, destlen);
start_read_offset += destlen;
start_read_offset %= ring_buffer_size;
return start_read_offset;
}
/*
*
* hv_copyto_ringbuffer()
*
* Helper routine to copy from source to ring buffer.
* Assume there is enough room. Handles wrap-around in dest case only!!
*
*/
static u32 hv_copyto_ringbuffer(
struct hv_ring_buffer_info *ring_info,
u32 start_write_offset,
void *src,
u32 srclen)
{
void *ring_buffer = hv_get_ring_buffer(ring_info);
u32 ring_buffer_size = hv_get_ring_buffersize(ring_info);
u32 frag_len;
/* wrap-around detected! */
if (srclen > ring_buffer_size - start_write_offset) {
frag_len = ring_buffer_size - start_write_offset;
memcpy(ring_buffer + start_write_offset, src, frag_len);
memcpy(ring_buffer, src + frag_len, srclen - frag_len);
} else
memcpy(ring_buffer + start_write_offset, src, srclen);
start_write_offset += srclen;
start_write_offset %= ring_buffer_size;
return start_write_offset;
}
/*
*
* hv_ringbuffer_get_debuginfo()
*
* Get various debug metrics for the specified ring buffer
*
*/
void hv_ringbuffer_get_debuginfo(struct hv_ring_buffer_info *ring_info,
struct hv_ring_buffer_debug_info *debug_info)
{
u32 bytes_avail_towrite;
u32 bytes_avail_toread;
if (ring_info->ring_buffer) {
hv_get_ringbuffer_availbytes(ring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
debug_info->bytes_avail_toread = bytes_avail_toread;
debug_info->bytes_avail_towrite = bytes_avail_towrite;
debug_info->current_read_index =
ring_info->ring_buffer->read_index;
debug_info->current_write_index =
ring_info->ring_buffer->write_index;
debug_info->current_interrupt_mask =
ring_info->ring_buffer->interrupt_mask;
}
}
/*
*
* hv_get_ringbuffer_interrupt_mask()
*
* Get the interrupt mask for the specified ring buffer
*
*/
u32 hv_get_ringbuffer_interrupt_mask(struct hv_ring_buffer_info *rbi)
{
return rbi->ring_buffer->interrupt_mask;
}
/*
*
* hv_ringbuffer_init()
*
*Initialize the ring buffer
*
*/
int hv_ringbuffer_init(struct hv_ring_buffer_info *ring_info,
void *buffer, u32 buflen)
{
if (sizeof(struct hv_ring_buffer) != PAGE_SIZE)
return -EINVAL;
memset(ring_info, 0, sizeof(struct hv_ring_buffer_info));
ring_info->ring_buffer = (struct hv_ring_buffer *)buffer;
ring_info->ring_buffer->read_index =
ring_info->ring_buffer->write_index = 0;
ring_info->ring_size = buflen;
ring_info->ring_datasize = buflen - sizeof(struct hv_ring_buffer);
spin_lock_init(&ring_info->ring_lock);
return 0;
}
/*
*
* hv_ringbuffer_cleanup()
*
* Cleanup the ring buffer
*
*/
void hv_ringbuffer_cleanup(struct hv_ring_buffer_info *ring_info)
{
}
/*
*
* hv_ringbuffer_write()
*
* Write to the ring buffer
*
*/
int hv_ringbuffer_write(struct hv_ring_buffer_info *outring_info,
struct scatterlist *sglist, u32 sgcount)
{
int i = 0;
u32 bytes_avail_towrite;
u32 bytes_avail_toread;
u32 totalbytes_towrite = 0;
struct scatterlist *sg;
u32 next_write_location;
u64 prev_indices = 0;
unsigned long flags;
for_each_sg(sglist, sg, sgcount, i)
{
totalbytes_towrite += sg->length;
}
totalbytes_towrite += sizeof(u64);
spin_lock_irqsave(&outring_info->ring_lock, flags);
hv_get_ringbuffer_availbytes(outring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
/* If there is only room for the packet, assume it is full. */
/* Otherwise, the next time around, we think the ring buffer */
/* is empty since the read index == write index */
if (bytes_avail_towrite <= totalbytes_towrite) {
spin_unlock_irqrestore(&outring_info->ring_lock, flags);
return -EAGAIN;
}
/* Write to the ring buffer */
next_write_location = hv_get_next_write_location(outring_info);
for_each_sg(sglist, sg, sgcount, i)
{
next_write_location = hv_copyto_ringbuffer(outring_info,
next_write_location,
sg_virt(sg),
sg->length);
}
/* Set previous packet start */
prev_indices = hv_get_ring_bufferindices(outring_info);
next_write_location = hv_copyto_ringbuffer(outring_info,
next_write_location,
&prev_indices,
sizeof(u64));
/* Make sure we flush all writes before updating the writeIndex */
smp_wmb();
/* Now, update the write location */
hv_set_next_write_location(outring_info, next_write_location);
spin_unlock_irqrestore(&outring_info->ring_lock, flags);
return 0;
}
/*
*
* hv_ringbuffer_peek()
*
* Read without advancing the read index
*
*/
int hv_ringbuffer_peek(struct hv_ring_buffer_info *Inring_info,
void *Buffer, u32 buflen)
{
u32 bytes_avail_towrite;
u32 bytes_avail_toread;
u32 next_read_location = 0;
unsigned long flags;
spin_lock_irqsave(&Inring_info->ring_lock, flags);
hv_get_ringbuffer_availbytes(Inring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
/* Make sure there is something to read */
if (bytes_avail_toread < buflen) {
spin_unlock_irqrestore(&Inring_info->ring_lock, flags);
return -EAGAIN;
}
/* Convert to byte offset */
next_read_location = hv_get_next_read_location(Inring_info);
next_read_location = hv_copyfrom_ringbuffer(Inring_info,
Buffer,
buflen,
next_read_location);
spin_unlock_irqrestore(&Inring_info->ring_lock, flags);
return 0;
}
/*
*
* hv_ringbuffer_read()
*
* Read and advance the read index
*
*/
int hv_ringbuffer_read(struct hv_ring_buffer_info *inring_info, void *buffer,
u32 buflen, u32 offset)
{
u32 bytes_avail_towrite;
u32 bytes_avail_toread;
u32 next_read_location = 0;
u64 prev_indices = 0;
unsigned long flags;
if (buflen <= 0)
return -EINVAL;
spin_lock_irqsave(&inring_info->ring_lock, flags);
hv_get_ringbuffer_availbytes(inring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
/* Make sure there is something to read */
if (bytes_avail_toread < buflen) {
spin_unlock_irqrestore(&inring_info->ring_lock, flags);
return -EAGAIN;
}
next_read_location =
hv_get_next_readlocation_withoffset(inring_info, offset);
next_read_location = hv_copyfrom_ringbuffer(inring_info,
buffer,
buflen,
next_read_location);
next_read_location = hv_copyfrom_ringbuffer(inring_info,
&prev_indices,
sizeof(u64),
next_read_location);
/* Make sure all reads are done before we update the read index since */
/* the writer may start writing to the read area once the read index */
/*is updated */
smp_mb();
/* Update the read index */
hv_set_next_read_location(inring_info, next_read_location);
spin_unlock_irqrestore(&inring_info->ring_lock, flags);
return 0;
}
| gpl-2.0 |
omnirom/android_kernel_motorola_msm8226 | sound/core/misc.c | 4526 | 3877 | /*
* Misc and compatibility things
* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/export.h>
#include <linux/moduleparam.h>
#include <linux/time.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <sound/core.h>
#ifdef CONFIG_SND_DEBUG
#ifdef CONFIG_SND_DEBUG_VERBOSE
#define DEFAULT_DEBUG_LEVEL 2
#else
#define DEFAULT_DEBUG_LEVEL 1
#endif
static int debug = DEFAULT_DEBUG_LEVEL;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0 = disable)");
#endif /* CONFIG_SND_DEBUG */
void release_and_free_resource(struct resource *res)
{
if (res) {
release_resource(res);
kfree(res);
}
}
EXPORT_SYMBOL(release_and_free_resource);
#ifdef CONFIG_SND_VERBOSE_PRINTK
/* strip the leading path if the given path is absolute */
static const char *sanity_file_name(const char *path)
{
if (*path == '/')
return strrchr(path, '/') + 1;
else
return path;
}
#endif
#if defined(CONFIG_SND_DEBUG) || defined(CONFIG_SND_VERBOSE_PRINTK)
void __snd_printk(unsigned int level, const char *path, int line,
const char *format, ...)
{
va_list args;
#ifdef CONFIG_SND_VERBOSE_PRINTK
struct va_format vaf;
char verbose_fmt[] = KERN_DEFAULT "ALSA %s:%d %pV";
#endif
#ifdef CONFIG_SND_DEBUG
if (debug < level)
return;
#endif
va_start(args, format);
#ifdef CONFIG_SND_VERBOSE_PRINTK
vaf.fmt = format;
vaf.va = &args;
if (format[0] == '<' && format[2] == '>') {
memcpy(verbose_fmt, format, 3);
vaf.fmt = format + 3;
} else if (level)
memcpy(verbose_fmt, KERN_DEBUG, 3);
printk(verbose_fmt, sanity_file_name(path), line, &vaf);
#else
vprintk(format, args);
#endif
va_end(args);
}
EXPORT_SYMBOL_GPL(__snd_printk);
#endif
#ifdef CONFIG_PCI
#include <linux/pci.h>
/**
* snd_pci_quirk_lookup_id - look up a PCI SSID quirk list
* @vendor: PCI SSV id
* @device: PCI SSD id
* @list: quirk list, terminated by a null entry
*
* Look through the given quirk list and finds a matching entry
* with the same PCI SSID. When subdevice is 0, all subdevice
* values may match.
*
* Returns the matched entry pointer, or NULL if nothing matched.
*/
const struct snd_pci_quirk *
snd_pci_quirk_lookup_id(u16 vendor, u16 device,
const struct snd_pci_quirk *list)
{
const struct snd_pci_quirk *q;
for (q = list; q->subvendor; q++) {
if (q->subvendor != vendor)
continue;
if (!q->subdevice ||
(device & q->subdevice_mask) == q->subdevice)
return q;
}
return NULL;
}
EXPORT_SYMBOL(snd_pci_quirk_lookup_id);
/**
* snd_pci_quirk_lookup - look up a PCI SSID quirk list
* @pci: pci_dev handle
* @list: quirk list, terminated by a null entry
*
* Look through the given quirk list and finds a matching entry
* with the same PCI SSID. When subdevice is 0, all subdevice
* values may match.
*
* Returns the matched entry pointer, or NULL if nothing matched.
*/
const struct snd_pci_quirk *
snd_pci_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list)
{
return snd_pci_quirk_lookup_id(pci->subsystem_vendor,
pci->subsystem_device,
list);
}
EXPORT_SYMBOL(snd_pci_quirk_lookup);
#endif
| gpl-2.0 |
jsr-d9/android_kernel_msm | net/wanrouter/wanmain.c | 5038 | 19563 | /*****************************************************************************
* wanmain.c WAN Multiprotocol Router Module. Main code.
*
* This module is completely hardware-independent and provides
* the following common services for the WAN Link Drivers:
* o WAN device management (registering, unregistering)
* o Network interface management
* o Physical connection management (dial-up, incoming calls)
* o Logical connection management (switched virtual circuits)
* o Protocol encapsulation/decapsulation
*
* Author: Gideon Hack
*
* Copyright: (c) 1995-1999 Sangoma Technologies Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
* ============================================================================
* Nov 24, 2000 Nenad Corbic Updated for 2.4.X kernels
* Nov 07, 2000 Nenad Corbic Fixed the Mulit-Port PPP for kernels 2.2.16 and
* greater.
* Aug 2, 2000 Nenad Corbic Block the Multi-Port PPP from running on
* kernels 2.2.16 or greater. The SyncPPP
* has changed.
* Jul 13, 2000 Nenad Corbic Added SyncPPP support
* Added extra debugging in device_setup().
* Oct 01, 1999 Gideon Hack Update for s514 PCI card
* Dec 27, 1996 Gene Kozin Initial version (based on Sangoma's WANPIPE)
* Jan 16, 1997 Gene Kozin router_devlist made public
* Jan 31, 1997 Alan Cox Hacked it about a bit for 2.1
* Jun 27, 1997 Alan Cox realigned with vendor code
* Oct 15, 1997 Farhan Thawar changed wan_encapsulate to add a pad byte of 0
* Apr 20, 1998 Alan Cox Fixed 2.1 symbols
* May 17, 1998 K. Baranowski Fixed SNAP encapsulation in wan_encapsulate
* Dec 15, 1998 Arnaldo Melo support for firmwares of up to 128000 bytes
* check wandev->setup return value
* Dec 22, 1998 Arnaldo Melo vmalloc/vfree used in device_setup to allocate
* kernel memory and copy configuration data to
* kernel space (for big firmwares)
* Jun 02, 1999 Gideon Hack Updates for Linux 2.0.X and 2.2.X kernels.
*****************************************************************************/
#include <linux/stddef.h> /* offsetof(), etc. */
#include <linux/capability.h>
#include <linux/errno.h> /* return codes */
#include <linux/kernel.h>
#include <linux/module.h> /* support for loadable modules */
#include <linux/slab.h> /* kmalloc(), kfree() */
#include <linux/mutex.h>
#include <linux/mm.h>
#include <linux/string.h> /* inline mem*, str* functions */
#include <asm/byteorder.h> /* htons(), etc. */
#include <linux/wanrouter.h> /* WAN router API definitions */
#include <linux/vmalloc.h> /* vmalloc, vfree */
#include <asm/uaccess.h> /* copy_to/from_user */
#include <linux/init.h> /* __initfunc et al. */
#define DEV_TO_SLAVE(dev) (*((struct net_device **)netdev_priv(dev)))
/*
* Function Prototypes
*/
/*
* WAN device IOCTL handlers
*/
static DEFINE_MUTEX(wanrouter_mutex);
static int wanrouter_device_setup(struct wan_device *wandev,
wandev_conf_t __user *u_conf);
static int wanrouter_device_stat(struct wan_device *wandev,
wandev_stat_t __user *u_stat);
static int wanrouter_device_shutdown(struct wan_device *wandev);
static int wanrouter_device_new_if(struct wan_device *wandev,
wanif_conf_t __user *u_conf);
static int wanrouter_device_del_if(struct wan_device *wandev,
char __user *u_name);
/*
* Miscellaneous
*/
static struct wan_device *wanrouter_find_device(char *name);
static int wanrouter_delete_interface(struct wan_device *wandev, char *name);
static void lock_adapter_irq(spinlock_t *lock, unsigned long *smp_flags)
__acquires(lock);
static void unlock_adapter_irq(spinlock_t *lock, unsigned long *smp_flags)
__releases(lock);
/*
* Global Data
*/
static char wanrouter_fullname[] = "Sangoma WANPIPE Router";
static char wanrouter_copyright[] = "(c) 1995-2000 Sangoma Technologies Inc.";
static char wanrouter_modname[] = ROUTER_NAME; /* short module name */
struct wan_device* wanrouter_router_devlist; /* list of registered devices */
/*
* Organize Unique Identifiers for encapsulation/decapsulation
*/
#if 0
static unsigned char wanrouter_oui_ether[] = { 0x00, 0x00, 0x00 };
static unsigned char wanrouter_oui_802_2[] = { 0x00, 0x80, 0xC2 };
#endif
static int __init wanrouter_init(void)
{
int err;
printk(KERN_INFO "%s v%u.%u %s\n",
wanrouter_fullname, ROUTER_VERSION, ROUTER_RELEASE,
wanrouter_copyright);
err = wanrouter_proc_init();
if (err)
printk(KERN_INFO "%s: can't create entry in proc filesystem!\n",
wanrouter_modname);
return err;
}
static void __exit wanrouter_cleanup (void)
{
wanrouter_proc_cleanup();
}
/*
* This is just plain dumb. We should move the bugger to drivers/net/wan,
* slap it first in directory and make it module_init(). The only reason
* for subsys_initcall() here is that net goes after drivers (why, BTW?)
*/
subsys_initcall(wanrouter_init);
module_exit(wanrouter_cleanup);
/*
* Kernel APIs
*/
/*
* Register WAN device.
* o verify device credentials
* o create an entry for the device in the /proc/net/router directory
* o initialize internally maintained fields of the wan_device structure
* o link device data space to a singly-linked list
* o if it's the first device, then start kernel 'thread'
* o increment module use count
*
* Return:
* 0 Ok
* < 0 error.
*
* Context: process
*/
int register_wan_device(struct wan_device *wandev)
{
int err, namelen;
if ((wandev == NULL) || (wandev->magic != ROUTER_MAGIC) ||
(wandev->name == NULL))
return -EINVAL;
namelen = strlen(wandev->name);
if (!namelen || (namelen > WAN_DRVNAME_SZ))
return -EINVAL;
if (wanrouter_find_device(wandev->name))
return -EEXIST;
#ifdef WANDEBUG
printk(KERN_INFO "%s: registering WAN device %s\n",
wanrouter_modname, wandev->name);
#endif
/*
* Register /proc directory entry
*/
err = wanrouter_proc_add(wandev);
if (err) {
printk(KERN_INFO
"%s: can't create /proc/net/router/%s entry!\n",
wanrouter_modname, wandev->name);
return err;
}
/*
* Initialize fields of the wan_device structure maintained by the
* router and update local data.
*/
wandev->ndev = 0;
wandev->dev = NULL;
wandev->next = wanrouter_router_devlist;
wanrouter_router_devlist = wandev;
return 0;
}
/*
* Unregister WAN device.
* o shut down device
* o unlink device data space from the linked list
* o delete device entry in the /proc/net/router directory
* o decrement module use count
*
* Return: 0 Ok
* <0 error.
* Context: process
*/
int unregister_wan_device(char *name)
{
struct wan_device *wandev, *prev;
if (name == NULL)
return -EINVAL;
for (wandev = wanrouter_router_devlist, prev = NULL;
wandev && strcmp(wandev->name, name);
prev = wandev, wandev = wandev->next)
;
if (wandev == NULL)
return -ENODEV;
#ifdef WANDEBUG
printk(KERN_INFO "%s: unregistering WAN device %s\n",
wanrouter_modname, name);
#endif
if (wandev->state != WAN_UNCONFIGURED)
wanrouter_device_shutdown(wandev);
if (prev)
prev->next = wandev->next;
else
wanrouter_router_devlist = wandev->next;
wanrouter_proc_delete(wandev);
return 0;
}
#if 0
/*
* Encapsulate packet.
*
* Return: encapsulation header size
* < 0 - unsupported Ethertype
*
* Notes:
* 1. This function may be called on interrupt context.
*/
int wanrouter_encapsulate(struct sk_buff *skb, struct net_device *dev,
unsigned short type)
{
int hdr_len = 0;
switch (type) {
case ETH_P_IP: /* IP datagram encapsulation */
hdr_len += 1;
skb_push(skb, 1);
skb->data[0] = NLPID_IP;
break;
case ETH_P_IPX: /* SNAP encapsulation */
case ETH_P_ARP:
hdr_len += 7;
skb_push(skb, 7);
skb->data[0] = 0;
skb->data[1] = NLPID_SNAP;
skb_copy_to_linear_data_offset(skb, 2, wanrouter_oui_ether,
sizeof(wanrouter_oui_ether));
*((unsigned short*)&skb->data[5]) = htons(type);
break;
default: /* Unknown packet type */
printk(KERN_INFO
"%s: unsupported Ethertype 0x%04X on interface %s!\n",
wanrouter_modname, type, dev->name);
hdr_len = -EINVAL;
}
return hdr_len;
}
/*
* Decapsulate packet.
*
* Return: Ethertype (in network order)
* 0 unknown encapsulation
*
* Notes:
* 1. This function may be called on interrupt context.
*/
__be16 wanrouter_type_trans(struct sk_buff *skb, struct net_device *dev)
{
int cnt = skb->data[0] ? 0 : 1; /* there may be a pad present */
__be16 ethertype;
switch (skb->data[cnt]) {
case NLPID_IP: /* IP datagramm */
ethertype = htons(ETH_P_IP);
cnt += 1;
break;
case NLPID_SNAP: /* SNAP encapsulation */
if (memcmp(&skb->data[cnt + 1], wanrouter_oui_ether,
sizeof(wanrouter_oui_ether))){
printk(KERN_INFO
"%s: unsupported SNAP OUI %02X-%02X-%02X "
"on interface %s!\n", wanrouter_modname,
skb->data[cnt+1], skb->data[cnt+2],
skb->data[cnt+3], dev->name);
return 0;
}
ethertype = *((__be16*)&skb->data[cnt+4]);
cnt += 6;
break;
/* add other protocols, e.g. CLNP, ESIS, ISIS, if needed */
default:
printk(KERN_INFO
"%s: unsupported NLPID 0x%02X on interface %s!\n",
wanrouter_modname, skb->data[cnt], dev->name);
return 0;
}
skb->protocol = ethertype;
skb->pkt_type = PACKET_HOST; /* Physically point to point */
skb_pull(skb, cnt);
skb_reset_mac_header(skb);
return ethertype;
}
#endif /* 0 */
/*
* WAN device IOCTL.
* o find WAN device associated with this node
* o execute requested action or pass command to the device driver
*/
long wanrouter_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
struct inode *inode = file->f_path.dentry->d_inode;
int err = 0;
struct proc_dir_entry *dent;
struct wan_device *wandev;
void __user *data = (void __user *)arg;
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if ((cmd >> 8) != ROUTER_IOCTL)
return -EINVAL;
dent = PDE(inode);
if ((dent == NULL) || (dent->data == NULL))
return -EINVAL;
wandev = dent->data;
if (wandev->magic != ROUTER_MAGIC)
return -EINVAL;
mutex_lock(&wanrouter_mutex);
switch (cmd) {
case ROUTER_SETUP:
err = wanrouter_device_setup(wandev, data);
break;
case ROUTER_DOWN:
err = wanrouter_device_shutdown(wandev);
break;
case ROUTER_STAT:
err = wanrouter_device_stat(wandev, data);
break;
case ROUTER_IFNEW:
err = wanrouter_device_new_if(wandev, data);
break;
case ROUTER_IFDEL:
err = wanrouter_device_del_if(wandev, data);
break;
case ROUTER_IFSTAT:
break;
default:
if ((cmd >= ROUTER_USER) &&
(cmd <= ROUTER_USER_MAX) &&
wandev->ioctl)
err = wandev->ioctl(wandev, cmd, arg);
else err = -EINVAL;
}
mutex_unlock(&wanrouter_mutex);
return err;
}
/*
* WAN Driver IOCTL Handlers
*/
/*
* Setup WAN link device.
* o verify user address space
* o allocate kernel memory and copy configuration data to kernel space
* o if configuration data includes extension, copy it to kernel space too
* o call driver's setup() entry point
*/
static int wanrouter_device_setup(struct wan_device *wandev,
wandev_conf_t __user *u_conf)
{
void *data = NULL;
wandev_conf_t *conf;
int err = -EINVAL;
if (wandev->setup == NULL) { /* Nothing to do ? */
printk(KERN_INFO "%s: ERROR, No setup script: wandev->setup()\n",
wandev->name);
return 0;
}
conf = kmalloc(sizeof(wandev_conf_t), GFP_KERNEL);
if (conf == NULL){
printk(KERN_INFO "%s: ERROR, Failed to allocate kernel memory !\n",
wandev->name);
return -ENOBUFS;
}
if (copy_from_user(conf, u_conf, sizeof(wandev_conf_t))) {
printk(KERN_INFO "%s: Failed to copy user config data to kernel space!\n",
wandev->name);
kfree(conf);
return -EFAULT;
}
if (conf->magic != ROUTER_MAGIC) {
kfree(conf);
printk(KERN_INFO "%s: ERROR, Invalid MAGIC Number\n",
wandev->name);
return -EINVAL;
}
if (conf->data_size && conf->data) {
if (conf->data_size > 128000) {
printk(KERN_INFO
"%s: ERROR, Invalid firmware data size %i !\n",
wandev->name, conf->data_size);
kfree(conf);
return -EINVAL;
}
data = vmalloc(conf->data_size);
if (!data) {
printk(KERN_INFO
"%s: ERROR, Failed allocate kernel memory !\n",
wandev->name);
kfree(conf);
return -ENOBUFS;
}
if (!copy_from_user(data, conf->data, conf->data_size)) {
conf->data = data;
err = wandev->setup(wandev, conf);
} else {
printk(KERN_INFO
"%s: ERROR, Failed to copy from user data !\n",
wandev->name);
err = -EFAULT;
}
vfree(data);
} else {
printk(KERN_INFO
"%s: ERROR, No firmware found ! Firmware size = %i !\n",
wandev->name, conf->data_size);
}
kfree(conf);
return err;
}
/*
* Shutdown WAN device.
* o delete all not opened logical channels for this device
* o call driver's shutdown() entry point
*/
static int wanrouter_device_shutdown(struct wan_device *wandev)
{
struct net_device *dev;
int err=0;
if (wandev->state == WAN_UNCONFIGURED)
return 0;
printk(KERN_INFO "\n%s: Shutting Down!\n",wandev->name);
for (dev = wandev->dev; dev;) {
err = wanrouter_delete_interface(wandev, dev->name);
if (err)
return err;
/* The above function deallocates the current dev
* structure. Therefore, we cannot use netdev_priv(dev)
* as the next element: wandev->dev points to the
* next element */
dev = wandev->dev;
}
if (wandev->ndev)
return -EBUSY; /* there are opened interfaces */
if (wandev->shutdown)
err=wandev->shutdown(wandev);
return err;
}
/*
* Get WAN device status & statistics.
*/
static int wanrouter_device_stat(struct wan_device *wandev,
wandev_stat_t __user *u_stat)
{
wandev_stat_t stat;
memset(&stat, 0, sizeof(stat));
/* Ask device driver to update device statistics */
if ((wandev->state != WAN_UNCONFIGURED) && wandev->update)
wandev->update(wandev);
/* Fill out structure */
stat.ndev = wandev->ndev;
stat.state = wandev->state;
if (copy_to_user(u_stat, &stat, sizeof(stat)))
return -EFAULT;
return 0;
}
/*
* Create new WAN interface.
* o verify user address space
* o copy configuration data to kernel address space
* o allocate network interface data space
* o call driver's new_if() entry point
* o make sure there is no interface name conflict
* o register network interface
*/
static int wanrouter_device_new_if(struct wan_device *wandev,
wanif_conf_t __user *u_conf)
{
wanif_conf_t *cnf;
struct net_device *dev = NULL;
int err;
if ((wandev->state == WAN_UNCONFIGURED) || (wandev->new_if == NULL))
return -ENODEV;
cnf = kmalloc(sizeof(wanif_conf_t), GFP_KERNEL);
if (!cnf)
return -ENOBUFS;
err = -EFAULT;
if (copy_from_user(cnf, u_conf, sizeof(wanif_conf_t)))
goto out;
err = -EINVAL;
if (cnf->magic != ROUTER_MAGIC)
goto out;
if (cnf->config_id == WANCONFIG_MPPP) {
printk(KERN_INFO "%s: Wanpipe Mulit-Port PPP support has not been compiled in!\n",
wandev->name);
err = -EPROTONOSUPPORT;
goto out;
} else {
err = wandev->new_if(wandev, dev, cnf);
}
if (!err) {
/* Register network interface. This will invoke init()
* function supplied by the driver. If device registered
* successfully, add it to the interface list.
*/
if (dev->name == NULL) {
err = -EINVAL;
} else {
#ifdef WANDEBUG
printk(KERN_INFO "%s: registering interface %s...\n",
wanrouter_modname, dev->name);
#endif
err = register_netdev(dev);
if (!err) {
struct net_device *slave = NULL;
unsigned long smp_flags=0;
lock_adapter_irq(&wandev->lock, &smp_flags);
if (wandev->dev == NULL) {
wandev->dev = dev;
} else {
for (slave=wandev->dev;
DEV_TO_SLAVE(slave);
slave = DEV_TO_SLAVE(slave))
DEV_TO_SLAVE(slave) = dev;
}
++wandev->ndev;
unlock_adapter_irq(&wandev->lock, &smp_flags);
err = 0; /* done !!! */
goto out;
}
}
if (wandev->del_if)
wandev->del_if(wandev, dev);
free_netdev(dev);
}
out:
kfree(cnf);
return err;
}
/*
* Delete WAN logical channel.
* o verify user address space
* o copy configuration data to kernel address space
*/
static int wanrouter_device_del_if(struct wan_device *wandev, char __user *u_name)
{
char name[WAN_IFNAME_SZ + 1];
int err = 0;
if (wandev->state == WAN_UNCONFIGURED)
return -ENODEV;
memset(name, 0, sizeof(name));
if (copy_from_user(name, u_name, WAN_IFNAME_SZ))
return -EFAULT;
err = wanrouter_delete_interface(wandev, name);
if (err)
return err;
/* If last interface being deleted, shutdown card
* This helps with administration at leaf nodes
* (You can tell if the person at the other end of the phone
* has an interface configured) and avoids DoS vulnerabilities
* in binary driver files - this fixes a problem with the current
* Sangoma driver going into strange states when all the network
* interfaces are deleted and the link irrecoverably disconnected.
*/
if (!wandev->ndev && wandev->shutdown)
err = wandev->shutdown(wandev);
return err;
}
/*
* Miscellaneous Functions
*/
/*
* Find WAN device by name.
* Return pointer to the WAN device data space or NULL if device not found.
*/
static struct wan_device *wanrouter_find_device(char *name)
{
struct wan_device *wandev;
for (wandev = wanrouter_router_devlist;
wandev && strcmp(wandev->name, name);
wandev = wandev->next);
return wandev;
}
/*
* Delete WAN logical channel identified by its name.
* o find logical channel by its name
* o call driver's del_if() entry point
* o unregister network interface
* o unlink channel data space from linked list of channels
* o release channel data space
*
* Return: 0 success
* -ENODEV channel not found.
* -EBUSY interface is open
*
* Note: If (force != 0), then device will be destroyed even if interface
* associated with it is open. It's caller's responsibility to make
* sure that opened interfaces are not removed!
*/
static int wanrouter_delete_interface(struct wan_device *wandev, char *name)
{
struct net_device *dev = NULL, *prev = NULL;
unsigned long smp_flags=0;
lock_adapter_irq(&wandev->lock, &smp_flags);
dev = wandev->dev;
prev = NULL;
while (dev && strcmp(name, dev->name)) {
struct net_device **slave = netdev_priv(dev);
prev = dev;
dev = *slave;
}
unlock_adapter_irq(&wandev->lock, &smp_flags);
if (dev == NULL)
return -ENODEV; /* interface not found */
if (netif_running(dev))
return -EBUSY; /* interface in use */
if (wandev->del_if)
wandev->del_if(wandev, dev);
lock_adapter_irq(&wandev->lock, &smp_flags);
if (prev) {
struct net_device **prev_slave = netdev_priv(prev);
struct net_device **slave = netdev_priv(dev);
*prev_slave = *slave;
} else {
struct net_device **slave = netdev_priv(dev);
wandev->dev = *slave;
}
--wandev->ndev;
unlock_adapter_irq(&wandev->lock, &smp_flags);
printk(KERN_INFO "%s: unregistering '%s'\n", wandev->name, dev->name);
unregister_netdev(dev);
free_netdev(dev);
return 0;
}
static void lock_adapter_irq(spinlock_t *lock, unsigned long *smp_flags)
__acquires(lock)
{
spin_lock_irqsave(lock, *smp_flags);
}
static void unlock_adapter_irq(spinlock_t *lock, unsigned long *smp_flags)
__releases(lock)
{
spin_unlock_irqrestore(lock, *smp_flags);
}
EXPORT_SYMBOL(register_wan_device);
EXPORT_SYMBOL(unregister_wan_device);
MODULE_LICENSE("GPL");
/*
* End
*/
| gpl-2.0 |
VanirRezound/kernel-vigor-aosp-3.4 | drivers/acpi/acpi_ipmi.c | 7086 | 14747 | /*
* acpi_ipmi.c - ACPI IPMI opregion
*
* Copyright (C) 2010 Intel Corporation
* Copyright (C) 2010 Zhao Yakui <yakui.zhao@intel.com>
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <acpi/acpi_bus.h>
#include <acpi/acpi_drivers.h>
#include <linux/ipmi.h>
#include <linux/device.h>
#include <linux/pnp.h>
MODULE_AUTHOR("Zhao Yakui");
MODULE_DESCRIPTION("ACPI IPMI Opregion driver");
MODULE_LICENSE("GPL");
#define IPMI_FLAGS_HANDLER_INSTALL 0
#define ACPI_IPMI_OK 0
#define ACPI_IPMI_TIMEOUT 0x10
#define ACPI_IPMI_UNKNOWN 0x07
/* the IPMI timeout is 5s */
#define IPMI_TIMEOUT (5 * HZ)
struct acpi_ipmi_device {
/* the device list attached to driver_data.ipmi_devices */
struct list_head head;
/* the IPMI request message list */
struct list_head tx_msg_list;
struct mutex tx_msg_lock;
acpi_handle handle;
struct pnp_dev *pnp_dev;
ipmi_user_t user_interface;
int ipmi_ifnum; /* IPMI interface number */
long curr_msgid;
unsigned long flags;
struct ipmi_smi_info smi_data;
};
struct ipmi_driver_data {
struct list_head ipmi_devices;
struct ipmi_smi_watcher bmc_events;
struct ipmi_user_hndl ipmi_hndlrs;
struct mutex ipmi_lock;
};
struct acpi_ipmi_msg {
struct list_head head;
/*
* General speaking the addr type should be SI_ADDR_TYPE. And
* the addr channel should be BMC.
* In fact it can also be IPMB type. But we will have to
* parse it from the Netfn command buffer. It is so complex
* that it is skipped.
*/
struct ipmi_addr addr;
long tx_msgid;
/* it is used to track whether the IPMI message is finished */
struct completion tx_complete;
struct kernel_ipmi_msg tx_message;
int msg_done;
/* tx data . And copy it from ACPI object buffer */
u8 tx_data[64];
int tx_len;
u8 rx_data[64];
int rx_len;
struct acpi_ipmi_device *device;
};
/* IPMI request/response buffer per ACPI 4.0, sec 5.5.2.4.3.2 */
struct acpi_ipmi_buffer {
u8 status;
u8 length;
u8 data[64];
};
static void ipmi_register_bmc(int iface, struct device *dev);
static void ipmi_bmc_gone(int iface);
static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data);
static void acpi_add_ipmi_device(struct acpi_ipmi_device *ipmi_device);
static void acpi_remove_ipmi_device(struct acpi_ipmi_device *ipmi_device);
static struct ipmi_driver_data driver_data = {
.ipmi_devices = LIST_HEAD_INIT(driver_data.ipmi_devices),
.bmc_events = {
.owner = THIS_MODULE,
.new_smi = ipmi_register_bmc,
.smi_gone = ipmi_bmc_gone,
},
.ipmi_hndlrs = {
.ipmi_recv_hndl = ipmi_msg_handler,
},
};
static struct acpi_ipmi_msg *acpi_alloc_ipmi_msg(struct acpi_ipmi_device *ipmi)
{
struct acpi_ipmi_msg *ipmi_msg;
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
ipmi_msg = kzalloc(sizeof(struct acpi_ipmi_msg), GFP_KERNEL);
if (!ipmi_msg) {
dev_warn(&pnp_dev->dev, "Can't allocate memory for ipmi_msg\n");
return NULL;
}
init_completion(&ipmi_msg->tx_complete);
INIT_LIST_HEAD(&ipmi_msg->head);
ipmi_msg->device = ipmi;
return ipmi_msg;
}
#define IPMI_OP_RGN_NETFN(offset) ((offset >> 8) & 0xff)
#define IPMI_OP_RGN_CMD(offset) (offset & 0xff)
static void acpi_format_ipmi_msg(struct acpi_ipmi_msg *tx_msg,
acpi_physical_address address,
acpi_integer *value)
{
struct kernel_ipmi_msg *msg;
struct acpi_ipmi_buffer *buffer;
struct acpi_ipmi_device *device;
msg = &tx_msg->tx_message;
/*
* IPMI network function and command are encoded in the address
* within the IPMI OpRegion; see ACPI 4.0, sec 5.5.2.4.3.
*/
msg->netfn = IPMI_OP_RGN_NETFN(address);
msg->cmd = IPMI_OP_RGN_CMD(address);
msg->data = tx_msg->tx_data;
/*
* value is the parameter passed by the IPMI opregion space handler.
* It points to the IPMI request message buffer
*/
buffer = (struct acpi_ipmi_buffer *)value;
/* copy the tx message data */
msg->data_len = buffer->length;
memcpy(tx_msg->tx_data, buffer->data, msg->data_len);
/*
* now the default type is SYSTEM_INTERFACE and channel type is BMC.
* If the netfn is APP_REQUEST and the cmd is SEND_MESSAGE,
* the addr type should be changed to IPMB. Then we will have to parse
* the IPMI request message buffer to get the IPMB address.
* If so, please fix me.
*/
tx_msg->addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
tx_msg->addr.channel = IPMI_BMC_CHANNEL;
tx_msg->addr.data[0] = 0;
/* Get the msgid */
device = tx_msg->device;
mutex_lock(&device->tx_msg_lock);
device->curr_msgid++;
tx_msg->tx_msgid = device->curr_msgid;
mutex_unlock(&device->tx_msg_lock);
}
static void acpi_format_ipmi_response(struct acpi_ipmi_msg *msg,
acpi_integer *value, int rem_time)
{
struct acpi_ipmi_buffer *buffer;
/*
* value is also used as output parameter. It represents the response
* IPMI message returned by IPMI command.
*/
buffer = (struct acpi_ipmi_buffer *)value;
if (!rem_time && !msg->msg_done) {
buffer->status = ACPI_IPMI_TIMEOUT;
return;
}
/*
* If the flag of msg_done is not set or the recv length is zero, it
* means that the IPMI command is not executed correctly.
* The status code will be ACPI_IPMI_UNKNOWN.
*/
if (!msg->msg_done || !msg->rx_len) {
buffer->status = ACPI_IPMI_UNKNOWN;
return;
}
/*
* If the IPMI response message is obtained correctly, the status code
* will be ACPI_IPMI_OK
*/
buffer->status = ACPI_IPMI_OK;
buffer->length = msg->rx_len;
memcpy(buffer->data, msg->rx_data, msg->rx_len);
}
static void ipmi_flush_tx_msg(struct acpi_ipmi_device *ipmi)
{
struct acpi_ipmi_msg *tx_msg, *temp;
int count = HZ / 10;
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
list_for_each_entry_safe(tx_msg, temp, &ipmi->tx_msg_list, head) {
/* wake up the sleep thread on the Tx msg */
complete(&tx_msg->tx_complete);
}
/* wait for about 100ms to flush the tx message list */
while (count--) {
if (list_empty(&ipmi->tx_msg_list))
break;
schedule_timeout(1);
}
if (!list_empty(&ipmi->tx_msg_list))
dev_warn(&pnp_dev->dev, "tx msg list is not NULL\n");
}
static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data)
{
struct acpi_ipmi_device *ipmi_device = user_msg_data;
int msg_found = 0;
struct acpi_ipmi_msg *tx_msg;
struct pnp_dev *pnp_dev = ipmi_device->pnp_dev;
if (msg->user != ipmi_device->user_interface) {
dev_warn(&pnp_dev->dev, "Unexpected response is returned. "
"returned user %p, expected user %p\n",
msg->user, ipmi_device->user_interface);
ipmi_free_recv_msg(msg);
return;
}
mutex_lock(&ipmi_device->tx_msg_lock);
list_for_each_entry(tx_msg, &ipmi_device->tx_msg_list, head) {
if (msg->msgid == tx_msg->tx_msgid) {
msg_found = 1;
break;
}
}
mutex_unlock(&ipmi_device->tx_msg_lock);
if (!msg_found) {
dev_warn(&pnp_dev->dev, "Unexpected response (msg id %ld) is "
"returned.\n", msg->msgid);
ipmi_free_recv_msg(msg);
return;
}
if (msg->msg.data_len) {
/* copy the response data to Rx_data buffer */
memcpy(tx_msg->rx_data, msg->msg_data, msg->msg.data_len);
tx_msg->rx_len = msg->msg.data_len;
tx_msg->msg_done = 1;
}
complete(&tx_msg->tx_complete);
ipmi_free_recv_msg(msg);
};
static void ipmi_register_bmc(int iface, struct device *dev)
{
struct acpi_ipmi_device *ipmi_device, *temp;
struct pnp_dev *pnp_dev;
ipmi_user_t user;
int err;
struct ipmi_smi_info smi_data;
acpi_handle handle;
err = ipmi_get_smi_info(iface, &smi_data);
if (err)
return;
if (smi_data.addr_src != SI_ACPI) {
put_device(smi_data.dev);
return;
}
handle = smi_data.addr_info.acpi_info.acpi_handle;
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry(temp, &driver_data.ipmi_devices, head) {
/*
* if the corresponding ACPI handle is already added
* to the device list, don't add it again.
*/
if (temp->handle == handle)
goto out;
}
ipmi_device = kzalloc(sizeof(*ipmi_device), GFP_KERNEL);
if (!ipmi_device)
goto out;
pnp_dev = to_pnp_dev(smi_data.dev);
ipmi_device->handle = handle;
ipmi_device->pnp_dev = pnp_dev;
err = ipmi_create_user(iface, &driver_data.ipmi_hndlrs,
ipmi_device, &user);
if (err) {
dev_warn(&pnp_dev->dev, "Can't create IPMI user interface\n");
kfree(ipmi_device);
goto out;
}
acpi_add_ipmi_device(ipmi_device);
ipmi_device->user_interface = user;
ipmi_device->ipmi_ifnum = iface;
mutex_unlock(&driver_data.ipmi_lock);
memcpy(&ipmi_device->smi_data, &smi_data, sizeof(struct ipmi_smi_info));
return;
out:
mutex_unlock(&driver_data.ipmi_lock);
put_device(smi_data.dev);
return;
}
static void ipmi_bmc_gone(int iface)
{
struct acpi_ipmi_device *ipmi_device, *temp;
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry_safe(ipmi_device, temp,
&driver_data.ipmi_devices, head) {
if (ipmi_device->ipmi_ifnum != iface)
continue;
acpi_remove_ipmi_device(ipmi_device);
put_device(ipmi_device->smi_data.dev);
kfree(ipmi_device);
break;
}
mutex_unlock(&driver_data.ipmi_lock);
}
/* --------------------------------------------------------------------------
* Address Space Management
* -------------------------------------------------------------------------- */
/*
* This is the IPMI opregion space handler.
* @function: indicates the read/write. In fact as the IPMI message is driven
* by command, only write is meaningful.
* @address: This contains the netfn/command of IPMI request message.
* @bits : not used.
* @value : it is an in/out parameter. It points to the IPMI message buffer.
* Before the IPMI message is sent, it represents the actual request
* IPMI message. After the IPMI message is finished, it represents
* the response IPMI message returned by IPMI command.
* @handler_context: IPMI device context.
*/
static acpi_status
acpi_ipmi_space_handler(u32 function, acpi_physical_address address,
u32 bits, acpi_integer *value,
void *handler_context, void *region_context)
{
struct acpi_ipmi_msg *tx_msg;
struct acpi_ipmi_device *ipmi_device = handler_context;
int err, rem_time;
acpi_status status;
/*
* IPMI opregion message.
* IPMI message is firstly written to the BMC and system software
* can get the respsonse. So it is unmeaningful for the read access
* of IPMI opregion.
*/
if ((function & ACPI_IO_MASK) == ACPI_READ)
return AE_TYPE;
if (!ipmi_device->user_interface)
return AE_NOT_EXIST;
tx_msg = acpi_alloc_ipmi_msg(ipmi_device);
if (!tx_msg)
return AE_NO_MEMORY;
acpi_format_ipmi_msg(tx_msg, address, value);
mutex_lock(&ipmi_device->tx_msg_lock);
list_add_tail(&tx_msg->head, &ipmi_device->tx_msg_list);
mutex_unlock(&ipmi_device->tx_msg_lock);
err = ipmi_request_settime(ipmi_device->user_interface,
&tx_msg->addr,
tx_msg->tx_msgid,
&tx_msg->tx_message,
NULL, 0, 0, 0);
if (err) {
status = AE_ERROR;
goto end_label;
}
rem_time = wait_for_completion_timeout(&tx_msg->tx_complete,
IPMI_TIMEOUT);
acpi_format_ipmi_response(tx_msg, value, rem_time);
status = AE_OK;
end_label:
mutex_lock(&ipmi_device->tx_msg_lock);
list_del(&tx_msg->head);
mutex_unlock(&ipmi_device->tx_msg_lock);
kfree(tx_msg);
return status;
}
static void ipmi_remove_space_handler(struct acpi_ipmi_device *ipmi)
{
if (!test_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags))
return;
acpi_remove_address_space_handler(ipmi->handle,
ACPI_ADR_SPACE_IPMI, &acpi_ipmi_space_handler);
clear_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags);
}
static int ipmi_install_space_handler(struct acpi_ipmi_device *ipmi)
{
acpi_status status;
if (test_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags))
return 0;
status = acpi_install_address_space_handler(ipmi->handle,
ACPI_ADR_SPACE_IPMI,
&acpi_ipmi_space_handler,
NULL, ipmi);
if (ACPI_FAILURE(status)) {
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
dev_warn(&pnp_dev->dev, "Can't register IPMI opregion space "
"handle\n");
return -EINVAL;
}
set_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags);
return 0;
}
static void acpi_add_ipmi_device(struct acpi_ipmi_device *ipmi_device)
{
INIT_LIST_HEAD(&ipmi_device->head);
mutex_init(&ipmi_device->tx_msg_lock);
INIT_LIST_HEAD(&ipmi_device->tx_msg_list);
ipmi_install_space_handler(ipmi_device);
list_add_tail(&ipmi_device->head, &driver_data.ipmi_devices);
}
static void acpi_remove_ipmi_device(struct acpi_ipmi_device *ipmi_device)
{
/*
* If the IPMI user interface is created, it should be
* destroyed.
*/
if (ipmi_device->user_interface) {
ipmi_destroy_user(ipmi_device->user_interface);
ipmi_device->user_interface = NULL;
}
/* flush the Tx_msg list */
if (!list_empty(&ipmi_device->tx_msg_list))
ipmi_flush_tx_msg(ipmi_device);
list_del(&ipmi_device->head);
ipmi_remove_space_handler(ipmi_device);
}
static int __init acpi_ipmi_init(void)
{
int result = 0;
if (acpi_disabled)
return result;
mutex_init(&driver_data.ipmi_lock);
result = ipmi_smi_watcher_register(&driver_data.bmc_events);
return result;
}
static void __exit acpi_ipmi_exit(void)
{
struct acpi_ipmi_device *ipmi_device, *temp;
if (acpi_disabled)
return;
ipmi_smi_watcher_unregister(&driver_data.bmc_events);
/*
* When one smi_watcher is unregistered, it is only deleted
* from the smi_watcher list. But the smi_gone callback function
* is not called. So explicitly uninstall the ACPI IPMI oregion
* handler and free it.
*/
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry_safe(ipmi_device, temp,
&driver_data.ipmi_devices, head) {
acpi_remove_ipmi_device(ipmi_device);
put_device(ipmi_device->smi_data.dev);
kfree(ipmi_device);
}
mutex_unlock(&driver_data.ipmi_lock);
}
module_init(acpi_ipmi_init);
module_exit(acpi_ipmi_exit);
| gpl-2.0 |
NooNameR/Dirty | drivers/acpi/acpi_ipmi.c | 7086 | 14747 | /*
* acpi_ipmi.c - ACPI IPMI opregion
*
* Copyright (C) 2010 Intel Corporation
* Copyright (C) 2010 Zhao Yakui <yakui.zhao@intel.com>
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <acpi/acpi_bus.h>
#include <acpi/acpi_drivers.h>
#include <linux/ipmi.h>
#include <linux/device.h>
#include <linux/pnp.h>
MODULE_AUTHOR("Zhao Yakui");
MODULE_DESCRIPTION("ACPI IPMI Opregion driver");
MODULE_LICENSE("GPL");
#define IPMI_FLAGS_HANDLER_INSTALL 0
#define ACPI_IPMI_OK 0
#define ACPI_IPMI_TIMEOUT 0x10
#define ACPI_IPMI_UNKNOWN 0x07
/* the IPMI timeout is 5s */
#define IPMI_TIMEOUT (5 * HZ)
struct acpi_ipmi_device {
/* the device list attached to driver_data.ipmi_devices */
struct list_head head;
/* the IPMI request message list */
struct list_head tx_msg_list;
struct mutex tx_msg_lock;
acpi_handle handle;
struct pnp_dev *pnp_dev;
ipmi_user_t user_interface;
int ipmi_ifnum; /* IPMI interface number */
long curr_msgid;
unsigned long flags;
struct ipmi_smi_info smi_data;
};
struct ipmi_driver_data {
struct list_head ipmi_devices;
struct ipmi_smi_watcher bmc_events;
struct ipmi_user_hndl ipmi_hndlrs;
struct mutex ipmi_lock;
};
struct acpi_ipmi_msg {
struct list_head head;
/*
* General speaking the addr type should be SI_ADDR_TYPE. And
* the addr channel should be BMC.
* In fact it can also be IPMB type. But we will have to
* parse it from the Netfn command buffer. It is so complex
* that it is skipped.
*/
struct ipmi_addr addr;
long tx_msgid;
/* it is used to track whether the IPMI message is finished */
struct completion tx_complete;
struct kernel_ipmi_msg tx_message;
int msg_done;
/* tx data . And copy it from ACPI object buffer */
u8 tx_data[64];
int tx_len;
u8 rx_data[64];
int rx_len;
struct acpi_ipmi_device *device;
};
/* IPMI request/response buffer per ACPI 4.0, sec 5.5.2.4.3.2 */
struct acpi_ipmi_buffer {
u8 status;
u8 length;
u8 data[64];
};
static void ipmi_register_bmc(int iface, struct device *dev);
static void ipmi_bmc_gone(int iface);
static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data);
static void acpi_add_ipmi_device(struct acpi_ipmi_device *ipmi_device);
static void acpi_remove_ipmi_device(struct acpi_ipmi_device *ipmi_device);
static struct ipmi_driver_data driver_data = {
.ipmi_devices = LIST_HEAD_INIT(driver_data.ipmi_devices),
.bmc_events = {
.owner = THIS_MODULE,
.new_smi = ipmi_register_bmc,
.smi_gone = ipmi_bmc_gone,
},
.ipmi_hndlrs = {
.ipmi_recv_hndl = ipmi_msg_handler,
},
};
static struct acpi_ipmi_msg *acpi_alloc_ipmi_msg(struct acpi_ipmi_device *ipmi)
{
struct acpi_ipmi_msg *ipmi_msg;
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
ipmi_msg = kzalloc(sizeof(struct acpi_ipmi_msg), GFP_KERNEL);
if (!ipmi_msg) {
dev_warn(&pnp_dev->dev, "Can't allocate memory for ipmi_msg\n");
return NULL;
}
init_completion(&ipmi_msg->tx_complete);
INIT_LIST_HEAD(&ipmi_msg->head);
ipmi_msg->device = ipmi;
return ipmi_msg;
}
#define IPMI_OP_RGN_NETFN(offset) ((offset >> 8) & 0xff)
#define IPMI_OP_RGN_CMD(offset) (offset & 0xff)
static void acpi_format_ipmi_msg(struct acpi_ipmi_msg *tx_msg,
acpi_physical_address address,
acpi_integer *value)
{
struct kernel_ipmi_msg *msg;
struct acpi_ipmi_buffer *buffer;
struct acpi_ipmi_device *device;
msg = &tx_msg->tx_message;
/*
* IPMI network function and command are encoded in the address
* within the IPMI OpRegion; see ACPI 4.0, sec 5.5.2.4.3.
*/
msg->netfn = IPMI_OP_RGN_NETFN(address);
msg->cmd = IPMI_OP_RGN_CMD(address);
msg->data = tx_msg->tx_data;
/*
* value is the parameter passed by the IPMI opregion space handler.
* It points to the IPMI request message buffer
*/
buffer = (struct acpi_ipmi_buffer *)value;
/* copy the tx message data */
msg->data_len = buffer->length;
memcpy(tx_msg->tx_data, buffer->data, msg->data_len);
/*
* now the default type is SYSTEM_INTERFACE and channel type is BMC.
* If the netfn is APP_REQUEST and the cmd is SEND_MESSAGE,
* the addr type should be changed to IPMB. Then we will have to parse
* the IPMI request message buffer to get the IPMB address.
* If so, please fix me.
*/
tx_msg->addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
tx_msg->addr.channel = IPMI_BMC_CHANNEL;
tx_msg->addr.data[0] = 0;
/* Get the msgid */
device = tx_msg->device;
mutex_lock(&device->tx_msg_lock);
device->curr_msgid++;
tx_msg->tx_msgid = device->curr_msgid;
mutex_unlock(&device->tx_msg_lock);
}
static void acpi_format_ipmi_response(struct acpi_ipmi_msg *msg,
acpi_integer *value, int rem_time)
{
struct acpi_ipmi_buffer *buffer;
/*
* value is also used as output parameter. It represents the response
* IPMI message returned by IPMI command.
*/
buffer = (struct acpi_ipmi_buffer *)value;
if (!rem_time && !msg->msg_done) {
buffer->status = ACPI_IPMI_TIMEOUT;
return;
}
/*
* If the flag of msg_done is not set or the recv length is zero, it
* means that the IPMI command is not executed correctly.
* The status code will be ACPI_IPMI_UNKNOWN.
*/
if (!msg->msg_done || !msg->rx_len) {
buffer->status = ACPI_IPMI_UNKNOWN;
return;
}
/*
* If the IPMI response message is obtained correctly, the status code
* will be ACPI_IPMI_OK
*/
buffer->status = ACPI_IPMI_OK;
buffer->length = msg->rx_len;
memcpy(buffer->data, msg->rx_data, msg->rx_len);
}
static void ipmi_flush_tx_msg(struct acpi_ipmi_device *ipmi)
{
struct acpi_ipmi_msg *tx_msg, *temp;
int count = HZ / 10;
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
list_for_each_entry_safe(tx_msg, temp, &ipmi->tx_msg_list, head) {
/* wake up the sleep thread on the Tx msg */
complete(&tx_msg->tx_complete);
}
/* wait for about 100ms to flush the tx message list */
while (count--) {
if (list_empty(&ipmi->tx_msg_list))
break;
schedule_timeout(1);
}
if (!list_empty(&ipmi->tx_msg_list))
dev_warn(&pnp_dev->dev, "tx msg list is not NULL\n");
}
static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data)
{
struct acpi_ipmi_device *ipmi_device = user_msg_data;
int msg_found = 0;
struct acpi_ipmi_msg *tx_msg;
struct pnp_dev *pnp_dev = ipmi_device->pnp_dev;
if (msg->user != ipmi_device->user_interface) {
dev_warn(&pnp_dev->dev, "Unexpected response is returned. "
"returned user %p, expected user %p\n",
msg->user, ipmi_device->user_interface);
ipmi_free_recv_msg(msg);
return;
}
mutex_lock(&ipmi_device->tx_msg_lock);
list_for_each_entry(tx_msg, &ipmi_device->tx_msg_list, head) {
if (msg->msgid == tx_msg->tx_msgid) {
msg_found = 1;
break;
}
}
mutex_unlock(&ipmi_device->tx_msg_lock);
if (!msg_found) {
dev_warn(&pnp_dev->dev, "Unexpected response (msg id %ld) is "
"returned.\n", msg->msgid);
ipmi_free_recv_msg(msg);
return;
}
if (msg->msg.data_len) {
/* copy the response data to Rx_data buffer */
memcpy(tx_msg->rx_data, msg->msg_data, msg->msg.data_len);
tx_msg->rx_len = msg->msg.data_len;
tx_msg->msg_done = 1;
}
complete(&tx_msg->tx_complete);
ipmi_free_recv_msg(msg);
};
static void ipmi_register_bmc(int iface, struct device *dev)
{
struct acpi_ipmi_device *ipmi_device, *temp;
struct pnp_dev *pnp_dev;
ipmi_user_t user;
int err;
struct ipmi_smi_info smi_data;
acpi_handle handle;
err = ipmi_get_smi_info(iface, &smi_data);
if (err)
return;
if (smi_data.addr_src != SI_ACPI) {
put_device(smi_data.dev);
return;
}
handle = smi_data.addr_info.acpi_info.acpi_handle;
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry(temp, &driver_data.ipmi_devices, head) {
/*
* if the corresponding ACPI handle is already added
* to the device list, don't add it again.
*/
if (temp->handle == handle)
goto out;
}
ipmi_device = kzalloc(sizeof(*ipmi_device), GFP_KERNEL);
if (!ipmi_device)
goto out;
pnp_dev = to_pnp_dev(smi_data.dev);
ipmi_device->handle = handle;
ipmi_device->pnp_dev = pnp_dev;
err = ipmi_create_user(iface, &driver_data.ipmi_hndlrs,
ipmi_device, &user);
if (err) {
dev_warn(&pnp_dev->dev, "Can't create IPMI user interface\n");
kfree(ipmi_device);
goto out;
}
acpi_add_ipmi_device(ipmi_device);
ipmi_device->user_interface = user;
ipmi_device->ipmi_ifnum = iface;
mutex_unlock(&driver_data.ipmi_lock);
memcpy(&ipmi_device->smi_data, &smi_data, sizeof(struct ipmi_smi_info));
return;
out:
mutex_unlock(&driver_data.ipmi_lock);
put_device(smi_data.dev);
return;
}
static void ipmi_bmc_gone(int iface)
{
struct acpi_ipmi_device *ipmi_device, *temp;
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry_safe(ipmi_device, temp,
&driver_data.ipmi_devices, head) {
if (ipmi_device->ipmi_ifnum != iface)
continue;
acpi_remove_ipmi_device(ipmi_device);
put_device(ipmi_device->smi_data.dev);
kfree(ipmi_device);
break;
}
mutex_unlock(&driver_data.ipmi_lock);
}
/* --------------------------------------------------------------------------
* Address Space Management
* -------------------------------------------------------------------------- */
/*
* This is the IPMI opregion space handler.
* @function: indicates the read/write. In fact as the IPMI message is driven
* by command, only write is meaningful.
* @address: This contains the netfn/command of IPMI request message.
* @bits : not used.
* @value : it is an in/out parameter. It points to the IPMI message buffer.
* Before the IPMI message is sent, it represents the actual request
* IPMI message. After the IPMI message is finished, it represents
* the response IPMI message returned by IPMI command.
* @handler_context: IPMI device context.
*/
static acpi_status
acpi_ipmi_space_handler(u32 function, acpi_physical_address address,
u32 bits, acpi_integer *value,
void *handler_context, void *region_context)
{
struct acpi_ipmi_msg *tx_msg;
struct acpi_ipmi_device *ipmi_device = handler_context;
int err, rem_time;
acpi_status status;
/*
* IPMI opregion message.
* IPMI message is firstly written to the BMC and system software
* can get the respsonse. So it is unmeaningful for the read access
* of IPMI opregion.
*/
if ((function & ACPI_IO_MASK) == ACPI_READ)
return AE_TYPE;
if (!ipmi_device->user_interface)
return AE_NOT_EXIST;
tx_msg = acpi_alloc_ipmi_msg(ipmi_device);
if (!tx_msg)
return AE_NO_MEMORY;
acpi_format_ipmi_msg(tx_msg, address, value);
mutex_lock(&ipmi_device->tx_msg_lock);
list_add_tail(&tx_msg->head, &ipmi_device->tx_msg_list);
mutex_unlock(&ipmi_device->tx_msg_lock);
err = ipmi_request_settime(ipmi_device->user_interface,
&tx_msg->addr,
tx_msg->tx_msgid,
&tx_msg->tx_message,
NULL, 0, 0, 0);
if (err) {
status = AE_ERROR;
goto end_label;
}
rem_time = wait_for_completion_timeout(&tx_msg->tx_complete,
IPMI_TIMEOUT);
acpi_format_ipmi_response(tx_msg, value, rem_time);
status = AE_OK;
end_label:
mutex_lock(&ipmi_device->tx_msg_lock);
list_del(&tx_msg->head);
mutex_unlock(&ipmi_device->tx_msg_lock);
kfree(tx_msg);
return status;
}
static void ipmi_remove_space_handler(struct acpi_ipmi_device *ipmi)
{
if (!test_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags))
return;
acpi_remove_address_space_handler(ipmi->handle,
ACPI_ADR_SPACE_IPMI, &acpi_ipmi_space_handler);
clear_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags);
}
static int ipmi_install_space_handler(struct acpi_ipmi_device *ipmi)
{
acpi_status status;
if (test_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags))
return 0;
status = acpi_install_address_space_handler(ipmi->handle,
ACPI_ADR_SPACE_IPMI,
&acpi_ipmi_space_handler,
NULL, ipmi);
if (ACPI_FAILURE(status)) {
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
dev_warn(&pnp_dev->dev, "Can't register IPMI opregion space "
"handle\n");
return -EINVAL;
}
set_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags);
return 0;
}
static void acpi_add_ipmi_device(struct acpi_ipmi_device *ipmi_device)
{
INIT_LIST_HEAD(&ipmi_device->head);
mutex_init(&ipmi_device->tx_msg_lock);
INIT_LIST_HEAD(&ipmi_device->tx_msg_list);
ipmi_install_space_handler(ipmi_device);
list_add_tail(&ipmi_device->head, &driver_data.ipmi_devices);
}
static void acpi_remove_ipmi_device(struct acpi_ipmi_device *ipmi_device)
{
/*
* If the IPMI user interface is created, it should be
* destroyed.
*/
if (ipmi_device->user_interface) {
ipmi_destroy_user(ipmi_device->user_interface);
ipmi_device->user_interface = NULL;
}
/* flush the Tx_msg list */
if (!list_empty(&ipmi_device->tx_msg_list))
ipmi_flush_tx_msg(ipmi_device);
list_del(&ipmi_device->head);
ipmi_remove_space_handler(ipmi_device);
}
static int __init acpi_ipmi_init(void)
{
int result = 0;
if (acpi_disabled)
return result;
mutex_init(&driver_data.ipmi_lock);
result = ipmi_smi_watcher_register(&driver_data.bmc_events);
return result;
}
static void __exit acpi_ipmi_exit(void)
{
struct acpi_ipmi_device *ipmi_device, *temp;
if (acpi_disabled)
return;
ipmi_smi_watcher_unregister(&driver_data.bmc_events);
/*
* When one smi_watcher is unregistered, it is only deleted
* from the smi_watcher list. But the smi_gone callback function
* is not called. So explicitly uninstall the ACPI IPMI oregion
* handler and free it.
*/
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry_safe(ipmi_device, temp,
&driver_data.ipmi_devices, head) {
acpi_remove_ipmi_device(ipmi_device);
put_device(ipmi_device->smi_data.dev);
kfree(ipmi_device);
}
mutex_unlock(&driver_data.ipmi_lock);
}
module_init(acpi_ipmi_init);
module_exit(acpi_ipmi_exit);
| gpl-2.0 |
Galaxy-Tab-S2/android_kernel_samsung_gts210wifi | drivers/acpi/acpi_ipmi.c | 7086 | 14747 | /*
* acpi_ipmi.c - ACPI IPMI opregion
*
* Copyright (C) 2010 Intel Corporation
* Copyright (C) 2010 Zhao Yakui <yakui.zhao@intel.com>
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <acpi/acpi_bus.h>
#include <acpi/acpi_drivers.h>
#include <linux/ipmi.h>
#include <linux/device.h>
#include <linux/pnp.h>
MODULE_AUTHOR("Zhao Yakui");
MODULE_DESCRIPTION("ACPI IPMI Opregion driver");
MODULE_LICENSE("GPL");
#define IPMI_FLAGS_HANDLER_INSTALL 0
#define ACPI_IPMI_OK 0
#define ACPI_IPMI_TIMEOUT 0x10
#define ACPI_IPMI_UNKNOWN 0x07
/* the IPMI timeout is 5s */
#define IPMI_TIMEOUT (5 * HZ)
struct acpi_ipmi_device {
/* the device list attached to driver_data.ipmi_devices */
struct list_head head;
/* the IPMI request message list */
struct list_head tx_msg_list;
struct mutex tx_msg_lock;
acpi_handle handle;
struct pnp_dev *pnp_dev;
ipmi_user_t user_interface;
int ipmi_ifnum; /* IPMI interface number */
long curr_msgid;
unsigned long flags;
struct ipmi_smi_info smi_data;
};
struct ipmi_driver_data {
struct list_head ipmi_devices;
struct ipmi_smi_watcher bmc_events;
struct ipmi_user_hndl ipmi_hndlrs;
struct mutex ipmi_lock;
};
struct acpi_ipmi_msg {
struct list_head head;
/*
* General speaking the addr type should be SI_ADDR_TYPE. And
* the addr channel should be BMC.
* In fact it can also be IPMB type. But we will have to
* parse it from the Netfn command buffer. It is so complex
* that it is skipped.
*/
struct ipmi_addr addr;
long tx_msgid;
/* it is used to track whether the IPMI message is finished */
struct completion tx_complete;
struct kernel_ipmi_msg tx_message;
int msg_done;
/* tx data . And copy it from ACPI object buffer */
u8 tx_data[64];
int tx_len;
u8 rx_data[64];
int rx_len;
struct acpi_ipmi_device *device;
};
/* IPMI request/response buffer per ACPI 4.0, sec 5.5.2.4.3.2 */
struct acpi_ipmi_buffer {
u8 status;
u8 length;
u8 data[64];
};
static void ipmi_register_bmc(int iface, struct device *dev);
static void ipmi_bmc_gone(int iface);
static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data);
static void acpi_add_ipmi_device(struct acpi_ipmi_device *ipmi_device);
static void acpi_remove_ipmi_device(struct acpi_ipmi_device *ipmi_device);
static struct ipmi_driver_data driver_data = {
.ipmi_devices = LIST_HEAD_INIT(driver_data.ipmi_devices),
.bmc_events = {
.owner = THIS_MODULE,
.new_smi = ipmi_register_bmc,
.smi_gone = ipmi_bmc_gone,
},
.ipmi_hndlrs = {
.ipmi_recv_hndl = ipmi_msg_handler,
},
};
static struct acpi_ipmi_msg *acpi_alloc_ipmi_msg(struct acpi_ipmi_device *ipmi)
{
struct acpi_ipmi_msg *ipmi_msg;
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
ipmi_msg = kzalloc(sizeof(struct acpi_ipmi_msg), GFP_KERNEL);
if (!ipmi_msg) {
dev_warn(&pnp_dev->dev, "Can't allocate memory for ipmi_msg\n");
return NULL;
}
init_completion(&ipmi_msg->tx_complete);
INIT_LIST_HEAD(&ipmi_msg->head);
ipmi_msg->device = ipmi;
return ipmi_msg;
}
#define IPMI_OP_RGN_NETFN(offset) ((offset >> 8) & 0xff)
#define IPMI_OP_RGN_CMD(offset) (offset & 0xff)
static void acpi_format_ipmi_msg(struct acpi_ipmi_msg *tx_msg,
acpi_physical_address address,
acpi_integer *value)
{
struct kernel_ipmi_msg *msg;
struct acpi_ipmi_buffer *buffer;
struct acpi_ipmi_device *device;
msg = &tx_msg->tx_message;
/*
* IPMI network function and command are encoded in the address
* within the IPMI OpRegion; see ACPI 4.0, sec 5.5.2.4.3.
*/
msg->netfn = IPMI_OP_RGN_NETFN(address);
msg->cmd = IPMI_OP_RGN_CMD(address);
msg->data = tx_msg->tx_data;
/*
* value is the parameter passed by the IPMI opregion space handler.
* It points to the IPMI request message buffer
*/
buffer = (struct acpi_ipmi_buffer *)value;
/* copy the tx message data */
msg->data_len = buffer->length;
memcpy(tx_msg->tx_data, buffer->data, msg->data_len);
/*
* now the default type is SYSTEM_INTERFACE and channel type is BMC.
* If the netfn is APP_REQUEST and the cmd is SEND_MESSAGE,
* the addr type should be changed to IPMB. Then we will have to parse
* the IPMI request message buffer to get the IPMB address.
* If so, please fix me.
*/
tx_msg->addr.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
tx_msg->addr.channel = IPMI_BMC_CHANNEL;
tx_msg->addr.data[0] = 0;
/* Get the msgid */
device = tx_msg->device;
mutex_lock(&device->tx_msg_lock);
device->curr_msgid++;
tx_msg->tx_msgid = device->curr_msgid;
mutex_unlock(&device->tx_msg_lock);
}
static void acpi_format_ipmi_response(struct acpi_ipmi_msg *msg,
acpi_integer *value, int rem_time)
{
struct acpi_ipmi_buffer *buffer;
/*
* value is also used as output parameter. It represents the response
* IPMI message returned by IPMI command.
*/
buffer = (struct acpi_ipmi_buffer *)value;
if (!rem_time && !msg->msg_done) {
buffer->status = ACPI_IPMI_TIMEOUT;
return;
}
/*
* If the flag of msg_done is not set or the recv length is zero, it
* means that the IPMI command is not executed correctly.
* The status code will be ACPI_IPMI_UNKNOWN.
*/
if (!msg->msg_done || !msg->rx_len) {
buffer->status = ACPI_IPMI_UNKNOWN;
return;
}
/*
* If the IPMI response message is obtained correctly, the status code
* will be ACPI_IPMI_OK
*/
buffer->status = ACPI_IPMI_OK;
buffer->length = msg->rx_len;
memcpy(buffer->data, msg->rx_data, msg->rx_len);
}
static void ipmi_flush_tx_msg(struct acpi_ipmi_device *ipmi)
{
struct acpi_ipmi_msg *tx_msg, *temp;
int count = HZ / 10;
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
list_for_each_entry_safe(tx_msg, temp, &ipmi->tx_msg_list, head) {
/* wake up the sleep thread on the Tx msg */
complete(&tx_msg->tx_complete);
}
/* wait for about 100ms to flush the tx message list */
while (count--) {
if (list_empty(&ipmi->tx_msg_list))
break;
schedule_timeout(1);
}
if (!list_empty(&ipmi->tx_msg_list))
dev_warn(&pnp_dev->dev, "tx msg list is not NULL\n");
}
static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data)
{
struct acpi_ipmi_device *ipmi_device = user_msg_data;
int msg_found = 0;
struct acpi_ipmi_msg *tx_msg;
struct pnp_dev *pnp_dev = ipmi_device->pnp_dev;
if (msg->user != ipmi_device->user_interface) {
dev_warn(&pnp_dev->dev, "Unexpected response is returned. "
"returned user %p, expected user %p\n",
msg->user, ipmi_device->user_interface);
ipmi_free_recv_msg(msg);
return;
}
mutex_lock(&ipmi_device->tx_msg_lock);
list_for_each_entry(tx_msg, &ipmi_device->tx_msg_list, head) {
if (msg->msgid == tx_msg->tx_msgid) {
msg_found = 1;
break;
}
}
mutex_unlock(&ipmi_device->tx_msg_lock);
if (!msg_found) {
dev_warn(&pnp_dev->dev, "Unexpected response (msg id %ld) is "
"returned.\n", msg->msgid);
ipmi_free_recv_msg(msg);
return;
}
if (msg->msg.data_len) {
/* copy the response data to Rx_data buffer */
memcpy(tx_msg->rx_data, msg->msg_data, msg->msg.data_len);
tx_msg->rx_len = msg->msg.data_len;
tx_msg->msg_done = 1;
}
complete(&tx_msg->tx_complete);
ipmi_free_recv_msg(msg);
};
static void ipmi_register_bmc(int iface, struct device *dev)
{
struct acpi_ipmi_device *ipmi_device, *temp;
struct pnp_dev *pnp_dev;
ipmi_user_t user;
int err;
struct ipmi_smi_info smi_data;
acpi_handle handle;
err = ipmi_get_smi_info(iface, &smi_data);
if (err)
return;
if (smi_data.addr_src != SI_ACPI) {
put_device(smi_data.dev);
return;
}
handle = smi_data.addr_info.acpi_info.acpi_handle;
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry(temp, &driver_data.ipmi_devices, head) {
/*
* if the corresponding ACPI handle is already added
* to the device list, don't add it again.
*/
if (temp->handle == handle)
goto out;
}
ipmi_device = kzalloc(sizeof(*ipmi_device), GFP_KERNEL);
if (!ipmi_device)
goto out;
pnp_dev = to_pnp_dev(smi_data.dev);
ipmi_device->handle = handle;
ipmi_device->pnp_dev = pnp_dev;
err = ipmi_create_user(iface, &driver_data.ipmi_hndlrs,
ipmi_device, &user);
if (err) {
dev_warn(&pnp_dev->dev, "Can't create IPMI user interface\n");
kfree(ipmi_device);
goto out;
}
acpi_add_ipmi_device(ipmi_device);
ipmi_device->user_interface = user;
ipmi_device->ipmi_ifnum = iface;
mutex_unlock(&driver_data.ipmi_lock);
memcpy(&ipmi_device->smi_data, &smi_data, sizeof(struct ipmi_smi_info));
return;
out:
mutex_unlock(&driver_data.ipmi_lock);
put_device(smi_data.dev);
return;
}
static void ipmi_bmc_gone(int iface)
{
struct acpi_ipmi_device *ipmi_device, *temp;
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry_safe(ipmi_device, temp,
&driver_data.ipmi_devices, head) {
if (ipmi_device->ipmi_ifnum != iface)
continue;
acpi_remove_ipmi_device(ipmi_device);
put_device(ipmi_device->smi_data.dev);
kfree(ipmi_device);
break;
}
mutex_unlock(&driver_data.ipmi_lock);
}
/* --------------------------------------------------------------------------
* Address Space Management
* -------------------------------------------------------------------------- */
/*
* This is the IPMI opregion space handler.
* @function: indicates the read/write. In fact as the IPMI message is driven
* by command, only write is meaningful.
* @address: This contains the netfn/command of IPMI request message.
* @bits : not used.
* @value : it is an in/out parameter. It points to the IPMI message buffer.
* Before the IPMI message is sent, it represents the actual request
* IPMI message. After the IPMI message is finished, it represents
* the response IPMI message returned by IPMI command.
* @handler_context: IPMI device context.
*/
static acpi_status
acpi_ipmi_space_handler(u32 function, acpi_physical_address address,
u32 bits, acpi_integer *value,
void *handler_context, void *region_context)
{
struct acpi_ipmi_msg *tx_msg;
struct acpi_ipmi_device *ipmi_device = handler_context;
int err, rem_time;
acpi_status status;
/*
* IPMI opregion message.
* IPMI message is firstly written to the BMC and system software
* can get the respsonse. So it is unmeaningful for the read access
* of IPMI opregion.
*/
if ((function & ACPI_IO_MASK) == ACPI_READ)
return AE_TYPE;
if (!ipmi_device->user_interface)
return AE_NOT_EXIST;
tx_msg = acpi_alloc_ipmi_msg(ipmi_device);
if (!tx_msg)
return AE_NO_MEMORY;
acpi_format_ipmi_msg(tx_msg, address, value);
mutex_lock(&ipmi_device->tx_msg_lock);
list_add_tail(&tx_msg->head, &ipmi_device->tx_msg_list);
mutex_unlock(&ipmi_device->tx_msg_lock);
err = ipmi_request_settime(ipmi_device->user_interface,
&tx_msg->addr,
tx_msg->tx_msgid,
&tx_msg->tx_message,
NULL, 0, 0, 0);
if (err) {
status = AE_ERROR;
goto end_label;
}
rem_time = wait_for_completion_timeout(&tx_msg->tx_complete,
IPMI_TIMEOUT);
acpi_format_ipmi_response(tx_msg, value, rem_time);
status = AE_OK;
end_label:
mutex_lock(&ipmi_device->tx_msg_lock);
list_del(&tx_msg->head);
mutex_unlock(&ipmi_device->tx_msg_lock);
kfree(tx_msg);
return status;
}
static void ipmi_remove_space_handler(struct acpi_ipmi_device *ipmi)
{
if (!test_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags))
return;
acpi_remove_address_space_handler(ipmi->handle,
ACPI_ADR_SPACE_IPMI, &acpi_ipmi_space_handler);
clear_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags);
}
static int ipmi_install_space_handler(struct acpi_ipmi_device *ipmi)
{
acpi_status status;
if (test_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags))
return 0;
status = acpi_install_address_space_handler(ipmi->handle,
ACPI_ADR_SPACE_IPMI,
&acpi_ipmi_space_handler,
NULL, ipmi);
if (ACPI_FAILURE(status)) {
struct pnp_dev *pnp_dev = ipmi->pnp_dev;
dev_warn(&pnp_dev->dev, "Can't register IPMI opregion space "
"handle\n");
return -EINVAL;
}
set_bit(IPMI_FLAGS_HANDLER_INSTALL, &ipmi->flags);
return 0;
}
static void acpi_add_ipmi_device(struct acpi_ipmi_device *ipmi_device)
{
INIT_LIST_HEAD(&ipmi_device->head);
mutex_init(&ipmi_device->tx_msg_lock);
INIT_LIST_HEAD(&ipmi_device->tx_msg_list);
ipmi_install_space_handler(ipmi_device);
list_add_tail(&ipmi_device->head, &driver_data.ipmi_devices);
}
static void acpi_remove_ipmi_device(struct acpi_ipmi_device *ipmi_device)
{
/*
* If the IPMI user interface is created, it should be
* destroyed.
*/
if (ipmi_device->user_interface) {
ipmi_destroy_user(ipmi_device->user_interface);
ipmi_device->user_interface = NULL;
}
/* flush the Tx_msg list */
if (!list_empty(&ipmi_device->tx_msg_list))
ipmi_flush_tx_msg(ipmi_device);
list_del(&ipmi_device->head);
ipmi_remove_space_handler(ipmi_device);
}
static int __init acpi_ipmi_init(void)
{
int result = 0;
if (acpi_disabled)
return result;
mutex_init(&driver_data.ipmi_lock);
result = ipmi_smi_watcher_register(&driver_data.bmc_events);
return result;
}
static void __exit acpi_ipmi_exit(void)
{
struct acpi_ipmi_device *ipmi_device, *temp;
if (acpi_disabled)
return;
ipmi_smi_watcher_unregister(&driver_data.bmc_events);
/*
* When one smi_watcher is unregistered, it is only deleted
* from the smi_watcher list. But the smi_gone callback function
* is not called. So explicitly uninstall the ACPI IPMI oregion
* handler and free it.
*/
mutex_lock(&driver_data.ipmi_lock);
list_for_each_entry_safe(ipmi_device, temp,
&driver_data.ipmi_devices, head) {
acpi_remove_ipmi_device(ipmi_device);
put_device(ipmi_device->smi_data.dev);
kfree(ipmi_device);
}
mutex_unlock(&driver_data.ipmi_lock);
}
module_init(acpi_ipmi_init);
module_exit(acpi_ipmi_exit);
| gpl-2.0 |
philippedeswert/kernel-adaptation-n950-n9 | drivers/infiniband/ulp/ipoib/ipoib_ethtool.c | 8110 | 2985 | /*
* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/kernel.h>
#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include "ipoib.h"
static void ipoib_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
{
strncpy(drvinfo->driver, "ipoib", sizeof(drvinfo->driver) - 1);
}
static int ipoib_get_coalesce(struct net_device *dev,
struct ethtool_coalesce *coal)
{
struct ipoib_dev_priv *priv = netdev_priv(dev);
coal->rx_coalesce_usecs = priv->ethtool.coalesce_usecs;
coal->rx_max_coalesced_frames = priv->ethtool.max_coalesced_frames;
return 0;
}
static int ipoib_set_coalesce(struct net_device *dev,
struct ethtool_coalesce *coal)
{
struct ipoib_dev_priv *priv = netdev_priv(dev);
int ret;
/*
* These values are saved in the private data and returned
* when ipoib_get_coalesce() is called
*/
if (coal->rx_coalesce_usecs > 0xffff ||
coal->rx_max_coalesced_frames > 0xffff)
return -EINVAL;
ret = ib_modify_cq(priv->recv_cq, coal->rx_max_coalesced_frames,
coal->rx_coalesce_usecs);
if (ret && ret != -ENOSYS) {
ipoib_warn(priv, "failed modifying CQ (%d)\n", ret);
return ret;
}
priv->ethtool.coalesce_usecs = coal->rx_coalesce_usecs;
priv->ethtool.max_coalesced_frames = coal->rx_max_coalesced_frames;
return 0;
}
static const struct ethtool_ops ipoib_ethtool_ops = {
.get_drvinfo = ipoib_get_drvinfo,
.get_coalesce = ipoib_get_coalesce,
.set_coalesce = ipoib_set_coalesce,
};
void ipoib_set_ethtool_ops(struct net_device *dev)
{
SET_ETHTOOL_OPS(dev, &ipoib_ethtool_ops);
}
| gpl-2.0 |
regalstreak/Beast-Kernel-Samsung-StarPro | drivers/staging/vt6655/aes_ccmp.c | 8622 | 14285 | /*
* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
*
* File: aes_ccmp.c
*
* Purpose: AES_CCMP decryption
*
* Author: Warren Hsu
*
* Date: Feb 15, 2005
*
* Functions:
* AESbGenCCMP - Parsing RX-packet
*
*
* Revision History:
*
*/
#include "device.h"
#include "80211hdr.h"
/*--------------------- Static Definitions -------------------------*/
/*--------------------- Static Classes ----------------------------*/
/*--------------------- Static Variables --------------------------*/
/*
* SBOX Table
*/
unsigned char sbox_table[256] =
{
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
};
unsigned char dot2_table[256] = {
0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e,
0x60, 0x62, 0x64, 0x66, 0x68, 0x6a, 0x6c, 0x6e, 0x70, 0x72, 0x74, 0x76, 0x78, 0x7a, 0x7c, 0x7e,
0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9c, 0x9e,
0xa0, 0xa2, 0xa4, 0xa6, 0xa8, 0xaa, 0xac, 0xae, 0xb0, 0xb2, 0xb4, 0xb6, 0xb8, 0xba, 0xbc, 0xbe,
0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce, 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xea, 0xec, 0xee, 0xf0, 0xf2, 0xf4, 0xf6, 0xf8, 0xfa, 0xfc, 0xfe,
0x1b, 0x19, 0x1f, 0x1d, 0x13, 0x11, 0x17, 0x15, 0x0b, 0x09, 0x0f, 0x0d, 0x03, 0x01, 0x07, 0x05,
0x3b, 0x39, 0x3f, 0x3d, 0x33, 0x31, 0x37, 0x35, 0x2b, 0x29, 0x2f, 0x2d, 0x23, 0x21, 0x27, 0x25,
0x5b, 0x59, 0x5f, 0x5d, 0x53, 0x51, 0x57, 0x55, 0x4b, 0x49, 0x4f, 0x4d, 0x43, 0x41, 0x47, 0x45,
0x7b, 0x79, 0x7f, 0x7d, 0x73, 0x71, 0x77, 0x75, 0x6b, 0x69, 0x6f, 0x6d, 0x63, 0x61, 0x67, 0x65,
0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85,
0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5,
0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5,
0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5
};
unsigned char dot3_table[256] = {
0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09, 0x18, 0x1b, 0x1e, 0x1d, 0x14, 0x17, 0x12, 0x11,
0x30, 0x33, 0x36, 0x35, 0x3c, 0x3f, 0x3a, 0x39, 0x28, 0x2b, 0x2e, 0x2d, 0x24, 0x27, 0x22, 0x21,
0x60, 0x63, 0x66, 0x65, 0x6c, 0x6f, 0x6a, 0x69, 0x78, 0x7b, 0x7e, 0x7d, 0x74, 0x77, 0x72, 0x71,
0x50, 0x53, 0x56, 0x55, 0x5c, 0x5f, 0x5a, 0x59, 0x48, 0x4b, 0x4e, 0x4d, 0x44, 0x47, 0x42, 0x41,
0xc0, 0xc3, 0xc6, 0xc5, 0xcc, 0xcf, 0xca, 0xc9, 0xd8, 0xdb, 0xde, 0xdd, 0xd4, 0xd7, 0xd2, 0xd1,
0xf0, 0xf3, 0xf6, 0xf5, 0xfc, 0xff, 0xfa, 0xf9, 0xe8, 0xeb, 0xee, 0xed, 0xe4, 0xe7, 0xe2, 0xe1,
0xa0, 0xa3, 0xa6, 0xa5, 0xac, 0xaf, 0xaa, 0xa9, 0xb8, 0xbb, 0xbe, 0xbd, 0xb4, 0xb7, 0xb2, 0xb1,
0x90, 0x93, 0x96, 0x95, 0x9c, 0x9f, 0x9a, 0x99, 0x88, 0x8b, 0x8e, 0x8d, 0x84, 0x87, 0x82, 0x81,
0x9b, 0x98, 0x9d, 0x9e, 0x97, 0x94, 0x91, 0x92, 0x83, 0x80, 0x85, 0x86, 0x8f, 0x8c, 0x89, 0x8a,
0xab, 0xa8, 0xad, 0xae, 0xa7, 0xa4, 0xa1, 0xa2, 0xb3, 0xb0, 0xb5, 0xb6, 0xbf, 0xbc, 0xb9, 0xba,
0xfb, 0xf8, 0xfd, 0xfe, 0xf7, 0xf4, 0xf1, 0xf2, 0xe3, 0xe0, 0xe5, 0xe6, 0xef, 0xec, 0xe9, 0xea,
0xcb, 0xc8, 0xcd, 0xce, 0xc7, 0xc4, 0xc1, 0xc2, 0xd3, 0xd0, 0xd5, 0xd6, 0xdf, 0xdc, 0xd9, 0xda,
0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a,
0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a,
0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a,
0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a
};
/*--------------------- Static Functions --------------------------*/
/*--------------------- Export Variables --------------------------*/
/*--------------------- Export Functions --------------------------*/
void xor_128(unsigned char *a, unsigned char *b, unsigned char *out)
{
unsigned long *dwPtrA = (unsigned long *) a;
unsigned long *dwPtrB = (unsigned long *) b;
unsigned long *dwPtrOut =(unsigned long *) out;
(*dwPtrOut++) = (*dwPtrA++) ^ (*dwPtrB++);
(*dwPtrOut++) = (*dwPtrA++) ^ (*dwPtrB++);
(*dwPtrOut++) = (*dwPtrA++) ^ (*dwPtrB++);
(*dwPtrOut++) = (*dwPtrA++) ^ (*dwPtrB++);
}
void xor_32(unsigned char *a, unsigned char *b, unsigned char *out)
{
unsigned long *dwPtrA = (unsigned long *) a;
unsigned long *dwPtrB = (unsigned long *) b;
unsigned long *dwPtrOut =(unsigned long *) out;
(*dwPtrOut++) = (*dwPtrA++) ^ (*dwPtrB++);
}
void AddRoundKey(unsigned char *key, int round)
{
unsigned char sbox_key[4];
unsigned char rcon_table[10] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36};
sbox_key[0] = sbox_table[key[13]];
sbox_key[1] = sbox_table[key[14]];
sbox_key[2] = sbox_table[key[15]];
sbox_key[3] = sbox_table[key[12]];
key[0] = key[0] ^ rcon_table[round];
xor_32(&key[0], sbox_key, &key[0]);
xor_32(&key[4], &key[0], &key[4]);
xor_32(&key[8], &key[4], &key[8]);
xor_32(&key[12], &key[8], &key[12]);
}
void SubBytes(unsigned char *in, unsigned char *out)
{
int i;
for (i=0; i< 16; i++)
{
out[i] = sbox_table[in[i]];
}
}
void ShiftRows(unsigned char *in, unsigned char *out)
{
out[0] = in[0];
out[1] = in[5];
out[2] = in[10];
out[3] = in[15];
out[4] = in[4];
out[5] = in[9];
out[6] = in[14];
out[7] = in[3];
out[8] = in[8];
out[9] = in[13];
out[10] = in[2];
out[11] = in[7];
out[12] = in[12];
out[13] = in[1];
out[14] = in[6];
out[15] = in[11];
}
void MixColumns(unsigned char *in, unsigned char *out)
{
out[0] = dot2_table[in[0]] ^ dot3_table[in[1]] ^ in[2] ^ in[3];
out[1] = in[0] ^ dot2_table[in[1]] ^ dot3_table[in[2]] ^ in[3];
out[2] = in[0] ^ in[1] ^ dot2_table[in[2]] ^ dot3_table[in[3]];
out[3] = dot3_table[in[0]] ^ in[1] ^ in[2] ^ dot2_table[in[3]];
}
void AESv128(unsigned char *key, unsigned char *data, unsigned char *ciphertext)
{
int i;
int round;
unsigned char TmpdataA[16];
unsigned char TmpdataB[16];
unsigned char abyRoundKey[16];
for(i=0; i<16; i++)
abyRoundKey[i] = key[i];
for (round = 0; round < 11; round++)
{
if (round == 0)
{
xor_128(abyRoundKey, data, ciphertext);
AddRoundKey(abyRoundKey, round);
}
else if (round == 10)
{
SubBytes(ciphertext, TmpdataA);
ShiftRows(TmpdataA, TmpdataB);
xor_128(TmpdataB, abyRoundKey, ciphertext);
}
else // round 1 ~ 9
{
SubBytes(ciphertext, TmpdataA);
ShiftRows(TmpdataA, TmpdataB);
MixColumns(&TmpdataB[0], &TmpdataA[0]);
MixColumns(&TmpdataB[4], &TmpdataA[4]);
MixColumns(&TmpdataB[8], &TmpdataA[8]);
MixColumns(&TmpdataB[12], &TmpdataA[12]);
xor_128(TmpdataA, abyRoundKey, ciphertext);
AddRoundKey(abyRoundKey, round);
}
}
}
/*
* Description: AES decryption
*
* Parameters:
* In:
* pbyRxKey - The key used to decrypt
* pbyFrame - Starting address of packet header
* wFrameSize - Total packet size including CRC
* Out:
* none
*
* Return Value: MIC compare result
*
*/
bool AESbGenCCMP(unsigned char *pbyRxKey, unsigned char *pbyFrame, unsigned short wFrameSize)
{
unsigned char abyNonce[13];
unsigned char MIC_IV[16];
unsigned char MIC_HDR1[16];
unsigned char MIC_HDR2[16];
unsigned char abyMIC[16];
unsigned char abyCTRPLD[16];
unsigned char abyTmp[16];
unsigned char abyPlainText[16];
unsigned char abyLastCipher[16];
PS802_11Header pMACHeader = (PS802_11Header) pbyFrame;
unsigned char *pbyIV;
unsigned char *pbyPayload;
unsigned short wHLen = 22;
unsigned short wPayloadSize = wFrameSize - 8 - 8 - 4 - WLAN_HDR_ADDR3_LEN;//8 is IV, 8 is MIC, 4 is CRC
bool bA4 = false;
unsigned char byTmp;
unsigned short wCnt;
int ii,jj,kk;
pbyIV = pbyFrame + WLAN_HDR_ADDR3_LEN;
if ( WLAN_GET_FC_TODS(*(unsigned short *)pbyFrame) &&
WLAN_GET_FC_FROMDS(*(unsigned short *)pbyFrame) ) {
bA4 = true;
pbyIV += 6; // 6 is 802.11 address4
wHLen += 6;
wPayloadSize -= 6;
}
pbyPayload = pbyIV + 8; //IV-length
abyNonce[0] = 0x00; //now is 0, if Qos here will be priority
memcpy(&(abyNonce[1]), pMACHeader->abyAddr2, ETH_ALEN);
abyNonce[7] = pbyIV[7];
abyNonce[8] = pbyIV[6];
abyNonce[9] = pbyIV[5];
abyNonce[10] = pbyIV[4];
abyNonce[11] = pbyIV[1];
abyNonce[12] = pbyIV[0];
//MIC_IV
MIC_IV[0] = 0x59;
memcpy(&(MIC_IV[1]), &(abyNonce[0]), 13);
MIC_IV[14] = (unsigned char)(wPayloadSize >> 8);
MIC_IV[15] = (unsigned char)(wPayloadSize & 0xff);
//MIC_HDR1
MIC_HDR1[0] = (unsigned char)(wHLen >> 8);
MIC_HDR1[1] = (unsigned char)(wHLen & 0xff);
byTmp = (unsigned char)(pMACHeader->wFrameCtl & 0xff);
MIC_HDR1[2] = byTmp & 0x8f;
byTmp = (unsigned char)(pMACHeader->wFrameCtl >> 8);
byTmp &= 0x87;
MIC_HDR1[3] = byTmp | 0x40;
memcpy(&(MIC_HDR1[4]), pMACHeader->abyAddr1, ETH_ALEN);
memcpy(&(MIC_HDR1[10]), pMACHeader->abyAddr2, ETH_ALEN);
//MIC_HDR2
memcpy(&(MIC_HDR2[0]), pMACHeader->abyAddr3, ETH_ALEN);
byTmp = (unsigned char)(pMACHeader->wSeqCtl & 0xff);
MIC_HDR2[6] = byTmp & 0x0f;
MIC_HDR2[7] = 0;
if ( bA4 ) {
memcpy(&(MIC_HDR2[8]), pMACHeader->abyAddr4, ETH_ALEN);
} else {
MIC_HDR2[8] = 0x00;
MIC_HDR2[9] = 0x00;
MIC_HDR2[10] = 0x00;
MIC_HDR2[11] = 0x00;
MIC_HDR2[12] = 0x00;
MIC_HDR2[13] = 0x00;
}
MIC_HDR2[14] = 0x00;
MIC_HDR2[15] = 0x00;
//CCMP
AESv128(pbyRxKey,MIC_IV,abyMIC);
for ( kk=0; kk<16; kk++ ) {
abyTmp[kk] = MIC_HDR1[kk] ^ abyMIC[kk];
}
AESv128(pbyRxKey,abyTmp,abyMIC);
for ( kk=0; kk<16; kk++ ) {
abyTmp[kk] = MIC_HDR2[kk] ^ abyMIC[kk];
}
AESv128(pbyRxKey,abyTmp,abyMIC);
wCnt = 1;
abyCTRPLD[0] = 0x01;
memcpy(&(abyCTRPLD[1]), &(abyNonce[0]), 13);
for(jj=wPayloadSize; jj>16; jj=jj-16) {
abyCTRPLD[14] = (unsigned char) (wCnt >> 8);
abyCTRPLD[15] = (unsigned char) (wCnt & 0xff);
AESv128(pbyRxKey,abyCTRPLD,abyTmp);
for ( kk=0; kk<16; kk++ ) {
abyPlainText[kk] = abyTmp[kk] ^ pbyPayload[kk];
}
for ( kk=0; kk<16; kk++ ) {
abyTmp[kk] = abyMIC[kk] ^ abyPlainText[kk];
}
AESv128(pbyRxKey,abyTmp,abyMIC);
memcpy(pbyPayload, abyPlainText, 16);
wCnt++;
pbyPayload += 16;
} //for wPayloadSize
//last payload
memcpy(&(abyLastCipher[0]), pbyPayload, jj);
for ( ii=jj; ii<16; ii++ ) {
abyLastCipher[ii] = 0x00;
}
abyCTRPLD[14] = (unsigned char) (wCnt >> 8);
abyCTRPLD[15] = (unsigned char) (wCnt & 0xff);
AESv128(pbyRxKey,abyCTRPLD,abyTmp);
for ( kk=0; kk<16; kk++ ) {
abyPlainText[kk] = abyTmp[kk] ^ abyLastCipher[kk];
}
memcpy(pbyPayload, abyPlainText, jj);
pbyPayload += jj;
//for MIC calculation
for ( ii=jj; ii<16; ii++ ) {
abyPlainText[ii] = 0x00;
}
for ( kk=0; kk<16; kk++ ) {
abyTmp[kk] = abyMIC[kk] ^ abyPlainText[kk];
}
AESv128(pbyRxKey,abyTmp,abyMIC);
//=>above is the calculate MIC
//--------------------------------------------
wCnt = 0;
abyCTRPLD[14] = (unsigned char) (wCnt >> 8);
abyCTRPLD[15] = (unsigned char) (wCnt & 0xff);
AESv128(pbyRxKey,abyCTRPLD,abyTmp);
for ( kk=0; kk<8; kk++ ) {
abyTmp[kk] = abyTmp[kk] ^ pbyPayload[kk];
}
//=>above is the dec-MIC from packet
//--------------------------------------------
if ( !memcmp(abyMIC,abyTmp,8) ) {
return true;
} else {
return false;
}
}
| gpl-2.0 |
qwertyTom/android_kernel_cyanogen_msm8916 | drivers/scsi/FlashPoint.c | 10414 | 200499 | /*
FlashPoint.c -- FlashPoint SCCB Manager for Linux
This file contains the FlashPoint SCCB Manager from BusLogic's FlashPoint
Driver Developer's Kit, with minor modifications by Leonard N. Zubkoff for
Linux compatibility. It was provided by BusLogic in the form of 16 separate
source files, which would have unnecessarily cluttered the scsi directory, so
the individual files have been combined into this single file.
Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
This file is available under both the GNU General Public License
and a BSD-style copyright; see LICENSE.FlashPoint for details.
*/
#ifdef CONFIG_SCSI_FLASHPOINT
#define MAX_CARDS 8
#undef BUSTYPE_PCI
#define CRCMASK 0xA001
#define FAILURE 0xFFFFFFFFL
struct sccb;
typedef void (*CALL_BK_FN) (struct sccb *);
struct sccb_mgr_info {
unsigned long si_baseaddr;
unsigned char si_present;
unsigned char si_intvect;
unsigned char si_id;
unsigned char si_lun;
unsigned short si_fw_revision;
unsigned short si_per_targ_init_sync;
unsigned short si_per_targ_fast_nego;
unsigned short si_per_targ_ultra_nego;
unsigned short si_per_targ_no_disc;
unsigned short si_per_targ_wide_nego;
unsigned short si_flags;
unsigned char si_card_family;
unsigned char si_bustype;
unsigned char si_card_model[3];
unsigned char si_relative_cardnum;
unsigned char si_reserved[4];
unsigned long si_OS_reserved;
unsigned char si_XlatInfo[4];
unsigned long si_reserved2[5];
unsigned long si_secondary_range;
};
#define SCSI_PARITY_ENA 0x0001
#define LOW_BYTE_TERM 0x0010
#define HIGH_BYTE_TERM 0x0020
#define BUSTYPE_PCI 0x3
#define SUPPORT_16TAR_32LUN 0x0002
#define SOFT_RESET 0x0004
#define EXTENDED_TRANSLATION 0x0008
#define POST_ALL_UNDERRRUNS 0x0040
#define FLAG_SCAM_ENABLED 0x0080
#define FLAG_SCAM_LEVEL2 0x0100
#define HARPOON_FAMILY 0x02
/* SCCB struct used for both SCCB and UCB manager compiles!
* The UCB Manager treats the SCCB as it's 'native hardware structure'
*/
#pragma pack(1)
struct sccb {
unsigned char OperationCode;
unsigned char ControlByte;
unsigned char CdbLength;
unsigned char RequestSenseLength;
unsigned long DataLength;
unsigned long DataPointer;
unsigned char CcbRes[2];
unsigned char HostStatus;
unsigned char TargetStatus;
unsigned char TargID;
unsigned char Lun;
unsigned char Cdb[12];
unsigned char CcbRes1;
unsigned char Reserved1;
unsigned long Reserved2;
unsigned long SensePointer;
CALL_BK_FN SccbCallback; /* VOID (*SccbCallback)(); */
unsigned long SccbIOPort; /* Identifies board base port */
unsigned char SccbStatus;
unsigned char SCCBRes2;
unsigned short SccbOSFlags;
unsigned long Sccb_XferCnt; /* actual transfer count */
unsigned long Sccb_ATC;
unsigned long SccbVirtDataPtr; /* virtual addr for OS/2 */
unsigned long Sccb_res1;
unsigned short Sccb_MGRFlags;
unsigned short Sccb_sgseg;
unsigned char Sccb_scsimsg; /* identify msg for selection */
unsigned char Sccb_tag;
unsigned char Sccb_scsistat;
unsigned char Sccb_idmsg; /* image of last msg in */
struct sccb *Sccb_forwardlink;
struct sccb *Sccb_backlink;
unsigned long Sccb_savedATC;
unsigned char Save_Cdb[6];
unsigned char Save_CdbLen;
unsigned char Sccb_XferState;
unsigned long Sccb_SGoffset;
};
#pragma pack()
#define SCATTER_GATHER_COMMAND 0x02
#define RESIDUAL_COMMAND 0x03
#define RESIDUAL_SG_COMMAND 0x04
#define RESET_COMMAND 0x81
#define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */
#define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */
#define SCCB_DATA_XFER_OUT 0x10 /* Write */
#define SCCB_DATA_XFER_IN 0x08 /* Read */
#define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */
#define BUS_FREE_ST 0
#define SELECT_ST 1
#define SELECT_BDR_ST 2 /* Select w\ Bus Device Reset */
#define SELECT_SN_ST 3 /* Select w\ Sync Nego */
#define SELECT_WN_ST 4 /* Select w\ Wide Data Nego */
#define SELECT_Q_ST 5 /* Select w\ Tagged Q'ing */
#define COMMAND_ST 6
#define DATA_OUT_ST 7
#define DATA_IN_ST 8
#define DISCONNECT_ST 9
#define ABORT_ST 11
#define F_HOST_XFER_DIR 0x01
#define F_ALL_XFERRED 0x02
#define F_SG_XFER 0x04
#define F_AUTO_SENSE 0x08
#define F_ODD_BALL_CNT 0x10
#define F_NO_DATA_YET 0x80
#define F_STATUSLOADED 0x01
#define F_DEV_SELECTED 0x04
#define SCCB_COMPLETE 0x00 /* SCCB completed without error */
#define SCCB_DATA_UNDER_RUN 0x0C
#define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */
#define SCCB_DATA_OVER_RUN 0x12
#define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */
#define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */
#define SCCB_BM_ERR 0x30 /* BusMaster error. */
#define SCCB_PARITY_ERR 0x34 /* SCSI parity error */
#define SCCB_IN_PROCESS 0x00
#define SCCB_SUCCESS 0x01
#define SCCB_ABORT 0x02
#define SCCB_ERROR 0x04
#define ORION_FW_REV 3110
#define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */
#define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */
#define MAX_SCSI_TAR 16
#define MAX_LUN 32
#define LUN_MASK 0x1f
#define SG_BUF_CNT 16 /*Number of prefetched elements. */
#define SG_ELEMENT_SIZE 8 /*Eight byte per element. */
#define RD_HARPOON(ioport) inb((u32)ioport)
#define RDW_HARPOON(ioport) inw((u32)ioport)
#define RD_HARP32(ioport,offset,data) (data = inl((u32)(ioport + offset)))
#define WR_HARPOON(ioport,val) outb((u8) val, (u32)ioport)
#define WRW_HARPOON(ioport,val) outw((u16)val, (u32)ioport)
#define WR_HARP32(ioport,offset,data) outl(data, (u32)(ioport + offset))
#define TAR_SYNC_MASK (BIT(7)+BIT(6))
#define SYNC_TRYING BIT(6)
#define SYNC_SUPPORTED (BIT(7)+BIT(6))
#define TAR_WIDE_MASK (BIT(5)+BIT(4))
#define WIDE_ENABLED BIT(4)
#define WIDE_NEGOCIATED BIT(5)
#define TAR_TAG_Q_MASK (BIT(3)+BIT(2))
#define TAG_Q_TRYING BIT(2)
#define TAG_Q_REJECT BIT(3)
#define TAR_ALLOW_DISC BIT(0)
#define EE_SYNC_MASK (BIT(0)+BIT(1))
#define EE_SYNC_5MB BIT(0)
#define EE_SYNC_10MB BIT(1)
#define EE_SYNC_20MB (BIT(0)+BIT(1))
#define EE_WIDE_SCSI BIT(7)
struct sccb_mgr_tar_info {
struct sccb *TarSelQ_Head;
struct sccb *TarSelQ_Tail;
unsigned char TarLUN_CA; /*Contingent Allgiance */
unsigned char TarTagQ_Cnt;
unsigned char TarSelQ_Cnt;
unsigned char TarStatus;
unsigned char TarEEValue;
unsigned char TarSyncCtrl;
unsigned char TarReserved[2]; /* for alignment */
unsigned char LunDiscQ_Idx[MAX_LUN];
unsigned char TarLUNBusy[MAX_LUN];
};
struct nvram_info {
unsigned char niModel; /* Model No. of card */
unsigned char niCardNo; /* Card no. */
unsigned long niBaseAddr; /* Port Address of card */
unsigned char niSysConf; /* Adapter Configuration byte - Byte 16 of eeprom map */
unsigned char niScsiConf; /* SCSI Configuration byte - Byte 17 of eeprom map */
unsigned char niScamConf; /* SCAM Configuration byte - Byte 20 of eeprom map */
unsigned char niAdapId; /* Host Adapter ID - Byte 24 of eerpom map */
unsigned char niSyncTbl[MAX_SCSI_TAR / 2]; /* Sync/Wide byte of targets */
unsigned char niScamTbl[MAX_SCSI_TAR][4]; /* Compressed Scam name string of Targets */
};
#define MODEL_LT 1
#define MODEL_DL 2
#define MODEL_LW 3
#define MODEL_DW 4
struct sccb_card {
struct sccb *currentSCCB;
struct sccb_mgr_info *cardInfo;
unsigned long ioPort;
unsigned short cmdCounter;
unsigned char discQCount;
unsigned char tagQ_Lst;
unsigned char cardIndex;
unsigned char scanIndex;
unsigned char globalFlags;
unsigned char ourId;
struct nvram_info *pNvRamInfo;
struct sccb *discQ_Tbl[QUEUE_DEPTH];
};
#define F_TAG_STARTED 0x01
#define F_CONLUN_IO 0x02
#define F_DO_RENEGO 0x04
#define F_NO_FILTER 0x08
#define F_GREEN_PC 0x10
#define F_HOST_XFER_ACT 0x20
#define F_NEW_SCCB_CMD 0x40
#define F_UPDATE_EEPROM 0x80
#define ID_STRING_LENGTH 32
#define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */
#define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */
#define ASSIGN_ID 0x00
#define SET_P_FLAG 0x01
#define CFG_CMPLT 0x03
#define DOM_MSTR 0x0F
#define SYNC_PTRN 0x1F
#define ID_0_7 0x18
#define ID_8_F 0x11
#define MISC_CODE 0x14
#define CLR_P_FLAG 0x18
#define INIT_SELTD 0x01
#define LEVEL2_TAR 0x02
enum scam_id_st { ID0, ID1, ID2, ID3, ID4, ID5, ID6, ID7, ID8, ID9, ID10, ID11,
ID12,
ID13, ID14, ID15, ID_UNUSED, ID_UNASSIGNED, ID_ASSIGNED, LEGACY,
CLR_PRIORITY, NO_ID_AVAIL
};
typedef struct SCCBscam_info {
unsigned char id_string[ID_STRING_LENGTH];
enum scam_id_st state;
} SCCBSCAM_INFO;
#define SCSI_REQUEST_SENSE 0x03
#define SCSI_READ 0x08
#define SCSI_WRITE 0x0A
#define SCSI_START_STOP_UNIT 0x1B
#define SCSI_READ_EXTENDED 0x28
#define SCSI_WRITE_EXTENDED 0x2A
#define SCSI_WRITE_AND_VERIFY 0x2E
#define SSGOOD 0x00
#define SSCHECK 0x02
#define SSQ_FULL 0x28
#define SMCMD_COMP 0x00
#define SMEXT 0x01
#define SMSAVE_DATA_PTR 0x02
#define SMREST_DATA_PTR 0x03
#define SMDISC 0x04
#define SMABORT 0x06
#define SMREJECT 0x07
#define SMNO_OP 0x08
#define SMPARITY 0x09
#define SMDEV_RESET 0x0C
#define SMABORT_TAG 0x0D
#define SMINIT_RECOVERY 0x0F
#define SMREL_RECOVERY 0x10
#define SMIDENT 0x80
#define DISC_PRIV 0x40
#define SMSYNC 0x01
#define SMWDTR 0x03
#define SM8BIT 0x00
#define SM16BIT 0x01
#define SMIGNORWR 0x23 /* Ignore Wide Residue */
#define SIX_BYTE_CMD 0x06
#define TWELVE_BYTE_CMD 0x0C
#define ASYNC 0x00
#define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */
#define EEPROM_WD_CNT 256
#define EEPROM_CHECK_SUM 0
#define FW_SIGNATURE 2
#define MODEL_NUMB_0 4
#define MODEL_NUMB_2 6
#define MODEL_NUMB_4 8
#define SYSTEM_CONFIG 16
#define SCSI_CONFIG 17
#define BIOS_CONFIG 18
#define SCAM_CONFIG 20
#define ADAPTER_SCSI_ID 24
#define IGNORE_B_SCAN 32
#define SEND_START_ENA 34
#define DEVICE_ENABLE 36
#define SYNC_RATE_TBL 38
#define SYNC_RATE_TBL01 38
#define SYNC_RATE_TBL23 40
#define SYNC_RATE_TBL45 42
#define SYNC_RATE_TBL67 44
#define SYNC_RATE_TBL89 46
#define SYNC_RATE_TBLab 48
#define SYNC_RATE_TBLcd 50
#define SYNC_RATE_TBLef 52
#define EE_SCAMBASE 256
#define SCAM_ENABLED BIT(2)
#define SCAM_LEVEL2 BIT(3)
#define RENEGO_ENA BIT(10)
#define CONNIO_ENA BIT(11)
#define GREEN_PC_ENA BIT(12)
#define AUTO_RATE_00 00
#define AUTO_RATE_05 01
#define AUTO_RATE_10 02
#define AUTO_RATE_20 03
#define WIDE_NEGO_BIT BIT(7)
#define DISC_ENABLE_BIT BIT(6)
#define hp_vendor_id_0 0x00 /* LSB */
#define ORION_VEND_0 0x4B
#define hp_vendor_id_1 0x01 /* MSB */
#define ORION_VEND_1 0x10
#define hp_device_id_0 0x02 /* LSB */
#define ORION_DEV_0 0x30
#define hp_device_id_1 0x03 /* MSB */
#define ORION_DEV_1 0x81
/* Sub Vendor ID and Sub Device ID only available in
Harpoon Version 2 and higher */
#define hp_sub_device_id_0 0x06 /* LSB */
#define hp_semaphore 0x0C
#define SCCB_MGR_ACTIVE BIT(0)
#define TICKLE_ME BIT(1)
#define SCCB_MGR_PRESENT BIT(3)
#define BIOS_IN_USE BIT(4)
#define hp_sys_ctrl 0x0F
#define STOP_CLK BIT(0) /*Turn off BusMaster Clock */
#define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */
#define HALT_MACH BIT(3) /*Halt State Machine */
#define HARD_ABORT BIT(4) /*Hard Abort */
#define hp_host_blk_cnt 0x13
#define XFER_BLK64 0x06 /* 1 1 0 64 byte per block */
#define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes */
#define hp_int_mask 0x17
#define INT_CMD_COMPL BIT(0) /* DMA command complete */
#define INT_EXT_STATUS BIT(1) /* Extended Status Set */
#define hp_xfer_cnt_lo 0x18
#define hp_xfer_cnt_hi 0x1A
#define hp_xfer_cmd 0x1B
#define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */
#define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */
#define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */
#define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */
#define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */
#define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT))
#define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT))
#define hp_host_addr_lo 0x1C
#define hp_host_addr_hmi 0x1E
#define hp_ee_ctrl 0x22
#define EXT_ARB_ACK BIT(7)
#define SCSI_TERM_ENA_H BIT(6) /* SCSI high byte terminator */
#define SEE_MS BIT(5)
#define SEE_CS BIT(3)
#define SEE_CLK BIT(2)
#define SEE_DO BIT(1)
#define SEE_DI BIT(0)
#define EE_READ 0x06
#define EE_WRITE 0x05
#define EWEN 0x04
#define EWEN_ADDR 0x03C0
#define EWDS 0x04
#define EWDS_ADDR 0x0000
#define hp_bm_ctrl 0x26
#define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */
#define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */
#define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */
#define FAST_SINGLE BIT(6) /*?? */
#define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L)
#define hp_sg_addr 0x28
#define hp_page_ctrl 0x29
#define SCATTER_EN BIT(0)
#define SGRAM_ARAM BIT(1)
#define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */
#define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */
#define hp_pci_stat_cfg 0x2D
#define REC_MASTER_ABORT BIT(5) /*received Master abort */
#define hp_rev_num 0x33
#define hp_stack_data 0x34
#define hp_stack_addr 0x35
#define hp_ext_status 0x36
#define BM_FORCE_OFF BIT(0) /*Bus Master is forced to get off */
#define PCI_TGT_ABORT BIT(0) /*PCI bus master transaction aborted */
#define PCI_DEV_TMOUT BIT(1) /*PCI Device Time out */
#define CMD_ABORTED BIT(4) /*Command aborted */
#define BM_PARITY_ERR BIT(5) /*parity error on data received */
#define PIO_OVERRUN BIT(6) /*Slave data overrun */
#define BM_CMD_BUSY BIT(7) /*Bus master transfer command busy */
#define BAD_EXT_STATUS (BM_FORCE_OFF | PCI_DEV_TMOUT | CMD_ABORTED | \
BM_PARITY_ERR | PIO_OVERRUN)
#define hp_int_status 0x37
#define EXT_STATUS_ON BIT(1) /*Extended status is valid */
#define SCSI_INTERRUPT BIT(2) /*Global indication of a SCSI int. */
#define INT_ASSERTED BIT(5) /* */
#define hp_fifo_cnt 0x38
#define hp_intena 0x40
#define RESET BIT(7)
#define PROG_HLT BIT(6)
#define PARITY BIT(5)
#define FIFO BIT(4)
#define SEL BIT(3)
#define SCAM_SEL BIT(2)
#define RSEL BIT(1)
#define TIMEOUT BIT(0)
#define BUS_FREE BIT(15)
#define XFER_CNT_0 BIT(14)
#define PHASE BIT(13)
#define IUNKWN BIT(12)
#define ICMD_COMP BIT(11)
#define ITICKLE BIT(10)
#define IDO_STRT BIT(9)
#define ITAR_DISC BIT(8)
#define AUTO_INT (BIT(12)+BIT(11)+BIT(10)+BIT(9)+BIT(8))
#define CLR_ALL_INT 0xFFFF
#define CLR_ALL_INT_1 0xFF00
#define hp_intstat 0x42
#define hp_scsisig 0x44
#define SCSI_SEL BIT(7)
#define SCSI_BSY BIT(6)
#define SCSI_REQ BIT(5)
#define SCSI_ACK BIT(4)
#define SCSI_ATN BIT(3)
#define SCSI_CD BIT(2)
#define SCSI_MSG BIT(1)
#define SCSI_IOBIT BIT(0)
#define S_SCSI_PHZ (BIT(2)+BIT(1)+BIT(0))
#define S_MSGO_PH (BIT(2)+BIT(1) )
#define S_MSGI_PH (BIT(2)+BIT(1)+BIT(0))
#define S_DATAI_PH ( BIT(0))
#define S_DATAO_PH 0x00
#define S_ILL_PH ( BIT(1) )
#define hp_scsictrl_0 0x45
#define SEL_TAR BIT(6)
#define ENA_ATN BIT(4)
#define ENA_RESEL BIT(2)
#define SCSI_RST BIT(1)
#define ENA_SCAM_SEL BIT(0)
#define hp_portctrl_0 0x46
#define SCSI_PORT BIT(7)
#define SCSI_INBIT BIT(6)
#define DMA_PORT BIT(5)
#define DMA_RD BIT(4)
#define HOST_PORT BIT(3)
#define HOST_WRT BIT(2)
#define SCSI_BUS_EN BIT(1)
#define START_TO BIT(0)
#define hp_scsireset 0x47
#define SCSI_INI BIT(6)
#define SCAM_EN BIT(5)
#define DMA_RESET BIT(3)
#define HPSCSI_RESET BIT(2)
#define PROG_RESET BIT(1)
#define FIFO_CLR BIT(0)
#define hp_xfercnt_0 0x48
#define hp_xfercnt_2 0x4A
#define hp_fifodata_0 0x4C
#define hp_addstat 0x4E
#define SCAM_TIMER BIT(7)
#define SCSI_MODE8 BIT(3)
#define SCSI_PAR_ERR BIT(0)
#define hp_prgmcnt_0 0x4F
#define hp_selfid_0 0x50
#define hp_selfid_1 0x51
#define hp_arb_id 0x52
#define hp_select_id 0x53
#define hp_synctarg_base 0x54
#define hp_synctarg_12 0x54
#define hp_synctarg_13 0x55
#define hp_synctarg_14 0x56
#define hp_synctarg_15 0x57
#define hp_synctarg_8 0x58
#define hp_synctarg_9 0x59
#define hp_synctarg_10 0x5A
#define hp_synctarg_11 0x5B
#define hp_synctarg_4 0x5C
#define hp_synctarg_5 0x5D
#define hp_synctarg_6 0x5E
#define hp_synctarg_7 0x5F
#define hp_synctarg_0 0x60
#define hp_synctarg_1 0x61
#define hp_synctarg_2 0x62
#define hp_synctarg_3 0x63
#define NARROW_SCSI BIT(4)
#define DEFAULT_OFFSET 0x0F
#define hp_autostart_0 0x64
#define hp_autostart_1 0x65
#define hp_autostart_3 0x67
#define AUTO_IMMED BIT(5)
#define SELECT BIT(6)
#define END_DATA (BIT(7)+BIT(6))
#define hp_gp_reg_0 0x68
#define hp_gp_reg_1 0x69
#define hp_gp_reg_3 0x6B
#define hp_seltimeout 0x6C
#define TO_4ms 0x67 /* 3.9959ms */
#define TO_5ms 0x03 /* 4.9152ms */
#define TO_10ms 0x07 /* 11.xxxms */
#define TO_250ms 0x99 /* 250.68ms */
#define TO_290ms 0xB1 /* 289.99ms */
#define hp_clkctrl_0 0x6D
#define PWR_DWN BIT(6)
#define ACTdeassert BIT(4)
#define CLK_40MHZ (BIT(1) + BIT(0))
#define CLKCTRL_DEFAULT (ACTdeassert | CLK_40MHZ)
#define hp_fiforead 0x6E
#define hp_fifowrite 0x6F
#define hp_offsetctr 0x70
#define hp_xferstat 0x71
#define FIFO_EMPTY BIT(6)
#define hp_portctrl_1 0x72
#define CHK_SCSI_P BIT(3)
#define HOST_MODE8 BIT(0)
#define hp_xfer_pad 0x73
#define ID_UNLOCK BIT(3)
#define hp_scsidata_0 0x74
#define hp_scsidata_1 0x75
#define hp_aramBase 0x80
#define BIOS_DATA_OFFSET 0x60
#define BIOS_RELATIVE_CARD 0x64
#define AR3 (BIT(9) + BIT(8))
#define SDATA BIT(10)
#define CRD_OP BIT(11) /* Cmp Reg. w/ Data */
#define CRR_OP BIT(12) /* Cmp Reg. w. Reg. */
#define CPE_OP (BIT(14)+BIT(11)) /* Cmp SCSI phs & Branch EQ */
#define CPN_OP (BIT(14)+BIT(12)) /* Cmp SCSI phs & Branch NOT EQ */
#define ADATA_OUT 0x00
#define ADATA_IN BIT(8)
#define ACOMMAND BIT(10)
#define ASTATUS (BIT(10)+BIT(8))
#define AMSG_OUT (BIT(10)+BIT(9))
#define AMSG_IN (BIT(10)+BIT(9)+BIT(8))
#define BRH_OP BIT(13) /* Branch */
#define ALWAYS 0x00
#define EQUAL BIT(8)
#define NOT_EQ BIT(9)
#define TCB_OP (BIT(13)+BIT(11)) /* Test condition & branch */
#define FIFO_0 BIT(10)
#define MPM_OP BIT(15) /* Match phase and move data */
#define MRR_OP BIT(14) /* Move DReg. to Reg. */
#define S_IDREG (BIT(2)+BIT(1)+BIT(0))
#define D_AR0 0x00
#define D_AR1 BIT(0)
#define D_BUCKET (BIT(2) + BIT(1) + BIT(0))
#define RAT_OP (BIT(14)+BIT(13)+BIT(11))
#define SSI_OP (BIT(15)+BIT(11))
#define SSI_ITAR_DISC (ITAR_DISC >> 8)
#define SSI_IDO_STRT (IDO_STRT >> 8)
#define SSI_ICMD_COMP (ICMD_COMP >> 8)
#define SSI_ITICKLE (ITICKLE >> 8)
#define SSI_IUNKWN (IUNKWN >> 8)
#define SSI_INO_CC (IUNKWN >> 8)
#define SSI_IRFAIL (IUNKWN >> 8)
#define NP 0x10 /*Next Phase */
#define NTCMD 0x02 /*Non- Tagged Command start */
#define CMDPZ 0x04 /*Command phase */
#define DINT 0x12 /*Data Out/In interrupt */
#define DI 0x13 /*Data Out */
#define DC 0x19 /*Disconnect Message */
#define ST 0x1D /*Status Phase */
#define UNKNWN 0x24 /*Unknown bus action */
#define CC 0x25 /*Command Completion failure */
#define TICK 0x26 /*New target reselected us. */
#define SELCHK 0x28 /*Select & Check SCSI ID latch reg */
#define ID_MSG_STRT hp_aramBase + 0x00
#define NON_TAG_ID_MSG hp_aramBase + 0x06
#define CMD_STRT hp_aramBase + 0x08
#define SYNC_MSGS hp_aramBase + 0x08
#define TAG_STRT 0x00
#define DISCONNECT_START 0x10/2
#define END_DATA_START 0x14/2
#define CMD_ONLY_STRT CMDPZ/2
#define SELCHK_STRT SELCHK/2
#define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;}
/* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2), \
xfercnt <<= 16,\
xfercnt |= RDW_HARPOON((unsigned short)(port+hp_xfercnt_0)))
*/
#define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((port+hp_host_addr_lo), (unsigned short)(addr & 0x0000FFFFL)),\
addr >>= 16,\
WRW_HARPOON((port+hp_host_addr_hmi), (unsigned short)(addr & 0x0000FFFFL)),\
WR_HARP32(port,hp_xfercnt_0,count),\
WRW_HARPOON((port+hp_xfer_cnt_lo), (unsigned short)(count & 0x0000FFFFL)),\
count >>= 16,\
WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
#define ACCEPT_MSG(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
#define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
#define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),\
WR_HARPOON(port+hp_scsireset, 0x00))
#define ARAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
(RD_HARPOON(p_port+hp_page_ctrl) | SGRAM_ARAM)))
#define SGRAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
(RD_HARPOON(p_port+hp_page_ctrl) & ~SGRAM_ARAM)))
#define MDISABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
(RD_HARPOON(p_port+hp_page_ctrl) | G_INT_DISABLE)))
#define MENABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
(RD_HARPOON(p_port+hp_page_ctrl) & ~G_INT_DISABLE)))
static unsigned char FPT_sisyncn(unsigned long port, unsigned char p_card,
unsigned char syncFlag);
static void FPT_ssel(unsigned long port, unsigned char p_card);
static void FPT_sres(unsigned long port, unsigned char p_card,
struct sccb_card *pCurrCard);
static void FPT_shandem(unsigned long port, unsigned char p_card,
struct sccb *pCurrSCCB);
static void FPT_stsyncn(unsigned long port, unsigned char p_card);
static void FPT_sisyncr(unsigned long port, unsigned char sync_pulse,
unsigned char offset);
static void FPT_sssyncv(unsigned long p_port, unsigned char p_id,
unsigned char p_sync_value,
struct sccb_mgr_tar_info *currTar_Info);
static void FPT_sresb(unsigned long port, unsigned char p_card);
static void FPT_sxfrp(unsigned long p_port, unsigned char p_card);
static void FPT_schkdd(unsigned long port, unsigned char p_card);
static unsigned char FPT_RdStack(unsigned long port, unsigned char index);
static void FPT_WrStack(unsigned long portBase, unsigned char index,
unsigned char data);
static unsigned char FPT_ChkIfChipInitialized(unsigned long ioPort);
static void FPT_SendMsg(unsigned long port, unsigned char message);
static void FPT_queueFlushTargSccb(unsigned char p_card, unsigned char thisTarg,
unsigned char error_code);
static void FPT_sinits(struct sccb *p_sccb, unsigned char p_card);
static void FPT_RNVRamData(struct nvram_info *pNvRamInfo);
static unsigned char FPT_siwidn(unsigned long port, unsigned char p_card);
static void FPT_stwidn(unsigned long port, unsigned char p_card);
static void FPT_siwidr(unsigned long port, unsigned char width);
static void FPT_queueSelectFail(struct sccb_card *pCurrCard,
unsigned char p_card);
static void FPT_queueDisconnect(struct sccb *p_SCCB, unsigned char p_card);
static void FPT_queueCmdComplete(struct sccb_card *pCurrCard,
struct sccb *p_SCCB, unsigned char p_card);
static void FPT_queueSearchSelect(struct sccb_card *pCurrCard,
unsigned char p_card);
static void FPT_queueFlushSccb(unsigned char p_card, unsigned char error_code);
static void FPT_queueAddSccb(struct sccb *p_SCCB, unsigned char card);
static unsigned char FPT_queueFindSccb(struct sccb *p_SCCB,
unsigned char p_card);
static void FPT_utilUpdateResidual(struct sccb *p_SCCB);
static unsigned short FPT_CalcCrc16(unsigned char buffer[]);
static unsigned char FPT_CalcLrc(unsigned char buffer[]);
static void FPT_Wait1Second(unsigned long p_port);
static void FPT_Wait(unsigned long p_port, unsigned char p_delay);
static void FPT_utilEEWriteOnOff(unsigned long p_port, unsigned char p_mode);
static void FPT_utilEEWrite(unsigned long p_port, unsigned short ee_data,
unsigned short ee_addr);
static unsigned short FPT_utilEERead(unsigned long p_port,
unsigned short ee_addr);
static unsigned short FPT_utilEEReadOrg(unsigned long p_port,
unsigned short ee_addr);
static void FPT_utilEESendCmdAddr(unsigned long p_port, unsigned char ee_cmd,
unsigned short ee_addr);
static void FPT_phaseDataOut(unsigned long port, unsigned char p_card);
static void FPT_phaseDataIn(unsigned long port, unsigned char p_card);
static void FPT_phaseCommand(unsigned long port, unsigned char p_card);
static void FPT_phaseStatus(unsigned long port, unsigned char p_card);
static void FPT_phaseMsgOut(unsigned long port, unsigned char p_card);
static void FPT_phaseMsgIn(unsigned long port, unsigned char p_card);
static void FPT_phaseIllegal(unsigned long port, unsigned char p_card);
static void FPT_phaseDecode(unsigned long port, unsigned char p_card);
static void FPT_phaseChkFifo(unsigned long port, unsigned char p_card);
static void FPT_phaseBusFree(unsigned long p_port, unsigned char p_card);
static void FPT_XbowInit(unsigned long port, unsigned char scamFlg);
static void FPT_BusMasterInit(unsigned long p_port);
static void FPT_DiagEEPROM(unsigned long p_port);
static void FPT_dataXferProcessor(unsigned long port,
struct sccb_card *pCurrCard);
static void FPT_busMstrSGDataXferStart(unsigned long port,
struct sccb *pCurrSCCB);
static void FPT_busMstrDataXferStart(unsigned long port,
struct sccb *pCurrSCCB);
static void FPT_hostDataXferAbort(unsigned long port, unsigned char p_card,
struct sccb *pCurrSCCB);
static void FPT_hostDataXferRestart(struct sccb *currSCCB);
static unsigned char FPT_SccbMgr_bad_isr(unsigned long p_port,
unsigned char p_card,
struct sccb_card *pCurrCard,
unsigned short p_int);
static void FPT_SccbMgrTableInitAll(void);
static void FPT_SccbMgrTableInitCard(struct sccb_card *pCurrCard,
unsigned char p_card);
static void FPT_SccbMgrTableInitTarget(unsigned char p_card,
unsigned char target);
static void FPT_scini(unsigned char p_card, unsigned char p_our_id,
unsigned char p_power_up);
static int FPT_scarb(unsigned long p_port, unsigned char p_sel_type);
static void FPT_scbusf(unsigned long p_port);
static void FPT_scsel(unsigned long p_port);
static void FPT_scasid(unsigned char p_card, unsigned long p_port);
static unsigned char FPT_scxferc(unsigned long p_port, unsigned char p_data);
static unsigned char FPT_scsendi(unsigned long p_port,
unsigned char p_id_string[]);
static unsigned char FPT_sciso(unsigned long p_port,
unsigned char p_id_string[]);
static void FPT_scwirod(unsigned long p_port, unsigned char p_data_bit);
static void FPT_scwiros(unsigned long p_port, unsigned char p_data_bit);
static unsigned char FPT_scvalq(unsigned char p_quintet);
static unsigned char FPT_scsell(unsigned long p_port, unsigned char targ_id);
static void FPT_scwtsel(unsigned long p_port);
static void FPT_inisci(unsigned char p_card, unsigned long p_port,
unsigned char p_our_id);
static void FPT_scsavdi(unsigned char p_card, unsigned long p_port);
static unsigned char FPT_scmachid(unsigned char p_card,
unsigned char p_id_string[]);
static void FPT_autoCmdCmplt(unsigned long p_port, unsigned char p_card);
static void FPT_autoLoadDefaultMap(unsigned long p_port);
static struct sccb_mgr_tar_info FPT_sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR] =
{ {{0}} };
static struct sccb_card FPT_BL_Card[MAX_CARDS] = { {0} };
static SCCBSCAM_INFO FPT_scamInfo[MAX_SCSI_TAR] = { {{0}} };
static struct nvram_info FPT_nvRamInfo[MAX_MB_CARDS] = { {0} };
static unsigned char FPT_mbCards = 0;
static unsigned char FPT_scamHAString[] =
{ 0x63, 0x07, 'B', 'U', 'S', 'L', 'O', 'G', 'I', 'C',
' ', 'B', 'T', '-', '9', '3', '0',
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20
};
static unsigned short FPT_default_intena = 0;
static void (*FPT_s_PhaseTbl[8]) (unsigned long, unsigned char) = {
0};
/*---------------------------------------------------------------------
*
* Function: FlashPoint_ProbeHostAdapter
*
* Description: Setup and/or Search for cards and return info to caller.
*
*---------------------------------------------------------------------*/
static int FlashPoint_ProbeHostAdapter(struct sccb_mgr_info *pCardInfo)
{
static unsigned char first_time = 1;
unsigned char i, j, id, ScamFlg;
unsigned short temp, temp2, temp3, temp4, temp5, temp6;
unsigned long ioport;
struct nvram_info *pCurrNvRam;
ioport = pCardInfo->si_baseaddr;
if (RD_HARPOON(ioport + hp_vendor_id_0) != ORION_VEND_0)
return (int)FAILURE;
if ((RD_HARPOON(ioport + hp_vendor_id_1) != ORION_VEND_1))
return (int)FAILURE;
if ((RD_HARPOON(ioport + hp_device_id_0) != ORION_DEV_0))
return (int)FAILURE;
if ((RD_HARPOON(ioport + hp_device_id_1) != ORION_DEV_1))
return (int)FAILURE;
if (RD_HARPOON(ioport + hp_rev_num) != 0x0f) {
/* For new Harpoon then check for sub_device ID LSB
the bits(0-3) must be all ZERO for compatible with
current version of SCCBMgr, else skip this Harpoon
device. */
if (RD_HARPOON(ioport + hp_sub_device_id_0) & 0x0f)
return (int)FAILURE;
}
if (first_time) {
FPT_SccbMgrTableInitAll();
first_time = 0;
FPT_mbCards = 0;
}
if (FPT_RdStack(ioport, 0) != 0x00) {
if (FPT_ChkIfChipInitialized(ioport) == 0) {
pCurrNvRam = NULL;
WR_HARPOON(ioport + hp_semaphore, 0x00);
FPT_XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
FPT_DiagEEPROM(ioport);
} else {
if (FPT_mbCards < MAX_MB_CARDS) {
pCurrNvRam = &FPT_nvRamInfo[FPT_mbCards];
FPT_mbCards++;
pCurrNvRam->niBaseAddr = ioport;
FPT_RNVRamData(pCurrNvRam);
} else
return (int)FAILURE;
}
} else
pCurrNvRam = NULL;
WR_HARPOON(ioport + hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(ioport + hp_sys_ctrl, 0x00);
if (pCurrNvRam)
pCardInfo->si_id = pCurrNvRam->niAdapId;
else
pCardInfo->si_id =
(unsigned
char)(FPT_utilEERead(ioport,
(ADAPTER_SCSI_ID /
2)) & (unsigned char)0x0FF);
pCardInfo->si_lun = 0x00;
pCardInfo->si_fw_revision = ORION_FW_REV;
temp2 = 0x0000;
temp3 = 0x0000;
temp4 = 0x0000;
temp5 = 0x0000;
temp6 = 0x0000;
for (id = 0; id < (16 / 2); id++) {
if (pCurrNvRam) {
temp = (unsigned short)pCurrNvRam->niSyncTbl[id];
temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
(((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
} else
temp =
FPT_utilEERead(ioport,
(unsigned short)((SYNC_RATE_TBL / 2)
+ id));
for (i = 0; i < 2; temp >>= 8, i++) {
temp2 >>= 1;
temp3 >>= 1;
temp4 >>= 1;
temp5 >>= 1;
temp6 >>= 1;
switch (temp & 0x3) {
case AUTO_RATE_20: /* Synchronous, 20 mega-transfers/second */
temp6 |= 0x8000; /* Fall through */
case AUTO_RATE_10: /* Synchronous, 10 mega-transfers/second */
temp5 |= 0x8000; /* Fall through */
case AUTO_RATE_05: /* Synchronous, 5 mega-transfers/second */
temp2 |= 0x8000; /* Fall through */
case AUTO_RATE_00: /* Asynchronous */
break;
}
if (temp & DISC_ENABLE_BIT)
temp3 |= 0x8000;
if (temp & WIDE_NEGO_BIT)
temp4 |= 0x8000;
}
}
pCardInfo->si_per_targ_init_sync = temp2;
pCardInfo->si_per_targ_no_disc = temp3;
pCardInfo->si_per_targ_wide_nego = temp4;
pCardInfo->si_per_targ_fast_nego = temp5;
pCardInfo->si_per_targ_ultra_nego = temp6;
if (pCurrNvRam)
i = pCurrNvRam->niSysConf;
else
i = (unsigned
char)(FPT_utilEERead(ioport, (SYSTEM_CONFIG / 2)));
if (pCurrNvRam)
ScamFlg = pCurrNvRam->niScamConf;
else
ScamFlg =
(unsigned char)FPT_utilEERead(ioport, SCAM_CONFIG / 2);
pCardInfo->si_flags = 0x0000;
if (i & 0x01)
pCardInfo->si_flags |= SCSI_PARITY_ENA;
if (!(i & 0x02))
pCardInfo->si_flags |= SOFT_RESET;
if (i & 0x10)
pCardInfo->si_flags |= EXTENDED_TRANSLATION;
if (ScamFlg & SCAM_ENABLED)
pCardInfo->si_flags |= FLAG_SCAM_ENABLED;
if (ScamFlg & SCAM_LEVEL2)
pCardInfo->si_flags |= FLAG_SCAM_LEVEL2;
j = (RD_HARPOON(ioport + hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
if (i & 0x04) {
j |= SCSI_TERM_ENA_L;
}
WR_HARPOON(ioport + hp_bm_ctrl, j);
j = (RD_HARPOON(ioport + hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
if (i & 0x08) {
j |= SCSI_TERM_ENA_H;
}
WR_HARPOON(ioport + hp_ee_ctrl, j);
if (!(RD_HARPOON(ioport + hp_page_ctrl) & NARROW_SCSI_CARD))
pCardInfo->si_flags |= SUPPORT_16TAR_32LUN;
pCardInfo->si_card_family = HARPOON_FAMILY;
pCardInfo->si_bustype = BUSTYPE_PCI;
if (pCurrNvRam) {
pCardInfo->si_card_model[0] = '9';
switch (pCurrNvRam->niModel & 0x0f) {
case MODEL_LT:
pCardInfo->si_card_model[1] = '3';
pCardInfo->si_card_model[2] = '0';
break;
case MODEL_LW:
pCardInfo->si_card_model[1] = '5';
pCardInfo->si_card_model[2] = '0';
break;
case MODEL_DL:
pCardInfo->si_card_model[1] = '3';
pCardInfo->si_card_model[2] = '2';
break;
case MODEL_DW:
pCardInfo->si_card_model[1] = '5';
pCardInfo->si_card_model[2] = '2';
break;
}
} else {
temp = FPT_utilEERead(ioport, (MODEL_NUMB_0 / 2));
pCardInfo->si_card_model[0] = (unsigned char)(temp >> 8);
temp = FPT_utilEERead(ioport, (MODEL_NUMB_2 / 2));
pCardInfo->si_card_model[1] = (unsigned char)(temp & 0x00FF);
pCardInfo->si_card_model[2] = (unsigned char)(temp >> 8);
}
if (pCardInfo->si_card_model[1] == '3') {
if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7))
pCardInfo->si_flags |= LOW_BYTE_TERM;
} else if (pCardInfo->si_card_model[2] == '0') {
temp = RD_HARPOON(ioport + hp_xfer_pad);
WR_HARPOON(ioport + hp_xfer_pad, (temp & ~BIT(4)));
if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7))
pCardInfo->si_flags |= LOW_BYTE_TERM;
WR_HARPOON(ioport + hp_xfer_pad, (temp | BIT(4)));
if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7))
pCardInfo->si_flags |= HIGH_BYTE_TERM;
WR_HARPOON(ioport + hp_xfer_pad, temp);
} else {
temp = RD_HARPOON(ioport + hp_ee_ctrl);
temp2 = RD_HARPOON(ioport + hp_xfer_pad);
WR_HARPOON(ioport + hp_ee_ctrl, (temp | SEE_CS));
WR_HARPOON(ioport + hp_xfer_pad, (temp2 | BIT(4)));
temp3 = 0;
for (i = 0; i < 8; i++) {
temp3 <<= 1;
if (!(RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)))
temp3 |= 1;
WR_HARPOON(ioport + hp_xfer_pad, (temp2 & ~BIT(4)));
WR_HARPOON(ioport + hp_xfer_pad, (temp2 | BIT(4)));
}
WR_HARPOON(ioport + hp_ee_ctrl, temp);
WR_HARPOON(ioport + hp_xfer_pad, temp2);
if (!(temp3 & BIT(7)))
pCardInfo->si_flags |= LOW_BYTE_TERM;
if (!(temp3 & BIT(6)))
pCardInfo->si_flags |= HIGH_BYTE_TERM;
}
ARAM_ACCESS(ioport);
for (i = 0; i < 4; i++) {
pCardInfo->si_XlatInfo[i] =
RD_HARPOON(ioport + hp_aramBase + BIOS_DATA_OFFSET + i);
}
/* return with -1 if no sort, else return with
logical card number sorted by BIOS (zero-based) */
pCardInfo->si_relative_cardnum =
(unsigned
char)(RD_HARPOON(ioport + hp_aramBase + BIOS_RELATIVE_CARD) - 1);
SGRAM_ACCESS(ioport);
FPT_s_PhaseTbl[0] = FPT_phaseDataOut;
FPT_s_PhaseTbl[1] = FPT_phaseDataIn;
FPT_s_PhaseTbl[2] = FPT_phaseIllegal;
FPT_s_PhaseTbl[3] = FPT_phaseIllegal;
FPT_s_PhaseTbl[4] = FPT_phaseCommand;
FPT_s_PhaseTbl[5] = FPT_phaseStatus;
FPT_s_PhaseTbl[6] = FPT_phaseMsgOut;
FPT_s_PhaseTbl[7] = FPT_phaseMsgIn;
pCardInfo->si_present = 0x01;
return 0;
}
/*---------------------------------------------------------------------
*
* Function: FlashPoint_HardwareResetHostAdapter
*
* Description: Setup adapter for normal operation (hard reset).
*
*---------------------------------------------------------------------*/
static unsigned long FlashPoint_HardwareResetHostAdapter(struct sccb_mgr_info
*pCardInfo)
{
struct sccb_card *CurrCard = NULL;
struct nvram_info *pCurrNvRam;
unsigned char i, j, thisCard, ScamFlg;
unsigned short temp, sync_bit_map, id;
unsigned long ioport;
ioport = pCardInfo->si_baseaddr;
for (thisCard = 0; thisCard <= MAX_CARDS; thisCard++) {
if (thisCard == MAX_CARDS) {
return FAILURE;
}
if (FPT_BL_Card[thisCard].ioPort == ioport) {
CurrCard = &FPT_BL_Card[thisCard];
FPT_SccbMgrTableInitCard(CurrCard, thisCard);
break;
}
else if (FPT_BL_Card[thisCard].ioPort == 0x00) {
FPT_BL_Card[thisCard].ioPort = ioport;
CurrCard = &FPT_BL_Card[thisCard];
if (FPT_mbCards)
for (i = 0; i < FPT_mbCards; i++) {
if (CurrCard->ioPort ==
FPT_nvRamInfo[i].niBaseAddr)
CurrCard->pNvRamInfo =
&FPT_nvRamInfo[i];
}
FPT_SccbMgrTableInitCard(CurrCard, thisCard);
CurrCard->cardIndex = thisCard;
CurrCard->cardInfo = pCardInfo;
break;
}
}
pCurrNvRam = CurrCard->pNvRamInfo;
if (pCurrNvRam) {
ScamFlg = pCurrNvRam->niScamConf;
} else {
ScamFlg =
(unsigned char)FPT_utilEERead(ioport, SCAM_CONFIG / 2);
}
FPT_BusMasterInit(ioport);
FPT_XbowInit(ioport, ScamFlg);
FPT_autoLoadDefaultMap(ioport);
for (i = 0, id = 0x01; i != pCardInfo->si_id; i++, id <<= 1) {
}
WR_HARPOON(ioport + hp_selfid_0, id);
WR_HARPOON(ioport + hp_selfid_1, 0x00);
WR_HARPOON(ioport + hp_arb_id, pCardInfo->si_id);
CurrCard->ourId = pCardInfo->si_id;
i = (unsigned char)pCardInfo->si_flags;
if (i & SCSI_PARITY_ENA)
WR_HARPOON(ioport + hp_portctrl_1, (HOST_MODE8 | CHK_SCSI_P));
j = (RD_HARPOON(ioport + hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
if (i & LOW_BYTE_TERM)
j |= SCSI_TERM_ENA_L;
WR_HARPOON(ioport + hp_bm_ctrl, j);
j = (RD_HARPOON(ioport + hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
if (i & HIGH_BYTE_TERM)
j |= SCSI_TERM_ENA_H;
WR_HARPOON(ioport + hp_ee_ctrl, j);
if (!(pCardInfo->si_flags & SOFT_RESET)) {
FPT_sresb(ioport, thisCard);
FPT_scini(thisCard, pCardInfo->si_id, 0);
}
if (pCardInfo->si_flags & POST_ALL_UNDERRRUNS)
CurrCard->globalFlags |= F_NO_FILTER;
if (pCurrNvRam) {
if (pCurrNvRam->niSysConf & 0x10)
CurrCard->globalFlags |= F_GREEN_PC;
} else {
if (FPT_utilEERead(ioport, (SYSTEM_CONFIG / 2)) & GREEN_PC_ENA)
CurrCard->globalFlags |= F_GREEN_PC;
}
/* Set global flag to indicate Re-Negotiation to be done on all
ckeck condition */
if (pCurrNvRam) {
if (pCurrNvRam->niScsiConf & 0x04)
CurrCard->globalFlags |= F_DO_RENEGO;
} else {
if (FPT_utilEERead(ioport, (SCSI_CONFIG / 2)) & RENEGO_ENA)
CurrCard->globalFlags |= F_DO_RENEGO;
}
if (pCurrNvRam) {
if (pCurrNvRam->niScsiConf & 0x08)
CurrCard->globalFlags |= F_CONLUN_IO;
} else {
if (FPT_utilEERead(ioport, (SCSI_CONFIG / 2)) & CONNIO_ENA)
CurrCard->globalFlags |= F_CONLUN_IO;
}
temp = pCardInfo->si_per_targ_no_disc;
for (i = 0, id = 1; i < MAX_SCSI_TAR; i++, id <<= 1) {
if (temp & id)
FPT_sccbMgrTbl[thisCard][i].TarStatus |= TAR_ALLOW_DISC;
}
sync_bit_map = 0x0001;
for (id = 0; id < (MAX_SCSI_TAR / 2); id++) {
if (pCurrNvRam) {
temp = (unsigned short)pCurrNvRam->niSyncTbl[id];
temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
(((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
} else
temp =
FPT_utilEERead(ioport,
(unsigned short)((SYNC_RATE_TBL / 2)
+ id));
for (i = 0; i < 2; temp >>= 8, i++) {
if (pCardInfo->si_per_targ_init_sync & sync_bit_map) {
FPT_sccbMgrTbl[thisCard][id * 2 +
i].TarEEValue =
(unsigned char)temp;
}
else {
FPT_sccbMgrTbl[thisCard][id * 2 +
i].TarStatus |=
SYNC_SUPPORTED;
FPT_sccbMgrTbl[thisCard][id * 2 +
i].TarEEValue =
(unsigned char)(temp & ~EE_SYNC_MASK);
}
/* if ((pCardInfo->si_per_targ_wide_nego & sync_bit_map) ||
(id*2+i >= 8)){
*/
if (pCardInfo->si_per_targ_wide_nego & sync_bit_map) {
FPT_sccbMgrTbl[thisCard][id * 2 +
i].TarEEValue |=
EE_WIDE_SCSI;
}
else { /* NARROW SCSI */
FPT_sccbMgrTbl[thisCard][id * 2 +
i].TarStatus |=
WIDE_NEGOCIATED;
}
sync_bit_map <<= 1;
}
}
WR_HARPOON((ioport + hp_semaphore),
(unsigned char)(RD_HARPOON((ioport + hp_semaphore)) |
SCCB_MGR_PRESENT));
return (unsigned long)CurrCard;
}
static void FlashPoint_ReleaseHostAdapter(unsigned long pCurrCard)
{
unsigned char i;
unsigned long portBase;
unsigned long regOffset;
unsigned long scamData;
unsigned long *pScamTbl;
struct nvram_info *pCurrNvRam;
pCurrNvRam = ((struct sccb_card *)pCurrCard)->pNvRamInfo;
if (pCurrNvRam) {
FPT_WrStack(pCurrNvRam->niBaseAddr, 0, pCurrNvRam->niModel);
FPT_WrStack(pCurrNvRam->niBaseAddr, 1, pCurrNvRam->niSysConf);
FPT_WrStack(pCurrNvRam->niBaseAddr, 2, pCurrNvRam->niScsiConf);
FPT_WrStack(pCurrNvRam->niBaseAddr, 3, pCurrNvRam->niScamConf);
FPT_WrStack(pCurrNvRam->niBaseAddr, 4, pCurrNvRam->niAdapId);
for (i = 0; i < MAX_SCSI_TAR / 2; i++)
FPT_WrStack(pCurrNvRam->niBaseAddr,
(unsigned char)(i + 5),
pCurrNvRam->niSyncTbl[i]);
portBase = pCurrNvRam->niBaseAddr;
for (i = 0; i < MAX_SCSI_TAR; i++) {
regOffset = hp_aramBase + 64 + i * 4;
pScamTbl = (unsigned long *)&pCurrNvRam->niScamTbl[i];
scamData = *pScamTbl;
WR_HARP32(portBase, regOffset, scamData);
}
} else {
FPT_WrStack(((struct sccb_card *)pCurrCard)->ioPort, 0, 0);
}
}
static void FPT_RNVRamData(struct nvram_info *pNvRamInfo)
{
unsigned char i;
unsigned long portBase;
unsigned long regOffset;
unsigned long scamData;
unsigned long *pScamTbl;
pNvRamInfo->niModel = FPT_RdStack(pNvRamInfo->niBaseAddr, 0);
pNvRamInfo->niSysConf = FPT_RdStack(pNvRamInfo->niBaseAddr, 1);
pNvRamInfo->niScsiConf = FPT_RdStack(pNvRamInfo->niBaseAddr, 2);
pNvRamInfo->niScamConf = FPT_RdStack(pNvRamInfo->niBaseAddr, 3);
pNvRamInfo->niAdapId = FPT_RdStack(pNvRamInfo->niBaseAddr, 4);
for (i = 0; i < MAX_SCSI_TAR / 2; i++)
pNvRamInfo->niSyncTbl[i] =
FPT_RdStack(pNvRamInfo->niBaseAddr, (unsigned char)(i + 5));
portBase = pNvRamInfo->niBaseAddr;
for (i = 0; i < MAX_SCSI_TAR; i++) {
regOffset = hp_aramBase + 64 + i * 4;
RD_HARP32(portBase, regOffset, scamData);
pScamTbl = (unsigned long *)&pNvRamInfo->niScamTbl[i];
*pScamTbl = scamData;
}
}
static unsigned char FPT_RdStack(unsigned long portBase, unsigned char index)
{
WR_HARPOON(portBase + hp_stack_addr, index);
return RD_HARPOON(portBase + hp_stack_data);
}
static void FPT_WrStack(unsigned long portBase, unsigned char index,
unsigned char data)
{
WR_HARPOON(portBase + hp_stack_addr, index);
WR_HARPOON(portBase + hp_stack_data, data);
}
static unsigned char FPT_ChkIfChipInitialized(unsigned long ioPort)
{
if ((RD_HARPOON(ioPort + hp_arb_id) & 0x0f) != FPT_RdStack(ioPort, 4))
return 0;
if ((RD_HARPOON(ioPort + hp_clkctrl_0) & CLKCTRL_DEFAULT)
!= CLKCTRL_DEFAULT)
return 0;
if ((RD_HARPOON(ioPort + hp_seltimeout) == TO_250ms) ||
(RD_HARPOON(ioPort + hp_seltimeout) == TO_290ms))
return 1;
return 0;
}
/*---------------------------------------------------------------------
*
* Function: FlashPoint_StartCCB
*
* Description: Start a command pointed to by p_Sccb. When the
* command is completed it will be returned via the
* callback function.
*
*---------------------------------------------------------------------*/
static void FlashPoint_StartCCB(unsigned long pCurrCard, struct sccb *p_Sccb)
{
unsigned long ioport;
unsigned char thisCard, lun;
struct sccb *pSaveSccb;
CALL_BK_FN callback;
thisCard = ((struct sccb_card *)pCurrCard)->cardIndex;
ioport = ((struct sccb_card *)pCurrCard)->ioPort;
if ((p_Sccb->TargID >= MAX_SCSI_TAR) || (p_Sccb->Lun >= MAX_LUN)) {
p_Sccb->HostStatus = SCCB_COMPLETE;
p_Sccb->SccbStatus = SCCB_ERROR;
callback = (CALL_BK_FN) p_Sccb->SccbCallback;
if (callback)
callback(p_Sccb);
return;
}
FPT_sinits(p_Sccb, thisCard);
if (!((struct sccb_card *)pCurrCard)->cmdCounter) {
WR_HARPOON(ioport + hp_semaphore,
(RD_HARPOON(ioport + hp_semaphore)
| SCCB_MGR_ACTIVE));
if (((struct sccb_card *)pCurrCard)->globalFlags & F_GREEN_PC) {
WR_HARPOON(ioport + hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(ioport + hp_sys_ctrl, 0x00);
}
}
((struct sccb_card *)pCurrCard)->cmdCounter++;
if (RD_HARPOON(ioport + hp_semaphore) & BIOS_IN_USE) {
WR_HARPOON(ioport + hp_semaphore,
(RD_HARPOON(ioport + hp_semaphore)
| TICKLE_ME));
if (p_Sccb->OperationCode == RESET_COMMAND) {
pSaveSccb =
((struct sccb_card *)pCurrCard)->currentSCCB;
((struct sccb_card *)pCurrCard)->currentSCCB = p_Sccb;
FPT_queueSelectFail(&FPT_BL_Card[thisCard], thisCard);
((struct sccb_card *)pCurrCard)->currentSCCB =
pSaveSccb;
} else {
FPT_queueAddSccb(p_Sccb, thisCard);
}
}
else if ((RD_HARPOON(ioport + hp_page_ctrl) & G_INT_DISABLE)) {
if (p_Sccb->OperationCode == RESET_COMMAND) {
pSaveSccb =
((struct sccb_card *)pCurrCard)->currentSCCB;
((struct sccb_card *)pCurrCard)->currentSCCB = p_Sccb;
FPT_queueSelectFail(&FPT_BL_Card[thisCard], thisCard);
((struct sccb_card *)pCurrCard)->currentSCCB =
pSaveSccb;
} else {
FPT_queueAddSccb(p_Sccb, thisCard);
}
}
else {
MDISABLE_INT(ioport);
if ((((struct sccb_card *)pCurrCard)->globalFlags & F_CONLUN_IO)
&&
((FPT_sccbMgrTbl[thisCard][p_Sccb->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
lun = p_Sccb->Lun;
else
lun = 0;
if ((((struct sccb_card *)pCurrCard)->currentSCCB == NULL) &&
(FPT_sccbMgrTbl[thisCard][p_Sccb->TargID].TarSelQ_Cnt == 0)
&& (FPT_sccbMgrTbl[thisCard][p_Sccb->TargID].TarLUNBusy[lun]
== 0)) {
((struct sccb_card *)pCurrCard)->currentSCCB = p_Sccb;
FPT_ssel(p_Sccb->SccbIOPort, thisCard);
}
else {
if (p_Sccb->OperationCode == RESET_COMMAND) {
pSaveSccb =
((struct sccb_card *)pCurrCard)->
currentSCCB;
((struct sccb_card *)pCurrCard)->currentSCCB =
p_Sccb;
FPT_queueSelectFail(&FPT_BL_Card[thisCard],
thisCard);
((struct sccb_card *)pCurrCard)->currentSCCB =
pSaveSccb;
} else {
FPT_queueAddSccb(p_Sccb, thisCard);
}
}
MENABLE_INT(ioport);
}
}
/*---------------------------------------------------------------------
*
* Function: FlashPoint_AbortCCB
*
* Description: Abort the command pointed to by p_Sccb. When the
* command is completed it will be returned via the
* callback function.
*
*---------------------------------------------------------------------*/
static int FlashPoint_AbortCCB(unsigned long pCurrCard, struct sccb *p_Sccb)
{
unsigned long ioport;
unsigned char thisCard;
CALL_BK_FN callback;
unsigned char TID;
struct sccb *pSaveSCCB;
struct sccb_mgr_tar_info *currTar_Info;
ioport = ((struct sccb_card *)pCurrCard)->ioPort;
thisCard = ((struct sccb_card *)pCurrCard)->cardIndex;
if (!(RD_HARPOON(ioport + hp_page_ctrl) & G_INT_DISABLE)) {
if (FPT_queueFindSccb(p_Sccb, thisCard)) {
((struct sccb_card *)pCurrCard)->cmdCounter--;
if (!((struct sccb_card *)pCurrCard)->cmdCounter)
WR_HARPOON(ioport + hp_semaphore,
(RD_HARPOON(ioport + hp_semaphore)
& (unsigned
char)(~(SCCB_MGR_ACTIVE |
TICKLE_ME))));
p_Sccb->SccbStatus = SCCB_ABORT;
callback = p_Sccb->SccbCallback;
callback(p_Sccb);
return 0;
}
else {
if (((struct sccb_card *)pCurrCard)->currentSCCB ==
p_Sccb) {
p_Sccb->SccbStatus = SCCB_ABORT;
return 0;
}
else {
TID = p_Sccb->TargID;
if (p_Sccb->Sccb_tag) {
MDISABLE_INT(ioport);
if (((struct sccb_card *)pCurrCard)->
discQ_Tbl[p_Sccb->Sccb_tag] ==
p_Sccb) {
p_Sccb->SccbStatus = SCCB_ABORT;
p_Sccb->Sccb_scsistat =
ABORT_ST;
p_Sccb->Sccb_scsimsg =
SMABORT_TAG;
if (((struct sccb_card *)
pCurrCard)->currentSCCB ==
NULL) {
((struct sccb_card *)
pCurrCard)->
currentSCCB = p_Sccb;
FPT_ssel(ioport,
thisCard);
} else {
pSaveSCCB =
((struct sccb_card
*)pCurrCard)->
currentSCCB;
((struct sccb_card *)
pCurrCard)->
currentSCCB = p_Sccb;
FPT_queueSelectFail((struct sccb_card *)pCurrCard, thisCard);
((struct sccb_card *)
pCurrCard)->
currentSCCB = pSaveSCCB;
}
}
MENABLE_INT(ioport);
return 0;
} else {
currTar_Info =
&FPT_sccbMgrTbl[thisCard][p_Sccb->
TargID];
if (FPT_BL_Card[thisCard].
discQ_Tbl[currTar_Info->
LunDiscQ_Idx[p_Sccb->Lun]]
== p_Sccb) {
p_Sccb->SccbStatus = SCCB_ABORT;
return 0;
}
}
}
}
}
return -1;
}
/*---------------------------------------------------------------------
*
* Function: FlashPoint_InterruptPending
*
* Description: Do a quick check to determine if there is a pending
* interrupt for this card and disable the IRQ Pin if so.
*
*---------------------------------------------------------------------*/
static unsigned char FlashPoint_InterruptPending(unsigned long pCurrCard)
{
unsigned long ioport;
ioport = ((struct sccb_card *)pCurrCard)->ioPort;
if (RD_HARPOON(ioport + hp_int_status) & INT_ASSERTED) {
return 1;
}
else
return 0;
}
/*---------------------------------------------------------------------
*
* Function: FlashPoint_HandleInterrupt
*
* Description: This is our entry point when an interrupt is generated
* by the card and the upper level driver passes it on to
* us.
*
*---------------------------------------------------------------------*/
static int FlashPoint_HandleInterrupt(unsigned long pCurrCard)
{
struct sccb *currSCCB;
unsigned char thisCard, result, bm_status, bm_int_st;
unsigned short hp_int;
unsigned char i, target;
unsigned long ioport;
thisCard = ((struct sccb_card *)pCurrCard)->cardIndex;
ioport = ((struct sccb_card *)pCurrCard)->ioPort;
MDISABLE_INT(ioport);
if ((bm_int_st = RD_HARPOON(ioport + hp_int_status)) & EXT_STATUS_ON)
bm_status =
RD_HARPOON(ioport +
hp_ext_status) & (unsigned char)BAD_EXT_STATUS;
else
bm_status = 0;
WR_HARPOON(ioport + hp_int_mask, (INT_CMD_COMPL | SCSI_INTERRUPT));
while ((hp_int =
RDW_HARPOON((ioport +
hp_intstat)) & FPT_default_intena) | bm_status) {
currSCCB = ((struct sccb_card *)pCurrCard)->currentSCCB;
if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) {
result =
FPT_SccbMgr_bad_isr(ioport, thisCard,
((struct sccb_card *)pCurrCard),
hp_int);
WRW_HARPOON((ioport + hp_intstat),
(FIFO | TIMEOUT | RESET | SCAM_SEL));
bm_status = 0;
if (result) {
MENABLE_INT(ioport);
return result;
}
}
else if (hp_int & ICMD_COMP) {
if (!(hp_int & BUS_FREE)) {
/* Wait for the BusFree before starting a new command. We
must also check for being reselected since the BusFree
may not show up if another device reselects us in 1.5us or
less. SRR Wednesday, 3/8/1995.
*/
while (!
(RDW_HARPOON((ioport + hp_intstat)) &
(BUS_FREE | RSEL))) ;
}
if (((struct sccb_card *)pCurrCard)->
globalFlags & F_HOST_XFER_ACT)
FPT_phaseChkFifo(ioport, thisCard);
/* WRW_HARPOON((ioport+hp_intstat),
(BUS_FREE | ICMD_COMP | ITAR_DISC | XFER_CNT_0));
*/
WRW_HARPOON((ioport + hp_intstat), CLR_ALL_INT_1);
FPT_autoCmdCmplt(ioport, thisCard);
}
else if (hp_int & ITAR_DISC) {
if (((struct sccb_card *)pCurrCard)->
globalFlags & F_HOST_XFER_ACT) {
FPT_phaseChkFifo(ioport, thisCard);
}
if (RD_HARPOON(ioport + hp_gp_reg_1) == SMSAVE_DATA_PTR) {
WR_HARPOON(ioport + hp_gp_reg_1, 0x00);
currSCCB->Sccb_XferState |= F_NO_DATA_YET;
currSCCB->Sccb_savedATC = currSCCB->Sccb_ATC;
}
currSCCB->Sccb_scsistat = DISCONNECT_ST;
FPT_queueDisconnect(currSCCB, thisCard);
/* Wait for the BusFree before starting a new command. We
must also check for being reselected since the BusFree
may not show up if another device reselects us in 1.5us or
less. SRR Wednesday, 3/8/1995.
*/
while (!
(RDW_HARPOON((ioport + hp_intstat)) &
(BUS_FREE | RSEL))
&& !((RDW_HARPOON((ioport + hp_intstat)) & PHASE)
&& RD_HARPOON((ioport + hp_scsisig)) ==
(SCSI_BSY | SCSI_REQ | SCSI_CD | SCSI_MSG |
SCSI_IOBIT))) ;
/*
The additional loop exit condition above detects a timing problem
with the revision D/E harpoon chips. The caller should reset the
host adapter to recover when 0xFE is returned.
*/
if (!
(RDW_HARPOON((ioport + hp_intstat)) &
(BUS_FREE | RSEL))) {
MENABLE_INT(ioport);
return 0xFE;
}
WRW_HARPOON((ioport + hp_intstat),
(BUS_FREE | ITAR_DISC));
((struct sccb_card *)pCurrCard)->globalFlags |=
F_NEW_SCCB_CMD;
}
else if (hp_int & RSEL) {
WRW_HARPOON((ioport + hp_intstat),
(PROG_HLT | RSEL | PHASE | BUS_FREE));
if (RDW_HARPOON((ioport + hp_intstat)) & ITAR_DISC) {
if (((struct sccb_card *)pCurrCard)->
globalFlags & F_HOST_XFER_ACT) {
FPT_phaseChkFifo(ioport, thisCard);
}
if (RD_HARPOON(ioport + hp_gp_reg_1) ==
SMSAVE_DATA_PTR) {
WR_HARPOON(ioport + hp_gp_reg_1, 0x00);
currSCCB->Sccb_XferState |=
F_NO_DATA_YET;
currSCCB->Sccb_savedATC =
currSCCB->Sccb_ATC;
}
WRW_HARPOON((ioport + hp_intstat),
(BUS_FREE | ITAR_DISC));
currSCCB->Sccb_scsistat = DISCONNECT_ST;
FPT_queueDisconnect(currSCCB, thisCard);
}
FPT_sres(ioport, thisCard,
((struct sccb_card *)pCurrCard));
FPT_phaseDecode(ioport, thisCard);
}
else if ((hp_int & IDO_STRT) && (!(hp_int & BUS_FREE))) {
WRW_HARPOON((ioport + hp_intstat),
(IDO_STRT | XFER_CNT_0));
FPT_phaseDecode(ioport, thisCard);
}
else if ((hp_int & IUNKWN) || (hp_int & PROG_HLT)) {
WRW_HARPOON((ioport + hp_intstat),
(PHASE | IUNKWN | PROG_HLT));
if ((RD_HARPOON(ioport + hp_prgmcnt_0) & (unsigned char)
0x3f) < (unsigned char)SELCHK) {
FPT_phaseDecode(ioport, thisCard);
} else {
/* Harpoon problem some SCSI target device respond to selection
with short BUSY pulse (<400ns) this will make the Harpoon is not able
to latch the correct Target ID into reg. x53.
The work around require to correct this reg. But when write to this
reg. (0x53) also increment the FIFO write addr reg (0x6f), thus we
need to read this reg first then restore it later. After update to 0x53 */
i = (unsigned
char)(RD_HARPOON(ioport + hp_fifowrite));
target =
(unsigned
char)(RD_HARPOON(ioport + hp_gp_reg_3));
WR_HARPOON(ioport + hp_xfer_pad,
(unsigned char)ID_UNLOCK);
WR_HARPOON(ioport + hp_select_id,
(unsigned char)(target | target <<
4));
WR_HARPOON(ioport + hp_xfer_pad,
(unsigned char)0x00);
WR_HARPOON(ioport + hp_fifowrite, i);
WR_HARPOON(ioport + hp_autostart_3,
(AUTO_IMMED + TAG_STRT));
}
}
else if (hp_int & XFER_CNT_0) {
WRW_HARPOON((ioport + hp_intstat), XFER_CNT_0);
FPT_schkdd(ioport, thisCard);
}
else if (hp_int & BUS_FREE) {
WRW_HARPOON((ioport + hp_intstat), BUS_FREE);
if (((struct sccb_card *)pCurrCard)->
globalFlags & F_HOST_XFER_ACT) {
FPT_hostDataXferAbort(ioport, thisCard,
currSCCB);
}
FPT_phaseBusFree(ioport, thisCard);
}
else if (hp_int & ITICKLE) {
WRW_HARPOON((ioport + hp_intstat), ITICKLE);
((struct sccb_card *)pCurrCard)->globalFlags |=
F_NEW_SCCB_CMD;
}
if (((struct sccb_card *)pCurrCard)->
globalFlags & F_NEW_SCCB_CMD) {
((struct sccb_card *)pCurrCard)->globalFlags &=
~F_NEW_SCCB_CMD;
if (((struct sccb_card *)pCurrCard)->currentSCCB ==
NULL) {
FPT_queueSearchSelect(((struct sccb_card *)
pCurrCard), thisCard);
}
if (((struct sccb_card *)pCurrCard)->currentSCCB !=
NULL) {
((struct sccb_card *)pCurrCard)->globalFlags &=
~F_NEW_SCCB_CMD;
FPT_ssel(ioport, thisCard);
}
break;
}
} /*end while */
MENABLE_INT(ioport);
return 0;
}
/*---------------------------------------------------------------------
*
* Function: Sccb_bad_isr
*
* Description: Some type of interrupt has occurred which is slightly
* out of the ordinary. We will now decode it fully, in
* this routine. This is broken up in an attempt to save
* processing time.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_SccbMgr_bad_isr(unsigned long p_port,
unsigned char p_card,
struct sccb_card *pCurrCard,
unsigned short p_int)
{
unsigned char temp, ScamFlg;
struct sccb_mgr_tar_info *currTar_Info;
struct nvram_info *pCurrNvRam;
if (RD_HARPOON(p_port + hp_ext_status) &
(BM_FORCE_OFF | PCI_DEV_TMOUT | BM_PARITY_ERR | PIO_OVERRUN)) {
if (pCurrCard->globalFlags & F_HOST_XFER_ACT) {
FPT_hostDataXferAbort(p_port, p_card,
pCurrCard->currentSCCB);
}
if (RD_HARPOON(p_port + hp_pci_stat_cfg) & REC_MASTER_ABORT)
{
WR_HARPOON(p_port + hp_pci_stat_cfg,
(RD_HARPOON(p_port + hp_pci_stat_cfg) &
~REC_MASTER_ABORT));
WR_HARPOON(p_port + hp_host_blk_cnt, 0x00);
}
if (pCurrCard->currentSCCB != NULL) {
if (!pCurrCard->currentSCCB->HostStatus)
pCurrCard->currentSCCB->HostStatus =
SCCB_BM_ERR;
FPT_sxfrp(p_port, p_card);
temp = (unsigned char)(RD_HARPOON(p_port + hp_ee_ctrl) &
(EXT_ARB_ACK | SCSI_TERM_ENA_H));
WR_HARPOON(p_port + hp_ee_ctrl,
((unsigned char)temp | SEE_MS | SEE_CS));
WR_HARPOON(p_port + hp_ee_ctrl, temp);
if (!
(RDW_HARPOON((p_port + hp_intstat)) &
(BUS_FREE | RESET))) {
FPT_phaseDecode(p_port, p_card);
}
}
}
else if (p_int & RESET) {
WR_HARPOON(p_port + hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(p_port + hp_sys_ctrl, 0x00);
if (pCurrCard->currentSCCB != NULL) {
if (pCurrCard->globalFlags & F_HOST_XFER_ACT)
FPT_hostDataXferAbort(p_port, p_card,
pCurrCard->currentSCCB);
}
DISABLE_AUTO(p_port);
FPT_sresb(p_port, p_card);
while (RD_HARPOON(p_port + hp_scsictrl_0) & SCSI_RST) {
}
pCurrNvRam = pCurrCard->pNvRamInfo;
if (pCurrNvRam) {
ScamFlg = pCurrNvRam->niScamConf;
} else {
ScamFlg =
(unsigned char)FPT_utilEERead(p_port,
SCAM_CONFIG / 2);
}
FPT_XbowInit(p_port, ScamFlg);
FPT_scini(p_card, pCurrCard->ourId, 0);
return 0xFF;
}
else if (p_int & FIFO) {
WRW_HARPOON((p_port + hp_intstat), FIFO);
if (pCurrCard->currentSCCB != NULL)
FPT_sxfrp(p_port, p_card);
}
else if (p_int & TIMEOUT) {
DISABLE_AUTO(p_port);
WRW_HARPOON((p_port + hp_intstat),
(PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE |
IUNKWN));
pCurrCard->currentSCCB->HostStatus = SCCB_SELECTION_TIMEOUT;
currTar_Info =
&FPT_sccbMgrTbl[p_card][pCurrCard->currentSCCB->TargID];
if ((pCurrCard->globalFlags & F_CONLUN_IO)
&& ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING))
currTar_Info->TarLUNBusy[pCurrCard->currentSCCB->Lun] =
0;
else
currTar_Info->TarLUNBusy[0] = 0;
if (currTar_Info->TarEEValue & EE_SYNC_MASK) {
currTar_Info->TarSyncCtrl = 0;
currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
}
if (currTar_Info->TarEEValue & EE_WIDE_SCSI) {
currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
}
FPT_sssyncv(p_port, pCurrCard->currentSCCB->TargID, NARROW_SCSI,
currTar_Info);
FPT_queueCmdComplete(pCurrCard, pCurrCard->currentSCCB, p_card);
}
else if (p_int & SCAM_SEL) {
FPT_scarb(p_port, LEVEL2_TAR);
FPT_scsel(p_port);
FPT_scasid(p_card, p_port);
FPT_scbusf(p_port);
WRW_HARPOON((p_port + hp_intstat), SCAM_SEL);
}
return 0x00;
}
/*---------------------------------------------------------------------
*
* Function: SccbMgrTableInit
*
* Description: Initialize all Sccb manager data structures.
*
*---------------------------------------------------------------------*/
static void FPT_SccbMgrTableInitAll()
{
unsigned char thisCard;
for (thisCard = 0; thisCard < MAX_CARDS; thisCard++) {
FPT_SccbMgrTableInitCard(&FPT_BL_Card[thisCard], thisCard);
FPT_BL_Card[thisCard].ioPort = 0x00;
FPT_BL_Card[thisCard].cardInfo = NULL;
FPT_BL_Card[thisCard].cardIndex = 0xFF;
FPT_BL_Card[thisCard].ourId = 0x00;
FPT_BL_Card[thisCard].pNvRamInfo = NULL;
}
}
/*---------------------------------------------------------------------
*
* Function: SccbMgrTableInit
*
* Description: Initialize all Sccb manager data structures.
*
*---------------------------------------------------------------------*/
static void FPT_SccbMgrTableInitCard(struct sccb_card *pCurrCard,
unsigned char p_card)
{
unsigned char scsiID, qtag;
for (qtag = 0; qtag < QUEUE_DEPTH; qtag++) {
FPT_BL_Card[p_card].discQ_Tbl[qtag] = NULL;
}
for (scsiID = 0; scsiID < MAX_SCSI_TAR; scsiID++) {
FPT_sccbMgrTbl[p_card][scsiID].TarStatus = 0;
FPT_sccbMgrTbl[p_card][scsiID].TarEEValue = 0;
FPT_SccbMgrTableInitTarget(p_card, scsiID);
}
pCurrCard->scanIndex = 0x00;
pCurrCard->currentSCCB = NULL;
pCurrCard->globalFlags = 0x00;
pCurrCard->cmdCounter = 0x00;
pCurrCard->tagQ_Lst = 0x01;
pCurrCard->discQCount = 0;
}
/*---------------------------------------------------------------------
*
* Function: SccbMgrTableInit
*
* Description: Initialize all Sccb manager data structures.
*
*---------------------------------------------------------------------*/
static void FPT_SccbMgrTableInitTarget(unsigned char p_card,
unsigned char target)
{
unsigned char lun, qtag;
struct sccb_mgr_tar_info *currTar_Info;
currTar_Info = &FPT_sccbMgrTbl[p_card][target];
currTar_Info->TarSelQ_Cnt = 0;
currTar_Info->TarSyncCtrl = 0;
currTar_Info->TarSelQ_Head = NULL;
currTar_Info->TarSelQ_Tail = NULL;
currTar_Info->TarTagQ_Cnt = 0;
currTar_Info->TarLUN_CA = 0;
for (lun = 0; lun < MAX_LUN; lun++) {
currTar_Info->TarLUNBusy[lun] = 0;
currTar_Info->LunDiscQ_Idx[lun] = 0;
}
for (qtag = 0; qtag < QUEUE_DEPTH; qtag++) {
if (FPT_BL_Card[p_card].discQ_Tbl[qtag] != NULL) {
if (FPT_BL_Card[p_card].discQ_Tbl[qtag]->TargID ==
target) {
FPT_BL_Card[p_card].discQ_Tbl[qtag] = NULL;
FPT_BL_Card[p_card].discQCount--;
}
}
}
}
/*---------------------------------------------------------------------
*
* Function: sfetm
*
* Description: Read in a message byte from the SCSI bus, and check
* for a parity error.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_sfm(unsigned long port, struct sccb *pCurrSCCB)
{
unsigned char message;
unsigned short TimeOutLoop;
TimeOutLoop = 0;
while ((!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)) &&
(TimeOutLoop++ < 20000)) {
}
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
message = RD_HARPOON(port + hp_scsidata_0);
WR_HARPOON(port + hp_scsisig, SCSI_ACK + S_MSGI_PH);
if (TimeOutLoop > 20000)
message = 0x00; /* force message byte = 0 if Time Out on Req */
if ((RDW_HARPOON((port + hp_intstat)) & PARITY) &&
(RD_HARPOON(port + hp_addstat) & SCSI_PAR_ERR)) {
WR_HARPOON(port + hp_scsisig, (SCSI_ACK + S_ILL_PH));
WR_HARPOON(port + hp_xferstat, 0);
WR_HARPOON(port + hp_fiforead, 0);
WR_HARPOON(port + hp_fifowrite, 0);
if (pCurrSCCB != NULL) {
pCurrSCCB->Sccb_scsimsg = SMPARITY;
}
message = 0x00;
do {
ACCEPT_MSG_ATN(port);
TimeOutLoop = 0;
while ((!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)) &&
(TimeOutLoop++ < 20000)) {
}
if (TimeOutLoop > 20000) {
WRW_HARPOON((port + hp_intstat), PARITY);
return message;
}
if ((RD_HARPOON(port + hp_scsisig) & S_SCSI_PHZ) !=
S_MSGI_PH) {
WRW_HARPOON((port + hp_intstat), PARITY);
return message;
}
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
RD_HARPOON(port + hp_scsidata_0);
WR_HARPOON(port + hp_scsisig, (SCSI_ACK + S_ILL_PH));
} while (1);
}
WR_HARPOON(port + hp_scsisig, (SCSI_ACK + S_ILL_PH));
WR_HARPOON(port + hp_xferstat, 0);
WR_HARPOON(port + hp_fiforead, 0);
WR_HARPOON(port + hp_fifowrite, 0);
return message;
}
/*---------------------------------------------------------------------
*
* Function: FPT_ssel
*
* Description: Load up automation and select target device.
*
*---------------------------------------------------------------------*/
static void FPT_ssel(unsigned long port, unsigned char p_card)
{
unsigned char auto_loaded, i, target, *theCCB;
unsigned long cdb_reg;
struct sccb_card *CurrCard;
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
unsigned char lastTag, lun;
CurrCard = &FPT_BL_Card[p_card];
currSCCB = CurrCard->currentSCCB;
target = currSCCB->TargID;
currTar_Info = &FPT_sccbMgrTbl[p_card][target];
lastTag = CurrCard->tagQ_Lst;
ARAM_ACCESS(port);
if ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) == TAG_Q_REJECT)
currSCCB->ControlByte &= ~F_USE_CMD_Q;
if (((CurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING)))
lun = currSCCB->Lun;
else
lun = 0;
if (CurrCard->globalFlags & F_TAG_STARTED) {
if (!(currSCCB->ControlByte & F_USE_CMD_Q)) {
if ((currTar_Info->TarLUN_CA == 0)
&& ((currTar_Info->TarStatus & TAR_TAG_Q_MASK)
== TAG_Q_TRYING)) {
if (currTar_Info->TarTagQ_Cnt != 0) {
currTar_Info->TarLUNBusy[lun] = 1;
FPT_queueSelectFail(CurrCard, p_card);
SGRAM_ACCESS(port);
return;
}
else {
currTar_Info->TarLUNBusy[lun] = 1;
}
}
/*End non-tagged */
else {
currTar_Info->TarLUNBusy[lun] = 1;
}
}
/*!Use cmd Q Tagged */
else {
if (currTar_Info->TarLUN_CA == 1) {
FPT_queueSelectFail(CurrCard, p_card);
SGRAM_ACCESS(port);
return;
}
currTar_Info->TarLUNBusy[lun] = 1;
} /*else use cmd Q tagged */
}
/*if glob tagged started */
else {
currTar_Info->TarLUNBusy[lun] = 1;
}
if ((((CurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
|| (!(currSCCB->ControlByte & F_USE_CMD_Q)))) {
if (CurrCard->discQCount >= QUEUE_DEPTH) {
currTar_Info->TarLUNBusy[lun] = 1;
FPT_queueSelectFail(CurrCard, p_card);
SGRAM_ACCESS(port);
return;
}
for (i = 1; i < QUEUE_DEPTH; i++) {
if (++lastTag >= QUEUE_DEPTH)
lastTag = 1;
if (CurrCard->discQ_Tbl[lastTag] == NULL) {
CurrCard->tagQ_Lst = lastTag;
currTar_Info->LunDiscQ_Idx[lun] = lastTag;
CurrCard->discQ_Tbl[lastTag] = currSCCB;
CurrCard->discQCount++;
break;
}
}
if (i == QUEUE_DEPTH) {
currTar_Info->TarLUNBusy[lun] = 1;
FPT_queueSelectFail(CurrCard, p_card);
SGRAM_ACCESS(port);
return;
}
}
auto_loaded = 0;
WR_HARPOON(port + hp_select_id, target);
WR_HARPOON(port + hp_gp_reg_3, target); /* Use by new automation logic */
if (currSCCB->OperationCode == RESET_COMMAND) {
WRW_HARPOON((port + ID_MSG_STRT), (MPM_OP + AMSG_OUT +
(currSCCB->
Sccb_idmsg & ~DISC_PRIV)));
WRW_HARPOON((port + ID_MSG_STRT + 2), BRH_OP + ALWAYS + NP);
currSCCB->Sccb_scsimsg = SMDEV_RESET;
WR_HARPOON(port + hp_autostart_3, (SELECT + SELCHK_STRT));
auto_loaded = 1;
currSCCB->Sccb_scsistat = SELECT_BDR_ST;
if (currTar_Info->TarEEValue & EE_SYNC_MASK) {
currTar_Info->TarSyncCtrl = 0;
currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
}
if (currTar_Info->TarEEValue & EE_WIDE_SCSI) {
currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
}
FPT_sssyncv(port, target, NARROW_SCSI, currTar_Info);
FPT_SccbMgrTableInitTarget(p_card, target);
}
else if (currSCCB->Sccb_scsistat == ABORT_ST) {
WRW_HARPOON((port + ID_MSG_STRT), (MPM_OP + AMSG_OUT +
(currSCCB->
Sccb_idmsg & ~DISC_PRIV)));
WRW_HARPOON((port + ID_MSG_STRT + 2), BRH_OP + ALWAYS + CMDPZ);
WRW_HARPOON((port + SYNC_MSGS + 0), (MPM_OP + AMSG_OUT +
(((unsigned
char)(currSCCB->
ControlByte &
TAG_TYPE_MASK)
>> 6) | (unsigned char)
0x20)));
WRW_HARPOON((port + SYNC_MSGS + 2),
(MPM_OP + AMSG_OUT + currSCCB->Sccb_tag));
WRW_HARPOON((port + SYNC_MSGS + 4), (BRH_OP + ALWAYS + NP));
WR_HARPOON(port + hp_autostart_3, (SELECT + SELCHK_STRT));
auto_loaded = 1;
}
else if (!(currTar_Info->TarStatus & WIDE_NEGOCIATED)) {
auto_loaded = FPT_siwidn(port, p_card);
currSCCB->Sccb_scsistat = SELECT_WN_ST;
}
else if (!((currTar_Info->TarStatus & TAR_SYNC_MASK)
== SYNC_SUPPORTED)) {
auto_loaded = FPT_sisyncn(port, p_card, 0);
currSCCB->Sccb_scsistat = SELECT_SN_ST;
}
if (!auto_loaded) {
if (currSCCB->ControlByte & F_USE_CMD_Q) {
CurrCard->globalFlags |= F_TAG_STARTED;
if ((currTar_Info->TarStatus & TAR_TAG_Q_MASK)
== TAG_Q_REJECT) {
currSCCB->ControlByte &= ~F_USE_CMD_Q;
/* Fix up the start instruction with a jump to
Non-Tag-CMD handling */
WRW_HARPOON((port + ID_MSG_STRT),
BRH_OP + ALWAYS + NTCMD);
WRW_HARPOON((port + NON_TAG_ID_MSG),
(MPM_OP + AMSG_OUT +
currSCCB->Sccb_idmsg));
WR_HARPOON(port + hp_autostart_3,
(SELECT + SELCHK_STRT));
/* Setup our STATE so we know what happened when
the wheels fall off. */
currSCCB->Sccb_scsistat = SELECT_ST;
currTar_Info->TarLUNBusy[lun] = 1;
}
else {
WRW_HARPOON((port + ID_MSG_STRT),
(MPM_OP + AMSG_OUT +
currSCCB->Sccb_idmsg));
WRW_HARPOON((port + ID_MSG_STRT + 2),
(MPM_OP + AMSG_OUT +
(((unsigned char)(currSCCB->
ControlByte &
TAG_TYPE_MASK)
>> 6) | (unsigned char)0x20)));
for (i = 1; i < QUEUE_DEPTH; i++) {
if (++lastTag >= QUEUE_DEPTH)
lastTag = 1;
if (CurrCard->discQ_Tbl[lastTag] ==
NULL) {
WRW_HARPOON((port +
ID_MSG_STRT + 6),
(MPM_OP + AMSG_OUT +
lastTag));
CurrCard->tagQ_Lst = lastTag;
currSCCB->Sccb_tag = lastTag;
CurrCard->discQ_Tbl[lastTag] =
currSCCB;
CurrCard->discQCount++;
break;
}
}
if (i == QUEUE_DEPTH) {
currTar_Info->TarLUNBusy[lun] = 1;
FPT_queueSelectFail(CurrCard, p_card);
SGRAM_ACCESS(port);
return;
}
currSCCB->Sccb_scsistat = SELECT_Q_ST;
WR_HARPOON(port + hp_autostart_3,
(SELECT + SELCHK_STRT));
}
}
else {
WRW_HARPOON((port + ID_MSG_STRT),
BRH_OP + ALWAYS + NTCMD);
WRW_HARPOON((port + NON_TAG_ID_MSG),
(MPM_OP + AMSG_OUT + currSCCB->Sccb_idmsg));
currSCCB->Sccb_scsistat = SELECT_ST;
WR_HARPOON(port + hp_autostart_3,
(SELECT + SELCHK_STRT));
}
theCCB = (unsigned char *)&currSCCB->Cdb[0];
cdb_reg = port + CMD_STRT;
for (i = 0; i < currSCCB->CdbLength; i++) {
WRW_HARPOON(cdb_reg, (MPM_OP + ACOMMAND + *theCCB));
cdb_reg += 2;
theCCB++;
}
if (currSCCB->CdbLength != TWELVE_BYTE_CMD)
WRW_HARPOON(cdb_reg, (BRH_OP + ALWAYS + NP));
}
/* auto_loaded */
WRW_HARPOON((port + hp_fiforead), (unsigned short)0x00);
WR_HARPOON(port + hp_xferstat, 0x00);
WRW_HARPOON((port + hp_intstat), (PROG_HLT | TIMEOUT | SEL | BUS_FREE));
WR_HARPOON(port + hp_portctrl_0, (SCSI_PORT));
if (!(currSCCB->Sccb_MGRFlags & F_DEV_SELECTED)) {
WR_HARPOON(port + hp_scsictrl_0,
(SEL_TAR | ENA_ATN | ENA_RESEL | ENA_SCAM_SEL));
} else {
/* auto_loaded = (RD_HARPOON(port+hp_autostart_3) & (unsigned char)0x1F);
auto_loaded |= AUTO_IMMED; */
auto_loaded = AUTO_IMMED;
DISABLE_AUTO(port);
WR_HARPOON(port + hp_autostart_3, auto_loaded);
}
SGRAM_ACCESS(port);
}
/*---------------------------------------------------------------------
*
* Function: FPT_sres
*
* Description: Hookup the correct CCB and handle the incoming messages.
*
*---------------------------------------------------------------------*/
static void FPT_sres(unsigned long port, unsigned char p_card,
struct sccb_card *pCurrCard)
{
unsigned char our_target, message, lun = 0, tag, msgRetryCount;
struct sccb_mgr_tar_info *currTar_Info;
struct sccb *currSCCB;
if (pCurrCard->currentSCCB != NULL) {
currTar_Info =
&FPT_sccbMgrTbl[p_card][pCurrCard->currentSCCB->TargID];
DISABLE_AUTO(port);
WR_HARPOON((port + hp_scsictrl_0), (ENA_RESEL | ENA_SCAM_SEL));
currSCCB = pCurrCard->currentSCCB;
if (currSCCB->Sccb_scsistat == SELECT_WN_ST) {
currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
currSCCB->Sccb_scsistat = BUS_FREE_ST;
}
if (currSCCB->Sccb_scsistat == SELECT_SN_ST) {
currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
currSCCB->Sccb_scsistat = BUS_FREE_ST;
}
if (((pCurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING))) {
currTar_Info->TarLUNBusy[currSCCB->Lun] = 0;
if (currSCCB->Sccb_scsistat != ABORT_ST) {
pCurrCard->discQCount--;
pCurrCard->discQ_Tbl[currTar_Info->
LunDiscQ_Idx[currSCCB->
Lun]]
= NULL;
}
} else {
currTar_Info->TarLUNBusy[0] = 0;
if (currSCCB->Sccb_tag) {
if (currSCCB->Sccb_scsistat != ABORT_ST) {
pCurrCard->discQCount--;
pCurrCard->discQ_Tbl[currSCCB->
Sccb_tag] = NULL;
}
} else {
if (currSCCB->Sccb_scsistat != ABORT_ST) {
pCurrCard->discQCount--;
pCurrCard->discQ_Tbl[currTar_Info->
LunDiscQ_Idx[0]] =
NULL;
}
}
}
FPT_queueSelectFail(&FPT_BL_Card[p_card], p_card);
}
WRW_HARPOON((port + hp_fiforead), (unsigned short)0x00);
our_target = (unsigned char)(RD_HARPOON(port + hp_select_id) >> 4);
currTar_Info = &FPT_sccbMgrTbl[p_card][our_target];
msgRetryCount = 0;
do {
currTar_Info = &FPT_sccbMgrTbl[p_card][our_target];
tag = 0;
while (!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)) {
if (!(RD_HARPOON(port + hp_scsisig) & SCSI_BSY)) {
WRW_HARPOON((port + hp_intstat), PHASE);
return;
}
}
WRW_HARPOON((port + hp_intstat), PHASE);
if ((RD_HARPOON(port + hp_scsisig) & S_SCSI_PHZ) == S_MSGI_PH) {
message = FPT_sfm(port, pCurrCard->currentSCCB);
if (message) {
if (message <= (0x80 | LUN_MASK)) {
lun = message & (unsigned char)LUN_MASK;
if ((currTar_Info->
TarStatus & TAR_TAG_Q_MASK) ==
TAG_Q_TRYING) {
if (currTar_Info->TarTagQ_Cnt !=
0) {
if (!
(currTar_Info->
TarLUN_CA)) {
ACCEPT_MSG(port); /*Release the ACK for ID msg. */
message =
FPT_sfm
(port,
pCurrCard->
currentSCCB);
if (message) {
ACCEPT_MSG
(port);
}
else
message
= 0;
if (message !=
0) {
tag =
FPT_sfm
(port,
pCurrCard->
currentSCCB);
if (!
(tag))
message
=
0;
}
}
/*C.A. exists! */
}
/*End Q cnt != 0 */
}
/*End Tag cmds supported! */
}
/*End valid ID message. */
else {
ACCEPT_MSG_ATN(port);
}
}
/* End good id message. */
else {
message = 0;
}
} else {
ACCEPT_MSG_ATN(port);
while (!
(RDW_HARPOON((port + hp_intstat)) &
(PHASE | RESET))
&& !(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)
&& (RD_HARPOON(port + hp_scsisig) & SCSI_BSY)) ;
return;
}
if (message == 0) {
msgRetryCount++;
if (msgRetryCount == 1) {
FPT_SendMsg(port, SMPARITY);
} else {
FPT_SendMsg(port, SMDEV_RESET);
FPT_sssyncv(port, our_target, NARROW_SCSI,
currTar_Info);
if (FPT_sccbMgrTbl[p_card][our_target].
TarEEValue & EE_SYNC_MASK) {
FPT_sccbMgrTbl[p_card][our_target].
TarStatus &= ~TAR_SYNC_MASK;
}
if (FPT_sccbMgrTbl[p_card][our_target].
TarEEValue & EE_WIDE_SCSI) {
FPT_sccbMgrTbl[p_card][our_target].
TarStatus &= ~TAR_WIDE_MASK;
}
FPT_queueFlushTargSccb(p_card, our_target,
SCCB_COMPLETE);
FPT_SccbMgrTableInitTarget(p_card, our_target);
return;
}
}
} while (message == 0);
if (((pCurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))) {
currTar_Info->TarLUNBusy[lun] = 1;
pCurrCard->currentSCCB =
pCurrCard->discQ_Tbl[currTar_Info->LunDiscQ_Idx[lun]];
if (pCurrCard->currentSCCB != NULL) {
ACCEPT_MSG(port);
} else {
ACCEPT_MSG_ATN(port);
}
} else {
currTar_Info->TarLUNBusy[0] = 1;
if (tag) {
if (pCurrCard->discQ_Tbl[tag] != NULL) {
pCurrCard->currentSCCB =
pCurrCard->discQ_Tbl[tag];
currTar_Info->TarTagQ_Cnt--;
ACCEPT_MSG(port);
} else {
ACCEPT_MSG_ATN(port);
}
} else {
pCurrCard->currentSCCB =
pCurrCard->discQ_Tbl[currTar_Info->LunDiscQ_Idx[0]];
if (pCurrCard->currentSCCB != NULL) {
ACCEPT_MSG(port);
} else {
ACCEPT_MSG_ATN(port);
}
}
}
if (pCurrCard->currentSCCB != NULL) {
if (pCurrCard->currentSCCB->Sccb_scsistat == ABORT_ST) {
/* During Abort Tag command, the target could have got re-selected
and completed the command. Check the select Q and remove the CCB
if it is in the Select Q */
FPT_queueFindSccb(pCurrCard->currentSCCB, p_card);
}
}
while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ) &&
(RD_HARPOON(port + hp_scsisig) & SCSI_BSY)) ;
}
static void FPT_SendMsg(unsigned long port, unsigned char message)
{
while (!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)) {
if (!(RD_HARPOON(port + hp_scsisig) & SCSI_BSY)) {
WRW_HARPOON((port + hp_intstat), PHASE);
return;
}
}
WRW_HARPOON((port + hp_intstat), PHASE);
if ((RD_HARPOON(port + hp_scsisig) & S_SCSI_PHZ) == S_MSGO_PH) {
WRW_HARPOON((port + hp_intstat),
(BUS_FREE | PHASE | XFER_CNT_0));
WR_HARPOON(port + hp_portctrl_0, SCSI_BUS_EN);
WR_HARPOON(port + hp_scsidata_0, message);
WR_HARPOON(port + hp_scsisig, (SCSI_ACK + S_ILL_PH));
ACCEPT_MSG(port);
WR_HARPOON(port + hp_portctrl_0, 0x00);
if ((message == SMABORT) || (message == SMDEV_RESET) ||
(message == SMABORT_TAG)) {
while (!
(RDW_HARPOON((port + hp_intstat)) &
(BUS_FREE | PHASE))) {
}
if (RDW_HARPOON((port + hp_intstat)) & BUS_FREE) {
WRW_HARPOON((port + hp_intstat), BUS_FREE);
}
}
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_sdecm
*
* Description: Determine the proper response to the message from the
* target device.
*
*---------------------------------------------------------------------*/
static void FPT_sdecm(unsigned char message, unsigned long port,
unsigned char p_card)
{
struct sccb *currSCCB;
struct sccb_card *CurrCard;
struct sccb_mgr_tar_info *currTar_Info;
CurrCard = &FPT_BL_Card[p_card];
currSCCB = CurrCard->currentSCCB;
currTar_Info = &FPT_sccbMgrTbl[p_card][currSCCB->TargID];
if (message == SMREST_DATA_PTR) {
if (!(currSCCB->Sccb_XferState & F_NO_DATA_YET)) {
currSCCB->Sccb_ATC = currSCCB->Sccb_savedATC;
FPT_hostDataXferRestart(currSCCB);
}
ACCEPT_MSG(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
else if (message == SMCMD_COMP) {
if (currSCCB->Sccb_scsistat == SELECT_Q_ST) {
currTar_Info->TarStatus &=
~(unsigned char)TAR_TAG_Q_MASK;
currTar_Info->TarStatus |= (unsigned char)TAG_Q_REJECT;
}
ACCEPT_MSG(port);
}
else if ((message == SMNO_OP) || (message >= SMIDENT)
|| (message == SMINIT_RECOVERY) || (message == SMREL_RECOVERY)) {
ACCEPT_MSG(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
else if (message == SMREJECT) {
if ((currSCCB->Sccb_scsistat == SELECT_SN_ST) ||
(currSCCB->Sccb_scsistat == SELECT_WN_ST) ||
((currTar_Info->TarStatus & TAR_SYNC_MASK) == SYNC_TRYING)
|| ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) ==
TAG_Q_TRYING))
{
WRW_HARPOON((port + hp_intstat), BUS_FREE);
ACCEPT_MSG(port);
while ((!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)) &&
(!(RDW_HARPOON((port + hp_intstat)) & BUS_FREE)))
{
}
if (currSCCB->Lun == 0x00) {
if ((currSCCB->Sccb_scsistat == SELECT_SN_ST)) {
currTar_Info->TarStatus |=
(unsigned char)SYNC_SUPPORTED;
currTar_Info->TarEEValue &=
~EE_SYNC_MASK;
}
else if ((currSCCB->Sccb_scsistat ==
SELECT_WN_ST)) {
currTar_Info->TarStatus =
(currTar_Info->
TarStatus & ~WIDE_ENABLED) |
WIDE_NEGOCIATED;
currTar_Info->TarEEValue &=
~EE_WIDE_SCSI;
}
else if ((currTar_Info->
TarStatus & TAR_TAG_Q_MASK) ==
TAG_Q_TRYING) {
currTar_Info->TarStatus =
(currTar_Info->
TarStatus & ~(unsigned char)
TAR_TAG_Q_MASK) | TAG_Q_REJECT;
currSCCB->ControlByte &= ~F_USE_CMD_Q;
CurrCard->discQCount--;
CurrCard->discQ_Tbl[currSCCB->
Sccb_tag] = NULL;
currSCCB->Sccb_tag = 0x00;
}
}
if (RDW_HARPOON((port + hp_intstat)) & BUS_FREE) {
if (currSCCB->Lun == 0x00) {
WRW_HARPOON((port + hp_intstat),
BUS_FREE);
CurrCard->globalFlags |= F_NEW_SCCB_CMD;
}
}
else {
if ((CurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->
TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING))
currTar_Info->TarLUNBusy[currSCCB->
Lun] = 1;
else
currTar_Info->TarLUNBusy[0] = 1;
currSCCB->ControlByte &=
~(unsigned char)F_USE_CMD_Q;
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
}
else {
ACCEPT_MSG(port);
while ((!(RD_HARPOON(port + hp_scsisig) & SCSI_REQ)) &&
(!(RDW_HARPOON((port + hp_intstat)) & BUS_FREE)))
{
}
if (!(RDW_HARPOON((port + hp_intstat)) & BUS_FREE)) {
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
}
}
else if (message == SMEXT) {
ACCEPT_MSG(port);
FPT_shandem(port, p_card, currSCCB);
}
else if (message == SMIGNORWR) {
ACCEPT_MSG(port); /* ACK the RESIDUE MSG */
message = FPT_sfm(port, currSCCB);
if (currSCCB->Sccb_scsimsg != SMPARITY)
ACCEPT_MSG(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
else {
currSCCB->HostStatus = SCCB_PHASE_SEQUENCE_FAIL;
currSCCB->Sccb_scsimsg = SMREJECT;
ACCEPT_MSG_ATN(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_shandem
*
* Description: Decide what to do with the extended message.
*
*---------------------------------------------------------------------*/
static void FPT_shandem(unsigned long port, unsigned char p_card,
struct sccb *pCurrSCCB)
{
unsigned char length, message;
length = FPT_sfm(port, pCurrSCCB);
if (length) {
ACCEPT_MSG(port);
message = FPT_sfm(port, pCurrSCCB);
if (message) {
if (message == SMSYNC) {
if (length == 0x03) {
ACCEPT_MSG(port);
FPT_stsyncn(port, p_card);
} else {
pCurrSCCB->Sccb_scsimsg = SMREJECT;
ACCEPT_MSG_ATN(port);
}
} else if (message == SMWDTR) {
if (length == 0x02) {
ACCEPT_MSG(port);
FPT_stwidn(port, p_card);
} else {
pCurrSCCB->Sccb_scsimsg = SMREJECT;
ACCEPT_MSG_ATN(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED +
DISCONNECT_START));
}
} else {
pCurrSCCB->Sccb_scsimsg = SMREJECT;
ACCEPT_MSG_ATN(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
} else {
if (pCurrSCCB->Sccb_scsimsg != SMPARITY)
ACCEPT_MSG(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
} else {
if (pCurrSCCB->Sccb_scsimsg == SMPARITY)
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_sisyncn
*
* Description: Read in a message byte from the SCSI bus, and check
* for a parity error.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_sisyncn(unsigned long port, unsigned char p_card,
unsigned char syncFlag)
{
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
currTar_Info = &FPT_sccbMgrTbl[p_card][currSCCB->TargID];
if (!((currTar_Info->TarStatus & TAR_SYNC_MASK) == SYNC_TRYING)) {
WRW_HARPOON((port + ID_MSG_STRT),
(MPM_OP + AMSG_OUT +
(currSCCB->
Sccb_idmsg & ~(unsigned char)DISC_PRIV)));
WRW_HARPOON((port + ID_MSG_STRT + 2), BRH_OP + ALWAYS + CMDPZ);
WRW_HARPOON((port + SYNC_MSGS + 0),
(MPM_OP + AMSG_OUT + SMEXT));
WRW_HARPOON((port + SYNC_MSGS + 2), (MPM_OP + AMSG_OUT + 0x03));
WRW_HARPOON((port + SYNC_MSGS + 4),
(MPM_OP + AMSG_OUT + SMSYNC));
if ((currTar_Info->TarEEValue & EE_SYNC_MASK) == EE_SYNC_20MB)
WRW_HARPOON((port + SYNC_MSGS + 6),
(MPM_OP + AMSG_OUT + 12));
else if ((currTar_Info->TarEEValue & EE_SYNC_MASK) ==
EE_SYNC_10MB)
WRW_HARPOON((port + SYNC_MSGS + 6),
(MPM_OP + AMSG_OUT + 25));
else if ((currTar_Info->TarEEValue & EE_SYNC_MASK) ==
EE_SYNC_5MB)
WRW_HARPOON((port + SYNC_MSGS + 6),
(MPM_OP + AMSG_OUT + 50));
else
WRW_HARPOON((port + SYNC_MSGS + 6),
(MPM_OP + AMSG_OUT + 00));
WRW_HARPOON((port + SYNC_MSGS + 8), (RAT_OP));
WRW_HARPOON((port + SYNC_MSGS + 10),
(MPM_OP + AMSG_OUT + DEFAULT_OFFSET));
WRW_HARPOON((port + SYNC_MSGS + 12), (BRH_OP + ALWAYS + NP));
if (syncFlag == 0) {
WR_HARPOON(port + hp_autostart_3,
(SELECT + SELCHK_STRT));
currTar_Info->TarStatus =
((currTar_Info->
TarStatus & ~(unsigned char)TAR_SYNC_MASK) |
(unsigned char)SYNC_TRYING);
} else {
WR_HARPOON(port + hp_autostart_3,
(AUTO_IMMED + CMD_ONLY_STRT));
}
return 1;
}
else {
currTar_Info->TarStatus |= (unsigned char)SYNC_SUPPORTED;
currTar_Info->TarEEValue &= ~EE_SYNC_MASK;
return 0;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_stsyncn
*
* Description: The has sent us a Sync Nego message so handle it as
* necessary.
*
*---------------------------------------------------------------------*/
static void FPT_stsyncn(unsigned long port, unsigned char p_card)
{
unsigned char sync_msg, offset, sync_reg, our_sync_msg;
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
currTar_Info = &FPT_sccbMgrTbl[p_card][currSCCB->TargID];
sync_msg = FPT_sfm(port, currSCCB);
if ((sync_msg == 0x00) && (currSCCB->Sccb_scsimsg == SMPARITY)) {
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
return;
}
ACCEPT_MSG(port);
offset = FPT_sfm(port, currSCCB);
if ((offset == 0x00) && (currSCCB->Sccb_scsimsg == SMPARITY)) {
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
return;
}
if ((currTar_Info->TarEEValue & EE_SYNC_MASK) == EE_SYNC_20MB)
our_sync_msg = 12; /* Setup our Message to 20mb/s */
else if ((currTar_Info->TarEEValue & EE_SYNC_MASK) == EE_SYNC_10MB)
our_sync_msg = 25; /* Setup our Message to 10mb/s */
else if ((currTar_Info->TarEEValue & EE_SYNC_MASK) == EE_SYNC_5MB)
our_sync_msg = 50; /* Setup our Message to 5mb/s */
else
our_sync_msg = 0; /* Message = Async */
if (sync_msg < our_sync_msg) {
sync_msg = our_sync_msg; /*if faster, then set to max. */
}
if (offset == ASYNC)
sync_msg = ASYNC;
if (offset > MAX_OFFSET)
offset = MAX_OFFSET;
sync_reg = 0x00;
if (sync_msg > 12)
sync_reg = 0x20; /* Use 10MB/s */
if (sync_msg > 25)
sync_reg = 0x40; /* Use 6.6MB/s */
if (sync_msg > 38)
sync_reg = 0x60; /* Use 5MB/s */
if (sync_msg > 50)
sync_reg = 0x80; /* Use 4MB/s */
if (sync_msg > 62)
sync_reg = 0xA0; /* Use 3.33MB/s */
if (sync_msg > 75)
sync_reg = 0xC0; /* Use 2.85MB/s */
if (sync_msg > 87)
sync_reg = 0xE0; /* Use 2.5MB/s */
if (sync_msg > 100) {
sync_reg = 0x00; /* Use ASYNC */
offset = 0x00;
}
if (currTar_Info->TarStatus & WIDE_ENABLED)
sync_reg |= offset;
else
sync_reg |= (offset | NARROW_SCSI);
FPT_sssyncv(port, currSCCB->TargID, sync_reg, currTar_Info);
if (currSCCB->Sccb_scsistat == SELECT_SN_ST) {
ACCEPT_MSG(port);
currTar_Info->TarStatus = ((currTar_Info->TarStatus &
~(unsigned char)TAR_SYNC_MASK) |
(unsigned char)SYNC_SUPPORTED);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
else {
ACCEPT_MSG_ATN(port);
FPT_sisyncr(port, sync_msg, offset);
currTar_Info->TarStatus = ((currTar_Info->TarStatus &
~(unsigned char)TAR_SYNC_MASK) |
(unsigned char)SYNC_SUPPORTED);
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_sisyncr
*
* Description: Answer the targets sync message.
*
*---------------------------------------------------------------------*/
static void FPT_sisyncr(unsigned long port, unsigned char sync_pulse,
unsigned char offset)
{
ARAM_ACCESS(port);
WRW_HARPOON((port + SYNC_MSGS + 0), (MPM_OP + AMSG_OUT + SMEXT));
WRW_HARPOON((port + SYNC_MSGS + 2), (MPM_OP + AMSG_OUT + 0x03));
WRW_HARPOON((port + SYNC_MSGS + 4), (MPM_OP + AMSG_OUT + SMSYNC));
WRW_HARPOON((port + SYNC_MSGS + 6), (MPM_OP + AMSG_OUT + sync_pulse));
WRW_HARPOON((port + SYNC_MSGS + 8), (RAT_OP));
WRW_HARPOON((port + SYNC_MSGS + 10), (MPM_OP + AMSG_OUT + offset));
WRW_HARPOON((port + SYNC_MSGS + 12), (BRH_OP + ALWAYS + NP));
SGRAM_ACCESS(port);
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
WRW_HARPOON((port + hp_intstat), CLR_ALL_INT_1);
WR_HARPOON(port + hp_autostart_3, (AUTO_IMMED + CMD_ONLY_STRT));
while (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | AUTO_INT))) {
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_siwidn
*
* Description: Read in a message byte from the SCSI bus, and check
* for a parity error.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_siwidn(unsigned long port, unsigned char p_card)
{
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
currTar_Info = &FPT_sccbMgrTbl[p_card][currSCCB->TargID];
if (!((currTar_Info->TarStatus & TAR_WIDE_MASK) == WIDE_NEGOCIATED)) {
WRW_HARPOON((port + ID_MSG_STRT),
(MPM_OP + AMSG_OUT +
(currSCCB->
Sccb_idmsg & ~(unsigned char)DISC_PRIV)));
WRW_HARPOON((port + ID_MSG_STRT + 2), BRH_OP + ALWAYS + CMDPZ);
WRW_HARPOON((port + SYNC_MSGS + 0),
(MPM_OP + AMSG_OUT + SMEXT));
WRW_HARPOON((port + SYNC_MSGS + 2), (MPM_OP + AMSG_OUT + 0x02));
WRW_HARPOON((port + SYNC_MSGS + 4),
(MPM_OP + AMSG_OUT + SMWDTR));
WRW_HARPOON((port + SYNC_MSGS + 6), (RAT_OP));
WRW_HARPOON((port + SYNC_MSGS + 8),
(MPM_OP + AMSG_OUT + SM16BIT));
WRW_HARPOON((port + SYNC_MSGS + 10), (BRH_OP + ALWAYS + NP));
WR_HARPOON(port + hp_autostart_3, (SELECT + SELCHK_STRT));
currTar_Info->TarStatus = ((currTar_Info->TarStatus &
~(unsigned char)TAR_WIDE_MASK) |
(unsigned char)WIDE_ENABLED);
return 1;
}
else {
currTar_Info->TarStatus = ((currTar_Info->TarStatus &
~(unsigned char)TAR_WIDE_MASK) |
WIDE_NEGOCIATED);
currTar_Info->TarEEValue &= ~EE_WIDE_SCSI;
return 0;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_stwidn
*
* Description: The has sent us a Wide Nego message so handle it as
* necessary.
*
*---------------------------------------------------------------------*/
static void FPT_stwidn(unsigned long port, unsigned char p_card)
{
unsigned char width;
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
currTar_Info = &FPT_sccbMgrTbl[p_card][currSCCB->TargID];
width = FPT_sfm(port, currSCCB);
if ((width == 0x00) && (currSCCB->Sccb_scsimsg == SMPARITY)) {
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
return;
}
if (!(currTar_Info->TarEEValue & EE_WIDE_SCSI))
width = 0;
if (width) {
currTar_Info->TarStatus |= WIDE_ENABLED;
width = 0;
} else {
width = NARROW_SCSI;
currTar_Info->TarStatus &= ~WIDE_ENABLED;
}
FPT_sssyncv(port, currSCCB->TargID, width, currTar_Info);
if (currSCCB->Sccb_scsistat == SELECT_WN_ST) {
currTar_Info->TarStatus |= WIDE_NEGOCIATED;
if (!
((currTar_Info->TarStatus & TAR_SYNC_MASK) ==
SYNC_SUPPORTED)) {
ACCEPT_MSG_ATN(port);
ARAM_ACCESS(port);
FPT_sisyncn(port, p_card, 1);
currSCCB->Sccb_scsistat = SELECT_SN_ST;
SGRAM_ACCESS(port);
} else {
ACCEPT_MSG(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
}
else {
ACCEPT_MSG_ATN(port);
if (currTar_Info->TarEEValue & EE_WIDE_SCSI)
width = SM16BIT;
else
width = SM8BIT;
FPT_siwidr(port, width);
currTar_Info->TarStatus |= (WIDE_NEGOCIATED | WIDE_ENABLED);
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_siwidr
*
* Description: Answer the targets Wide nego message.
*
*---------------------------------------------------------------------*/
static void FPT_siwidr(unsigned long port, unsigned char width)
{
ARAM_ACCESS(port);
WRW_HARPOON((port + SYNC_MSGS + 0), (MPM_OP + AMSG_OUT + SMEXT));
WRW_HARPOON((port + SYNC_MSGS + 2), (MPM_OP + AMSG_OUT + 0x02));
WRW_HARPOON((port + SYNC_MSGS + 4), (MPM_OP + AMSG_OUT + SMWDTR));
WRW_HARPOON((port + SYNC_MSGS + 6), (RAT_OP));
WRW_HARPOON((port + SYNC_MSGS + 8), (MPM_OP + AMSG_OUT + width));
WRW_HARPOON((port + SYNC_MSGS + 10), (BRH_OP + ALWAYS + NP));
SGRAM_ACCESS(port);
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
WRW_HARPOON((port + hp_intstat), CLR_ALL_INT_1);
WR_HARPOON(port + hp_autostart_3, (AUTO_IMMED + CMD_ONLY_STRT));
while (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | AUTO_INT))) {
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_sssyncv
*
* Description: Write the desired value to the Sync Register for the
* ID specified.
*
*---------------------------------------------------------------------*/
static void FPT_sssyncv(unsigned long p_port, unsigned char p_id,
unsigned char p_sync_value,
struct sccb_mgr_tar_info *currTar_Info)
{
unsigned char index;
index = p_id;
switch (index) {
case 0:
index = 12; /* hp_synctarg_0 */
break;
case 1:
index = 13; /* hp_synctarg_1 */
break;
case 2:
index = 14; /* hp_synctarg_2 */
break;
case 3:
index = 15; /* hp_synctarg_3 */
break;
case 4:
index = 8; /* hp_synctarg_4 */
break;
case 5:
index = 9; /* hp_synctarg_5 */
break;
case 6:
index = 10; /* hp_synctarg_6 */
break;
case 7:
index = 11; /* hp_synctarg_7 */
break;
case 8:
index = 4; /* hp_synctarg_8 */
break;
case 9:
index = 5; /* hp_synctarg_9 */
break;
case 10:
index = 6; /* hp_synctarg_10 */
break;
case 11:
index = 7; /* hp_synctarg_11 */
break;
case 12:
index = 0; /* hp_synctarg_12 */
break;
case 13:
index = 1; /* hp_synctarg_13 */
break;
case 14:
index = 2; /* hp_synctarg_14 */
break;
case 15:
index = 3; /* hp_synctarg_15 */
}
WR_HARPOON(p_port + hp_synctarg_base + index, p_sync_value);
currTar_Info->TarSyncCtrl = p_sync_value;
}
/*---------------------------------------------------------------------
*
* Function: FPT_sresb
*
* Description: Reset the desired card's SCSI bus.
*
*---------------------------------------------------------------------*/
static void FPT_sresb(unsigned long port, unsigned char p_card)
{
unsigned char scsiID, i;
struct sccb_mgr_tar_info *currTar_Info;
WR_HARPOON(port + hp_page_ctrl,
(RD_HARPOON(port + hp_page_ctrl) | G_INT_DISABLE));
WRW_HARPOON((port + hp_intstat), CLR_ALL_INT);
WR_HARPOON(port + hp_scsictrl_0, SCSI_RST);
scsiID = RD_HARPOON(port + hp_seltimeout);
WR_HARPOON(port + hp_seltimeout, TO_5ms);
WRW_HARPOON((port + hp_intstat), TIMEOUT);
WR_HARPOON(port + hp_portctrl_0, (SCSI_PORT | START_TO));
while (!(RDW_HARPOON((port + hp_intstat)) & TIMEOUT)) {
}
WR_HARPOON(port + hp_seltimeout, scsiID);
WR_HARPOON(port + hp_scsictrl_0, ENA_SCAM_SEL);
FPT_Wait(port, TO_5ms);
WRW_HARPOON((port + hp_intstat), CLR_ALL_INT);
WR_HARPOON(port + hp_int_mask, (RD_HARPOON(port + hp_int_mask) | 0x00));
for (scsiID = 0; scsiID < MAX_SCSI_TAR; scsiID++) {
currTar_Info = &FPT_sccbMgrTbl[p_card][scsiID];
if (currTar_Info->TarEEValue & EE_SYNC_MASK) {
currTar_Info->TarSyncCtrl = 0;
currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
}
if (currTar_Info->TarEEValue & EE_WIDE_SCSI) {
currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
}
FPT_sssyncv(port, scsiID, NARROW_SCSI, currTar_Info);
FPT_SccbMgrTableInitTarget(p_card, scsiID);
}
FPT_BL_Card[p_card].scanIndex = 0x00;
FPT_BL_Card[p_card].currentSCCB = NULL;
FPT_BL_Card[p_card].globalFlags &= ~(F_TAG_STARTED | F_HOST_XFER_ACT
| F_NEW_SCCB_CMD);
FPT_BL_Card[p_card].cmdCounter = 0x00;
FPT_BL_Card[p_card].discQCount = 0x00;
FPT_BL_Card[p_card].tagQ_Lst = 0x01;
for (i = 0; i < QUEUE_DEPTH; i++)
FPT_BL_Card[p_card].discQ_Tbl[i] = NULL;
WR_HARPOON(port + hp_page_ctrl,
(RD_HARPOON(port + hp_page_ctrl) & ~G_INT_DISABLE));
}
/*---------------------------------------------------------------------
*
* Function: FPT_ssenss
*
* Description: Setup for the Auto Sense command.
*
*---------------------------------------------------------------------*/
static void FPT_ssenss(struct sccb_card *pCurrCard)
{
unsigned char i;
struct sccb *currSCCB;
currSCCB = pCurrCard->currentSCCB;
currSCCB->Save_CdbLen = currSCCB->CdbLength;
for (i = 0; i < 6; i++) {
currSCCB->Save_Cdb[i] = currSCCB->Cdb[i];
}
currSCCB->CdbLength = SIX_BYTE_CMD;
currSCCB->Cdb[0] = SCSI_REQUEST_SENSE;
currSCCB->Cdb[1] = currSCCB->Cdb[1] & (unsigned char)0xE0; /*Keep LUN. */
currSCCB->Cdb[2] = 0x00;
currSCCB->Cdb[3] = 0x00;
currSCCB->Cdb[4] = currSCCB->RequestSenseLength;
currSCCB->Cdb[5] = 0x00;
currSCCB->Sccb_XferCnt = (unsigned long)currSCCB->RequestSenseLength;
currSCCB->Sccb_ATC = 0x00;
currSCCB->Sccb_XferState |= F_AUTO_SENSE;
currSCCB->Sccb_XferState &= ~F_SG_XFER;
currSCCB->Sccb_idmsg = currSCCB->Sccb_idmsg & ~(unsigned char)DISC_PRIV;
currSCCB->ControlByte = 0x00;
currSCCB->Sccb_MGRFlags &= F_STATUSLOADED;
}
/*---------------------------------------------------------------------
*
* Function: FPT_sxfrp
*
* Description: Transfer data into the bit bucket until the device
* decides to switch phase.
*
*---------------------------------------------------------------------*/
static void FPT_sxfrp(unsigned long p_port, unsigned char p_card)
{
unsigned char curr_phz;
DISABLE_AUTO(p_port);
if (FPT_BL_Card[p_card].globalFlags & F_HOST_XFER_ACT) {
FPT_hostDataXferAbort(p_port, p_card,
FPT_BL_Card[p_card].currentSCCB);
}
/* If the Automation handled the end of the transfer then do not
match the phase or we will get out of sync with the ISR. */
if (RDW_HARPOON((p_port + hp_intstat)) &
(BUS_FREE | XFER_CNT_0 | AUTO_INT))
return;
WR_HARPOON(p_port + hp_xfercnt_0, 0x00);
curr_phz = RD_HARPOON(p_port + hp_scsisig) & (unsigned char)S_SCSI_PHZ;
WRW_HARPOON((p_port + hp_intstat), XFER_CNT_0);
WR_HARPOON(p_port + hp_scsisig, curr_phz);
while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET)) &&
(curr_phz ==
(RD_HARPOON(p_port + hp_scsisig) & (unsigned char)S_SCSI_PHZ)))
{
if (curr_phz & (unsigned char)SCSI_IOBIT) {
WR_HARPOON(p_port + hp_portctrl_0,
(SCSI_PORT | HOST_PORT | SCSI_INBIT));
if (!(RD_HARPOON(p_port + hp_xferstat) & FIFO_EMPTY)) {
RD_HARPOON(p_port + hp_fifodata_0);
}
} else {
WR_HARPOON(p_port + hp_portctrl_0,
(SCSI_PORT | HOST_PORT | HOST_WRT));
if (RD_HARPOON(p_port + hp_xferstat) & FIFO_EMPTY) {
WR_HARPOON(p_port + hp_fifodata_0, 0xFA);
}
}
} /* End of While loop for padding data I/O phase */
while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
if (RD_HARPOON(p_port + hp_scsisig) & SCSI_REQ)
break;
}
WR_HARPOON(p_port + hp_portctrl_0,
(SCSI_PORT | HOST_PORT | SCSI_INBIT));
while (!(RD_HARPOON(p_port + hp_xferstat) & FIFO_EMPTY)) {
RD_HARPOON(p_port + hp_fifodata_0);
}
if (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
WR_HARPOON(p_port + hp_autostart_0,
(AUTO_IMMED + DISCONNECT_START));
while (!(RDW_HARPOON((p_port + hp_intstat)) & AUTO_INT)) {
}
if (RDW_HARPOON((p_port + hp_intstat)) &
(ICMD_COMP | ITAR_DISC))
while (!
(RDW_HARPOON((p_port + hp_intstat)) &
(BUS_FREE | RSEL))) ;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_schkdd
*
* Description: Make sure data has been flushed from both FIFOs and abort
* the operations if necessary.
*
*---------------------------------------------------------------------*/
static void FPT_schkdd(unsigned long port, unsigned char p_card)
{
unsigned short TimeOutLoop;
unsigned char sPhase;
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if ((currSCCB->Sccb_scsistat != DATA_OUT_ST) &&
(currSCCB->Sccb_scsistat != DATA_IN_ST)) {
return;
}
if (currSCCB->Sccb_XferState & F_ODD_BALL_CNT) {
currSCCB->Sccb_ATC += (currSCCB->Sccb_XferCnt - 1);
currSCCB->Sccb_XferCnt = 1;
currSCCB->Sccb_XferState &= ~F_ODD_BALL_CNT;
WRW_HARPOON((port + hp_fiforead), (unsigned short)0x00);
WR_HARPOON(port + hp_xferstat, 0x00);
}
else {
currSCCB->Sccb_ATC += currSCCB->Sccb_XferCnt;
currSCCB->Sccb_XferCnt = 0;
}
if ((RDW_HARPOON((port + hp_intstat)) & PARITY) &&
(currSCCB->HostStatus == SCCB_COMPLETE)) {
currSCCB->HostStatus = SCCB_PARITY_ERR;
WRW_HARPOON((port + hp_intstat), PARITY);
}
FPT_hostDataXferAbort(port, p_card, currSCCB);
while (RD_HARPOON(port + hp_scsisig) & SCSI_ACK) {
}
TimeOutLoop = 0;
while (RD_HARPOON(port + hp_xferstat) & FIFO_EMPTY) {
if (RDW_HARPOON((port + hp_intstat)) & BUS_FREE) {
return;
}
if (RD_HARPOON(port + hp_offsetctr) & (unsigned char)0x1F) {
break;
}
if (RDW_HARPOON((port + hp_intstat)) & RESET) {
return;
}
if ((RD_HARPOON(port + hp_scsisig) & SCSI_REQ)
|| (TimeOutLoop++ > 0x3000))
break;
}
sPhase = RD_HARPOON(port + hp_scsisig) & (SCSI_BSY | S_SCSI_PHZ);
if ((!(RD_HARPOON(port + hp_xferstat) & FIFO_EMPTY)) ||
(RD_HARPOON(port + hp_offsetctr) & (unsigned char)0x1F) ||
(sPhase == (SCSI_BSY | S_DATAO_PH)) ||
(sPhase == (SCSI_BSY | S_DATAI_PH))) {
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
if (!(currSCCB->Sccb_XferState & F_ALL_XFERRED)) {
if (currSCCB->Sccb_XferState & F_HOST_XFER_DIR) {
FPT_phaseDataIn(port, p_card);
}
else {
FPT_phaseDataOut(port, p_card);
}
} else {
FPT_sxfrp(port, p_card);
if (!(RDW_HARPOON((port + hp_intstat)) &
(BUS_FREE | ICMD_COMP | ITAR_DISC | RESET))) {
WRW_HARPOON((port + hp_intstat), AUTO_INT);
FPT_phaseDecode(port, p_card);
}
}
}
else {
WR_HARPOON(port + hp_portctrl_0, 0x00);
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_sinits
*
* Description: Setup SCCB manager fields in this SCCB.
*
*---------------------------------------------------------------------*/
static void FPT_sinits(struct sccb *p_sccb, unsigned char p_card)
{
struct sccb_mgr_tar_info *currTar_Info;
if ((p_sccb->TargID >= MAX_SCSI_TAR) || (p_sccb->Lun >= MAX_LUN)) {
return;
}
currTar_Info = &FPT_sccbMgrTbl[p_card][p_sccb->TargID];
p_sccb->Sccb_XferState = 0x00;
p_sccb->Sccb_XferCnt = p_sccb->DataLength;
if ((p_sccb->OperationCode == SCATTER_GATHER_COMMAND) ||
(p_sccb->OperationCode == RESIDUAL_SG_COMMAND)) {
p_sccb->Sccb_SGoffset = 0;
p_sccb->Sccb_XferState = F_SG_XFER;
p_sccb->Sccb_XferCnt = 0x00;
}
if (p_sccb->DataLength == 0x00)
p_sccb->Sccb_XferState |= F_ALL_XFERRED;
if (p_sccb->ControlByte & F_USE_CMD_Q) {
if ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) == TAG_Q_REJECT)
p_sccb->ControlByte &= ~F_USE_CMD_Q;
else
currTar_Info->TarStatus |= TAG_Q_TRYING;
}
/* For !single SCSI device in system & device allow Disconnect
or command is tag_q type then send Cmd with Disconnect Enable
else send Cmd with Disconnect Disable */
/*
if (((!(FPT_BL_Card[p_card].globalFlags & F_SINGLE_DEVICE)) &&
(currTar_Info->TarStatus & TAR_ALLOW_DISC)) ||
(currTar_Info->TarStatus & TAG_Q_TRYING)) {
*/
if ((currTar_Info->TarStatus & TAR_ALLOW_DISC) ||
(currTar_Info->TarStatus & TAG_Q_TRYING)) {
p_sccb->Sccb_idmsg =
(unsigned char)(SMIDENT | DISC_PRIV) | p_sccb->Lun;
}
else {
p_sccb->Sccb_idmsg = (unsigned char)SMIDENT | p_sccb->Lun;
}
p_sccb->HostStatus = 0x00;
p_sccb->TargetStatus = 0x00;
p_sccb->Sccb_tag = 0x00;
p_sccb->Sccb_MGRFlags = 0x00;
p_sccb->Sccb_sgseg = 0x00;
p_sccb->Sccb_ATC = 0x00;
p_sccb->Sccb_savedATC = 0x00;
/*
p_sccb->SccbVirtDataPtr = 0x00;
p_sccb->Sccb_forwardlink = NULL;
p_sccb->Sccb_backlink = NULL;
*/
p_sccb->Sccb_scsistat = BUS_FREE_ST;
p_sccb->SccbStatus = SCCB_IN_PROCESS;
p_sccb->Sccb_scsimsg = SMNO_OP;
}
/*---------------------------------------------------------------------
*
* Function: Phase Decode
*
* Description: Determine the phase and call the appropriate function.
*
*---------------------------------------------------------------------*/
static void FPT_phaseDecode(unsigned long p_port, unsigned char p_card)
{
unsigned char phase_ref;
void (*phase) (unsigned long, unsigned char);
DISABLE_AUTO(p_port);
phase_ref =
(unsigned char)(RD_HARPOON(p_port + hp_scsisig) & S_SCSI_PHZ);
phase = FPT_s_PhaseTbl[phase_ref];
(*phase) (p_port, p_card); /* Call the correct phase func */
}
/*---------------------------------------------------------------------
*
* Function: Data Out Phase
*
* Description: Start up both the BusMaster and Xbow.
*
*---------------------------------------------------------------------*/
static void FPT_phaseDataOut(unsigned long port, unsigned char p_card)
{
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB == NULL) {
return; /* Exit if No SCCB record */
}
currSCCB->Sccb_scsistat = DATA_OUT_ST;
currSCCB->Sccb_XferState &= ~(F_HOST_XFER_DIR | F_NO_DATA_YET);
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
WRW_HARPOON((port + hp_intstat), XFER_CNT_0);
WR_HARPOON(port + hp_autostart_0, (END_DATA + END_DATA_START));
FPT_dataXferProcessor(port, &FPT_BL_Card[p_card]);
if (currSCCB->Sccb_XferCnt == 0) {
if ((currSCCB->ControlByte & SCCB_DATA_XFER_OUT) &&
(currSCCB->HostStatus == SCCB_COMPLETE))
currSCCB->HostStatus = SCCB_DATA_OVER_RUN;
FPT_sxfrp(port, p_card);
if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
FPT_phaseDecode(port, p_card);
}
}
/*---------------------------------------------------------------------
*
* Function: Data In Phase
*
* Description: Startup the BusMaster and the XBOW.
*
*---------------------------------------------------------------------*/
static void FPT_phaseDataIn(unsigned long port, unsigned char p_card)
{
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB == NULL) {
return; /* Exit if No SCCB record */
}
currSCCB->Sccb_scsistat = DATA_IN_ST;
currSCCB->Sccb_XferState |= F_HOST_XFER_DIR;
currSCCB->Sccb_XferState &= ~F_NO_DATA_YET;
WR_HARPOON(port + hp_portctrl_0, SCSI_PORT);
WRW_HARPOON((port + hp_intstat), XFER_CNT_0);
WR_HARPOON(port + hp_autostart_0, (END_DATA + END_DATA_START));
FPT_dataXferProcessor(port, &FPT_BL_Card[p_card]);
if (currSCCB->Sccb_XferCnt == 0) {
if ((currSCCB->ControlByte & SCCB_DATA_XFER_IN) &&
(currSCCB->HostStatus == SCCB_COMPLETE))
currSCCB->HostStatus = SCCB_DATA_OVER_RUN;
FPT_sxfrp(port, p_card);
if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
FPT_phaseDecode(port, p_card);
}
}
/*---------------------------------------------------------------------
*
* Function: Command Phase
*
* Description: Load the CDB into the automation and start it up.
*
*---------------------------------------------------------------------*/
static void FPT_phaseCommand(unsigned long p_port, unsigned char p_card)
{
struct sccb *currSCCB;
unsigned long cdb_reg;
unsigned char i;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB->OperationCode == RESET_COMMAND) {
currSCCB->HostStatus = SCCB_PHASE_SEQUENCE_FAIL;
currSCCB->CdbLength = SIX_BYTE_CMD;
}
WR_HARPOON(p_port + hp_scsisig, 0x00);
ARAM_ACCESS(p_port);
cdb_reg = p_port + CMD_STRT;
for (i = 0; i < currSCCB->CdbLength; i++) {
if (currSCCB->OperationCode == RESET_COMMAND)
WRW_HARPOON(cdb_reg, (MPM_OP + ACOMMAND + 0x00));
else
WRW_HARPOON(cdb_reg,
(MPM_OP + ACOMMAND + currSCCB->Cdb[i]));
cdb_reg += 2;
}
if (currSCCB->CdbLength != TWELVE_BYTE_CMD)
WRW_HARPOON(cdb_reg, (BRH_OP + ALWAYS + NP));
WR_HARPOON(p_port + hp_portctrl_0, (SCSI_PORT));
currSCCB->Sccb_scsistat = COMMAND_ST;
WR_HARPOON(p_port + hp_autostart_3, (AUTO_IMMED | CMD_ONLY_STRT));
SGRAM_ACCESS(p_port);
}
/*---------------------------------------------------------------------
*
* Function: Status phase
*
* Description: Bring in the status and command complete message bytes
*
*---------------------------------------------------------------------*/
static void FPT_phaseStatus(unsigned long port, unsigned char p_card)
{
/* Start-up the automation to finish off this command and let the
isr handle the interrupt for command complete when it comes in.
We could wait here for the interrupt to be generated?
*/
WR_HARPOON(port + hp_scsisig, 0x00);
WR_HARPOON(port + hp_autostart_0, (AUTO_IMMED + END_DATA_START));
}
/*---------------------------------------------------------------------
*
* Function: Phase Message Out
*
* Description: Send out our message (if we have one) and handle whatever
* else is involed.
*
*---------------------------------------------------------------------*/
static void FPT_phaseMsgOut(unsigned long port, unsigned char p_card)
{
unsigned char message, scsiID;
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB != NULL) {
message = currSCCB->Sccb_scsimsg;
scsiID = currSCCB->TargID;
if (message == SMDEV_RESET) {
currTar_Info = &FPT_sccbMgrTbl[p_card][scsiID];
currTar_Info->TarSyncCtrl = 0;
FPT_sssyncv(port, scsiID, NARROW_SCSI, currTar_Info);
if (FPT_sccbMgrTbl[p_card][scsiID].
TarEEValue & EE_SYNC_MASK) {
FPT_sccbMgrTbl[p_card][scsiID].TarStatus &=
~TAR_SYNC_MASK;
}
if (FPT_sccbMgrTbl[p_card][scsiID].
TarEEValue & EE_WIDE_SCSI) {
FPT_sccbMgrTbl[p_card][scsiID].TarStatus &=
~TAR_WIDE_MASK;
}
FPT_queueFlushSccb(p_card, SCCB_COMPLETE);
FPT_SccbMgrTableInitTarget(p_card, scsiID);
} else if (currSCCB->Sccb_scsistat == ABORT_ST) {
currSCCB->HostStatus = SCCB_COMPLETE;
if (FPT_BL_Card[p_card].discQ_Tbl[currSCCB->Sccb_tag] !=
NULL) {
FPT_BL_Card[p_card].discQ_Tbl[currSCCB->
Sccb_tag] = NULL;
FPT_sccbMgrTbl[p_card][scsiID].TarTagQ_Cnt--;
}
}
else if (currSCCB->Sccb_scsistat < COMMAND_ST) {
if (message == SMNO_OP) {
currSCCB->Sccb_MGRFlags |= F_DEV_SELECTED;
FPT_ssel(port, p_card);
return;
}
} else {
if (message == SMABORT)
FPT_queueFlushSccb(p_card, SCCB_COMPLETE);
}
} else {
message = SMABORT;
}
WRW_HARPOON((port + hp_intstat), (BUS_FREE | PHASE | XFER_CNT_0));
WR_HARPOON(port + hp_portctrl_0, SCSI_BUS_EN);
WR_HARPOON(port + hp_scsidata_0, message);
WR_HARPOON(port + hp_scsisig, (SCSI_ACK + S_ILL_PH));
ACCEPT_MSG(port);
WR_HARPOON(port + hp_portctrl_0, 0x00);
if ((message == SMABORT) || (message == SMDEV_RESET) ||
(message == SMABORT_TAG)) {
while (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | PHASE))) {
}
if (RDW_HARPOON((port + hp_intstat)) & BUS_FREE) {
WRW_HARPOON((port + hp_intstat), BUS_FREE);
if (currSCCB != NULL) {
if ((FPT_BL_Card[p_card].
globalFlags & F_CONLUN_IO)
&&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING))
FPT_sccbMgrTbl[p_card][currSCCB->
TargID].
TarLUNBusy[currSCCB->Lun] = 0;
else
FPT_sccbMgrTbl[p_card][currSCCB->
TargID].
TarLUNBusy[0] = 0;
FPT_queueCmdComplete(&FPT_BL_Card[p_card],
currSCCB, p_card);
}
else {
FPT_BL_Card[p_card].globalFlags |=
F_NEW_SCCB_CMD;
}
}
else {
FPT_sxfrp(port, p_card);
}
}
else {
if (message == SMPARITY) {
currSCCB->Sccb_scsimsg = SMNO_OP;
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
} else {
FPT_sxfrp(port, p_card);
}
}
}
/*---------------------------------------------------------------------
*
* Function: Message In phase
*
* Description: Bring in the message and determine what to do with it.
*
*---------------------------------------------------------------------*/
static void FPT_phaseMsgIn(unsigned long port, unsigned char p_card)
{
unsigned char message;
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (FPT_BL_Card[p_card].globalFlags & F_HOST_XFER_ACT) {
FPT_phaseChkFifo(port, p_card);
}
message = RD_HARPOON(port + hp_scsidata_0);
if ((message == SMDISC) || (message == SMSAVE_DATA_PTR)) {
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + END_DATA_START));
}
else {
message = FPT_sfm(port, currSCCB);
if (message) {
FPT_sdecm(message, port, p_card);
} else {
if (currSCCB->Sccb_scsimsg != SMPARITY)
ACCEPT_MSG(port);
WR_HARPOON(port + hp_autostart_1,
(AUTO_IMMED + DISCONNECT_START));
}
}
}
/*---------------------------------------------------------------------
*
* Function: Illegal phase
*
* Description: Target switched to some illegal phase, so all we can do
* is report an error back to the host (if that is possible)
* and send an ABORT message to the misbehaving target.
*
*---------------------------------------------------------------------*/
static void FPT_phaseIllegal(unsigned long port, unsigned char p_card)
{
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
WR_HARPOON(port + hp_scsisig, RD_HARPOON(port + hp_scsisig));
if (currSCCB != NULL) {
currSCCB->HostStatus = SCCB_PHASE_SEQUENCE_FAIL;
currSCCB->Sccb_scsistat = ABORT_ST;
currSCCB->Sccb_scsimsg = SMABORT;
}
ACCEPT_MSG_ATN(port);
}
/*---------------------------------------------------------------------
*
* Function: Phase Check FIFO
*
* Description: Make sure data has been flushed from both FIFOs and abort
* the operations if necessary.
*
*---------------------------------------------------------------------*/
static void FPT_phaseChkFifo(unsigned long port, unsigned char p_card)
{
unsigned long xfercnt;
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB->Sccb_scsistat == DATA_IN_ST) {
while ((!(RD_HARPOON(port + hp_xferstat) & FIFO_EMPTY)) &&
(RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY)) {
}
if (!(RD_HARPOON(port + hp_xferstat) & FIFO_EMPTY)) {
currSCCB->Sccb_ATC += currSCCB->Sccb_XferCnt;
currSCCB->Sccb_XferCnt = 0;
if ((RDW_HARPOON((port + hp_intstat)) & PARITY) &&
(currSCCB->HostStatus == SCCB_COMPLETE)) {
currSCCB->HostStatus = SCCB_PARITY_ERR;
WRW_HARPOON((port + hp_intstat), PARITY);
}
FPT_hostDataXferAbort(port, p_card, currSCCB);
FPT_dataXferProcessor(port, &FPT_BL_Card[p_card]);
while ((!(RD_HARPOON(port + hp_xferstat) & FIFO_EMPTY))
&& (RD_HARPOON(port + hp_ext_status) &
BM_CMD_BUSY)) {
}
}
}
/*End Data In specific code. */
GET_XFER_CNT(port, xfercnt);
WR_HARPOON(port + hp_xfercnt_0, 0x00);
WR_HARPOON(port + hp_portctrl_0, 0x00);
currSCCB->Sccb_ATC += (currSCCB->Sccb_XferCnt - xfercnt);
currSCCB->Sccb_XferCnt = xfercnt;
if ((RDW_HARPOON((port + hp_intstat)) & PARITY) &&
(currSCCB->HostStatus == SCCB_COMPLETE)) {
currSCCB->HostStatus = SCCB_PARITY_ERR;
WRW_HARPOON((port + hp_intstat), PARITY);
}
FPT_hostDataXferAbort(port, p_card, currSCCB);
WR_HARPOON(port + hp_fifowrite, 0x00);
WR_HARPOON(port + hp_fiforead, 0x00);
WR_HARPOON(port + hp_xferstat, 0x00);
WRW_HARPOON((port + hp_intstat), XFER_CNT_0);
}
/*---------------------------------------------------------------------
*
* Function: Phase Bus Free
*
* Description: We just went bus free so figure out if it was
* because of command complete or from a disconnect.
*
*---------------------------------------------------------------------*/
static void FPT_phaseBusFree(unsigned long port, unsigned char p_card)
{
struct sccb *currSCCB;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB != NULL) {
DISABLE_AUTO(port);
if (currSCCB->OperationCode == RESET_COMMAND) {
if ((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[currSCCB->Lun] = 0;
else
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[0] = 0;
FPT_queueCmdComplete(&FPT_BL_Card[p_card], currSCCB,
p_card);
FPT_queueSearchSelect(&FPT_BL_Card[p_card], p_card);
}
else if (currSCCB->Sccb_scsistat == SELECT_SN_ST) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarStatus |=
(unsigned char)SYNC_SUPPORTED;
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarEEValue &=
~EE_SYNC_MASK;
}
else if (currSCCB->Sccb_scsistat == SELECT_WN_ST) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarStatus =
(FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & ~WIDE_ENABLED) | WIDE_NEGOCIATED;
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarEEValue &=
~EE_WIDE_SCSI;
}
else if (currSCCB->Sccb_scsistat == SELECT_Q_ST) {
/* Make sure this is not a phony BUS_FREE. If we were
reselected or if BUSY is NOT on then this is a
valid BUS FREE. SRR Wednesday, 5/10/1995. */
if ((!(RD_HARPOON(port + hp_scsisig) & SCSI_BSY)) ||
(RDW_HARPOON((port + hp_intstat)) & RSEL)) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus &= ~TAR_TAG_Q_MASK;
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus |= TAG_Q_REJECT;
}
else {
return;
}
}
else {
currSCCB->Sccb_scsistat = BUS_FREE_ST;
if (!currSCCB->HostStatus) {
currSCCB->HostStatus = SCCB_PHASE_SEQUENCE_FAIL;
}
if ((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[currSCCB->Lun] = 0;
else
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[0] = 0;
FPT_queueCmdComplete(&FPT_BL_Card[p_card], currSCCB,
p_card);
return;
}
FPT_BL_Card[p_card].globalFlags |= F_NEW_SCCB_CMD;
} /*end if !=null */
}
/*---------------------------------------------------------------------
*
* Function: Auto Load Default Map
*
* Description: Load the Automation RAM with the defualt map values.
*
*---------------------------------------------------------------------*/
static void FPT_autoLoadDefaultMap(unsigned long p_port)
{
unsigned long map_addr;
ARAM_ACCESS(p_port);
map_addr = p_port + hp_aramBase;
WRW_HARPOON(map_addr, (MPM_OP + AMSG_OUT + 0xC0)); /*ID MESSAGE */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + AMSG_OUT + 0x20)); /*SIMPLE TAG QUEUEING MSG */
map_addr += 2;
WRW_HARPOON(map_addr, RAT_OP); /*RESET ATTENTION */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + AMSG_OUT + 0x00)); /*TAG ID MSG */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 0 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 1 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 2 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 3 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 4 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 5 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 6 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 7 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 8 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 9 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 10 */
map_addr += 2;
WRW_HARPOON(map_addr, (MPM_OP + ACOMMAND + 0x00)); /*CDB BYTE 11 */
map_addr += 2;
WRW_HARPOON(map_addr, (CPE_OP + ADATA_OUT + DINT)); /*JUMP IF DATA OUT */
map_addr += 2;
WRW_HARPOON(map_addr, (TCB_OP + FIFO_0 + DI)); /*JUMP IF NO DATA IN FIFO */
map_addr += 2; /*This means AYNC DATA IN */
WRW_HARPOON(map_addr, (SSI_OP + SSI_IDO_STRT)); /*STOP AND INTERRUPT */
map_addr += 2;
WRW_HARPOON(map_addr, (CPE_OP + ADATA_IN + DINT)); /*JUMP IF NOT DATA IN PHZ */
map_addr += 2;
WRW_HARPOON(map_addr, (CPN_OP + AMSG_IN + ST)); /*IF NOT MSG IN CHECK 4 DATA IN */
map_addr += 2;
WRW_HARPOON(map_addr, (CRD_OP + SDATA + 0x02)); /*SAVE DATA PTR MSG? */
map_addr += 2;
WRW_HARPOON(map_addr, (BRH_OP + NOT_EQ + DC)); /*GO CHECK FOR DISCONNECT MSG */
map_addr += 2;
WRW_HARPOON(map_addr, (MRR_OP + SDATA + D_AR1)); /*SAVE DATA PTRS MSG */
map_addr += 2;
WRW_HARPOON(map_addr, (CPN_OP + AMSG_IN + ST)); /*IF NOT MSG IN CHECK DATA IN */
map_addr += 2;
WRW_HARPOON(map_addr, (CRD_OP + SDATA + 0x04)); /*DISCONNECT MSG? */
map_addr += 2;
WRW_HARPOON(map_addr, (BRH_OP + NOT_EQ + UNKNWN)); /*UKNKNOWN MSG */
map_addr += 2;
WRW_HARPOON(map_addr, (MRR_OP + SDATA + D_BUCKET)); /*XFER DISCONNECT MSG */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_ITAR_DISC)); /*STOP AND INTERRUPT */
map_addr += 2;
WRW_HARPOON(map_addr, (CPN_OP + ASTATUS + UNKNWN)); /*JUMP IF NOT STATUS PHZ. */
map_addr += 2;
WRW_HARPOON(map_addr, (MRR_OP + SDATA + D_AR0)); /*GET STATUS BYTE */
map_addr += 2;
WRW_HARPOON(map_addr, (CPN_OP + AMSG_IN + CC)); /*ERROR IF NOT MSG IN PHZ */
map_addr += 2;
WRW_HARPOON(map_addr, (CRD_OP + SDATA + 0x00)); /*CHECK FOR CMD COMPLETE MSG. */
map_addr += 2;
WRW_HARPOON(map_addr, (BRH_OP + NOT_EQ + CC)); /*ERROR IF NOT CMD COMPLETE MSG. */
map_addr += 2;
WRW_HARPOON(map_addr, (MRR_OP + SDATA + D_BUCKET)); /*GET CMD COMPLETE MSG */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_ICMD_COMP)); /*END OF COMMAND */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_IUNKWN)); /*RECEIVED UNKNOWN MSG BYTE */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_INO_CC)); /*NO COMMAND COMPLETE AFTER STATUS */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_ITICKLE)); /*BIOS Tickled the Mgr */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_IRFAIL)); /*EXPECTED ID/TAG MESSAGES AND */
map_addr += 2; /* DIDN'T GET ONE */
WRW_HARPOON(map_addr, (CRR_OP + AR3 + S_IDREG)); /* comp SCSI SEL ID & AR3 */
map_addr += 2;
WRW_HARPOON(map_addr, (BRH_OP + EQUAL + 0x00)); /*SEL ID OK then Conti. */
map_addr += 2;
WRW_HARPOON(map_addr, (SSI_OP + SSI_INO_CC)); /*NO COMMAND COMPLETE AFTER STATUS */
SGRAM_ACCESS(p_port);
}
/*---------------------------------------------------------------------
*
* Function: Auto Command Complete
*
* Description: Post command back to host and find another command
* to execute.
*
*---------------------------------------------------------------------*/
static void FPT_autoCmdCmplt(unsigned long p_port, unsigned char p_card)
{
struct sccb *currSCCB;
unsigned char status_byte;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
status_byte = RD_HARPOON(p_port + hp_gp_reg_0);
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarLUN_CA = 0;
if (status_byte != SSGOOD) {
if (status_byte == SSQ_FULL) {
if (((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[currSCCB->Lun] = 1;
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
LunDiscQ_Idx[currSCCB->Lun]] =
NULL;
} else {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[0] = 1;
if (currSCCB->Sccb_tag) {
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].discQ_Tbl[currSCCB->
Sccb_tag]
= NULL;
} else {
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
LunDiscQ_Idx[0]] = NULL;
}
}
currSCCB->Sccb_MGRFlags |= F_STATUSLOADED;
FPT_queueSelectFail(&FPT_BL_Card[p_card], p_card);
return;
}
if (currSCCB->Sccb_scsistat == SELECT_SN_ST) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarStatus |=
(unsigned char)SYNC_SUPPORTED;
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarEEValue &=
~EE_SYNC_MASK;
FPT_BL_Card[p_card].globalFlags |= F_NEW_SCCB_CMD;
if (((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[currSCCB->Lun] = 1;
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
LunDiscQ_Idx[currSCCB->Lun]] =
NULL;
} else {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[0] = 1;
if (currSCCB->Sccb_tag) {
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].discQ_Tbl[currSCCB->
Sccb_tag]
= NULL;
} else {
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
LunDiscQ_Idx[0]] = NULL;
}
}
return;
}
if (currSCCB->Sccb_scsistat == SELECT_WN_ST) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarStatus =
(FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & ~WIDE_ENABLED) | WIDE_NEGOCIATED;
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarEEValue &=
~EE_WIDE_SCSI;
FPT_BL_Card[p_card].globalFlags |= F_NEW_SCCB_CMD;
if (((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[currSCCB->Lun] = 1;
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
LunDiscQ_Idx[currSCCB->Lun]] =
NULL;
} else {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUNBusy[0] = 1;
if (currSCCB->Sccb_tag) {
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].discQ_Tbl[currSCCB->
Sccb_tag]
= NULL;
} else {
if (FPT_BL_Card[p_card].discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
LunDiscQ_Idx[0]] = NULL;
}
}
return;
}
if (status_byte == SSCHECK) {
if (FPT_BL_Card[p_card].globalFlags & F_DO_RENEGO) {
if (FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarEEValue & EE_SYNC_MASK) {
FPT_sccbMgrTbl[p_card][currSCCB->
TargID].
TarStatus &= ~TAR_SYNC_MASK;
}
if (FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarEEValue & EE_WIDE_SCSI) {
FPT_sccbMgrTbl[p_card][currSCCB->
TargID].
TarStatus &= ~TAR_WIDE_MASK;
}
}
}
if (!(currSCCB->Sccb_XferState & F_AUTO_SENSE)) {
currSCCB->SccbStatus = SCCB_ERROR;
currSCCB->TargetStatus = status_byte;
if (status_byte == SSCHECK) {
FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarLUN_CA = 1;
if (currSCCB->RequestSenseLength !=
NO_AUTO_REQUEST_SENSE) {
if (currSCCB->RequestSenseLength == 0)
currSCCB->RequestSenseLength =
14;
FPT_ssenss(&FPT_BL_Card[p_card]);
FPT_BL_Card[p_card].globalFlags |=
F_NEW_SCCB_CMD;
if (((FPT_BL_Card[p_card].
globalFlags & F_CONLUN_IO)
&&
((FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING))) {
FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
TarLUNBusy[currSCCB->Lun] =
1;
if (FPT_BL_Card[p_card].
discQCount != 0)
FPT_BL_Card[p_card].
discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[FPT_sccbMgrTbl
[p_card]
[currSCCB->
TargID].
LunDiscQ_Idx
[currSCCB->Lun]] =
NULL;
} else {
FPT_sccbMgrTbl[p_card]
[currSCCB->TargID].
TarLUNBusy[0] = 1;
if (currSCCB->Sccb_tag) {
if (FPT_BL_Card[p_card].
discQCount != 0)
FPT_BL_Card
[p_card].
discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl[currSCCB->
Sccb_tag]
= NULL;
} else {
if (FPT_BL_Card[p_card].
discQCount != 0)
FPT_BL_Card
[p_card].
discQCount--;
FPT_BL_Card[p_card].
discQ_Tbl
[FPT_sccbMgrTbl
[p_card][currSCCB->
TargID].
LunDiscQ_Idx[0]] =
NULL;
}
}
return;
}
}
}
}
if ((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((FPT_sccbMgrTbl[p_card][currSCCB->TargID].
TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarLUNBusy[currSCCB->
Lun] = 0;
else
FPT_sccbMgrTbl[p_card][currSCCB->TargID].TarLUNBusy[0] = 0;
FPT_queueCmdComplete(&FPT_BL_Card[p_card], currSCCB, p_card);
}
#define SHORT_WAIT 0x0000000F
#define LONG_WAIT 0x0000FFFFL
/*---------------------------------------------------------------------
*
* Function: Data Transfer Processor
*
* Description: This routine performs two tasks.
* (1) Start data transfer by calling HOST_DATA_XFER_START
* function. Once data transfer is started, (2) Depends
* on the type of data transfer mode Scatter/Gather mode
* or NON Scatter/Gather mode. In NON Scatter/Gather mode,
* this routine checks Sccb_MGRFlag (F_HOST_XFER_ACT bit) for
* data transfer done. In Scatter/Gather mode, this routine
* checks bus master command complete and dual rank busy
* bit to keep chaining SC transfer command. Similarly,
* in Scatter/Gather mode, it checks Sccb_MGRFlag
* (F_HOST_XFER_ACT bit) for data transfer done.
*
*---------------------------------------------------------------------*/
static void FPT_dataXferProcessor(unsigned long port,
struct sccb_card *pCurrCard)
{
struct sccb *currSCCB;
currSCCB = pCurrCard->currentSCCB;
if (currSCCB->Sccb_XferState & F_SG_XFER) {
if (pCurrCard->globalFlags & F_HOST_XFER_ACT)
{
currSCCB->Sccb_sgseg += (unsigned char)SG_BUF_CNT;
currSCCB->Sccb_SGoffset = 0x00;
}
pCurrCard->globalFlags |= F_HOST_XFER_ACT;
FPT_busMstrSGDataXferStart(port, currSCCB);
}
else {
if (!(pCurrCard->globalFlags & F_HOST_XFER_ACT)) {
pCurrCard->globalFlags |= F_HOST_XFER_ACT;
FPT_busMstrDataXferStart(port, currSCCB);
}
}
}
/*---------------------------------------------------------------------
*
* Function: BusMaster Scatter Gather Data Transfer Start
*
* Description:
*
*---------------------------------------------------------------------*/
static void FPT_busMstrSGDataXferStart(unsigned long p_port,
struct sccb *pcurrSCCB)
{
unsigned long count, addr, tmpSGCnt;
unsigned int sg_index;
unsigned char sg_count, i;
unsigned long reg_offset;
if (pcurrSCCB->Sccb_XferState & F_HOST_XFER_DIR) {
count = ((unsigned long)HOST_RD_CMD) << 24;
}
else {
count = ((unsigned long)HOST_WRT_CMD) << 24;
}
sg_count = 0;
tmpSGCnt = 0;
sg_index = pcurrSCCB->Sccb_sgseg;
reg_offset = hp_aramBase;
i = (unsigned char)(RD_HARPOON(p_port + hp_page_ctrl) &
~(SGRAM_ARAM | SCATTER_EN));
WR_HARPOON(p_port + hp_page_ctrl, i);
while ((sg_count < (unsigned char)SG_BUF_CNT) &&
((unsigned long)(sg_index * (unsigned int)SG_ELEMENT_SIZE) <
pcurrSCCB->DataLength)) {
tmpSGCnt += *(((unsigned long *)pcurrSCCB->DataPointer) +
(sg_index * 2));
count |= *(((unsigned long *)pcurrSCCB->DataPointer) +
(sg_index * 2));
addr = *(((unsigned long *)pcurrSCCB->DataPointer) +
((sg_index * 2) + 1));
if ((!sg_count) && (pcurrSCCB->Sccb_SGoffset)) {
addr +=
((count & 0x00FFFFFFL) - pcurrSCCB->Sccb_SGoffset);
count =
(count & 0xFF000000L) | pcurrSCCB->Sccb_SGoffset;
tmpSGCnt = count & 0x00FFFFFFL;
}
WR_HARP32(p_port, reg_offset, addr);
reg_offset += 4;
WR_HARP32(p_port, reg_offset, count);
reg_offset += 4;
count &= 0xFF000000L;
sg_index++;
sg_count++;
} /*End While */
pcurrSCCB->Sccb_XferCnt = tmpSGCnt;
WR_HARPOON(p_port + hp_sg_addr, (sg_count << 4));
if (pcurrSCCB->Sccb_XferState & F_HOST_XFER_DIR) {
WR_HARP32(p_port, hp_xfercnt_0, tmpSGCnt);
WR_HARPOON(p_port + hp_portctrl_0,
(DMA_PORT | SCSI_PORT | SCSI_INBIT));
WR_HARPOON(p_port + hp_scsisig, S_DATAI_PH);
}
else {
if ((!(RD_HARPOON(p_port + hp_synctarg_0) & NARROW_SCSI)) &&
(tmpSGCnt & 0x000000001)) {
pcurrSCCB->Sccb_XferState |= F_ODD_BALL_CNT;
tmpSGCnt--;
}
WR_HARP32(p_port, hp_xfercnt_0, tmpSGCnt);
WR_HARPOON(p_port + hp_portctrl_0,
(SCSI_PORT | DMA_PORT | DMA_RD));
WR_HARPOON(p_port + hp_scsisig, S_DATAO_PH);
}
WR_HARPOON(p_port + hp_page_ctrl, (unsigned char)(i | SCATTER_EN));
}
/*---------------------------------------------------------------------
*
* Function: BusMaster Data Transfer Start
*
* Description:
*
*---------------------------------------------------------------------*/
static void FPT_busMstrDataXferStart(unsigned long p_port,
struct sccb *pcurrSCCB)
{
unsigned long addr, count;
if (!(pcurrSCCB->Sccb_XferState & F_AUTO_SENSE)) {
count = pcurrSCCB->Sccb_XferCnt;
addr =
(unsigned long)pcurrSCCB->DataPointer + pcurrSCCB->Sccb_ATC;
}
else {
addr = pcurrSCCB->SensePointer;
count = pcurrSCCB->RequestSenseLength;
}
HP_SETUP_ADDR_CNT(p_port, addr, count);
if (pcurrSCCB->Sccb_XferState & F_HOST_XFER_DIR) {
WR_HARPOON(p_port + hp_portctrl_0,
(DMA_PORT | SCSI_PORT | SCSI_INBIT));
WR_HARPOON(p_port + hp_scsisig, S_DATAI_PH);
WR_HARPOON(p_port + hp_xfer_cmd,
(XFER_DMA_HOST | XFER_HOST_AUTO | XFER_DMA_8BIT));
}
else {
WR_HARPOON(p_port + hp_portctrl_0,
(SCSI_PORT | DMA_PORT | DMA_RD));
WR_HARPOON(p_port + hp_scsisig, S_DATAO_PH);
WR_HARPOON(p_port + hp_xfer_cmd,
(XFER_HOST_DMA | XFER_HOST_AUTO | XFER_DMA_8BIT));
}
}
/*---------------------------------------------------------------------
*
* Function: BusMaster Timeout Handler
*
* Description: This function is called after a bus master command busy time
* out is detected. This routines issue halt state machine
* with a software time out for command busy. If command busy
* is still asserted at the end of the time out, it issues
* hard abort with another software time out. It hard abort
* command busy is also time out, it'll just give up.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_busMstrTimeOut(unsigned long p_port)
{
unsigned long timeout;
timeout = LONG_WAIT;
WR_HARPOON(p_port + hp_sys_ctrl, HALT_MACH);
while ((!(RD_HARPOON(p_port + hp_ext_status) & CMD_ABORTED))
&& timeout--) {
}
if (RD_HARPOON(p_port + hp_ext_status) & BM_CMD_BUSY) {
WR_HARPOON(p_port + hp_sys_ctrl, HARD_ABORT);
timeout = LONG_WAIT;
while ((RD_HARPOON(p_port + hp_ext_status) & BM_CMD_BUSY)
&& timeout--) {
}
}
RD_HARPOON(p_port + hp_int_status); /*Clear command complete */
if (RD_HARPOON(p_port + hp_ext_status) & BM_CMD_BUSY) {
return 1;
}
else {
return 0;
}
}
/*---------------------------------------------------------------------
*
* Function: Host Data Transfer Abort
*
* Description: Abort any in progress transfer.
*
*---------------------------------------------------------------------*/
static void FPT_hostDataXferAbort(unsigned long port, unsigned char p_card,
struct sccb *pCurrSCCB)
{
unsigned long timeout;
unsigned long remain_cnt;
unsigned int sg_ptr;
FPT_BL_Card[p_card].globalFlags &= ~F_HOST_XFER_ACT;
if (pCurrSCCB->Sccb_XferState & F_AUTO_SENSE) {
if (!(RD_HARPOON(port + hp_int_status) & INT_CMD_COMPL)) {
WR_HARPOON(port + hp_bm_ctrl,
(RD_HARPOON(port + hp_bm_ctrl) |
FLUSH_XFER_CNTR));
timeout = LONG_WAIT;
while ((RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY)
&& timeout--) {
}
WR_HARPOON(port + hp_bm_ctrl,
(RD_HARPOON(port + hp_bm_ctrl) &
~FLUSH_XFER_CNTR));
if (RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY) {
if (FPT_busMstrTimeOut(port)) {
if (pCurrSCCB->HostStatus == 0x00)
pCurrSCCB->HostStatus =
SCCB_BM_ERR;
}
if (RD_HARPOON(port + hp_int_status) &
INT_EXT_STATUS)
if (RD_HARPOON(port + hp_ext_status) &
BAD_EXT_STATUS)
if (pCurrSCCB->HostStatus ==
0x00)
{
pCurrSCCB->HostStatus =
SCCB_BM_ERR;
}
}
}
}
else if (pCurrSCCB->Sccb_XferCnt) {
if (pCurrSCCB->Sccb_XferState & F_SG_XFER) {
WR_HARPOON(port + hp_page_ctrl,
(RD_HARPOON(port + hp_page_ctrl) &
~SCATTER_EN));
WR_HARPOON(port + hp_sg_addr, 0x00);
sg_ptr = pCurrSCCB->Sccb_sgseg + SG_BUF_CNT;
if (sg_ptr >
(unsigned int)(pCurrSCCB->DataLength /
SG_ELEMENT_SIZE)) {
sg_ptr =
(unsigned int)(pCurrSCCB->DataLength /
SG_ELEMENT_SIZE);
}
remain_cnt = pCurrSCCB->Sccb_XferCnt;
while (remain_cnt < 0x01000000L) {
sg_ptr--;
if (remain_cnt >
(unsigned
long)(*(((unsigned long *)pCurrSCCB->
DataPointer) + (sg_ptr * 2)))) {
remain_cnt -=
(unsigned
long)(*(((unsigned long *)
pCurrSCCB->DataPointer) +
(sg_ptr * 2)));
}
else {
break;
}
}
if (remain_cnt < 0x01000000L) {
pCurrSCCB->Sccb_SGoffset = remain_cnt;
pCurrSCCB->Sccb_sgseg = (unsigned short)sg_ptr;
if ((unsigned long)(sg_ptr * SG_ELEMENT_SIZE) ==
pCurrSCCB->DataLength && (remain_cnt == 0))
pCurrSCCB->Sccb_XferState |=
F_ALL_XFERRED;
}
else {
if (pCurrSCCB->HostStatus == 0x00) {
pCurrSCCB->HostStatus =
SCCB_GROSS_FW_ERR;
}
}
}
if (!(pCurrSCCB->Sccb_XferState & F_HOST_XFER_DIR)) {
if (RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY) {
FPT_busMstrTimeOut(port);
}
else {
if (RD_HARPOON(port + hp_int_status) &
INT_EXT_STATUS) {
if (RD_HARPOON(port + hp_ext_status) &
BAD_EXT_STATUS) {
if (pCurrSCCB->HostStatus ==
0x00) {
pCurrSCCB->HostStatus =
SCCB_BM_ERR;
}
}
}
}
}
else {
if ((RD_HARPOON(port + hp_fifo_cnt)) >= BM_THRESHOLD) {
timeout = SHORT_WAIT;
while ((RD_HARPOON(port + hp_ext_status) &
BM_CMD_BUSY)
&& ((RD_HARPOON(port + hp_fifo_cnt)) >=
BM_THRESHOLD) && timeout--) {
}
}
if (RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY) {
WR_HARPOON(port + hp_bm_ctrl,
(RD_HARPOON(port + hp_bm_ctrl) |
FLUSH_XFER_CNTR));
timeout = LONG_WAIT;
while ((RD_HARPOON(port + hp_ext_status) &
BM_CMD_BUSY) && timeout--) {
}
WR_HARPOON(port + hp_bm_ctrl,
(RD_HARPOON(port + hp_bm_ctrl) &
~FLUSH_XFER_CNTR));
if (RD_HARPOON(port + hp_ext_status) &
BM_CMD_BUSY) {
if (pCurrSCCB->HostStatus == 0x00) {
pCurrSCCB->HostStatus =
SCCB_BM_ERR;
}
FPT_busMstrTimeOut(port);
}
}
if (RD_HARPOON(port + hp_int_status) & INT_EXT_STATUS) {
if (RD_HARPOON(port + hp_ext_status) &
BAD_EXT_STATUS) {
if (pCurrSCCB->HostStatus == 0x00) {
pCurrSCCB->HostStatus =
SCCB_BM_ERR;
}
}
}
}
}
else {
if (RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY) {
timeout = LONG_WAIT;
while ((RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY)
&& timeout--) {
}
if (RD_HARPOON(port + hp_ext_status) & BM_CMD_BUSY) {
if (pCurrSCCB->HostStatus == 0x00) {
pCurrSCCB->HostStatus = SCCB_BM_ERR;
}
FPT_busMstrTimeOut(port);
}
}
if (RD_HARPOON(port + hp_int_status) & INT_EXT_STATUS) {
if (RD_HARPOON(port + hp_ext_status) & BAD_EXT_STATUS) {
if (pCurrSCCB->HostStatus == 0x00) {
pCurrSCCB->HostStatus = SCCB_BM_ERR;
}
}
}
if (pCurrSCCB->Sccb_XferState & F_SG_XFER) {
WR_HARPOON(port + hp_page_ctrl,
(RD_HARPOON(port + hp_page_ctrl) &
~SCATTER_EN));
WR_HARPOON(port + hp_sg_addr, 0x00);
pCurrSCCB->Sccb_sgseg += SG_BUF_CNT;
pCurrSCCB->Sccb_SGoffset = 0x00;
if ((unsigned long)(pCurrSCCB->Sccb_sgseg *
SG_ELEMENT_SIZE) >=
pCurrSCCB->DataLength) {
pCurrSCCB->Sccb_XferState |= F_ALL_XFERRED;
pCurrSCCB->Sccb_sgseg =
(unsigned short)(pCurrSCCB->DataLength /
SG_ELEMENT_SIZE);
}
}
else {
if (!(pCurrSCCB->Sccb_XferState & F_AUTO_SENSE))
pCurrSCCB->Sccb_XferState |= F_ALL_XFERRED;
}
}
WR_HARPOON(port + hp_int_mask, (INT_CMD_COMPL | SCSI_INTERRUPT));
}
/*---------------------------------------------------------------------
*
* Function: Host Data Transfer Restart
*
* Description: Reset the available count due to a restore data
* pointers message.
*
*---------------------------------------------------------------------*/
static void FPT_hostDataXferRestart(struct sccb *currSCCB)
{
unsigned long data_count;
unsigned int sg_index;
unsigned long *sg_ptr;
if (currSCCB->Sccb_XferState & F_SG_XFER) {
currSCCB->Sccb_XferCnt = 0;
sg_index = 0xffff; /*Index by long words into sg list. */
data_count = 0; /*Running count of SG xfer counts. */
sg_ptr = (unsigned long *)currSCCB->DataPointer;
while (data_count < currSCCB->Sccb_ATC) {
sg_index++;
data_count += *(sg_ptr + (sg_index * 2));
}
if (data_count == currSCCB->Sccb_ATC) {
currSCCB->Sccb_SGoffset = 0;
sg_index++;
}
else {
currSCCB->Sccb_SGoffset =
data_count - currSCCB->Sccb_ATC;
}
currSCCB->Sccb_sgseg = (unsigned short)sg_index;
}
else {
currSCCB->Sccb_XferCnt =
currSCCB->DataLength - currSCCB->Sccb_ATC;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_scini
*
* Description: Setup all data structures necessary for SCAM selection.
*
*---------------------------------------------------------------------*/
static void FPT_scini(unsigned char p_card, unsigned char p_our_id,
unsigned char p_power_up)
{
unsigned char loser, assigned_id;
unsigned long p_port;
unsigned char i, k, ScamFlg;
struct sccb_card *currCard;
struct nvram_info *pCurrNvRam;
currCard = &FPT_BL_Card[p_card];
p_port = currCard->ioPort;
pCurrNvRam = currCard->pNvRamInfo;
if (pCurrNvRam) {
ScamFlg = pCurrNvRam->niScamConf;
i = pCurrNvRam->niSysConf;
} else {
ScamFlg =
(unsigned char)FPT_utilEERead(p_port, SCAM_CONFIG / 2);
i = (unsigned
char)(FPT_utilEERead(p_port, (SYSTEM_CONFIG / 2)));
}
if (!(i & 0x02)) /* check if reset bus in AutoSCSI parameter set */
return;
FPT_inisci(p_card, p_port, p_our_id);
/* Force to wait 1 sec after SCSI bus reset. Some SCAM device FW
too slow to return to SCAM selection */
/* if (p_power_up)
FPT_Wait1Second(p_port);
else
FPT_Wait(p_port, TO_250ms); */
FPT_Wait1Second(p_port);
if ((ScamFlg & SCAM_ENABLED) && (ScamFlg & SCAM_LEVEL2)) {
while (!(FPT_scarb(p_port, INIT_SELTD))) {
}
FPT_scsel(p_port);
do {
FPT_scxferc(p_port, SYNC_PTRN);
FPT_scxferc(p_port, DOM_MSTR);
loser =
FPT_scsendi(p_port,
&FPT_scamInfo[p_our_id].id_string[0]);
} while (loser == 0xFF);
FPT_scbusf(p_port);
if ((p_power_up) && (!loser)) {
FPT_sresb(p_port, p_card);
FPT_Wait(p_port, TO_250ms);
while (!(FPT_scarb(p_port, INIT_SELTD))) {
}
FPT_scsel(p_port);
do {
FPT_scxferc(p_port, SYNC_PTRN);
FPT_scxferc(p_port, DOM_MSTR);
loser =
FPT_scsendi(p_port,
&FPT_scamInfo[p_our_id].
id_string[0]);
} while (loser == 0xFF);
FPT_scbusf(p_port);
}
}
else {
loser = 0;
}
if (!loser) {
FPT_scamInfo[p_our_id].state = ID_ASSIGNED;
if (ScamFlg & SCAM_ENABLED) {
for (i = 0; i < MAX_SCSI_TAR; i++) {
if ((FPT_scamInfo[i].state == ID_UNASSIGNED) ||
(FPT_scamInfo[i].state == ID_UNUSED)) {
if (FPT_scsell(p_port, i)) {
FPT_scamInfo[i].state = LEGACY;
if ((FPT_scamInfo[i].
id_string[0] != 0xFF)
|| (FPT_scamInfo[i].
id_string[1] != 0xFA)) {
FPT_scamInfo[i].
id_string[0] = 0xFF;
FPT_scamInfo[i].
id_string[1] = 0xFA;
if (pCurrNvRam == NULL)
currCard->
globalFlags
|=
F_UPDATE_EEPROM;
}
}
}
}
FPT_sresb(p_port, p_card);
FPT_Wait1Second(p_port);
while (!(FPT_scarb(p_port, INIT_SELTD))) {
}
FPT_scsel(p_port);
FPT_scasid(p_card, p_port);
}
}
else if ((loser) && (ScamFlg & SCAM_ENABLED)) {
FPT_scamInfo[p_our_id].id_string[0] = SLV_TYPE_CODE0;
assigned_id = 0;
FPT_scwtsel(p_port);
do {
while (FPT_scxferc(p_port, 0x00) != SYNC_PTRN) {
}
i = FPT_scxferc(p_port, 0x00);
if (i == ASSIGN_ID) {
if (!
(FPT_scsendi
(p_port,
&FPT_scamInfo[p_our_id].id_string[0]))) {
i = FPT_scxferc(p_port, 0x00);
if (FPT_scvalq(i)) {
k = FPT_scxferc(p_port, 0x00);
if (FPT_scvalq(k)) {
currCard->ourId =
((unsigned char)(i
<<
3)
+
(k &
(unsigned char)7))
& (unsigned char)
0x3F;
FPT_inisci(p_card,
p_port,
p_our_id);
FPT_scamInfo[currCard->
ourId].
state = ID_ASSIGNED;
FPT_scamInfo[currCard->
ourId].
id_string[0]
= SLV_TYPE_CODE0;
assigned_id = 1;
}
}
}
}
else if (i == SET_P_FLAG) {
if (!(FPT_scsendi(p_port,
&FPT_scamInfo[p_our_id].
id_string[0])))
FPT_scamInfo[p_our_id].id_string[0] |=
0x80;
}
} while (!assigned_id);
while (FPT_scxferc(p_port, 0x00) != CFG_CMPLT) {
}
}
if (ScamFlg & SCAM_ENABLED) {
FPT_scbusf(p_port);
if (currCard->globalFlags & F_UPDATE_EEPROM) {
FPT_scsavdi(p_card, p_port);
currCard->globalFlags &= ~F_UPDATE_EEPROM;
}
}
/*
for (i=0,k=0; i < MAX_SCSI_TAR; i++)
{
if ((FPT_scamInfo[i].state == ID_ASSIGNED) ||
(FPT_scamInfo[i].state == LEGACY))
k++;
}
if (k==2)
currCard->globalFlags |= F_SINGLE_DEVICE;
else
currCard->globalFlags &= ~F_SINGLE_DEVICE;
*/
}
/*---------------------------------------------------------------------
*
* Function: FPT_scarb
*
* Description: Gain control of the bus and wait SCAM select time (250ms)
*
*---------------------------------------------------------------------*/
static int FPT_scarb(unsigned long p_port, unsigned char p_sel_type)
{
if (p_sel_type == INIT_SELTD) {
while (RD_HARPOON(p_port + hp_scsisig) & (SCSI_SEL | SCSI_BSY)) {
}
if (RD_HARPOON(p_port + hp_scsisig) & SCSI_SEL)
return 0;
if (RD_HARPOON(p_port + hp_scsidata_0) != 00)
return 0;
WR_HARPOON(p_port + hp_scsisig,
(RD_HARPOON(p_port + hp_scsisig) | SCSI_BSY));
if (RD_HARPOON(p_port + hp_scsisig) & SCSI_SEL) {
WR_HARPOON(p_port + hp_scsisig,
(RD_HARPOON(p_port + hp_scsisig) &
~SCSI_BSY));
return 0;
}
WR_HARPOON(p_port + hp_scsisig,
(RD_HARPOON(p_port + hp_scsisig) | SCSI_SEL));
if (RD_HARPOON(p_port + hp_scsidata_0) != 00) {
WR_HARPOON(p_port + hp_scsisig,
(RD_HARPOON(p_port + hp_scsisig) &
~(SCSI_BSY | SCSI_SEL)));
return 0;
}
}
WR_HARPOON(p_port + hp_clkctrl_0, (RD_HARPOON(p_port + hp_clkctrl_0)
& ~ACTdeassert));
WR_HARPOON(p_port + hp_scsireset, SCAM_EN);
WR_HARPOON(p_port + hp_scsidata_0, 0x00);
WR_HARPOON(p_port + hp_scsidata_1, 0x00);
WR_HARPOON(p_port + hp_portctrl_0, SCSI_BUS_EN);
WR_HARPOON(p_port + hp_scsisig,
(RD_HARPOON(p_port + hp_scsisig) | SCSI_MSG));
WR_HARPOON(p_port + hp_scsisig, (RD_HARPOON(p_port + hp_scsisig)
& ~SCSI_BSY));
FPT_Wait(p_port, TO_250ms);
return 1;
}
/*---------------------------------------------------------------------
*
* Function: FPT_scbusf
*
* Description: Release the SCSI bus and disable SCAM selection.
*
*---------------------------------------------------------------------*/
static void FPT_scbusf(unsigned long p_port)
{
WR_HARPOON(p_port + hp_page_ctrl,
(RD_HARPOON(p_port + hp_page_ctrl) | G_INT_DISABLE));
WR_HARPOON(p_port + hp_scsidata_0, 0x00);
WR_HARPOON(p_port + hp_portctrl_0, (RD_HARPOON(p_port + hp_portctrl_0)
& ~SCSI_BUS_EN));
WR_HARPOON(p_port + hp_scsisig, 0x00);
WR_HARPOON(p_port + hp_scsireset, (RD_HARPOON(p_port + hp_scsireset)
& ~SCAM_EN));
WR_HARPOON(p_port + hp_clkctrl_0, (RD_HARPOON(p_port + hp_clkctrl_0)
| ACTdeassert));
WRW_HARPOON((p_port + hp_intstat), (BUS_FREE | AUTO_INT | SCAM_SEL));
WR_HARPOON(p_port + hp_page_ctrl,
(RD_HARPOON(p_port + hp_page_ctrl) & ~G_INT_DISABLE));
}
/*---------------------------------------------------------------------
*
* Function: FPT_scasid
*
* Description: Assign an ID to all the SCAM devices.
*
*---------------------------------------------------------------------*/
static void FPT_scasid(unsigned char p_card, unsigned long p_port)
{
unsigned char temp_id_string[ID_STRING_LENGTH];
unsigned char i, k, scam_id;
unsigned char crcBytes[3];
struct nvram_info *pCurrNvRam;
unsigned short *pCrcBytes;
pCurrNvRam = FPT_BL_Card[p_card].pNvRamInfo;
i = 0;
while (!i) {
for (k = 0; k < ID_STRING_LENGTH; k++) {
temp_id_string[k] = (unsigned char)0x00;
}
FPT_scxferc(p_port, SYNC_PTRN);
FPT_scxferc(p_port, ASSIGN_ID);
if (!(FPT_sciso(p_port, &temp_id_string[0]))) {
if (pCurrNvRam) {
pCrcBytes = (unsigned short *)&crcBytes[0];
*pCrcBytes = FPT_CalcCrc16(&temp_id_string[0]);
crcBytes[2] = FPT_CalcLrc(&temp_id_string[0]);
temp_id_string[1] = crcBytes[2];
temp_id_string[2] = crcBytes[0];
temp_id_string[3] = crcBytes[1];
for (k = 4; k < ID_STRING_LENGTH; k++)
temp_id_string[k] = (unsigned char)0x00;
}
i = FPT_scmachid(p_card, temp_id_string);
if (i == CLR_PRIORITY) {
FPT_scxferc(p_port, MISC_CODE);
FPT_scxferc(p_port, CLR_P_FLAG);
i = 0; /*Not the last ID yet. */
}
else if (i != NO_ID_AVAIL) {
if (i < 8)
FPT_scxferc(p_port, ID_0_7);
else
FPT_scxferc(p_port, ID_8_F);
scam_id = (i & (unsigned char)0x07);
for (k = 1; k < 0x08; k <<= 1)
if (!(k & i))
scam_id += 0x08; /*Count number of zeros in DB0-3. */
FPT_scxferc(p_port, scam_id);
i = 0; /*Not the last ID yet. */
}
}
else {
i = 1;
}
} /*End while */
FPT_scxferc(p_port, SYNC_PTRN);
FPT_scxferc(p_port, CFG_CMPLT);
}
/*---------------------------------------------------------------------
*
* Function: FPT_scsel
*
* Description: Select all the SCAM devices.
*
*---------------------------------------------------------------------*/
static void FPT_scsel(unsigned long p_port)
{
WR_HARPOON(p_port + hp_scsisig, SCSI_SEL);
FPT_scwiros(p_port, SCSI_MSG);
WR_HARPOON(p_port + hp_scsisig, (SCSI_SEL | SCSI_BSY));
WR_HARPOON(p_port + hp_scsisig,
(SCSI_SEL | SCSI_BSY | SCSI_IOBIT | SCSI_CD));
WR_HARPOON(p_port + hp_scsidata_0,
(unsigned char)(RD_HARPOON(p_port + hp_scsidata_0) |
(unsigned char)(BIT(7) + BIT(6))));
WR_HARPOON(p_port + hp_scsisig, (SCSI_BSY | SCSI_IOBIT | SCSI_CD));
FPT_scwiros(p_port, SCSI_SEL);
WR_HARPOON(p_port + hp_scsidata_0,
(unsigned char)(RD_HARPOON(p_port + hp_scsidata_0) &
~(unsigned char)BIT(6)));
FPT_scwirod(p_port, BIT(6));
WR_HARPOON(p_port + hp_scsisig,
(SCSI_SEL | SCSI_BSY | SCSI_IOBIT | SCSI_CD));
}
/*---------------------------------------------------------------------
*
* Function: FPT_scxferc
*
* Description: Handshake the p_data (DB4-0) across the bus.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_scxferc(unsigned long p_port, unsigned char p_data)
{
unsigned char curr_data, ret_data;
curr_data = p_data | BIT(7) | BIT(5); /*Start with DB7 & DB5 asserted. */
WR_HARPOON(p_port + hp_scsidata_0, curr_data);
curr_data &= ~BIT(7);
WR_HARPOON(p_port + hp_scsidata_0, curr_data);
FPT_scwirod(p_port, BIT(7)); /*Wait for DB7 to be released. */
while (!(RD_HARPOON(p_port + hp_scsidata_0) & BIT(5))) ;
ret_data = (RD_HARPOON(p_port + hp_scsidata_0) & (unsigned char)0x1F);
curr_data |= BIT(6);
WR_HARPOON(p_port + hp_scsidata_0, curr_data);
curr_data &= ~BIT(5);
WR_HARPOON(p_port + hp_scsidata_0, curr_data);
FPT_scwirod(p_port, BIT(5)); /*Wait for DB5 to be released. */
curr_data &= ~(BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); /*Release data bits */
curr_data |= BIT(7);
WR_HARPOON(p_port + hp_scsidata_0, curr_data);
curr_data &= ~BIT(6);
WR_HARPOON(p_port + hp_scsidata_0, curr_data);
FPT_scwirod(p_port, BIT(6)); /*Wait for DB6 to be released. */
return ret_data;
}
/*---------------------------------------------------------------------
*
* Function: FPT_scsendi
*
* Description: Transfer our Identification string to determine if we
* will be the dominant master.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_scsendi(unsigned long p_port,
unsigned char p_id_string[])
{
unsigned char ret_data, byte_cnt, bit_cnt, defer;
defer = 0;
for (byte_cnt = 0; byte_cnt < ID_STRING_LENGTH; byte_cnt++) {
for (bit_cnt = 0x80; bit_cnt != 0; bit_cnt >>= 1) {
if (defer)
ret_data = FPT_scxferc(p_port, 00);
else if (p_id_string[byte_cnt] & bit_cnt)
ret_data = FPT_scxferc(p_port, 02);
else {
ret_data = FPT_scxferc(p_port, 01);
if (ret_data & 02)
defer = 1;
}
if ((ret_data & 0x1C) == 0x10)
return 0x00; /*End of isolation stage, we won! */
if (ret_data & 0x1C)
return 0xFF;
if ((defer) && (!(ret_data & 0x1F)))
return 0x01; /*End of isolation stage, we lost. */
} /*bit loop */
} /*byte loop */
if (defer)
return 0x01; /*We lost */
else
return 0; /*We WON! Yeeessss! */
}
/*---------------------------------------------------------------------
*
* Function: FPT_sciso
*
* Description: Transfer the Identification string.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_sciso(unsigned long p_port,
unsigned char p_id_string[])
{
unsigned char ret_data, the_data, byte_cnt, bit_cnt;
the_data = 0;
for (byte_cnt = 0; byte_cnt < ID_STRING_LENGTH; byte_cnt++) {
for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
ret_data = FPT_scxferc(p_port, 0);
if (ret_data & 0xFC)
return 0xFF;
else {
the_data <<= 1;
if (ret_data & BIT(1)) {
the_data |= 1;
}
}
if ((ret_data & 0x1F) == 0) {
/*
if(bit_cnt != 0 || bit_cnt != 8)
{
byte_cnt = 0;
bit_cnt = 0;
FPT_scxferc(p_port, SYNC_PTRN);
FPT_scxferc(p_port, ASSIGN_ID);
continue;
}
*/
if (byte_cnt)
return 0x00;
else
return 0xFF;
}
} /*bit loop */
p_id_string[byte_cnt] = the_data;
} /*byte loop */
return 0;
}
/*---------------------------------------------------------------------
*
* Function: FPT_scwirod
*
* Description: Sample the SCSI data bus making sure the signal has been
* deasserted for the correct number of consecutive samples.
*
*---------------------------------------------------------------------*/
static void FPT_scwirod(unsigned long p_port, unsigned char p_data_bit)
{
unsigned char i;
i = 0;
while (i < MAX_SCSI_TAR) {
if (RD_HARPOON(p_port + hp_scsidata_0) & p_data_bit)
i = 0;
else
i++;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_scwiros
*
* Description: Sample the SCSI Signal lines making sure the signal has been
* deasserted for the correct number of consecutive samples.
*
*---------------------------------------------------------------------*/
static void FPT_scwiros(unsigned long p_port, unsigned char p_data_bit)
{
unsigned char i;
i = 0;
while (i < MAX_SCSI_TAR) {
if (RD_HARPOON(p_port + hp_scsisig) & p_data_bit)
i = 0;
else
i++;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_scvalq
*
* Description: Make sure we received a valid data byte.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_scvalq(unsigned char p_quintet)
{
unsigned char count;
for (count = 1; count < 0x08; count <<= 1) {
if (!(p_quintet & count))
p_quintet -= 0x80;
}
if (p_quintet & 0x18)
return 0;
else
return 1;
}
/*---------------------------------------------------------------------
*
* Function: FPT_scsell
*
* Description: Select the specified device ID using a selection timeout
* less than 4ms. If somebody responds then it is a legacy
* drive and this ID must be marked as such.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_scsell(unsigned long p_port, unsigned char targ_id)
{
unsigned long i;
WR_HARPOON(p_port + hp_page_ctrl,
(RD_HARPOON(p_port + hp_page_ctrl) | G_INT_DISABLE));
ARAM_ACCESS(p_port);
WR_HARPOON(p_port + hp_addstat,
(RD_HARPOON(p_port + hp_addstat) | SCAM_TIMER));
WR_HARPOON(p_port + hp_seltimeout, TO_4ms);
for (i = p_port + CMD_STRT; i < p_port + CMD_STRT + 12; i += 2) {
WRW_HARPOON(i, (MPM_OP + ACOMMAND));
}
WRW_HARPOON(i, (BRH_OP + ALWAYS + NP));
WRW_HARPOON((p_port + hp_intstat),
(RESET | TIMEOUT | SEL | BUS_FREE | AUTO_INT));
WR_HARPOON(p_port + hp_select_id, targ_id);
WR_HARPOON(p_port + hp_portctrl_0, SCSI_PORT);
WR_HARPOON(p_port + hp_autostart_3, (SELECT | CMD_ONLY_STRT));
WR_HARPOON(p_port + hp_scsictrl_0, (SEL_TAR | ENA_RESEL));
while (!(RDW_HARPOON((p_port + hp_intstat)) &
(RESET | PROG_HLT | TIMEOUT | AUTO_INT))) {
}
if (RDW_HARPOON((p_port + hp_intstat)) & RESET)
FPT_Wait(p_port, TO_250ms);
DISABLE_AUTO(p_port);
WR_HARPOON(p_port + hp_addstat,
(RD_HARPOON(p_port + hp_addstat) & ~SCAM_TIMER));
WR_HARPOON(p_port + hp_seltimeout, TO_290ms);
SGRAM_ACCESS(p_port);
if (RDW_HARPOON((p_port + hp_intstat)) & (RESET | TIMEOUT)) {
WRW_HARPOON((p_port + hp_intstat),
(RESET | TIMEOUT | SEL | BUS_FREE | PHASE));
WR_HARPOON(p_port + hp_page_ctrl,
(RD_HARPOON(p_port + hp_page_ctrl) &
~G_INT_DISABLE));
return 0; /*No legacy device */
}
else {
while (!(RDW_HARPOON((p_port + hp_intstat)) & BUS_FREE)) {
if (RD_HARPOON(p_port + hp_scsisig) & SCSI_REQ) {
WR_HARPOON(p_port + hp_scsisig,
(SCSI_ACK + S_ILL_PH));
ACCEPT_MSG(p_port);
}
}
WRW_HARPOON((p_port + hp_intstat), CLR_ALL_INT_1);
WR_HARPOON(p_port + hp_page_ctrl,
(RD_HARPOON(p_port + hp_page_ctrl) &
~G_INT_DISABLE));
return 1; /*Found one of them oldies! */
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_scwtsel
*
* Description: Wait to be selected by another SCAM initiator.
*
*---------------------------------------------------------------------*/
static void FPT_scwtsel(unsigned long p_port)
{
while (!(RDW_HARPOON((p_port + hp_intstat)) & SCAM_SEL)) {
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_inisci
*
* Description: Setup the data Structure with the info from the EEPROM.
*
*---------------------------------------------------------------------*/
static void FPT_inisci(unsigned char p_card, unsigned long p_port,
unsigned char p_our_id)
{
unsigned char i, k, max_id;
unsigned short ee_data;
struct nvram_info *pCurrNvRam;
pCurrNvRam = FPT_BL_Card[p_card].pNvRamInfo;
if (RD_HARPOON(p_port + hp_page_ctrl) & NARROW_SCSI_CARD)
max_id = 0x08;
else
max_id = 0x10;
if (pCurrNvRam) {
for (i = 0; i < max_id; i++) {
for (k = 0; k < 4; k++)
FPT_scamInfo[i].id_string[k] =
pCurrNvRam->niScamTbl[i][k];
for (k = 4; k < ID_STRING_LENGTH; k++)
FPT_scamInfo[i].id_string[k] =
(unsigned char)0x00;
if (FPT_scamInfo[i].id_string[0] == 0x00)
FPT_scamInfo[i].state = ID_UNUSED; /*Default to unused ID. */
else
FPT_scamInfo[i].state = ID_UNASSIGNED; /*Default to unassigned ID. */
}
} else {
for (i = 0; i < max_id; i++) {
for (k = 0; k < ID_STRING_LENGTH; k += 2) {
ee_data =
FPT_utilEERead(p_port,
(unsigned
short)((EE_SCAMBASE / 2) +
(unsigned short)(i *
((unsigned short)ID_STRING_LENGTH / 2)) + (unsigned short)(k / 2)));
FPT_scamInfo[i].id_string[k] =
(unsigned char)ee_data;
ee_data >>= 8;
FPT_scamInfo[i].id_string[k + 1] =
(unsigned char)ee_data;
}
if ((FPT_scamInfo[i].id_string[0] == 0x00) ||
(FPT_scamInfo[i].id_string[0] == 0xFF))
FPT_scamInfo[i].state = ID_UNUSED; /*Default to unused ID. */
else
FPT_scamInfo[i].state = ID_UNASSIGNED; /*Default to unassigned ID. */
}
}
for (k = 0; k < ID_STRING_LENGTH; k++)
FPT_scamInfo[p_our_id].id_string[k] = FPT_scamHAString[k];
}
/*---------------------------------------------------------------------
*
* Function: FPT_scmachid
*
* Description: Match the Device ID string with our values stored in
* the EEPROM.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_scmachid(unsigned char p_card,
unsigned char p_id_string[])
{
unsigned char i, k, match;
for (i = 0; i < MAX_SCSI_TAR; i++) {
match = 1;
for (k = 0; k < ID_STRING_LENGTH; k++) {
if (p_id_string[k] != FPT_scamInfo[i].id_string[k])
match = 0;
}
if (match) {
FPT_scamInfo[i].state = ID_ASSIGNED;
return i;
}
}
if (p_id_string[0] & BIT(5))
i = 8;
else
i = MAX_SCSI_TAR;
if (((p_id_string[0] & 0x06) == 0x02)
|| ((p_id_string[0] & 0x06) == 0x04))
match = p_id_string[1] & (unsigned char)0x1F;
else
match = 7;
while (i > 0) {
i--;
if (FPT_scamInfo[match].state == ID_UNUSED) {
for (k = 0; k < ID_STRING_LENGTH; k++) {
FPT_scamInfo[match].id_string[k] =
p_id_string[k];
}
FPT_scamInfo[match].state = ID_ASSIGNED;
if (FPT_BL_Card[p_card].pNvRamInfo == NULL)
FPT_BL_Card[p_card].globalFlags |=
F_UPDATE_EEPROM;
return match;
}
match--;
if (match == 0xFF) {
if (p_id_string[0] & BIT(5))
match = 7;
else
match = MAX_SCSI_TAR - 1;
}
}
if (p_id_string[0] & BIT(7)) {
return CLR_PRIORITY;
}
if (p_id_string[0] & BIT(5))
i = 8;
else
i = MAX_SCSI_TAR;
if (((p_id_string[0] & 0x06) == 0x02)
|| ((p_id_string[0] & 0x06) == 0x04))
match = p_id_string[1] & (unsigned char)0x1F;
else
match = 7;
while (i > 0) {
i--;
if (FPT_scamInfo[match].state == ID_UNASSIGNED) {
for (k = 0; k < ID_STRING_LENGTH; k++) {
FPT_scamInfo[match].id_string[k] =
p_id_string[k];
}
FPT_scamInfo[match].id_string[0] |= BIT(7);
FPT_scamInfo[match].state = ID_ASSIGNED;
if (FPT_BL_Card[p_card].pNvRamInfo == NULL)
FPT_BL_Card[p_card].globalFlags |=
F_UPDATE_EEPROM;
return match;
}
match--;
if (match == 0xFF) {
if (p_id_string[0] & BIT(5))
match = 7;
else
match = MAX_SCSI_TAR - 1;
}
}
return NO_ID_AVAIL;
}
/*---------------------------------------------------------------------
*
* Function: FPT_scsavdi
*
* Description: Save off the device SCAM ID strings.
*
*---------------------------------------------------------------------*/
static void FPT_scsavdi(unsigned char p_card, unsigned long p_port)
{
unsigned char i, k, max_id;
unsigned short ee_data, sum_data;
sum_data = 0x0000;
for (i = 1; i < EE_SCAMBASE / 2; i++) {
sum_data += FPT_utilEERead(p_port, i);
}
FPT_utilEEWriteOnOff(p_port, 1); /* Enable write access to the EEPROM */
if (RD_HARPOON(p_port + hp_page_ctrl) & NARROW_SCSI_CARD)
max_id = 0x08;
else
max_id = 0x10;
for (i = 0; i < max_id; i++) {
for (k = 0; k < ID_STRING_LENGTH; k += 2) {
ee_data = FPT_scamInfo[i].id_string[k + 1];
ee_data <<= 8;
ee_data |= FPT_scamInfo[i].id_string[k];
sum_data += ee_data;
FPT_utilEEWrite(p_port, ee_data,
(unsigned short)((EE_SCAMBASE / 2) +
(unsigned short)(i *
((unsigned short)ID_STRING_LENGTH / 2)) + (unsigned short)(k / 2)));
}
}
FPT_utilEEWrite(p_port, sum_data, EEPROM_CHECK_SUM / 2);
FPT_utilEEWriteOnOff(p_port, 0); /* Turn off write access */
}
/*---------------------------------------------------------------------
*
* Function: FPT_XbowInit
*
* Description: Setup the Xbow for normal operation.
*
*---------------------------------------------------------------------*/
static void FPT_XbowInit(unsigned long port, unsigned char ScamFlg)
{
unsigned char i;
i = RD_HARPOON(port + hp_page_ctrl);
WR_HARPOON(port + hp_page_ctrl, (unsigned char)(i | G_INT_DISABLE));
WR_HARPOON(port + hp_scsireset, 0x00);
WR_HARPOON(port + hp_portctrl_1, HOST_MODE8);
WR_HARPOON(port + hp_scsireset, (DMA_RESET | HPSCSI_RESET | PROG_RESET |
FIFO_CLR));
WR_HARPOON(port + hp_scsireset, SCSI_INI);
WR_HARPOON(port + hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(port + hp_scsisig, 0x00); /* Clear any signals we might */
WR_HARPOON(port + hp_scsictrl_0, ENA_SCAM_SEL);
WRW_HARPOON((port + hp_intstat), CLR_ALL_INT);
FPT_default_intena = RESET | RSEL | PROG_HLT | TIMEOUT |
BUS_FREE | XFER_CNT_0 | AUTO_INT;
if ((ScamFlg & SCAM_ENABLED) && (ScamFlg & SCAM_LEVEL2))
FPT_default_intena |= SCAM_SEL;
WRW_HARPOON((port + hp_intena), FPT_default_intena);
WR_HARPOON(port + hp_seltimeout, TO_290ms);
/* Turn on SCSI_MODE8 for narrow cards to fix the
strapping issue with the DUAL CHANNEL card */
if (RD_HARPOON(port + hp_page_ctrl) & NARROW_SCSI_CARD)
WR_HARPOON(port + hp_addstat, SCSI_MODE8);
WR_HARPOON(port + hp_page_ctrl, i);
}
/*---------------------------------------------------------------------
*
* Function: FPT_BusMasterInit
*
* Description: Initialize the BusMaster for normal operations.
*
*---------------------------------------------------------------------*/
static void FPT_BusMasterInit(unsigned long p_port)
{
WR_HARPOON(p_port + hp_sys_ctrl, DRVR_RST);
WR_HARPOON(p_port + hp_sys_ctrl, 0x00);
WR_HARPOON(p_port + hp_host_blk_cnt, XFER_BLK64);
WR_HARPOON(p_port + hp_bm_ctrl, (BMCTRL_DEFAULT));
WR_HARPOON(p_port + hp_ee_ctrl, (SCSI_TERM_ENA_H));
RD_HARPOON(p_port + hp_int_status); /*Clear interrupts. */
WR_HARPOON(p_port + hp_int_mask, (INT_CMD_COMPL | SCSI_INTERRUPT));
WR_HARPOON(p_port + hp_page_ctrl, (RD_HARPOON(p_port + hp_page_ctrl) &
~SCATTER_EN));
}
/*---------------------------------------------------------------------
*
* Function: FPT_DiagEEPROM
*
* Description: Verfiy checksum and 'Key' and initialize the EEPROM if
* necessary.
*
*---------------------------------------------------------------------*/
static void FPT_DiagEEPROM(unsigned long p_port)
{
unsigned short index, temp, max_wd_cnt;
if (RD_HARPOON(p_port + hp_page_ctrl) & NARROW_SCSI_CARD)
max_wd_cnt = EEPROM_WD_CNT;
else
max_wd_cnt = EEPROM_WD_CNT * 2;
temp = FPT_utilEERead(p_port, FW_SIGNATURE / 2);
if (temp == 0x4641) {
for (index = 2; index < max_wd_cnt; index++) {
temp += FPT_utilEERead(p_port, index);
}
if (temp == FPT_utilEERead(p_port, EEPROM_CHECK_SUM / 2)) {
return; /*EEPROM is Okay so return now! */
}
}
FPT_utilEEWriteOnOff(p_port, (unsigned char)1);
for (index = 0; index < max_wd_cnt; index++) {
FPT_utilEEWrite(p_port, 0x0000, index);
}
temp = 0;
FPT_utilEEWrite(p_port, 0x4641, FW_SIGNATURE / 2);
temp += 0x4641;
FPT_utilEEWrite(p_port, 0x3920, MODEL_NUMB_0 / 2);
temp += 0x3920;
FPT_utilEEWrite(p_port, 0x3033, MODEL_NUMB_2 / 2);
temp += 0x3033;
FPT_utilEEWrite(p_port, 0x2020, MODEL_NUMB_4 / 2);
temp += 0x2020;
FPT_utilEEWrite(p_port, 0x70D3, SYSTEM_CONFIG / 2);
temp += 0x70D3;
FPT_utilEEWrite(p_port, 0x0010, BIOS_CONFIG / 2);
temp += 0x0010;
FPT_utilEEWrite(p_port, 0x0003, SCAM_CONFIG / 2);
temp += 0x0003;
FPT_utilEEWrite(p_port, 0x0007, ADAPTER_SCSI_ID / 2);
temp += 0x0007;
FPT_utilEEWrite(p_port, 0x0000, IGNORE_B_SCAN / 2);
temp += 0x0000;
FPT_utilEEWrite(p_port, 0x0000, SEND_START_ENA / 2);
temp += 0x0000;
FPT_utilEEWrite(p_port, 0x0000, DEVICE_ENABLE / 2);
temp += 0x0000;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBL01 / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBL23 / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBL45 / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBL67 / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBL89 / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBLab / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBLcd / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x4242, SYNC_RATE_TBLef / 2);
temp += 0x4242;
FPT_utilEEWrite(p_port, 0x6C46, 64 / 2); /*PRODUCT ID */
temp += 0x6C46;
FPT_utilEEWrite(p_port, 0x7361, 66 / 2); /* FlashPoint LT */
temp += 0x7361;
FPT_utilEEWrite(p_port, 0x5068, 68 / 2);
temp += 0x5068;
FPT_utilEEWrite(p_port, 0x696F, 70 / 2);
temp += 0x696F;
FPT_utilEEWrite(p_port, 0x746E, 72 / 2);
temp += 0x746E;
FPT_utilEEWrite(p_port, 0x4C20, 74 / 2);
temp += 0x4C20;
FPT_utilEEWrite(p_port, 0x2054, 76 / 2);
temp += 0x2054;
FPT_utilEEWrite(p_port, 0x2020, 78 / 2);
temp += 0x2020;
index = ((EE_SCAMBASE / 2) + (7 * 16));
FPT_utilEEWrite(p_port, (0x0700 + TYPE_CODE0), index);
temp += (0x0700 + TYPE_CODE0);
index++;
FPT_utilEEWrite(p_port, 0x5542, index); /*Vendor ID code */
temp += 0x5542; /* BUSLOGIC */
index++;
FPT_utilEEWrite(p_port, 0x4C53, index);
temp += 0x4C53;
index++;
FPT_utilEEWrite(p_port, 0x474F, index);
temp += 0x474F;
index++;
FPT_utilEEWrite(p_port, 0x4349, index);
temp += 0x4349;
index++;
FPT_utilEEWrite(p_port, 0x5442, index); /*Vendor unique code */
temp += 0x5442; /* BT- 930 */
index++;
FPT_utilEEWrite(p_port, 0x202D, index);
temp += 0x202D;
index++;
FPT_utilEEWrite(p_port, 0x3339, index);
temp += 0x3339;
index++; /*Serial # */
FPT_utilEEWrite(p_port, 0x2030, index); /* 01234567 */
temp += 0x2030;
index++;
FPT_utilEEWrite(p_port, 0x5453, index);
temp += 0x5453;
index++;
FPT_utilEEWrite(p_port, 0x5645, index);
temp += 0x5645;
index++;
FPT_utilEEWrite(p_port, 0x2045, index);
temp += 0x2045;
index++;
FPT_utilEEWrite(p_port, 0x202F, index);
temp += 0x202F;
index++;
FPT_utilEEWrite(p_port, 0x4F4A, index);
temp += 0x4F4A;
index++;
FPT_utilEEWrite(p_port, 0x204E, index);
temp += 0x204E;
index++;
FPT_utilEEWrite(p_port, 0x3539, index);
temp += 0x3539;
FPT_utilEEWrite(p_port, temp, EEPROM_CHECK_SUM / 2);
FPT_utilEEWriteOnOff(p_port, (unsigned char)0);
}
/*---------------------------------------------------------------------
*
* Function: Queue Search Select
*
* Description: Try to find a new command to execute.
*
*---------------------------------------------------------------------*/
static void FPT_queueSearchSelect(struct sccb_card *pCurrCard,
unsigned char p_card)
{
unsigned char scan_ptr, lun;
struct sccb_mgr_tar_info *currTar_Info;
struct sccb *pOldSccb;
scan_ptr = pCurrCard->scanIndex;
do {
currTar_Info = &FPT_sccbMgrTbl[p_card][scan_ptr];
if ((pCurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING)) {
if (currTar_Info->TarSelQ_Cnt != 0) {
scan_ptr++;
if (scan_ptr == MAX_SCSI_TAR)
scan_ptr = 0;
for (lun = 0; lun < MAX_LUN; lun++) {
if (currTar_Info->TarLUNBusy[lun] == 0) {
pCurrCard->currentSCCB =
currTar_Info->TarSelQ_Head;
pOldSccb = NULL;
while ((pCurrCard->
currentSCCB != NULL)
&& (lun !=
pCurrCard->
currentSCCB->Lun)) {
pOldSccb =
pCurrCard->
currentSCCB;
pCurrCard->currentSCCB =
(struct sccb
*)(pCurrCard->
currentSCCB)->
Sccb_forwardlink;
}
if (pCurrCard->currentSCCB ==
NULL)
continue;
if (pOldSccb != NULL) {
pOldSccb->
Sccb_forwardlink =
(struct sccb
*)(pCurrCard->
currentSCCB)->
Sccb_forwardlink;
pOldSccb->
Sccb_backlink =
(struct sccb
*)(pCurrCard->
currentSCCB)->
Sccb_backlink;
currTar_Info->
TarSelQ_Cnt--;
} else {
currTar_Info->
TarSelQ_Head =
(struct sccb
*)(pCurrCard->
currentSCCB)->
Sccb_forwardlink;
if (currTar_Info->
TarSelQ_Head ==
NULL) {
currTar_Info->
TarSelQ_Tail
= NULL;
currTar_Info->
TarSelQ_Cnt
= 0;
} else {
currTar_Info->
TarSelQ_Cnt--;
currTar_Info->
TarSelQ_Head->
Sccb_backlink
=
(struct sccb
*)NULL;
}
}
pCurrCard->scanIndex = scan_ptr;
pCurrCard->globalFlags |=
F_NEW_SCCB_CMD;
break;
}
}
}
else {
scan_ptr++;
if (scan_ptr == MAX_SCSI_TAR) {
scan_ptr = 0;
}
}
} else {
if ((currTar_Info->TarSelQ_Cnt != 0) &&
(currTar_Info->TarLUNBusy[0] == 0)) {
pCurrCard->currentSCCB =
currTar_Info->TarSelQ_Head;
currTar_Info->TarSelQ_Head =
(struct sccb *)(pCurrCard->currentSCCB)->
Sccb_forwardlink;
if (currTar_Info->TarSelQ_Head == NULL) {
currTar_Info->TarSelQ_Tail = NULL;
currTar_Info->TarSelQ_Cnt = 0;
} else {
currTar_Info->TarSelQ_Cnt--;
currTar_Info->TarSelQ_Head->
Sccb_backlink = (struct sccb *)NULL;
}
scan_ptr++;
if (scan_ptr == MAX_SCSI_TAR)
scan_ptr = 0;
pCurrCard->scanIndex = scan_ptr;
pCurrCard->globalFlags |= F_NEW_SCCB_CMD;
break;
}
else {
scan_ptr++;
if (scan_ptr == MAX_SCSI_TAR) {
scan_ptr = 0;
}
}
}
} while (scan_ptr != pCurrCard->scanIndex);
}
/*---------------------------------------------------------------------
*
* Function: Queue Select Fail
*
* Description: Add the current SCCB to the head of the Queue.
*
*---------------------------------------------------------------------*/
static void FPT_queueSelectFail(struct sccb_card *pCurrCard,
unsigned char p_card)
{
unsigned char thisTarg;
struct sccb_mgr_tar_info *currTar_Info;
if (pCurrCard->currentSCCB != NULL) {
thisTarg =
(unsigned char)(((struct sccb *)(pCurrCard->currentSCCB))->
TargID);
currTar_Info = &FPT_sccbMgrTbl[p_card][thisTarg];
pCurrCard->currentSCCB->Sccb_backlink = (struct sccb *)NULL;
pCurrCard->currentSCCB->Sccb_forwardlink =
currTar_Info->TarSelQ_Head;
if (currTar_Info->TarSelQ_Cnt == 0) {
currTar_Info->TarSelQ_Tail = pCurrCard->currentSCCB;
}
else {
currTar_Info->TarSelQ_Head->Sccb_backlink =
pCurrCard->currentSCCB;
}
currTar_Info->TarSelQ_Head = pCurrCard->currentSCCB;
pCurrCard->currentSCCB = NULL;
currTar_Info->TarSelQ_Cnt++;
}
}
/*---------------------------------------------------------------------
*
* Function: Queue Command Complete
*
* Description: Call the callback function with the current SCCB.
*
*---------------------------------------------------------------------*/
static void FPT_queueCmdComplete(struct sccb_card *pCurrCard,
struct sccb *p_sccb, unsigned char p_card)
{
unsigned char i, SCSIcmd;
CALL_BK_FN callback;
struct sccb_mgr_tar_info *currTar_Info;
SCSIcmd = p_sccb->Cdb[0];
if (!(p_sccb->Sccb_XferState & F_ALL_XFERRED)) {
if ((p_sccb->
ControlByte & (SCCB_DATA_XFER_OUT | SCCB_DATA_XFER_IN))
&& (p_sccb->HostStatus == SCCB_COMPLETE)
&& (p_sccb->TargetStatus != SSCHECK))
if ((SCSIcmd == SCSI_READ) ||
(SCSIcmd == SCSI_WRITE) ||
(SCSIcmd == SCSI_READ_EXTENDED) ||
(SCSIcmd == SCSI_WRITE_EXTENDED) ||
(SCSIcmd == SCSI_WRITE_AND_VERIFY) ||
(SCSIcmd == SCSI_START_STOP_UNIT) ||
(pCurrCard->globalFlags & F_NO_FILTER)
)
p_sccb->HostStatus = SCCB_DATA_UNDER_RUN;
}
if (p_sccb->SccbStatus == SCCB_IN_PROCESS) {
if (p_sccb->HostStatus || p_sccb->TargetStatus)
p_sccb->SccbStatus = SCCB_ERROR;
else
p_sccb->SccbStatus = SCCB_SUCCESS;
}
if (p_sccb->Sccb_XferState & F_AUTO_SENSE) {
p_sccb->CdbLength = p_sccb->Save_CdbLen;
for (i = 0; i < 6; i++) {
p_sccb->Cdb[i] = p_sccb->Save_Cdb[i];
}
}
if ((p_sccb->OperationCode == RESIDUAL_SG_COMMAND) ||
(p_sccb->OperationCode == RESIDUAL_COMMAND)) {
FPT_utilUpdateResidual(p_sccb);
}
pCurrCard->cmdCounter--;
if (!pCurrCard->cmdCounter) {
if (pCurrCard->globalFlags & F_GREEN_PC) {
WR_HARPOON(pCurrCard->ioPort + hp_clkctrl_0,
(PWR_DWN | CLKCTRL_DEFAULT));
WR_HARPOON(pCurrCard->ioPort + hp_sys_ctrl, STOP_CLK);
}
WR_HARPOON(pCurrCard->ioPort + hp_semaphore,
(RD_HARPOON(pCurrCard->ioPort + hp_semaphore) &
~SCCB_MGR_ACTIVE));
}
if (pCurrCard->discQCount != 0) {
currTar_Info = &FPT_sccbMgrTbl[p_card][p_sccb->TargID];
if (((pCurrCard->globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) !=
TAG_Q_TRYING))) {
pCurrCard->discQCount--;
pCurrCard->discQ_Tbl[currTar_Info->
LunDiscQ_Idx[p_sccb->Lun]] = NULL;
} else {
if (p_sccb->Sccb_tag) {
pCurrCard->discQCount--;
pCurrCard->discQ_Tbl[p_sccb->Sccb_tag] = NULL;
} else {
pCurrCard->discQCount--;
pCurrCard->discQ_Tbl[currTar_Info->
LunDiscQ_Idx[0]] = NULL;
}
}
}
callback = (CALL_BK_FN) p_sccb->SccbCallback;
callback(p_sccb);
pCurrCard->globalFlags |= F_NEW_SCCB_CMD;
pCurrCard->currentSCCB = NULL;
}
/*---------------------------------------------------------------------
*
* Function: Queue Disconnect
*
* Description: Add SCCB to our disconnect array.
*
*---------------------------------------------------------------------*/
static void FPT_queueDisconnect(struct sccb *p_sccb, unsigned char p_card)
{
struct sccb_mgr_tar_info *currTar_Info;
currTar_Info = &FPT_sccbMgrTbl[p_card][p_sccb->TargID];
if (((FPT_BL_Card[p_card].globalFlags & F_CONLUN_IO) &&
((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))) {
FPT_BL_Card[p_card].discQ_Tbl[currTar_Info->
LunDiscQ_Idx[p_sccb->Lun]] =
p_sccb;
} else {
if (p_sccb->Sccb_tag) {
FPT_BL_Card[p_card].discQ_Tbl[p_sccb->Sccb_tag] =
p_sccb;
FPT_sccbMgrTbl[p_card][p_sccb->TargID].TarLUNBusy[0] =
0;
FPT_sccbMgrTbl[p_card][p_sccb->TargID].TarTagQ_Cnt++;
} else {
FPT_BL_Card[p_card].discQ_Tbl[currTar_Info->
LunDiscQ_Idx[0]] = p_sccb;
}
}
FPT_BL_Card[p_card].currentSCCB = NULL;
}
/*---------------------------------------------------------------------
*
* Function: Queue Flush SCCB
*
* Description: Flush all SCCB's back to the host driver for this target.
*
*---------------------------------------------------------------------*/
static void FPT_queueFlushSccb(unsigned char p_card, unsigned char error_code)
{
unsigned char qtag, thisTarg;
struct sccb *currSCCB;
struct sccb_mgr_tar_info *currTar_Info;
currSCCB = FPT_BL_Card[p_card].currentSCCB;
if (currSCCB != NULL) {
thisTarg = (unsigned char)currSCCB->TargID;
currTar_Info = &FPT_sccbMgrTbl[p_card][thisTarg];
for (qtag = 0; qtag < QUEUE_DEPTH; qtag++) {
if (FPT_BL_Card[p_card].discQ_Tbl[qtag] &&
(FPT_BL_Card[p_card].discQ_Tbl[qtag]->TargID ==
thisTarg)) {
FPT_BL_Card[p_card].discQ_Tbl[qtag]->
HostStatus = (unsigned char)error_code;
FPT_queueCmdComplete(&FPT_BL_Card[p_card],
FPT_BL_Card[p_card].
discQ_Tbl[qtag], p_card);
FPT_BL_Card[p_card].discQ_Tbl[qtag] = NULL;
currTar_Info->TarTagQ_Cnt--;
}
}
}
}
/*---------------------------------------------------------------------
*
* Function: Queue Flush Target SCCB
*
* Description: Flush all SCCB's back to the host driver for this target.
*
*---------------------------------------------------------------------*/
static void FPT_queueFlushTargSccb(unsigned char p_card, unsigned char thisTarg,
unsigned char error_code)
{
unsigned char qtag;
struct sccb_mgr_tar_info *currTar_Info;
currTar_Info = &FPT_sccbMgrTbl[p_card][thisTarg];
for (qtag = 0; qtag < QUEUE_DEPTH; qtag++) {
if (FPT_BL_Card[p_card].discQ_Tbl[qtag] &&
(FPT_BL_Card[p_card].discQ_Tbl[qtag]->TargID == thisTarg)) {
FPT_BL_Card[p_card].discQ_Tbl[qtag]->HostStatus =
(unsigned char)error_code;
FPT_queueCmdComplete(&FPT_BL_Card[p_card],
FPT_BL_Card[p_card].
discQ_Tbl[qtag], p_card);
FPT_BL_Card[p_card].discQ_Tbl[qtag] = NULL;
currTar_Info->TarTagQ_Cnt--;
}
}
}
static void FPT_queueAddSccb(struct sccb *p_SCCB, unsigned char p_card)
{
struct sccb_mgr_tar_info *currTar_Info;
currTar_Info = &FPT_sccbMgrTbl[p_card][p_SCCB->TargID];
p_SCCB->Sccb_forwardlink = NULL;
p_SCCB->Sccb_backlink = currTar_Info->TarSelQ_Tail;
if (currTar_Info->TarSelQ_Cnt == 0) {
currTar_Info->TarSelQ_Head = p_SCCB;
}
else {
currTar_Info->TarSelQ_Tail->Sccb_forwardlink = p_SCCB;
}
currTar_Info->TarSelQ_Tail = p_SCCB;
currTar_Info->TarSelQ_Cnt++;
}
/*---------------------------------------------------------------------
*
* Function: Queue Find SCCB
*
* Description: Search the target select Queue for this SCCB, and
* remove it if found.
*
*---------------------------------------------------------------------*/
static unsigned char FPT_queueFindSccb(struct sccb *p_SCCB,
unsigned char p_card)
{
struct sccb *q_ptr;
struct sccb_mgr_tar_info *currTar_Info;
currTar_Info = &FPT_sccbMgrTbl[p_card][p_SCCB->TargID];
q_ptr = currTar_Info->TarSelQ_Head;
while (q_ptr != NULL) {
if (q_ptr == p_SCCB) {
if (currTar_Info->TarSelQ_Head == q_ptr) {
currTar_Info->TarSelQ_Head =
q_ptr->Sccb_forwardlink;
}
if (currTar_Info->TarSelQ_Tail == q_ptr) {
currTar_Info->TarSelQ_Tail =
q_ptr->Sccb_backlink;
}
if (q_ptr->Sccb_forwardlink != NULL) {
q_ptr->Sccb_forwardlink->Sccb_backlink =
q_ptr->Sccb_backlink;
}
if (q_ptr->Sccb_backlink != NULL) {
q_ptr->Sccb_backlink->Sccb_forwardlink =
q_ptr->Sccb_forwardlink;
}
currTar_Info->TarSelQ_Cnt--;
return 1;
}
else {
q_ptr = q_ptr->Sccb_forwardlink;
}
}
return 0;
}
/*---------------------------------------------------------------------
*
* Function: Utility Update Residual Count
*
* Description: Update the XferCnt to the remaining byte count.
* If we transferred all the data then just write zero.
* If Non-SG transfer then report Total Cnt - Actual Transfer
* Cnt. For SG transfers add the count fields of all
* remaining SG elements, as well as any partial remaining
* element.
*
*---------------------------------------------------------------------*/
static void FPT_utilUpdateResidual(struct sccb *p_SCCB)
{
unsigned long partial_cnt;
unsigned int sg_index;
unsigned long *sg_ptr;
if (p_SCCB->Sccb_XferState & F_ALL_XFERRED) {
p_SCCB->DataLength = 0x0000;
}
else if (p_SCCB->Sccb_XferState & F_SG_XFER) {
partial_cnt = 0x0000;
sg_index = p_SCCB->Sccb_sgseg;
sg_ptr = (unsigned long *)p_SCCB->DataPointer;
if (p_SCCB->Sccb_SGoffset) {
partial_cnt = p_SCCB->Sccb_SGoffset;
sg_index++;
}
while (((unsigned long)sg_index *
(unsigned long)SG_ELEMENT_SIZE) < p_SCCB->DataLength) {
partial_cnt += *(sg_ptr + (sg_index * 2));
sg_index++;
}
p_SCCB->DataLength = partial_cnt;
}
else {
p_SCCB->DataLength -= p_SCCB->Sccb_ATC;
}
}
/*---------------------------------------------------------------------
*
* Function: Wait 1 Second
*
* Description: Wait for 1 second.
*
*---------------------------------------------------------------------*/
static void FPT_Wait1Second(unsigned long p_port)
{
unsigned char i;
for (i = 0; i < 4; i++) {
FPT_Wait(p_port, TO_250ms);
if ((RD_HARPOON(p_port + hp_scsictrl_0) & SCSI_RST))
break;
if ((RDW_HARPOON((p_port + hp_intstat)) & SCAM_SEL))
break;
}
}
/*---------------------------------------------------------------------
*
* Function: FPT_Wait
*
* Description: Wait the desired delay.
*
*---------------------------------------------------------------------*/
static void FPT_Wait(unsigned long p_port, unsigned char p_delay)
{
unsigned char old_timer;
unsigned char green_flag;
old_timer = RD_HARPOON(p_port + hp_seltimeout);
green_flag = RD_HARPOON(p_port + hp_clkctrl_0);
WR_HARPOON(p_port + hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(p_port + hp_seltimeout, p_delay);
WRW_HARPOON((p_port + hp_intstat), TIMEOUT);
WRW_HARPOON((p_port + hp_intena), (FPT_default_intena & ~TIMEOUT));
WR_HARPOON(p_port + hp_portctrl_0,
(RD_HARPOON(p_port + hp_portctrl_0) | START_TO));
while (!(RDW_HARPOON((p_port + hp_intstat)) & TIMEOUT)) {
if ((RD_HARPOON(p_port + hp_scsictrl_0) & SCSI_RST))
break;
if ((RDW_HARPOON((p_port + hp_intstat)) & SCAM_SEL))
break;
}
WR_HARPOON(p_port + hp_portctrl_0,
(RD_HARPOON(p_port + hp_portctrl_0) & ~START_TO));
WRW_HARPOON((p_port + hp_intstat), TIMEOUT);
WRW_HARPOON((p_port + hp_intena), FPT_default_intena);
WR_HARPOON(p_port + hp_clkctrl_0, green_flag);
WR_HARPOON(p_port + hp_seltimeout, old_timer);
}
/*---------------------------------------------------------------------
*
* Function: Enable/Disable Write to EEPROM
*
* Description: The EEPROM must first be enabled for writes
* A total of 9 clocks are needed.
*
*---------------------------------------------------------------------*/
static void FPT_utilEEWriteOnOff(unsigned long p_port, unsigned char p_mode)
{
unsigned char ee_value;
ee_value =
(unsigned char)(RD_HARPOON(p_port + hp_ee_ctrl) &
(EXT_ARB_ACK | SCSI_TERM_ENA_H));
if (p_mode)
FPT_utilEESendCmdAddr(p_port, EWEN, EWEN_ADDR);
else
FPT_utilEESendCmdAddr(p_port, EWDS, EWDS_ADDR);
WR_HARPOON(p_port + hp_ee_ctrl, (ee_value | SEE_MS)); /*Turn off CS */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value); /*Turn off Master Select */
}
/*---------------------------------------------------------------------
*
* Function: Write EEPROM
*
* Description: Write a word to the EEPROM at the specified
* address.
*
*---------------------------------------------------------------------*/
static void FPT_utilEEWrite(unsigned long p_port, unsigned short ee_data,
unsigned short ee_addr)
{
unsigned char ee_value;
unsigned short i;
ee_value =
(unsigned
char)((RD_HARPOON(p_port + hp_ee_ctrl) &
(EXT_ARB_ACK | SCSI_TERM_ENA_H)) | (SEE_MS | SEE_CS));
FPT_utilEESendCmdAddr(p_port, EE_WRITE, ee_addr);
ee_value |= (SEE_MS + SEE_CS);
for (i = 0x8000; i != 0; i >>= 1) {
if (i & ee_data)
ee_value |= SEE_DO;
else
ee_value &= ~SEE_DO;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value |= SEE_CLK; /* Clock data! */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value &= ~SEE_CLK;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
}
ee_value &= (EXT_ARB_ACK | SCSI_TERM_ENA_H);
WR_HARPOON(p_port + hp_ee_ctrl, (ee_value | SEE_MS));
FPT_Wait(p_port, TO_10ms);
WR_HARPOON(p_port + hp_ee_ctrl, (ee_value | SEE_MS | SEE_CS)); /* Set CS to EEPROM */
WR_HARPOON(p_port + hp_ee_ctrl, (ee_value | SEE_MS)); /* Turn off CS */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value); /* Turn off Master Select */
}
/*---------------------------------------------------------------------
*
* Function: Read EEPROM
*
* Description: Read a word from the EEPROM at the desired
* address.
*
*---------------------------------------------------------------------*/
static unsigned short FPT_utilEERead(unsigned long p_port,
unsigned short ee_addr)
{
unsigned short i, ee_data1, ee_data2;
i = 0;
ee_data1 = FPT_utilEEReadOrg(p_port, ee_addr);
do {
ee_data2 = FPT_utilEEReadOrg(p_port, ee_addr);
if (ee_data1 == ee_data2)
return ee_data1;
ee_data1 = ee_data2;
i++;
} while (i < 4);
return ee_data1;
}
/*---------------------------------------------------------------------
*
* Function: Read EEPROM Original
*
* Description: Read a word from the EEPROM at the desired
* address.
*
*---------------------------------------------------------------------*/
static unsigned short FPT_utilEEReadOrg(unsigned long p_port,
unsigned short ee_addr)
{
unsigned char ee_value;
unsigned short i, ee_data;
ee_value =
(unsigned
char)((RD_HARPOON(p_port + hp_ee_ctrl) &
(EXT_ARB_ACK | SCSI_TERM_ENA_H)) | (SEE_MS | SEE_CS));
FPT_utilEESendCmdAddr(p_port, EE_READ, ee_addr);
ee_value |= (SEE_MS + SEE_CS);
ee_data = 0;
for (i = 1; i <= 16; i++) {
ee_value |= SEE_CLK; /* Clock data! */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value &= ~SEE_CLK;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_data <<= 1;
if (RD_HARPOON(p_port + hp_ee_ctrl) & SEE_DI)
ee_data |= 1;
}
ee_value &= ~(SEE_MS + SEE_CS);
WR_HARPOON(p_port + hp_ee_ctrl, (ee_value | SEE_MS)); /*Turn off CS */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value); /*Turn off Master Select */
return ee_data;
}
/*---------------------------------------------------------------------
*
* Function: Send EE command and Address to the EEPROM
*
* Description: Transfers the correct command and sends the address
* to the eeprom.
*
*---------------------------------------------------------------------*/
static void FPT_utilEESendCmdAddr(unsigned long p_port, unsigned char ee_cmd,
unsigned short ee_addr)
{
unsigned char ee_value;
unsigned char narrow_flg;
unsigned short i;
narrow_flg =
(unsigned char)(RD_HARPOON(p_port + hp_page_ctrl) &
NARROW_SCSI_CARD);
ee_value = SEE_MS;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value |= SEE_CS; /* Set CS to EEPROM */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
for (i = 0x04; i != 0; i >>= 1) {
if (i & ee_cmd)
ee_value |= SEE_DO;
else
ee_value &= ~SEE_DO;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value |= SEE_CLK; /* Clock data! */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value &= ~SEE_CLK;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
}
if (narrow_flg)
i = 0x0080;
else
i = 0x0200;
while (i != 0) {
if (i & ee_addr)
ee_value |= SEE_DO;
else
ee_value &= ~SEE_DO;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value |= SEE_CLK; /* Clock data! */
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
ee_value &= ~SEE_CLK;
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
WR_HARPOON(p_port + hp_ee_ctrl, ee_value);
i >>= 1;
}
}
static unsigned short FPT_CalcCrc16(unsigned char buffer[])
{
unsigned short crc = 0;
int i, j;
unsigned short ch;
for (i = 0; i < ID_STRING_LENGTH; i++) {
ch = (unsigned short)buffer[i];
for (j = 0; j < 8; j++) {
if ((crc ^ ch) & 1)
crc = (crc >> 1) ^ CRCMASK;
else
crc >>= 1;
ch >>= 1;
}
}
return crc;
}
static unsigned char FPT_CalcLrc(unsigned char buffer[])
{
int i;
unsigned char lrc;
lrc = 0;
for (i = 0; i < ID_STRING_LENGTH; i++)
lrc ^= buffer[i];
return lrc;
}
/*
The following inline definitions avoid type conflicts.
*/
static inline unsigned char
FlashPoint__ProbeHostAdapter(struct FlashPoint_Info *FlashPointInfo)
{
return FlashPoint_ProbeHostAdapter((struct sccb_mgr_info *)
FlashPointInfo);
}
static inline FlashPoint_CardHandle_T
FlashPoint__HardwareResetHostAdapter(struct FlashPoint_Info *FlashPointInfo)
{
return FlashPoint_HardwareResetHostAdapter((struct sccb_mgr_info *)
FlashPointInfo);
}
static inline void
FlashPoint__ReleaseHostAdapter(FlashPoint_CardHandle_T CardHandle)
{
FlashPoint_ReleaseHostAdapter(CardHandle);
}
static inline void
FlashPoint__StartCCB(FlashPoint_CardHandle_T CardHandle,
struct BusLogic_CCB *CCB)
{
FlashPoint_StartCCB(CardHandle, (struct sccb *)CCB);
}
static inline void
FlashPoint__AbortCCB(FlashPoint_CardHandle_T CardHandle,
struct BusLogic_CCB *CCB)
{
FlashPoint_AbortCCB(CardHandle, (struct sccb *)CCB);
}
static inline bool
FlashPoint__InterruptPending(FlashPoint_CardHandle_T CardHandle)
{
return FlashPoint_InterruptPending(CardHandle);
}
static inline int
FlashPoint__HandleInterrupt(FlashPoint_CardHandle_T CardHandle)
{
return FlashPoint_HandleInterrupt(CardHandle);
}
#define FlashPoint_ProbeHostAdapter FlashPoint__ProbeHostAdapter
#define FlashPoint_HardwareResetHostAdapter FlashPoint__HardwareResetHostAdapter
#define FlashPoint_ReleaseHostAdapter FlashPoint__ReleaseHostAdapter
#define FlashPoint_StartCCB FlashPoint__StartCCB
#define FlashPoint_AbortCCB FlashPoint__AbortCCB
#define FlashPoint_InterruptPending FlashPoint__InterruptPending
#define FlashPoint_HandleInterrupt FlashPoint__HandleInterrupt
#else /* !CONFIG_SCSI_FLASHPOINT */
/*
Define prototypes for the FlashPoint SCCB Manager Functions.
*/
extern unsigned char FlashPoint_ProbeHostAdapter(struct FlashPoint_Info *);
extern FlashPoint_CardHandle_T
FlashPoint_HardwareResetHostAdapter(struct FlashPoint_Info *);
extern void FlashPoint_StartCCB(FlashPoint_CardHandle_T, struct BusLogic_CCB *);
extern int FlashPoint_AbortCCB(FlashPoint_CardHandle_T, struct BusLogic_CCB *);
extern bool FlashPoint_InterruptPending(FlashPoint_CardHandle_T);
extern int FlashPoint_HandleInterrupt(FlashPoint_CardHandle_T);
extern void FlashPoint_ReleaseHostAdapter(FlashPoint_CardHandle_T);
#endif /* CONFIG_SCSI_FLASHPOINT */
| gpl-2.0 |
Pivosgroup/TOFULinux-kernel | arch/mips/cobalt/setup.c | 10926 | 2784 | /*
* Setup pointers to hardware dependent routines.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/gt64120.h>
#include <cobalt.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
const char *get_system_type(void)
{
switch (cobalt_board_id) {
case COBALT_BRD_ID_QUBE1:
return "Cobalt Qube";
case COBALT_BRD_ID_RAQ1:
return "Cobalt RaQ";
case COBALT_BRD_ID_QUBE2:
return "Cobalt Qube2";
case COBALT_BRD_ID_RAQ2:
return "Cobalt RaQ2";
}
return "MIPS Cobalt";
}
/*
* Cobalt doesn't have PS/2 keyboard/mouse interfaces,
* keyboard conntroller is never used.
* Also PCI-ISA bridge DMA contoroller is never used.
*/
static struct resource cobalt_reserved_resources[] = {
{ /* dma1 */
.start = 0x00,
.end = 0x1f,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
{ /* keyboard */
.start = 0x60,
.end = 0x6f,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
{ /* dma page reg */
.start = 0x80,
.end = 0x8f,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
{ /* dma2 */
.start = 0xc0,
.end = 0xdf,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
};
void __init plat_mem_setup(void)
{
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_halt;
set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
/* I/O port resource */
ioport_resource.end = 0x01ffffff;
/* These resources have been reserved by VIA SuperI/O chip. */
for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
request_resource(&ioport_resource, cobalt_reserved_resources + i);
}
/*
* Prom init. We read our one and only communication with the firmware.
* Grab the amount of installed memory.
* Better boot loaders (CoLo) pass a command line too :-)
*/
void __init prom_init(void)
{
unsigned long memsz;
int argc, i;
char **argv;
memsz = fw_arg0 & 0x7fff0000;
argc = fw_arg0 & 0x0000ffff;
argv = (char **)fw_arg1;
for (i = 1; i < argc; i++) {
strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
if (i < (argc - 1))
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
}
add_memory_region(0x0, memsz, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
/* Nothing to do! */
}
| gpl-2.0 |
somcom3x/kernel_gogh | fs/minix/itree_v1.c | 13486 | 1481 | #include <linux/buffer_head.h>
#include <linux/slab.h>
#include "minix.h"
enum {DEPTH = 3, DIRECT = 7}; /* Only double indirect */
typedef u16 block_t; /* 16 bit, host order */
static inline unsigned long block_to_cpu(block_t n)
{
return n;
}
static inline block_t cpu_to_block(unsigned long n)
{
return n;
}
static inline block_t *i_data(struct inode *inode)
{
return (block_t *)minix_i(inode)->u.i1_data;
}
static int block_to_path(struct inode * inode, long block, int offsets[DEPTH])
{
int n = 0;
char b[BDEVNAME_SIZE];
if (block < 0) {
printk("MINIX-fs: block_to_path: block %ld < 0 on dev %s\n",
block, bdevname(inode->i_sb->s_bdev, b));
} else if (block >= (minix_sb(inode->i_sb)->s_max_size/BLOCK_SIZE)) {
if (printk_ratelimit())
printk("MINIX-fs: block_to_path: "
"block %ld too big on dev %s\n",
block, bdevname(inode->i_sb->s_bdev, b));
} else if (block < 7) {
offsets[n++] = block;
} else if ((block -= 7) < 512) {
offsets[n++] = 7;
offsets[n++] = block;
} else {
block -= 512;
offsets[n++] = 8;
offsets[n++] = block>>9;
offsets[n++] = block & 511;
}
return n;
}
#include "itree_common.c"
int V1_minix_get_block(struct inode * inode, long block,
struct buffer_head *bh_result, int create)
{
return get_block(inode, block, bh_result, create);
}
void V1_minix_truncate(struct inode * inode)
{
truncate(inode);
}
unsigned V1_minix_blocks(loff_t size, struct super_block *sb)
{
return nblocks(size, sb);
}
| gpl-2.0 |
starsoc/linux-star-x7 | sound/soc/codecs/ak4641.c | 175 | 17903 | /*
* ak4641.c -- AK4641 ALSA Soc Audio driver
*
* Copyright (C) 2008 Harald Welte <laforge@gnufiish.org>
* Copyright (C) 2011 Dmitry Artamonow <mad_soft@inbox.ru>
*
* Based on ak4535.c by Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/ak4641.h>
#include "ak4641.h"
/* codec private data */
struct ak4641_priv {
unsigned int sysclk;
int deemph;
int playback_fs;
};
/*
* ak4641 register cache
*/
static const u8 ak4641_reg[AK4641_CACHEREGNUM] = {
0x00, 0x80, 0x00, 0x80,
0x02, 0x00, 0x11, 0x05,
0x00, 0x00, 0x36, 0x10,
0x00, 0x00, 0x57, 0x00,
0x88, 0x88, 0x08, 0x08
};
static const int deemph_settings[] = {44100, 0, 48000, 32000};
static int ak4641_set_deemph(struct snd_soc_codec *codec)
{
struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
int i, best = 0;
for (i = 0 ; i < ARRAY_SIZE(deemph_settings); i++) {
/* if deemphasis is on, select the nearest available rate */
if (ak4641->deemph && deemph_settings[i] != 0 &&
abs(deemph_settings[i] - ak4641->playback_fs) <
abs(deemph_settings[best] - ak4641->playback_fs))
best = i;
if (!ak4641->deemph && deemph_settings[i] == 0)
best = i;
}
dev_dbg(codec->dev, "Set deemphasis %d\n", best);
return snd_soc_update_bits(codec, AK4641_DAC, 0x3, best);
}
static int ak4641_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
int deemph = ucontrol->value.enumerated.item[0];
if (deemph > 1)
return -EINVAL;
ak4641->deemph = deemph;
return ak4641_set_deemph(codec);
}
static int ak4641_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = ak4641->deemph;
return 0;
};
static const char *ak4641_mono_out[] = {"(L + R)/2", "Hi-Z"};
static const char *ak4641_hp_out[] = {"Stereo", "Mono"};
static const char *ak4641_mic_select[] = {"Internal", "External"};
static const char *ak4641_mic_or_dac[] = {"Microphone", "Voice DAC"};
static const DECLARE_TLV_DB_SCALE(mono_gain_tlv, -1700, 2300, 0);
static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, 0, 2000, 0);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(master_tlv, -12750, 50, 0);
static const DECLARE_TLV_DB_SCALE(mic_stereo_sidetone_tlv, -2700, 300, 0);
static const DECLARE_TLV_DB_SCALE(mic_mono_sidetone_tlv, -400, 400, 0);
static const DECLARE_TLV_DB_SCALE(capture_tlv, -800, 50, 0);
static const DECLARE_TLV_DB_SCALE(alc_tlv, -800, 50, 0);
static const DECLARE_TLV_DB_SCALE(aux_in_tlv, -2100, 300, 0);
static const struct soc_enum ak4641_mono_out_enum =
SOC_ENUM_SINGLE(AK4641_SIG1, 6, 2, ak4641_mono_out);
static const struct soc_enum ak4641_hp_out_enum =
SOC_ENUM_SINGLE(AK4641_MODE2, 2, 2, ak4641_hp_out);
static const struct soc_enum ak4641_mic_select_enum =
SOC_ENUM_SINGLE(AK4641_MIC, 1, 2, ak4641_mic_select);
static const struct soc_enum ak4641_mic_or_dac_enum =
SOC_ENUM_SINGLE(AK4641_BTIF, 4, 2, ak4641_mic_or_dac);
static const struct snd_kcontrol_new ak4641_snd_controls[] = {
SOC_ENUM("Mono 1 Output", ak4641_mono_out_enum),
SOC_SINGLE_TLV("Mono 1 Gain Volume", AK4641_SIG1, 7, 1, 1,
mono_gain_tlv),
SOC_ENUM("Headphone Output", ak4641_hp_out_enum),
SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
ak4641_get_deemph, ak4641_put_deemph),
SOC_SINGLE_TLV("Mic Boost Volume", AK4641_MIC, 0, 1, 0, mic_boost_tlv),
SOC_SINGLE("ALC Operation Time", AK4641_TIMER, 0, 3, 0),
SOC_SINGLE("ALC Recovery Time", AK4641_TIMER, 2, 3, 0),
SOC_SINGLE("ALC ZC Time", AK4641_TIMER, 4, 3, 0),
SOC_SINGLE("ALC 1 Switch", AK4641_ALC1, 5, 1, 0),
SOC_SINGLE_TLV("ALC Volume", AK4641_ALC2, 0, 71, 0, alc_tlv),
SOC_SINGLE("Left Out Enable Switch", AK4641_SIG2, 1, 1, 0),
SOC_SINGLE("Right Out Enable Switch", AK4641_SIG2, 0, 1, 0),
SOC_SINGLE_TLV("Capture Volume", AK4641_PGA, 0, 71, 0, capture_tlv),
SOC_DOUBLE_R_TLV("Master Playback Volume", AK4641_LATT,
AK4641_RATT, 0, 255, 1, master_tlv),
SOC_SINGLE_TLV("AUX In Volume", AK4641_VOL, 0, 15, 0, aux_in_tlv),
SOC_SINGLE("Equalizer Switch", AK4641_DAC, 2, 1, 0),
SOC_SINGLE_TLV("EQ1 100 Hz Volume", AK4641_EQLO, 0, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ2 250 Hz Volume", AK4641_EQLO, 4, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ3 1 kHz Volume", AK4641_EQMID, 0, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ4 3.5 kHz Volume", AK4641_EQMID, 4, 15, 1, eq_tlv),
SOC_SINGLE_TLV("EQ5 10 kHz Volume", AK4641_EQHI, 0, 15, 1, eq_tlv),
};
/* Mono 1 Mixer */
static const struct snd_kcontrol_new ak4641_mono1_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("Mic Mono Sidetone Volume", AK4641_VOL, 7, 1, 0,
mic_mono_sidetone_tlv),
SOC_DAPM_SINGLE("Mic Mono Sidetone Switch", AK4641_SIG1, 4, 1, 0),
SOC_DAPM_SINGLE("Mono Playback Switch", AK4641_SIG1, 5, 1, 0),
};
/* Stereo Mixer */
static const struct snd_kcontrol_new ak4641_stereo_mixer_controls[] = {
SOC_DAPM_SINGLE_TLV("Mic Sidetone Volume", AK4641_VOL, 4, 7, 0,
mic_stereo_sidetone_tlv),
SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4641_SIG2, 4, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", AK4641_SIG2, 7, 1, 0),
SOC_DAPM_SINGLE("Aux Bypass Switch", AK4641_SIG2, 5, 1, 0),
};
/* Input Mixer */
static const struct snd_kcontrol_new ak4641_input_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Capture Switch", AK4641_MIC, 2, 1, 0),
SOC_DAPM_SINGLE("Aux Capture Switch", AK4641_MIC, 5, 1, 0),
};
/* Mic mux */
static const struct snd_kcontrol_new ak4641_mic_mux_control =
SOC_DAPM_ENUM("Mic Select", ak4641_mic_select_enum);
/* Input mux */
static const struct snd_kcontrol_new ak4641_input_mux_control =
SOC_DAPM_ENUM("Input Select", ak4641_mic_or_dac_enum);
/* mono 2 switch */
static const struct snd_kcontrol_new ak4641_mono2_control =
SOC_DAPM_SINGLE("Switch", AK4641_SIG1, 0, 1, 0);
/* ak4641 dapm widgets */
static const struct snd_soc_dapm_widget ak4641_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Stereo Mixer", SND_SOC_NOPM, 0, 0,
&ak4641_stereo_mixer_controls[0],
ARRAY_SIZE(ak4641_stereo_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono1 Mixer", SND_SOC_NOPM, 0, 0,
&ak4641_mono1_mixer_controls[0],
ARRAY_SIZE(ak4641_mono1_mixer_controls)),
SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0,
&ak4641_input_mixer_controls[0],
ARRAY_SIZE(ak4641_input_mixer_controls)),
SND_SOC_DAPM_MUX("Mic Mux", SND_SOC_NOPM, 0, 0,
&ak4641_mic_mux_control),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&ak4641_input_mux_control),
SND_SOC_DAPM_SWITCH("Mono 2 Enable", SND_SOC_NOPM, 0, 0,
&ak4641_mono2_control),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("MOUT1"),
SND_SOC_DAPM_OUTPUT("MOUT2"),
SND_SOC_DAPM_OUTPUT("MICOUT"),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", AK4641_PM1, 0, 0),
SND_SOC_DAPM_PGA("Mic", AK4641_PM1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX In", AK4641_PM1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", AK4641_PM1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line Out", AK4641_PM1, 4, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", AK4641_PM2, 0, 0),
SND_SOC_DAPM_PGA("Mono Out 2", AK4641_PM2, 3, 0, NULL, 0),
SND_SOC_DAPM_ADC("Voice ADC", "Voice Capture", AK4641_BTIF, 0, 0),
SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", AK4641_BTIF, 1, 0),
SND_SOC_DAPM_MICBIAS("Mic Int Bias", AK4641_MIC, 3, 0),
SND_SOC_DAPM_MICBIAS("Mic Ext Bias", AK4641_MIC, 4, 0),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("MICEXT"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("AIN"),
};
static const struct snd_soc_dapm_route ak4641_audio_map[] = {
/* Stereo Mixer */
{"Stereo Mixer", "Playback Switch", "DAC"},
{"Stereo Mixer", "Mic Sidetone Switch", "Input Mux"},
{"Stereo Mixer", "Aux Bypass Switch", "AUX In"},
/* Mono 1 Mixer */
{"Mono1 Mixer", "Mic Mono Sidetone Switch", "Input Mux"},
{"Mono1 Mixer", "Mono Playback Switch", "DAC"},
/* Mic */
{"Mic", NULL, "AIN"},
{"Mic Mux", "Internal", "Mic Int Bias"},
{"Mic Mux", "External", "Mic Ext Bias"},
{"Mic Int Bias", NULL, "MICIN"},
{"Mic Ext Bias", NULL, "MICEXT"},
{"MICOUT", NULL, "Mic Mux"},
/* Input Mux */
{"Input Mux", "Microphone", "Mic"},
{"Input Mux", "Voice DAC", "Voice DAC"},
/* Line Out */
{"LOUT", NULL, "Line Out"},
{"ROUT", NULL, "Line Out"},
{"Line Out", NULL, "Stereo Mixer"},
/* Mono 1 Out */
{"MOUT1", NULL, "Mono Out"},
{"Mono Out", NULL, "Mono1 Mixer"},
/* Mono 2 Out */
{"MOUT2", NULL, "Mono 2 Enable"},
{"Mono 2 Enable", "Switch", "Mono Out 2"},
{"Mono Out 2", NULL, "Stereo Mixer"},
{"Voice ADC", NULL, "Mono 2 Enable"},
/* Aux In */
{"AUX In", NULL, "AUX"},
/* ADC */
{"ADC", NULL, "Input Mixer"},
{"Input Mixer", "Mic Capture Switch", "Mic"},
{"Input Mixer", "Aux Capture Switch", "AUX In"},
};
static int ak4641_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
ak4641->sysclk = freq;
return 0;
}
static int ak4641_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
int rate = params_rate(params), fs = 256;
u8 mode2;
if (rate)
fs = ak4641->sysclk / rate;
else
return -EINVAL;
/* set fs */
switch (fs) {
case 1024:
mode2 = (0x2 << 5);
break;
case 512:
mode2 = (0x1 << 5);
break;
case 256:
mode2 = (0x0 << 5);
break;
default:
dev_err(codec->dev, "Error: unsupported fs=%d\n", fs);
return -EINVAL;
}
snd_soc_update_bits(codec, AK4641_MODE2, (0x3 << 5), mode2);
/* Update de-emphasis filter for the new rate */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ak4641->playback_fs = rate;
ak4641_set_deemph(codec);
};
return 0;
}
static int ak4641_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u8 btif;
int ret;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
btif = (0x3 << 5);
break;
case SND_SOC_DAIFMT_LEFT_J:
btif = (0x2 << 5);
break;
case SND_SOC_DAIFMT_DSP_A: /* MSB after FRM */
btif = (0x0 << 5);
break;
case SND_SOC_DAIFMT_DSP_B: /* MSB during FRM */
btif = (0x1 << 5);
break;
default:
return -EINVAL;
}
ret = snd_soc_update_bits(codec, AK4641_BTIF, (0x3 << 5), btif);
if (ret < 0)
return ret;
return 0;
}
static int ak4641_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u8 mode1 = 0;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
mode1 = 0x02;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode1 = 0x01;
break;
default:
return -EINVAL;
}
return snd_soc_write(codec, AK4641_MODE1, mode1);
}
static int ak4641_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
return snd_soc_update_bits(codec, AK4641_DAC, 0x20, mute ? 0x20 : 0);
}
static int ak4641_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct ak4641_platform_data *pdata = codec->dev->platform_data;
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
/* unmute */
snd_soc_update_bits(codec, AK4641_DAC, 0x20, 0);
break;
case SND_SOC_BIAS_PREPARE:
/* mute */
snd_soc_update_bits(codec, AK4641_DAC, 0x20, 0x20);
break;
case SND_SOC_BIAS_STANDBY:
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
if (pdata && gpio_is_valid(pdata->gpio_power))
gpio_set_value(pdata->gpio_power, 1);
mdelay(1);
if (pdata && gpio_is_valid(pdata->gpio_npdn))
gpio_set_value(pdata->gpio_npdn, 1);
mdelay(1);
ret = snd_soc_cache_sync(codec);
if (ret) {
dev_err(codec->dev,
"Failed to sync cache: %d\n", ret);
return ret;
}
}
snd_soc_update_bits(codec, AK4641_PM1, 0x80, 0x80);
snd_soc_update_bits(codec, AK4641_PM2, 0x80, 0);
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, AK4641_PM1, 0x80, 0);
if (pdata && gpio_is_valid(pdata->gpio_npdn))
gpio_set_value(pdata->gpio_npdn, 0);
if (pdata && gpio_is_valid(pdata->gpio_power))
gpio_set_value(pdata->gpio_power, 0);
codec->cache_sync = 1;
break;
}
codec->dapm.bias_level = level;
return 0;
}
#define AK4641_RATES (SNDRV_PCM_RATE_8000_48000)
#define AK4641_RATES_BT (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000)
#define AK4641_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
static const struct snd_soc_dai_ops ak4641_i2s_dai_ops = {
.hw_params = ak4641_i2s_hw_params,
.set_fmt = ak4641_i2s_set_dai_fmt,
.digital_mute = ak4641_mute,
.set_sysclk = ak4641_set_dai_sysclk,
};
static const struct snd_soc_dai_ops ak4641_pcm_dai_ops = {
.hw_params = NULL, /* rates are controlled by BT chip */
.set_fmt = ak4641_pcm_set_dai_fmt,
.digital_mute = ak4641_mute,
.set_sysclk = ak4641_set_dai_sysclk,
};
static struct snd_soc_dai_driver ak4641_dai[] = {
{
.name = "ak4641-hifi",
.id = 1,
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AK4641_RATES,
.formats = AK4641_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AK4641_RATES,
.formats = AK4641_FORMATS,
},
.ops = &ak4641_i2s_dai_ops,
.symmetric_rates = 1,
},
{
.name = "ak4641-voice",
.id = 1,
.playback = {
.stream_name = "Voice Playback",
.channels_min = 1,
.channels_max = 1,
.rates = AK4641_RATES_BT,
.formats = AK4641_FORMATS,
},
.capture = {
.stream_name = "Voice Capture",
.channels_min = 1,
.channels_max = 1,
.rates = AK4641_RATES_BT,
.formats = AK4641_FORMATS,
},
.ops = &ak4641_pcm_dai_ops,
.symmetric_rates = 1,
},
};
static int ak4641_suspend(struct snd_soc_codec *codec)
{
ak4641_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int ak4641_resume(struct snd_soc_codec *codec)
{
ak4641_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
static int ak4641_probe(struct snd_soc_codec *codec)
{
int ret;
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
if (ret != 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
return ret;
}
/* power on device */
ak4641_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
static int ak4641_remove(struct snd_soc_codec *codec)
{
ak4641_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static struct snd_soc_codec_driver soc_codec_dev_ak4641 = {
.probe = ak4641_probe,
.remove = ak4641_remove,
.suspend = ak4641_suspend,
.resume = ak4641_resume,
.controls = ak4641_snd_controls,
.num_controls = ARRAY_SIZE(ak4641_snd_controls),
.dapm_widgets = ak4641_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4641_dapm_widgets),
.dapm_routes = ak4641_audio_map,
.num_dapm_routes = ARRAY_SIZE(ak4641_audio_map),
.set_bias_level = ak4641_set_bias_level,
.reg_cache_size = ARRAY_SIZE(ak4641_reg),
.reg_word_size = sizeof(u8),
.reg_cache_default = ak4641_reg,
.reg_cache_step = 1,
};
static int __devinit ak4641_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct ak4641_platform_data *pdata = i2c->dev.platform_data;
struct ak4641_priv *ak4641;
int ret;
ak4641 = devm_kzalloc(&i2c->dev, sizeof(struct ak4641_priv),
GFP_KERNEL);
if (!ak4641)
return -ENOMEM;
if (pdata) {
if (gpio_is_valid(pdata->gpio_power)) {
ret = gpio_request_one(pdata->gpio_power,
GPIOF_OUT_INIT_LOW, "ak4641 power");
if (ret)
goto err_out;
}
if (gpio_is_valid(pdata->gpio_npdn)) {
ret = gpio_request_one(pdata->gpio_npdn,
GPIOF_OUT_INIT_LOW, "ak4641 npdn");
if (ret)
goto err_gpio;
udelay(1); /* > 150 ns */
gpio_set_value(pdata->gpio_npdn, 1);
}
}
i2c_set_clientdata(i2c, ak4641);
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_ak4641,
ak4641_dai, ARRAY_SIZE(ak4641_dai));
if (ret != 0)
goto err_gpio2;
return 0;
err_gpio2:
if (pdata) {
if (gpio_is_valid(pdata->gpio_power))
gpio_set_value(pdata->gpio_power, 0);
if (gpio_is_valid(pdata->gpio_npdn))
gpio_free(pdata->gpio_npdn);
}
err_gpio:
if (pdata && gpio_is_valid(pdata->gpio_power))
gpio_free(pdata->gpio_power);
err_out:
return ret;
}
static int __devexit ak4641_i2c_remove(struct i2c_client *i2c)
{
struct ak4641_platform_data *pdata = i2c->dev.platform_data;
snd_soc_unregister_codec(&i2c->dev);
if (pdata) {
if (gpio_is_valid(pdata->gpio_power)) {
gpio_set_value(pdata->gpio_power, 0);
gpio_free(pdata->gpio_power);
}
if (gpio_is_valid(pdata->gpio_npdn))
gpio_free(pdata->gpio_npdn);
}
return 0;
}
static const struct i2c_device_id ak4641_i2c_id[] = {
{ "ak4641", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4641_i2c_id);
static struct i2c_driver ak4641_i2c_driver = {
.driver = {
.name = "ak4641",
.owner = THIS_MODULE,
},
.probe = ak4641_i2c_probe,
.remove = __devexit_p(ak4641_i2c_remove),
.id_table = ak4641_i2c_id,
};
module_i2c_driver(ak4641_i2c_driver);
MODULE_DESCRIPTION("SoC AK4641 driver");
MODULE_AUTHOR("Harald Welte <laforge@gnufiish.org>");
MODULE_LICENSE("GPL");
| gpl-2.0 |
vakkov/kernel-adaptation-n900 | drivers/net/wireless/iwlwifi/iwl-agn-rx.c | 175 | 11470 | /******************************************************************************
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
* USA
*
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Intel Linux Wireless <ilw@linux.intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-agn-calib.h"
#include "iwl-sta.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-agn-hw.h"
#include "iwl-agn.h"
void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
struct iwl_rx_mem_buffer *rxb)
{
struct iwl_rx_packet *pkt = rxb_addr(rxb);
struct iwl_missed_beacon_notif *missed_beacon;
missed_beacon = &pkt->u.missed_beacon;
if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
priv->missed_beacon_threshold) {
IWL_DEBUG_CALIB(priv,
"missed bcn cnsq %d totl %d rcd %d expctd %d\n",
le32_to_cpu(missed_beacon->consecutive_missed_beacons),
le32_to_cpu(missed_beacon->total_missed_becons),
le32_to_cpu(missed_beacon->num_recvd_beacons),
le32_to_cpu(missed_beacon->num_expected_beacons));
if (!test_bit(STATUS_SCANNING, &priv->status))
iwl_init_sensitivity(priv);
}
}
/* Calculate noise level, based on measurements during network silence just
* before arriving beacon. This measurement can be done only if we know
* exactly when to expect beacons, therefore only when we're associated. */
static void iwl_rx_calc_noise(struct iwl_priv *priv)
{
struct statistics_rx_non_phy *rx_info;
int num_active_rx = 0;
int total_silence = 0;
int bcn_silence_a, bcn_silence_b, bcn_silence_c;
int last_rx_noise;
if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics)
rx_info = &(priv->_agn.statistics_bt.rx.general.common);
else
rx_info = &(priv->_agn.statistics.rx.general);
bcn_silence_a =
le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
bcn_silence_b =
le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
bcn_silence_c =
le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
if (bcn_silence_a) {
total_silence += bcn_silence_a;
num_active_rx++;
}
if (bcn_silence_b) {
total_silence += bcn_silence_b;
num_active_rx++;
}
if (bcn_silence_c) {
total_silence += bcn_silence_c;
num_active_rx++;
}
/* Average among active antennas */
if (num_active_rx)
last_rx_noise = (total_silence / num_active_rx) - 107;
else
last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n",
bcn_silence_a, bcn_silence_b, bcn_silence_c,
last_rx_noise);
}
#ifdef CONFIG_IWLWIFI_DEBUGFS
/*
* based on the assumption of all statistics counter are in DWORD
* FIXME: This function is for debugging, do not deal with
* the case of counters roll-over.
*/
static void iwl_accumulative_statistics(struct iwl_priv *priv,
__le32 *stats)
{
int i, size;
__le32 *prev_stats;
u32 *accum_stats;
u32 *delta, *max_delta;
struct statistics_general_common *general, *accum_general;
struct statistics_tx *tx, *accum_tx;
if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
prev_stats = (__le32 *)&priv->_agn.statistics_bt;
accum_stats = (u32 *)&priv->_agn.accum_statistics_bt;
size = sizeof(struct iwl_bt_notif_statistics);
general = &priv->_agn.statistics_bt.general.common;
accum_general = &priv->_agn.accum_statistics_bt.general.common;
tx = &priv->_agn.statistics_bt.tx;
accum_tx = &priv->_agn.accum_statistics_bt.tx;
delta = (u32 *)&priv->_agn.delta_statistics_bt;
max_delta = (u32 *)&priv->_agn.max_delta_bt;
} else {
prev_stats = (__le32 *)&priv->_agn.statistics;
accum_stats = (u32 *)&priv->_agn.accum_statistics;
size = sizeof(struct iwl_notif_statistics);
general = &priv->_agn.statistics.general.common;
accum_general = &priv->_agn.accum_statistics.general.common;
tx = &priv->_agn.statistics.tx;
accum_tx = &priv->_agn.accum_statistics.tx;
delta = (u32 *)&priv->_agn.delta_statistics;
max_delta = (u32 *)&priv->_agn.max_delta;
}
for (i = sizeof(__le32); i < size;
i += sizeof(__le32), stats++, prev_stats++, delta++,
max_delta++, accum_stats++) {
if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
*delta = (le32_to_cpu(*stats) -
le32_to_cpu(*prev_stats));
*accum_stats += *delta;
if (*delta > *max_delta)
*max_delta = *delta;
}
}
/* reset accumulative statistics for "no-counter" type statistics */
accum_general->temperature = general->temperature;
accum_general->temperature_m = general->temperature_m;
accum_general->ttl_timestamp = general->ttl_timestamp;
accum_tx->tx_power.ant_a = tx->tx_power.ant_a;
accum_tx->tx_power.ant_b = tx->tx_power.ant_b;
accum_tx->tx_power.ant_c = tx->tx_power.ant_c;
}
#endif
#define REG_RECALIB_PERIOD (60)
/**
* iwl_good_plcp_health - checks for plcp error.
*
* When the plcp error is exceeding the thresholds, reset the radio
* to improve the throughput.
*/
bool iwl_good_plcp_health(struct iwl_priv *priv,
struct iwl_rx_packet *pkt)
{
bool rc = true;
int combined_plcp_delta;
unsigned int plcp_msec;
unsigned long plcp_received_jiffies;
if (priv->cfg->base_params->plcp_delta_threshold ==
IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
return rc;
}
/*
* check for plcp_err and trigger radio reset if it exceeds
* the plcp error threshold plcp_delta.
*/
plcp_received_jiffies = jiffies;
plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
(long) priv->plcp_jiffies);
priv->plcp_jiffies = plcp_received_jiffies;
/*
* check to make sure plcp_msec is not 0 to prevent division
* by zero.
*/
if (plcp_msec) {
struct statistics_rx_phy *ofdm;
struct statistics_rx_ht_phy *ofdm_ht;
if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
ofdm = &pkt->u.stats_bt.rx.ofdm;
ofdm_ht = &pkt->u.stats_bt.rx.ofdm_ht;
combined_plcp_delta =
(le32_to_cpu(ofdm->plcp_err) -
le32_to_cpu(priv->_agn.statistics_bt.
rx.ofdm.plcp_err)) +
(le32_to_cpu(ofdm_ht->plcp_err) -
le32_to_cpu(priv->_agn.statistics_bt.
rx.ofdm_ht.plcp_err));
} else {
ofdm = &pkt->u.stats.rx.ofdm;
ofdm_ht = &pkt->u.stats.rx.ofdm_ht;
combined_plcp_delta =
(le32_to_cpu(ofdm->plcp_err) -
le32_to_cpu(priv->_agn.statistics.
rx.ofdm.plcp_err)) +
(le32_to_cpu(ofdm_ht->plcp_err) -
le32_to_cpu(priv->_agn.statistics.
rx.ofdm_ht.plcp_err));
}
if ((combined_plcp_delta > 0) &&
((combined_plcp_delta * 100) / plcp_msec) >
priv->cfg->base_params->plcp_delta_threshold) {
/*
* if plcp_err exceed the threshold,
* the following data is printed in csv format:
* Text: plcp_err exceeded %d,
* Received ofdm.plcp_err,
* Current ofdm.plcp_err,
* Received ofdm_ht.plcp_err,
* Current ofdm_ht.plcp_err,
* combined_plcp_delta,
* plcp_msec
*/
IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
"%u, %u, %u, %u, %d, %u mSecs\n",
priv->cfg->base_params->plcp_delta_threshold,
le32_to_cpu(ofdm->plcp_err),
le32_to_cpu(ofdm->plcp_err),
le32_to_cpu(ofdm_ht->plcp_err),
le32_to_cpu(ofdm_ht->plcp_err),
combined_plcp_delta, plcp_msec);
rc = false;
}
}
return rc;
}
void iwl_rx_statistics(struct iwl_priv *priv,
struct iwl_rx_mem_buffer *rxb)
{
int change;
struct iwl_rx_packet *pkt = rxb_addr(rxb);
if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
IWL_DEBUG_RX(priv,
"Statistics notification received (%d vs %d).\n",
(int)sizeof(struct iwl_bt_notif_statistics),
le32_to_cpu(pkt->len_n_flags) &
FH_RSCSR_FRAME_SIZE_MSK);
change = ((priv->_agn.statistics_bt.general.common.temperature !=
pkt->u.stats_bt.general.common.temperature) ||
((priv->_agn.statistics_bt.flag &
STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
(pkt->u.stats_bt.flag &
STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
#ifdef CONFIG_IWLWIFI_DEBUGFS
iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats_bt);
#endif
} else {
IWL_DEBUG_RX(priv,
"Statistics notification received (%d vs %d).\n",
(int)sizeof(struct iwl_notif_statistics),
le32_to_cpu(pkt->len_n_flags) &
FH_RSCSR_FRAME_SIZE_MSK);
change = ((priv->_agn.statistics.general.common.temperature !=
pkt->u.stats.general.common.temperature) ||
((priv->_agn.statistics.flag &
STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
(pkt->u.stats.flag &
STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
#ifdef CONFIG_IWLWIFI_DEBUGFS
iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats);
#endif
}
iwl_recover_from_statistics(priv, pkt);
if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics)
memcpy(&priv->_agn.statistics_bt, &pkt->u.stats_bt,
sizeof(priv->_agn.statistics_bt));
else
memcpy(&priv->_agn.statistics, &pkt->u.stats,
sizeof(priv->_agn.statistics));
set_bit(STATUS_STATISTICS, &priv->status);
/* Reschedule the statistics timer to occur in
* REG_RECALIB_PERIOD seconds to ensure we get a
* thermal update even if the uCode doesn't give
* us one */
mod_timer(&priv->statistics_periodic, jiffies +
msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
(pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
iwl_rx_calc_noise(priv);
queue_work(priv->workqueue, &priv->run_time_calib_work);
}
if (priv->cfg->ops->lib->temp_ops.temperature && change)
priv->cfg->ops->lib->temp_ops.temperature(priv);
}
void iwl_reply_statistics(struct iwl_priv *priv,
struct iwl_rx_mem_buffer *rxb)
{
struct iwl_rx_packet *pkt = rxb_addr(rxb);
if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) {
#ifdef CONFIG_IWLWIFI_DEBUGFS
memset(&priv->_agn.accum_statistics, 0,
sizeof(struct iwl_notif_statistics));
memset(&priv->_agn.delta_statistics, 0,
sizeof(struct iwl_notif_statistics));
memset(&priv->_agn.max_delta, 0,
sizeof(struct iwl_notif_statistics));
memset(&priv->_agn.accum_statistics_bt, 0,
sizeof(struct iwl_bt_notif_statistics));
memset(&priv->_agn.delta_statistics_bt, 0,
sizeof(struct iwl_bt_notif_statistics));
memset(&priv->_agn.max_delta_bt, 0,
sizeof(struct iwl_bt_notif_statistics));
#endif
IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
}
iwl_rx_statistics(priv, rxb);
}
| gpl-2.0 |
MTDEV-KERNEL/abenagiel-android_kernel_fih_msm7x30 | arch/arm/mach-msm/qdsp6v2/audio_mvs.c | 175 | 23212 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/list.h>
#include <linux/uaccess.h>
#include <linux/mutex.h>
#include <linux/wakelock.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/msm_audio_mvs.h>
#include <mach/qdsp6v2/q6voice.h>
/* Each buffer is 20 ms, queue holds 200 ms of data. */
#define MVS_MAX_Q_LEN 10
/* Length of the DSP frame info header added to the voc packet. */
#define DSP_FRAME_HDR_LEN 1
enum audio_mvs_state_type {
AUDIO_MVS_CLOSED,
AUDIO_MVS_STARTED,
AUDIO_MVS_STOPPED
};
struct audio_mvs_buf_node {
struct list_head list;
struct msm_audio_mvs_frame frame;
};
struct audio_mvs_info_type {
enum audio_mvs_state_type state;
uint32_t mvs_mode;
uint32_t rate_type;
struct list_head in_queue;
struct list_head free_in_queue;
struct list_head out_queue;
struct list_head free_out_queue;
wait_queue_head_t out_wait;
struct mutex lock;
struct mutex in_lock;
struct mutex out_lock;
spinlock_t dsp_lock;
struct wake_lock suspend_lock;
struct wake_lock idle_lock;
void *memory_chunk;
};
static struct audio_mvs_info_type audio_mvs_info;
static uint32_t audio_mvs_get_rate(uint32_t mvs_mode, uint32_t rate_type)
{
uint32_t cvs_rate;
if (mvs_mode == MVS_MODE_AMR_WB)
cvs_rate = rate_type - MVS_AMR_MODE_0660;
else
cvs_rate = rate_type;
pr_debug("%s: CVS rate is %d for MVS mode %d\n",
__func__, cvs_rate, mvs_mode);
return cvs_rate;
}
static void audio_mvs_process_ul_pkt(uint8_t *voc_pkt,
uint32_t pkt_len,
void *private_data)
{
struct audio_mvs_buf_node *buf_node = NULL;
struct audio_mvs_info_type *audio = private_data;
unsigned long dsp_flags;
/* Copy up-link packet into out_queue. */
spin_lock_irqsave(&audio->dsp_lock, dsp_flags);
if (!list_empty(&audio->free_out_queue)) {
buf_node = list_first_entry(&audio->free_out_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
switch (audio->mvs_mode) {
case MVS_MODE_AMR:
case MVS_MODE_AMR_WB: {
/* Remove the DSP frame info header. Header format:
* Bits 0-3: Frame rate
* Bits 4-7: Frame type
*/
buf_node->frame.frame_type = ((*voc_pkt) & 0xF0) >> 4;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
buf_node->frame.len = pkt_len - DSP_FRAME_HDR_LEN;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
list_add_tail(&buf_node->list, &audio->out_queue);
break;
}
case MVS_MODE_IS127: {
buf_node->frame.frame_type = 0;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
buf_node->frame.len = pkt_len - DSP_FRAME_HDR_LEN;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
list_add_tail(&buf_node->list, &audio->out_queue);
break;
}
case MVS_MODE_G729A: {
/* G729 frames are 10ms each, but the DSP works with
* 20ms frames and sends two 10ms frames per buffer.
* Extract the two frames and put them in separate
* buffers.
*/
/* Remove the first DSP frame info header.
* Header format:
* Bits 0-1: Frame type
*/
buf_node->frame.frame_type = (*voc_pkt) & 0x03;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
/* There are two frames in the buffer. Length of the
* first frame:
*/
buf_node->frame.len = (pkt_len -
2 * DSP_FRAME_HDR_LEN) / 2;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
voc_pkt = voc_pkt + buf_node->frame.len;
list_add_tail(&buf_node->list, &audio->out_queue);
/* Get another buffer from the free Q and fill in the
* second frame.
*/
if (!list_empty(&audio->free_out_queue)) {
buf_node =
list_first_entry(&audio->free_out_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
/* Remove the second DSP frame info header.
* Header format:
* Bits 0-1: Frame type
*/
buf_node->frame.frame_type = (*voc_pkt) & 0x03;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
/* There are two frames in the buffer. Length
* of the first frame:
*/
buf_node->frame.len = (pkt_len -
2 * DSP_FRAME_HDR_LEN) / 2;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
list_add_tail(&buf_node->list,
&audio->out_queue);
} else {
/* Drop the second frame. */
pr_err("%s: UL data dropped, read is slow\n",
__func__);
}
break;
}
case MVS_MODE_G711A: {
/* G711 frames are 10ms each, but the DSP works with
* 20ms frames and sends two 10ms frames per buffer.
* Extract the two frames and put them in separate
* buffers.
*/
/* Remove the first DSP frame info header.
* Header format:
* Bits 0-1: Frame type
* Bits 2-3: Frame rate
*/
buf_node->frame.frame_type = (*voc_pkt) & 0x03;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
/* There are two frames in the buffer. Length of the
* first frame:
*/
buf_node->frame.len = (pkt_len -
2 * DSP_FRAME_HDR_LEN) / 2;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
voc_pkt = voc_pkt + buf_node->frame.len;
list_add_tail(&buf_node->list, &audio->out_queue);
/* Get another buffer from the free Q and fill in the
* second frame.
*/
if (!list_empty(&audio->free_out_queue)) {
buf_node =
list_first_entry(&audio->free_out_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
/* Remove the second DSP frame info header.
* Header format:
* Bits 0-1: Frame type
* Bits 2-3: Frame rate
*/
buf_node->frame.frame_type = (*voc_pkt) & 0x03;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
/* There are two frames in the buffer. Length
* of the second frame:
*/
buf_node->frame.len = (pkt_len -
2 * DSP_FRAME_HDR_LEN) / 2;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
list_add_tail(&buf_node->list,
&audio->out_queue);
} else {
/* Drop the second frame. */
pr_err("%s: UL data dropped, read is slow\n",
__func__);
}
break;
}
default: {
buf_node->frame.frame_type = 0;
buf_node->frame.len = pkt_len;
memcpy(&buf_node->frame.voc_pkt[0],
voc_pkt,
buf_node->frame.len);
list_add_tail(&buf_node->list, &audio->out_queue);
}
}
} else {
pr_err("%s: UL data dropped, read is slow\n", __func__);
}
spin_unlock_irqrestore(&audio->dsp_lock, dsp_flags);
wake_up(&audio->out_wait);
}
static void audio_mvs_process_dl_pkt(uint8_t *voc_pkt,
uint32_t *pkt_len,
void *private_data)
{
struct audio_mvs_buf_node *buf_node = NULL;
struct audio_mvs_info_type *audio = private_data;
unsigned long dsp_flags;
spin_lock_irqsave(&audio->dsp_lock, dsp_flags);
if (!list_empty(&audio->in_queue)) {
uint32_t rate_type = audio_mvs_get_rate(audio->mvs_mode,
audio->rate_type);
buf_node = list_first_entry(&audio->in_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
switch (audio->mvs_mode) {
case MVS_MODE_AMR:
case MVS_MODE_AMR_WB: {
/* Add the DSP frame info header. Header format:
* Bits 0-3: Frame rate
* Bits 4-7: Frame type
*/
*voc_pkt = ((buf_node->frame.frame_type & 0x0F) << 4) |
(rate_type & 0x0F);
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
*pkt_len = buf_node->frame.len + DSP_FRAME_HDR_LEN;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
list_add_tail(&buf_node->list, &audio->free_in_queue);
break;
}
case MVS_MODE_IS127: {
/* Add the DSP frame info header. Header format:
* Bits 0-3: Frame rate
* Bits 4-7: Frame type
*/
*voc_pkt = rate_type & 0x0F;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
*pkt_len = buf_node->frame.len + DSP_FRAME_HDR_LEN;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
list_add_tail(&buf_node->list, &audio->free_in_queue);
break;
}
case MVS_MODE_G729A: {
/* G729 frames are 10ms each but the DSP expects 20ms
* worth of data, so send two 10ms frames per buffer.
*/
/* Add the first DSP frame info header. Header format:
* Bits 0-1: Frame type
*/
*voc_pkt = buf_node->frame.frame_type & 0x03;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
*pkt_len = buf_node->frame.len + DSP_FRAME_HDR_LEN;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
voc_pkt = voc_pkt + buf_node->frame.len;
list_add_tail(&buf_node->list, &audio->free_in_queue);
if (!list_empty(&audio->in_queue)) {
/* Get the second buffer. */
buf_node = list_first_entry(&audio->in_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
/* Add the second DSP frame info header.
* Header format:
* Bits 0-1: Frame type
*/
*voc_pkt = buf_node->frame.frame_type & 0x03;
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
*pkt_len = *pkt_len +
buf_node->frame.len + DSP_FRAME_HDR_LEN;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
list_add_tail(&buf_node->list,
&audio->free_in_queue);
} else {
/* Only 10ms worth of data is available, signal
* erasure frame.
*/
*voc_pkt = MVS_G729A_ERASURE & 0x03;
*pkt_len = *pkt_len + DSP_FRAME_HDR_LEN;
}
break;
}
case MVS_MODE_G711A: {
/* G711 frames are 10ms each but the DSP expects 20ms
* worth of data, so send two 10ms frames per buffer.
*/
/* Add the first DSP frame info header. Header format:
* Bits 0-1: Frame type
* Bits 2-3: Frame rate
*/
*voc_pkt = ((rate_type & 0x0F) << 2) |
(buf_node->frame.frame_type & 0x03);
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
*pkt_len = buf_node->frame.len + DSP_FRAME_HDR_LEN;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
voc_pkt = voc_pkt + buf_node->frame.len;
list_add_tail(&buf_node->list, &audio->free_in_queue);
if (!list_empty(&audio->in_queue)) {
/* Get the second buffer. */
buf_node = list_first_entry(&audio->in_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
/* Add the second DSP frame info header.
* Header format:
* Bits 0-1: Frame type
* Bits 2-3: Frame rate
*/
*voc_pkt = ((rate_type & 0x0F) << 2) |
(buf_node->frame.frame_type & 0x03);
voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
*pkt_len = *pkt_len +
buf_node->frame.len + DSP_FRAME_HDR_LEN;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
list_add_tail(&buf_node->list,
&audio->free_in_queue);
} else {
/* Only 10ms worth of data is available, signal
* erasure frame.
*/
*voc_pkt = ((rate_type & 0x0F) << 2) |
(MVS_G711A_ERASURE & 0x03);
*pkt_len = *pkt_len + DSP_FRAME_HDR_LEN;
}
break;
}
default: {
*pkt_len = buf_node->frame.len;
memcpy(voc_pkt,
&buf_node->frame.voc_pkt[0],
buf_node->frame.len);
list_add_tail(&buf_node->list, &audio->free_in_queue);
}
}
} else {
*pkt_len = 0;
pr_info("%s: No DL data available to send to MVS\n", __func__);
}
spin_unlock_irqrestore(&audio->dsp_lock, dsp_flags);
}
static uint32_t audio_mvs_get_media_type(uint32_t mvs_mode, uint32_t rate_type)
{
uint32_t media_type;
switch (mvs_mode) {
case MVS_MODE_IS127:
media_type = VSS_MEDIA_ID_EVRC_MODEM;
break;
case MVS_MODE_AMR:
media_type = VSS_MEDIA_ID_AMR_NB_MODEM;
break;
case MVS_MODE_LINEAR_PCM:
media_type = VSS_MEDIA_ID_PCM_NB;
break;
case MVS_MODE_PCM:
media_type = VSS_MEDIA_ID_PCM_NB;
break;
case MVS_MODE_AMR_WB:
media_type = VSS_MEDIA_ID_AMR_WB_MODEM;
break;
case MVS_MODE_G729A:
media_type = VSS_MEDIA_ID_G729;
break;
case MVS_MODE_G711A:
if (rate_type == MVS_G711A_MODE_MULAW)
media_type = VSS_MEDIA_ID_G711_MULAW;
else
media_type = VSS_MEDIA_ID_G711_ALAW;
break;
default:
media_type = VSS_MEDIA_ID_PCM_NB;
}
pr_debug("%s: media_type is 0x%x\n", __func__, media_type);
return media_type;
}
static uint32_t audio_mvs_get_network_type(uint32_t mvs_mode)
{
uint32_t network_type;
switch (mvs_mode) {
case MVS_MODE_IS127:
case MVS_MODE_AMR:
case MVS_MODE_LINEAR_PCM:
case MVS_MODE_PCM:
case MVS_MODE_G729A:
case MVS_MODE_G711A:
network_type = VSS_NETWORK_ID_VOIP_NB;
break;
case MVS_MODE_AMR_WB:
network_type = VSS_NETWORK_ID_VOIP_WB;
break;
default:
network_type = VSS_NETWORK_ID_DEFAULT;
}
pr_debug("%s: network_type is 0x%x\n", __func__, network_type);
return network_type;
}
static int audio_mvs_start(struct audio_mvs_info_type *audio)
{
int rc = 0;
pr_info("%s\n", __func__);
/* Prevent sleep. */
wake_lock(&audio->suspend_lock);
wake_lock(&audio->idle_lock);
rc = voice_set_voc_path_full(1);
if (rc == 0) {
voice_register_mvs_cb(audio_mvs_process_ul_pkt,
audio_mvs_process_dl_pkt,
audio);
voice_config_vocoder(
audio_mvs_get_media_type(audio->mvs_mode, audio->rate_type),
audio_mvs_get_rate(audio->mvs_mode, audio->rate_type),
audio_mvs_get_network_type(audio->mvs_mode));
audio->state = AUDIO_MVS_STARTED;
} else {
pr_err("%s: Error %d setting voc path to full\n", __func__, rc);
}
return rc;
}
static int audio_mvs_stop(struct audio_mvs_info_type *audio)
{
int rc = 0;
pr_info("%s\n", __func__);
voice_set_voc_path_full(0);
audio->state = AUDIO_MVS_STOPPED;
/* Allow sleep. */
wake_unlock(&audio->suspend_lock);
wake_unlock(&audio->idle_lock);
return rc;
}
static int audio_mvs_open(struct inode *inode, struct file *file)
{
int rc = 0;
int i;
int offset = 0;
struct audio_mvs_buf_node *buf_node = NULL;
pr_info("%s\n", __func__);
mutex_lock(&audio_mvs_info.lock);
/* Allocate input and output buffers. */
audio_mvs_info.memory_chunk = kmalloc(2 * MVS_MAX_Q_LEN *
sizeof(struct audio_mvs_buf_node),
GFP_KERNEL);
if (audio_mvs_info.memory_chunk != NULL) {
for (i = 0; i < MVS_MAX_Q_LEN; i++) {
buf_node = audio_mvs_info.memory_chunk + offset;
list_add_tail(&buf_node->list,
&audio_mvs_info.free_in_queue);
offset = offset + sizeof(struct audio_mvs_buf_node);
}
for (i = 0; i < MVS_MAX_Q_LEN; i++) {
buf_node = audio_mvs_info.memory_chunk + offset;
list_add_tail(&buf_node->list,
&audio_mvs_info.free_out_queue);
offset = offset + sizeof(struct audio_mvs_buf_node);
}
audio_mvs_info.state = AUDIO_MVS_STOPPED;
file->private_data = &audio_mvs_info;
} else {
pr_err("%s: No memory for IO buffers\n", __func__);
rc = -ENOMEM;
}
mutex_unlock(&audio_mvs_info.lock);
return rc;
}
static int audio_mvs_release(struct inode *inode, struct file *file)
{
struct list_head *ptr = NULL;
struct list_head *next = NULL;
struct audio_mvs_buf_node *buf_node = NULL;
struct audio_mvs_info_type *audio = file->private_data;
pr_info("%s\n", __func__);
mutex_lock(&audio->lock);
if (audio->state == AUDIO_MVS_STARTED)
audio_mvs_stop(audio);
/* Free input and output memory. */
mutex_lock(&audio->in_lock);
list_for_each_safe(ptr, next, &audio->in_queue) {
buf_node = list_entry(ptr, struct audio_mvs_buf_node, list);
list_del(&buf_node->list);
}
list_for_each_safe(ptr, next, &audio->free_in_queue) {
buf_node = list_entry(ptr, struct audio_mvs_buf_node, list);
list_del(&buf_node->list);
}
mutex_unlock(&audio->in_lock);
mutex_lock(&audio->out_lock);
list_for_each_safe(ptr, next, &audio->out_queue) {
buf_node = list_entry(ptr, struct audio_mvs_buf_node, list);
list_del(&buf_node->list);
}
list_for_each_safe(ptr, next, &audio->free_out_queue) {
buf_node = list_entry(ptr, struct audio_mvs_buf_node, list);
list_del(&buf_node->list);
}
mutex_unlock(&audio->out_lock);
kfree(audio->memory_chunk);
audio->memory_chunk = NULL;
audio->state = AUDIO_MVS_CLOSED;
mutex_unlock(&audio->lock);
return 0;
}
static ssize_t audio_mvs_read(struct file *file,
char __user *buf,
size_t count,
loff_t *pos)
{
int rc = 0;
struct audio_mvs_buf_node *buf_node = NULL;
struct audio_mvs_info_type *audio = file->private_data;
pr_debug("%s:\n", __func__);
rc = wait_event_interruptible_timeout(audio->out_wait,
(!list_empty(&audio->out_queue) ||
audio->state == AUDIO_MVS_STOPPED),
1 * HZ);
if (rc > 0) {
mutex_lock(&audio->out_lock);
if ((audio->state == AUDIO_MVS_STARTED) &&
(!list_empty(&audio->out_queue))) {
if (count >= sizeof(struct msm_audio_mvs_frame)) {
buf_node = list_first_entry(&audio->out_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
rc = copy_to_user(buf,
&buf_node->frame,
sizeof(struct msm_audio_mvs_frame));
if (rc == 0) {
rc = buf_node->frame.len +
sizeof(buf_node->frame.frame_type) +
sizeof(buf_node->frame.len);
} else {
pr_err("%s: Copy to user retuned %d",
__func__, rc);
rc = -EFAULT;
}
list_add_tail(&buf_node->list,
&audio->free_out_queue);
} else {
pr_err("%s: Read count %d < sizeof(frame) %d",
__func__, count,
sizeof(struct msm_audio_mvs_frame));
rc = -ENOMEM;
}
} else {
pr_err("%s: Read performed in state %d\n",
__func__, audio->state);
rc = -EPERM;
}
mutex_unlock(&audio->out_lock);
} else if (rc == 0) {
pr_err("%s: No UL data available\n", __func__);
rc = -ETIMEDOUT;
} else {
pr_err("%s: Read was interrupted\n", __func__);
rc = -ERESTARTSYS;
}
return rc;
}
static ssize_t audio_mvs_write(struct file *file,
const char __user *buf,
size_t count,
loff_t *pos)
{
int rc = 0;
struct audio_mvs_buf_node *buf_node = NULL;
struct audio_mvs_info_type *audio = file->private_data;
pr_debug("%s:\n", __func__);
mutex_lock(&audio->in_lock);
if (audio->state == AUDIO_MVS_STARTED) {
if (count <= sizeof(struct msm_audio_mvs_frame)) {
if (!list_empty(&audio->free_in_queue)) {
buf_node =
list_first_entry(&audio->free_in_queue,
struct audio_mvs_buf_node,
list);
list_del(&buf_node->list);
rc = copy_from_user(&buf_node->frame,
buf,
count);
list_add_tail(&buf_node->list,
&audio->in_queue);
} else {
pr_err("%s: No free DL buffs\n", __func__);
}
} else {
pr_err("%s: Write count %d < sizeof(frame) %d",
__func__, count,
sizeof(struct msm_audio_mvs_frame));
rc = -ENOMEM;
}
} else {
pr_err("%s: Write performed in invalid state %d\n",
__func__, audio->state);
rc = -EPERM;
}
mutex_unlock(&audio->in_lock);
return rc;
}
static long audio_mvs_ioctl(struct file *file,
unsigned int cmd,
unsigned long arg)
{
int rc = 0;
struct audio_mvs_info_type *audio = file->private_data;
pr_info("%s:\n", __func__);
switch (cmd) {
case AUDIO_GET_MVS_CONFIG: {
struct msm_audio_mvs_config config;
pr_info("%s: IOCTL GET_MVS_CONFIG\n", __func__);
mutex_lock(&audio->lock);
config.mvs_mode = audio->mvs_mode;
config.rate_type = audio->rate_type;
mutex_unlock(&audio->lock);
rc = copy_to_user((void *)arg, &config, sizeof(config));
if (rc == 0)
rc = sizeof(config);
else
pr_err("%s: Config copy failed %d\n", __func__, rc);
break;
}
case AUDIO_SET_MVS_CONFIG: {
struct msm_audio_mvs_config config;
pr_info("%s: IOCTL SET_MVS_CONFIG\n", __func__);
rc = copy_from_user(&config, (void *)arg, sizeof(config));
if (rc == 0) {
mutex_lock(&audio->lock);
if (audio->state == AUDIO_MVS_STOPPED) {
audio->mvs_mode = config.mvs_mode;
audio->rate_type = config.rate_type;
} else {
pr_err("%s: Set confg called in state %d\n",
__func__, audio->state);
rc = -EPERM;
}
mutex_unlock(&audio->lock);
} else {
pr_err("%s: Config copy failed %d\n", __func__, rc);
}
break;
}
case AUDIO_START: {
pr_info("%s: IOCTL START\n", __func__);
mutex_lock(&audio->lock);
if (audio->state == AUDIO_MVS_STOPPED) {
rc = audio_mvs_start(audio);
if (rc != 0)
audio_mvs_stop(audio);
} else {
pr_err("%s: Start called in invalid state %d\n",
__func__, audio->state);
rc = -EPERM;
}
mutex_unlock(&audio->lock);
break;
}
case AUDIO_STOP: {
pr_info("%s: IOCTL STOP\n", __func__);
mutex_lock(&audio->lock);
if (audio->state == AUDIO_MVS_STARTED) {
rc = audio_mvs_stop(audio);
} else {
pr_err("%s: Stop called in invalid state %d\n",
__func__, audio->state);
rc = -EPERM;
}
mutex_unlock(&audio->lock);
break;
}
default: {
pr_err("%s: Unknown IOCTL %d\n", __func__, cmd);
}
}
return rc;
}
static const struct file_operations audio_mvs_fops = {
.owner = THIS_MODULE,
.open = audio_mvs_open,
.release = audio_mvs_release,
.read = audio_mvs_read,
.write = audio_mvs_write,
.unlocked_ioctl = audio_mvs_ioctl
};
struct miscdevice audio_mvs_misc = {
.minor = MISC_DYNAMIC_MINOR,
.name = "msm_mvs",
.fops = &audio_mvs_fops
};
static int __init audio_mvs_init(void)
{
int rc = 0;
memset(&audio_mvs_info, 0, sizeof(audio_mvs_info));
init_waitqueue_head(&audio_mvs_info.out_wait);
mutex_init(&audio_mvs_info.lock);
mutex_init(&audio_mvs_info.in_lock);
mutex_init(&audio_mvs_info.out_lock);
spin_lock_init(&audio_mvs_info.dsp_lock);
INIT_LIST_HEAD(&audio_mvs_info.in_queue);
INIT_LIST_HEAD(&audio_mvs_info.free_in_queue);
INIT_LIST_HEAD(&audio_mvs_info.out_queue);
INIT_LIST_HEAD(&audio_mvs_info.free_out_queue);
wake_lock_init(&audio_mvs_info.suspend_lock,
WAKE_LOCK_SUSPEND,
"audio_mvs_suspend");
wake_lock_init(&audio_mvs_info.idle_lock,
WAKE_LOCK_IDLE,
"audio_mvs_idle");
rc = misc_register(&audio_mvs_misc);
return rc;
}
static void __exit audio_mvs_exit(void){
pr_info("%s:\n", __func__);
misc_deregister(&audio_mvs_misc);
}
module_init(audio_mvs_init);
module_exit(audio_mvs_exit);
MODULE_DESCRIPTION("MSM MVS driver");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
freedesktop-unofficial-mirror/drm-intel | sound/soc/fsl/fsl_dma.c | 431 | 31386 | /*
* Freescale DMA ALSA SoC PCM driver
*
* Author: Timur Tabi <timur@freescale.com>
*
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
* This driver implements ASoC support for the Elo DMA controller, which is
* the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
* the PCM driver is what handles the DMA buffer.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/io.h>
#include "fsl_dma.h"
#include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
/*
* The formats that the DMA controller supports, which is anything
* that is 8, 16, or 32 bits.
*/
#define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_U16_BE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S24_BE | \
SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_U24_BE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_S32_BE | \
SNDRV_PCM_FMTBIT_U32_LE | \
SNDRV_PCM_FMTBIT_U32_BE)
struct dma_object {
struct snd_soc_platform_driver dai;
dma_addr_t ssi_stx_phys;
dma_addr_t ssi_srx_phys;
unsigned int ssi_fifo_depth;
struct ccsr_dma_channel __iomem *channel;
unsigned int irq;
bool assigned;
char path[1];
};
/*
* The number of DMA links to use. Two is the bare minimum, but if you
* have really small links you might need more.
*/
#define NUM_DMA_LINKS 2
/** fsl_dma_private: p-substream DMA data
*
* Each substream has a 1-to-1 association with a DMA channel.
*
* The link[] array is first because it needs to be aligned on a 32-byte
* boundary, so putting it first will ensure alignment without padding the
* structure.
*
* @link[]: array of link descriptors
* @dma_channel: pointer to the DMA channel's registers
* @irq: IRQ for this DMA channel
* @substream: pointer to the substream object, needed by the ISR
* @ssi_sxx_phys: bus address of the STX or SRX register to use
* @ld_buf_phys: physical address of the LD buffer
* @current_link: index into link[] of the link currently being processed
* @dma_buf_phys: physical address of the DMA buffer
* @dma_buf_next: physical address of the next period to process
* @dma_buf_end: physical address of the byte after the end of the DMA
* @buffer period_size: the size of a single period
* @num_periods: the number of periods in the DMA buffer
*/
struct fsl_dma_private {
struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
struct ccsr_dma_channel __iomem *dma_channel;
unsigned int irq;
struct snd_pcm_substream *substream;
dma_addr_t ssi_sxx_phys;
unsigned int ssi_fifo_depth;
dma_addr_t ld_buf_phys;
unsigned int current_link;
dma_addr_t dma_buf_phys;
dma_addr_t dma_buf_next;
dma_addr_t dma_buf_end;
size_t period_size;
unsigned int num_periods;
};
/**
* fsl_dma_hardare: define characteristics of the PCM hardware.
*
* The PCM hardware is the Freescale DMA controller. This structure defines
* the capabilities of that hardware.
*
* Since the sampling rate and data format are not controlled by the DMA
* controller, we specify no limits for those values. The only exception is
* period_bytes_min, which is set to a reasonably low value to prevent the
* DMA controller from generating too many interrupts per second.
*
* Since each link descriptor has a 32-bit byte count field, we set
* period_bytes_max to the largest 32-bit number. We also have no maximum
* number of periods.
*
* Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
* limitation in the SSI driver requires the sample rates for playback and
* capture to be the same.
*/
static const struct snd_pcm_hardware fsl_dma_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_JOINT_DUPLEX |
SNDRV_PCM_INFO_PAUSE,
.formats = FSLDMA_PCM_FORMATS,
.period_bytes_min = 512, /* A reasonable limit */
.period_bytes_max = (u32) -1,
.periods_min = NUM_DMA_LINKS,
.periods_max = (unsigned int) -1,
.buffer_bytes_max = 128 * 1024, /* A reasonable limit */
};
/**
* fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
*
* This function should be called by the ISR whenever the DMA controller
* halts data transfer.
*/
static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
{
snd_pcm_stop_xrun(substream);
}
/**
* fsl_dma_update_pointers - update LD pointers to point to the next period
*
* As each period is completed, this function changes the the link
* descriptor pointers for that period to point to the next period.
*/
static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
{
struct fsl_dma_link_descriptor *link =
&dma_private->link[dma_private->current_link];
/* Update our link descriptors to point to the next period. On a 36-bit
* system, we also need to update the ESAD bits. We also set (keep) the
* snoop bits. See the comments in fsl_dma_hw_params() about snooping.
*/
if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
#ifdef CONFIG_PHYS_64BIT
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(dma_private->dma_buf_next));
#endif
} else {
link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
#ifdef CONFIG_PHYS_64BIT
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(dma_private->dma_buf_next));
#endif
}
/* Update our variables for next time */
dma_private->dma_buf_next += dma_private->period_size;
if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
dma_private->dma_buf_next = dma_private->dma_buf_phys;
if (++dma_private->current_link >= NUM_DMA_LINKS)
dma_private->current_link = 0;
}
/**
* fsl_dma_isr: interrupt handler for the DMA controller
*
* @irq: IRQ of the DMA channel
* @dev_id: pointer to the dma_private structure for this DMA channel
*/
static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
{
struct fsl_dma_private *dma_private = dev_id;
struct snd_pcm_substream *substream = dma_private->substream;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
irqreturn_t ret = IRQ_NONE;
u32 sr, sr2 = 0;
/* We got an interrupt, so read the status register to see what we
were interrupted for.
*/
sr = in_be32(&dma_channel->sr);
if (sr & CCSR_DMA_SR_TE) {
dev_err(dev, "dma transmit error\n");
fsl_dma_abort_stream(substream);
sr2 |= CCSR_DMA_SR_TE;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_CH)
ret = IRQ_HANDLED;
if (sr & CCSR_DMA_SR_PE) {
dev_err(dev, "dma programming error\n");
fsl_dma_abort_stream(substream);
sr2 |= CCSR_DMA_SR_PE;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_EOLNI) {
sr2 |= CCSR_DMA_SR_EOLNI;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_CB)
ret = IRQ_HANDLED;
if (sr & CCSR_DMA_SR_EOSI) {
/* Tell ALSA we completed a period. */
snd_pcm_period_elapsed(substream);
/*
* Update our link descriptors to point to the next period. We
* only need to do this if the number of periods is not equal to
* the number of links.
*/
if (dma_private->num_periods != NUM_DMA_LINKS)
fsl_dma_update_pointers(dma_private);
sr2 |= CCSR_DMA_SR_EOSI;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_EOLSI) {
sr2 |= CCSR_DMA_SR_EOLSI;
ret = IRQ_HANDLED;
}
/* Clear the bits that we set */
if (sr2)
out_be32(&dma_channel->sr, sr2);
return ret;
}
/**
* fsl_dma_new: initialize this PCM driver.
*
* This function is called when the codec driver calls snd_soc_new_pcms(),
* once for each .dai_link in the machine driver's snd_soc_card
* structure.
*
* snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
* (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
* is specified. Therefore, any DMA buffers we allocate will always be in low
* memory, but we support for 36-bit physical addresses anyway.
*
* Regardless of where the memory is actually allocated, since the device can
* technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
*/
static int fsl_dma_new(struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
if (ret)
return ret;
/* Some codecs have separate DAIs for playback and capture, so we
* should allocate a DMA buffer only for the streams that are valid.
*/
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
fsl_dma_hardware.buffer_bytes_max,
&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
if (ret) {
dev_err(card->dev, "can't alloc playback dma buffer\n");
return ret;
}
}
if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
fsl_dma_hardware.buffer_bytes_max,
&pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
if (ret) {
dev_err(card->dev, "can't alloc capture dma buffer\n");
snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
return ret;
}
}
return 0;
}
/**
* fsl_dma_open: open a new substream.
*
* Each substream has its own DMA buffer.
*
* ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
* descriptors that ping-pong from one period to the next. For example, if
* there are six periods and two link descriptors, this is how they look
* before playback starts:
*
* The last link descriptor
* ____________ points back to the first
* | |
* V |
* ___ ___ |
* | |->| |->|
* |___| |___|
* | |
* | |
* V V
* _________________________________________
* | | | | | | | The DMA buffer is
* | | | | | | | divided into 6 parts
* |______|______|______|______|______|______|
*
* and here's how they look after the first period is finished playing:
*
* ____________
* | |
* V |
* ___ ___ |
* | |->| |->|
* |___| |___|
* | |
* |______________
* | |
* V V
* _________________________________________
* | | | | | | |
* | | | | | | |
* |______|______|______|______|______|______|
*
* The first link descriptor now points to the third period. The DMA
* controller is currently playing the second period. When it finishes, it
* will jump back to the first descriptor and play the third period.
*
* There are four reasons we do this:
*
* 1. The only way to get the DMA controller to automatically restart the
* transfer when it gets to the end of the buffer is to use chaining
* mode. Basic direct mode doesn't offer that feature.
* 2. We need to receive an interrupt at the end of every period. The DMA
* controller can generate an interrupt at the end of every link transfer
* (aka segment). Making each period into a DMA segment will give us the
* interrupts we need.
* 3. By creating only two link descriptors, regardless of the number of
* periods, we do not need to reallocate the link descriptors if the
* number of periods changes.
* 4. All of the audio data is still stored in a single, contiguous DMA
* buffer, which is what ALSA expects. We're just dividing it into
* contiguous parts, and creating a link descriptor for each one.
*/
static int fsl_dma_open(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct dma_object *dma =
container_of(rtd->platform->driver, struct dma_object, dai);
struct fsl_dma_private *dma_private;
struct ccsr_dma_channel __iomem *dma_channel;
dma_addr_t ld_buf_phys;
u64 temp_link; /* Pointer to next link descriptor */
u32 mr;
unsigned int channel;
int ret = 0;
unsigned int i;
/*
* Reject any DMA buffer whose size is not a multiple of the period
* size. We need to make sure that the DMA buffer can be evenly divided
* into periods.
*/
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(dev, "invalid buffer size\n");
return ret;
}
channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
if (dma->assigned) {
dev_err(dev, "dma channel already assigned\n");
return -EBUSY;
}
dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
&ld_buf_phys, GFP_KERNEL);
if (!dma_private) {
dev_err(dev, "can't allocate dma private data\n");
return -ENOMEM;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
else
dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
dma_private->dma_channel = dma->channel;
dma_private->irq = dma->irq;
dma_private->substream = substream;
dma_private->ld_buf_phys = ld_buf_phys;
dma_private->dma_buf_phys = substream->dma_buffer.addr;
ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
dma_private);
if (ret) {
dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
dma_private->irq, ret);
dma_free_coherent(dev, sizeof(struct fsl_dma_private),
dma_private, dma_private->ld_buf_phys);
return ret;
}
dma->assigned = 1;
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
runtime->private_data = dma_private;
/* Program the fixed DMA controller parameters */
dma_channel = dma_private->dma_channel;
temp_link = dma_private->ld_buf_phys +
sizeof(struct fsl_dma_link_descriptor);
for (i = 0; i < NUM_DMA_LINKS; i++) {
dma_private->link[i].next = cpu_to_be64(temp_link);
temp_link += sizeof(struct fsl_dma_link_descriptor);
}
/* The last link descriptor points to the first */
dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
/* Tell the DMA controller where the first link descriptor is */
out_be32(&dma_channel->clndar,
CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
out_be32(&dma_channel->eclndar,
CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
/* The manual says the BCR must be clear before enabling EMP */
out_be32(&dma_channel->bcr, 0);
/*
* Program the mode register for interrupts, external master control,
* and source/destination hold. Also clear the Channel Abort bit.
*/
mr = in_be32(&dma_channel->mr) &
~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
/*
* We want External Master Start and External Master Pause enabled,
* because the SSI is controlling the DMA controller. We want the DMA
* controller to be set up in advance, and then we signal only the SSI
* to start transferring.
*
* We want End-Of-Segment Interrupts enabled, because this will generate
* an interrupt at the end of each segment (each link descriptor
* represents one segment). Each DMA segment is the same thing as an
* ALSA period, so this is how we get an interrupt at the end of every
* period.
*
* We want Error Interrupt enabled, so that we can get an error if
* the DMA controller is mis-programmed somehow.
*/
mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
CCSR_DMA_MR_EMS_EN;
/* For playback, we want the destination address to be held. For
capture, set the source address to be held. */
mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
out_be32(&dma_channel->mr, mr);
return 0;
}
/**
* fsl_dma_hw_params: continue initializing the DMA links
*
* This function obtains hardware parameters about the opened stream and
* programs the DMA controller accordingly.
*
* One drawback of big-endian is that when copying integers of different
* sizes to a fixed-sized register, the address to which the integer must be
* copied is dependent on the size of the integer.
*
* For example, if P is the address of a 32-bit register, and X is a 32-bit
* integer, then X should be copied to address P. However, if X is a 16-bit
* integer, then it should be copied to P+2. If X is an 8-bit register,
* then it should be copied to P+3.
*
* So for playback of 8-bit samples, the DMA controller must transfer single
* bytes from the DMA buffer to the last byte of the STX0 register, i.e.
* offset by 3 bytes. For 16-bit samples, the offset is two bytes.
*
* For 24-bit samples, the offset is 1 byte. However, the DMA controller
* does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
* and 8 bytes at a time). So we do not support packed 24-bit samples.
* 24-bit data must be padded to 32 bits.
*/
static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
/* Number of bits per sample */
unsigned int sample_bits =
snd_pcm_format_physical_width(params_format(hw_params));
/* Number of bytes per frame */
unsigned int sample_bytes = sample_bits / 8;
/* Bus address of SSI STX register */
dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
/* Size of the DMA buffer, in bytes */
size_t buffer_size = params_buffer_bytes(hw_params);
/* Number of bytes per period */
size_t period_size = params_period_bytes(hw_params);
/* Pointer to next period */
dma_addr_t temp_addr = substream->dma_buffer.addr;
/* Pointer to DMA controller */
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
u32 mr; /* DMA Mode Register */
unsigned int i;
/* Initialize our DMA tracking variables */
dma_private->period_size = period_size;
dma_private->num_periods = params_periods(hw_params);
dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
dma_private->dma_buf_next = dma_private->dma_buf_phys +
(NUM_DMA_LINKS * period_size);
if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
/* This happens if the number of periods == NUM_DMA_LINKS */
dma_private->dma_buf_next = dma_private->dma_buf_phys;
mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
/* Due to a quirk of the SSI's STX register, the target address
* for the DMA operations depends on the sample size. So we calculate
* that offset here. While we're at it, also tell the DMA controller
* how much data to transfer per sample.
*/
switch (sample_bits) {
case 8:
mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
ssi_sxx_phys += 3;
break;
case 16:
mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
ssi_sxx_phys += 2;
break;
case 32:
mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
break;
default:
/* We should never get here */
dev_err(dev, "unsupported sample size %u\n", sample_bits);
return -EINVAL;
}
/*
* BWC determines how many bytes are sent/received before the DMA
* controller checks the SSI to see if it needs to stop. BWC should
* always be a multiple of the frame size, so that we always transmit
* whole frames. Each frame occupies two slots in the FIFO. The
* parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
* (MR[BWC] can only represent even powers of two).
*
* To simplify the process, we set BWC to the largest value that is
* less than or equal to the FIFO watermark. For playback, this ensures
* that we transfer the maximum amount without overrunning the FIFO.
* For capture, this ensures that we transfer the maximum amount without
* underrunning the FIFO.
*
* f = SSI FIFO depth
* w = SSI watermark value (which equals f - 2)
* b = DMA bandwidth count (in bytes)
* s = sample size (in bytes, which equals frame_size * 2)
*
* For playback, we never transmit more than the transmit FIFO
* watermark, otherwise we might write more data than the FIFO can hold.
* The watermark is equal to the FIFO depth minus two.
*
* For capture, two equations must hold:
* w > f - (b / s)
* w >= b / s
*
* So, b > 2 * s, but b must also be <= s * w. To simplify, we set
* b = s * w, which is equal to
* (dma_private->ssi_fifo_depth - 2) * sample_bytes.
*/
mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
out_be32(&dma_channel->mr, mr);
for (i = 0; i < NUM_DMA_LINKS; i++) {
struct fsl_dma_link_descriptor *link = &dma_private->link[i];
link->count = cpu_to_be32(period_size);
/* The snoop bit tells the DMA controller whether it should tell
* the ECM to snoop during a read or write to an address. For
* audio, we use DMA to transfer data between memory and an I/O
* device (the SSI's STX0 or SRX0 register). Snooping is only
* needed if there is a cache, so we need to snoop memory
* addresses only. For playback, that means we snoop the source
* but not the destination. For capture, we snoop the
* destination but not the source.
*
* Note that failing to snoop properly is unlikely to cause
* cache incoherency if the period size is larger than the
* size of L1 cache. This is because filling in one period will
* flush out the data for the previous period. So if you
* increased period_bytes_min to a large enough size, you might
* get more performance by not snooping, and you'll still be
* okay. You'll need to update fsl_dma_update_pointers() also.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
link->source_addr = cpu_to_be32(temp_addr);
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(temp_addr));
link->dest_addr = cpu_to_be32(ssi_sxx_phys);
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
upper_32_bits(ssi_sxx_phys));
} else {
link->source_addr = cpu_to_be32(ssi_sxx_phys);
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
upper_32_bits(ssi_sxx_phys));
link->dest_addr = cpu_to_be32(temp_addr);
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(temp_addr));
}
temp_addr += period_size;
}
return 0;
}
/**
* fsl_dma_pointer: determine the current position of the DMA transfer
*
* This function is called by ALSA when ALSA wants to know where in the
* stream buffer the hardware currently is.
*
* For playback, the SAR register contains the physical address of the most
* recent DMA transfer. For capture, the value is in the DAR register.
*
* The base address of the buffer is stored in the source_addr field of the
* first link descriptor.
*/
static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
dma_addr_t position;
snd_pcm_uframes_t frames;
/* Obtain the current DMA pointer, but don't read the ESAD bits if we
* only have 32-bit DMA addresses. This function is typically called
* in interrupt context, so we need to optimize it.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
position = in_be32(&dma_channel->sar);
#ifdef CONFIG_PHYS_64BIT
position |= (u64)(in_be32(&dma_channel->satr) &
CCSR_DMA_ATR_ESAD_MASK) << 32;
#endif
} else {
position = in_be32(&dma_channel->dar);
#ifdef CONFIG_PHYS_64BIT
position |= (u64)(in_be32(&dma_channel->datr) &
CCSR_DMA_ATR_ESAD_MASK) << 32;
#endif
}
/*
* When capture is started, the SSI immediately starts to fill its FIFO.
* This means that the DMA controller is not started until the FIFO is
* full. However, ALSA calls this function before that happens, when
* MR.DAR is still zero. In this case, just return zero to indicate
* that nothing has been received yet.
*/
if (!position)
return 0;
if ((position < dma_private->dma_buf_phys) ||
(position > dma_private->dma_buf_end)) {
dev_err(dev, "dma pointer is out of range, halting stream\n");
return SNDRV_PCM_POS_XRUN;
}
frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
/*
* If the current address is just past the end of the buffer, wrap it
* around.
*/
if (frames == runtime->buffer_size)
frames = 0;
return frames;
}
/**
* fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
*
* Release the resources allocated in fsl_dma_hw_params() and de-program the
* registers.
*
* This function can be called multiple times.
*/
static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
if (dma_private) {
struct ccsr_dma_channel __iomem *dma_channel;
dma_channel = dma_private->dma_channel;
/* Stop the DMA */
out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
out_be32(&dma_channel->mr, 0);
/* Reset all the other registers */
out_be32(&dma_channel->sr, -1);
out_be32(&dma_channel->clndar, 0);
out_be32(&dma_channel->eclndar, 0);
out_be32(&dma_channel->satr, 0);
out_be32(&dma_channel->sar, 0);
out_be32(&dma_channel->datr, 0);
out_be32(&dma_channel->dar, 0);
out_be32(&dma_channel->bcr, 0);
out_be32(&dma_channel->nlndar, 0);
out_be32(&dma_channel->enlndar, 0);
}
return 0;
}
/**
* fsl_dma_close: close the stream.
*/
static int fsl_dma_close(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct dma_object *dma =
container_of(rtd->platform->driver, struct dma_object, dai);
if (dma_private) {
if (dma_private->irq)
free_irq(dma_private->irq, dma_private);
/* Deallocate the fsl_dma_private structure */
dma_free_coherent(dev, sizeof(struct fsl_dma_private),
dma_private, dma_private->ld_buf_phys);
substream->runtime->private_data = NULL;
}
dma->assigned = 0;
return 0;
}
/*
* Remove this PCM driver.
*/
static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
{
struct snd_pcm_substream *substream;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
substream = pcm->streams[i].substream;
if (substream) {
snd_dma_free_pages(&substream->dma_buffer);
substream->dma_buffer.area = NULL;
substream->dma_buffer.addr = 0;
}
}
}
/**
* find_ssi_node -- returns the SSI node that points to its DMA channel node
*
* Although this DMA driver attempts to operate independently of the other
* devices, it still needs to determine some information about the SSI device
* that it's working with. Unfortunately, the device tree does not contain
* a pointer from the DMA channel node to the SSI node -- the pointer goes the
* other way. So we need to scan the device tree for SSI nodes until we find
* the one that points to the given DMA channel node. It's ugly, but at least
* it's contained in this one function.
*/
static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
{
struct device_node *ssi_np, *np;
for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
/* Check each DMA phandle to see if it points to us. We
* assume that device_node pointers are a valid comparison.
*/
np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
of_node_put(np);
if (np == dma_channel_np)
return ssi_np;
np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
of_node_put(np);
if (np == dma_channel_np)
return ssi_np;
}
return NULL;
}
static struct snd_pcm_ops fsl_dma_ops = {
.open = fsl_dma_open,
.close = fsl_dma_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = fsl_dma_hw_params,
.hw_free = fsl_dma_hw_free,
.pointer = fsl_dma_pointer,
};
static int fsl_soc_dma_probe(struct platform_device *pdev)
{
struct dma_object *dma;
struct device_node *np = pdev->dev.of_node;
struct device_node *ssi_np;
struct resource res;
const uint32_t *iprop;
int ret;
/* Find the SSI node that points to us. */
ssi_np = find_ssi_node(np);
if (!ssi_np) {
dev_err(&pdev->dev, "cannot find parent SSI node\n");
return -ENODEV;
}
ret = of_address_to_resource(ssi_np, 0, &res);
if (ret) {
dev_err(&pdev->dev, "could not determine resources for %s\n",
ssi_np->full_name);
of_node_put(ssi_np);
return ret;
}
dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL);
if (!dma) {
dev_err(&pdev->dev, "could not allocate dma object\n");
of_node_put(ssi_np);
return -ENOMEM;
}
strcpy(dma->path, np->full_name);
dma->dai.ops = &fsl_dma_ops;
dma->dai.pcm_new = fsl_dma_new;
dma->dai.pcm_free = fsl_dma_free_dma_buffers;
/* Store the SSI-specific information that we need */
dma->ssi_stx_phys = res.start + CCSR_SSI_STX0;
dma->ssi_srx_phys = res.start + CCSR_SSI_SRX0;
iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
if (iprop)
dma->ssi_fifo_depth = be32_to_cpup(iprop);
else
/* Older 8610 DTs didn't have the fifo-depth property */
dma->ssi_fifo_depth = 8;
of_node_put(ssi_np);
ret = snd_soc_register_platform(&pdev->dev, &dma->dai);
if (ret) {
dev_err(&pdev->dev, "could not register platform\n");
kfree(dma);
return ret;
}
dma->channel = of_iomap(np, 0);
dma->irq = irq_of_parse_and_map(np, 0);
dev_set_drvdata(&pdev->dev, dma);
return 0;
}
static int fsl_soc_dma_remove(struct platform_device *pdev)
{
struct dma_object *dma = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_platform(&pdev->dev);
iounmap(dma->channel);
irq_dispose_mapping(dma->irq);
kfree(dma);
return 0;
}
static const struct of_device_id fsl_soc_dma_ids[] = {
{ .compatible = "fsl,ssi-dma-channel", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
static struct platform_driver fsl_soc_dma_driver = {
.driver = {
.name = "fsl-pcm-audio",
.of_match_table = fsl_soc_dma_ids,
},
.probe = fsl_soc_dma_probe,
.remove = fsl_soc_dma_remove,
};
module_platform_driver(fsl_soc_dma_driver);
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
caio2k/kernel-n9 | drivers/media/video/gspca/sn9c20x.c | 431 | 72345 | /*
* Sonix sn9c201 sn9c202 library
* Copyright (C) 2008-2009 microdia project <microdia@googlegroups.com>
* Copyright (C) 2009 Brian Johnson <brijohn@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifdef CONFIG_USB_GSPCA_SN9C20X_EVDEV
#include <linux/kthread.h>
#include <linux/freezer.h>
#include <linux/usb/input.h>
#include <linux/input.h>
#endif
#include "gspca.h"
#include "jpeg.h"
#include <media/v4l2-chip-ident.h>
MODULE_AUTHOR("Brian Johnson <brijohn@gmail.com>, "
"microdia project <microdia@googlegroups.com>");
MODULE_DESCRIPTION("GSPCA/SN9C20X USB Camera Driver");
MODULE_LICENSE("GPL");
#define MODULE_NAME "sn9c20x"
#define MODE_RAW 0x10
#define MODE_JPEG 0x20
#define MODE_SXGA 0x80
#define SENSOR_OV9650 0
#define SENSOR_OV9655 1
#define SENSOR_SOI968 2
#define SENSOR_OV7660 3
#define SENSOR_OV7670 4
#define SENSOR_MT9V011 5
#define SENSOR_MT9V111 6
#define SENSOR_MT9V112 7
#define SENSOR_MT9M001 8
#define SENSOR_MT9M111 9
#define SENSOR_HV7131R 10
#define SENSOR_MT9VPRB 20
/* specific webcam descriptor */
struct sd {
struct gspca_dev gspca_dev;
#define MIN_AVG_LUM 80
#define MAX_AVG_LUM 130
atomic_t avg_lum;
u8 old_step;
u8 older_step;
u8 exposure_step;
u8 brightness;
u8 contrast;
u8 saturation;
s16 hue;
u8 gamma;
u8 red;
u8 blue;
u8 hflip;
u8 vflip;
u8 gain;
u16 exposure;
u8 auto_exposure;
u8 i2c_addr;
u8 sensor;
u8 hstart;
u8 vstart;
u8 *jpeg_hdr;
u8 quality;
#ifdef CONFIG_USB_GSPCA_SN9C20X_EVDEV
struct input_dev *input_dev;
u8 input_gpio;
struct task_struct *input_task;
#endif
};
struct i2c_reg_u8 {
u8 reg;
u8 val;
};
struct i2c_reg_u16 {
u8 reg;
u16 val;
};
static int sd_setbrightness(struct gspca_dev *gspca_dev, s32 val);
static int sd_getbrightness(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setcontrast(struct gspca_dev *gspca_dev, s32 val);
static int sd_getcontrast(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setsaturation(struct gspca_dev *gspca_dev, s32 val);
static int sd_getsaturation(struct gspca_dev *gspca_dev, s32 *val);
static int sd_sethue(struct gspca_dev *gspca_dev, s32 val);
static int sd_gethue(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setgamma(struct gspca_dev *gspca_dev, s32 val);
static int sd_getgamma(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setredbalance(struct gspca_dev *gspca_dev, s32 val);
static int sd_getredbalance(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setbluebalance(struct gspca_dev *gspca_dev, s32 val);
static int sd_getbluebalance(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setvflip(struct gspca_dev *gspca_dev, s32 val);
static int sd_getvflip(struct gspca_dev *gspca_dev, s32 *val);
static int sd_sethflip(struct gspca_dev *gspca_dev, s32 val);
static int sd_gethflip(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setgain(struct gspca_dev *gspca_dev, s32 val);
static int sd_getgain(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setexposure(struct gspca_dev *gspca_dev, s32 val);
static int sd_getexposure(struct gspca_dev *gspca_dev, s32 *val);
static int sd_setautoexposure(struct gspca_dev *gspca_dev, s32 val);
static int sd_getautoexposure(struct gspca_dev *gspca_dev, s32 *val);
static struct ctrl sd_ctrls[] = {
{
#define BRIGHTNESS_IDX 0
{
.id = V4L2_CID_BRIGHTNESS,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Brightness",
.minimum = 0,
.maximum = 0xff,
.step = 1,
#define BRIGHTNESS_DEFAULT 0x7f
.default_value = BRIGHTNESS_DEFAULT,
},
.set = sd_setbrightness,
.get = sd_getbrightness,
},
{
#define CONTRAST_IDX 1
{
.id = V4L2_CID_CONTRAST,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Contrast",
.minimum = 0,
.maximum = 0xff,
.step = 1,
#define CONTRAST_DEFAULT 0x7f
.default_value = CONTRAST_DEFAULT,
},
.set = sd_setcontrast,
.get = sd_getcontrast,
},
{
#define SATURATION_IDX 2
{
.id = V4L2_CID_SATURATION,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Saturation",
.minimum = 0,
.maximum = 0xff,
.step = 1,
#define SATURATION_DEFAULT 0x7f
.default_value = SATURATION_DEFAULT,
},
.set = sd_setsaturation,
.get = sd_getsaturation,
},
{
#define HUE_IDX 3
{
.id = V4L2_CID_HUE,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Hue",
.minimum = -180,
.maximum = 180,
.step = 1,
#define HUE_DEFAULT 0
.default_value = HUE_DEFAULT,
},
.set = sd_sethue,
.get = sd_gethue,
},
{
#define GAMMA_IDX 4
{
.id = V4L2_CID_GAMMA,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Gamma",
.minimum = 0,
.maximum = 0xff,
.step = 1,
#define GAMMA_DEFAULT 0x10
.default_value = GAMMA_DEFAULT,
},
.set = sd_setgamma,
.get = sd_getgamma,
},
{
#define BLUE_IDX 5
{
.id = V4L2_CID_BLUE_BALANCE,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Blue Balance",
.minimum = 0,
.maximum = 0x7f,
.step = 1,
#define BLUE_DEFAULT 0x28
.default_value = BLUE_DEFAULT,
},
.set = sd_setbluebalance,
.get = sd_getbluebalance,
},
{
#define RED_IDX 6
{
.id = V4L2_CID_RED_BALANCE,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Red Balance",
.minimum = 0,
.maximum = 0x7f,
.step = 1,
#define RED_DEFAULT 0x28
.default_value = RED_DEFAULT,
},
.set = sd_setredbalance,
.get = sd_getredbalance,
},
{
#define HFLIP_IDX 7
{
.id = V4L2_CID_HFLIP,
.type = V4L2_CTRL_TYPE_BOOLEAN,
.name = "Horizontal Flip",
.minimum = 0,
.maximum = 1,
.step = 1,
#define HFLIP_DEFAULT 0
.default_value = HFLIP_DEFAULT,
},
.set = sd_sethflip,
.get = sd_gethflip,
},
{
#define VFLIP_IDX 8
{
.id = V4L2_CID_VFLIP,
.type = V4L2_CTRL_TYPE_BOOLEAN,
.name = "Vertical Flip",
.minimum = 0,
.maximum = 1,
.step = 1,
#define VFLIP_DEFAULT 0
.default_value = VFLIP_DEFAULT,
},
.set = sd_setvflip,
.get = sd_getvflip,
},
{
#define EXPOSURE_IDX 9
{
.id = V4L2_CID_EXPOSURE,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Exposure",
.minimum = 0,
.maximum = 0x1780,
.step = 1,
#define EXPOSURE_DEFAULT 0x33
.default_value = EXPOSURE_DEFAULT,
},
.set = sd_setexposure,
.get = sd_getexposure,
},
{
#define GAIN_IDX 10
{
.id = V4L2_CID_GAIN,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Gain",
.minimum = 0,
.maximum = 28,
.step = 1,
#define GAIN_DEFAULT 0x00
.default_value = GAIN_DEFAULT,
},
.set = sd_setgain,
.get = sd_getgain,
},
{
#define AUTOGAIN_IDX 11
{
.id = V4L2_CID_AUTOGAIN,
.type = V4L2_CTRL_TYPE_BOOLEAN,
.name = "Auto Exposure",
.minimum = 0,
.maximum = 1,
.step = 1,
#define AUTO_EXPOSURE_DEFAULT 1
.default_value = AUTO_EXPOSURE_DEFAULT,
},
.set = sd_setautoexposure,
.get = sd_getautoexposure,
},
};
static const struct v4l2_pix_format vga_mode[] = {
{160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
.bytesperline = 240,
.sizeimage = 240 * 120,
.colorspace = V4L2_COLORSPACE_JPEG,
.priv = 0 | MODE_JPEG},
{160, 120, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 160,
.sizeimage = 160 * 120,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0 | MODE_RAW},
{160, 120, V4L2_PIX_FMT_SN9C20X_I420, V4L2_FIELD_NONE,
.bytesperline = 240,
.sizeimage = 240 * 120,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0},
{320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
.bytesperline = 480,
.sizeimage = 480 * 240 ,
.colorspace = V4L2_COLORSPACE_JPEG,
.priv = 1 | MODE_JPEG},
{320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 320,
.sizeimage = 320 * 240 ,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1 | MODE_RAW},
{320, 240, V4L2_PIX_FMT_SN9C20X_I420, V4L2_FIELD_NONE,
.bytesperline = 480,
.sizeimage = 480 * 240 ,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1},
{640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
.bytesperline = 960,
.sizeimage = 960 * 480,
.colorspace = V4L2_COLORSPACE_JPEG,
.priv = 2 | MODE_JPEG},
{640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 640,
.sizeimage = 640 * 480,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2 | MODE_RAW},
{640, 480, V4L2_PIX_FMT_SN9C20X_I420, V4L2_FIELD_NONE,
.bytesperline = 960,
.sizeimage = 960 * 480,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2},
};
static const struct v4l2_pix_format sxga_mode[] = {
{160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
.bytesperline = 240,
.sizeimage = 240 * 120,
.colorspace = V4L2_COLORSPACE_JPEG,
.priv = 0 | MODE_JPEG},
{160, 120, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 160,
.sizeimage = 160 * 120,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0 | MODE_RAW},
{160, 120, V4L2_PIX_FMT_SN9C20X_I420, V4L2_FIELD_NONE,
.bytesperline = 240,
.sizeimage = 240 * 120,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0},
{320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
.bytesperline = 480,
.sizeimage = 480 * 240 ,
.colorspace = V4L2_COLORSPACE_JPEG,
.priv = 1 | MODE_JPEG},
{320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 320,
.sizeimage = 320 * 240 ,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1 | MODE_RAW},
{320, 240, V4L2_PIX_FMT_SN9C20X_I420, V4L2_FIELD_NONE,
.bytesperline = 480,
.sizeimage = 480 * 240 ,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1},
{640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
.bytesperline = 960,
.sizeimage = 960 * 480,
.colorspace = V4L2_COLORSPACE_JPEG,
.priv = 2 | MODE_JPEG},
{640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 640,
.sizeimage = 640 * 480,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2 | MODE_RAW},
{640, 480, V4L2_PIX_FMT_SN9C20X_I420, V4L2_FIELD_NONE,
.bytesperline = 960,
.sizeimage = 960 * 480,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2},
{1280, 1024, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
.bytesperline = 1280,
.sizeimage = (1280 * 1024) + 64,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 3 | MODE_RAW | MODE_SXGA},
};
static const s16 hsv_red_x[] = {
41, 44, 46, 48, 50, 52, 54, 56,
58, 60, 62, 64, 66, 68, 70, 72,
74, 76, 78, 80, 81, 83, 85, 87,
88, 90, 92, 93, 95, 97, 98, 100,
101, 102, 104, 105, 107, 108, 109, 110,
112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123, 123, 124, 125, 125,
126, 127, 127, 128, 128, 129, 129, 129,
130, 130, 130, 130, 131, 131, 131, 131,
131, 131, 131, 131, 130, 130, 130, 130,
129, 129, 129, 128, 128, 127, 127, 126,
125, 125, 124, 123, 122, 122, 121, 120,
119, 118, 117, 116, 115, 114, 112, 111,
110, 109, 107, 106, 105, 103, 102, 101,
99, 98, 96, 94, 93, 91, 90, 88,
86, 84, 83, 81, 79, 77, 75, 74,
72, 70, 68, 66, 64, 62, 60, 58,
56, 54, 52, 49, 47, 45, 43, 41,
39, 36, 34, 32, 30, 28, 25, 23,
21, 19, 16, 14, 12, 9, 7, 5,
3, 0, -1, -3, -6, -8, -10, -12,
-15, -17, -19, -22, -24, -26, -28, -30,
-33, -35, -37, -39, -41, -44, -46, -48,
-50, -52, -54, -56, -58, -60, -62, -64,
-66, -68, -70, -72, -74, -76, -78, -80,
-81, -83, -85, -87, -88, -90, -92, -93,
-95, -97, -98, -100, -101, -102, -104, -105,
-107, -108, -109, -110, -112, -113, -114, -115,
-116, -117, -118, -119, -120, -121, -122, -123,
-123, -124, -125, -125, -126, -127, -127, -128,
-128, -128, -128, -128, -128, -128, -128, -128,
-128, -128, -128, -128, -128, -128, -128, -128,
-128, -128, -128, -128, -128, -128, -128, -128,
-128, -127, -127, -126, -125, -125, -124, -123,
-122, -122, -121, -120, -119, -118, -117, -116,
-115, -114, -112, -111, -110, -109, -107, -106,
-105, -103, -102, -101, -99, -98, -96, -94,
-93, -91, -90, -88, -86, -84, -83, -81,
-79, -77, -75, -74, -72, -70, -68, -66,
-64, -62, -60, -58, -56, -54, -52, -49,
-47, -45, -43, -41, -39, -36, -34, -32,
-30, -28, -25, -23, -21, -19, -16, -14,
-12, -9, -7, -5, -3, 0, 1, 3,
6, 8, 10, 12, 15, 17, 19, 22,
24, 26, 28, 30, 33, 35, 37, 39, 41
};
static const s16 hsv_red_y[] = {
82, 80, 78, 76, 74, 73, 71, 69,
67, 65, 63, 61, 58, 56, 54, 52,
50, 48, 46, 44, 41, 39, 37, 35,
32, 30, 28, 26, 23, 21, 19, 16,
14, 12, 10, 7, 5, 3, 0, -1,
-3, -6, -8, -10, -13, -15, -17, -19,
-22, -24, -26, -29, -31, -33, -35, -38,
-40, -42, -44, -46, -48, -51, -53, -55,
-57, -59, -61, -63, -65, -67, -69, -71,
-73, -75, -77, -79, -81, -82, -84, -86,
-88, -89, -91, -93, -94, -96, -98, -99,
-101, -102, -104, -105, -106, -108, -109, -110,
-112, -113, -114, -115, -116, -117, -119, -120,
-120, -121, -122, -123, -124, -125, -126, -126,
-127, -128, -128, -128, -128, -128, -128, -128,
-128, -128, -128, -128, -128, -128, -128, -128,
-128, -128, -128, -128, -128, -128, -128, -128,
-128, -128, -128, -128, -128, -128, -128, -128,
-127, -127, -126, -125, -125, -124, -123, -122,
-121, -120, -119, -118, -117, -116, -115, -114,
-113, -111, -110, -109, -107, -106, -105, -103,
-102, -100, -99, -97, -96, -94, -92, -91,
-89, -87, -85, -84, -82, -80, -78, -76,
-74, -73, -71, -69, -67, -65, -63, -61,
-58, -56, -54, -52, -50, -48, -46, -44,
-41, -39, -37, -35, -32, -30, -28, -26,
-23, -21, -19, -16, -14, -12, -10, -7,
-5, -3, 0, 1, 3, 6, 8, 10,
13, 15, 17, 19, 22, 24, 26, 29,
31, 33, 35, 38, 40, 42, 44, 46,
48, 51, 53, 55, 57, 59, 61, 63,
65, 67, 69, 71, 73, 75, 77, 79,
81, 82, 84, 86, 88, 89, 91, 93,
94, 96, 98, 99, 101, 102, 104, 105,
106, 108, 109, 110, 112, 113, 114, 115,
116, 117, 119, 120, 120, 121, 122, 123,
124, 125, 126, 126, 127, 128, 128, 129,
129, 130, 130, 131, 131, 131, 131, 132,
132, 132, 132, 132, 132, 132, 132, 132,
132, 132, 132, 131, 131, 131, 130, 130,
130, 129, 129, 128, 127, 127, 126, 125,
125, 124, 123, 122, 121, 120, 119, 118,
117, 116, 115, 114, 113, 111, 110, 109,
107, 106, 105, 103, 102, 100, 99, 97,
96, 94, 92, 91, 89, 87, 85, 84, 82
};
static const s16 hsv_green_x[] = {
-124, -124, -125, -125, -125, -125, -125, -125,
-125, -126, -126, -125, -125, -125, -125, -125,
-125, -124, -124, -124, -123, -123, -122, -122,
-121, -121, -120, -120, -119, -118, -117, -117,
-116, -115, -114, -113, -112, -111, -110, -109,
-108, -107, -105, -104, -103, -102, -100, -99,
-98, -96, -95, -93, -92, -91, -89, -87,
-86, -84, -83, -81, -79, -77, -76, -74,
-72, -70, -69, -67, -65, -63, -61, -59,
-57, -55, -53, -51, -49, -47, -45, -43,
-41, -39, -37, -35, -33, -30, -28, -26,
-24, -22, -20, -18, -15, -13, -11, -9,
-7, -4, -2, 0, 1, 3, 6, 8,
10, 12, 14, 17, 19, 21, 23, 25,
27, 29, 32, 34, 36, 38, 40, 42,
44, 46, 48, 50, 52, 54, 56, 58,
60, 62, 64, 66, 68, 70, 71, 73,
75, 77, 78, 80, 82, 83, 85, 87,
88, 90, 91, 93, 94, 96, 97, 98,
100, 101, 102, 104, 105, 106, 107, 108,
109, 111, 112, 113, 113, 114, 115, 116,
117, 118, 118, 119, 120, 120, 121, 122,
122, 123, 123, 124, 124, 124, 125, 125,
125, 125, 125, 125, 125, 126, 126, 125,
125, 125, 125, 125, 125, 124, 124, 124,
123, 123, 122, 122, 121, 121, 120, 120,
119, 118, 117, 117, 116, 115, 114, 113,
112, 111, 110, 109, 108, 107, 105, 104,
103, 102, 100, 99, 98, 96, 95, 93,
92, 91, 89, 87, 86, 84, 83, 81,
79, 77, 76, 74, 72, 70, 69, 67,
65, 63, 61, 59, 57, 55, 53, 51,
49, 47, 45, 43, 41, 39, 37, 35,
33, 30, 28, 26, 24, 22, 20, 18,
15, 13, 11, 9, 7, 4, 2, 0,
-1, -3, -6, -8, -10, -12, -14, -17,
-19, -21, -23, -25, -27, -29, -32, -34,
-36, -38, -40, -42, -44, -46, -48, -50,
-52, -54, -56, -58, -60, -62, -64, -66,
-68, -70, -71, -73, -75, -77, -78, -80,
-82, -83, -85, -87, -88, -90, -91, -93,
-94, -96, -97, -98, -100, -101, -102, -104,
-105, -106, -107, -108, -109, -111, -112, -113,
-113, -114, -115, -116, -117, -118, -118, -119,
-120, -120, -121, -122, -122, -123, -123, -124, -124
};
static const s16 hsv_green_y[] = {
-100, -99, -98, -97, -95, -94, -93, -91,
-90, -89, -87, -86, -84, -83, -81, -80,
-78, -76, -75, -73, -71, -70, -68, -66,
-64, -63, -61, -59, -57, -55, -53, -51,
-49, -48, -46, -44, -42, -40, -38, -36,
-34, -32, -30, -27, -25, -23, -21, -19,
-17, -15, -13, -11, -9, -7, -4, -2,
0, 1, 3, 5, 7, 9, 11, 14,
16, 18, 20, 22, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42, 44, 46,
48, 50, 52, 54, 56, 58, 59, 61,
63, 65, 67, 68, 70, 72, 74, 75,
77, 78, 80, 82, 83, 85, 86, 88,
89, 90, 92, 93, 95, 96, 97, 98,
100, 101, 102, 103, 104, 105, 106, 107,
108, 109, 110, 111, 112, 112, 113, 114,
115, 115, 116, 116, 117, 117, 118, 118,
119, 119, 119, 120, 120, 120, 120, 120,
121, 121, 121, 121, 121, 121, 120, 120,
120, 120, 120, 119, 119, 119, 118, 118,
117, 117, 116, 116, 115, 114, 114, 113,
112, 111, 111, 110, 109, 108, 107, 106,
105, 104, 103, 102, 100, 99, 98, 97,
95, 94, 93, 91, 90, 89, 87, 86,
84, 83, 81, 80, 78, 76, 75, 73,
71, 70, 68, 66, 64, 63, 61, 59,
57, 55, 53, 51, 49, 48, 46, 44,
42, 40, 38, 36, 34, 32, 30, 27,
25, 23, 21, 19, 17, 15, 13, 11,
9, 7, 4, 2, 0, -1, -3, -5,
-7, -9, -11, -14, -16, -18, -20, -22,
-24, -26, -28, -30, -32, -34, -36, -38,
-40, -42, -44, -46, -48, -50, -52, -54,
-56, -58, -59, -61, -63, -65, -67, -68,
-70, -72, -74, -75, -77, -78, -80, -82,
-83, -85, -86, -88, -89, -90, -92, -93,
-95, -96, -97, -98, -100, -101, -102, -103,
-104, -105, -106, -107, -108, -109, -110, -111,
-112, -112, -113, -114, -115, -115, -116, -116,
-117, -117, -118, -118, -119, -119, -119, -120,
-120, -120, -120, -120, -121, -121, -121, -121,
-121, -121, -120, -120, -120, -120, -120, -119,
-119, -119, -118, -118, -117, -117, -116, -116,
-115, -114, -114, -113, -112, -111, -111, -110,
-109, -108, -107, -106, -105, -104, -103, -102, -100
};
static const s16 hsv_blue_x[] = {
112, 113, 114, 114, 115, 116, 117, 117,
118, 118, 119, 119, 120, 120, 120, 121,
121, 121, 122, 122, 122, 122, 122, 122,
122, 122, 122, 122, 122, 122, 121, 121,
121, 120, 120, 120, 119, 119, 118, 118,
117, 116, 116, 115, 114, 113, 113, 112,
111, 110, 109, 108, 107, 106, 105, 104,
103, 102, 100, 99, 98, 97, 95, 94,
93, 91, 90, 88, 87, 85, 84, 82,
80, 79, 77, 76, 74, 72, 70, 69,
67, 65, 63, 61, 60, 58, 56, 54,
52, 50, 48, 46, 44, 42, 40, 38,
36, 34, 32, 30, 28, 26, 24, 22,
19, 17, 15, 13, 11, 9, 7, 5,
2, 0, -1, -3, -5, -7, -9, -12,
-14, -16, -18, -20, -22, -24, -26, -28,
-31, -33, -35, -37, -39, -41, -43, -45,
-47, -49, -51, -53, -54, -56, -58, -60,
-62, -64, -66, -67, -69, -71, -73, -74,
-76, -78, -79, -81, -83, -84, -86, -87,
-89, -90, -92, -93, -94, -96, -97, -98,
-99, -101, -102, -103, -104, -105, -106, -107,
-108, -109, -110, -111, -112, -113, -114, -114,
-115, -116, -117, -117, -118, -118, -119, -119,
-120, -120, -120, -121, -121, -121, -122, -122,
-122, -122, -122, -122, -122, -122, -122, -122,
-122, -122, -121, -121, -121, -120, -120, -120,
-119, -119, -118, -118, -117, -116, -116, -115,
-114, -113, -113, -112, -111, -110, -109, -108,
-107, -106, -105, -104, -103, -102, -100, -99,
-98, -97, -95, -94, -93, -91, -90, -88,
-87, -85, -84, -82, -80, -79, -77, -76,
-74, -72, -70, -69, -67, -65, -63, -61,
-60, -58, -56, -54, -52, -50, -48, -46,
-44, -42, -40, -38, -36, -34, -32, -30,
-28, -26, -24, -22, -19, -17, -15, -13,
-11, -9, -7, -5, -2, 0, 1, 3,
5, 7, 9, 12, 14, 16, 18, 20,
22, 24, 26, 28, 31, 33, 35, 37,
39, 41, 43, 45, 47, 49, 51, 53,
54, 56, 58, 60, 62, 64, 66, 67,
69, 71, 73, 74, 76, 78, 79, 81,
83, 84, 86, 87, 89, 90, 92, 93,
94, 96, 97, 98, 99, 101, 102, 103,
104, 105, 106, 107, 108, 109, 110, 111, 112
};
static const s16 hsv_blue_y[] = {
-11, -13, -15, -17, -19, -21, -23, -25,
-27, -29, -31, -33, -35, -37, -39, -41,
-43, -45, -46, -48, -50, -52, -54, -55,
-57, -59, -61, -62, -64, -66, -67, -69,
-71, -72, -74, -75, -77, -78, -80, -81,
-83, -84, -86, -87, -88, -90, -91, -92,
-93, -95, -96, -97, -98, -99, -100, -101,
-102, -103, -104, -105, -106, -106, -107, -108,
-109, -109, -110, -111, -111, -112, -112, -113,
-113, -114, -114, -114, -115, -115, -115, -115,
-116, -116, -116, -116, -116, -116, -116, -116,
-116, -115, -115, -115, -115, -114, -114, -114,
-113, -113, -112, -112, -111, -111, -110, -110,
-109, -108, -108, -107, -106, -105, -104, -103,
-102, -101, -100, -99, -98, -97, -96, -95,
-94, -93, -91, -90, -89, -88, -86, -85,
-84, -82, -81, -79, -78, -76, -75, -73,
-71, -70, -68, -67, -65, -63, -62, -60,
-58, -56, -55, -53, -51, -49, -47, -45,
-44, -42, -40, -38, -36, -34, -32, -30,
-28, -26, -24, -22, -20, -18, -16, -14,
-12, -10, -8, -6, -4, -2, 0, 1,
3, 5, 7, 9, 11, 13, 15, 17,
19, 21, 23, 25, 27, 29, 31, 33,
35, 37, 39, 41, 43, 45, 46, 48,
50, 52, 54, 55, 57, 59, 61, 62,
64, 66, 67, 69, 71, 72, 74, 75,
77, 78, 80, 81, 83, 84, 86, 87,
88, 90, 91, 92, 93, 95, 96, 97,
98, 99, 100, 101, 102, 103, 104, 105,
106, 106, 107, 108, 109, 109, 110, 111,
111, 112, 112, 113, 113, 114, 114, 114,
115, 115, 115, 115, 116, 116, 116, 116,
116, 116, 116, 116, 116, 115, 115, 115,
115, 114, 114, 114, 113, 113, 112, 112,
111, 111, 110, 110, 109, 108, 108, 107,
106, 105, 104, 103, 102, 101, 100, 99,
98, 97, 96, 95, 94, 93, 91, 90,
89, 88, 86, 85, 84, 82, 81, 79,
78, 76, 75, 73, 71, 70, 68, 67,
65, 63, 62, 60, 58, 56, 55, 53,
51, 49, 47, 45, 44, 42, 40, 38,
36, 34, 32, 30, 28, 26, 24, 22,
20, 18, 16, 14, 12, 10, 8, 6,
4, 2, 0, -1, -3, -5, -7, -9, -11
};
static u16 i2c_ident[] = {
V4L2_IDENT_OV9650,
V4L2_IDENT_OV9655,
V4L2_IDENT_SOI968,
V4L2_IDENT_OV7660,
V4L2_IDENT_OV7670,
V4L2_IDENT_MT9V011,
V4L2_IDENT_MT9V111,
V4L2_IDENT_MT9V112,
V4L2_IDENT_MT9M001C12ST,
V4L2_IDENT_MT9M111,
V4L2_IDENT_HV7131R,
};
static u16 bridge_init[][2] = {
{0x1000, 0x78}, {0x1001, 0x40}, {0x1002, 0x1c},
{0x1020, 0x80}, {0x1061, 0x01}, {0x1067, 0x40},
{0x1068, 0x30}, {0x1069, 0x20}, {0x106a, 0x10},
{0x106b, 0x08}, {0x1188, 0x87}, {0x11a1, 0x00},
{0x11a2, 0x00}, {0x11a3, 0x6a}, {0x11a4, 0x50},
{0x11ab, 0x00}, {0x11ac, 0x00}, {0x11ad, 0x50},
{0x11ae, 0x3c}, {0x118a, 0x04}, {0x0395, 0x04},
{0x11b8, 0x3a}, {0x118b, 0x0e}, {0x10f7, 0x05},
{0x10f8, 0x14}, {0x10fa, 0xff}, {0x10f9, 0x00},
{0x11ba, 0x0a}, {0x11a5, 0x2d}, {0x11a6, 0x2d},
{0x11a7, 0x3a}, {0x11a8, 0x05}, {0x11a9, 0x04},
{0x11aa, 0x3f}, {0x11af, 0x28}, {0x11b0, 0xd8},
{0x11b1, 0x14}, {0x11b2, 0xec}, {0x11b3, 0x32},
{0x11b4, 0xdd}, {0x11b5, 0x32}, {0x11b6, 0xdd},
{0x10e0, 0x2c}, {0x11bc, 0x40}, {0x11bd, 0x01},
{0x11be, 0xf0}, {0x11bf, 0x00}, {0x118c, 0x1f},
{0x118d, 0x1f}, {0x118e, 0x1f}, {0x118f, 0x1f},
{0x1180, 0x01}, {0x1181, 0x00}, {0x1182, 0x01},
{0x1183, 0x00}, {0x1184, 0x50}, {0x1185, 0x80}
};
/* Gain = (bit[3:0] / 16 + 1) * (bit[4] + 1) * (bit[5] + 1) * (bit[6] + 1) */
static u8 ov_gain[] = {
0x00 /* 1x */, 0x04 /* 1.25x */, 0x08 /* 1.5x */, 0x0c /* 1.75x */,
0x10 /* 2x */, 0x12 /* 2.25x */, 0x14 /* 2.5x */, 0x16 /* 2.75x */,
0x18 /* 3x */, 0x1a /* 3.25x */, 0x1c /* 3.5x */, 0x1e /* 3.75x */,
0x30 /* 4x */, 0x31 /* 4.25x */, 0x32 /* 4.5x */, 0x33 /* 4.75x */,
0x34 /* 5x */, 0x35 /* 5.25x */, 0x36 /* 5.5x */, 0x37 /* 5.75x */,
0x38 /* 6x */, 0x39 /* 6.25x */, 0x3a /* 6.5x */, 0x3b /* 6.75x */,
0x3c /* 7x */, 0x3d /* 7.25x */, 0x3e /* 7.5x */, 0x3f /* 7.75x */,
0x70 /* 8x */
};
/* Gain = (bit[8] + 1) * (bit[7] + 1) * (bit[6:0] * 0.03125) */
static u16 micron1_gain[] = {
/* 1x 1.25x 1.5x 1.75x */
0x0020, 0x0028, 0x0030, 0x0038,
/* 2x 2.25x 2.5x 2.75x */
0x00a0, 0x00a4, 0x00a8, 0x00ac,
/* 3x 3.25x 3.5x 3.75x */
0x00b0, 0x00b4, 0x00b8, 0x00bc,
/* 4x 4.25x 4.5x 4.75x */
0x00c0, 0x00c4, 0x00c8, 0x00cc,
/* 5x 5.25x 5.5x 5.75x */
0x00d0, 0x00d4, 0x00d8, 0x00dc,
/* 6x 6.25x 6.5x 6.75x */
0x00e0, 0x00e4, 0x00e8, 0x00ec,
/* 7x 7.25x 7.5x 7.75x */
0x00f0, 0x00f4, 0x00f8, 0x00fc,
/* 8x */
0x01c0
};
/* mt9m001 sensor uses a different gain formula then other micron sensors */
/* Gain = (bit[6] + 1) * (bit[5-0] * 0.125) */
static u16 micron2_gain[] = {
/* 1x 1.25x 1.5x 1.75x */
0x0008, 0x000a, 0x000c, 0x000e,
/* 2x 2.25x 2.5x 2.75x */
0x0010, 0x0012, 0x0014, 0x0016,
/* 3x 3.25x 3.5x 3.75x */
0x0018, 0x001a, 0x001c, 0x001e,
/* 4x 4.25x 4.5x 4.75x */
0x0020, 0x0051, 0x0052, 0x0053,
/* 5x 5.25x 5.5x 5.75x */
0x0054, 0x0055, 0x0056, 0x0057,
/* 6x 6.25x 6.5x 6.75x */
0x0058, 0x0059, 0x005a, 0x005b,
/* 7x 7.25x 7.5x 7.75x */
0x005c, 0x005d, 0x005e, 0x005f,
/* 8x */
0x0060
};
/* Gain = .5 + bit[7:0] / 16 */
static u8 hv7131r_gain[] = {
0x08 /* 1x */, 0x0c /* 1.25x */, 0x10 /* 1.5x */, 0x14 /* 1.75x */,
0x18 /* 2x */, 0x1c /* 2.25x */, 0x20 /* 2.5x */, 0x24 /* 2.75x */,
0x28 /* 3x */, 0x2c /* 3.25x */, 0x30 /* 3.5x */, 0x34 /* 3.75x */,
0x38 /* 4x */, 0x3c /* 4.25x */, 0x40 /* 4.5x */, 0x44 /* 4.75x */,
0x48 /* 5x */, 0x4c /* 5.25x */, 0x50 /* 5.5x */, 0x54 /* 5.75x */,
0x58 /* 6x */, 0x5c /* 6.25x */, 0x60 /* 6.5x */, 0x64 /* 6.75x */,
0x68 /* 7x */, 0x6c /* 7.25x */, 0x70 /* 7.5x */, 0x74 /* 7.75x */,
0x78 /* 8x */
};
static struct i2c_reg_u8 soi968_init[] = {
{0x12, 0x80}, {0x0c, 0x00}, {0x0f, 0x1f},
{0x11, 0x80}, {0x38, 0x52}, {0x1e, 0x00},
{0x33, 0x08}, {0x35, 0x8c}, {0x36, 0x0c},
{0x37, 0x04}, {0x45, 0x04}, {0x47, 0xff},
{0x3e, 0x00}, {0x3f, 0x00}, {0x3b, 0x20},
{0x3a, 0x96}, {0x3d, 0x0a}, {0x14, 0x8e},
{0x13, 0x8b}, {0x12, 0x40}, {0x17, 0x13},
{0x18, 0x63}, {0x19, 0x01}, {0x1a, 0x79},
{0x32, 0x24}, {0x03, 0x00}, {0x11, 0x40},
{0x2a, 0x10}, {0x2b, 0xe0}, {0x10, 0x32},
{0x00, 0x00}, {0x01, 0x80}, {0x02, 0x80},
};
static struct i2c_reg_u8 ov7660_init[] = {
{0x0e, 0x80}, {0x0d, 0x08}, {0x0f, 0xc3},
{0x04, 0xc3}, {0x10, 0x40}, {0x11, 0x40},
{0x12, 0x05}, {0x13, 0xba}, {0x14, 0x2a},
{0x37, 0x0f}, {0x38, 0x02}, {0x39, 0x43},
{0x3a, 0x00}, {0x69, 0x90}, {0x2d, 0xf6},
{0x2e, 0x0b}, {0x01, 0x78}, {0x02, 0x50},
};
static struct i2c_reg_u8 ov7670_init[] = {
{0x12, 0x80}, {0x11, 0x80}, {0x3a, 0x04}, {0x12, 0x01},
{0x32, 0xb6}, {0x03, 0x0a}, {0x0c, 0x00}, {0x3e, 0x00},
{0x70, 0x3a}, {0x71, 0x35}, {0x72, 0x11}, {0x73, 0xf0},
{0xa2, 0x02}, {0x13, 0xe0}, {0x00, 0x00}, {0x10, 0x00},
{0x0d, 0x40}, {0x14, 0x28}, {0xa5, 0x05}, {0xab, 0x07},
{0x24, 0x95}, {0x25, 0x33}, {0x26, 0xe3}, {0x9f, 0x75},
{0xa0, 0x65}, {0xa1, 0x0b}, {0xa6, 0xd8}, {0xa7, 0xd8},
{0xa8, 0xf0}, {0xa9, 0x90}, {0xaa, 0x94}, {0x13, 0xe5},
{0x0e, 0x61}, {0x0f, 0x4b}, {0x16, 0x02}, {0x1e, 0x27},
{0x21, 0x02}, {0x22, 0x91}, {0x29, 0x07}, {0x33, 0x0b},
{0x35, 0x0b}, {0x37, 0x1d}, {0x38, 0x71}, {0x39, 0x2a},
{0x3c, 0x78}, {0x4d, 0x40}, {0x4e, 0x20}, {0x69, 0x00},
{0x74, 0x19}, {0x8d, 0x4f}, {0x8e, 0x00}, {0x8f, 0x00},
{0x90, 0x00}, {0x91, 0x00}, {0x96, 0x00}, {0x9a, 0x80},
{0xb0, 0x84}, {0xb1, 0x0c}, {0xb2, 0x0e}, {0xb3, 0x82},
{0xb8, 0x0a}, {0x43, 0x0a}, {0x44, 0xf0}, {0x45, 0x20},
{0x46, 0x7d}, {0x47, 0x29}, {0x48, 0x4a}, {0x59, 0x8c},
{0x5a, 0xa5}, {0x5b, 0xde}, {0x5c, 0x96}, {0x5d, 0x66},
{0x5e, 0x10}, {0x6c, 0x0a}, {0x6d, 0x55}, {0x6e, 0x11},
{0x6f, 0x9e}, {0x6a, 0x40}, {0x01, 0x40}, {0x02, 0x40},
{0x13, 0xe7}, {0x4f, 0x6e}, {0x50, 0x70}, {0x51, 0x02},
{0x52, 0x1d}, {0x53, 0x56}, {0x54, 0x73}, {0x55, 0x0a},
{0x56, 0x55}, {0x57, 0x80}, {0x58, 0x9e}, {0x41, 0x08},
{0x3f, 0x02}, {0x75, 0x03}, {0x76, 0x63}, {0x4c, 0x04},
{0x77, 0x06}, {0x3d, 0x02}, {0x4b, 0x09}, {0xc9, 0x30},
{0x41, 0x08}, {0x56, 0x48}, {0x34, 0x11}, {0xa4, 0x88},
{0x96, 0x00}, {0x97, 0x30}, {0x98, 0x20}, {0x99, 0x30},
{0x9a, 0x84}, {0x9b, 0x29}, {0x9c, 0x03}, {0x9d, 0x99},
{0x9e, 0x7f}, {0x78, 0x04}, {0x79, 0x01}, {0xc8, 0xf0},
{0x79, 0x0f}, {0xc8, 0x00}, {0x79, 0x10}, {0xc8, 0x7e},
{0x79, 0x0a}, {0xc8, 0x80}, {0x79, 0x0b}, {0xc8, 0x01},
{0x79, 0x0c}, {0xc8, 0x0f}, {0x79, 0x0d}, {0xc8, 0x20},
{0x79, 0x09}, {0xc8, 0x80}, {0x79, 0x02}, {0xc8, 0xc0},
{0x79, 0x03}, {0xc8, 0x40}, {0x79, 0x05}, {0xc8, 0x30},
{0x79, 0x26}, {0x62, 0x20}, {0x63, 0x00}, {0x64, 0x06},
{0x65, 0x00}, {0x66, 0x05}, {0x94, 0x05}, {0x95, 0x0a},
{0x17, 0x13}, {0x18, 0x01}, {0x19, 0x02}, {0x1a, 0x7a},
{0x46, 0x59}, {0x47, 0x30}, {0x58, 0x9a}, {0x59, 0x84},
{0x5a, 0x91}, {0x5b, 0x57}, {0x5c, 0x75}, {0x5d, 0x6d},
{0x5e, 0x13}, {0x64, 0x07}, {0x94, 0x07}, {0x95, 0x0d},
{0xa6, 0xdf}, {0xa7, 0xdf}, {0x48, 0x4d}, {0x51, 0x00},
{0x6b, 0x0a}, {0x11, 0x80}, {0x2a, 0x00}, {0x2b, 0x00},
{0x92, 0x00}, {0x93, 0x00}, {0x55, 0x0a}, {0x56, 0x60},
{0x4f, 0x6e}, {0x50, 0x70}, {0x51, 0x00}, {0x52, 0x1d},
{0x53, 0x56}, {0x54, 0x73}, {0x58, 0x9a}, {0x4f, 0x6e},
{0x50, 0x70}, {0x51, 0x00}, {0x52, 0x1d}, {0x53, 0x56},
{0x54, 0x73}, {0x58, 0x9a}, {0x3f, 0x01}, {0x7b, 0x03},
{0x7c, 0x09}, {0x7d, 0x16}, {0x7e, 0x38}, {0x7f, 0x47},
{0x80, 0x53}, {0x81, 0x5e}, {0x82, 0x6a}, {0x83, 0x74},
{0x84, 0x80}, {0x85, 0x8c}, {0x86, 0x9b}, {0x87, 0xb2},
{0x88, 0xcc}, {0x89, 0xe5}, {0x7a, 0x24}, {0x3b, 0x00},
{0x9f, 0x76}, {0xa0, 0x65}, {0x13, 0xe2}, {0x6b, 0x0a},
{0x11, 0x80}, {0x2a, 0x00}, {0x2b, 0x00}, {0x92, 0x00},
{0x93, 0x00},
};
static struct i2c_reg_u8 ov9650_init[] = {
{0x12, 0x80}, {0x00, 0x00}, {0x01, 0x78},
{0x02, 0x78}, {0x03, 0x36}, {0x04, 0x03},
{0x05, 0x00}, {0x06, 0x00}, {0x08, 0x00},
{0x09, 0x01}, {0x0c, 0x00}, {0x0d, 0x00},
{0x0e, 0xa0}, {0x0f, 0x52}, {0x10, 0x7c},
{0x11, 0x80}, {0x12, 0x45}, {0x13, 0xc2},
{0x14, 0x2e}, {0x15, 0x00}, {0x16, 0x07},
{0x17, 0x24}, {0x18, 0xc5}, {0x19, 0x00},
{0x1a, 0x3c}, {0x1b, 0x00}, {0x1e, 0x04},
{0x1f, 0x00}, {0x24, 0x78}, {0x25, 0x68},
{0x26, 0xd4}, {0x27, 0x80}, {0x28, 0x80},
{0x29, 0x30}, {0x2a, 0x00}, {0x2b, 0x00},
{0x2c, 0x80}, {0x2d, 0x00}, {0x2e, 0x00},
{0x2f, 0x00}, {0x30, 0x08}, {0x31, 0x30},
{0x32, 0x84}, {0x33, 0xe2}, {0x34, 0xbf},
{0x35, 0x81}, {0x36, 0xf9}, {0x37, 0x00},
{0x38, 0x93}, {0x39, 0x50}, {0x3a, 0x01},
{0x3b, 0x01}, {0x3c, 0x73}, {0x3d, 0x19},
{0x3e, 0x0b}, {0x3f, 0x80}, {0x40, 0xc1},
{0x41, 0x00}, {0x42, 0x08}, {0x67, 0x80},
{0x68, 0x80}, {0x69, 0x40}, {0x6a, 0x00},
{0x6b, 0x0a}, {0x8b, 0x06}, {0x8c, 0x20},
{0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0xdf},
{0x92, 0x00}, {0x93, 0x00}, {0x94, 0x88},
{0x95, 0x88}, {0x96, 0x04}, {0xa1, 0x00},
{0xa5, 0x80}, {0xa8, 0x80}, {0xa9, 0xb8},
{0xaa, 0x92}, {0xab, 0x0a},
};
static struct i2c_reg_u8 ov9655_init[] = {
{0x12, 0x80}, {0x12, 0x01}, {0x0d, 0x00}, {0x0e, 0x61},
{0x11, 0x80}, {0x13, 0xba}, {0x14, 0x2e}, {0x16, 0x24},
{0x1e, 0x04}, {0x1e, 0x04}, {0x1e, 0x04}, {0x27, 0x08},
{0x28, 0x08}, {0x29, 0x15}, {0x2c, 0x08}, {0x32, 0xbf},
{0x34, 0x3d}, {0x35, 0x00}, {0x36, 0xf8}, {0x38, 0x12},
{0x39, 0x57}, {0x3a, 0x00}, {0x3b, 0xcc}, {0x3c, 0x0c},
{0x3d, 0x19}, {0x3e, 0x0c}, {0x3f, 0x01}, {0x41, 0x40},
{0x42, 0x80}, {0x45, 0x46}, {0x46, 0x62}, {0x47, 0x2a},
{0x48, 0x3c}, {0x4a, 0xf0}, {0x4b, 0xdc}, {0x4c, 0xdc},
{0x4d, 0xdc}, {0x4e, 0xdc}, {0x69, 0x02}, {0x6c, 0x04},
{0x6f, 0x9e}, {0x70, 0x05}, {0x71, 0x78}, {0x77, 0x02},
{0x8a, 0x23}, {0x8c, 0x0d}, {0x90, 0x7e}, {0x91, 0x7c},
{0x9f, 0x6e}, {0xa0, 0x6e}, {0xa5, 0x68}, {0xa6, 0x60},
{0xa8, 0xc1}, {0xa9, 0xfa}, {0xaa, 0x92}, {0xab, 0x04},
{0xac, 0x80}, {0xad, 0x80}, {0xae, 0x80}, {0xaf, 0x80},
{0xb2, 0xf2}, {0xb3, 0x20}, {0xb5, 0x00}, {0xb6, 0xaf},
{0xbb, 0xae}, {0xbc, 0x44}, {0xbd, 0x44}, {0xbe, 0x3b},
{0xbf, 0x3a}, {0xc0, 0xe2}, {0xc1, 0xc8}, {0xc2, 0x01},
{0xc4, 0x00}, {0xc6, 0x85}, {0xc7, 0x81}, {0xc9, 0xe0},
{0xca, 0xe8}, {0xcc, 0xd8}, {0xcd, 0x93}, {0x12, 0x61},
{0x36, 0xfa}, {0x8c, 0x8d}, {0xc0, 0xaa}, {0x69, 0x0a},
{0x03, 0x12}, {0x17, 0x14}, {0x18, 0x00}, {0x19, 0x01},
{0x1a, 0x3d}, {0x32, 0xbf}, {0x11, 0x80}, {0x2a, 0x10},
{0x2b, 0x0a}, {0x92, 0x00}, {0x93, 0x00}, {0x1e, 0x04},
{0x1e, 0x04}, {0x10, 0x7c}, {0x04, 0x03}, {0xa1, 0x00},
{0x2d, 0x00}, {0x2e, 0x00}, {0x00, 0x00}, {0x01, 0x80},
{0x02, 0x80}, {0x12, 0x61}, {0x36, 0xfa}, {0x8c, 0x8d},
{0xc0, 0xaa}, {0x69, 0x0a}, {0x03, 0x12}, {0x17, 0x14},
{0x18, 0x00}, {0x19, 0x01}, {0x1a, 0x3d}, {0x32, 0xbf},
{0x11, 0x80}, {0x2a, 0x10}, {0x2b, 0x0a}, {0x92, 0x00},
{0x93, 0x00}, {0x04, 0x01}, {0x10, 0x1f}, {0xa1, 0x00},
{0x00, 0x0a}, {0xa1, 0x00}, {0x10, 0x5d}, {0x04, 0x03},
{0x00, 0x01}, {0xa1, 0x00}, {0x10, 0x7c}, {0x04, 0x03},
{0x00, 0x03}, {0x00, 0x0a}, {0x00, 0x10}, {0x00, 0x13},
};
static struct i2c_reg_u16 mt9v112_init[] = {
{0xf0, 0x0000}, {0x0d, 0x0021}, {0x0d, 0x0020},
{0x34, 0xc019}, {0x0a, 0x0011}, {0x0b, 0x000b},
{0x20, 0x0703}, {0x35, 0x2022}, {0xf0, 0x0001},
{0x05, 0x0000}, {0x06, 0x340c}, {0x3b, 0x042a},
{0x3c, 0x0400}, {0xf0, 0x0002}, {0x2e, 0x0c58},
{0x5b, 0x0001}, {0xc8, 0x9f0b}, {0xf0, 0x0001},
{0x9b, 0x5300}, {0xf0, 0x0000}, {0x2b, 0x0020},
{0x2c, 0x002a}, {0x2d, 0x0032}, {0x2e, 0x0020},
{0x09, 0x01dc}, {0x01, 0x000c}, {0x02, 0x0020},
{0x03, 0x01e0}, {0x04, 0x0280}, {0x06, 0x000c},
{0x05, 0x0098}, {0x20, 0x0703}, {0x09, 0x01f2},
{0x2b, 0x00a0}, {0x2c, 0x00a0}, {0x2d, 0x00a0},
{0x2e, 0x00a0}, {0x01, 0x000c}, {0x02, 0x0020},
{0x03, 0x01e0}, {0x04, 0x0280}, {0x06, 0x000c},
{0x05, 0x0098}, {0x09, 0x01c1}, {0x2b, 0x00ae},
{0x2c, 0x00ae}, {0x2d, 0x00ae}, {0x2e, 0x00ae},
};
static struct i2c_reg_u16 mt9v111_init[] = {
{0x01, 0x0004}, {0x0d, 0x0001}, {0x0d, 0x0000},
{0x01, 0x0001}, {0x02, 0x0016}, {0x03, 0x01e1},
{0x04, 0x0281}, {0x05, 0x0004}, {0x07, 0x3002},
{0x21, 0x0000}, {0x25, 0x4024}, {0x26, 0xff03},
{0x27, 0xff10}, {0x2b, 0x7828}, {0x2c, 0xb43c},
{0x2d, 0xf0a0}, {0x2e, 0x0c64}, {0x2f, 0x0064},
{0x67, 0x4010}, {0x06, 0x301e}, {0x08, 0x0480},
{0x01, 0x0004}, {0x02, 0x0016}, {0x03, 0x01e6},
{0x04, 0x0286}, {0x05, 0x0004}, {0x06, 0x0000},
{0x07, 0x3002}, {0x08, 0x0008}, {0x0c, 0x0000},
{0x0d, 0x0000}, {0x0e, 0x0000}, {0x0f, 0x0000},
{0x10, 0x0000}, {0x11, 0x0000}, {0x12, 0x00b0},
{0x13, 0x007c}, {0x14, 0x0000}, {0x15, 0x0000},
{0x16, 0x0000}, {0x17, 0x0000}, {0x18, 0x0000},
{0x19, 0x0000}, {0x1a, 0x0000}, {0x1b, 0x0000},
{0x1c, 0x0000}, {0x1d, 0x0000}, {0x30, 0x0000},
{0x30, 0x0005}, {0x31, 0x0000}, {0x02, 0x0016},
{0x03, 0x01e1}, {0x04, 0x0281}, {0x05, 0x0004},
{0x06, 0x0000}, {0x07, 0x3002}, {0x06, 0x002d},
{0x05, 0x0004}, {0x09, 0x0064}, {0x2b, 0x00a0},
{0x2c, 0x00a0}, {0x2d, 0x00a0}, {0x2e, 0x00a0},
{0x02, 0x0016}, {0x03, 0x01e1}, {0x04, 0x0281},
{0x05, 0x0004}, {0x06, 0x002d}, {0x07, 0x3002},
{0x0e, 0x0008}, {0x06, 0x002d}, {0x05, 0x0004},
};
static struct i2c_reg_u16 mt9v011_init[] = {
{0x07, 0x0002}, {0x0d, 0x0001}, {0x0d, 0x0000},
{0x01, 0x0008}, {0x02, 0x0016}, {0x03, 0x01e1},
{0x04, 0x0281}, {0x05, 0x0083}, {0x06, 0x0006},
{0x0d, 0x0002}, {0x0a, 0x0000}, {0x0b, 0x0000},
{0x0c, 0x0000}, {0x0d, 0x0000}, {0x0e, 0x0000},
{0x0f, 0x0000}, {0x10, 0x0000}, {0x11, 0x0000},
{0x12, 0x0000}, {0x13, 0x0000}, {0x14, 0x0000},
{0x15, 0x0000}, {0x16, 0x0000}, {0x17, 0x0000},
{0x18, 0x0000}, {0x19, 0x0000}, {0x1a, 0x0000},
{0x1b, 0x0000}, {0x1c, 0x0000}, {0x1d, 0x0000},
{0x32, 0x0000}, {0x20, 0x1101}, {0x21, 0x0000},
{0x22, 0x0000}, {0x23, 0x0000}, {0x24, 0x0000},
{0x25, 0x0000}, {0x26, 0x0000}, {0x27, 0x0024},
{0x2f, 0xf7b0}, {0x30, 0x0005}, {0x31, 0x0000},
{0x32, 0x0000}, {0x33, 0x0000}, {0x34, 0x0100},
{0x3d, 0x068f}, {0x40, 0x01e0}, {0x41, 0x00d1},
{0x44, 0x0082}, {0x5a, 0x0000}, {0x5b, 0x0000},
{0x5c, 0x0000}, {0x5d, 0x0000}, {0x5e, 0x0000},
{0x5f, 0xa31d}, {0x62, 0x0611}, {0x0a, 0x0000},
{0x06, 0x0029}, {0x05, 0x0009}, {0x20, 0x1101},
{0x20, 0x1101}, {0x09, 0x0064}, {0x07, 0x0003},
{0x2b, 0x0033}, {0x2c, 0x00a0}, {0x2d, 0x00a0},
{0x2e, 0x0033}, {0x07, 0x0002}, {0x06, 0x0000},
{0x06, 0x0029}, {0x05, 0x0009},
};
static struct i2c_reg_u16 mt9m001_init[] = {
{0x0d, 0x0001}, {0x0d, 0x0000}, {0x01, 0x000e},
{0x02, 0x0014}, {0x03, 0x03c1}, {0x04, 0x0501},
{0x05, 0x0083}, {0x06, 0x0006}, {0x0d, 0x0002},
{0x0a, 0x0000}, {0x0c, 0x0000}, {0x11, 0x0000},
{0x1e, 0x8000}, {0x5f, 0x8904}, {0x60, 0x0000},
{0x61, 0x0000}, {0x62, 0x0498}, {0x63, 0x0000},
{0x64, 0x0000}, {0x20, 0x111d}, {0x06, 0x00f2},
{0x05, 0x0013}, {0x09, 0x10f2}, {0x07, 0x0003},
{0x2b, 0x002a}, {0x2d, 0x002a}, {0x2c, 0x002a},
{0x2e, 0x0029}, {0x07, 0x0002},
};
static struct i2c_reg_u16 mt9m111_init[] = {
{0xf0, 0x0000}, {0x0d, 0x0021}, {0x0d, 0x0008},
{0xf0, 0x0001}, {0x3a, 0x4300}, {0x9b, 0x4300},
{0x06, 0x708e}, {0xf0, 0x0002}, {0x2e, 0x0a1e},
{0xf0, 0x0000},
};
static struct i2c_reg_u8 hv7131r_init[] = {
{0x02, 0x08}, {0x02, 0x00}, {0x01, 0x08},
{0x02, 0x00}, {0x20, 0x00}, {0x21, 0xd0},
{0x22, 0x00}, {0x23, 0x09}, {0x01, 0x08},
{0x01, 0x08}, {0x01, 0x08}, {0x25, 0x07},
{0x26, 0xc3}, {0x27, 0x50}, {0x30, 0x62},
{0x31, 0x10}, {0x32, 0x06}, {0x33, 0x10},
{0x20, 0x00}, {0x21, 0xd0}, {0x22, 0x00},
{0x23, 0x09}, {0x01, 0x08},
};
static int reg_r(struct gspca_dev *gspca_dev, u16 reg, u16 length)
{
struct usb_device *dev = gspca_dev->dev;
int result;
result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
0x00,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
reg,
0x00,
gspca_dev->usb_buf,
length,
500);
if (unlikely(result < 0 || result != length)) {
err("Read register failed 0x%02X", reg);
return -EIO;
}
return 0;
}
static int reg_w(struct gspca_dev *gspca_dev, u16 reg,
const u8 *buffer, int length)
{
struct usb_device *dev = gspca_dev->dev;
int result;
memcpy(gspca_dev->usb_buf, buffer, length);
result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
0x08,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
reg,
0x00,
gspca_dev->usb_buf,
length,
500);
if (unlikely(result < 0 || result != length)) {
err("Write register failed index 0x%02X", reg);
return -EIO;
}
return 0;
}
static int reg_w1(struct gspca_dev *gspca_dev, u16 reg, const u8 value)
{
u8 data[1] = {value};
return reg_w(gspca_dev, reg, data, 1);
}
static int i2c_w(struct gspca_dev *gspca_dev, const u8 *buffer)
{
int i;
reg_w(gspca_dev, 0x10c0, buffer, 8);
for (i = 0; i < 5; i++) {
reg_r(gspca_dev, 0x10c0, 1);
if (gspca_dev->usb_buf[0] & 0x04) {
if (gspca_dev->usb_buf[0] & 0x08)
return -EIO;
return 0;
}
msleep(1);
}
return -EIO;
}
static int i2c_w1(struct gspca_dev *gspca_dev, u8 reg, u8 val)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 row[8];
/*
* from the point of view of the bridge, the length
* includes the address
*/
row[0] = 0x81 | (2 << 4);
row[1] = sd->i2c_addr;
row[2] = reg;
row[3] = val;
row[4] = 0x00;
row[5] = 0x00;
row[6] = 0x00;
row[7] = 0x10;
return i2c_w(gspca_dev, row);
}
static int i2c_w2(struct gspca_dev *gspca_dev, u8 reg, u16 val)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 row[8];
/*
* from the point of view of the bridge, the length
* includes the address
*/
row[0] = 0x81 | (3 << 4);
row[1] = sd->i2c_addr;
row[2] = reg;
row[3] = (val >> 8) & 0xff;
row[4] = val & 0xff;
row[5] = 0x00;
row[6] = 0x00;
row[7] = 0x10;
return i2c_w(gspca_dev, row);
}
int i2c_r1(struct gspca_dev *gspca_dev, u8 reg, u8 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 row[8];
row[0] = 0x81 | (1 << 4);
row[1] = sd->i2c_addr;
row[2] = reg;
row[3] = 0;
row[4] = 0;
row[5] = 0;
row[6] = 0;
row[7] = 0x10;
if (i2c_w(gspca_dev, row) < 0)
return -EIO;
row[0] = 0x81 | (1 << 4) | 0x02;
row[2] = 0;
if (i2c_w(gspca_dev, row) < 0)
return -EIO;
if (reg_r(gspca_dev, 0x10c2, 5) < 0)
return -EIO;
*val = gspca_dev->usb_buf[4];
return 0;
}
int i2c_r2(struct gspca_dev *gspca_dev, u8 reg, u16 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 row[8];
row[0] = 0x81 | (1 << 4);
row[1] = sd->i2c_addr;
row[2] = reg;
row[3] = 0;
row[4] = 0;
row[5] = 0;
row[6] = 0;
row[7] = 0x10;
if (i2c_w(gspca_dev, row) < 0)
return -EIO;
row[0] = 0x81 | (2 << 4) | 0x02;
row[2] = 0;
if (i2c_w(gspca_dev, row) < 0)
return -EIO;
if (reg_r(gspca_dev, 0x10c2, 5) < 0)
return -EIO;
*val = (gspca_dev->usb_buf[3] << 8) | gspca_dev->usb_buf[4];
return 0;
}
static int ov9650_init_sensor(struct gspca_dev *gspca_dev)
{
int i;
struct sd *sd = (struct sd *) gspca_dev;
for (i = 0; i < ARRAY_SIZE(ov9650_init); i++) {
if (i2c_w1(gspca_dev, ov9650_init[i].reg,
ov9650_init[i].val) < 0) {
err("OV9650 sensor initialization failed");
return -ENODEV;
}
}
sd->hstart = 1;
sd->vstart = 7;
return 0;
}
static int ov9655_init_sensor(struct gspca_dev *gspca_dev)
{
int i;
struct sd *sd = (struct sd *) gspca_dev;
for (i = 0; i < ARRAY_SIZE(ov9655_init); i++) {
if (i2c_w1(gspca_dev, ov9655_init[i].reg,
ov9655_init[i].val) < 0) {
err("OV9655 sensor initialization failed");
return -ENODEV;
}
}
/* disable hflip and vflip */
gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX);
sd->hstart = 0;
sd->vstart = 7;
return 0;
}
static int soi968_init_sensor(struct gspca_dev *gspca_dev)
{
int i;
struct sd *sd = (struct sd *) gspca_dev;
for (i = 0; i < ARRAY_SIZE(soi968_init); i++) {
if (i2c_w1(gspca_dev, soi968_init[i].reg,
soi968_init[i].val) < 0) {
err("SOI968 sensor initialization failed");
return -ENODEV;
}
}
/* disable hflip and vflip */
gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX) | (1 << EXPOSURE_IDX);
sd->hstart = 60;
sd->vstart = 11;
return 0;
}
static int ov7660_init_sensor(struct gspca_dev *gspca_dev)
{
int i;
struct sd *sd = (struct sd *) gspca_dev;
for (i = 0; i < ARRAY_SIZE(ov7660_init); i++) {
if (i2c_w1(gspca_dev, ov7660_init[i].reg,
ov7660_init[i].val) < 0) {
err("OV7660 sensor initialization failed");
return -ENODEV;
}
}
/* disable hflip and vflip */
gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX);
sd->hstart = 1;
sd->vstart = 1;
return 0;
}
static int ov7670_init_sensor(struct gspca_dev *gspca_dev)
{
int i;
struct sd *sd = (struct sd *) gspca_dev;
for (i = 0; i < ARRAY_SIZE(ov7670_init); i++) {
if (i2c_w1(gspca_dev, ov7670_init[i].reg,
ov7670_init[i].val) < 0) {
err("OV7670 sensor initialization failed");
return -ENODEV;
}
}
/* disable hflip and vflip */
gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX);
sd->hstart = 0;
sd->vstart = 1;
return 0;
}
static int mt9v_init_sensor(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
int i;
u16 value;
int ret;
sd->i2c_addr = 0x5d;
ret = i2c_r2(gspca_dev, 0xff, &value);
if ((ret == 0) && (value == 0x8243)) {
for (i = 0; i < ARRAY_SIZE(mt9v011_init); i++) {
if (i2c_w2(gspca_dev, mt9v011_init[i].reg,
mt9v011_init[i].val) < 0) {
err("MT9V011 sensor initialization failed");
return -ENODEV;
}
}
sd->hstart = 2;
sd->vstart = 2;
sd->sensor = SENSOR_MT9V011;
info("MT9V011 sensor detected");
return 0;
}
sd->i2c_addr = 0x5c;
i2c_w2(gspca_dev, 0x01, 0x0004);
ret = i2c_r2(gspca_dev, 0xff, &value);
if ((ret == 0) && (value == 0x823a)) {
for (i = 0; i < ARRAY_SIZE(mt9v111_init); i++) {
if (i2c_w2(gspca_dev, mt9v111_init[i].reg,
mt9v111_init[i].val) < 0) {
err("MT9V111 sensor initialization failed");
return -ENODEV;
}
}
sd->hstart = 2;
sd->vstart = 2;
sd->sensor = SENSOR_MT9V111;
info("MT9V111 sensor detected");
return 0;
}
sd->i2c_addr = 0x5d;
ret = i2c_w2(gspca_dev, 0xf0, 0x0000);
if (ret < 0) {
sd->i2c_addr = 0x48;
i2c_w2(gspca_dev, 0xf0, 0x0000);
}
ret = i2c_r2(gspca_dev, 0x00, &value);
if ((ret == 0) && (value == 0x1229)) {
for (i = 0; i < ARRAY_SIZE(mt9v112_init); i++) {
if (i2c_w2(gspca_dev, mt9v112_init[i].reg,
mt9v112_init[i].val) < 0) {
err("MT9V112 sensor initialization failed");
return -ENODEV;
}
}
sd->hstart = 6;
sd->vstart = 2;
sd->sensor = SENSOR_MT9V112;
info("MT9V112 sensor detected");
return 0;
}
return -ENODEV;
}
static int mt9m111_init_sensor(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
int i;
for (i = 0; i < ARRAY_SIZE(mt9m111_init); i++) {
if (i2c_w2(gspca_dev, mt9m111_init[i].reg,
mt9m111_init[i].val) < 0) {
err("MT9M111 sensor initialization failed");
return -ENODEV;
}
}
gspca_dev->ctrl_dis = (1 << EXPOSURE_IDX) | (1 << AUTOGAIN_IDX) | (1 << GAIN_IDX);
sd->hstart = 0;
sd->vstart = 2;
return 0;
}
static int mt9m001_init_sensor(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
int i;
for (i = 0; i < ARRAY_SIZE(mt9m001_init); i++) {
if (i2c_w2(gspca_dev, mt9m001_init[i].reg,
mt9m001_init[i].val) < 0) {
err("MT9M001 sensor initialization failed");
return -ENODEV;
}
}
/* disable hflip and vflip */
gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX);
sd->hstart = 2;
sd->vstart = 2;
return 0;
}
static int hv7131r_init_sensor(struct gspca_dev *gspca_dev)
{
int i;
struct sd *sd = (struct sd *) gspca_dev;
for (i = 0; i < ARRAY_SIZE(hv7131r_init); i++) {
if (i2c_w1(gspca_dev, hv7131r_init[i].reg,
hv7131r_init[i].val) < 0) {
err("HV7131R Sensor initialization failed");
return -ENODEV;
}
}
sd->hstart = 0;
sd->vstart = 1;
return 0;
}
#ifdef CONFIG_USB_GSPCA_SN9C20X_EVDEV
static int input_kthread(void *data)
{
struct gspca_dev *gspca_dev = (struct gspca_dev *)data;
struct sd *sd = (struct sd *) gspca_dev;
DECLARE_WAIT_QUEUE_HEAD(wait);
set_freezable();
for (;;) {
if (kthread_should_stop())
break;
if (reg_r(gspca_dev, 0x1005, 1) < 0)
continue;
input_report_key(sd->input_dev,
KEY_CAMERA,
gspca_dev->usb_buf[0] & sd->input_gpio);
input_sync(sd->input_dev);
wait_event_freezable_timeout(wait,
kthread_should_stop(),
msecs_to_jiffies(100));
}
return 0;
}
static int sn9c20x_input_init(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
if (sd->input_gpio == 0)
return 0;
sd->input_dev = input_allocate_device();
if (!sd->input_dev)
return -ENOMEM;
sd->input_dev->name = "SN9C20X Webcam";
sd->input_dev->phys = kasprintf(GFP_KERNEL, "usb-%s-%s",
gspca_dev->dev->bus->bus_name,
gspca_dev->dev->devpath);
if (!sd->input_dev->phys)
return -ENOMEM;
usb_to_input_id(gspca_dev->dev, &sd->input_dev->id);
sd->input_dev->dev.parent = &gspca_dev->dev->dev;
set_bit(EV_KEY, sd->input_dev->evbit);
set_bit(KEY_CAMERA, sd->input_dev->keybit);
if (input_register_device(sd->input_dev))
return -EINVAL;
sd->input_task = kthread_run(input_kthread, gspca_dev, "sn9c20x/%d",
gspca_dev->vdev.minor);
if (IS_ERR(sd->input_task))
return -EINVAL;
return 0;
}
static void sn9c20x_input_cleanup(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
if (sd->input_task != NULL && !IS_ERR(sd->input_task))
kthread_stop(sd->input_task);
if (sd->input_dev != NULL) {
input_unregister_device(sd->input_dev);
kfree(sd->input_dev->phys);
input_free_device(sd->input_dev);
sd->input_dev = NULL;
}
}
#endif
static int set_cmatrix(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
s32 hue_coord, hue_index = 180 + sd->hue;
u8 cmatrix[21];
memset(cmatrix, 0, 21);
cmatrix[2] = (sd->contrast * 0x25 / 0x100) + 0x26;
cmatrix[0] = 0x13 + (cmatrix[2] - 0x26) * 0x13 / 0x25;
cmatrix[4] = 0x07 + (cmatrix[2] - 0x26) * 0x07 / 0x25;
cmatrix[18] = sd->brightness - 0x80;
hue_coord = (hsv_red_x[hue_index] * sd->saturation) >> 8;
cmatrix[6] = (unsigned char)(hue_coord & 0xff);
cmatrix[7] = (unsigned char)((hue_coord >> 8) & 0x0f);
hue_coord = (hsv_red_y[hue_index] * sd->saturation) >> 8;
cmatrix[8] = (unsigned char)(hue_coord & 0xff);
cmatrix[9] = (unsigned char)((hue_coord >> 8) & 0x0f);
hue_coord = (hsv_green_x[hue_index] * sd->saturation) >> 8;
cmatrix[10] = (unsigned char)(hue_coord & 0xff);
cmatrix[11] = (unsigned char)((hue_coord >> 8) & 0x0f);
hue_coord = (hsv_green_y[hue_index] * sd->saturation) >> 8;
cmatrix[12] = (unsigned char)(hue_coord & 0xff);
cmatrix[13] = (unsigned char)((hue_coord >> 8) & 0x0f);
hue_coord = (hsv_blue_x[hue_index] * sd->saturation) >> 8;
cmatrix[14] = (unsigned char)(hue_coord & 0xff);
cmatrix[15] = (unsigned char)((hue_coord >> 8) & 0x0f);
hue_coord = (hsv_blue_y[hue_index] * sd->saturation) >> 8;
cmatrix[16] = (unsigned char)(hue_coord & 0xff);
cmatrix[17] = (unsigned char)((hue_coord >> 8) & 0x0f);
return reg_w(gspca_dev, 0x10e1, cmatrix, 21);
}
static int set_gamma(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 gamma[17];
u8 gval = sd->gamma * 0xb8 / 0x100;
gamma[0] = 0x0a;
gamma[1] = 0x13 + (gval * (0xcb - 0x13) / 0xb8);
gamma[2] = 0x25 + (gval * (0xee - 0x25) / 0xb8);
gamma[3] = 0x37 + (gval * (0xfa - 0x37) / 0xb8);
gamma[4] = 0x45 + (gval * (0xfc - 0x45) / 0xb8);
gamma[5] = 0x55 + (gval * (0xfb - 0x55) / 0xb8);
gamma[6] = 0x65 + (gval * (0xfc - 0x65) / 0xb8);
gamma[7] = 0x74 + (gval * (0xfd - 0x74) / 0xb8);
gamma[8] = 0x83 + (gval * (0xfe - 0x83) / 0xb8);
gamma[9] = 0x92 + (gval * (0xfc - 0x92) / 0xb8);
gamma[10] = 0xa1 + (gval * (0xfc - 0xa1) / 0xb8);
gamma[11] = 0xb0 + (gval * (0xfc - 0xb0) / 0xb8);
gamma[12] = 0xbf + (gval * (0xfb - 0xbf) / 0xb8);
gamma[13] = 0xce + (gval * (0xfb - 0xce) / 0xb8);
gamma[14] = 0xdf + (gval * (0xfd - 0xdf) / 0xb8);
gamma[15] = 0xea + (gval * (0xf9 - 0xea) / 0xb8);
gamma[16] = 0xf5;
return reg_w(gspca_dev, 0x1190, gamma, 17);
}
static int set_redblue(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
reg_w1(gspca_dev, 0x118c, sd->red);
reg_w1(gspca_dev, 0x118f, sd->blue);
return 0;
}
static int set_hvflip(struct gspca_dev *gspca_dev)
{
u8 value, tslb;
u16 value2;
struct sd *sd = (struct sd *) gspca_dev;
switch (sd->sensor) {
case SENSOR_OV9650:
i2c_r1(gspca_dev, 0x1e, &value);
value &= ~0x30;
tslb = 0x01;
if (sd->hflip)
value |= 0x20;
if (sd->vflip) {
value |= 0x10;
tslb = 0x49;
}
i2c_w1(gspca_dev, 0x1e, value);
i2c_w1(gspca_dev, 0x3a, tslb);
break;
case SENSOR_MT9V111:
case SENSOR_MT9V011:
i2c_r2(gspca_dev, 0x20, &value2);
value2 &= ~0xc0a0;
if (sd->hflip)
value2 |= 0x8080;
if (sd->vflip)
value2 |= 0x4020;
i2c_w2(gspca_dev, 0x20, value2);
break;
case SENSOR_MT9M111:
case SENSOR_MT9V112:
i2c_r2(gspca_dev, 0x20, &value2);
value2 &= ~0x0003;
if (sd->hflip)
value2 |= 0x0002;
if (sd->vflip)
value2 |= 0x0001;
i2c_w2(gspca_dev, 0x20, value2);
break;
case SENSOR_HV7131R:
i2c_r1(gspca_dev, 0x01, &value);
value &= ~0x03;
if (sd->vflip)
value |= 0x01;
if (sd->hflip)
value |= 0x02;
i2c_w1(gspca_dev, 0x01, value);
break;
}
return 0;
}
static int set_exposure(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 exp[8] = {0x81, sd->i2c_addr, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e};
switch (sd->sensor) {
case SENSOR_OV7660:
case SENSOR_OV7670:
case SENSOR_OV9655:
case SENSOR_OV9650:
exp[0] |= (3 << 4);
exp[2] = 0x2d;
exp[3] = sd->exposure & 0xff;
exp[4] = sd->exposure >> 8;
break;
case SENSOR_MT9M001:
case SENSOR_MT9V112:
case SENSOR_MT9V111:
case SENSOR_MT9V011:
exp[0] |= (3 << 4);
exp[2] = 0x09;
exp[3] = sd->exposure >> 8;
exp[4] = sd->exposure & 0xff;
break;
case SENSOR_HV7131R:
exp[0] |= (4 << 4);
exp[2] = 0x25;
exp[3] = ((sd->exposure * 0xffffff) / 0xffff) >> 16;
exp[4] = ((sd->exposure * 0xffffff) / 0xffff) >> 8;
exp[5] = ((sd->exposure * 0xffffff) / 0xffff) & 0xff;
break;
default:
return 0;
}
i2c_w(gspca_dev, exp);
return 0;
}
static int set_gain(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 gain[8] = {0x81, sd->i2c_addr, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d};
switch (sd->sensor) {
case SENSOR_OV7660:
case SENSOR_OV7670:
case SENSOR_SOI968:
case SENSOR_OV9655:
case SENSOR_OV9650:
gain[0] |= (2 << 4);
gain[3] = ov_gain[sd->gain];
break;
case SENSOR_MT9V011:
case SENSOR_MT9V111:
gain[0] |= (3 << 4);
gain[2] = 0x35;
gain[3] = micron1_gain[sd->gain] >> 8;
gain[4] = micron1_gain[sd->gain] & 0xff;
break;
case SENSOR_MT9V112:
gain[0] |= (3 << 4);
gain[2] = 0x2f;
gain[3] = micron1_gain[sd->gain] >> 8;
gain[4] = micron1_gain[sd->gain] & 0xff;
break;
case SENSOR_MT9M001:
gain[0] |= (3 << 4);
gain[2] = 0x2f;
gain[3] = micron2_gain[sd->gain] >> 8;
gain[4] = micron2_gain[sd->gain] & 0xff;
break;
case SENSOR_HV7131R:
gain[0] |= (2 << 4);
gain[2] = 0x30;
gain[3] = hv7131r_gain[sd->gain];
break;
default:
return 0;
}
i2c_w(gspca_dev, gain);
return 0;
}
static int sd_setbrightness(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->brightness = val;
if (gspca_dev->streaming)
return set_cmatrix(gspca_dev);
return 0;
}
static int sd_getbrightness(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->brightness;
return 0;
}
static int sd_setcontrast(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->contrast = val;
if (gspca_dev->streaming)
return set_cmatrix(gspca_dev);
return 0;
}
static int sd_getcontrast(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->contrast;
return 0;
}
static int sd_setsaturation(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->saturation = val;
if (gspca_dev->streaming)
return set_cmatrix(gspca_dev);
return 0;
}
static int sd_getsaturation(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->saturation;
return 0;
}
static int sd_sethue(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->hue = val;
if (gspca_dev->streaming)
return set_cmatrix(gspca_dev);
return 0;
}
static int sd_gethue(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->hue;
return 0;
}
static int sd_setgamma(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->gamma = val;
if (gspca_dev->streaming)
return set_gamma(gspca_dev);
return 0;
}
static int sd_getgamma(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->gamma;
return 0;
}
static int sd_setredbalance(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->red = val;
if (gspca_dev->streaming)
return set_redblue(gspca_dev);
return 0;
}
static int sd_getredbalance(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->red;
return 0;
}
static int sd_setbluebalance(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->blue = val;
if (gspca_dev->streaming)
return set_redblue(gspca_dev);
return 0;
}
static int sd_getbluebalance(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->blue;
return 0;
}
static int sd_sethflip(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->hflip = val;
if (gspca_dev->streaming)
return set_hvflip(gspca_dev);
return 0;
}
static int sd_gethflip(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->hflip;
return 0;
}
static int sd_setvflip(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->vflip = val;
if (gspca_dev->streaming)
return set_hvflip(gspca_dev);
return 0;
}
static int sd_getvflip(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->vflip;
return 0;
}
static int sd_setexposure(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->exposure = val;
if (gspca_dev->streaming)
return set_exposure(gspca_dev);
return 0;
}
static int sd_getexposure(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->exposure;
return 0;
}
static int sd_setgain(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->gain = val;
if (gspca_dev->streaming)
return set_gain(gspca_dev);
return 0;
}
static int sd_getgain(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->gain;
return 0;
}
static int sd_setautoexposure(struct gspca_dev *gspca_dev, s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->auto_exposure = val;
return 0;
}
static int sd_getautoexposure(struct gspca_dev *gspca_dev, s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->auto_exposure;
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int sd_dbg_g_register(struct gspca_dev *gspca_dev,
struct v4l2_dbg_register *reg)
{
struct sd *sd = (struct sd *) gspca_dev;
switch (reg->match.type) {
case V4L2_CHIP_MATCH_HOST:
if (reg->match.addr != 0)
return -EINVAL;
if (reg->reg < 0x1000 || reg->reg > 0x11ff)
return -EINVAL;
if (reg_r(gspca_dev, reg->reg, 1) < 0)
return -EINVAL;
reg->val = gspca_dev->usb_buf[0];
return 0;
case V4L2_CHIP_MATCH_I2C_ADDR:
if (reg->match.addr != sd->i2c_addr)
return -EINVAL;
if (sd->sensor >= SENSOR_MT9V011 &&
sd->sensor <= SENSOR_MT9M111) {
if (i2c_r2(gspca_dev, reg->reg, (u16 *)®->val) < 0)
return -EINVAL;
} else {
if (i2c_r1(gspca_dev, reg->reg, (u8 *)®->val) < 0)
return -EINVAL;
}
return 0;
}
return -EINVAL;
}
static int sd_dbg_s_register(struct gspca_dev *gspca_dev,
struct v4l2_dbg_register *reg)
{
struct sd *sd = (struct sd *) gspca_dev;
switch (reg->match.type) {
case V4L2_CHIP_MATCH_HOST:
if (reg->match.addr != 0)
return -EINVAL;
if (reg->reg < 0x1000 || reg->reg > 0x11ff)
return -EINVAL;
if (reg_w1(gspca_dev, reg->reg, reg->val) < 0)
return -EINVAL;
return 0;
case V4L2_CHIP_MATCH_I2C_ADDR:
if (reg->match.addr != sd->i2c_addr)
return -EINVAL;
if (sd->sensor >= SENSOR_MT9V011 &&
sd->sensor <= SENSOR_MT9M111) {
if (i2c_w2(gspca_dev, reg->reg, reg->val) < 0)
return -EINVAL;
} else {
if (i2c_w1(gspca_dev, reg->reg, reg->val) < 0)
return -EINVAL;
}
return 0;
}
return -EINVAL;
}
#endif
static int sd_chip_ident(struct gspca_dev *gspca_dev,
struct v4l2_dbg_chip_ident *chip)
{
struct sd *sd = (struct sd *) gspca_dev;
switch (chip->match.type) {
case V4L2_CHIP_MATCH_HOST:
if (chip->match.addr != 0)
return -EINVAL;
chip->revision = 0;
chip->ident = V4L2_IDENT_SN9C20X;
return 0;
case V4L2_CHIP_MATCH_I2C_ADDR:
if (chip->match.addr != sd->i2c_addr)
return -EINVAL;
chip->revision = 0;
chip->ident = i2c_ident[sd->sensor];
return 0;
}
return -EINVAL;
}
static int sd_config(struct gspca_dev *gspca_dev,
const struct usb_device_id *id)
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
cam = &gspca_dev->cam;
sd->sensor = (id->driver_info >> 8) & 0xff;
sd->i2c_addr = id->driver_info & 0xff;
switch (sd->sensor) {
case SENSOR_MT9M111:
case SENSOR_OV9650:
case SENSOR_SOI968:
cam->cam_mode = sxga_mode;
cam->nmodes = ARRAY_SIZE(sxga_mode);
break;
default:
cam->cam_mode = vga_mode;
cam->nmodes = ARRAY_SIZE(vga_mode);
}
sd->old_step = 0;
sd->older_step = 0;
sd->exposure_step = 16;
sd->brightness = BRIGHTNESS_DEFAULT;
sd->contrast = CONTRAST_DEFAULT;
sd->saturation = SATURATION_DEFAULT;
sd->hue = HUE_DEFAULT;
sd->gamma = GAMMA_DEFAULT;
sd->red = RED_DEFAULT;
sd->blue = BLUE_DEFAULT;
sd->hflip = HFLIP_DEFAULT;
sd->vflip = VFLIP_DEFAULT;
sd->exposure = EXPOSURE_DEFAULT;
sd->gain = GAIN_DEFAULT;
sd->auto_exposure = AUTO_EXPOSURE_DEFAULT;
sd->quality = 95;
#ifdef CONFIG_USB_GSPCA_SN9C20X_EVDEV
sd->input_gpio = (id->driver_info >> 16) & 0xff;
if (sn9c20x_input_init(gspca_dev) < 0)
return -ENODEV;
#endif
return 0;
}
static int sd_init(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
int i;
u8 value;
u8 i2c_init[9] =
{0x80, sd->i2c_addr, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03};
for (i = 0; i < ARRAY_SIZE(bridge_init); i++) {
value = bridge_init[i][1];
if (reg_w(gspca_dev, bridge_init[i][0], &value, 1) < 0) {
err("Device initialization failed");
return -ENODEV;
}
}
if (reg_w(gspca_dev, 0x10c0, i2c_init, 9) < 0) {
err("Device initialization failed");
return -ENODEV;
}
switch (sd->sensor) {
case SENSOR_OV9650:
if (ov9650_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("OV9650 sensor detected");
break;
case SENSOR_OV9655:
if (ov9655_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("OV9655 sensor detected");
break;
case SENSOR_SOI968:
if (soi968_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("SOI968 sensor detected");
break;
case SENSOR_OV7660:
if (ov7660_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("OV7660 sensor detected");
break;
case SENSOR_OV7670:
if (ov7670_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("OV7670 sensor detected");
break;
case SENSOR_MT9VPRB:
if (mt9v_init_sensor(gspca_dev) < 0)
return -ENODEV;
break;
case SENSOR_MT9M111:
if (mt9m111_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("MT9M111 sensor detected");
break;
case SENSOR_MT9M001:
if (mt9m001_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("MT9M001 sensor detected");
break;
case SENSOR_HV7131R:
if (hv7131r_init_sensor(gspca_dev) < 0)
return -ENODEV;
info("HV7131R sensor detected");
break;
default:
info("Unsupported Sensor");
return -ENODEV;
}
return 0;
}
static void configure_sensor_output(struct gspca_dev *gspca_dev, int mode)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 value;
switch (sd->sensor) {
case SENSOR_SOI968:
if (mode & MODE_SXGA) {
i2c_w1(gspca_dev, 0x17, 0x1d);
i2c_w1(gspca_dev, 0x18, 0xbd);
i2c_w1(gspca_dev, 0x19, 0x01);
i2c_w1(gspca_dev, 0x1a, 0x81);
i2c_w1(gspca_dev, 0x12, 0x00);
sd->hstart = 140;
sd->vstart = 19;
} else {
i2c_w1(gspca_dev, 0x17, 0x13);
i2c_w1(gspca_dev, 0x18, 0x63);
i2c_w1(gspca_dev, 0x19, 0x01);
i2c_w1(gspca_dev, 0x1a, 0x79);
i2c_w1(gspca_dev, 0x12, 0x40);
sd->hstart = 60;
sd->vstart = 11;
}
break;
case SENSOR_OV9650:
if (mode & MODE_SXGA) {
i2c_w1(gspca_dev, 0x17, 0x1b);
i2c_w1(gspca_dev, 0x18, 0xbc);
i2c_w1(gspca_dev, 0x19, 0x01);
i2c_w1(gspca_dev, 0x1a, 0x82);
i2c_r1(gspca_dev, 0x12, &value);
i2c_w1(gspca_dev, 0x12, value & 0x07);
} else {
i2c_w1(gspca_dev, 0x17, 0x24);
i2c_w1(gspca_dev, 0x18, 0xc5);
i2c_w1(gspca_dev, 0x19, 0x00);
i2c_w1(gspca_dev, 0x1a, 0x3c);
i2c_r1(gspca_dev, 0x12, &value);
i2c_w1(gspca_dev, 0x12, (value & 0x7) | 0x40);
}
break;
case SENSOR_MT9M111:
if (mode & MODE_SXGA) {
i2c_w2(gspca_dev, 0xf0, 0x0002);
i2c_w2(gspca_dev, 0xc8, 0x970b);
i2c_w2(gspca_dev, 0xf0, 0x0000);
} else {
i2c_w2(gspca_dev, 0xf0, 0x0002);
i2c_w2(gspca_dev, 0xc8, 0x8000);
i2c_w2(gspca_dev, 0xf0, 0x0000);
}
break;
}
}
#define HW_WIN(mode, hstart, vstart) \
((const u8 []){hstart & 0xff, hstart >> 8, \
vstart & 0xff, vstart >> 8, \
(mode & MODE_SXGA ? 1280 >> 4 : 640 >> 4), \
(mode & MODE_SXGA ? 1024 >> 3 : 480 >> 3)})
#define CLR_WIN(width, height) \
((const u8 [])\
{0, width >> 2, 0, height >> 1,\
((width >> 10) & 0x01) | ((height >> 8) & 0x6)})
static int sd_start(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
int mode = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv;
int width = gspca_dev->width;
int height = gspca_dev->height;
u8 fmt, scale = 0;
sd->jpeg_hdr = kmalloc(JPEG_HDR_SZ, GFP_KERNEL);
if (sd->jpeg_hdr == NULL)
return -ENOMEM;
jpeg_define(sd->jpeg_hdr, height, width,
0x21);
jpeg_set_qual(sd->jpeg_hdr, sd->quality);
if (mode & MODE_RAW)
fmt = 0x2d;
else if (mode & MODE_JPEG)
fmt = 0x2c;
else
fmt = 0x2f;
switch (mode & 0x0f) {
case 3:
scale = 0xc0;
info("Set 1280x1024");
break;
case 2:
scale = 0x80;
info("Set 640x480");
break;
case 1:
scale = 0x90;
info("Set 320x240");
break;
case 0:
scale = 0xa0;
info("Set 160x120");
break;
}
configure_sensor_output(gspca_dev, mode);
reg_w(gspca_dev, 0x1100, sd->jpeg_hdr + JPEG_QT0_OFFSET, 64);
reg_w(gspca_dev, 0x1140, sd->jpeg_hdr + JPEG_QT1_OFFSET, 64);
reg_w(gspca_dev, 0x10fb, CLR_WIN(width, height), 5);
reg_w(gspca_dev, 0x1180, HW_WIN(mode, sd->hstart, sd->vstart), 6);
reg_w1(gspca_dev, 0x1189, scale);
reg_w1(gspca_dev, 0x10e0, fmt);
set_cmatrix(gspca_dev);
set_gamma(gspca_dev);
set_redblue(gspca_dev);
set_gain(gspca_dev);
set_exposure(gspca_dev);
set_hvflip(gspca_dev);
reg_r(gspca_dev, 0x1061, 1);
reg_w1(gspca_dev, 0x1061, gspca_dev->usb_buf[0] | 0x02);
return 0;
}
static void sd_stopN(struct gspca_dev *gspca_dev)
{
reg_r(gspca_dev, 0x1061, 1);
reg_w1(gspca_dev, 0x1061, gspca_dev->usb_buf[0] & ~0x02);
}
static void sd_stop0(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
kfree(sd->jpeg_hdr);
}
static void do_autoexposure(struct gspca_dev *gspca_dev, u16 avg_lum)
{
struct sd *sd = (struct sd *) gspca_dev;
s16 new_exp;
/*
* some hardcoded values are present
* like those for maximal/minimal exposure
* and exposure steps
*/
if (avg_lum < MIN_AVG_LUM) {
if (sd->exposure > 0x1770)
return;
new_exp = sd->exposure + sd->exposure_step;
if (new_exp > 0x1770)
new_exp = 0x1770;
if (new_exp < 0x10)
new_exp = 0x10;
sd->exposure = new_exp;
set_exposure(gspca_dev);
sd->older_step = sd->old_step;
sd->old_step = 1;
if (sd->old_step ^ sd->older_step)
sd->exposure_step /= 2;
else
sd->exposure_step += 2;
}
if (avg_lum > MAX_AVG_LUM) {
if (sd->exposure < 0x10)
return;
new_exp = sd->exposure - sd->exposure_step;
if (new_exp > 0x1700)
new_exp = 0x1770;
if (new_exp < 0x10)
new_exp = 0x10;
sd->exposure = new_exp;
set_exposure(gspca_dev);
sd->older_step = sd->old_step;
sd->old_step = 0;
if (sd->old_step ^ sd->older_step)
sd->exposure_step /= 2;
else
sd->exposure_step += 2;
}
}
static void do_autogain(struct gspca_dev *gspca_dev, u16 avg_lum)
{
struct sd *sd = (struct sd *) gspca_dev;
if (avg_lum < MIN_AVG_LUM) {
if (sd->gain + 1 <= 28) {
sd->gain++;
set_gain(gspca_dev);
}
}
if (avg_lum > MAX_AVG_LUM) {
if (sd->gain >= 1) {
sd->gain--;
set_gain(gspca_dev);
}
}
}
static void sd_dqcallback(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
int avg_lum;
if (!sd->auto_exposure)
return;
avg_lum = atomic_read(&sd->avg_lum);
if (sd->sensor == SENSOR_SOI968)
do_autogain(gspca_dev, avg_lum);
else
do_autoexposure(gspca_dev, avg_lum);
}
static void sd_pkt_scan(struct gspca_dev *gspca_dev,
struct gspca_frame *frame, /* target */
u8 *data, /* isoc packet */
int len) /* iso packet length */
{
struct sd *sd = (struct sd *) gspca_dev;
int avg_lum;
static unsigned char frame_header[] =
{0xff, 0xff, 0x00, 0xc4, 0xc4, 0x96};
if (len == 64 && memcmp(data, frame_header, 6) == 0) {
avg_lum = ((data[35] >> 2) & 3) |
(data[20] << 2) |
(data[19] << 10);
avg_lum += ((data[35] >> 4) & 3) |
(data[22] << 2) |
(data[21] << 10);
avg_lum += ((data[35] >> 6) & 3) |
(data[24] << 2) |
(data[23] << 10);
avg_lum += (data[36] & 3) |
(data[26] << 2) |
(data[25] << 10);
avg_lum += ((data[36] >> 2) & 3) |
(data[28] << 2) |
(data[27] << 10);
avg_lum += ((data[36] >> 4) & 3) |
(data[30] << 2) |
(data[29] << 10);
avg_lum += ((data[36] >> 6) & 3) |
(data[32] << 2) |
(data[31] << 10);
avg_lum += ((data[44] >> 4) & 3) |
(data[34] << 2) |
(data[33] << 10);
avg_lum >>= 9;
atomic_set(&sd->avg_lum, avg_lum);
gspca_frame_add(gspca_dev, LAST_PACKET,
frame, data, len);
return;
}
if (gspca_dev->last_packet_type == LAST_PACKET) {
if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv
& MODE_JPEG) {
gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
sd->jpeg_hdr, JPEG_HDR_SZ);
gspca_frame_add(gspca_dev, INTER_PACKET, frame,
data, len);
} else {
gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
data, len);
}
} else {
gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len);
}
}
/* sub-driver description */
static const struct sd_desc sd_desc = {
.name = MODULE_NAME,
.ctrls = sd_ctrls,
.nctrls = ARRAY_SIZE(sd_ctrls),
.config = sd_config,
.init = sd_init,
.start = sd_start,
.stopN = sd_stopN,
.stop0 = sd_stop0,
.pkt_scan = sd_pkt_scan,
.dq_callback = sd_dqcallback,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.set_register = sd_dbg_s_register,
.get_register = sd_dbg_g_register,
#endif
.get_chip_ident = sd_chip_ident,
};
#define SN9C20X(sensor, i2c_addr, button_mask) \
.driver_info = (button_mask << 16) \
| (SENSOR_ ## sensor << 8) \
| (i2c_addr)
static const __devinitdata struct usb_device_id device_table[] = {
{USB_DEVICE(0x0c45, 0x6240), SN9C20X(MT9M001, 0x5d, 0)},
{USB_DEVICE(0x0c45, 0x6242), SN9C20X(MT9M111, 0x5d, 0)},
{USB_DEVICE(0x0c45, 0x6248), SN9C20X(OV9655, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x624e), SN9C20X(SOI968, 0x30, 0x10)},
{USB_DEVICE(0x0c45, 0x624f), SN9C20X(OV9650, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x6251), SN9C20X(OV9650, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x6253), SN9C20X(OV9650, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x6260), SN9C20X(OV7670, 0x21, 0)},
{USB_DEVICE(0x0c45, 0x6270), SN9C20X(MT9VPRB, 0x00, 0)},
{USB_DEVICE(0x0c45, 0x627b), SN9C20X(OV7660, 0x21, 0)},
{USB_DEVICE(0x0c45, 0x627c), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0x0c45, 0x627f), SN9C20X(OV9650, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x6280), SN9C20X(MT9M001, 0x5d, 0)},
{USB_DEVICE(0x0c45, 0x6282), SN9C20X(MT9M111, 0x5d, 0)},
{USB_DEVICE(0x0c45, 0x6288), SN9C20X(OV9655, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x628e), SN9C20X(SOI968, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x628f), SN9C20X(OV9650, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x62a0), SN9C20X(OV7670, 0x21, 0)},
{USB_DEVICE(0x0c45, 0x62b0), SN9C20X(MT9VPRB, 0x00, 0)},
{USB_DEVICE(0x0c45, 0x62b3), SN9C20X(OV9655, 0x30, 0)},
{USB_DEVICE(0x0c45, 0x62bb), SN9C20X(OV7660, 0x21, 0)},
{USB_DEVICE(0x0c45, 0x62bc), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0x045e, 0x00f4), SN9C20X(OV9650, 0x30, 0)},
{USB_DEVICE(0x145f, 0x013d), SN9C20X(OV7660, 0x21, 0)},
{USB_DEVICE(0x0458, 0x7029), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0xa168, 0x0610), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0xa168, 0x0611), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0xa168, 0x0613), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0xa168, 0x0618), SN9C20X(HV7131R, 0x11, 0)},
{USB_DEVICE(0xa168, 0x0614), SN9C20X(MT9M111, 0x5d, 0)},
{USB_DEVICE(0xa168, 0x0615), SN9C20X(MT9M111, 0x5d, 0)},
{USB_DEVICE(0xa168, 0x0617), SN9C20X(MT9M111, 0x5d, 0)},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
/* -- device connect -- */
static int sd_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
THIS_MODULE);
}
static void sd_disconnect(struct usb_interface *intf)
{
#ifdef CONFIG_USB_GSPCA_SN9C20X_EVDEV
struct gspca_dev *gspca_dev = usb_get_intfdata(intf);
sn9c20x_input_cleanup(gspca_dev);
#endif
gspca_disconnect(intf);
}
static struct usb_driver sd_driver = {
.name = MODULE_NAME,
.id_table = device_table,
.probe = sd_probe,
.disconnect = sd_disconnect,
#ifdef CONFIG_PM
.suspend = gspca_suspend,
.resume = gspca_resume,
.reset_resume = gspca_resume,
#endif
};
/* -- module insert / remove -- */
static int __init sd_mod_init(void)
{
int ret;
ret = usb_register(&sd_driver);
if (ret < 0)
return ret;
info("registered");
return 0;
}
static void __exit sd_mod_exit(void)
{
usb_deregister(&sd_driver);
info("deregistered");
}
module_init(sd_mod_init);
module_exit(sd_mod_exit);
| gpl-2.0 |
mifl/android_kernel_pantech_ef45k | sound/soc/msm/msm8660-apq-wm8903.c | 431 | 18623 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/mfd/pmic8058.h>
#include <linux/mfd/pmic8901.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/delay.h>
#include <mach/mpp.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/soc-dsp.h>
#include <sound/pcm.h>
#include <asm/mach-types.h>
#include "msm-pcm-routing.h"
#include "../codecs/wm8903.h"
#define MSM_GPIO_CLASS_D0_EN 80
#define MSM_GPIO_CLASS_D1_EN 81
#define MSM_CDC_MIC_I2S_MCLK 108
static int msm8660_spk_func;
static int msm8660_headset_func;
static int msm8660_headphone_func;
static struct clk *mic_bit_clk;
static struct clk *spkr_osr_clk;
static struct clk *spkr_bit_clk;
static struct clk *wm8903_mclk;
static int rx_hw_param_status;
static int tx_hw_param_status;
/* Platform specific logic */
enum {
GET_ERR,
SET_ERR,
ENABLE_ERR,
NONE
};
enum {
FUNC_OFF,
FUNC_ON,
};
static struct wm8903_vdd {
struct regulator *reg_id;
const char *name;
u32 voltage;
} wm8903_vdds[] = {
{ NULL, "8058_l16", 1800000 },
{ NULL, "8058_l0", 1200000 },
{ NULL, "8058_s3", 1800000 },
};
static void classd_amp_pwr(int enable)
{
int rc;
pr_debug("%s, enable = %d\n", __func__, enable);
if (enable) {
/* currently external PA isn't used for LINEOUTL */
rc = gpio_request(MSM_GPIO_CLASS_D0_EN, "CLASSD0_EN");
if (rc) {
pr_err("%s: spkr PA gpio %d request failed\n",
__func__, MSM_GPIO_CLASS_D0_EN);
return;
}
gpio_direction_output(MSM_GPIO_CLASS_D0_EN, 1);
gpio_set_value_cansleep(MSM_GPIO_CLASS_D0_EN, 1);
rc = gpio_request(MSM_GPIO_CLASS_D1_EN, "CLASSD1_EN");
if (rc) {
pr_err("%s: spkr PA gpio %d request failed\n",
__func__, MSM_GPIO_CLASS_D1_EN);
return;
}
gpio_direction_output(MSM_GPIO_CLASS_D1_EN, 1);
gpio_set_value_cansleep(MSM_GPIO_CLASS_D1_EN, 1);
} else {
gpio_set_value_cansleep(MSM_GPIO_CLASS_D0_EN, 0);
gpio_free(MSM_GPIO_CLASS_D0_EN);
gpio_set_value_cansleep(MSM_GPIO_CLASS_D1_EN, 0);
gpio_free(MSM_GPIO_CLASS_D1_EN);
}
}
static void extern_poweramp_on(void)
{
pr_debug("%s: enable stereo spkr amp\n", __func__);
classd_amp_pwr(1);
}
static void extern_poweramp_off(void)
{
pr_debug("%s: disable stereo spkr amp\n", __func__);
classd_amp_pwr(0);
}
static int msm8660_wm8903_powerup(void)
{
int rc = 0, index, stage = NONE;
struct wm8903_vdd *vdd = NULL;
for (index = 0; index < ARRAY_SIZE(wm8903_vdds); index++) {
vdd = &wm8903_vdds[index];
vdd->reg_id = regulator_get(NULL, vdd->name);
if (IS_ERR(vdd->reg_id)) {
pr_err("%s: Unable to get %s\n", __func__, vdd->name);
stage = GET_ERR;
rc = -ENODEV;
break;
}
rc = regulator_set_voltage(vdd->reg_id,
vdd->voltage, vdd->voltage);
if (rc) {
pr_err("%s: unable to set %s voltage to %dV\n",
__func__, vdd->name, vdd->voltage);
stage = SET_ERR;
break;
}
rc = regulator_enable(vdd->reg_id);
if (rc) {
pr_err("%s:failed to enable %s\n", __func__, vdd->name);
stage = ENABLE_ERR;
break;
}
}
if (index != ARRAY_SIZE(wm8903_vdds)) {
if (stage != GET_ERR) {
vdd = &wm8903_vdds[index];
regulator_put(vdd->reg_id);
vdd->reg_id = NULL;
}
while (index--) {
vdd = &wm8903_vdds[index];
regulator_disable(vdd->reg_id);
regulator_put(vdd->reg_id);
vdd->reg_id = NULL;
}
}
return rc;
}
static void msm8660_wm8903_powerdown(void)
{
int index = ARRAY_SIZE(wm8903_vdds);
struct wm8903_vdd *vdd = NULL;
while (index--) {
vdd = &wm8903_vdds[index];
if (vdd->reg_id) {
regulator_disable(vdd->reg_id);
regulator_put(vdd->reg_id);
}
}
}
static int msm8660_wm8903_enable_mclk(int enable)
{
int ret = 0;
if (enable) {
ret = gpio_request(MSM_CDC_MIC_I2S_MCLK, "I2S_Clock");
if (ret != 0) {
pr_err("%s: failed to request GPIO\n", __func__);
return ret;
}
wm8903_mclk = clk_get_sys(NULL, "i2s_mic_osr_clk");
if (IS_ERR(wm8903_mclk)) {
pr_err("Failed to get i2s_mic_osr_clk\n");
gpio_free(MSM_CDC_MIC_I2S_MCLK);
return IS_ERR(wm8903_mclk);
}
/* Master clock OSR 256 */
clk_set_rate(wm8903_mclk, 48000 * 256);
ret = clk_prepare_enable(wm8903_mclk);
if (ret != 0) {
pr_err("Unable to enable i2s_mic_osr_clk\n");
gpio_free(MSM_CDC_MIC_I2S_MCLK);
clk_put(wm8903_mclk);
return ret;
}
} else {
if (wm8903_mclk) {
clk_disable_unprepare(wm8903_mclk);
clk_put(wm8903_mclk);
gpio_free(MSM_CDC_MIC_I2S_MCLK);
wm8903_mclk = NULL;
}
}
return ret;
}
static int msm8660_wm8903_prepare(void)
{
int ret = 0;
ret = msm8660_wm8903_powerup();
if (ret) {
pr_err("Unable to powerup wm8903\n");
return ret;
}
ret = msm8660_wm8903_enable_mclk(1);
if (ret) {
pr_err("Unable to enable mclk to wm8903\n");
return ret;
}
return ret;
}
static void msm8660_wm8903_unprepare(void)
{
msm8660_wm8903_powerdown();
msm8660_wm8903_enable_mclk(0);
}
static int msm8660_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int rate = params_rate(params), ret = 0;
pr_debug("Enter %s rate = %d\n", __func__, rate);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (rx_hw_param_status)
return 0;
/* wm8903 run @ LRC*256 */
ret = snd_soc_dai_set_sysclk(codec_dai, 0, rate * 256,
SND_SOC_CLOCK_IN);
snd_soc_dai_digital_mute(codec_dai, 0);
if (ret < 0) {
pr_err("can't set rx codec clk configuration\n");
return ret;
}
clk_set_rate(wm8903_mclk, rate * 256);
/* set as slave mode CPU */
clk_set_rate(spkr_bit_clk, 0);
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM);
rx_hw_param_status++;
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
if (tx_hw_param_status)
return 0;
clk_set_rate(wm8903_mclk, rate * 256);
ret = snd_soc_dai_set_sysclk(codec_dai, 0, rate * 256,
SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("can't set tx codec clk configuration\n");
return ret;
}
clk_set_rate(mic_bit_clk, 0);
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM);
tx_hw_param_status++;
}
return 0;
}
static int msm8660_i2s_startup(struct snd_pcm_substream *substream)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
pr_debug("Enter %s\n", __func__);
/* ON Dragonboard, I2S between wm8903 and CPU is shared by
* CODEC_SPEAKER and CODEC_MIC therefore CPU only can operate
* as input SLAVE mode.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* config WM8903 in Mater mode */
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_CBM_CFM |
SND_SOC_DAIFMT_I2S);
if (ret != 0) {
pr_err("codec_dai set_fmt error\n");
return ret;
}
/* config CPU in SLAVE mode */
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM);
if (ret != 0) {
pr_err("cpu_dai set_fmt error\n");
return ret;
}
spkr_osr_clk = clk_get_sys(NULL, "i2s_spkr_osr_clk");
if (IS_ERR(spkr_osr_clk)) {
pr_err("Failed to get i2s_spkr_osr_clk\n");
return PTR_ERR(spkr_osr_clk);
}
clk_set_rate(spkr_osr_clk, 48000 * 256);
ret = clk_prepare_enable(spkr_osr_clk);
if (ret != 0) {
pr_err("Unable to enable i2s_spkr_osr_clk\n");
clk_put(spkr_osr_clk);
return ret;
}
spkr_bit_clk = clk_get_sys(NULL, "i2s_spkr_bit_clk");
if (IS_ERR(spkr_bit_clk)) {
pr_err("Failed to get i2s_spkr_bit_clk\n");
clk_disable_unprepare(spkr_osr_clk);
clk_put(spkr_osr_clk);
return PTR_ERR(spkr_bit_clk);
}
clk_set_rate(spkr_bit_clk, 0);
ret = clk_prepare_enable(spkr_bit_clk);
if (ret != 0) {
pr_err("Unable to enable i2s_spkr_bit_clk\n");
clk_disable_unprepare(spkr_osr_clk);
clk_put(spkr_osr_clk);
clk_put(spkr_bit_clk);
return ret;
}
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
/* config WM8903 in Mater mode */
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_CBM_CFM |
SND_SOC_DAIFMT_I2S);
if (ret != 0) {
pr_err("codec_dai set_fmt error\n");
return ret;
}
/* config CPU in SLAVE mode */
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM);
if (ret != 0) {
pr_err("codec_dai set_fmt error\n");
return ret;
}
mic_bit_clk = clk_get_sys(NULL, "i2s_mic_bit_clk");
if (IS_ERR(mic_bit_clk)) {
pr_err("Failed to get i2s_mic_bit_clk\n");
return PTR_ERR(mic_bit_clk);
}
clk_set_rate(mic_bit_clk, 0);
ret = clk_prepare_enable(mic_bit_clk);
if (ret != 0) {
pr_err("Unable to enable i2s_mic_bit_clk\n");
clk_put(mic_bit_clk);
return ret;
}
}
return ret;
}
static void msm8660_i2s_shutdown(struct snd_pcm_substream *substream)
{
pr_debug("Enter %s\n", __func__);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
tx_hw_param_status = 0;
rx_hw_param_status = 0;
if (spkr_bit_clk) {
clk_disable_unprepare(spkr_bit_clk);
clk_put(spkr_bit_clk);
spkr_bit_clk = NULL;
}
if (spkr_osr_clk) {
clk_disable_unprepare(spkr_osr_clk);
clk_put(spkr_osr_clk);
spkr_osr_clk = NULL;
}
if (mic_bit_clk) {
clk_disable_unprepare(mic_bit_clk);
clk_put(mic_bit_clk);
mic_bit_clk = NULL;
}
}
}
static void msm8660_ext_control(struct snd_soc_codec *codec)
{
/* set the enpoints to their new connetion states */
if (msm8660_spk_func == FUNC_ON)
snd_soc_dapm_enable_pin(&codec->dapm, "Ext Spk");
else
snd_soc_dapm_disable_pin(&codec->dapm, "Ext Spk");
/* set the enpoints to their new connetion states */
if (msm8660_headset_func == FUNC_ON)
snd_soc_dapm_enable_pin(&codec->dapm, "Headset Jack");
else
snd_soc_dapm_disable_pin(&codec->dapm, "Headset Jack");
/* set the enpoints to their new connetion states */
if (msm8660_headphone_func == FUNC_ON)
snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
else
snd_soc_dapm_disable_pin(&codec->dapm, "Headphone Jack");
/* signal a DAPM event */
snd_soc_dapm_sync(&codec->dapm);
}
static int msm8660_get_spk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = msm8660_spk_func;
return 0;
}
static int msm8660_set_spk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
pr_debug("%s()\n", __func__);
if (msm8660_spk_func == ucontrol->value.integer.value[0])
return 0;
msm8660_spk_func = ucontrol->value.integer.value[0];
msm8660_ext_control(codec);
return 1;
}
static int msm8660_get_hs(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = msm8660_headset_func;
return 0;
}
static int msm8660_set_hs(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
pr_debug("%s()\n", __func__);
if (msm8660_headset_func == ucontrol->value.integer.value[0])
return 0;
msm8660_headset_func = ucontrol->value.integer.value[0];
msm8660_ext_control(codec);
return 1;
}
static int msm8660_get_hph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = msm8660_headphone_func;
return 0;
}
static int msm8660_set_hph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
pr_debug("%s()\n", __func__);
if (msm8660_headphone_func == ucontrol->value.integer.value[0])
return 0;
msm8660_headphone_func = ucontrol->value.integer.value[0];
msm8660_ext_control(codec);
return 1;
}
static int msm8660_spkramp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
if (SND_SOC_DAPM_EVENT_ON(event))
extern_poweramp_on();
else
extern_poweramp_off();
return 0;
}
static struct snd_soc_ops machine_ops = {
.startup = msm8660_i2s_startup,
.shutdown = msm8660_i2s_shutdown,
.hw_params = msm8660_i2s_hw_params,
};
static const struct snd_soc_dapm_widget msm8660_dapm_widgets[] = {
SND_SOC_DAPM_SPK("Ext Spk", msm8660_spkramp_event),
SND_SOC_DAPM_MIC("Headset Jack", NULL),
SND_SOC_DAPM_MIC("Headphone Jack", NULL),
/* to fix a bug in wm8903.c, where audio doesn't function
* after suspend/resume
*/
SND_SOC_DAPM_SUPPLY("CLK_SYS_ENA", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* Match with wm8903 codec line out pin */
{"Ext Spk", NULL, "LINEOUTL"},
{"Ext Spk", NULL, "LINEOUTR"},
/* Headset connects to IN3L with Bias */
{"IN3L", NULL, "Mic Bias"},
{"Mic Bias", NULL, "Headset Jack"},
/* Headphone connects to IN3R with Bias */
{"IN3R", NULL, "Mic Bias"},
{"Mic Bias", NULL, "Headphone Jack"},
{"ADCL", NULL, "CLK_SYS_ENA"},
{"ADCR", NULL, "CLK_SYS_ENA"},
{"DACL", NULL, "CLK_SYS_ENA"},
{"DACR", NULL, "CLK_SYS_ENA"},
};
static const char *cmn_status[] = {"Off", "On"};
static const struct soc_enum msm8660_enum[] = {
SOC_ENUM_SINGLE_EXT(2, cmn_status),
};
static const struct snd_kcontrol_new wm8903_msm8660_controls[] = {
SOC_ENUM_EXT("Speaker Function", msm8660_enum[0], msm8660_get_spk,
msm8660_set_spk),
SOC_ENUM_EXT("Headset Function", msm8660_enum[0], msm8660_get_hs,
msm8660_set_hs),
SOC_ENUM_EXT("Headphone Function", msm8660_enum[0], msm8660_get_hph,
msm8660_set_hph),
};
static int msm8660_audrx_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_codec *codec = rtd->codec;
int err;
snd_soc_dapm_disable_pin(&codec->dapm, "Ext Spk");
snd_soc_dapm_enable_pin(&codec->dapm, "CLK_SYS_ENA");
err = snd_soc_add_controls(codec, wm8903_msm8660_controls,
ARRAY_SIZE(wm8903_msm8660_controls));
if (err < 0)
return err;
snd_soc_dapm_new_controls(&codec->dapm, msm8660_dapm_widgets,
ARRAY_SIZE(msm8660_dapm_widgets));
snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_sync(&codec->dapm);
return 0;
}
static int pri_i2s_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
rate->min = rate->max = 48000;
return 0;
}
/*
* LPA Needs only RX BE DAI links.
* Hence define seperate BE list for lpa
*/
static const char *lpa_mm_be[] = {
LPASS_BE_PRI_I2S_RX,
};
static struct snd_soc_dsp_link lpa_fe_media = {
.supported_be = lpa_mm_be,
.num_be = ARRAY_SIZE(lpa_mm_be),
.fe_playback_channels = 2,
.fe_capture_channels = 1,
.trigger = {
SND_SOC_DSP_TRIGGER_POST,
SND_SOC_DSP_TRIGGER_POST
},
};
static const char *mm1_be[] = {
LPASS_BE_PRI_I2S_RX,
LPASS_BE_PRI_I2S_TX,
LPASS_BE_HDMI,
};
static struct snd_soc_dsp_link fe_media = {
.supported_be = mm1_be,
.num_be = ARRAY_SIZE(mm1_be),
.fe_playback_channels = 2,
.fe_capture_channels = 1,
.trigger = {
SND_SOC_DSP_TRIGGER_POST, SND_SOC_DSP_TRIGGER_POST},
};
/* Digital audio interface glue - connects codec <---> CPU */
static struct snd_soc_dai_link msm8660_dai[] = {
/* FrontEnd DAI Links */
{
.name = "MSM8660 Media",
.stream_name = "MultiMedia",
.cpu_dai_name = "MultiMedia1",
.platform_name = "msm-pcm-dsp",
.dynamic = 1,
.dsp_link = &fe_media,
.be_id = MSM_FRONTEND_DAI_MULTIMEDIA1
},
{
.name = "MSM8660 Media2",
.stream_name = "MultiMedia2",
.cpu_dai_name = "MultiMedia2",
.platform_name = "msm-pcm-dsp",
.dynamic = 1,
.dsp_link = &fe_media,
.be_id = MSM_FRONTEND_DAI_MULTIMEDIA2,
},
/* Backend DAI Links */
{
.name = LPASS_BE_PRI_I2S_RX,
.stream_name = "Primary I2S Playback",
.cpu_dai_name = "msm-dai-q6.0",
.platform_name = "msm-pcm-routing",
.codec_name = "wm8903-codec.3-001a",
.codec_dai_name = "wm8903-hifi",
.no_pcm = 1,
.be_hw_params_fixup = pri_i2s_be_hw_params_fixup,
.ops = &machine_ops,
.init = &msm8660_audrx_init,
.be_id = MSM_BACKEND_DAI_PRI_I2S_RX
},
{
.name = LPASS_BE_PRI_I2S_TX,
.stream_name = "Primary I2S Capture",
.cpu_dai_name = "msm-dai-q6.1",
.platform_name = "msm-pcm-routing",
.codec_name = "wm8903-codec.3-001a",
.codec_dai_name = "wm8903-hifi",
.no_pcm = 1,
.ops = &machine_ops,
.be_hw_params_fixup = pri_i2s_be_hw_params_fixup,
.be_id = MSM_BACKEND_DAI_PRI_I2S_TX
},
/* LPA frontend DAI link*/
{
.name = "MSM8660 LPA",
.stream_name = "LPA",
.cpu_dai_name = "MultiMedia3",
.platform_name = "msm-pcm-lpa",
.dynamic = 1,
.dsp_link = &lpa_fe_media,
.be_id = MSM_FRONTEND_DAI_MULTIMEDIA3,
},
/* HDMI backend DAI link */
{
.name = LPASS_BE_HDMI,
.stream_name = "HDMI Playback",
.cpu_dai_name = "msm-dai-q6.8",
.platform_name = "msm-pcm-routing",
.codec_name = "msm-stub-codec.1",
.codec_dai_name = "msm-stub-rx",
.no_codec = 1,
.no_pcm = 1,
.be_hw_params_fixup = pri_i2s_be_hw_params_fixup,
.be_id = MSM_BACKEND_DAI_HDMI_RX
},
};
struct snd_soc_card snd_soc_card_msm8660 = {
.name = "msm8660-snd-card",
.dai_link = msm8660_dai,
.num_links = ARRAY_SIZE(msm8660_dai),
};
static struct platform_device *msm_snd_device;
static int __init msm_audio_init(void)
{
int ret = 0;
if (machine_is_msm8x60_dragon()) {
/* wm8903 audio codec needs to power up and mclk existing
before it's probed */
ret = msm8660_wm8903_prepare();
if (ret) {
pr_err("failed to prepare wm8903 audio codec\n");
return ret;
}
msm_snd_device = platform_device_alloc("soc-audio", 0);
if (!msm_snd_device) {
pr_err("Platform device allocation failed\n");
msm8660_wm8903_unprepare();
return -ENOMEM;
}
platform_set_drvdata(msm_snd_device, &snd_soc_card_msm8660);
ret = platform_device_add(msm_snd_device);
if (ret) {
platform_device_put(msm_snd_device);
msm8660_wm8903_unprepare();
return ret;
}
}
return ret;
}
module_init(msm_audio_init);
static void __exit msm_audio_exit(void)
{
msm8660_wm8903_unprepare();
platform_device_unregister(msm_snd_device);
}
module_exit(msm_audio_exit);
MODULE_DESCRIPTION("ALSA SoC MSM8660");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
free-z4u/android_kernel_htc_msm7x30 | drivers/net/sfc/mcdi.c | 687 | 31691 | /****************************************************************************
* Driver for Solarflare Solarstorm network controllers and boards
* Copyright 2008-2011 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation, incorporated herein by reference.
*/
#include <linux/delay.h>
#include "net_driver.h"
#include "nic.h"
#include "io.h"
#include "regs.h"
#include "mcdi_pcol.h"
#include "phy.h"
/**************************************************************************
*
* Management-Controller-to-Driver Interface
*
**************************************************************************
*/
/* Software-defined structure to the shared-memory */
#define CMD_NOTIFY_PORT0 0
#define CMD_NOTIFY_PORT1 4
#define CMD_PDU_PORT0 0x008
#define CMD_PDU_PORT1 0x108
#define REBOOT_FLAG_PORT0 0x3f8
#define REBOOT_FLAG_PORT1 0x3fc
#define MCDI_RPC_TIMEOUT (10 * HZ)
#define MCDI_PDU(efx) \
(efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
#define MCDI_DOORBELL(efx) \
(efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
#define MCDI_REBOOT_FLAG(efx) \
(efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
#define SEQ_MASK \
EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
{
struct siena_nic_data *nic_data;
EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
nic_data = efx->nic_data;
return &nic_data->mcdi;
}
void efx_mcdi_init(struct efx_nic *efx)
{
struct efx_mcdi_iface *mcdi;
if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
return;
mcdi = efx_mcdi(efx);
init_waitqueue_head(&mcdi->wq);
spin_lock_init(&mcdi->iface_lock);
atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
mcdi->mode = MCDI_MODE_POLL;
(void) efx_mcdi_poll_reboot(efx);
}
static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
const u8 *inbuf, size_t inlen)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
unsigned int i;
efx_dword_t hdr;
u32 xflags, seqno;
BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
BUG_ON(inlen & 3 || inlen >= 0x100);
seqno = mcdi->seqno & SEQ_MASK;
xflags = 0;
if (mcdi->mode == MCDI_MODE_EVENTS)
xflags |= MCDI_HEADER_XFLAGS_EVREQ;
EFX_POPULATE_DWORD_6(hdr,
MCDI_HEADER_RESPONSE, 0,
MCDI_HEADER_RESYNC, 1,
MCDI_HEADER_CODE, cmd,
MCDI_HEADER_DATALEN, inlen,
MCDI_HEADER_SEQ, seqno,
MCDI_HEADER_XFLAGS, xflags);
efx_writed(efx, &hdr, pdu);
for (i = 0; i < inlen; i += 4)
_efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
/* Ensure the payload is written out before the header */
wmb();
/* ring the doorbell with a distinctive value */
_efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
}
static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
int i;
BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
BUG_ON(outlen & 3 || outlen >= 0x100);
for (i = 0; i < outlen; i += 4)
*((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
}
static int efx_mcdi_poll(struct efx_nic *efx)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
unsigned long time, finish;
unsigned int respseq, respcmd, error;
unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
unsigned int rc, spins;
efx_dword_t reg;
/* Check for a reboot atomically with respect to efx_mcdi_copyout() */
rc = -efx_mcdi_poll_reboot(efx);
if (rc)
goto out;
/* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
* because generally mcdi responses are fast. After that, back off
* and poll once a jiffy (approximately)
*/
spins = TICK_USEC;
finish = jiffies + MCDI_RPC_TIMEOUT;
while (1) {
if (spins != 0) {
--spins;
udelay(1);
} else {
schedule_timeout_uninterruptible(1);
}
time = jiffies;
rmb();
efx_readd(efx, ®, pdu);
/* All 1's indicates that shared memory is in reset (and is
* not a valid header). Wait for it to come out reset before
* completing the command */
if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
break;
if (time_after(time, finish))
return -ETIMEDOUT;
}
mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
if (error && mcdi->resplen == 0) {
netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
rc = EIO;
} else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
netif_err(efx, hw, efx->net_dev,
"MC response mismatch tx seq 0x%x rx seq 0x%x\n",
respseq, mcdi->seqno);
rc = EIO;
} else if (error) {
efx_readd(efx, ®, pdu + 4);
switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
#define TRANSLATE_ERROR(name) \
case MC_CMD_ERR_ ## name: \
rc = name; \
break
TRANSLATE_ERROR(ENOENT);
TRANSLATE_ERROR(EINTR);
TRANSLATE_ERROR(EACCES);
TRANSLATE_ERROR(EBUSY);
TRANSLATE_ERROR(EINVAL);
TRANSLATE_ERROR(EDEADLK);
TRANSLATE_ERROR(ENOSYS);
TRANSLATE_ERROR(ETIME);
#undef TRANSLATE_ERROR
default:
rc = EIO;
break;
}
} else
rc = 0;
out:
mcdi->resprc = rc;
if (rc)
mcdi->resplen = 0;
/* Return rc=0 like wait_event_timeout() */
return 0;
}
/* Test and clear MC-rebooted flag for this port/function */
int efx_mcdi_poll_reboot(struct efx_nic *efx)
{
unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
efx_dword_t reg;
uint32_t value;
if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
return false;
efx_readd(efx, ®, addr);
value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
if (value == 0)
return 0;
EFX_ZERO_DWORD(reg);
efx_writed(efx, ®, addr);
if (value == MC_STATUS_DWORD_ASSERT)
return -EINTR;
else
return -EIO;
}
static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
{
/* Wait until the interface becomes QUIESCENT and we win the race
* to mark it RUNNING. */
wait_event(mcdi->wq,
atomic_cmpxchg(&mcdi->state,
MCDI_STATE_QUIESCENT,
MCDI_STATE_RUNNING)
== MCDI_STATE_QUIESCENT);
}
static int efx_mcdi_await_completion(struct efx_nic *efx)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
if (wait_event_timeout(
mcdi->wq,
atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
MCDI_RPC_TIMEOUT) == 0)
return -ETIMEDOUT;
/* Check if efx_mcdi_set_mode() switched us back to polled completions.
* In which case, poll for completions directly. If efx_mcdi_ev_cpl()
* completed the request first, then we'll just end up completing the
* request again, which is safe.
*
* We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
* wait_event_timeout() implicitly provides.
*/
if (mcdi->mode == MCDI_MODE_POLL)
return efx_mcdi_poll(efx);
return 0;
}
static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
{
/* If the interface is RUNNING, then move to COMPLETED and wake any
* waiters. If the interface isn't in RUNNING then we've received a
* duplicate completion after we've already transitioned back to
* QUIESCENT. [A subsequent invocation would increment seqno, so would
* have failed the seqno check].
*/
if (atomic_cmpxchg(&mcdi->state,
MCDI_STATE_RUNNING,
MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
wake_up(&mcdi->wq);
return true;
}
return false;
}
static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
{
atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
wake_up(&mcdi->wq);
}
static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
unsigned int datalen, unsigned int errno)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
bool wake = false;
spin_lock(&mcdi->iface_lock);
if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
if (mcdi->credits)
/* The request has been cancelled */
--mcdi->credits;
else
netif_err(efx, hw, efx->net_dev,
"MC response mismatch tx seq 0x%x rx "
"seq 0x%x\n", seqno, mcdi->seqno);
} else {
mcdi->resprc = errno;
mcdi->resplen = datalen;
wake = true;
}
spin_unlock(&mcdi->iface_lock);
if (wake)
efx_mcdi_complete(mcdi);
}
/* Issue the given command by writing the data into the shared memory PDU,
* ring the doorbell and wait for completion. Copyout the result. */
int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
size_t *outlen_actual)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
int rc;
BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
efx_mcdi_acquire(mcdi);
/* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
spin_lock_bh(&mcdi->iface_lock);
++mcdi->seqno;
spin_unlock_bh(&mcdi->iface_lock);
efx_mcdi_copyin(efx, cmd, inbuf, inlen);
if (mcdi->mode == MCDI_MODE_POLL)
rc = efx_mcdi_poll(efx);
else
rc = efx_mcdi_await_completion(efx);
if (rc != 0) {
/* Close the race with efx_mcdi_ev_cpl() executing just too late
* and completing a request we've just cancelled, by ensuring
* that the seqno check therein fails.
*/
spin_lock_bh(&mcdi->iface_lock);
++mcdi->seqno;
++mcdi->credits;
spin_unlock_bh(&mcdi->iface_lock);
netif_err(efx, hw, efx->net_dev,
"MC command 0x%x inlen %d mode %d timed out\n",
cmd, (int)inlen, mcdi->mode);
} else {
size_t resplen;
/* At the very least we need a memory barrier here to ensure
* we pick up changes from efx_mcdi_ev_cpl(). Protect against
* a spurious efx_mcdi_ev_cpl() running concurrently by
* acquiring the iface_lock. */
spin_lock_bh(&mcdi->iface_lock);
rc = -mcdi->resprc;
resplen = mcdi->resplen;
spin_unlock_bh(&mcdi->iface_lock);
if (rc == 0) {
efx_mcdi_copyout(efx, outbuf,
min(outlen, mcdi->resplen + 3) & ~0x3);
if (outlen_actual != NULL)
*outlen_actual = resplen;
} else if (cmd == MC_CMD_REBOOT && rc == -EIO)
; /* Don't reset if MC_CMD_REBOOT returns EIO */
else if (rc == -EIO || rc == -EINTR) {
netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
-rc);
efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
} else
netif_dbg(efx, hw, efx->net_dev,
"MC command 0x%x inlen %d failed rc=%d\n",
cmd, (int)inlen, -rc);
}
efx_mcdi_release(mcdi);
return rc;
}
void efx_mcdi_mode_poll(struct efx_nic *efx)
{
struct efx_mcdi_iface *mcdi;
if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
return;
mcdi = efx_mcdi(efx);
if (mcdi->mode == MCDI_MODE_POLL)
return;
/* We can switch from event completion to polled completion, because
* mcdi requests are always completed in shared memory. We do this by
* switching the mode to POLL'd then completing the request.
* efx_mcdi_await_completion() will then call efx_mcdi_poll().
*
* We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
* which efx_mcdi_complete() provides for us.
*/
mcdi->mode = MCDI_MODE_POLL;
efx_mcdi_complete(mcdi);
}
void efx_mcdi_mode_event(struct efx_nic *efx)
{
struct efx_mcdi_iface *mcdi;
if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
return;
mcdi = efx_mcdi(efx);
if (mcdi->mode == MCDI_MODE_EVENTS)
return;
/* We can't switch from polled to event completion in the middle of a
* request, because the completion method is specified in the request.
* So acquire the interface to serialise the requestors. We don't need
* to acquire the iface_lock to change the mode here, but we do need a
* write memory barrier ensure that efx_mcdi_rpc() sees it, which
* efx_mcdi_acquire() provides.
*/
efx_mcdi_acquire(mcdi);
mcdi->mode = MCDI_MODE_EVENTS;
efx_mcdi_release(mcdi);
}
static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
/* If there is an outstanding MCDI request, it has been terminated
* either by a BADASSERT or REBOOT event. If the mcdi interface is
* in polled mode, then do nothing because the MC reboot handler will
* set the header correctly. However, if the mcdi interface is waiting
* for a CMDDONE event it won't receive it [and since all MCDI events
* are sent to the same queue, we can't be racing with
* efx_mcdi_ev_cpl()]
*
* There's a race here with efx_mcdi_rpc(), because we might receive
* a REBOOT event *before* the request has been copied out. In polled
* mode (during startup) this is irrelevant, because efx_mcdi_complete()
* is ignored. In event mode, this condition is just an edge-case of
* receiving a REBOOT event after posting the MCDI request. Did the mc
* reboot before or after the copyout? The best we can do always is
* just return failure.
*/
spin_lock(&mcdi->iface_lock);
if (efx_mcdi_complete(mcdi)) {
if (mcdi->mode == MCDI_MODE_EVENTS) {
mcdi->resprc = rc;
mcdi->resplen = 0;
++mcdi->credits;
}
} else
/* Nobody was waiting for an MCDI request, so trigger a reset */
efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
spin_unlock(&mcdi->iface_lock);
}
static unsigned int efx_mcdi_event_link_speed[] = {
[MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
[MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
[MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
};
static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
{
u32 flags, fcntl, speed, lpa;
speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
speed = efx_mcdi_event_link_speed[speed];
flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
/* efx->link_state is only modified by efx_mcdi_phy_get_link(),
* which is only run after flushing the event queues. Therefore, it
* is safe to modify the link state outside of the mac_lock here.
*/
efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
efx_mcdi_phy_check_fcntl(efx, lpa);
efx_link_status_changed(efx);
}
static const char *sensor_names[] = {
[MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
[MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
[MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
[MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
[MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
[MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
[MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
[MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
[MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
[MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
[MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
[MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
[MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
};
static const char *sensor_status_names[] = {
[MC_CMD_SENSOR_STATE_OK] = "OK",
[MC_CMD_SENSOR_STATE_WARNING] = "Warning",
[MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
[MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
};
static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
{
unsigned int monitor, state, value;
const char *name, *state_txt;
monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
/* Deal gracefully with the board having more drivers than we
* know about, but do not expect new sensor states. */
name = (monitor >= ARRAY_SIZE(sensor_names))
? "No sensor name available" :
sensor_names[monitor];
EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
state_txt = sensor_status_names[state];
netif_err(efx, hw, efx->net_dev,
"Sensor %d (%s) reports condition '%s' for raw value %d\n",
monitor, name, state_txt, value);
}
/* Called from falcon_process_eventq for MCDI events */
void efx_mcdi_process_event(struct efx_channel *channel,
efx_qword_t *event)
{
struct efx_nic *efx = channel->efx;
int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
switch (code) {
case MCDI_EVENT_CODE_BADSSERT:
netif_err(efx, hw, efx->net_dev,
"MC watchdog or assertion failure at 0x%x\n", data);
efx_mcdi_ev_death(efx, EINTR);
break;
case MCDI_EVENT_CODE_PMNOTICE:
netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
break;
case MCDI_EVENT_CODE_CMDDONE:
efx_mcdi_ev_cpl(efx,
MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
break;
case MCDI_EVENT_CODE_LINKCHANGE:
efx_mcdi_process_link_change(efx, event);
break;
case MCDI_EVENT_CODE_SENSOREVT:
efx_mcdi_sensor_event(efx, event);
break;
case MCDI_EVENT_CODE_SCHEDERR:
netif_info(efx, hw, efx->net_dev,
"MC Scheduler error address=0x%x\n", data);
break;
case MCDI_EVENT_CODE_REBOOT:
netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
efx_mcdi_ev_death(efx, EIO);
break;
case MCDI_EVENT_CODE_MAC_STATS_DMA:
/* MAC stats are gather lazily. We can ignore this. */
break;
default:
netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
code);
}
}
/**************************************************************************
*
* Specific request functions
*
**************************************************************************
*/
void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
{
u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
size_t outlength;
const __le16 *ver_words;
int rc;
BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
outbuf, sizeof(outbuf), &outlength);
if (rc)
goto fail;
if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
rc = -EIO;
goto fail;
}
ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
snprintf(buf, len, "%u.%u.%u.%u",
le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
return;
fail:
netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
buf[0] = 0;
}
int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
bool *was_attached)
{
u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
size_t outlen;
int rc;
MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
driver_operating ? 1 : 0);
MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
rc = -EIO;
goto fail;
}
if (was_attached != NULL)
*was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
return 0;
fail:
netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
u16 *fw_subtype_list)
{
uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
size_t outlen, offset, i;
int port_num = efx_port_num(efx);
int rc;
BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
rc = -EIO;
goto fail;
}
offset = (port_num)
? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
: MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
if (mac_address)
memcpy(mac_address, outbuf + offset, ETH_ALEN);
if (fw_subtype_list) {
offset = MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST;
for (i = 0;
i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN / 2;
i++) {
fw_subtype_list[i] =
le16_to_cpup((__le16 *)(outbuf + offset));
offset += 2;
}
}
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
__func__, rc, (int)outlen);
return rc;
}
int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
{
u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
u32 dest = 0;
int rc;
if (uart)
dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
if (evq)
dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
{
u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
size_t outlen;
int rc;
BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
rc = -EIO;
goto fail;
}
*nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
__func__, rc);
return rc;
}
int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
size_t *size_out, size_t *erase_size_out,
bool *protected_out)
{
u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
size_t outlen;
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
rc = -EIO;
goto fail;
}
*size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
*erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
*protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
(1 << MC_CMD_NVRAM_PROTECTED_LBN));
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
{
u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
loff_t offset, u8 *buffer, size_t length)
{
u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
size_t outlen;
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
loff_t offset, const u8 *buffer, size_t length)
{
u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
loff_t offset, size_t length)
{
u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
{
u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
{
u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
int rc;
MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), NULL);
if (rc)
return rc;
switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
case MC_CMD_NVRAM_TEST_PASS:
case MC_CMD_NVRAM_TEST_NOTSUPP:
return 0;
default:
return -EIO;
}
}
int efx_mcdi_nvram_test_all(struct efx_nic *efx)
{
u32 nvram_types;
unsigned int type;
int rc;
rc = efx_mcdi_nvram_types(efx, &nvram_types);
if (rc)
goto fail1;
type = 0;
while (nvram_types != 0) {
if (nvram_types & 1) {
rc = efx_mcdi_nvram_test(efx, type);
if (rc)
goto fail2;
}
type++;
nvram_types >>= 1;
}
return 0;
fail2:
netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
__func__, type);
fail1:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
static int efx_mcdi_read_assertion(struct efx_nic *efx)
{
u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
unsigned int flags, index, ofst;
const char *reason;
size_t outlen;
int retry;
int rc;
/* Attempt to read any stored assertion state before we reboot
* the mcfw out of the assertion handler. Retry twice, once
* because a boot-time assertion might cause this command to fail
* with EINTR. And once again because GET_ASSERTS can race with
* MC_CMD_REBOOT running on the other port. */
retry = 2;
do {
MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
outbuf, sizeof(outbuf), &outlen);
} while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
if (rc)
return rc;
if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
return -EIO;
/* Print out any recorded assertion state */
flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
return 0;
reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
? "system-level assertion"
: (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
? "thread-level assertion"
: (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
? "watchdog reset"
: "unknown assertion";
netif_err(efx, hw, efx->net_dev,
"MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
/* Print out the registers */
ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
for (index = 1; index < 32; index++) {
netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
MCDI_DWORD2(outbuf, ofst));
ofst += sizeof(efx_dword_t);
}
return 0;
}
static void efx_mcdi_exit_assertion(struct efx_nic *efx)
{
u8 inbuf[MC_CMD_REBOOT_IN_LEN];
/* Atomically reboot the mcfw out of the assertion handler */
BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
NULL, 0, NULL);
}
int efx_mcdi_handle_assertion(struct efx_nic *efx)
{
int rc;
rc = efx_mcdi_read_assertion(efx);
if (rc)
return rc;
efx_mcdi_exit_assertion(efx);
return 0;
}
void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
{
u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
int rc;
BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (rc)
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
__func__, rc);
}
int efx_mcdi_reset_port(struct efx_nic *efx)
{
int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
if (rc)
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
__func__, rc);
return rc;
}
int efx_mcdi_reset_mc(struct efx_nic *efx)
{
u8 inbuf[MC_CMD_REBOOT_IN_LEN];
int rc;
BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
NULL, 0, NULL);
/* White is black, and up is down */
if (rc == -EIO)
return 0;
if (rc == 0)
rc = -EIO;
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
const u8 *mac, int *id_out)
{
u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
size_t outlen;
int rc;
MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
MC_CMD_FILTER_MODE_SIMPLE);
memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
rc = -EIO;
goto fail;
}
*id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
return 0;
fail:
*id_out = -1;
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int
efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
{
return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
}
int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
{
u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
size_t outlen;
int rc;
rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto fail;
if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
rc = -EIO;
goto fail;
}
*id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
return 0;
fail:
*id_out = -1;
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
{
u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
int rc;
MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
{
int rc;
rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
if (rc)
goto fail;
return 0;
fail:
netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
return rc;
}
| gpl-2.0 |
michaelspacejames/android_kernel_cyanogen_msm8916 | arch/arm/mach-msm/dma.c | 943 | 24777 | /* linux/arch/arm/mach-msm/dma.c
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, 2012, 2013 The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/pm_runtime.h>
#include <mach/dma.h>
#define MODULE_NAME "msm_dmov"
#define MSM_DMOV_CHANNEL_COUNT 16
#define MSM_DMOV_CRCI_COUNT 16
enum {
CLK_DIS,
CLK_ENABLING,
CLK_EN,
CLK_TO_BE_DIS,
CLK_DISABLING
};
struct msm_dmov_ci_conf {
int start;
int end;
int burst;
};
struct msm_dmov_crci_conf {
int sd;
int blk_size;
};
struct msm_dmov_chan_conf {
int sd;
int block;
int priority;
};
struct msm_dmov_conf {
void *base;
struct msm_dmov_crci_conf *crci_conf;
struct msm_dmov_chan_conf *chan_conf;
int channel_active;
int sd;
size_t sd_size;
struct list_head staged_commands[MSM_DMOV_CHANNEL_COUNT];
struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT];
struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT];
struct mutex clock_lock;
spinlock_t lock;
unsigned int irq;
struct clk *clk;
struct clk *pclk;
struct clk *ebiclk;
unsigned int clk_ctl;
struct delayed_work work;
struct workqueue_struct *cmd_wq;
};
static void msm_dmov_clock_work(struct work_struct *);
#ifdef CONFIG_ARCH_MSM8X60
#define DMOV_CHANNEL_DEFAULT_CONF { .sd = 1, .block = 0, .priority = 0 }
#define DMOV_CHANNEL_MODEM_CONF { .sd = 3, .block = 0, .priority = 0 }
#define DMOV_CHANNEL_CONF(secd, blk, pri) \
{ .sd = secd, .block = blk, .priority = pri }
static struct msm_dmov_chan_conf adm0_chan_conf[] = {
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
};
static struct msm_dmov_chan_conf adm1_chan_conf[] = {
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_DEFAULT_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
DMOV_CHANNEL_MODEM_CONF,
};
#define DMOV_CRCI_DEFAULT_CONF { .sd = 1, .blk_size = 0 }
#define DMOV_CRCI_CONF(secd, blk) { .sd = secd, .blk_size = blk }
static struct msm_dmov_crci_conf adm0_crci_conf[] = {
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_CONF(1, 4),
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
};
static struct msm_dmov_crci_conf adm1_crci_conf[] = {
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_CONF(1, 1),
DMOV_CRCI_CONF(1, 1),
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_CONF(1, 1),
DMOV_CRCI_CONF(1, 1),
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_DEFAULT_CONF,
DMOV_CRCI_CONF(1, 1),
DMOV_CRCI_DEFAULT_CONF,
};
static struct msm_dmov_conf dmov_conf[] = {
{
.crci_conf = adm0_crci_conf,
.chan_conf = adm0_chan_conf,
.clock_lock = __MUTEX_INITIALIZER(dmov_conf[0].clock_lock),
.lock = __SPIN_LOCK_UNLOCKED(dmov_lock),
.clk_ctl = CLK_DIS,
.work = __DELAYED_WORK_INITIALIZER(dmov_conf[0].work,
msm_dmov_clock_work, 0),
}, {
.crci_conf = adm1_crci_conf,
.chan_conf = adm1_chan_conf,
.clock_lock = __MUTEX_INITIALIZER(dmov_conf[1].clock_lock),
.lock = __SPIN_LOCK_UNLOCKED(dmov_lock),
.clk_ctl = CLK_DIS,
.work = __DELAYED_WORK_INITIALIZER(dmov_conf[1].work,
msm_dmov_clock_work, 0),
}
};
#else
static struct msm_dmov_conf dmov_conf[] = {
{
.crci_conf = NULL,
.chan_conf = NULL,
.clock_lock = __MUTEX_INITIALIZER(dmov_conf[0].clock_lock),
.lock = __SPIN_LOCK_UNLOCKED(dmov_lock),
.clk_ctl = CLK_DIS,
.work = __DELAYED_WORK_INITIALIZER(dmov_conf[0].work,
msm_dmov_clock_work, 0),
}
};
#endif
#define MSM_DMOV_ID_COUNT (MSM_DMOV_CHANNEL_COUNT * ARRAY_SIZE(dmov_conf))
#define DMOV_REG(name, adm) ((name) + (dmov_conf[adm].base) +\
(dmov_conf[adm].sd * dmov_conf[adm].sd_size))
#define DMOV_ID_TO_ADM(id) ((id) / MSM_DMOV_CHANNEL_COUNT)
#define DMOV_ID_TO_CHAN(id) ((id) % MSM_DMOV_CHANNEL_COUNT)
#define DMOV_CHAN_ADM_TO_ID(ch, adm) ((ch) + (adm) * MSM_DMOV_CHANNEL_COUNT)
#ifdef CONFIG_MSM_ADM3
#define DMOV_IRQ_TO_ADM(irq) \
({ \
typeof(irq) _irq = irq; \
((_irq == INT_ADM1_MASTER) || (_irq == INT_ADM1_AARM)); \
})
#else
#define DMOV_IRQ_TO_ADM(irq) 0
#endif
enum {
MSM_DMOV_PRINT_ERRORS = 1,
MSM_DMOV_PRINT_IO = 2,
MSM_DMOV_PRINT_FLOW = 4
};
unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS;
#define MSM_DMOV_DPRINTF(mask, format, args...) \
do { \
if ((mask) & msm_dmov_print_mask) \
printk(KERN_ERR format, args); \
} while (0)
#define PRINT_ERROR(format, args...) \
MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_ERRORS, format, args);
#define PRINT_IO(format, args...) \
MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_IO, format, args);
#define PRINT_FLOW(format, args...) \
MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_FLOW, format, args);
static int msm_dmov_clk_on(int adm)
{
int ret;
ret = clk_prepare_enable(dmov_conf[adm].clk);
if (ret)
return ret;
if (dmov_conf[adm].pclk) {
ret = clk_prepare_enable(dmov_conf[adm].pclk);
if (ret) {
clk_disable_unprepare(dmov_conf[adm].clk);
return ret;
}
}
if (dmov_conf[adm].ebiclk) {
ret = clk_prepare_enable(dmov_conf[adm].ebiclk);
if (ret) {
if (dmov_conf[adm].pclk)
clk_disable_unprepare(dmov_conf[adm].pclk);
clk_disable_unprepare(dmov_conf[adm].clk);
}
}
return ret;
}
static void msm_dmov_clk_off(int adm)
{
if (dmov_conf[adm].ebiclk)
clk_disable_unprepare(dmov_conf[adm].ebiclk);
if (dmov_conf[adm].pclk)
clk_disable_unprepare(dmov_conf[adm].pclk);
clk_disable_unprepare(dmov_conf[adm].clk);
}
static void msm_dmov_clock_work(struct work_struct *work)
{
struct msm_dmov_conf *conf =
container_of(to_delayed_work(work), struct msm_dmov_conf, work);
int adm = DMOV_IRQ_TO_ADM(conf->irq);
unsigned long irq_flags;
mutex_lock(&conf->clock_lock);
spin_lock_irqsave(&conf->lock, irq_flags);
if (conf->clk_ctl == CLK_TO_BE_DIS) {
BUG_ON(conf->channel_active);
conf->clk_ctl = CLK_DISABLING;
spin_unlock_irqrestore(&conf->lock, irq_flags);
msm_dmov_clk_off(adm);
spin_lock_irqsave(&conf->lock, irq_flags);
if (conf->clk_ctl == CLK_DISABLING)
conf->clk_ctl = CLK_DIS;
}
spin_unlock_irqrestore(&conf->lock, irq_flags);
mutex_unlock(&conf->clock_lock);
}
enum {
NOFLUSH = 0,
GRACEFUL,
NONGRACEFUL,
};
/* Caller must hold the list lock */
static struct msm_dmov_cmd *start_ready_cmd(unsigned ch, int adm)
{
struct msm_dmov_cmd *cmd;
if (list_empty(&dmov_conf[adm].ready_commands[ch]))
return NULL;
cmd = list_entry(dmov_conf[adm].ready_commands[ch].next, typeof(*cmd),
list);
list_del(&cmd->list);
if (cmd->exec_func)
cmd->exec_func(cmd);
list_add_tail(&cmd->list, &dmov_conf[adm].active_commands[ch]);
if (!dmov_conf[adm].channel_active)
enable_irq(dmov_conf[adm].irq);
dmov_conf[adm].channel_active |= BIT(ch);
PRINT_IO("start_ready_cmd, %x, ch %d\n", cmd->cmdptr, ch);
writel_relaxed(cmd->cmdptr, DMOV_REG(DMOV_CMD_PTR(ch), adm));
return cmd;
}
static void msm_dmov_enqueue_cmd_ext_work(struct work_struct *work)
{
struct msm_dmov_cmd *cmd =
container_of(work, struct msm_dmov_cmd, work);
unsigned id = cmd->id;
unsigned status;
unsigned long flags;
int adm = DMOV_ID_TO_ADM(id);
int ch = 0;
mutex_lock(&dmov_conf[adm].clock_lock);
/*No spin_lock is required for the condition check below*/
BUG_ON(dmov_conf[adm].clk_ctl != CLK_ENABLING);
status = msm_dmov_clk_on(adm);
if (status != 0) {
PRINT_ERROR("ADM: Unexpected clock failure at dma.c:%d/%s()!\n",
__LINE__, __func__);
goto error;
}
spin_lock_irqsave(&dmov_conf[adm].lock, flags);
dmov_conf[adm].clk_ctl = CLK_EN;
for (ch = 0; ch < MSM_DMOV_CHANNEL_COUNT; ch++) {
while (!list_empty(&dmov_conf[adm].staged_commands[ch])) {
cmd = list_entry(dmov_conf[adm].staged_commands[ch].
next, typeof(*cmd), list);
list_del(&cmd->list);
list_add_tail(&cmd->list, &dmov_conf[adm].
ready_commands[ch]);
}
if (!list_empty(&dmov_conf[adm].ready_commands[ch])) {
status = readl_relaxed(DMOV_REG(DMOV_STATUS(ch), adm));
if (status & DMOV_STATUS_CMD_PTR_RDY) {
PRINT_IO("msm_dmov_enqueue_cmd(%d),"\
" start command, status %x\n",
id, status);
cmd = start_ready_cmd(ch, adm);
/*
* We added something to the ready list,
* and still hold the list lock.
* Thus, no need to check for cmd == NULL
*/
if (cmd->toflush) {
int flush = (cmd->toflush == GRACEFUL) ?
1 << 31 : 0;
writel_relaxed(flush,
DMOV_REG(DMOV_FLUSH0(ch), adm));
}
} else {
if (list_empty(&dmov_conf[adm].
active_commands[ch]))
PRINT_ERROR("msm_dmov_enqueue_cmd_ext"\
"(%d), stalled, status %x\n",
id, status);
PRINT_IO("msm_dmov_enqueue_cmd(%d),"\
"enqueue command, status "
"%x\n", id, status);
}
}
}
spin_unlock_irqrestore(&dmov_conf[adm].lock, flags);
error:
mutex_unlock(&dmov_conf[adm].clock_lock);
}
void msm_dmov_enqueue_cmd_ext_atomic(unsigned id, struct msm_dmov_cmd *cmd)
{
unsigned int status;
int adm = DMOV_ID_TO_ADM(id);
int ch = DMOV_ID_TO_CHAN(id);
status = readl_relaxed(DMOV_REG(DMOV_STATUS(ch), adm));
if (status & DMOV_STATUS_CMD_PTR_RDY) {
PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n",
id, status);
if (cmd->exec_func)
cmd->exec_func(cmd);
list_add_tail(&cmd->list, &dmov_conf[adm].active_commands[ch]);
if (!dmov_conf[adm].channel_active)
enable_irq(dmov_conf[adm].irq);
dmov_conf[adm].channel_active |= BIT(ch);
PRINT_IO("msm dmov enqueue command, %x, ch %d\n", cmd->cmdptr,
ch);
writel_relaxed(cmd->cmdptr, DMOV_REG(DMOV_CMD_PTR(ch), adm));
} else {
list_add_tail(&cmd->list, &dmov_conf[adm].ready_commands[ch]);
if (list_empty(&dmov_conf[adm].active_commands[ch]) &&
!list_empty(&dmov_conf[adm].ready_commands[ch]))
PRINT_ERROR("msm_dmov_enqueue_cmd_ext(%d), stalled, "
"status %x\n", id, status);
PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status "
"%x\n", id, status);
}
}
static void __msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd,
int onstack)
{
int adm = DMOV_ID_TO_ADM(id);
int ch = DMOV_ID_TO_CHAN(id);
unsigned long flags;
cmd->id = id;
cmd->toflush = 0;
spin_lock_irqsave(&dmov_conf[adm].lock, flags);
switch (dmov_conf[adm].clk_ctl) {
case CLK_DIS:
case CLK_DISABLING:
if (onstack)
INIT_WORK_ONSTACK(&cmd->work,
msm_dmov_enqueue_cmd_ext_work);
else
INIT_WORK(&cmd->work,
msm_dmov_enqueue_cmd_ext_work);
list_add_tail(&cmd->list, &dmov_conf[adm].staged_commands[ch]);
dmov_conf[adm].clk_ctl = CLK_ENABLING;
queue_work(dmov_conf[adm].cmd_wq, &cmd->work);
break;
case CLK_ENABLING:
list_add_tail(&cmd->list, &dmov_conf[adm].staged_commands[ch]);
break;
case CLK_EN:
msm_dmov_enqueue_cmd_ext_atomic(id, cmd);
break;
case CLK_TO_BE_DIS:
cancel_delayed_work(&dmov_conf[adm].work);
dmov_conf[adm].clk_ctl = CLK_EN;
msm_dmov_enqueue_cmd_ext_atomic(id, cmd);
break;
default:
PRINT_ERROR("ADM%d: Invalid CLK State.\n", adm);
BUG_ON(dmov_conf[adm].clk_ctl);
}
spin_unlock_irqrestore(&dmov_conf[adm].lock, flags);
}
void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd)
{
__msm_dmov_enqueue_cmd_ext(id, cmd, 0);
}
EXPORT_SYMBOL(msm_dmov_enqueue_cmd_ext);
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
{
/* Disable callback function (for backwards compatibility) */
cmd->exec_func = NULL;
__msm_dmov_enqueue_cmd_ext(id, cmd, 0);
}
EXPORT_SYMBOL(msm_dmov_enqueue_cmd);
void msm_dmov_flush(unsigned int id, int graceful)
{
unsigned long irq_flags;
int ch = DMOV_ID_TO_CHAN(id);
int adm = DMOV_ID_TO_ADM(id);
int flush = graceful ? DMOV_FLUSH_TYPE : 0;
struct msm_dmov_cmd *cmd;
spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
/* XXX not checking if flush cmd sent already */
if (!list_empty(&dmov_conf[adm].active_commands[ch])) {
PRINT_IO("msm_dmov_flush(%d), send flush cmd\n", id);
writel_relaxed(flush, DMOV_REG(DMOV_FLUSH0(ch), adm));
}
list_for_each_entry(cmd, &dmov_conf[adm].staged_commands[ch], list)
cmd->toflush = graceful ? GRACEFUL : NONGRACEFUL;
list_for_each_entry(cmd, &dmov_conf[adm].ready_commands[ch], list)
cmd->toflush = graceful ? GRACEFUL : NONGRACEFUL;
/* spin_unlock_irqrestore has the necessary barrier */
spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
}
EXPORT_SYMBOL(msm_dmov_flush);
struct msm_dmov_exec_cmdptr_cmd {
struct msm_dmov_cmd dmov_cmd;
struct completion complete;
unsigned id;
unsigned int result;
struct msm_dmov_errdata err;
};
static void
dmov_exec_cmdptr_complete_func(struct msm_dmov_cmd *_cmd,
unsigned int result,
struct msm_dmov_errdata *err)
{
struct msm_dmov_exec_cmdptr_cmd *cmd =
container_of(_cmd, struct msm_dmov_exec_cmdptr_cmd, dmov_cmd);
cmd->result = result;
if (result != 0x80000002 && err)
memcpy(&cmd->err, err, sizeof(struct msm_dmov_errdata));
complete(&cmd->complete);
}
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr)
{
struct msm_dmov_exec_cmdptr_cmd cmd;
PRINT_FLOW("dmov_exec_cmdptr(%d, %x)\n", id, cmdptr);
cmd.dmov_cmd.cmdptr = cmdptr;
cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func;
cmd.dmov_cmd.exec_func = NULL;
cmd.id = id;
cmd.result = 0;
init_completion(&cmd.complete);
__msm_dmov_enqueue_cmd_ext(id, &cmd.dmov_cmd, 1);
wait_for_completion_io(&cmd.complete);
if (cmd.result != 0x80000002) {
PRINT_ERROR("dmov_exec_cmdptr(%d): ERROR, result: %x\n",
id, cmd.result);
PRINT_ERROR("dmov_exec_cmdptr(%d): flush: %x %x %x %x\n",
id, cmd.err.flush[0], cmd.err.flush[1],
cmd.err.flush[2], cmd.err.flush[3]);
return -EIO;
}
PRINT_FLOW("dmov_exec_cmdptr(%d, %x) done\n", id, cmdptr);
return 0;
}
EXPORT_SYMBOL(msm_dmov_exec_cmd);
static void fill_errdata(struct msm_dmov_errdata *errdata, int ch, int adm)
{
errdata->flush[0] = readl_relaxed(DMOV_REG(DMOV_FLUSH0(ch), adm));
errdata->flush[1] = readl_relaxed(DMOV_REG(DMOV_FLUSH1(ch), adm));
errdata->flush[2] = 0;
errdata->flush[3] = readl_relaxed(DMOV_REG(DMOV_FLUSH3(ch), adm));
errdata->flush[4] = readl_relaxed(DMOV_REG(DMOV_FLUSH4(ch), adm));
errdata->flush[5] = readl_relaxed(DMOV_REG(DMOV_FLUSH5(ch), adm));
}
static irqreturn_t msm_dmov_isr(int irq, void *dev_id)
{
unsigned int int_status;
unsigned int mask;
unsigned int id;
unsigned int ch;
unsigned long irq_flags;
unsigned int ch_status;
unsigned int ch_result;
unsigned int valid = 0;
struct msm_dmov_cmd *cmd;
int adm = DMOV_IRQ_TO_ADM(irq);
spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
/* read and clear isr */
int_status = readl_relaxed(DMOV_REG(DMOV_ISR, adm));
PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status);
while (int_status) {
mask = int_status & -int_status;
ch = fls(mask) - 1;
id = DMOV_CHAN_ADM_TO_ID(ch, adm);
PRINT_FLOW("msm_datamover_irq_handler %08x %08x id %d\n",
int_status, mask, id);
int_status &= ~mask;
ch_status = readl_relaxed(DMOV_REG(DMOV_STATUS(ch), adm));
if (!(ch_status & DMOV_STATUS_RSLT_VALID)) {
PRINT_FLOW("msm_datamover_irq_handler id %d, "
"result not valid %x\n", id, ch_status);
continue;
}
do {
valid = 1;
ch_result = readl_relaxed(DMOV_REG(DMOV_RSLT(ch), adm));
if (list_empty(&dmov_conf[adm].active_commands[ch])) {
PRINT_ERROR("msm_datamover_irq_handler id %d,"\
" got result with no active command,"
" status %x, result %x\n",
id, ch_status, ch_result);
cmd = NULL;
} else {
cmd = list_entry(dmov_conf[adm].
active_commands[ch].next, typeof(*cmd),
list);
}
PRINT_FLOW("msm_datamover_irq_handler id %d, status"\
" %x, result %x\n", id, ch_status, ch_result);
if (ch_result & DMOV_RSLT_DONE) {
PRINT_FLOW("msm_datamover_irq_handler id %d,"\
" status %x\n", id, ch_status);
PRINT_IO("msm_datamover_irq_handler id %d,"\
" got result for %p,"
" result %x\n", id, cmd, ch_result);
if (cmd) {
list_del(&cmd->list);
cmd->complete_func(cmd, ch_result,
NULL);
}
}
if (ch_result & DMOV_RSLT_FLUSH) {
struct msm_dmov_errdata errdata;
fill_errdata(&errdata, ch, adm);
PRINT_FLOW("msm_datamover_irq_handler id %d,"\
" status %x\n", id, ch_status);
PRINT_FLOW("msm_datamover_irq_handler id %d,"\
" flush, result %x,flush0 %x\n", id,
ch_result, errdata.flush[0]);
if (cmd) {
list_del(&cmd->list);
cmd->complete_func(cmd, ch_result,
&errdata);
}
}
if (ch_result & DMOV_RSLT_ERROR) {
struct msm_dmov_errdata errdata;
fill_errdata(&errdata, ch, adm);
PRINT_ERROR("msm_datamover_irq_handler id %d,"\
" status %x\n", id, ch_status);
PRINT_ERROR("msm_datamover_irq_handler id %d,"\
" error, result %x, flush0 %x\n",
id, ch_result, errdata.flush[0]);
if (cmd) {
list_del(&cmd->list);
cmd->complete_func(cmd, ch_result,
&errdata);
}
/* this does not seem to work, once we get an
* error. the datamover will no longer accept
* commands
*/
writel_relaxed(0, DMOV_REG(DMOV_FLUSH0(ch),
adm));
}
rmb();
ch_status = readl_relaxed(DMOV_REG(DMOV_STATUS(ch),
adm));
PRINT_FLOW("msm_datamover_irq_handler id %d, status"\
" %x\n", id, ch_status);
if (ch_status & DMOV_STATUS_CMD_PTR_RDY) {
cmd = start_ready_cmd(ch, adm);
if (cmd != NULL) {
if (cmd->toflush) {
int flush = (cmd->toflush ==
GRACEFUL) ? 1 << 31 : 0;
writel_relaxed(flush,
DMOV_REG(DMOV_FLUSH0(ch), adm));
}
}
}
} while (ch_status & DMOV_STATUS_RSLT_VALID);
if (list_empty(&dmov_conf[adm].active_commands[ch]) &&
list_empty(&dmov_conf[adm].ready_commands[ch]))
dmov_conf[adm].channel_active &= ~(1U << ch);
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id,
ch_status);
}
if (!dmov_conf[adm].channel_active && valid) {
disable_irq_nosync(dmov_conf[adm].irq);
dmov_conf[adm].clk_ctl = CLK_TO_BE_DIS;
schedule_delayed_work(&dmov_conf[adm].work, (HZ/10));
}
spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
return valid ? IRQ_HANDLED : IRQ_NONE;
}
static int msm_dmov_suspend_late(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
int adm = (pdev->id >= 0) ? pdev->id : 0;
unsigned long irq_flags;
mutex_lock(&dmov_conf[adm].clock_lock);
spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
if (dmov_conf[adm].clk_ctl == CLK_TO_BE_DIS) {
BUG_ON(dmov_conf[adm].channel_active);
dmov_conf[adm].clk_ctl = CLK_DISABLING;
spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
msm_dmov_clk_off(adm);
spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
if (dmov_conf[adm].clk_ctl == CLK_DISABLING)
dmov_conf[adm].clk_ctl = CLK_DIS;
}
spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
mutex_unlock(&dmov_conf[adm].clock_lock);
return 0;
}
static int msm_dmov_runtime_suspend(struct device *dev)
{
dev_dbg(dev, "pm_runtime: suspending...\n");
return 0;
}
static int msm_dmov_runtime_resume(struct device *dev)
{
dev_dbg(dev, "pm_runtime: resuming...\n");
return 0;
}
static int msm_dmov_runtime_idle(struct device *dev)
{
dev_dbg(dev, "pm_runtime: idling...\n");
return 0;
}
static const struct dev_pm_ops msm_dmov_dev_pm_ops = {
.runtime_suspend = msm_dmov_runtime_suspend,
.runtime_resume = msm_dmov_runtime_resume,
.runtime_idle = msm_dmov_runtime_idle,
.suspend = msm_dmov_suspend_late,
};
static int msm_dmov_init_clocks(struct platform_device *pdev)
{
int adm = (pdev->id >= 0) ? pdev->id : 0;
int ret;
dmov_conf[adm].clk = clk_get(&pdev->dev, "core_clk");
if (IS_ERR(dmov_conf[adm].clk)) {
printk(KERN_ERR "%s: Error getting adm_clk\n", __func__);
dmov_conf[adm].clk = NULL;
return -ENOENT;
}
dmov_conf[adm].pclk = clk_get(&pdev->dev, "iface_clk");
if (IS_ERR(dmov_conf[adm].pclk)) {
dmov_conf[adm].pclk = NULL;
/* pclk not present on all SoCs, don't bail on failure */
}
dmov_conf[adm].ebiclk = clk_get(&pdev->dev, "mem_clk");
if (IS_ERR(dmov_conf[adm].ebiclk)) {
dmov_conf[adm].ebiclk = NULL;
/* ebiclk not present on all SoCs, don't bail on failure */
} else {
ret = clk_set_rate(dmov_conf[adm].ebiclk, 27000000);
if (ret)
return -ENOENT;
}
return 0;
}
static void config_datamover(int adm)
{
#ifdef CONFIG_MSM_ADM3
int i;
for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) {
struct msm_dmov_chan_conf *chan_conf =
dmov_conf[adm].chan_conf;
unsigned conf;
/* Only configure scorpion channels */
if (chan_conf[i].sd <= 1) {
conf = readl_relaxed(DMOV_REG(DMOV_CONF(i), adm));
conf &= ~DMOV_CONF_SD(7);
conf |= DMOV_CONF_SD(chan_conf[i].sd);
writel_relaxed(conf | DMOV_CONF_SHADOW_EN,
DMOV_REG(DMOV_CONF(i), adm));
}
}
for (i = 0; i < MSM_DMOV_CRCI_COUNT; i++) {
struct msm_dmov_crci_conf *crci_conf =
dmov_conf[adm].crci_conf;
writel_relaxed(DMOV_CRCI_CTL_BLK_SZ(crci_conf[i].blk_size),
DMOV_REG(DMOV_CRCI_CTL(i), adm));
}
#endif
}
static int msm_dmov_probe(struct platform_device *pdev)
{
int adm = (pdev->id >= 0) ? pdev->id : 0;
int i;
int ret;
struct msm_dmov_pdata *pdata = pdev->dev.platform_data;
struct resource *irqres =
platform_get_resource(pdev, IORESOURCE_IRQ, 0);
struct resource *mres =
platform_get_resource(pdev, IORESOURCE_MEM, 0);
char wq_name[12];
if (pdata) {
dmov_conf[adm].sd = pdata->sd;
dmov_conf[adm].sd_size = pdata->sd_size;
}
if (!dmov_conf[adm].sd_size)
return -ENXIO;
if (!irqres || !irqres->start)
return -ENXIO;
dmov_conf[adm].irq = irqres->start;
if (!mres || !mres->start)
return -ENXIO;
dmov_conf[adm].base = ioremap_nocache(mres->start, resource_size(mres));
if (!dmov_conf[adm].base)
return -ENOMEM;
snprintf(wq_name, sizeof(wq_name), "dmov%d_wq", adm);
dmov_conf[adm].cmd_wq = alloc_workqueue(wq_name, WQ_CPU_INTENSIVE, 1);
if (!dmov_conf[adm].cmd_wq) {
PRINT_ERROR("Couldn't allocate ADM%d workqueue.\n", adm);
ret = -ENOMEM;
goto out_map;
}
ret = request_irq(dmov_conf[adm].irq, msm_dmov_isr,
0, "msmdatamover", NULL);
if (ret) {
PRINT_ERROR("Requesting ADM%d irq %d failed\n", adm,
dmov_conf[adm].irq);
goto out_wq;
}
disable_irq(dmov_conf[adm].irq);
ret = msm_dmov_init_clocks(pdev);
if (ret) {
PRINT_ERROR("Requesting ADM%d clocks failed\n", adm);
goto out_irq;
}
ret = msm_dmov_clk_on(adm);
if (ret) {
PRINT_ERROR("Enabling ADM%d clocks failed\n", adm);
goto out_irq;
}
config_datamover(adm);
for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) {
INIT_LIST_HEAD(&dmov_conf[adm].staged_commands[i]);
INIT_LIST_HEAD(&dmov_conf[adm].ready_commands[i]);
INIT_LIST_HEAD(&dmov_conf[adm].active_commands[i]);
writel_relaxed(DMOV_RSLT_CONF_IRQ_EN
| DMOV_RSLT_CONF_FORCE_FLUSH_RSLT,
DMOV_REG(DMOV_RSLT_CONF(i), adm));
}
wmb();
msm_dmov_clk_off(adm);
return ret;
out_irq:
free_irq(dmov_conf[adm].irq, NULL);
out_wq:
destroy_workqueue(dmov_conf[adm].cmd_wq);
out_map:
iounmap(dmov_conf[adm].base);
return ret;
}
static struct platform_driver msm_dmov_driver = {
.probe = msm_dmov_probe,
.driver = {
.name = MODULE_NAME,
.owner = THIS_MODULE,
.pm = &msm_dmov_dev_pm_ops,
},
};
/* static int __init */
static int __init msm_init_datamover(void)
{
int ret;
ret = platform_driver_register(&msm_dmov_driver);
if (ret)
return ret;
return 0;
}
arch_initcall(msm_init_datamover);
| gpl-2.0 |
TheWhisp/android_kernel_samsung_msm7x27 | drivers/staging/comedi/drivers/addi-data/APCI1710_Ttl.c | 943 | 35073 | /**
@verbatim
Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
ADDI-DATA GmbH
Dieselstrasse 3
D-77833 Ottersweier
Tel: +19(0)7223/9493-0
Fax: +49(0)7223/9493-92
http://www.addi-data-com
info@addi-data.com
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
You should also find the complete GPL in the COPYING file accompanying this source code.
@endverbatim
*/
/*
+-----------------------------------------------------------------------+
| (C) ADDI-DATA GmbH Dieselstraße 3 D-77833 Ottersweier |
+-----------------------------------------------------------------------+
| Tel : +49 (0) 7223/9493-0 | email : info@addi-data.com |
| Fax : +49 (0) 7223/9493-92 | Internet : http://www.addi-data.com |
+-----------------------------------------------------------------------+
| Project : API APCI1710 | Compiler : gcc |
| Module name : TTL.C | Version : 2.96 |
+-------------------------------+---------------------------------------+
| Project manager: Eric Stolz | Date : 02/12/2002 |
+-----------------------------------------------------------------------+
| Description : APCI-1710 TTL I/O module |
| |
| |
+-----------------------------------------------------------------------+
| UPDATES |
+-----------------------------------------------------------------------+
| Date | Author | Description of updates |
+----------+-----------+------------------------------------------------+
| 13/05/98 | S. Weber | TTL digital input / output implementation |
|----------|-----------|------------------------------------------------|
| 08/05/00 | Guinot C | - 0400/0228 All Function in RING 0 |
| | | available |
+-----------------------------------------------------------------------+
| | | |
| | | |
+-----------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Included files |
+----------------------------------------------------------------------------+
*/
#include "APCI1710_Ttl.h"
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_InitTTLIODirection |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_PortAMode, |
| unsigned char_ b_PortBMode, |
| unsigned char_ b_PortCMode, |
| unsigned char_ b_PortDMode) |
+----------------------------------------------------------------------------+
| Task APCI1710_TTL_INIT (using defaults) : Configure the TTL I/O operating mode from selected |
| module (b_ModulNbr). You must calling this function be|
| for you call any other function witch access of TTL. |
APCI1710_TTL_INITDIRECTION(user inputs for direction)
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710|
| unsigned char_ b_ModulNbr : Module number to |
| configure (0 to 3)
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
b_InitType = (unsigned char) data[0];
b_PortAMode = (unsigned char) data[1];
b_PortBMode = (unsigned char) data[2];
b_PortCMode = (unsigned char) data[3];
b_PortDMode = (unsigned char) data[4];|
+----------------------------------------------------------------------------+
| Output Parameters : - |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: The module parameter is wrong |
| -3: The module is not a TTL module |
| -4: Function not available for this version |
| -5: Port A mode selection is wrong |
| -6: Port B mode selection is wrong |
| -7: Port C mode selection is wrong |
| -8: Port D mode selection is wrong |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnConfigInitTTLIO(struct comedi_device *dev, struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned char b_ModulNbr;
unsigned char b_InitType;
unsigned char b_PortAMode;
unsigned char b_PortBMode;
unsigned char b_PortCMode;
unsigned char b_PortDMode;
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
b_InitType = (unsigned char) data[0];
i_ReturnValue = insn->n;
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/**************************/
/* Test if TTL I/O module */
/**************************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TTL_IO) {
switch (b_InitType) {
case APCI1710_TTL_INIT:
devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_TTLInit = 1;
/***************************/
/* Set TTL port A to input */
/***************************/
devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_PortConfiguration[0] = 0;
/***************************/
/* Set TTL port B to input */
/***************************/
devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_PortConfiguration[1] = 0;
/***************************/
/* Set TTL port C to input */
/***************************/
devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_PortConfiguration[2] = 0;
/****************************/
/* Set TTL port D to output */
/****************************/
devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_PortConfiguration[3] = 1;
/*************************/
/* Set the configuration */
/*************************/
outl(0x8,
devpriv->s_BoardInfos.ui_Address + 20 +
(64 * b_ModulNbr));
break;
case APCI1710_TTL_INITDIRECTION:
b_PortAMode = (unsigned char) data[1];
b_PortBMode = (unsigned char) data[2];
b_PortCMode = (unsigned char) data[3];
b_PortDMode = (unsigned char) data[4];
/********************/
/* Test the version */
/********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] & 0xFFFF) >=
0x3230) {
/************************/
/* Test the port A mode */
/************************/
if ((b_PortAMode == 0)
|| (b_PortAMode == 1)) {
/************************/
/* Test the port B mode */
/************************/
if ((b_PortBMode == 0)
|| (b_PortBMode == 1)) {
/************************/
/* Test the port C mode */
/************************/
if ((b_PortCMode == 0)
|| (b_PortCMode
== 1)) {
/************************/
/* Test the port D mode */
/************************/
if ((b_PortDMode == 0) || (b_PortDMode == 1)) {
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_TTLInit
=
1;
/***********************/
/* Set TTL port A mode */
/***********************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[0]
=
b_PortAMode;
/***********************/
/* Set TTL port B mode */
/***********************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[1]
=
b_PortBMode;
/***********************/
/* Set TTL port C mode */
/***********************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[2]
=
b_PortCMode;
/***********************/
/* Set TTL port D mode */
/***********************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[3]
=
b_PortDMode;
/*************************/
/* Set the configuration */
/*************************/
outl((b_PortAMode << 0) | (b_PortBMode << 1) | (b_PortCMode << 2) | (b_PortDMode << 3), devpriv->s_BoardInfos.ui_Address + 20 + (64 * b_ModulNbr));
} else {
/**********************************/
/* Port D mode selection is wrong */
/**********************************/
DPRINTK("Port D mode selection is wrong\n");
i_ReturnValue
=
-8;
}
} else {
/**********************************/
/* Port C mode selection is wrong */
/**********************************/
DPRINTK("Port C mode selection is wrong\n");
i_ReturnValue =
-7;
}
} else {
/**********************************/
/* Port B mode selection is wrong */
/**********************************/
DPRINTK("Port B mode selection is wrong\n");
i_ReturnValue = -6;
}
} else {
/**********************************/
/* Port A mode selection is wrong */
/**********************************/
DPRINTK("Port A mode selection is wrong\n");
i_ReturnValue = -5;
}
} else {
/*******************************************/
/* Function not available for this version */
/*******************************************/
DPRINTK("Function not available for this version\n");
i_ReturnValue = -4;
}
break;
DPRINTK("\n");
default:
printk("Bad Config Type\n");
} /* switch end */
} else {
/**********************************/
/* The module is not a TTL module */
/**********************************/
DPRINTK("The module is not a TTL module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| INPUT FUNCTIONS |
+----------------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_ReadTTLIOChannelValue |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_SelectedPort, |
| unsigned char_ b_InputChannel, |
| unsigned char *_ pb_ChannelStatus) |
+----------------------------------------------------------------------------+
| Task : Read the status from selected TTL digital input |
| (b_InputChannel)
+----------------------------------------------------------------------------+
| Task : Read the status from digital input port |
| (b_SelectedPort) from selected TTL module (b_ModulNbr) |
+----------------------------------------------------------------------------+
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710|
| unsigned char_ b_ModulNbr : Module number to |
| configure (0 to 7) |
| unsigned char_ b_SelectedPort, : Selection from TTL I/O |
| port (0 to 2) |
| 0 : Port A selection |
| 1 : Port B selection |
| 2 : Port C selection |
| 3 : Port D selection |
| unsigned char_ b_InputChannel : Selection from digital |
| input ( 0 to 2)
APCI1710_TTL_READCHANNEL
b_ModulNbr = CR_AREF(insn->chanspec);
b_SelectedPort= CR_RANGE(insn->chanspec);
b_InputChannel= CR_CHAN(insn->chanspec);
b_ReadType = (unsigned char) data[0];
APCI1710_TTL_READPORT|
b_ModulNbr = CR_AREF(insn->chanspec);
b_SelectedPort= CR_RANGE(insn->chanspec);
b_ReadType = (unsigned char) data[0];
+----------------------------------------------------------------------------+
| Output Parameters : data[0]
unsigned char *_ pb_ChannelStatus : Digital input channel |
| status |
| 0 : Channle is not active|
| 1 : Channle is active |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: The module parameter is wrong |
| -3: The module is not a TTL module |
| -4: The selected TTL input port is wrong |
| -5: The selected TTL digital input is wrong |
| -6: TTL I/O not initialised |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnBitsReadTTLIO(struct comedi_device *dev, struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_StatusReg;
unsigned char b_ModulNbr;
unsigned char b_SelectedPort;
unsigned char b_InputChannel;
unsigned char b_ReadType;
unsigned char *pb_ChannelStatus;
unsigned char *pb_PortValue;
i_ReturnValue = insn->n;
b_ReadType = (unsigned char) data[0];
b_ModulNbr = CR_AREF(insn->chanspec);
b_SelectedPort = CR_RANGE(insn->chanspec);
b_InputChannel = CR_CHAN(insn->chanspec);
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/**************************/
/* Test if TTL I/O module */
/**************************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TTL_IO) {
switch (b_ReadType) {
case APCI1710_TTL_READCHANNEL:
pb_ChannelStatus = (unsigned char *) &data[0];
/********************************/
/* Test the TTL I/O port number */
/********************************/
if (((b_SelectedPort <= 2)
&& ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] &
0xFFFF) ==
0x3130))
|| ((b_SelectedPort <= 3)
&& ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] &
0xFFFF) >=
0x3230))) {
/******************************************/
/* Test the digital imnput channel number */
/******************************************/
if (((b_InputChannel <= 7)
&& (b_SelectedPort < 3))
|| ((b_InputChannel <= 1)
&& (b_SelectedPort ==
3))) {
/******************************************/
/* Test if the TTL I/O module initialised */
/******************************************/
if (devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.b_TTLInit ==
1) {
/***********************************/
/* Test if TTL port used for input */
/***********************************/
if (((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) == 0x3130) || (((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) >= 0x3230) && (devpriv->s_ModuleInfo[b_ModulNbr].s_TTLIOInfo.b_PortConfiguration[b_SelectedPort] == 0))) {
/**************************/
/* Read all digital input */
/**************************/
dw_StatusReg =
inl
(devpriv->
s_BoardInfos.
ui_Address
+
(64 * b_ModulNbr));
*pb_ChannelStatus
=
(unsigned char) (
(dw_StatusReg
>>
(8 * b_SelectedPort)) >> b_InputChannel) & 1;
} else {
/*******************************/
/* Selected TTL I/O port error */
/*******************************/
DPRINTK("Selected TTL I/O port error\n");
i_ReturnValue =
-4;
}
} else {
/***************************/
/* TTL I/O not initialised */
/***************************/
DPRINTK("TTL I/O not initialised\n");
i_ReturnValue = -6;
}
} else {
/********************************/
/* Selected digital input error */
/********************************/
DPRINTK("Selected digital input error\n");
i_ReturnValue = -5;
}
} else {
/*******************************/
/* Selected TTL I/O port error */
/*******************************/
DPRINTK("Selected TTL I/O port error\n");
i_ReturnValue = -4;
}
break;
case APCI1710_TTL_READPORT:
pb_PortValue = (unsigned char *) &data[0];
/********************************/
/* Test the TTL I/O port number */
/********************************/
if (((b_SelectedPort <= 2)
&& ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] &
0xFFFF) ==
0x3130))
|| ((b_SelectedPort <= 3)
&& ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] &
0xFFFF) >=
0x3230))) {
/******************************************/
/* Test if the TTL I/O module initialised */
/******************************************/
if (devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_TTLInit == 1) {
/***********************************/
/* Test if TTL port used for input */
/***********************************/
if (((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr]
&
0xFFFF)
== 0x3130)
|| (((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) >= 0x3230) && (devpriv->s_ModuleInfo[b_ModulNbr].s_TTLIOInfo.b_PortConfiguration[b_SelectedPort] == 0))) {
/**************************/
/* Read all digital input */
/**************************/
dw_StatusReg =
inl(devpriv->
s_BoardInfos.
ui_Address +
(64 * b_ModulNbr));
*pb_PortValue =
(unsigned char) (
(dw_StatusReg >>
(8 * b_SelectedPort)) & 0xFF);
} else {
/*******************************/
/* Selected TTL I/O port error */
/*******************************/
DPRINTK("Selected TTL I/O port error\n");
i_ReturnValue = -4;
}
} else {
/***************************/
/* TTL I/O not initialised */
/***************************/
DPRINTK("TTL I/O not initialised\n");
i_ReturnValue = -5;
}
} else {
/*******************************/
/* Selected TTL I/O port error */
/*******************************/
DPRINTK("Selected TTL I/O port error\n");
i_ReturnValue = -4;
}
break;
default:
printk("Bad ReadType\n");
} /* End Switch */
} else {
/**********************************/
/* The module is not a TTL module */
/**********************************/
DPRINTK("The module is not a TTL module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : int i_APCI1710_InsnReadTTLIOAllPortValue(comedi_device
*dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) |
+----------------------------------------------------------------------------+
| Task : Read the status from all digital input ports |
| (port A, port B and port C) from selected TTL |
| module (b_ModulNbr) |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710|
| unsigned char_ b_ModulNbr : Module number to |
| configure (0 to 3) |
+----------------------------------------------------------------------------+
| Output Parameters : PULONG_ pul_PortValue : Digital TTL inputs port |
| status |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: The module parameter is wrong |
| -3: The module is not a TTL module |
| -4: TTL I/O not initialised |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnReadTTLIOAllPortValue(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_StatusReg;
unsigned char b_ModulNbr;
unsigned int *pul_PortValue;
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
i_ReturnValue = insn->n;
pul_PortValue = (unsigned int *) &data[0];
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/**************************/
/* Test if TTL I/O module */
/**************************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TTL_IO) {
/******************************************/
/* Test if the TTL I/O module initialised */
/******************************************/
if (devpriv->
s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_TTLInit == 1) {
/**************************/
/* Read all digital input */
/**************************/
dw_StatusReg = inl(devpriv->s_BoardInfos.
ui_Address + (64 * b_ModulNbr));
/**********************/
/* Test if TTL Rev1.0 */
/**********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] & 0xFFFF) ==
0x3130) {
*pul_PortValue =
dw_StatusReg & 0xFFFFFFUL;
} else {
/**************************************/
/* Test if port A not used for output */
/**************************************/
if (devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration[0] == 1) {
*pul_PortValue =
dw_StatusReg &
0x3FFFF00UL;
}
/**************************************/
/* Test if port B not used for output */
/**************************************/
if (devpriv->
s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration[1] == 1) {
*pul_PortValue =
dw_StatusReg &
0x3FF00FFUL;
}
/**************************************/
/* Test if port C not used for output */
/**************************************/
if (devpriv->
s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration[2] == 1) {
*pul_PortValue =
dw_StatusReg &
0x300FFFFUL;
}
/**************************************/
/* Test if port D not used for output */
/**************************************/
if (devpriv->
s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration[3] == 1) {
*pul_PortValue =
dw_StatusReg &
0xFFFFFFUL;
}
}
} else {
/***************************/
/* TTL I/O not initialised */
/***************************/
DPRINTK("TTL I/O not initialised\n");
i_ReturnValue = -5;
}
} else {
/**********************************/
/* The module is not a TTL module */
/**********************************/
DPRINTK("The module is not a TTL module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| OUTPUT FUNCTIONS |
+----------------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_SetTTLIOChlOn |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_OutputChannel)
int i_APCI1710_InsnWriteSetTTLIOChlOnOff(struct comedi_device *dev,struct comedi_subdevice *s,
struct comedi_insn *insn,unsigned int *data) |
+----------------------------------------------------------------------------+
| Task : Sets or resets the output witch has been passed with the |
| parameter b_Channel. Setting an output means setting |
| an ouput high. |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3)|
| unsigned char_ b_OutputChannel : Selection from digital output |
| channel (0 or 1) |
| 0 : PD0 |
| 1 : PD1 |
| 2 to 9 : PA |
| 10 to 17: PB |
| 18 to 25: PC |
b_ModulNbr = CR_AREF(insn->chanspec);
b_OutputChannel= CR_CHAN(insn->chanspec);
ui_State = data[0]; /* ON or OFF */
+----------------------------------------------------------------------------+
| Output Parameters : - |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: The module parameter is wrong |
| -3: The module is not a TTL I/O module |
| -4: The selected digital output is wrong |
| -5: TTL I/O not initialised see function |
| " i_APCI1710_InitTTLIO"
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnWriteSetTTLIOChlOnOff(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_StatusReg = 0;
unsigned char b_ModulNbr;
unsigned char b_OutputChannel;
unsigned int ui_State;
i_ReturnValue = insn->n;
b_ModulNbr = CR_AREF(insn->chanspec);
b_OutputChannel = CR_CHAN(insn->chanspec);
ui_State = data[0]; /* ON or OFF */
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/**************************/
/* Test if TTL I/O module */
/**************************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TTL_IO) {
/******************************************/
/* Test if the TTL I/O module initialised */
/******************************************/
if (devpriv->s_ModuleInfo[b_ModulNbr].
s_TTLIOInfo.b_TTLInit == 1) {
/***********************************/
/* Test the TTL I/O channel number */
/***********************************/
if (((b_OutputChannel <= 1)
&& ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] &
0xFFFF) ==
0x3130))
|| ((b_OutputChannel <= 25)
&& ((devpriv->s_BoardInfos.
dw_MolduleConfiguration
[b_ModulNbr] &
0xFFFF) >=
0x3230))) {
/****************************************************/
/* Test if the selected channel is a output channel */
/****************************************************/
if (((b_OutputChannel <= 1)
&& (devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[3] == 1))
|| ((b_OutputChannel >= 2)
&& (b_OutputChannel <=
9)
&& (devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[0] == 1))
|| ((b_OutputChannel >= 10)
&& (b_OutputChannel <=
17)
&& (devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[1] == 1))
|| ((b_OutputChannel >= 18)
&& (b_OutputChannel <=
25)
&& (devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TTLIOInfo.
b_PortConfiguration
[2] == 1))) {
/************************/
/* Test if PD0 selected */
/************************/
if (b_OutputChannel == 0) {
outl(ui_State,
devpriv->
s_BoardInfos.
ui_Address +
(64 * b_ModulNbr));
} else {
/************************/
/* Test if PD1 selected */
/************************/
if (b_OutputChannel ==
1) {
outl(ui_State,
devpriv->
s_BoardInfos.
ui_Address
+ 4 +
(64 * b_ModulNbr));
} else {
b_OutputChannel
=
b_OutputChannel
- 2;
/********************/
/* Read all channel */
/********************/
dw_StatusReg =
inl
(devpriv->
s_BoardInfos.
ui_Address
+
(64 * b_ModulNbr));
if (ui_State) /* ON */
{
dw_StatusReg
=
(dw_StatusReg
>>
((b_OutputChannel / 8) * 8)) & 0xFF;
dw_StatusReg
=
dw_StatusReg
|
(1
<<
(b_OutputChannel
%
8));
} else /* Off */
{
dw_StatusReg
=
(dw_StatusReg
>>
((b_OutputChannel / 8) * 8)) & 0xFF;
dw_StatusReg
=
dw_StatusReg
&
(0xFF
-
(1 << (b_OutputChannel % 8)));
}
/****************************/
/* Set the new output value */
/****************************/
outl(dw_StatusReg, devpriv->s_BoardInfos.ui_Address + 8 + ((b_OutputChannel / 8) * 4) + (64 * b_ModulNbr));
}
}
} else {
/************************************/
/* The selected TTL output is wrong */
/************************************/
DPRINTK(" The selected TTL output is wrong\n");
i_ReturnValue = -4;
}
} else {
/************************************/
/* The selected TTL output is wrong */
/************************************/
DPRINTK("The selected TTL output is wrong\n");
i_ReturnValue = -4;
}
} else {
/***************************/
/* TTL I/O not initialised */
/***************************/
DPRINTK("TTL I/O not initialised\n");
i_ReturnValue = -5;
}
} else {
/**************************************/
/* The module is not a TTL I/O module */
/**************************************/
DPRINTK("The module is not a TTL I/O module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
| gpl-2.0 |
Shaky156/Shield-Tablet-CPU2.5Ghz-GPU060Mhz-Overclock | arch/mips/loongson/common/setup.c | 2479 | 1196 | /*
* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
* Author: Fuxin Zhang, zhangfx@lemote.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <asm/wbflush.h>
#include <loongson.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#include <linux/screen_info.h>
#endif
void (*__wbflush)(void);
EXPORT_SYMBOL(__wbflush);
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
".set\tnoreorder\n\t"
".set mips3\n\t"
"sync\n\t"
"nop\n\t"
".set\tpop\n\t"
".set mips0\n\t");
}
void __init plat_mem_setup(void)
{
__wbflush = wbflush_loongson;
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
screen_info = (struct screen_info) {
.orig_x = 0,
.orig_y = 25,
.orig_video_cols = 80,
.orig_video_lines = 25,
.orig_video_isVGA = VIDEO_TYPE_VGAC,
.orig_video_points = 16,
};
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
}
| gpl-2.0 |
multirom-op2/android_kernel_oneplus_msm8994 | arch/sparc/kernel/sun4d_irq.c | 2479 | 12316 | /*
* SS1000/SC2000 interrupt handling.
*
* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
* Heavily based on arch/sparc/kernel/irq.c.
*/
#include <linux/kernel_stat.h>
#include <linux/slab.h>
#include <linux/seq_file.h>
#include <asm/timer.h>
#include <asm/traps.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/sbi.h>
#include <asm/cacheflush.h>
#include <asm/setup.h>
#include <asm/oplib.h>
#include "kernel.h"
#include "irq.h"
/* Sun4d interrupts fall roughly into two categories. SBUS and
* cpu local. CPU local interrupts cover the timer interrupts
* and whatnot, and we encode those as normal PILs between
* 0 and 15.
* SBUS interrupts are encodes as a combination of board, level and slot.
*/
struct sun4d_handler_data {
unsigned int cpuid; /* target cpu */
unsigned int real_irq; /* interrupt level */
};
static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
{
return (board + 1) << 5 | (lvl << 2) | slot;
}
struct sun4d_timer_regs {
u32 l10_timer_limit;
u32 l10_cur_countx;
u32 l10_limit_noclear;
u32 ctrl;
u32 l10_cur_count;
};
static struct sun4d_timer_regs __iomem *sun4d_timers;
#define SUN4D_TIMER_IRQ 10
/* Specify which cpu handle interrupts from which board.
* Index is board - value is cpu.
*/
static unsigned char board_to_cpu[32];
static int pil_to_sbus[] = {
0,
0,
1,
2,
0,
3,
0,
4,
0,
5,
0,
6,
0,
7,
0,
0,
};
/* Exported for sun4d_smp.c */
DEFINE_SPINLOCK(sun4d_imsk_lock);
/* SBUS interrupts are encoded integers including the board number
* (plus one), the SBUS level, and the SBUS slot number. Sun4D
* IRQ dispatch is done by:
*
* 1) Reading the BW local interrupt table in order to get the bus
* interrupt mask.
*
* This table is indexed by SBUS interrupt level which can be
* derived from the PIL we got interrupted on.
*
* 2) For each bus showing interrupt pending from #1, read the
* SBI interrupt state register. This will indicate which slots
* have interrupts pending for that SBUS interrupt level.
*
* 3) Call the genreric IRQ support.
*/
static void sun4d_sbus_handler_irq(int sbusl)
{
unsigned int bus_mask;
unsigned int sbino, slot;
unsigned int sbil;
bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
bw_clear_intr_mask(sbusl, bus_mask);
sbil = (sbusl << 2);
/* Loop for each pending SBI */
for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
unsigned int idx, mask;
if (!(bus_mask & 1))
continue;
/* XXX This seems to ACK the irq twice. acquire_sbi()
* XXX uses swap, therefore this writes 0xf << sbil,
* XXX then later release_sbi() will write the individual
* XXX bits which were set again.
*/
mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
mask &= (0xf << sbil);
/* Loop for each pending SBI slot */
slot = (1 << sbil);
for (idx = 0; mask != 0; idx++, slot <<= 1) {
unsigned int pil;
struct irq_bucket *p;
if (!(mask & slot))
continue;
mask &= ~slot;
pil = sun4d_encode_irq(sbino, sbusl, idx);
p = irq_map[pil];
while (p) {
struct irq_bucket *next;
next = p->next;
generic_handle_irq(p->irq);
p = next;
}
release_sbi(SBI2DEVID(sbino), slot);
}
}
}
void sun4d_handler_irq(int pil, struct pt_regs *regs)
{
struct pt_regs *old_regs;
/* SBUS IRQ level (1 - 7) */
int sbusl = pil_to_sbus[pil];
/* FIXME: Is this necessary?? */
cc_get_ipen();
cc_set_iclr(1 << pil);
#ifdef CONFIG_SMP
/*
* Check IPI data structures after IRQ has been cleared. Hard and Soft
* IRQ can happen at the same time, so both cases are always handled.
*/
if (pil == SUN4D_IPI_IRQ)
sun4d_ipi_interrupt();
#endif
old_regs = set_irq_regs(regs);
irq_enter();
if (sbusl == 0) {
/* cpu interrupt */
struct irq_bucket *p;
p = irq_map[pil];
while (p) {
struct irq_bucket *next;
next = p->next;
generic_handle_irq(p->irq);
p = next;
}
} else {
/* SBUS interrupt */
sun4d_sbus_handler_irq(sbusl);
}
irq_exit();
set_irq_regs(old_regs);
}
static void sun4d_mask_irq(struct irq_data *data)
{
struct sun4d_handler_data *handler_data = data->handler_data;
unsigned int real_irq;
#ifdef CONFIG_SMP
int cpuid = handler_data->cpuid;
unsigned long flags;
#endif
real_irq = handler_data->real_irq;
#ifdef CONFIG_SMP
spin_lock_irqsave(&sun4d_imsk_lock, flags);
cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
#else
cc_set_imsk(cc_get_imsk() | (1 << real_irq));
#endif
}
static void sun4d_unmask_irq(struct irq_data *data)
{
struct sun4d_handler_data *handler_data = data->handler_data;
unsigned int real_irq;
#ifdef CONFIG_SMP
int cpuid = handler_data->cpuid;
unsigned long flags;
#endif
real_irq = handler_data->real_irq;
#ifdef CONFIG_SMP
spin_lock_irqsave(&sun4d_imsk_lock, flags);
cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
#else
cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
#endif
}
static unsigned int sun4d_startup_irq(struct irq_data *data)
{
irq_link(data->irq);
sun4d_unmask_irq(data);
return 0;
}
static void sun4d_shutdown_irq(struct irq_data *data)
{
sun4d_mask_irq(data);
irq_unlink(data->irq);
}
struct irq_chip sun4d_irq = {
.name = "sun4d",
.irq_startup = sun4d_startup_irq,
.irq_shutdown = sun4d_shutdown_irq,
.irq_unmask = sun4d_unmask_irq,
.irq_mask = sun4d_mask_irq,
};
#ifdef CONFIG_SMP
/* Setup IRQ distribution scheme. */
void __init sun4d_distribute_irqs(void)
{
struct device_node *dp;
int cpuid = cpu_logical_map(1);
if (cpuid == -1)
cpuid = cpu_logical_map(0);
for_each_node_by_name(dp, "sbi") {
int devid = of_getintprop_default(dp, "device-id", 0);
int board = of_getintprop_default(dp, "board#", 0);
board_to_cpu[board] = cpuid;
set_sbi_tid(devid, cpuid << 3);
}
printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
}
#endif
static void sun4d_clear_clock_irq(void)
{
sbus_readl(&sun4d_timers->l10_timer_limit);
}
static void sun4d_load_profile_irq(int cpu, unsigned int limit)
{
unsigned int value = limit ? timer_value(limit) : 0;
bw_set_prof_limit(cpu, value);
}
static void __init sun4d_load_profile_irqs(void)
{
int cpu = 0, mid;
while (!cpu_find_by_instance(cpu, NULL, &mid)) {
sun4d_load_profile_irq(mid >> 3, 0);
cpu++;
}
}
unsigned int _sun4d_build_device_irq(unsigned int real_irq,
unsigned int pil,
unsigned int board)
{
struct sun4d_handler_data *handler_data;
unsigned int irq;
irq = irq_alloc(real_irq, pil);
if (irq == 0) {
prom_printf("IRQ: allocate for %d %d %d failed\n",
real_irq, pil, board);
goto err_out;
}
handler_data = irq_get_handler_data(irq);
if (unlikely(handler_data))
goto err_out;
handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
if (unlikely(!handler_data)) {
prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
prom_halt();
}
handler_data->cpuid = board_to_cpu[board];
handler_data->real_irq = real_irq;
irq_set_chip_and_handler_name(irq, &sun4d_irq,
handle_level_irq, "level");
irq_set_handler_data(irq, handler_data);
err_out:
return irq;
}
unsigned int sun4d_build_device_irq(struct platform_device *op,
unsigned int real_irq)
{
struct device_node *dp = op->dev.of_node;
struct device_node *board_parent, *bus = dp->parent;
char *bus_connection;
const struct linux_prom_registers *regs;
unsigned int pil;
unsigned int irq;
int board, slot;
int sbusl;
irq = real_irq;
while (bus) {
if (!strcmp(bus->name, "sbi")) {
bus_connection = "io-unit";
break;
}
if (!strcmp(bus->name, "bootbus")) {
bus_connection = "cpu-unit";
break;
}
bus = bus->parent;
}
if (!bus)
goto err_out;
regs = of_get_property(dp, "reg", NULL);
if (!regs)
goto err_out;
slot = regs->which_io;
/*
* If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
* lacks a "board#" property, something is very wrong.
*/
if (!bus->parent || strcmp(bus->parent->name, bus_connection)) {
printk(KERN_ERR "%s: Error, parent is not %s.\n",
bus->full_name, bus_connection);
goto err_out;
}
board_parent = bus->parent;
board = of_getintprop_default(board_parent, "board#", -1);
if (board == -1) {
printk(KERN_ERR "%s: Error, lacks board# property.\n",
board_parent->full_name);
goto err_out;
}
sbusl = pil_to_sbus[real_irq];
if (sbusl)
pil = sun4d_encode_irq(board, sbusl, slot);
else
pil = real_irq;
irq = _sun4d_build_device_irq(real_irq, pil, board);
err_out:
return irq;
}
unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
{
return _sun4d_build_device_irq(real_irq, real_irq, board);
}
static void __init sun4d_fixup_trap_table(void)
{
#ifdef CONFIG_SMP
unsigned long flags;
struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
/* Adjust so that we jump directly to smp4d_ticker */
lvl14_save[2] += smp4d_ticker - real_irq_entry;
/* For SMP we use the level 14 ticker, however the bootup code
* has copied the firmware's level 14 vector into the boot cpu's
* trap table, we must fix this now or we get squashed.
*/
local_irq_save(flags);
patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
trap_table->inst_one = lvl14_save[0];
trap_table->inst_two = lvl14_save[1];
trap_table->inst_three = lvl14_save[2];
trap_table->inst_four = lvl14_save[3];
local_ops->cache_all();
local_irq_restore(flags);
#endif
}
static void __init sun4d_init_timers(void)
{
struct device_node *dp;
struct resource res;
unsigned int irq;
const u32 *reg;
int err;
int board;
dp = of_find_node_by_name(NULL, "cpu-unit");
if (!dp) {
prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
prom_halt();
}
/* Which cpu-unit we use is arbitrary, we can view the bootbus timer
* registers via any cpu's mapping. The first 'reg' property is the
* bootbus.
*/
reg = of_get_property(dp, "reg", NULL);
if (!reg) {
prom_printf("sun4d_init_timers: No reg property\n");
prom_halt();
}
board = of_getintprop_default(dp, "board#", -1);
if (board == -1) {
prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
prom_halt();
}
of_node_put(dp);
res.start = reg[1];
res.end = reg[2] - 1;
res.flags = reg[0] & 0xff;
sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
sizeof(struct sun4d_timer_regs), "user timer");
if (!sun4d_timers) {
prom_printf("sun4d_init_timers: Can't map timer regs\n");
prom_halt();
}
#ifdef CONFIG_SMP
sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
#else
sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
sparc_config.features |= FEAT_L10_CLOCKEVENT;
#endif
sparc_config.features |= FEAT_L10_CLOCKSOURCE;
sbus_writel(timer_value(sparc_config.cs_period),
&sun4d_timers->l10_timer_limit);
master_l10_counter = &sun4d_timers->l10_cur_count;
irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
if (err) {
prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
err);
prom_halt();
}
sun4d_load_profile_irqs();
sun4d_fixup_trap_table();
}
void __init sun4d_init_sbi_irq(void)
{
struct device_node *dp;
int target_cpu;
target_cpu = boot_cpu_id;
for_each_node_by_name(dp, "sbi") {
int devid = of_getintprop_default(dp, "device-id", 0);
int board = of_getintprop_default(dp, "board#", 0);
unsigned int mask;
set_sbi_tid(devid, target_cpu << 3);
board_to_cpu[board] = target_cpu;
/* Get rid of pending irqs from PROM */
mask = acquire_sbi(devid, 0xffffffff);
if (mask) {
printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
mask, board);
release_sbi(devid, mask);
}
}
}
void __init sun4d_init_IRQ(void)
{
local_irq_disable();
sparc_config.init_timers = sun4d_init_timers;
sparc_config.build_device_irq = sun4d_build_device_irq;
sparc_config.clock_rate = SBUS_CLOCK_RATE;
sparc_config.clear_clock_irq = sun4d_clear_clock_irq;
sparc_config.load_profile_irq = sun4d_load_profile_irq;
/* Cannot enable interrupts until OBP ticker is disabled. */
}
| gpl-2.0 |
sorenb-xlnx/linux-xlnx | drivers/sbus/char/flash.c | 2479 | 4867 | /* flash.c: Allow mmap access to the OBP Flash, for OBP updates.
*
* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/fcntl.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/io.h>
#include <asm/upa.h>
static DEFINE_MUTEX(flash_mutex);
static DEFINE_SPINLOCK(flash_lock);
static struct {
unsigned long read_base; /* Physical read address */
unsigned long write_base; /* Physical write address */
unsigned long read_size; /* Size of read area */
unsigned long write_size; /* Size of write area */
unsigned long busy; /* In use? */
} flash;
#define FLASH_MINOR 152
static int
flash_mmap(struct file *file, struct vm_area_struct *vma)
{
unsigned long addr;
unsigned long size;
spin_lock(&flash_lock);
if (flash.read_base == flash.write_base) {
addr = flash.read_base;
size = flash.read_size;
} else {
if ((vma->vm_flags & VM_READ) &&
(vma->vm_flags & VM_WRITE)) {
spin_unlock(&flash_lock);
return -EINVAL;
}
if (vma->vm_flags & VM_READ) {
addr = flash.read_base;
size = flash.read_size;
} else if (vma->vm_flags & VM_WRITE) {
addr = flash.write_base;
size = flash.write_size;
} else {
spin_unlock(&flash_lock);
return -ENXIO;
}
}
spin_unlock(&flash_lock);
if ((vma->vm_pgoff << PAGE_SHIFT) > size)
return -ENXIO;
addr = vma->vm_pgoff + (addr >> PAGE_SHIFT);
if (vma->vm_end - (vma->vm_start + (vma->vm_pgoff << PAGE_SHIFT)) > size)
size = vma->vm_end - (vma->vm_start + (vma->vm_pgoff << PAGE_SHIFT));
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
if (io_remap_pfn_range(vma, vma->vm_start, addr, size, vma->vm_page_prot))
return -EAGAIN;
return 0;
}
static long long
flash_llseek(struct file *file, long long offset, int origin)
{
mutex_lock(&flash_mutex);
switch (origin) {
case 0:
file->f_pos = offset;
break;
case 1:
file->f_pos += offset;
if (file->f_pos > flash.read_size)
file->f_pos = flash.read_size;
break;
case 2:
file->f_pos = flash.read_size;
break;
default:
mutex_unlock(&flash_mutex);
return -EINVAL;
}
mutex_unlock(&flash_mutex);
return file->f_pos;
}
static ssize_t
flash_read(struct file * file, char __user * buf,
size_t count, loff_t *ppos)
{
loff_t p = *ppos;
int i;
if (count > flash.read_size - p)
count = flash.read_size - p;
for (i = 0; i < count; i++) {
u8 data = upa_readb(flash.read_base + p + i);
if (put_user(data, buf))
return -EFAULT;
buf++;
}
*ppos += count;
return count;
}
static int
flash_open(struct inode *inode, struct file *file)
{
mutex_lock(&flash_mutex);
if (test_and_set_bit(0, (void *)&flash.busy) != 0) {
mutex_unlock(&flash_mutex);
return -EBUSY;
}
mutex_unlock(&flash_mutex);
return 0;
}
static int
flash_release(struct inode *inode, struct file *file)
{
spin_lock(&flash_lock);
flash.busy = 0;
spin_unlock(&flash_lock);
return 0;
}
static const struct file_operations flash_fops = {
/* no write to the Flash, use mmap
* and play flash dependent tricks.
*/
.owner = THIS_MODULE,
.llseek = flash_llseek,
.read = flash_read,
.mmap = flash_mmap,
.open = flash_open,
.release = flash_release,
};
static struct miscdevice flash_dev = { FLASH_MINOR, "flash", &flash_fops };
static int flash_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct device_node *parent;
parent = dp->parent;
if (strcmp(parent->name, "sbus") &&
strcmp(parent->name, "sbi") &&
strcmp(parent->name, "ebus"))
return -ENODEV;
flash.read_base = op->resource[0].start;
flash.read_size = resource_size(&op->resource[0]);
if (op->resource[1].flags) {
flash.write_base = op->resource[1].start;
flash.write_size = resource_size(&op->resource[1]);
} else {
flash.write_base = op->resource[0].start;
flash.write_size = resource_size(&op->resource[0]);
}
flash.busy = 0;
printk(KERN_INFO "%s: OBP Flash, RD %lx[%lx] WR %lx[%lx]\n",
op->dev.of_node->full_name,
flash.read_base, flash.read_size,
flash.write_base, flash.write_size);
return misc_register(&flash_dev);
}
static int flash_remove(struct platform_device *op)
{
misc_deregister(&flash_dev);
return 0;
}
static const struct of_device_id flash_match[] = {
{
.name = "flashprom",
},
{},
};
MODULE_DEVICE_TABLE(of, flash_match);
static struct platform_driver flash_driver = {
.driver = {
.name = "flash",
.owner = THIS_MODULE,
.of_match_table = flash_match,
},
.probe = flash_probe,
.remove = flash_remove,
};
module_platform_driver(flash_driver);
MODULE_LICENSE("GPL");
| gpl-2.0 |
CyanogenMod/android_kernel_google_steelhead | arch/x86/kernel/smp.c | 2735 | 6992 | /*
* Intel SMP support routines.
*
* (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
* (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
* (c) 2002,2003 Andi Kleen, SuSE Labs.
*
* i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
*
* This code is released under the GNU General Public License version 2 or
* later.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/gfp.h>
#include <asm/mtrr.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/proto.h>
#include <asm/apic.h>
/*
* Some notes on x86 processor bugs affecting SMP operation:
*
* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
* The Linux implications for SMP are handled as follows:
*
* Pentium III / [Xeon]
* None of the E1AP-E3AP errata are visible to the user.
*
* E1AP. see PII A1AP
* E2AP. see PII A2AP
* E3AP. see PII A3AP
*
* Pentium II / [Xeon]
* None of the A1AP-A3AP errata are visible to the user.
*
* A1AP. see PPro 1AP
* A2AP. see PPro 2AP
* A3AP. see PPro 7AP
*
* Pentium Pro
* None of 1AP-9AP errata are visible to the normal user,
* except occasional delivery of 'spurious interrupt' as trap #15.
* This is very rare and a non-problem.
*
* 1AP. Linux maps APIC as non-cacheable
* 2AP. worked around in hardware
* 3AP. fixed in C0 and above steppings microcode update.
* Linux does not use excessive STARTUP_IPIs.
* 4AP. worked around in hardware
* 5AP. symmetric IO mode (normal Linux operation) not affected.
* 'noapic' mode has vector 0xf filled out properly.
* 6AP. 'noapic' mode might be affected - fixed in later steppings
* 7AP. We do not assume writes to the LVT deassering IRQs
* 8AP. We do not enable low power mode (deep sleep) during MP bootup
* 9AP. We do not use mixed mode
*
* Pentium
* There is a marginal case where REP MOVS on 100MHz SMP
* machines with B stepping processors can fail. XXX should provide
* an L1cache=Writethrough or L1cache=off option.
*
* B stepping CPUs may hang. There are hardware work arounds
* for this. We warn about it in case your board doesn't have the work
* arounds. Basically that's so I can tell anyone with a B stepping
* CPU and SMP problems "tough".
*
* Specific items [From Pentium Processor Specification Update]
*
* 1AP. Linux doesn't use remote read
* 2AP. Linux doesn't trust APIC errors
* 3AP. We work around this
* 4AP. Linux never generated 3 interrupts of the same priority
* to cause a lost local interrupt.
* 5AP. Remote read is never used
* 6AP. not affected - worked around in hardware
* 7AP. not affected - worked around in hardware
* 8AP. worked around in hardware - we get explicit CS errors if not
* 9AP. only 'noapic' mode affected. Might generate spurious
* interrupts, we log only the first one and count the
* rest silently.
* 10AP. not affected - worked around in hardware
* 11AP. Linux reads the APIC between writes to avoid this, as per
* the documentation. Make sure you preserve this as it affects
* the C stepping chips too.
* 12AP. not affected - worked around in hardware
* 13AP. not affected - worked around in hardware
* 14AP. we always deassert INIT during bootup
* 15AP. not affected - worked around in hardware
* 16AP. not affected - worked around in hardware
* 17AP. not affected - worked around in hardware
* 18AP. not affected - worked around in hardware
* 19AP. not affected - worked around in BIOS
*
* If this sounds worrying believe me these bugs are either ___RARE___,
* or are signal timing bugs worked around in hardware and there's
* about nothing of note with C stepping upwards.
*/
/*
* this function sends a 'reschedule' IPI to another CPU.
* it goes straight through and wastes no time serializing
* anything. Worst case is that we lose a reschedule ...
*/
static void native_smp_send_reschedule(int cpu)
{
if (unlikely(cpu_is_offline(cpu))) {
WARN_ON(1);
return;
}
apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
}
void native_send_call_func_single_ipi(int cpu)
{
apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
}
void native_send_call_func_ipi(const struct cpumask *mask)
{
cpumask_var_t allbutself;
if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
return;
}
cpumask_copy(allbutself, cpu_online_mask);
cpumask_clear_cpu(smp_processor_id(), allbutself);
if (cpumask_equal(mask, allbutself) &&
cpumask_equal(cpu_online_mask, cpu_callout_mask))
apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
else
apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
free_cpumask_var(allbutself);
}
/*
* this function calls the 'stop' function on all other CPUs in the system.
*/
asmlinkage void smp_reboot_interrupt(void)
{
ack_APIC_irq();
irq_enter();
stop_this_cpu(NULL);
irq_exit();
}
static void native_stop_other_cpus(int wait)
{
unsigned long flags;
unsigned long timeout;
if (reboot_force)
return;
/*
* Use an own vector here because smp_call_function
* does lots of things not suitable in a panic situation.
* On most systems we could also use an NMI here,
* but there are a few systems around where NMI
* is problematic so stay with an non NMI for now
* (this implies we cannot stop CPUs spinning with irq off
* currently)
*/
if (num_online_cpus() > 1) {
apic->send_IPI_allbutself(REBOOT_VECTOR);
/*
* Don't wait longer than a second if the caller
* didn't ask us to wait.
*/
timeout = USEC_PER_SEC;
while (num_online_cpus() > 1 && (wait || timeout--))
udelay(1);
}
local_irq_save(flags);
disable_local_APIC();
local_irq_restore(flags);
}
/*
* Reschedule call back.
*/
void smp_reschedule_interrupt(struct pt_regs *regs)
{
ack_APIC_irq();
inc_irq_stat(irq_resched_count);
scheduler_ipi();
/*
* KVM uses this interrupt to force a cpu out of guest mode
*/
}
void smp_call_function_interrupt(struct pt_regs *regs)
{
ack_APIC_irq();
irq_enter();
generic_smp_call_function_interrupt();
inc_irq_stat(irq_call_count);
irq_exit();
}
void smp_call_function_single_interrupt(struct pt_regs *regs)
{
ack_APIC_irq();
irq_enter();
generic_smp_call_function_single_interrupt();
inc_irq_stat(irq_call_count);
irq_exit();
}
struct smp_ops smp_ops = {
.smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
.smp_prepare_cpus = native_smp_prepare_cpus,
.smp_cpus_done = native_smp_cpus_done,
.stop_other_cpus = native_stop_other_cpus,
.smp_send_reschedule = native_smp_send_reschedule,
.cpu_up = native_cpu_up,
.cpu_die = native_cpu_die,
.cpu_disable = native_cpu_disable,
.play_dead = native_play_dead,
.send_call_func_ipi = native_send_call_func_ipi,
.send_call_func_single_ipi = native_send_call_func_single_ipi,
};
EXPORT_SYMBOL_GPL(smp_ops);
| gpl-2.0 |
tycoo/moto_x_kernel | drivers/usb/early/ehci-dbgp.c | 2991 | 26421 | /*
* Standalone EHCI usb debug driver
*
* Originally written by:
* Eric W. Biederman" <ebiederm@xmission.com> and
* Yinghai Lu <yhlu.kernel@gmail.com>
*
* Changes for early/late printk and HW errata:
* Jason Wessel <jason.wessel@windriver.com>
* Copyright (C) 2009 Wind River Systems, Inc.
*
*/
#include <linux/console.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/pci_regs.h>
#include <linux/pci_ids.h>
#include <linux/usb/ch9.h>
#include <linux/usb/ehci_def.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/kgdb.h>
#include <linux/kthread.h>
#include <asm/io.h>
#include <asm/pci-direct.h>
#include <asm/fixmap.h>
/* The code here is intended to talk directly to the EHCI debug port
* and does not require that you have any kind of USB host controller
* drivers or USB device drivers compiled into the kernel.
*
* If you make a change to anything in here, the following test cases
* need to pass where a USB debug device works in the following
* configurations.
*
* 1. boot args: earlyprintk=dbgp
* o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
* o kernel compiled with CONFIG_USB_EHCI_HCD=y
* 2. boot args: earlyprintk=dbgp,keep
* o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
* o kernel compiled with CONFIG_USB_EHCI_HCD=y
* 3. boot args: earlyprintk=dbgp console=ttyUSB0
* o kernel has CONFIG_USB_EHCI_HCD=y and
* CONFIG_USB_SERIAL_DEBUG=y
* 4. boot args: earlyprintk=vga,dbgp
* o kernel compiled with # CONFIG_USB_EHCI_HCD is not set
* o kernel compiled with CONFIG_USB_EHCI_HCD=y
*
* For the 4th configuration you can turn on or off the DBGP_DEBUG
* such that you can debug the dbgp device's driver code.
*/
static int dbgp_phys_port = 1;
static struct ehci_caps __iomem *ehci_caps;
static struct ehci_regs __iomem *ehci_regs;
static struct ehci_dbg_port __iomem *ehci_debug;
static int dbgp_not_safe; /* Cannot use debug device during ehci reset */
static unsigned int dbgp_endpoint_out;
static unsigned int dbgp_endpoint_in;
struct ehci_dev {
u32 bus;
u32 slot;
u32 func;
};
static struct ehci_dev ehci_dev;
#define USB_DEBUG_DEVNUM 127
#ifdef DBGP_DEBUG
#define dbgp_printk printk
static void dbgp_ehci_status(char *str)
{
if (!ehci_debug)
return;
dbgp_printk("dbgp: %s\n", str);
dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control));
dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command));
dbgp_printk(" ehci conf flg: %08x\n",
readl(&ehci_regs->configured_flag));
dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status));
dbgp_printk(" ehci portsc : %08x\n",
readl(&ehci_regs->port_status[dbgp_phys_port - 1]));
}
#else
static inline void dbgp_ehci_status(char *str) { }
static inline void dbgp_printk(const char *fmt, ...) { }
#endif
static inline u32 dbgp_len_update(u32 x, u32 len)
{
return (x & ~0x0f) | (len & 0x0f);
}
#ifdef CONFIG_KGDB
static struct kgdb_io kgdbdbgp_io_ops;
#define dbgp_kgdb_mode (dbg_io_ops == &kgdbdbgp_io_ops)
#else
#define dbgp_kgdb_mode (0)
#endif
/* Local version of HC_LENGTH macro as ehci struct is not available here */
#define EARLY_HC_LENGTH(p) (0x00ff & (p)) /* bits 7 : 0 */
/*
* USB Packet IDs (PIDs)
*/
/* token */
#define USB_PID_OUT 0xe1
#define USB_PID_IN 0x69
#define USB_PID_SOF 0xa5
#define USB_PID_SETUP 0x2d
/* handshake */
#define USB_PID_ACK 0xd2
#define USB_PID_NAK 0x5a
#define USB_PID_STALL 0x1e
#define USB_PID_NYET 0x96
/* data */
#define USB_PID_DATA0 0xc3
#define USB_PID_DATA1 0x4b
#define USB_PID_DATA2 0x87
#define USB_PID_MDATA 0x0f
/* Special */
#define USB_PID_PREAMBLE 0x3c
#define USB_PID_ERR 0x3c
#define USB_PID_SPLIT 0x78
#define USB_PID_PING 0xb4
#define USB_PID_UNDEF_0 0xf0
#define USB_PID_DATA_TOGGLE 0x88
#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
#define PCI_CAP_ID_EHCI_DEBUG 0xa
#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
#define HUB_SHORT_RESET_TIME 10
#define HUB_LONG_RESET_TIME 200
#define HUB_RESET_TIMEOUT 500
#define DBGP_MAX_PACKET 8
#define DBGP_TIMEOUT (250 * 1000)
#define DBGP_LOOPS 1000
static inline u32 dbgp_pid_write_update(u32 x, u32 tok)
{
static int data0 = USB_PID_DATA1;
data0 ^= USB_PID_DATA_TOGGLE;
return (x & 0xffff0000) | (data0 << 8) | (tok & 0xff);
}
static inline u32 dbgp_pid_read_update(u32 x, u32 tok)
{
return (x & 0xffff0000) | (USB_PID_DATA0 << 8) | (tok & 0xff);
}
static int dbgp_wait_until_complete(void)
{
u32 ctrl;
int loop = DBGP_TIMEOUT;
do {
ctrl = readl(&ehci_debug->control);
/* Stop when the transaction is finished */
if (ctrl & DBGP_DONE)
break;
udelay(1);
} while (--loop > 0);
if (!loop)
return -DBGP_TIMEOUT;
/*
* Now that we have observed the completed transaction,
* clear the done bit.
*/
writel(ctrl | DBGP_DONE, &ehci_debug->control);
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
}
static inline void dbgp_mdelay(int ms)
{
int i;
while (ms--) {
for (i = 0; i < 1000; i++)
outb(0x1, 0x80);
}
}
static void dbgp_breath(void)
{
/* Sleep to give the debug port a chance to breathe */
}
static int dbgp_wait_until_done(unsigned ctrl, int loop)
{
u32 pids, lpid;
int ret;
retry:
writel(ctrl | DBGP_GO, &ehci_debug->control);
ret = dbgp_wait_until_complete();
pids = readl(&ehci_debug->pids);
lpid = DBGP_PID_GET(pids);
if (ret < 0) {
/* A -DBGP_TIMEOUT failure here means the device has
* failed, perhaps because it was unplugged, in which
* case we do not want to hang the system so the dbgp
* will be marked as unsafe to use. EHCI reset is the
* only way to recover if you unplug the dbgp device.
*/
if (ret == -DBGP_TIMEOUT && !dbgp_not_safe)
dbgp_not_safe = 1;
if (ret == -DBGP_ERR_BAD && --loop > 0)
goto retry;
return ret;
}
/*
* If the port is getting full or it has dropped data
* start pacing ourselves, not necessary but it's friendly.
*/
if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
dbgp_breath();
/* If I get a NACK reissue the transmission */
if (lpid == USB_PID_NAK) {
if (--loop > 0)
goto retry;
}
return ret;
}
static inline void dbgp_set_data(const void *buf, int size)
{
const unsigned char *bytes = buf;
u32 lo, hi;
int i;
lo = hi = 0;
for (i = 0; i < 4 && i < size; i++)
lo |= bytes[i] << (8*i);
for (; i < 8 && i < size; i++)
hi |= bytes[i] << (8*(i - 4));
writel(lo, &ehci_debug->data03);
writel(hi, &ehci_debug->data47);
}
static inline void dbgp_get_data(void *buf, int size)
{
unsigned char *bytes = buf;
u32 lo, hi;
int i;
lo = readl(&ehci_debug->data03);
hi = readl(&ehci_debug->data47);
for (i = 0; i < 4 && i < size; i++)
bytes[i] = (lo >> (8*i)) & 0xff;
for (; i < 8 && i < size; i++)
bytes[i] = (hi >> (8*(i - 4))) & 0xff;
}
static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
const char *bytes, int size)
{
int ret;
u32 addr;
u32 pids, ctrl;
if (size > DBGP_MAX_PACKET)
return -1;
addr = DBGP_EPADDR(devnum, endpoint);
pids = readl(&ehci_debug->pids);
pids = dbgp_pid_write_update(pids, USB_PID_OUT);
ctrl = readl(&ehci_debug->control);
ctrl = dbgp_len_update(ctrl, size);
ctrl |= DBGP_OUT;
ctrl |= DBGP_GO;
dbgp_set_data(bytes, size);
writel(addr, &ehci_debug->address);
writel(pids, &ehci_debug->pids);
ret = dbgp_wait_until_done(ctrl, DBGP_LOOPS);
return ret;
}
static int dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
int size, int loops)
{
u32 pids, addr, ctrl;
int ret;
if (size > DBGP_MAX_PACKET)
return -1;
addr = DBGP_EPADDR(devnum, endpoint);
pids = readl(&ehci_debug->pids);
pids = dbgp_pid_read_update(pids, USB_PID_IN);
ctrl = readl(&ehci_debug->control);
ctrl = dbgp_len_update(ctrl, size);
ctrl &= ~DBGP_OUT;
ctrl |= DBGP_GO;
writel(addr, &ehci_debug->address);
writel(pids, &ehci_debug->pids);
ret = dbgp_wait_until_done(ctrl, loops);
if (ret < 0)
return ret;
if (size > ret)
size = ret;
dbgp_get_data(data, size);
return ret;
}
static int dbgp_control_msg(unsigned devnum, int requesttype,
int request, int value, int index, void *data, int size)
{
u32 pids, addr, ctrl;
struct usb_ctrlrequest req;
int read;
int ret;
read = (requesttype & USB_DIR_IN) != 0;
if (size > (read ? DBGP_MAX_PACKET:0))
return -1;
/* Compute the control message */
req.bRequestType = requesttype;
req.bRequest = request;
req.wValue = cpu_to_le16(value);
req.wIndex = cpu_to_le16(index);
req.wLength = cpu_to_le16(size);
pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
addr = DBGP_EPADDR(devnum, 0);
ctrl = readl(&ehci_debug->control);
ctrl = dbgp_len_update(ctrl, sizeof(req));
ctrl |= DBGP_OUT;
ctrl |= DBGP_GO;
/* Send the setup message */
dbgp_set_data(&req, sizeof(req));
writel(addr, &ehci_debug->address);
writel(pids, &ehci_debug->pids);
ret = dbgp_wait_until_done(ctrl, DBGP_LOOPS);
if (ret < 0)
return ret;
/* Read the result */
return dbgp_bulk_read(devnum, 0, data, size, DBGP_LOOPS);
}
/* Find a PCI capability */
static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
{
u8 pos;
int bytes;
if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
PCI_STATUS_CAP_LIST))
return 0;
pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
u8 id;
pos &= ~3;
id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
if (id == 0xff)
break;
if (id == cap)
return pos;
pos = read_pci_config_byte(num, slot, func,
pos+PCI_CAP_LIST_NEXT);
}
return 0;
}
static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
{
u32 class;
class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
return 0;
return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
}
static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
{
u32 bus, slot, func;
for (bus = 0; bus < 256; bus++) {
for (slot = 0; slot < 32; slot++) {
for (func = 0; func < 8; func++) {
unsigned cap;
cap = __find_dbgp(bus, slot, func);
if (!cap)
continue;
if (ehci_num-- != 0)
continue;
*rbus = bus;
*rslot = slot;
*rfunc = func;
return cap;
}
}
}
return 0;
}
static int dbgp_ehci_startup(void)
{
u32 ctrl, cmd, status;
int loop;
/* Claim ownership, but do not enable yet */
ctrl = readl(&ehci_debug->control);
ctrl |= DBGP_OWNER;
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
writel(ctrl, &ehci_debug->control);
udelay(1);
dbgp_ehci_status("EHCI startup");
/* Start the ehci running */
cmd = readl(&ehci_regs->command);
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
cmd |= CMD_RUN;
writel(cmd, &ehci_regs->command);
/* Ensure everything is routed to the EHCI */
writel(FLAG_CF, &ehci_regs->configured_flag);
/* Wait until the controller is no longer halted */
loop = 1000;
do {
status = readl(&ehci_regs->status);
if (!(status & STS_HALT))
break;
udelay(1);
} while (--loop > 0);
if (!loop) {
dbgp_printk("ehci can not be started\n");
return -ENODEV;
}
dbgp_printk("ehci started\n");
return 0;
}
static int dbgp_ehci_controller_reset(void)
{
int loop = 250 * 1000;
u32 cmd;
/* Reset the EHCI controller */
cmd = readl(&ehci_regs->command);
cmd |= CMD_RESET;
writel(cmd, &ehci_regs->command);
do {
cmd = readl(&ehci_regs->command);
} while ((cmd & CMD_RESET) && (--loop > 0));
if (!loop) {
dbgp_printk("can not reset ehci\n");
return -1;
}
dbgp_ehci_status("ehci reset done");
return 0;
}
static int ehci_wait_for_port(int port);
/* Return 0 on success
* Return -ENODEV for any general failure
* Return -EIO if wait for port fails
*/
int dbgp_external_startup(void)
{
int devnum;
struct usb_debug_descriptor dbgp_desc;
int ret;
u32 ctrl, portsc, cmd;
int dbg_port = dbgp_phys_port;
int tries = 3;
int reset_port_tries = 1;
int try_hard_once = 1;
try_port_reset_again:
ret = dbgp_ehci_startup();
if (ret)
return ret;
/* Wait for a device to show up in the debug port */
ret = ehci_wait_for_port(dbg_port);
if (ret < 0) {
portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
if (!(portsc & PORT_CONNECT) && try_hard_once) {
/* Last ditch effort to try to force enable
* the debug device by using the packet test
* ehci command to try and wake it up. */
try_hard_once = 0;
cmd = readl(&ehci_regs->command);
cmd &= ~CMD_RUN;
writel(cmd, &ehci_regs->command);
portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
portsc |= PORT_TEST_PKT;
writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
dbgp_ehci_status("Trying to force debug port online");
mdelay(50);
dbgp_ehci_controller_reset();
goto try_port_reset_again;
} else if (reset_port_tries--) {
goto try_port_reset_again;
}
dbgp_printk("No device found in debug port\n");
return -EIO;
}
dbgp_ehci_status("wait for port done");
/* Enable the debug port */
ctrl = readl(&ehci_debug->control);
ctrl |= DBGP_CLAIM;
writel(ctrl, &ehci_debug->control);
ctrl = readl(&ehci_debug->control);
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
dbgp_printk("No device in debug port\n");
writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
return -ENODEV;
}
dbgp_ehci_status("debug ported enabled");
/* Completely transfer the debug device to the debug controller */
portsc = readl(&ehci_regs->port_status[dbg_port - 1]);
portsc &= ~PORT_PE;
writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
dbgp_mdelay(100);
try_again:
/* Find the debug device and make it device number 127 */
for (devnum = 0; devnum <= 127; devnum++) {
ret = dbgp_control_msg(devnum,
USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
&dbgp_desc, sizeof(dbgp_desc));
if (ret > 0)
break;
}
if (devnum > 127) {
dbgp_printk("Could not find attached debug device\n");
goto err;
}
if (ret < 0) {
dbgp_printk("Attached device is not a debug device\n");
goto err;
}
dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint;
/* Move the device to 127 if it isn't already there */
if (devnum != USB_DEBUG_DEVNUM) {
ret = dbgp_control_msg(devnum,
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
if (ret < 0) {
dbgp_printk("Could not move attached device to %d\n",
USB_DEBUG_DEVNUM);
goto err;
}
devnum = USB_DEBUG_DEVNUM;
dbgp_printk("debug device renamed to 127\n");
}
/* Enable the debug interface */
ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
if (ret < 0) {
dbgp_printk(" Could not enable the debug device\n");
goto err;
}
dbgp_printk("debug interface enabled\n");
/* Perform a small write to get the even/odd data state in sync
*/
ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
if (ret < 0) {
dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
goto err;
}
dbgp_printk("small write done\n");
dbgp_not_safe = 0;
return 0;
err:
if (tries--)
goto try_again;
return -ENODEV;
}
EXPORT_SYMBOL_GPL(dbgp_external_startup);
static int ehci_reset_port(int port)
{
u32 portsc;
u32 delay_time, delay;
int loop;
dbgp_ehci_status("reset port");
/* Reset the usb debug port */
portsc = readl(&ehci_regs->port_status[port - 1]);
portsc &= ~PORT_PE;
portsc |= PORT_RESET;
writel(portsc, &ehci_regs->port_status[port - 1]);
delay = HUB_ROOT_RESET_TIME;
for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
delay_time += delay) {
dbgp_mdelay(delay);
portsc = readl(&ehci_regs->port_status[port - 1]);
if (!(portsc & PORT_RESET))
break;
}
if (portsc & PORT_RESET) {
/* force reset to complete */
loop = 100 * 1000;
writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
&ehci_regs->port_status[port - 1]);
do {
udelay(1);
portsc = readl(&ehci_regs->port_status[port-1]);
} while ((portsc & PORT_RESET) && (--loop > 0));
}
/* Device went away? */
if (!(portsc & PORT_CONNECT))
return -ENOTCONN;
/* bomb out completely if something weird happened */
if ((portsc & PORT_CSC))
return -EINVAL;
/* If we've finished resetting, then break out of the loop */
if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
return 0;
return -EBUSY;
}
static int ehci_wait_for_port(int port)
{
u32 status;
int ret, reps;
for (reps = 0; reps < 300; reps++) {
status = readl(&ehci_regs->status);
if (status & STS_PCD)
break;
dbgp_mdelay(1);
}
ret = ehci_reset_port(port);
if (ret == 0)
return 0;
return -ENOTCONN;
}
typedef void (*set_debug_port_t)(int port);
static void __init default_set_debug_port(int port)
{
}
static set_debug_port_t __initdata set_debug_port = default_set_debug_port;
static void __init nvidia_set_debug_port(int port)
{
u32 dword;
dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
0x74);
dword &= ~(0x0f<<12);
dword |= ((port & 0x0f)<<12);
write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
dword);
dbgp_printk("set debug port to %d\n", port);
}
static void __init detect_set_debug_port(void)
{
u32 vendorid;
vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
0x00);
if ((vendorid & 0xffff) == 0x10de) {
dbgp_printk("using nvidia set_debug_port\n");
set_debug_port = nvidia_set_debug_port;
}
}
/* The code in early_ehci_bios_handoff() is derived from the usb pci
* quirk initialization, but altered so as to use the early PCI
* routines. */
#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
static void __init early_ehci_bios_handoff(void)
{
u32 hcc_params = readl(&ehci_caps->hcc_params);
int offset = (hcc_params >> 8) & 0xff;
u32 cap;
int msec;
if (!offset)
return;
cap = read_pci_config(ehci_dev.bus, ehci_dev.slot,
ehci_dev.func, offset);
dbgp_printk("dbgp: ehci BIOS state %08x\n", cap);
if ((cap & 0xff) == 1 && (cap & EHCI_USBLEGSUP_BIOS)) {
dbgp_printk("dbgp: BIOS handoff\n");
write_pci_config_byte(ehci_dev.bus, ehci_dev.slot,
ehci_dev.func, offset + 3, 1);
}
/* if boot firmware now owns EHCI, spin till it hands it over. */
msec = 1000;
while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
mdelay(10);
msec -= 10;
cap = read_pci_config(ehci_dev.bus, ehci_dev.slot,
ehci_dev.func, offset);
}
if (cap & EHCI_USBLEGSUP_BIOS) {
/* well, possibly buggy BIOS... try to shut it down,
* and hope nothing goes too wrong */
dbgp_printk("dbgp: BIOS handoff failed: %08x\n", cap);
write_pci_config_byte(ehci_dev.bus, ehci_dev.slot,
ehci_dev.func, offset + 2, 0);
}
/* just in case, always disable EHCI SMIs */
write_pci_config_byte(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
offset + EHCI_USBLEGCTLSTS, 0);
}
static int __init ehci_setup(void)
{
u32 ctrl, portsc, hcs_params;
u32 debug_port, new_debug_port = 0, n_ports;
int ret, i;
int port_map_tried;
int playtimes = 3;
early_ehci_bios_handoff();
try_next_time:
port_map_tried = 0;
try_next_port:
hcs_params = readl(&ehci_caps->hcs_params);
debug_port = HCS_DEBUG_PORT(hcs_params);
dbgp_phys_port = debug_port;
n_ports = HCS_N_PORTS(hcs_params);
dbgp_printk("debug_port: %d\n", debug_port);
dbgp_printk("n_ports: %d\n", n_ports);
dbgp_ehci_status("");
for (i = 1; i <= n_ports; i++) {
portsc = readl(&ehci_regs->port_status[i-1]);
dbgp_printk("portstatus%d: %08x\n", i, portsc);
}
if (port_map_tried && (new_debug_port != debug_port)) {
if (--playtimes) {
set_debug_port(new_debug_port);
goto try_next_time;
}
return -1;
}
/* Only reset the controller if it is not already in the
* configured state */
if (!(readl(&ehci_regs->configured_flag) & FLAG_CF)) {
if (dbgp_ehci_controller_reset() != 0)
return -1;
} else {
dbgp_ehci_status("ehci skip - already configured");
}
ret = dbgp_external_startup();
if (ret == -EIO)
goto next_debug_port;
if (ret < 0) {
/* Things didn't work so remove my claim */
ctrl = readl(&ehci_debug->control);
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
writel(ctrl, &ehci_debug->control);
return -1;
}
return 0;
next_debug_port:
port_map_tried |= (1<<(debug_port - 1));
new_debug_port = ((debug_port-1+1)%n_ports) + 1;
if (port_map_tried != ((1<<n_ports) - 1)) {
set_debug_port(new_debug_port);
goto try_next_port;
}
if (--playtimes) {
set_debug_port(new_debug_port);
goto try_next_time;
}
return -1;
}
int __init early_dbgp_init(char *s)
{
u32 debug_port, bar, offset;
u32 bus, slot, func, cap;
void __iomem *ehci_bar;
u32 dbgp_num;
u32 bar_val;
char *e;
int ret;
u8 byte;
if (!early_pci_allowed())
return -1;
dbgp_num = 0;
if (*s)
dbgp_num = simple_strtoul(s, &e, 10);
dbgp_printk("dbgp_num: %d\n", dbgp_num);
cap = find_dbgp(dbgp_num, &bus, &slot, &func);
if (!cap)
return -1;
dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
func);
debug_port = read_pci_config(bus, slot, func, cap);
bar = (debug_port >> 29) & 0x7;
bar = (bar * 4) + 0xc;
offset = (debug_port >> 16) & 0xfff;
dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
if (bar != PCI_BASE_ADDRESS_0) {
dbgp_printk("only debug ports on bar 1 handled.\n");
return -1;
}
bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
dbgp_printk("only simple 32bit mmio bars supported\n");
return -1;
}
/* double check if the mem space is enabled */
byte = read_pci_config_byte(bus, slot, func, 0x04);
if (!(byte & 0x2)) {
byte |= 0x02;
write_pci_config_byte(bus, slot, func, 0x04, byte);
dbgp_printk("mmio for ehci enabled\n");
}
/*
* FIXME I don't have the bar size so just guess PAGE_SIZE is more
* than enough. 1K is the biggest I have seen.
*/
set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
ehci_bar += bar_val & ~PAGE_MASK;
dbgp_printk("ehci_bar: %p\n", ehci_bar);
ehci_caps = ehci_bar;
ehci_regs = ehci_bar + EARLY_HC_LENGTH(readl(&ehci_caps->hc_capbase));
ehci_debug = ehci_bar + offset;
ehci_dev.bus = bus;
ehci_dev.slot = slot;
ehci_dev.func = func;
detect_set_debug_port();
ret = ehci_setup();
if (ret < 0) {
dbgp_printk("ehci_setup failed\n");
ehci_debug = NULL;
return -1;
}
dbgp_ehci_status("early_init_complete");
return 0;
}
static void early_dbgp_write(struct console *con, const char *str, u32 n)
{
int chunk, ret;
char buf[DBGP_MAX_PACKET];
int use_cr = 0;
u32 cmd, ctrl;
int reset_run = 0;
if (!ehci_debug || dbgp_not_safe)
return;
cmd = readl(&ehci_regs->command);
if (unlikely(!(cmd & CMD_RUN))) {
/* If the ehci controller is not in the run state do extended
* checks to see if the acpi or some other initialization also
* reset the ehci debug port */
ctrl = readl(&ehci_debug->control);
if (!(ctrl & DBGP_ENABLED)) {
dbgp_not_safe = 1;
dbgp_external_startup();
} else {
cmd |= CMD_RUN;
writel(cmd, &ehci_regs->command);
reset_run = 1;
}
}
while (n > 0) {
for (chunk = 0; chunk < DBGP_MAX_PACKET && n > 0;
str++, chunk++, n--) {
if (!use_cr && *str == '\n') {
use_cr = 1;
buf[chunk] = '\r';
str--;
n++;
continue;
}
if (use_cr)
use_cr = 0;
buf[chunk] = *str;
}
if (chunk > 0) {
ret = dbgp_bulk_write(USB_DEBUG_DEVNUM,
dbgp_endpoint_out, buf, chunk);
}
}
if (unlikely(reset_run)) {
cmd = readl(&ehci_regs->command);
cmd &= ~CMD_RUN;
writel(cmd, &ehci_regs->command);
}
}
struct console early_dbgp_console = {
.name = "earlydbg",
.write = early_dbgp_write,
.flags = CON_PRINTBUFFER,
.index = -1,
};
int dbgp_reset_prep(void)
{
u32 ctrl;
dbgp_not_safe = 1;
if (!ehci_debug)
return 0;
if ((early_dbgp_console.index != -1 &&
!(early_dbgp_console.flags & CON_BOOT)) ||
dbgp_kgdb_mode)
return 1;
/* This means the console is not initialized, or should get
* shutdown so as to allow for reuse of the usb device, which
* means it is time to shutdown the usb debug port. */
ctrl = readl(&ehci_debug->control);
if (ctrl & DBGP_ENABLED) {
ctrl &= ~(DBGP_CLAIM);
writel(ctrl, &ehci_debug->control);
}
return 0;
}
EXPORT_SYMBOL_GPL(dbgp_reset_prep);
#ifdef CONFIG_KGDB
static char kgdbdbgp_buf[DBGP_MAX_PACKET];
static int kgdbdbgp_buf_sz;
static int kgdbdbgp_buf_idx;
static int kgdbdbgp_loop_cnt = DBGP_LOOPS;
static int kgdbdbgp_read_char(void)
{
int ret;
if (kgdbdbgp_buf_idx < kgdbdbgp_buf_sz) {
char ch = kgdbdbgp_buf[kgdbdbgp_buf_idx++];
return ch;
}
ret = dbgp_bulk_read(USB_DEBUG_DEVNUM, dbgp_endpoint_in,
&kgdbdbgp_buf, DBGP_MAX_PACKET,
kgdbdbgp_loop_cnt);
if (ret <= 0)
return NO_POLL_CHAR;
kgdbdbgp_buf_sz = ret;
kgdbdbgp_buf_idx = 1;
return kgdbdbgp_buf[0];
}
static void kgdbdbgp_write_char(u8 chr)
{
early_dbgp_write(NULL, &chr, 1);
}
static struct kgdb_io kgdbdbgp_io_ops = {
.name = "kgdbdbgp",
.read_char = kgdbdbgp_read_char,
.write_char = kgdbdbgp_write_char,
};
static int kgdbdbgp_wait_time;
static int __init kgdbdbgp_parse_config(char *str)
{
char *ptr;
if (!ehci_debug) {
if (early_dbgp_init(str))
return -1;
}
ptr = strchr(str, ',');
if (ptr) {
ptr++;
kgdbdbgp_wait_time = simple_strtoul(ptr, &ptr, 10);
}
kgdb_register_io_module(&kgdbdbgp_io_ops);
kgdbdbgp_io_ops.is_console = early_dbgp_console.index != -1;
return 0;
}
early_param("kgdbdbgp", kgdbdbgp_parse_config);
static int kgdbdbgp_reader_thread(void *ptr)
{
int ret;
while (readl(&ehci_debug->control) & DBGP_ENABLED) {
kgdbdbgp_loop_cnt = 1;
ret = kgdbdbgp_read_char();
kgdbdbgp_loop_cnt = DBGP_LOOPS;
if (ret != NO_POLL_CHAR) {
if (ret == 0x3 || ret == '$') {
if (ret == '$')
kgdbdbgp_buf_idx--;
kgdb_breakpoint();
}
continue;
}
schedule_timeout_interruptible(kgdbdbgp_wait_time * HZ);
}
return 0;
}
static int __init kgdbdbgp_start_thread(void)
{
if (dbgp_kgdb_mode && kgdbdbgp_wait_time)
kthread_run(kgdbdbgp_reader_thread, NULL, "%s", "dbgp");
return 0;
}
module_init(kgdbdbgp_start_thread);
#endif /* CONFIG_KGDB */
| gpl-2.0 |
Split-Screen/android_kernel_asus_grouper | arch/x86/xen/pci-swiotlb-xen.c | 2991 | 1836 | /* Glue code to lib/swiotlb-xen.c */
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <xen/swiotlb-xen.h>
#include <asm/xen/hypervisor.h>
#include <xen/xen.h>
#include <asm/iommu_table.h>
int xen_swiotlb __read_mostly;
static struct dma_map_ops xen_swiotlb_dma_ops = {
.mapping_error = xen_swiotlb_dma_mapping_error,
.alloc_coherent = xen_swiotlb_alloc_coherent,
.free_coherent = xen_swiotlb_free_coherent,
.sync_single_for_cpu = xen_swiotlb_sync_single_for_cpu,
.sync_single_for_device = xen_swiotlb_sync_single_for_device,
.sync_sg_for_cpu = xen_swiotlb_sync_sg_for_cpu,
.sync_sg_for_device = xen_swiotlb_sync_sg_for_device,
.map_sg = xen_swiotlb_map_sg_attrs,
.unmap_sg = xen_swiotlb_unmap_sg_attrs,
.map_page = xen_swiotlb_map_page,
.unmap_page = xen_swiotlb_unmap_page,
.dma_supported = xen_swiotlb_dma_supported,
};
/*
* pci_xen_swiotlb_detect - set xen_swiotlb to 1 if necessary
*
* This returns non-zero if we are forced to use xen_swiotlb (by the boot
* option).
*/
int __init pci_xen_swiotlb_detect(void)
{
/* If running as PV guest, either iommu=soft, or swiotlb=force will
* activate this IOMMU. If running as PV privileged, activate it
* irregardless.
*/
if ((xen_initial_domain() || swiotlb || swiotlb_force) &&
(xen_pv_domain()))
xen_swiotlb = 1;
/* If we are running under Xen, we MUST disable the native SWIOTLB.
* Don't worry about swiotlb_force flag activating the native, as
* the 'swiotlb' flag is the only one turning it on. */
if (xen_pv_domain())
swiotlb = 0;
return xen_swiotlb;
}
void __init pci_xen_swiotlb_init(void)
{
if (xen_swiotlb) {
xen_swiotlb_init(1);
dma_ops = &xen_swiotlb_dma_ops;
/* Make sure ACS will be enabled */
pci_request_acs();
}
}
IOMMU_INIT_FINISH(pci_xen_swiotlb_detect,
0,
pci_xen_swiotlb_init,
0);
| gpl-2.0 |
sameerkhan07/furnace_kernel_motorola_falcon | drivers/media/video/v4l2-common.c | 4271 | 18941 | /*
* Video for Linux Two
*
* A generic video device interface for the LINUX operating system
* using a set of device structures/vectors for low level operations.
*
* This file replaces the videodev.c file that comes with the
* regular kernel distribution.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Author: Bill Dirks <bill@thedirks.org>
* based on code by Alan Cox, <alan@cymru.net>
*
*/
/*
* Video capture interface for Linux
*
* A generic video device interface for the LINUX operating system
* using a set of device structures/vectors for low level operations.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Author: Alan Cox, <alan@lxorguk.ukuu.org.uk>
*
* Fixes:
*/
/*
* Video4linux 1/2 integration by Justin Schoeman
* <justin@suntiger.ee.up.ac.za>
* 2.4 PROCFS support ported from 2.4 kernels by
* Iñaki García Etxebarria <garetxe@euskalnet.net>
* Makefile fix by "W. Michael Petullo" <mike@flyn.org>
* 2.4 devfs support ported from 2.4 kernels by
* Dan Merillat <dan@merillat.org>
* Added Gerd Knorrs v4l1 enhancements (Justin Schoeman)
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#if defined(CONFIG_SPI)
#include <linux/spi/spi.h>
#endif
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-chip-ident.h>
#include <linux/videodev2.h>
MODULE_AUTHOR("Bill Dirks, Justin Schoeman, Gerd Knorr");
MODULE_DESCRIPTION("misc helper functions for v4l2 device drivers");
MODULE_LICENSE("GPL");
/*
*
* V 4 L 2 D R I V E R H E L P E R A P I
*
*/
/*
* Video Standard Operations (contributed by Michael Schimek)
*/
/* Helper functions for control handling */
/* Check for correctness of the ctrl's value based on the data from
struct v4l2_queryctrl and the available menu items. Note that
menu_items may be NULL, in that case it is ignored. */
int v4l2_ctrl_check(struct v4l2_ext_control *ctrl, struct v4l2_queryctrl *qctrl,
const char * const *menu_items)
{
if (qctrl->flags & V4L2_CTRL_FLAG_DISABLED)
return -EINVAL;
if (qctrl->flags & V4L2_CTRL_FLAG_GRABBED)
return -EBUSY;
if (qctrl->type == V4L2_CTRL_TYPE_STRING)
return 0;
if (qctrl->type == V4L2_CTRL_TYPE_BUTTON ||
qctrl->type == V4L2_CTRL_TYPE_INTEGER64 ||
qctrl->type == V4L2_CTRL_TYPE_CTRL_CLASS)
return 0;
if (ctrl->value < qctrl->minimum || ctrl->value > qctrl->maximum)
return -ERANGE;
if (qctrl->type == V4L2_CTRL_TYPE_MENU && menu_items != NULL) {
if (menu_items[ctrl->value] == NULL ||
menu_items[ctrl->value][0] == '\0')
return -EINVAL;
}
if (qctrl->type == V4L2_CTRL_TYPE_BITMASK &&
(ctrl->value & ~qctrl->maximum))
return -ERANGE;
return 0;
}
EXPORT_SYMBOL(v4l2_ctrl_check);
/* Fill in a struct v4l2_queryctrl */
int v4l2_ctrl_query_fill(struct v4l2_queryctrl *qctrl, s32 min, s32 max, s32 step, s32 def)
{
const char *name;
v4l2_ctrl_fill(qctrl->id, &name, &qctrl->type,
&min, &max, &step, &def, &qctrl->flags);
if (name == NULL)
return -EINVAL;
qctrl->minimum = min;
qctrl->maximum = max;
qctrl->step = step;
qctrl->default_value = def;
qctrl->reserved[0] = qctrl->reserved[1] = 0;
strlcpy(qctrl->name, name, sizeof(qctrl->name));
return 0;
}
EXPORT_SYMBOL(v4l2_ctrl_query_fill);
/* Fill in a struct v4l2_querymenu based on the struct v4l2_queryctrl and
the menu. The qctrl pointer may be NULL, in which case it is ignored.
If menu_items is NULL, then the menu items are retrieved using
v4l2_ctrl_get_menu. */
int v4l2_ctrl_query_menu(struct v4l2_querymenu *qmenu, struct v4l2_queryctrl *qctrl,
const char * const *menu_items)
{
int i;
qmenu->reserved = 0;
if (menu_items == NULL)
menu_items = v4l2_ctrl_get_menu(qmenu->id);
if (menu_items == NULL ||
(qctrl && (qmenu->index < qctrl->minimum || qmenu->index > qctrl->maximum)))
return -EINVAL;
for (i = 0; i < qmenu->index && menu_items[i]; i++) ;
if (menu_items[i] == NULL || menu_items[i][0] == '\0')
return -EINVAL;
strlcpy(qmenu->name, menu_items[qmenu->index], sizeof(qmenu->name));
return 0;
}
EXPORT_SYMBOL(v4l2_ctrl_query_menu);
/* Fill in a struct v4l2_querymenu based on the specified array of valid
menu items (terminated by V4L2_CTRL_MENU_IDS_END).
Use this if there are 'holes' in the list of valid menu items. */
int v4l2_ctrl_query_menu_valid_items(struct v4l2_querymenu *qmenu, const u32 *ids)
{
const char * const *menu_items = v4l2_ctrl_get_menu(qmenu->id);
qmenu->reserved = 0;
if (menu_items == NULL || ids == NULL)
return -EINVAL;
while (*ids != V4L2_CTRL_MENU_IDS_END) {
if (*ids++ == qmenu->index) {
strlcpy(qmenu->name, menu_items[qmenu->index],
sizeof(qmenu->name));
return 0;
}
}
return -EINVAL;
}
EXPORT_SYMBOL(v4l2_ctrl_query_menu_valid_items);
/* ctrl_classes points to an array of u32 pointers, the last element is
a NULL pointer. Each u32 array is a 0-terminated array of control IDs.
Each array must be sorted low to high and belong to the same control
class. The array of u32 pointers must also be sorted, from low class IDs
to high class IDs.
This function returns the first ID that follows after the given ID.
When no more controls are available 0 is returned. */
u32 v4l2_ctrl_next(const u32 * const * ctrl_classes, u32 id)
{
u32 ctrl_class = V4L2_CTRL_ID2CLASS(id);
const u32 *pctrl;
if (ctrl_classes == NULL)
return 0;
/* if no query is desired, then check if the ID is part of ctrl_classes */
if ((id & V4L2_CTRL_FLAG_NEXT_CTRL) == 0) {
/* find class */
while (*ctrl_classes && V4L2_CTRL_ID2CLASS(**ctrl_classes) != ctrl_class)
ctrl_classes++;
if (*ctrl_classes == NULL)
return 0;
pctrl = *ctrl_classes;
/* find control ID */
while (*pctrl && *pctrl != id) pctrl++;
return *pctrl ? id : 0;
}
id &= V4L2_CTRL_ID_MASK;
id++; /* select next control */
/* find first class that matches (or is greater than) the class of
the ID */
while (*ctrl_classes && V4L2_CTRL_ID2CLASS(**ctrl_classes) < ctrl_class)
ctrl_classes++;
/* no more classes */
if (*ctrl_classes == NULL)
return 0;
pctrl = *ctrl_classes;
/* find first ctrl within the class that is >= ID */
while (*pctrl && *pctrl < id) pctrl++;
if (*pctrl)
return *pctrl;
/* we are at the end of the controls of the current class. */
/* continue with next class if available */
ctrl_classes++;
if (*ctrl_classes == NULL)
return 0;
return **ctrl_classes;
}
EXPORT_SYMBOL(v4l2_ctrl_next);
int v4l2_chip_match_host(const struct v4l2_dbg_match *match)
{
switch (match->type) {
case V4L2_CHIP_MATCH_HOST:
return match->addr == 0;
default:
return 0;
}
}
EXPORT_SYMBOL(v4l2_chip_match_host);
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
int v4l2_chip_match_i2c_client(struct i2c_client *c, const struct v4l2_dbg_match *match)
{
int len;
if (c == NULL || match == NULL)
return 0;
switch (match->type) {
case V4L2_CHIP_MATCH_I2C_DRIVER:
if (c->driver == NULL || c->driver->driver.name == NULL)
return 0;
len = strlen(c->driver->driver.name);
/* legacy drivers have a ' suffix, don't try to match that */
if (len && c->driver->driver.name[len - 1] == '\'')
len--;
return len && !strncmp(c->driver->driver.name, match->name, len);
case V4L2_CHIP_MATCH_I2C_ADDR:
return c->addr == match->addr;
default:
return 0;
}
}
EXPORT_SYMBOL(v4l2_chip_match_i2c_client);
int v4l2_chip_ident_i2c_client(struct i2c_client *c, struct v4l2_dbg_chip_ident *chip,
u32 ident, u32 revision)
{
if (!v4l2_chip_match_i2c_client(c, &chip->match))
return 0;
if (chip->ident == V4L2_IDENT_NONE) {
chip->ident = ident;
chip->revision = revision;
}
else {
chip->ident = V4L2_IDENT_AMBIGUOUS;
chip->revision = 0;
}
return 0;
}
EXPORT_SYMBOL(v4l2_chip_ident_i2c_client);
/* ----------------------------------------------------------------- */
/* I2C Helper functions */
void v4l2_i2c_subdev_init(struct v4l2_subdev *sd, struct i2c_client *client,
const struct v4l2_subdev_ops *ops)
{
v4l2_subdev_init(sd, ops);
sd->flags |= V4L2_SUBDEV_FL_IS_I2C;
/* the owner is the same as the i2c_client's driver owner */
sd->owner = client->driver->driver.owner;
/* i2c_client and v4l2_subdev point to one another */
v4l2_set_subdevdata(sd, client);
i2c_set_clientdata(client, sd);
/* initialize name */
snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
client->driver->driver.name, i2c_adapter_id(client->adapter),
client->addr);
}
EXPORT_SYMBOL_GPL(v4l2_i2c_subdev_init);
/* Load an i2c sub-device. */
struct v4l2_subdev *v4l2_i2c_new_subdev_board(struct v4l2_device *v4l2_dev,
struct i2c_adapter *adapter, struct i2c_board_info *info,
const unsigned short *probe_addrs)
{
struct v4l2_subdev *sd = NULL;
struct i2c_client *client;
BUG_ON(!v4l2_dev);
request_module(I2C_MODULE_PREFIX "%s", info->type);
/* Create the i2c client */
if (info->addr == 0 && probe_addrs)
client = i2c_new_probed_device(adapter, info, probe_addrs,
NULL);
else
client = i2c_new_device(adapter, info);
/* Note: by loading the module first we are certain that c->driver
will be set if the driver was found. If the module was not loaded
first, then the i2c core tries to delay-load the module for us,
and then c->driver is still NULL until the module is finally
loaded. This delay-load mechanism doesn't work if other drivers
want to use the i2c device, so explicitly loading the module
is the best alternative. */
if (client == NULL || client->driver == NULL)
goto error;
/* Lock the module so we can safely get the v4l2_subdev pointer */
if (!try_module_get(client->driver->driver.owner))
goto error;
sd = i2c_get_clientdata(client);
/* Register with the v4l2_device which increases the module's
use count as well. */
if (v4l2_device_register_subdev(v4l2_dev, sd))
sd = NULL;
/* Decrease the module use count to match the first try_module_get. */
module_put(client->driver->driver.owner);
error:
/* If we have a client but no subdev, then something went wrong and
we must unregister the client. */
if (client && sd == NULL)
i2c_unregister_device(client);
return sd;
}
EXPORT_SYMBOL_GPL(v4l2_i2c_new_subdev_board);
struct v4l2_subdev *v4l2_i2c_new_subdev(struct v4l2_device *v4l2_dev,
struct i2c_adapter *adapter, const char *client_type,
u8 addr, const unsigned short *probe_addrs)
{
struct i2c_board_info info;
/* Setup the i2c board info with the device type and
the device address. */
memset(&info, 0, sizeof(info));
strlcpy(info.type, client_type, sizeof(info.type));
info.addr = addr;
return v4l2_i2c_new_subdev_board(v4l2_dev, adapter, &info, probe_addrs);
}
EXPORT_SYMBOL_GPL(v4l2_i2c_new_subdev);
/* Return i2c client address of v4l2_subdev. */
unsigned short v4l2_i2c_subdev_addr(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return client ? client->addr : I2C_CLIENT_END;
}
EXPORT_SYMBOL_GPL(v4l2_i2c_subdev_addr);
/* Return a list of I2C tuner addresses to probe. Use only if the tuner
addresses are unknown. */
const unsigned short *v4l2_i2c_tuner_addrs(enum v4l2_i2c_tuner_type type)
{
static const unsigned short radio_addrs[] = {
#if defined(CONFIG_MEDIA_TUNER_TEA5761) || defined(CONFIG_MEDIA_TUNER_TEA5761_MODULE)
0x10,
#endif
0x60,
I2C_CLIENT_END
};
static const unsigned short demod_addrs[] = {
0x42, 0x43, 0x4a, 0x4b,
I2C_CLIENT_END
};
static const unsigned short tv_addrs[] = {
0x42, 0x43, 0x4a, 0x4b, /* tda8290 */
0x60, 0x61, 0x62, 0x63, 0x64,
I2C_CLIENT_END
};
switch (type) {
case ADDRS_RADIO:
return radio_addrs;
case ADDRS_DEMOD:
return demod_addrs;
case ADDRS_TV:
return tv_addrs;
case ADDRS_TV_WITH_DEMOD:
return tv_addrs + 4;
}
return NULL;
}
EXPORT_SYMBOL_GPL(v4l2_i2c_tuner_addrs);
#endif /* defined(CONFIG_I2C) */
#if defined(CONFIG_SPI)
/* Load a spi sub-device. */
void v4l2_spi_subdev_init(struct v4l2_subdev *sd, struct spi_device *spi,
const struct v4l2_subdev_ops *ops)
{
v4l2_subdev_init(sd, ops);
sd->flags |= V4L2_SUBDEV_FL_IS_SPI;
/* the owner is the same as the spi_device's driver owner */
sd->owner = spi->dev.driver->owner;
/* spi_device and v4l2_subdev point to one another */
v4l2_set_subdevdata(sd, spi);
spi_set_drvdata(spi, sd);
/* initialize name */
strlcpy(sd->name, spi->dev.driver->name, sizeof(sd->name));
}
EXPORT_SYMBOL_GPL(v4l2_spi_subdev_init);
struct v4l2_subdev *v4l2_spi_new_subdev(struct v4l2_device *v4l2_dev,
struct spi_master *master, struct spi_board_info *info)
{
struct v4l2_subdev *sd = NULL;
struct spi_device *spi = NULL;
BUG_ON(!v4l2_dev);
if (info->modalias)
request_module(info->modalias);
spi = spi_new_device(master, info);
if (spi == NULL || spi->dev.driver == NULL)
goto error;
if (!try_module_get(spi->dev.driver->owner))
goto error;
sd = spi_get_drvdata(spi);
/* Register with the v4l2_device which increases the module's
use count as well. */
if (v4l2_device_register_subdev(v4l2_dev, sd))
sd = NULL;
/* Decrease the module use count to match the first try_module_get. */
module_put(spi->dev.driver->owner);
error:
/* If we have a client but no subdev, then something went wrong and
we must unregister the client. */
if (spi && sd == NULL)
spi_unregister_device(spi);
return sd;
}
EXPORT_SYMBOL_GPL(v4l2_spi_new_subdev);
#endif /* defined(CONFIG_SPI) */
/* Clamp x to be between min and max, aligned to a multiple of 2^align. min
* and max don't have to be aligned, but there must be at least one valid
* value. E.g., min=17,max=31,align=4 is not allowed as there are no multiples
* of 16 between 17 and 31. */
static unsigned int clamp_align(unsigned int x, unsigned int min,
unsigned int max, unsigned int align)
{
/* Bits that must be zero to be aligned */
unsigned int mask = ~((1 << align) - 1);
/* Round to nearest aligned value */
if (align)
x = (x + (1 << (align - 1))) & mask;
/* Clamp to aligned value of min and max */
if (x < min)
x = (min + ~mask) & mask;
else if (x > max)
x = max & mask;
return x;
}
/* Bound an image to have a width between wmin and wmax, and height between
* hmin and hmax, inclusive. Additionally, the width will be a multiple of
* 2^walign, the height will be a multiple of 2^halign, and the overall size
* (width*height) will be a multiple of 2^salign. The image may be shrunk
* or enlarged to fit the alignment constraints.
*
* The width or height maximum must not be smaller than the corresponding
* minimum. The alignments must not be so high there are no possible image
* sizes within the allowed bounds. wmin and hmin must be at least 1
* (don't use 0). If you don't care about a certain alignment, specify 0,
* as 2^0 is 1 and one byte alignment is equivalent to no alignment. If
* you only want to adjust downward, specify a maximum that's the same as
* the initial value.
*/
void v4l_bound_align_image(u32 *w, unsigned int wmin, unsigned int wmax,
unsigned int walign,
u32 *h, unsigned int hmin, unsigned int hmax,
unsigned int halign, unsigned int salign)
{
*w = clamp_align(*w, wmin, wmax, walign);
*h = clamp_align(*h, hmin, hmax, halign);
/* Usually we don't need to align the size and are done now. */
if (!salign)
return;
/* How much alignment do we have? */
walign = __ffs(*w);
halign = __ffs(*h);
/* Enough to satisfy the image alignment? */
if (walign + halign < salign) {
/* Max walign where there is still a valid width */
unsigned int wmaxa = __fls(wmax ^ (wmin - 1));
/* Max halign where there is still a valid height */
unsigned int hmaxa = __fls(hmax ^ (hmin - 1));
/* up the smaller alignment until we have enough */
do {
if (halign >= hmaxa ||
(walign <= halign && walign < wmaxa)) {
*w = clamp_align(*w, wmin, wmax, walign + 1);
walign = __ffs(*w);
} else {
*h = clamp_align(*h, hmin, hmax, halign + 1);
halign = __ffs(*h);
}
} while (halign + walign < salign);
}
}
EXPORT_SYMBOL_GPL(v4l_bound_align_image);
/**
* v4l_fill_dv_preset_info - fill description of a digital video preset
* @preset - preset value
* @info - pointer to struct v4l2_dv_enum_preset
*
* drivers can use this helper function to fill description of dv preset
* in info.
*/
int v4l_fill_dv_preset_info(u32 preset, struct v4l2_dv_enum_preset *info)
{
static const struct v4l2_dv_preset_info {
u16 width;
u16 height;
const char *name;
} dv_presets[] = {
{ 0, 0, "Invalid" }, /* V4L2_DV_INVALID */
{ 720, 480, "480p@59.94" }, /* V4L2_DV_480P59_94 */
{ 720, 576, "576p@50" }, /* V4L2_DV_576P50 */
{ 1280, 720, "720p@24" }, /* V4L2_DV_720P24 */
{ 1280, 720, "720p@25" }, /* V4L2_DV_720P25 */
{ 1280, 720, "720p@30" }, /* V4L2_DV_720P30 */
{ 1280, 720, "720p@50" }, /* V4L2_DV_720P50 */
{ 1280, 720, "720p@59.94" }, /* V4L2_DV_720P59_94 */
{ 1280, 720, "720p@60" }, /* V4L2_DV_720P60 */
{ 1920, 1080, "1080i@29.97" }, /* V4L2_DV_1080I29_97 */
{ 1920, 1080, "1080i@30" }, /* V4L2_DV_1080I30 */
{ 1920, 1080, "1080i@25" }, /* V4L2_DV_1080I25 */
{ 1920, 1080, "1080i@50" }, /* V4L2_DV_1080I50 */
{ 1920, 1080, "1080i@60" }, /* V4L2_DV_1080I60 */
{ 1920, 1080, "1080p@24" }, /* V4L2_DV_1080P24 */
{ 1920, 1080, "1080p@25" }, /* V4L2_DV_1080P25 */
{ 1920, 1080, "1080p@30" }, /* V4L2_DV_1080P30 */
{ 1920, 1080, "1080p@50" }, /* V4L2_DV_1080P50 */
{ 1920, 1080, "1080p@60" }, /* V4L2_DV_1080P60 */
};
if (info == NULL || preset >= ARRAY_SIZE(dv_presets))
return -EINVAL;
info->preset = preset;
info->width = dv_presets[preset].width;
info->height = dv_presets[preset].height;
strlcpy(info->name, dv_presets[preset].name, sizeof(info->name));
return 0;
}
EXPORT_SYMBOL_GPL(v4l_fill_dv_preset_info);
const struct v4l2_frmsize_discrete *v4l2_find_nearest_format(
const struct v4l2_discrete_probe *probe,
s32 width, s32 height)
{
int i;
u32 error, min_error = UINT_MAX;
const struct v4l2_frmsize_discrete *size, *best = NULL;
if (!probe)
return best;
for (i = 0, size = probe->sizes; i < probe->num_sizes; i++, size++) {
error = abs(size->width - width) + abs(size->height - height);
if (error < min_error) {
min_error = error;
best = size;
}
if (!error)
break;
}
return best;
}
EXPORT_SYMBOL_GPL(v4l2_find_nearest_format);
| gpl-2.0 |
talnoah/android_kernel_htc_dlx | virt/drivers/net/ethernet/smsc/smc911x.c | 4527 | 58936 | /*
* smc911x.c
* This is a driver for SMSC's LAN911{5,6,7,8} single-chip Ethernet devices.
*
* Copyright (C) 2005 Sensoria Corp
* Derived from the unified SMC91x driver by Nicolas Pitre
* and the smsc911x.c reference driver by SMSC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Arguments:
* watchdog = TX watchdog timeout
* tx_fifo_kb = Size of TX FIFO in KB
*
* History:
* 04/16/05 Dustin McIntire Initial version
*/
static const char version[] =
"smc911x.c: v1.0 04-16-2005 by Dustin McIntire <dustin@sensoria.com>\n";
/* Debugging options */
#define ENABLE_SMC_DEBUG_RX 0
#define ENABLE_SMC_DEBUG_TX 0
#define ENABLE_SMC_DEBUG_DMA 0
#define ENABLE_SMC_DEBUG_PKTS 0
#define ENABLE_SMC_DEBUG_MISC 0
#define ENABLE_SMC_DEBUG_FUNC 0
#define SMC_DEBUG_RX ((ENABLE_SMC_DEBUG_RX ? 1 : 0) << 0)
#define SMC_DEBUG_TX ((ENABLE_SMC_DEBUG_TX ? 1 : 0) << 1)
#define SMC_DEBUG_DMA ((ENABLE_SMC_DEBUG_DMA ? 1 : 0) << 2)
#define SMC_DEBUG_PKTS ((ENABLE_SMC_DEBUG_PKTS ? 1 : 0) << 3)
#define SMC_DEBUG_MISC ((ENABLE_SMC_DEBUG_MISC ? 1 : 0) << 4)
#define SMC_DEBUG_FUNC ((ENABLE_SMC_DEBUG_FUNC ? 1 : 0) << 5)
#ifndef SMC_DEBUG
#define SMC_DEBUG ( SMC_DEBUG_RX | \
SMC_DEBUG_TX | \
SMC_DEBUG_DMA | \
SMC_DEBUG_PKTS | \
SMC_DEBUG_MISC | \
SMC_DEBUG_FUNC \
)
#endif
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/crc32.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/workqueue.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <asm/io.h>
#include "smc911x.h"
/*
* Transmit timeout, default 5 seconds.
*/
static int watchdog = 5000;
module_param(watchdog, int, 0400);
MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
static int tx_fifo_kb=8;
module_param(tx_fifo_kb, int, 0400);
MODULE_PARM_DESC(tx_fifo_kb,"transmit FIFO size in KB (1<x<15)(default=8)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:smc911x");
/*
* The internal workings of the driver. If you are changing anything
* here with the SMC stuff, you should have the datasheet and know
* what you are doing.
*/
#define CARDNAME "smc911x"
/*
* Use power-down feature of the chip
*/
#define POWER_DOWN 1
#if SMC_DEBUG > 0
#define DBG(n, args...) \
do { \
if (SMC_DEBUG & (n)) \
printk(args); \
} while (0)
#define PRINTK(args...) printk(args)
#else
#define DBG(n, args...) do { } while (0)
#define PRINTK(args...) printk(KERN_DEBUG args)
#endif
#if SMC_DEBUG_PKTS > 0
static void PRINT_PKT(u_char *buf, int length)
{
int i;
int remainder;
int lines;
lines = length / 16;
remainder = length % 16;
for (i = 0; i < lines ; i ++) {
int cur;
for (cur = 0; cur < 8; cur++) {
u_char a, b;
a = *buf++;
b = *buf++;
printk("%02x%02x ", a, b);
}
printk("\n");
}
for (i = 0; i < remainder/2 ; i++) {
u_char a, b;
a = *buf++;
b = *buf++;
printk("%02x%02x ", a, b);
}
printk("\n");
}
#else
#define PRINT_PKT(x...) do { } while (0)
#endif
/* this enables an interrupt in the interrupt mask register */
#define SMC_ENABLE_INT(lp, x) do { \
unsigned int __mask; \
__mask = SMC_GET_INT_EN((lp)); \
__mask |= (x); \
SMC_SET_INT_EN((lp), __mask); \
} while (0)
/* this disables an interrupt from the interrupt mask register */
#define SMC_DISABLE_INT(lp, x) do { \
unsigned int __mask; \
__mask = SMC_GET_INT_EN((lp)); \
__mask &= ~(x); \
SMC_SET_INT_EN((lp), __mask); \
} while (0)
/*
* this does a soft reset on the device
*/
static void smc911x_reset(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int reg, timeout=0, resets=1, irq_cfg;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
/* Take out of PM setting first */
if ((SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_) == 0) {
/* Write to the bytetest will take out of powerdown */
SMC_SET_BYTE_TEST(lp, 0);
timeout=10;
do {
udelay(10);
reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_;
} while (--timeout && !reg);
if (timeout == 0) {
PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name);
return;
}
}
/* Disable all interrupts */
spin_lock_irqsave(&lp->lock, flags);
SMC_SET_INT_EN(lp, 0);
spin_unlock_irqrestore(&lp->lock, flags);
while (resets--) {
SMC_SET_HW_CFG(lp, HW_CFG_SRST_);
timeout=10;
do {
udelay(10);
reg = SMC_GET_HW_CFG(lp);
/* If chip indicates reset timeout then try again */
if (reg & HW_CFG_SRST_TO_) {
PRINTK("%s: chip reset timeout, retrying...\n", dev->name);
resets++;
break;
}
} while (--timeout && (reg & HW_CFG_SRST_));
}
if (timeout == 0) {
PRINTK("%s: smc911x_reset timeout waiting for reset\n", dev->name);
return;
}
/* make sure EEPROM has finished loading before setting GPIO_CFG */
timeout=1000;
while (--timeout && (SMC_GET_E2P_CMD(lp) & E2P_CMD_EPC_BUSY_))
udelay(10);
if (timeout == 0){
PRINTK("%s: smc911x_reset timeout waiting for EEPROM busy\n", dev->name);
return;
}
/* Initialize interrupts */
SMC_SET_INT_EN(lp, 0);
SMC_ACK_INT(lp, -1);
/* Reset the FIFO level and flow control settings */
SMC_SET_HW_CFG(lp, (lp->tx_fifo_kb & 0xF) << 16);
//TODO: Figure out what appropriate pause time is
SMC_SET_FLOW(lp, FLOW_FCPT_ | FLOW_FCEN_);
SMC_SET_AFC_CFG(lp, lp->afc_cfg);
/* Set to LED outputs */
SMC_SET_GPIO_CFG(lp, 0x70070000);
/*
* Deassert IRQ for 1*10us for edge type interrupts
* and drive IRQ pin push-pull
*/
irq_cfg = (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_;
#ifdef SMC_DYNAMIC_BUS_CONFIG
if (lp->cfg.irq_polarity)
irq_cfg |= INT_CFG_IRQ_POL_;
#endif
SMC_SET_IRQ_CFG(lp, irq_cfg);
/* clear anything saved */
if (lp->pending_tx_skb != NULL) {
dev_kfree_skb (lp->pending_tx_skb);
lp->pending_tx_skb = NULL;
dev->stats.tx_errors++;
dev->stats.tx_aborted_errors++;
}
}
/*
* Enable Interrupts, Receive, and Transmit
*/
static void smc911x_enable(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned mask, cfg, cr;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
spin_lock_irqsave(&lp->lock, flags);
SMC_SET_MAC_ADDR(lp, dev->dev_addr);
/* Enable TX */
cfg = SMC_GET_HW_CFG(lp);
cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
cfg |= HW_CFG_SF_;
SMC_SET_HW_CFG(lp, cfg);
SMC_SET_FIFO_TDA(lp, 0xFF);
/* Update TX stats on every 64 packets received or every 1 sec */
SMC_SET_FIFO_TSL(lp, 64);
SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
SMC_GET_MAC_CR(lp, cr);
cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
SMC_SET_MAC_CR(lp, cr);
SMC_SET_TX_CFG(lp, TX_CFG_TX_ON_);
/* Add 2 byte padding to start of packets */
SMC_SET_RX_CFG(lp, (2<<8) & RX_CFG_RXDOFF_);
/* Turn on receiver and enable RX */
if (cr & MAC_CR_RXEN_)
DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name);
SMC_SET_MAC_CR(lp, cr | MAC_CR_RXEN_);
/* Interrupt on every received packet */
SMC_SET_FIFO_RSA(lp, 0x01);
SMC_SET_FIFO_RSL(lp, 0x00);
/* now, enable interrupts */
mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
INT_EN_GPT_INT_EN_ | INT_EN_RXDFH_INT_EN_ | INT_EN_RXE_EN_ |
INT_EN_PHY_INT_EN_;
if (IS_REV_A(lp->revision))
mask|=INT_EN_RDFL_EN_;
else {
mask|=INT_EN_RDFO_EN_;
}
SMC_ENABLE_INT(lp, mask);
spin_unlock_irqrestore(&lp->lock, flags);
}
/*
* this puts the device in an inactive state
*/
static void smc911x_shutdown(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned cr;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __func__);
/* Disable IRQ's */
SMC_SET_INT_EN(lp, 0);
/* Turn of Rx and TX */
spin_lock_irqsave(&lp->lock, flags);
SMC_GET_MAC_CR(lp, cr);
cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
SMC_SET_MAC_CR(lp, cr);
SMC_SET_TX_CFG(lp, TX_CFG_STOP_TX_);
spin_unlock_irqrestore(&lp->lock, flags);
}
static inline void smc911x_drop_pkt(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int fifo_count, timeout, reg;
DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __func__);
fifo_count = SMC_GET_RX_FIFO_INF(lp) & 0xFFFF;
if (fifo_count <= 4) {
/* Manually dump the packet data */
while (fifo_count--)
SMC_GET_RX_FIFO(lp);
} else {
/* Fast forward through the bad packet */
SMC_SET_RX_DP_CTRL(lp, RX_DP_CTRL_FFWD_BUSY_);
timeout=50;
do {
udelay(10);
reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_;
} while (--timeout && reg);
if (timeout == 0) {
PRINTK("%s: timeout waiting for RX fast forward\n", dev->name);
}
}
}
/*
* This is the procedure to handle the receipt of a packet.
* It should be called after checking for packet presence in
* the RX status FIFO. It must be called with the spin lock
* already held.
*/
static inline void smc911x_rcv(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int pkt_len, status;
struct sk_buff *skb;
unsigned char *data;
DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n",
dev->name, __func__);
status = SMC_GET_RX_STS_FIFO(lp);
DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x\n",
dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff);
pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
if (status & RX_STS_ES_) {
/* Deal with a bad packet */
dev->stats.rx_errors++;
if (status & RX_STS_CRC_ERR_)
dev->stats.rx_crc_errors++;
else {
if (status & RX_STS_LEN_ERR_)
dev->stats.rx_length_errors++;
if (status & RX_STS_MCAST_)
dev->stats.multicast++;
}
/* Remove the bad packet data from the RX FIFO */
smc911x_drop_pkt(dev);
} else {
/* Receive a valid packet */
/* Alloc a buffer with extra room for DMA alignment */
skb = netdev_alloc_skb(dev, pkt_len+32);
if (unlikely(skb == NULL)) {
PRINTK( "%s: Low memory, rcvd packet dropped.\n",
dev->name);
dev->stats.rx_dropped++;
smc911x_drop_pkt(dev);
return;
}
/* Align IP header to 32 bits
* Note that the device is configured to add a 2
* byte padding to the packet start, so we really
* want to write to the orignal data pointer */
data = skb->data;
skb_reserve(skb, 2);
skb_put(skb,pkt_len-4);
#ifdef SMC_USE_DMA
{
unsigned int fifo;
/* Lower the FIFO threshold if possible */
fifo = SMC_GET_FIFO_INT(lp);
if (fifo & 0xFF) fifo--;
DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n",
dev->name, fifo & 0xff);
SMC_SET_FIFO_INT(lp, fifo);
/* Setup RX DMA */
SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
lp->rxdma_active = 1;
lp->current_rx_skb = skb;
SMC_PULL_DATA(lp, data, (pkt_len+2+15) & ~15);
/* Packet processing deferred to DMA RX interrupt */
}
#else
SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
SMC_PULL_DATA(lp, data, pkt_len+2+3);
DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name);
PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb);
dev->stats.rx_packets++;
dev->stats.rx_bytes += pkt_len-4;
#endif
}
}
/*
* This is called to actually send a packet to the chip.
*/
static void smc911x_hardware_send_pkt(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
struct sk_buff *skb;
unsigned int cmdA, cmdB, len;
unsigned char *buf;
DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n", dev->name, __func__);
BUG_ON(lp->pending_tx_skb == NULL);
skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
/* cmdA {25:24] data alignment [20:16] start offset [10:0] buffer length */
/* cmdB {31:16] pkt tag [10:0] length */
#ifdef SMC_USE_DMA
/* 16 byte buffer alignment mode */
buf = (char*)((u32)(skb->data) & ~0xF);
len = (skb->len + 0xF + ((u32)skb->data & 0xF)) & ~0xF;
cmdA = (1<<24) | (((u32)skb->data & 0xF)<<16) |
TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
skb->len;
#else
buf = (char*)((u32)skb->data & ~0x3);
len = (skb->len + 3 + ((u32)skb->data & 3)) & ~0x3;
cmdA = (((u32)skb->data & 0x3) << 16) |
TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
skb->len;
#endif
/* tag is packet length so we can use this in stats update later */
cmdB = (skb->len << 16) | (skb->len & 0x7FF);
DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
dev->name, len, len, buf, cmdA, cmdB);
SMC_SET_TX_FIFO(lp, cmdA);
SMC_SET_TX_FIFO(lp, cmdB);
DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name);
PRINT_PKT(buf, len <= 64 ? len : 64);
/* Send pkt via PIO or DMA */
#ifdef SMC_USE_DMA
lp->current_tx_skb = skb;
SMC_PUSH_DATA(lp, buf, len);
/* DMA complete IRQ will free buffer and set jiffies */
#else
SMC_PUSH_DATA(lp, buf, len);
dev->trans_start = jiffies;
dev_kfree_skb_irq(skb);
#endif
if (!lp->tx_throttle) {
netif_wake_queue(dev);
}
SMC_ENABLE_INT(lp, INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
}
/*
* Since I am not sure if I will have enough room in the chip's ram
* to store the packet, I call this routine which either sends it
* now, or set the card to generates an interrupt when ready
* for the packet.
*/
static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int free;
unsigned long flags;
DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
dev->name, __func__);
spin_lock_irqsave(&lp->lock, flags);
BUG_ON(lp->pending_tx_skb != NULL);
free = SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TDFREE_;
DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free);
/* Turn off the flow when running out of space in FIFO */
if (free <= SMC911X_TX_FIFO_LOW_THRESHOLD) {
DBG(SMC_DEBUG_TX, "%s: Disabling data flow due to low FIFO space (%d)\n",
dev->name, free);
/* Reenable when at least 1 packet of size MTU present */
SMC_SET_FIFO_TDA(lp, (SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
lp->tx_throttle = 1;
netif_stop_queue(dev);
}
/* Drop packets when we run out of space in TX FIFO
* Account for overhead required for:
*
* Tx command words 8 bytes
* Start offset 15 bytes
* End padding 15 bytes
*/
if (unlikely(free < (skb->len + 8 + 15 + 15))) {
printk("%s: No Tx free space %d < %d\n",
dev->name, free, skb->len);
lp->pending_tx_skb = NULL;
dev->stats.tx_errors++;
dev->stats.tx_dropped++;
spin_unlock_irqrestore(&lp->lock, flags);
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
#ifdef SMC_USE_DMA
{
/* If the DMA is already running then defer this packet Tx until
* the DMA IRQ starts it
*/
if (lp->txdma_active) {
DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Tx DMA running, deferring packet\n", dev->name);
lp->pending_tx_skb = skb;
netif_stop_queue(dev);
spin_unlock_irqrestore(&lp->lock, flags);
return NETDEV_TX_OK;
} else {
DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Activating Tx DMA\n", dev->name);
lp->txdma_active = 1;
}
}
#endif
lp->pending_tx_skb = skb;
smc911x_hardware_send_pkt(dev);
spin_unlock_irqrestore(&lp->lock, flags);
return NETDEV_TX_OK;
}
/*
* This handles a TX status interrupt, which is only called when:
* - a TX error occurred, or
* - TX of a packet completed.
*/
static void smc911x_tx(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int tx_status;
DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
dev->name, __func__);
/* Collect the TX status */
while (((SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n",
dev->name,
(SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16);
tx_status = SMC_GET_TX_STS_FIFO(lp);
dev->stats.tx_packets++;
dev->stats.tx_bytes+=tx_status>>16;
DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n",
dev->name, (tx_status & 0xffff0000) >> 16,
tx_status & 0x0000ffff);
/* count Tx errors, but ignore lost carrier errors when in
* full-duplex mode */
if ((tx_status & TX_STS_ES_) && !(lp->ctl_rfduplx &&
!(tx_status & 0x00000306))) {
dev->stats.tx_errors++;
}
if (tx_status & TX_STS_MANY_COLL_) {
dev->stats.collisions+=16;
dev->stats.tx_aborted_errors++;
} else {
dev->stats.collisions+=(tx_status & TX_STS_COLL_CNT_) >> 3;
}
/* carrier error only has meaning for half-duplex communication */
if ((tx_status & (TX_STS_LOC_ | TX_STS_NO_CARR_)) &&
!lp->ctl_rfduplx) {
dev->stats.tx_carrier_errors++;
}
if (tx_status & TX_STS_LATE_COLL_) {
dev->stats.collisions++;
dev->stats.tx_aborted_errors++;
}
}
}
/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
/*
* Reads a register from the MII Management serial interface
*/
static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int phydata;
SMC_GET_MII(lp, phyreg, phyaddr, phydata);
DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
__func__, phyaddr, phyreg, phydata);
return phydata;
}
/*
* Writes a register to the MII Management serial interface
*/
static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
int phydata)
{
struct smc911x_local *lp = netdev_priv(dev);
DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__func__, phyaddr, phyreg, phydata);
SMC_SET_MII(lp, phyreg, phyaddr, phydata);
}
/*
* Finds and reports the PHY address (115 and 117 have external
* PHY interface 118 has internal only
*/
static void smc911x_phy_detect(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int phyaddr;
unsigned int cfg, id1, id2;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
lp->phy_type = 0;
/*
* Scan all 32 PHY addresses if necessary, starting at
* PHY#1 to PHY#31, and then PHY#0 last.
*/
switch(lp->version) {
case CHIP_9115:
case CHIP_9117:
case CHIP_9215:
case CHIP_9217:
cfg = SMC_GET_HW_CFG(lp);
if (cfg & HW_CFG_EXT_PHY_DET_) {
cfg &= ~HW_CFG_PHY_CLK_SEL_;
cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
SMC_SET_HW_CFG(lp, cfg);
udelay(10); /* Wait for clocks to stop */
cfg |= HW_CFG_EXT_PHY_EN_;
SMC_SET_HW_CFG(lp, cfg);
udelay(10); /* Wait for clocks to stop */
cfg &= ~HW_CFG_PHY_CLK_SEL_;
cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
SMC_SET_HW_CFG(lp, cfg);
udelay(10); /* Wait for clocks to stop */
cfg |= HW_CFG_SMI_SEL_;
SMC_SET_HW_CFG(lp, cfg);
for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
/* Read the PHY identifiers */
SMC_GET_PHY_ID1(lp, phyaddr & 31, id1);
SMC_GET_PHY_ID2(lp, phyaddr & 31, id2);
/* Make sure it is a valid identifier */
if (id1 != 0x0000 && id1 != 0xffff &&
id1 != 0x8000 && id2 != 0x0000 &&
id2 != 0xffff && id2 != 0x8000) {
/* Save the PHY's address */
lp->mii.phy_id = phyaddr & 31;
lp->phy_type = id1 << 16 | id2;
break;
}
}
if (phyaddr < 32)
/* Found an external PHY */
break;
}
default:
/* Internal media only */
SMC_GET_PHY_ID1(lp, 1, id1);
SMC_GET_PHY_ID2(lp, 1, id2);
/* Save the PHY's address */
lp->mii.phy_id = 1;
lp->phy_type = id1 << 16 | id2;
}
DBG(SMC_DEBUG_MISC, "%s: phy_id1=0x%x, phy_id2=0x%x phyaddr=0x%d\n",
dev->name, id1, id2, lp->mii.phy_id);
}
/*
* Sets the PHY to a configuration as determined by the user.
* Called with spin_lock held.
*/
static int smc911x_phy_fixed(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int phyaddr = lp->mii.phy_id;
int bmcr;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
/* Enter Link Disable state */
SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
bmcr |= BMCR_PDOWN;
SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
/*
* Set our fixed capabilities
* Disable auto-negotiation
*/
bmcr &= ~BMCR_ANENABLE;
if (lp->ctl_rfduplx)
bmcr |= BMCR_FULLDPLX;
if (lp->ctl_rspeed == 100)
bmcr |= BMCR_SPEED100;
/* Write our capabilities to the phy control register */
SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
/* Re-Configure the Receive/Phy Control register */
bmcr &= ~BMCR_PDOWN;
SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
return 1;
}
/*
* smc911x_phy_reset - reset the phy
* @dev: net device
* @phy: phy address
*
* Issue a software reset for the specified PHY and
* wait up to 100ms for the reset to complete. We should
* not access the PHY for 50ms after issuing the reset.
*
* The time to wait appears to be dependent on the PHY.
*
*/
static int smc911x_phy_reset(struct net_device *dev, int phy)
{
struct smc911x_local *lp = netdev_priv(dev);
int timeout;
unsigned long flags;
unsigned int reg;
DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __func__);
spin_lock_irqsave(&lp->lock, flags);
reg = SMC_GET_PMT_CTRL(lp);
reg &= ~0xfffff030;
reg |= PMT_CTRL_PHY_RST_;
SMC_SET_PMT_CTRL(lp, reg);
spin_unlock_irqrestore(&lp->lock, flags);
for (timeout = 2; timeout; timeout--) {
msleep(50);
spin_lock_irqsave(&lp->lock, flags);
reg = SMC_GET_PMT_CTRL(lp);
spin_unlock_irqrestore(&lp->lock, flags);
if (!(reg & PMT_CTRL_PHY_RST_)) {
/* extra delay required because the phy may
* not be completed with its reset
* when PHY_BCR_RESET_ is cleared. 256us
* should suffice, but use 500us to be safe
*/
udelay(500);
break;
}
}
return reg & PMT_CTRL_PHY_RST_;
}
/*
* smc911x_phy_powerdown - powerdown phy
* @dev: net device
* @phy: phy address
*
* Power down the specified PHY
*/
static void smc911x_phy_powerdown(struct net_device *dev, int phy)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int bmcr;
/* Enter Link Disable state */
SMC_GET_PHY_BMCR(lp, phy, bmcr);
bmcr |= BMCR_PDOWN;
SMC_SET_PHY_BMCR(lp, phy, bmcr);
}
/*
* smc911x_phy_check_media - check the media status and adjust BMCR
* @dev: net device
* @init: set true for initialisation
*
* Select duplex mode depending on negotiation state. This
* also updates our carrier state.
*/
static void smc911x_phy_check_media(struct net_device *dev, int init)
{
struct smc911x_local *lp = netdev_priv(dev);
int phyaddr = lp->mii.phy_id;
unsigned int bmcr, cr;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
/* duplex state has changed */
SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
SMC_GET_MAC_CR(lp, cr);
if (lp->mii.full_duplex) {
DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name);
bmcr |= BMCR_FULLDPLX;
cr |= MAC_CR_RCVOWN_;
} else {
DBG(SMC_DEBUG_MISC, "%s: Configuring for half-duplex mode\n", dev->name);
bmcr &= ~BMCR_FULLDPLX;
cr &= ~MAC_CR_RCVOWN_;
}
SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
SMC_SET_MAC_CR(lp, cr);
}
}
/*
* Configures the specified PHY through the MII management interface
* using Autonegotiation.
* Calls smc911x_phy_fixed() if the user has requested a certain config.
* If RPC ANEG bit is set, the media selection is dependent purely on
* the selection by the MII (either in the MII BMCR reg or the result
* of autonegotiation.) If the RPC ANEG bit is cleared, the selection
* is controlled by the RPC SPEED and RPC DPLX bits.
*/
static void smc911x_phy_configure(struct work_struct *work)
{
struct smc911x_local *lp = container_of(work, struct smc911x_local,
phy_configure);
struct net_device *dev = lp->netdev;
int phyaddr = lp->mii.phy_id;
int my_phy_caps; /* My PHY capabilities */
int my_ad_caps; /* My Advertised capabilities */
int status;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __func__);
/*
* We should not be called if phy_type is zero.
*/
if (lp->phy_type == 0)
return;
if (smc911x_phy_reset(dev, phyaddr)) {
printk("%s: PHY reset timed out\n", dev->name);
return;
}
spin_lock_irqsave(&lp->lock, flags);
/*
* Enable PHY Interrupts (for register 18)
* Interrupts listed here are enabled
*/
SMC_SET_PHY_INT_MASK(lp, phyaddr, PHY_INT_MASK_ENERGY_ON_ |
PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
PHY_INT_MASK_LINK_DOWN_);
/* If the user requested no auto neg, then go set his request */
if (lp->mii.force_media) {
smc911x_phy_fixed(dev);
goto smc911x_phy_configure_exit;
}
/* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
SMC_GET_PHY_BMSR(lp, phyaddr, my_phy_caps);
if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
printk(KERN_INFO "Auto negotiation NOT supported\n");
smc911x_phy_fixed(dev);
goto smc911x_phy_configure_exit;
}
/* CSMA capable w/ both pauses */
my_ad_caps = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
if (my_phy_caps & BMSR_100BASE4)
my_ad_caps |= ADVERTISE_100BASE4;
if (my_phy_caps & BMSR_100FULL)
my_ad_caps |= ADVERTISE_100FULL;
if (my_phy_caps & BMSR_100HALF)
my_ad_caps |= ADVERTISE_100HALF;
if (my_phy_caps & BMSR_10FULL)
my_ad_caps |= ADVERTISE_10FULL;
if (my_phy_caps & BMSR_10HALF)
my_ad_caps |= ADVERTISE_10HALF;
/* Disable capabilities not selected by our user */
if (lp->ctl_rspeed != 100)
my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
if (!lp->ctl_rfduplx)
my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
/* Update our Auto-Neg Advertisement Register */
SMC_SET_PHY_MII_ADV(lp, phyaddr, my_ad_caps);
lp->mii.advertising = my_ad_caps;
/*
* Read the register back. Without this, it appears that when
* auto-negotiation is restarted, sometimes it isn't ready and
* the link does not come up.
*/
udelay(10);
SMC_GET_PHY_MII_ADV(lp, phyaddr, status);
DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps);
DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps);
/* Restart auto-negotiation process in order to advertise my caps */
SMC_SET_PHY_BMCR(lp, phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
smc911x_phy_check_media(dev, 1);
smc911x_phy_configure_exit:
spin_unlock_irqrestore(&lp->lock, flags);
}
/*
* smc911x_phy_interrupt
*
* Purpose: Handle interrupts relating to PHY register 18. This is
* called from the "hard" interrupt handler under our private spinlock.
*/
static void smc911x_phy_interrupt(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int phyaddr = lp->mii.phy_id;
int status;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
if (lp->phy_type == 0)
return;
smc911x_phy_check_media(dev, 0);
/* read to clear status bits */
SMC_GET_PHY_INT_SRC(lp, phyaddr,status);
DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n",
dev->name, status & 0xffff);
DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n",
dev->name, SMC_GET_AFC_CFG(lp));
}
/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
/*
* This is the main routine of the driver, to handle the device when
* it needs some attention.
*/
static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct smc911x_local *lp = netdev_priv(dev);
unsigned int status, mask, timeout;
unsigned int rx_overrun=0, cr, pkts;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
spin_lock_irqsave(&lp->lock, flags);
/* Spurious interrupt check */
if ((SMC_GET_IRQ_CFG(lp) & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
(INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
spin_unlock_irqrestore(&lp->lock, flags);
return IRQ_NONE;
}
mask = SMC_GET_INT_EN(lp);
SMC_SET_INT_EN(lp, 0);
/* set a timeout value, so I don't stay here forever */
timeout = 8;
do {
status = SMC_GET_INT(lp);
DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
dev->name, status, mask, status & ~mask);
status &= mask;
if (!status)
break;
/* Handle SW interrupt condition */
if (status & INT_STS_SW_INT_) {
SMC_ACK_INT(lp, INT_STS_SW_INT_);
mask &= ~INT_EN_SW_INT_EN_;
}
/* Handle various error conditions */
if (status & INT_STS_RXE_) {
SMC_ACK_INT(lp, INT_STS_RXE_);
dev->stats.rx_errors++;
}
if (status & INT_STS_RXDFH_INT_) {
SMC_ACK_INT(lp, INT_STS_RXDFH_INT_);
dev->stats.rx_dropped+=SMC_GET_RX_DROP(lp);
}
/* Undocumented interrupt-what is the right thing to do here? */
if (status & INT_STS_RXDF_INT_) {
SMC_ACK_INT(lp, INT_STS_RXDF_INT_);
}
/* Rx Data FIFO exceeds set level */
if (status & INT_STS_RDFL_) {
if (IS_REV_A(lp->revision)) {
rx_overrun=1;
SMC_GET_MAC_CR(lp, cr);
cr &= ~MAC_CR_RXEN_;
SMC_SET_MAC_CR(lp, cr);
DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
dev->stats.rx_errors++;
dev->stats.rx_fifo_errors++;
}
SMC_ACK_INT(lp, INT_STS_RDFL_);
}
if (status & INT_STS_RDFO_) {
if (!IS_REV_A(lp->revision)) {
SMC_GET_MAC_CR(lp, cr);
cr &= ~MAC_CR_RXEN_;
SMC_SET_MAC_CR(lp, cr);
rx_overrun=1;
DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
dev->stats.rx_errors++;
dev->stats.rx_fifo_errors++;
}
SMC_ACK_INT(lp, INT_STS_RDFO_);
}
/* Handle receive condition */
if ((status & INT_STS_RSFL_) || rx_overrun) {
unsigned int fifo;
DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name);
fifo = SMC_GET_RX_FIFO_INF(lp);
pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n",
dev->name, pkts, fifo & 0xFFFF );
if (pkts != 0) {
#ifdef SMC_USE_DMA
unsigned int fifo;
if (lp->rxdma_active){
DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
"%s: RX DMA active\n", dev->name);
/* The DMA is already running so up the IRQ threshold */
fifo = SMC_GET_FIFO_INT(lp) & ~0xFF;
fifo |= pkts & 0xFF;
DBG(SMC_DEBUG_RX,
"%s: Setting RX stat FIFO threshold to %d\n",
dev->name, fifo & 0xff);
SMC_SET_FIFO_INT(lp, fifo);
} else
#endif
smc911x_rcv(dev);
}
SMC_ACK_INT(lp, INT_STS_RSFL_);
}
/* Handle transmit FIFO available */
if (status & INT_STS_TDFA_) {
DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name);
SMC_SET_FIFO_TDA(lp, 0xFF);
lp->tx_throttle = 0;
#ifdef SMC_USE_DMA
if (!lp->txdma_active)
#endif
netif_wake_queue(dev);
SMC_ACK_INT(lp, INT_STS_TDFA_);
}
/* Handle transmit done condition */
#if 1
if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC,
"%s: Tx stat FIFO limit (%d) /GPT irq\n",
dev->name, (SMC_GET_FIFO_INT(lp) & 0x00ff0000) >> 16);
smc911x_tx(dev);
SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
SMC_ACK_INT(lp, INT_STS_TSFL_);
SMC_ACK_INT(lp, INT_STS_TSFL_ | INT_STS_GPT_INT_);
}
#else
if (status & INT_STS_TSFL_) {
DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq\n", dev->name, );
smc911x_tx(dev);
SMC_ACK_INT(lp, INT_STS_TSFL_);
}
if (status & INT_STS_GPT_INT_) {
DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
dev->name,
SMC_GET_IRQ_CFG(lp),
SMC_GET_FIFO_INT(lp),
SMC_GET_RX_CFG(lp));
DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x "
"Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
dev->name,
(SMC_GET_RX_FIFO_INF(lp) & 0x00ff0000) >> 16,
SMC_GET_RX_FIFO_INF(lp) & 0xffff,
SMC_GET_RX_STS_FIFO_PEEK(lp));
SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
SMC_ACK_INT(lp, INT_STS_GPT_INT_);
}
#endif
/* Handle PHY interrupt condition */
if (status & INT_STS_PHY_INT_) {
DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name);
smc911x_phy_interrupt(dev);
SMC_ACK_INT(lp, INT_STS_PHY_INT_);
}
} while (--timeout);
/* restore mask state */
SMC_SET_INT_EN(lp, mask);
DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n",
dev->name, 8-timeout);
spin_unlock_irqrestore(&lp->lock, flags);
return IRQ_HANDLED;
}
#ifdef SMC_USE_DMA
static void
smc911x_tx_dma_irq(int dma, void *data)
{
struct net_device *dev = (struct net_device *)data;
struct smc911x_local *lp = netdev_priv(dev);
struct sk_buff *skb = lp->current_tx_skb;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: TX DMA irq handler\n", dev->name);
/* Clear the DMA interrupt sources */
SMC_DMA_ACK_IRQ(dev, dma);
BUG_ON(skb == NULL);
dma_unmap_single(NULL, tx_dmabuf, tx_dmalen, DMA_TO_DEVICE);
dev->trans_start = jiffies;
dev_kfree_skb_irq(skb);
lp->current_tx_skb = NULL;
if (lp->pending_tx_skb != NULL)
smc911x_hardware_send_pkt(dev);
else {
DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
"%s: No pending Tx packets. DMA disabled\n", dev->name);
spin_lock_irqsave(&lp->lock, flags);
lp->txdma_active = 0;
if (!lp->tx_throttle) {
netif_wake_queue(dev);
}
spin_unlock_irqrestore(&lp->lock, flags);
}
DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
"%s: TX DMA irq completed\n", dev->name);
}
static void
smc911x_rx_dma_irq(int dma, void *data)
{
struct net_device *dev = (struct net_device *)data;
unsigned long ioaddr = dev->base_addr;
struct smc911x_local *lp = netdev_priv(dev);
struct sk_buff *skb = lp->current_rx_skb;
unsigned long flags;
unsigned int pkts;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, "%s: RX DMA irq handler\n", dev->name);
/* Clear the DMA interrupt sources */
SMC_DMA_ACK_IRQ(dev, dma);
dma_unmap_single(NULL, rx_dmabuf, rx_dmalen, DMA_FROM_DEVICE);
BUG_ON(skb == NULL);
lp->current_rx_skb = NULL;
PRINT_PKT(skb->data, skb->len);
skb->protocol = eth_type_trans(skb, dev);
dev->stats.rx_packets++;
dev->stats.rx_bytes += skb->len;
netif_rx(skb);
spin_lock_irqsave(&lp->lock, flags);
pkts = (SMC_GET_RX_FIFO_INF(lp) & RX_FIFO_INF_RXSUSED_) >> 16;
if (pkts != 0) {
smc911x_rcv(dev);
}else {
lp->rxdma_active = 0;
}
spin_unlock_irqrestore(&lp->lock, flags);
DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
"%s: RX DMA irq completed. DMA RX FIFO PKTS %d\n",
dev->name, pkts);
}
#endif /* SMC_USE_DMA */
#ifdef CONFIG_NET_POLL_CONTROLLER
/*
* Polling receive - used by netconsole and other diagnostic tools
* to allow network i/o with interrupts disabled.
*/
static void smc911x_poll_controller(struct net_device *dev)
{
disable_irq(dev->irq);
smc911x_interrupt(dev->irq, dev);
enable_irq(dev->irq);
}
#endif
/* Our watchdog timed out. Called by the networking layer */
static void smc911x_timeout(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int status, mask;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
spin_lock_irqsave(&lp->lock, flags);
status = SMC_GET_INT(lp);
mask = SMC_GET_INT_EN(lp);
spin_unlock_irqrestore(&lp->lock, flags);
DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x\n",
dev->name, status, mask);
/* Dump the current TX FIFO contents and restart */
mask = SMC_GET_TX_CFG(lp);
SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
/*
* Reconfiguring the PHY doesn't seem like a bad idea here, but
* smc911x_phy_configure() calls msleep() which calls schedule_timeout()
* which calls schedule(). Hence we use a work queue.
*/
if (lp->phy_type != 0)
schedule_work(&lp->phy_configure);
/* We can accept TX packets again */
dev->trans_start = jiffies; /* prevent tx timeout */
netif_wake_queue(dev);
}
/*
* This routine will, depending on the values passed to it,
* either make it accept multicast packets, go into
* promiscuous mode (for TCPDUMP and cousins) or accept
* a select set of multicast packets
*/
static void smc911x_set_multicast_list(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int multicast_table[2];
unsigned int mcr, update_multicast = 0;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
spin_lock_irqsave(&lp->lock, flags);
SMC_GET_MAC_CR(lp, mcr);
spin_unlock_irqrestore(&lp->lock, flags);
if (dev->flags & IFF_PROMISC) {
DBG(SMC_DEBUG_MISC, "%s: RCR_PRMS\n", dev->name);
mcr |= MAC_CR_PRMS_;
}
/*
* Here, I am setting this to accept all multicast packets.
* I don't need to zero the multicast table, because the flag is
* checked before the table is
*/
else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
DBG(SMC_DEBUG_MISC, "%s: RCR_ALMUL\n", dev->name);
mcr |= MAC_CR_MCPAS_;
}
/*
* This sets the internal hardware table to filter out unwanted
* multicast packets before they take up memory.
*
* The SMC chip uses a hash table where the high 6 bits of the CRC of
* address are the offset into the table. If that bit is 1, then the
* multicast packet is accepted. Otherwise, it's dropped silently.
*
* To use the 6 bits as an offset into the table, the high 1 bit is
* the number of the 32 bit register, while the low 5 bits are the bit
* within that register.
*/
else if (!netdev_mc_empty(dev)) {
struct netdev_hw_addr *ha;
/* Set the Hash perfec mode */
mcr |= MAC_CR_HPFILT_;
/* start with a table of all zeros: reject all */
memset(multicast_table, 0, sizeof(multicast_table));
netdev_for_each_mc_addr(ha, dev) {
u32 position;
/* upper 6 bits are used as hash index */
position = ether_crc(ETH_ALEN, ha->addr)>>26;
multicast_table[position>>5] |= 1 << (position&0x1f);
}
/* be sure I get rid of flags I might have set */
mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
/* now, the table can be loaded into the chipset */
update_multicast = 1;
} else {
DBG(SMC_DEBUG_MISC, "%s: ~(MAC_CR_PRMS_|MAC_CR_MCPAS_)\n",
dev->name);
mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
/*
* since I'm disabling all multicast entirely, I need to
* clear the multicast list
*/
memset(multicast_table, 0, sizeof(multicast_table));
update_multicast = 1;
}
spin_lock_irqsave(&lp->lock, flags);
SMC_SET_MAC_CR(lp, mcr);
if (update_multicast) {
DBG(SMC_DEBUG_MISC,
"%s: update mcast hash table 0x%08x 0x%08x\n",
dev->name, multicast_table[0], multicast_table[1]);
SMC_SET_HASHL(lp, multicast_table[0]);
SMC_SET_HASHH(lp, multicast_table[1]);
}
spin_unlock_irqrestore(&lp->lock, flags);
}
/*
* Open and Initialize the board
*
* Set up everything, reset the card, etc..
*/
static int
smc911x_open(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
/*
* Check that the address is valid. If its not, refuse
* to bring the device up. The user must specify an
* address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
*/
if (!is_valid_ether_addr(dev->dev_addr)) {
PRINTK("%s: no valid ethernet hw addr\n", __func__);
return -EINVAL;
}
/* reset the hardware */
smc911x_reset(dev);
/* Configure the PHY, initialize the link state */
smc911x_phy_configure(&lp->phy_configure);
/* Turn on Tx + Rx */
smc911x_enable(dev);
netif_start_queue(dev);
return 0;
}
/*
* smc911x_close
*
* this makes the board clean up everything that it can
* and not talk to the outside world. Caused by
* an 'ifconfig ethX down'
*/
static int smc911x_close(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
netif_stop_queue(dev);
netif_carrier_off(dev);
/* clear everything */
smc911x_shutdown(dev);
if (lp->phy_type != 0) {
/* We need to ensure that no calls to
* smc911x_phy_configure are pending.
*/
cancel_work_sync(&lp->phy_configure);
smc911x_phy_powerdown(dev, lp->mii.phy_id);
}
if (lp->pending_tx_skb) {
dev_kfree_skb(lp->pending_tx_skb);
lp->pending_tx_skb = NULL;
}
return 0;
}
/*
* Ethtool support
*/
static int
smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct smc911x_local *lp = netdev_priv(dev);
int ret, status;
unsigned long flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
cmd->maxtxpkt = 1;
cmd->maxrxpkt = 1;
if (lp->phy_type != 0) {
spin_lock_irqsave(&lp->lock, flags);
ret = mii_ethtool_gset(&lp->mii, cmd);
spin_unlock_irqrestore(&lp->lock, flags);
} else {
cmd->supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_TP | SUPPORTED_AUI;
if (lp->ctl_rspeed == 10)
ethtool_cmd_speed_set(cmd, SPEED_10);
else if (lp->ctl_rspeed == 100)
ethtool_cmd_speed_set(cmd, SPEED_100);
cmd->autoneg = AUTONEG_DISABLE;
if (lp->mii.phy_id==1)
cmd->transceiver = XCVR_INTERNAL;
else
cmd->transceiver = XCVR_EXTERNAL;
cmd->port = 0;
SMC_GET_PHY_SPECIAL(lp, lp->mii.phy_id, status);
cmd->duplex =
(status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
DUPLEX_FULL : DUPLEX_HALF;
ret = 0;
}
return ret;
}
static int
smc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct smc911x_local *lp = netdev_priv(dev);
int ret;
unsigned long flags;
if (lp->phy_type != 0) {
spin_lock_irqsave(&lp->lock, flags);
ret = mii_ethtool_sset(&lp->mii, cmd);
spin_unlock_irqrestore(&lp->lock, flags);
} else {
if (cmd->autoneg != AUTONEG_DISABLE ||
cmd->speed != SPEED_10 ||
(cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
(cmd->port != PORT_TP && cmd->port != PORT_AUI))
return -EINVAL;
lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
ret = 0;
}
return ret;
}
static void
smc911x_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
strncpy(info->driver, CARDNAME, sizeof(info->driver));
strncpy(info->version, version, sizeof(info->version));
strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
}
static int smc911x_ethtool_nwayreset(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int ret = -EINVAL;
unsigned long flags;
if (lp->phy_type != 0) {
spin_lock_irqsave(&lp->lock, flags);
ret = mii_nway_restart(&lp->mii);
spin_unlock_irqrestore(&lp->lock, flags);
}
return ret;
}
static u32 smc911x_ethtool_getmsglevel(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
return lp->msg_enable;
}
static void smc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
{
struct smc911x_local *lp = netdev_priv(dev);
lp->msg_enable = level;
}
static int smc911x_ethtool_getregslen(struct net_device *dev)
{
/* System regs + MAC regs + PHY regs */
return (((E2P_CMD - ID_REV)/4 + 1) +
(WUCSR - MAC_CR)+1 + 32) * sizeof(u32);
}
static void smc911x_ethtool_getregs(struct net_device *dev,
struct ethtool_regs* regs, void *buf)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned long flags;
u32 reg,i,j=0;
u32 *data = (u32*)buf;
regs->version = lp->version;
for(i=ID_REV;i<=E2P_CMD;i+=4) {
data[j++] = SMC_inl(lp, i);
}
for(i=MAC_CR;i<=WUCSR;i++) {
spin_lock_irqsave(&lp->lock, flags);
SMC_GET_MAC_CSR(lp, i, reg);
spin_unlock_irqrestore(&lp->lock, flags);
data[j++] = reg;
}
for(i=0;i<=31;i++) {
spin_lock_irqsave(&lp->lock, flags);
SMC_GET_MII(lp, i, lp->mii.phy_id, reg);
spin_unlock_irqrestore(&lp->lock, flags);
data[j++] = reg & 0xFFFF;
}
}
static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
unsigned int timeout;
int e2p_cmd;
e2p_cmd = SMC_GET_E2P_CMD(lp);
for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
PRINTK("%s: %s timeout waiting for EEPROM to respond\n",
dev->name, __func__);
return -EFAULT;
}
mdelay(1);
e2p_cmd = SMC_GET_E2P_CMD(lp);
}
if (timeout == 0) {
PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n",
dev->name, __func__);
return -ETIMEDOUT;
}
return 0;
}
static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
int cmd, int addr)
{
struct smc911x_local *lp = netdev_priv(dev);
int ret;
if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
return ret;
SMC_SET_E2P_CMD(lp, E2P_CMD_EPC_BUSY_ |
((cmd) & (0x7<<28)) |
((addr) & 0xFF));
return 0;
}
static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
u8 *data)
{
struct smc911x_local *lp = netdev_priv(dev);
int ret;
if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
return ret;
*data = SMC_GET_E2P_DATA(lp);
return 0;
}
static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
u8 data)
{
struct smc911x_local *lp = netdev_priv(dev);
int ret;
if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
return ret;
SMC_SET_E2P_DATA(lp, data);
return 0;
}
static int smc911x_ethtool_geteeprom(struct net_device *dev,
struct ethtool_eeprom *eeprom, u8 *data)
{
u8 eebuf[SMC911X_EEPROM_LEN];
int i, ret;
for(i=0;i<SMC911X_EEPROM_LEN;i++) {
if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ_, i ))!=0)
return ret;
if ((ret=smc911x_ethtool_read_eeprom_byte(dev, &eebuf[i]))!=0)
return ret;
}
memcpy(data, eebuf+eeprom->offset, eeprom->len);
return 0;
}
static int smc911x_ethtool_seteeprom(struct net_device *dev,
struct ethtool_eeprom *eeprom, u8 *data)
{
int i, ret;
/* Enable erase */
if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN_, 0 ))!=0)
return ret;
for(i=eeprom->offset;i<(eeprom->offset+eeprom->len);i++) {
/* erase byte */
if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE_, i ))!=0)
return ret;
/* write byte */
if ((ret=smc911x_ethtool_write_eeprom_byte(dev, *data))!=0)
return ret;
if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE_, i ))!=0)
return ret;
}
return 0;
}
static int smc911x_ethtool_geteeprom_len(struct net_device *dev)
{
return SMC911X_EEPROM_LEN;
}
static const struct ethtool_ops smc911x_ethtool_ops = {
.get_settings = smc911x_ethtool_getsettings,
.set_settings = smc911x_ethtool_setsettings,
.get_drvinfo = smc911x_ethtool_getdrvinfo,
.get_msglevel = smc911x_ethtool_getmsglevel,
.set_msglevel = smc911x_ethtool_setmsglevel,
.nway_reset = smc911x_ethtool_nwayreset,
.get_link = ethtool_op_get_link,
.get_regs_len = smc911x_ethtool_getregslen,
.get_regs = smc911x_ethtool_getregs,
.get_eeprom_len = smc911x_ethtool_geteeprom_len,
.get_eeprom = smc911x_ethtool_geteeprom,
.set_eeprom = smc911x_ethtool_seteeprom,
};
/*
* smc911x_findirq
*
* This routine has a simple purpose -- make the SMC chip generate an
* interrupt, so an auto-detect routine can detect it, and find the IRQ,
*/
static int __devinit smc911x_findirq(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int timeout = 20;
unsigned long cookie;
DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
cookie = probe_irq_on();
/*
* Force a SW interrupt
*/
SMC_SET_INT_EN(lp, INT_EN_SW_INT_EN_);
/*
* Wait until positive that the interrupt has been generated
*/
do {
int int_status;
udelay(10);
int_status = SMC_GET_INT_EN(lp);
if (int_status & INT_EN_SW_INT_EN_)
break; /* got the interrupt */
} while (--timeout);
/*
* there is really nothing that I can do here if timeout fails,
* as autoirq_report will return a 0 anyway, which is what I
* want in this case. Plus, the clean up is needed in both
* cases.
*/
/* and disable all interrupts again */
SMC_SET_INT_EN(lp, 0);
/* and return what I found */
return probe_irq_off(cookie);
}
static const struct net_device_ops smc911x_netdev_ops = {
.ndo_open = smc911x_open,
.ndo_stop = smc911x_close,
.ndo_start_xmit = smc911x_hard_start_xmit,
.ndo_tx_timeout = smc911x_timeout,
.ndo_set_rx_mode = smc911x_set_multicast_list,
.ndo_change_mtu = eth_change_mtu,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = eth_mac_addr,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = smc911x_poll_controller,
#endif
};
/*
* Function: smc911x_probe(unsigned long ioaddr)
*
* Purpose:
* Tests to see if a given ioaddr points to an SMC911x chip.
* Returns a 0 on success
*
* Algorithm:
* (1) see if the endian word is OK
* (1) see if I recognize the chip ID in the appropriate register
*
* Here I do typical initialization tasks.
*
* o Initialize the structure if needed
* o print out my vanity message if not done so already
* o print out what type of hardware is detected
* o print out the ethernet address
* o find the IRQ
* o set up my private data
* o configure the dev structure with my subroutines
* o actually GRAB the irq.
* o GRAB the region
*/
static int __devinit smc911x_probe(struct net_device *dev)
{
struct smc911x_local *lp = netdev_priv(dev);
int i, retval;
unsigned int val, chip_id, revision;
const char *version_string;
unsigned long irq_flags;
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
/* First, see if the endian word is recognized */
val = SMC_GET_BYTE_TEST(lp);
DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val);
if (val != 0x87654321) {
printk(KERN_ERR "Invalid chip endian 0x%08x\n",val);
retval = -ENODEV;
goto err_out;
}
/*
* check if the revision register is something that I
* recognize. These might need to be added to later,
* as future revisions could be added.
*/
chip_id = SMC_GET_PN(lp);
DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id);
for(i=0;chip_ids[i].id != 0; i++) {
if (chip_ids[i].id == chip_id) break;
}
if (!chip_ids[i].id) {
printk(KERN_ERR "Unknown chip ID %04x\n", chip_id);
retval = -ENODEV;
goto err_out;
}
version_string = chip_ids[i].name;
revision = SMC_GET_REV(lp);
DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision);
/* At this point I'll assume that the chip is an SMC911x. */
DBG(SMC_DEBUG_MISC, "%s: Found a %s\n", CARDNAME, chip_ids[i].name);
/* Validate the TX FIFO size requested */
if ((tx_fifo_kb < 2) || (tx_fifo_kb > 14)) {
printk(KERN_ERR "Invalid TX FIFO size requested %d\n", tx_fifo_kb);
retval = -EINVAL;
goto err_out;
}
/* fill in some of the fields */
lp->version = chip_ids[i].id;
lp->revision = revision;
lp->tx_fifo_kb = tx_fifo_kb;
/* Reverse calculate the RX FIFO size from the TX */
lp->tx_fifo_size=(lp->tx_fifo_kb<<10) - 512;
lp->rx_fifo_size= ((0x4000 - 512 - lp->tx_fifo_size) / 16) * 15;
/* Set the automatic flow control values */
switch(lp->tx_fifo_kb) {
/*
* AFC_HI is about ((Rx Data Fifo Size)*2/3)/64
* AFC_LO is AFC_HI/2
* BACK_DUR is about 5uS*(AFC_LO) rounded down
*/
case 2:/* 13440 Rx Data Fifo Size */
lp->afc_cfg=0x008C46AF;break;
case 3:/* 12480 Rx Data Fifo Size */
lp->afc_cfg=0x0082419F;break;
case 4:/* 11520 Rx Data Fifo Size */
lp->afc_cfg=0x00783C9F;break;
case 5:/* 10560 Rx Data Fifo Size */
lp->afc_cfg=0x006E374F;break;
case 6:/* 9600 Rx Data Fifo Size */
lp->afc_cfg=0x0064328F;break;
case 7:/* 8640 Rx Data Fifo Size */
lp->afc_cfg=0x005A2D7F;break;
case 8:/* 7680 Rx Data Fifo Size */
lp->afc_cfg=0x0050287F;break;
case 9:/* 6720 Rx Data Fifo Size */
lp->afc_cfg=0x0046236F;break;
case 10:/* 5760 Rx Data Fifo Size */
lp->afc_cfg=0x003C1E6F;break;
case 11:/* 4800 Rx Data Fifo Size */
lp->afc_cfg=0x0032195F;break;
/*
* AFC_HI is ~1520 bytes less than RX Data Fifo Size
* AFC_LO is AFC_HI/2
* BACK_DUR is about 5uS*(AFC_LO) rounded down
*/
case 12:/* 3840 Rx Data Fifo Size */
lp->afc_cfg=0x0024124F;break;
case 13:/* 2880 Rx Data Fifo Size */
lp->afc_cfg=0x0015073F;break;
case 14:/* 1920 Rx Data Fifo Size */
lp->afc_cfg=0x0006032F;break;
default:
PRINTK("%s: ERROR -- no AFC_CFG setting found",
dev->name);
break;
}
DBG(SMC_DEBUG_MISC | SMC_DEBUG_TX | SMC_DEBUG_RX,
"%s: tx_fifo %d rx_fifo %d afc_cfg 0x%08x\n", CARDNAME,
lp->tx_fifo_size, lp->rx_fifo_size, lp->afc_cfg);
spin_lock_init(&lp->lock);
/* Get the MAC address */
SMC_GET_MAC_ADDR(lp, dev->dev_addr);
/* now, reset the chip, and put it into a known state */
smc911x_reset(dev);
/*
* If dev->irq is 0, then the device has to be banged on to see
* what the IRQ is.
*
* Specifying an IRQ is done with the assumption that the user knows
* what (s)he is doing. No checking is done!!!!
*/
if (dev->irq < 1) {
int trials;
trials = 3;
while (trials--) {
dev->irq = smc911x_findirq(dev);
if (dev->irq)
break;
/* kick the card and try again */
smc911x_reset(dev);
}
}
if (dev->irq == 0) {
printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
dev->name);
retval = -ENODEV;
goto err_out;
}
dev->irq = irq_canonicalize(dev->irq);
/* Fill in the fields of the device structure with ethernet values. */
ether_setup(dev);
dev->netdev_ops = &smc911x_netdev_ops;
dev->watchdog_timeo = msecs_to_jiffies(watchdog);
dev->ethtool_ops = &smc911x_ethtool_ops;
INIT_WORK(&lp->phy_configure, smc911x_phy_configure);
lp->mii.phy_id_mask = 0x1f;
lp->mii.reg_num_mask = 0x1f;
lp->mii.force_media = 0;
lp->mii.full_duplex = 0;
lp->mii.dev = dev;
lp->mii.mdio_read = smc911x_phy_read;
lp->mii.mdio_write = smc911x_phy_write;
/*
* Locate the phy, if any.
*/
smc911x_phy_detect(dev);
/* Set default parameters */
lp->msg_enable = NETIF_MSG_LINK;
lp->ctl_rfduplx = 1;
lp->ctl_rspeed = 100;
#ifdef SMC_DYNAMIC_BUS_CONFIG
irq_flags = lp->cfg.irq_flags;
#else
irq_flags = IRQF_SHARED | SMC_IRQ_SENSE;
#endif
/* Grab the IRQ */
retval = request_irq(dev->irq, smc911x_interrupt,
irq_flags, dev->name, dev);
if (retval)
goto err_out;
#ifdef SMC_USE_DMA
lp->rxdma = SMC_DMA_REQUEST(dev, smc911x_rx_dma_irq);
lp->txdma = SMC_DMA_REQUEST(dev, smc911x_tx_dma_irq);
lp->rxdma_active = 0;
lp->txdma_active = 0;
dev->dma = lp->rxdma;
#endif
retval = register_netdev(dev);
if (retval == 0) {
/* now, print out the card info, in a short format.. */
printk("%s: %s (rev %d) at %#lx IRQ %d",
dev->name, version_string, lp->revision,
dev->base_addr, dev->irq);
#ifdef SMC_USE_DMA
if (lp->rxdma != -1)
printk(" RXDMA %d ", lp->rxdma);
if (lp->txdma != -1)
printk("TXDMA %d", lp->txdma);
#endif
printk("\n");
if (!is_valid_ether_addr(dev->dev_addr)) {
printk("%s: Invalid ethernet MAC address. Please "
"set using ifconfig\n", dev->name);
} else {
/* Print the Ethernet address */
printk("%s: Ethernet addr: %pM\n",
dev->name, dev->dev_addr);
}
if (lp->phy_type == 0) {
PRINTK("%s: No PHY found\n", dev->name);
} else if ((lp->phy_type & ~0xff) == LAN911X_INTERNAL_PHY_ID) {
PRINTK("%s: LAN911x Internal PHY\n", dev->name);
} else {
PRINTK("%s: External PHY 0x%08x\n", dev->name, lp->phy_type);
}
}
err_out:
#ifdef SMC_USE_DMA
if (retval) {
if (lp->rxdma != -1) {
SMC_DMA_FREE(dev, lp->rxdma);
}
if (lp->txdma != -1) {
SMC_DMA_FREE(dev, lp->txdma);
}
}
#endif
return retval;
}
/*
* smc911x_init(void)
*
* Output:
* 0 --> there is a device
* anything else, error
*/
static int __devinit smc911x_drv_probe(struct platform_device *pdev)
{
struct net_device *ndev;
struct resource *res;
struct smc911x_local *lp;
unsigned int *addr;
int ret;
DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENODEV;
goto out;
}
/*
* Request the regions.
*/
if (!request_mem_region(res->start, SMC911X_IO_EXTENT, CARDNAME)) {
ret = -EBUSY;
goto out;
}
ndev = alloc_etherdev(sizeof(struct smc911x_local));
if (!ndev) {
ret = -ENOMEM;
goto release_1;
}
SET_NETDEV_DEV(ndev, &pdev->dev);
ndev->dma = (unsigned char)-1;
ndev->irq = platform_get_irq(pdev, 0);
lp = netdev_priv(ndev);
lp->netdev = ndev;
#ifdef SMC_DYNAMIC_BUS_CONFIG
{
struct smc911x_platdata *pd = pdev->dev.platform_data;
if (!pd) {
ret = -EINVAL;
goto release_both;
}
memcpy(&lp->cfg, pd, sizeof(lp->cfg));
}
#endif
addr = ioremap(res->start, SMC911X_IO_EXTENT);
if (!addr) {
ret = -ENOMEM;
goto release_both;
}
platform_set_drvdata(pdev, ndev);
lp->base = addr;
ndev->base_addr = res->start;
ret = smc911x_probe(ndev);
if (ret != 0) {
platform_set_drvdata(pdev, NULL);
iounmap(addr);
release_both:
free_netdev(ndev);
release_1:
release_mem_region(res->start, SMC911X_IO_EXTENT);
out:
printk("%s: not found (%d).\n", CARDNAME, ret);
}
#ifdef SMC_USE_DMA
else {
lp->physaddr = res->start;
lp->dev = &pdev->dev;
}
#endif
return ret;
}
static int __devexit smc911x_drv_remove(struct platform_device *pdev)
{
struct net_device *ndev = platform_get_drvdata(pdev);
struct smc911x_local *lp = netdev_priv(ndev);
struct resource *res;
DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
platform_set_drvdata(pdev, NULL);
unregister_netdev(ndev);
free_irq(ndev->irq, ndev);
#ifdef SMC_USE_DMA
{
if (lp->rxdma != -1) {
SMC_DMA_FREE(dev, lp->rxdma);
}
if (lp->txdma != -1) {
SMC_DMA_FREE(dev, lp->txdma);
}
}
#endif
iounmap(lp->base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, SMC911X_IO_EXTENT);
free_netdev(ndev);
return 0;
}
static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
{
struct net_device *ndev = platform_get_drvdata(dev);
struct smc911x_local *lp = netdev_priv(ndev);
DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
if (ndev) {
if (netif_running(ndev)) {
netif_device_detach(ndev);
smc911x_shutdown(ndev);
#if POWER_DOWN
/* Set D2 - Energy detect only setting */
SMC_SET_PMT_CTRL(lp, 2<<12);
#endif
}
}
return 0;
}
static int smc911x_drv_resume(struct platform_device *dev)
{
struct net_device *ndev = platform_get_drvdata(dev);
DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
if (ndev) {
struct smc911x_local *lp = netdev_priv(ndev);
if (netif_running(ndev)) {
smc911x_reset(ndev);
if (lp->phy_type != 0)
smc911x_phy_configure(&lp->phy_configure);
smc911x_enable(ndev);
netif_device_attach(ndev);
}
}
return 0;
}
static struct platform_driver smc911x_driver = {
.probe = smc911x_drv_probe,
.remove = __devexit_p(smc911x_drv_remove),
.suspend = smc911x_drv_suspend,
.resume = smc911x_drv_resume,
.driver = {
.name = CARDNAME,
.owner = THIS_MODULE,
},
};
module_platform_driver(smc911x_driver);
| gpl-2.0 |
Metallium-Devices/android_kernel_lge_msm8974 | drivers/dma/mxs-dma.c | 4783 | 18561 | /*
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Refer to drivers/dma/imx-sdma.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/semaphore.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/delay.h>
#include <linux/fsl/mxs-dma.h>
#include <asm/irq.h>
#include <mach/mxs.h>
#include <mach/common.h>
#include "dmaengine.h"
/*
* NOTE: The term "PIO" throughout the mxs-dma implementation means
* PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
* dma can program the controller registers of peripheral devices.
*/
#define MXS_DMA_APBH 0
#define MXS_DMA_APBX 1
#define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
#define APBH_VERSION_LATEST 3
#define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
#define HW_APBHX_CTRL0 0x000
#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
#define BP_APBH_CTRL0_RESET_CHANNEL 16
#define HW_APBHX_CTRL1 0x010
#define HW_APBHX_CTRL2 0x020
#define HW_APBHX_CHANNEL_CTRL 0x030
#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
#define HW_APBX_VERSION 0x800
#define BP_APBHX_VERSION_MAJOR 24
#define HW_APBHX_CHn_NXTCMDAR(n) \
(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
#define HW_APBHX_CHn_SEMA(n) \
(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
/*
* ccw bits definitions
*
* COMMAND: 0..1 (2)
* CHAIN: 2 (1)
* IRQ: 3 (1)
* NAND_LOCK: 4 (1) - not implemented
* NAND_WAIT4READY: 5 (1) - not implemented
* DEC_SEM: 6 (1)
* WAIT4END: 7 (1)
* HALT_ON_TERMINATE: 8 (1)
* TERMINATE_FLUSH: 9 (1)
* RESERVED: 10..11 (2)
* PIO_NUM: 12..15 (4)
*/
#define BP_CCW_COMMAND 0
#define BM_CCW_COMMAND (3 << 0)
#define CCW_CHAIN (1 << 2)
#define CCW_IRQ (1 << 3)
#define CCW_DEC_SEM (1 << 6)
#define CCW_WAIT4END (1 << 7)
#define CCW_HALT_ON_TERM (1 << 8)
#define CCW_TERM_FLUSH (1 << 9)
#define BP_CCW_PIO_NUM 12
#define BM_CCW_PIO_NUM (0xf << 12)
#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
#define MXS_DMA_CMD_NO_XFER 0
#define MXS_DMA_CMD_WRITE 1
#define MXS_DMA_CMD_READ 2
#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
struct mxs_dma_ccw {
u32 next;
u16 bits;
u16 xfer_bytes;
#define MAX_XFER_BYTES 0xff00
u32 bufaddr;
#define MXS_PIO_WORDS 16
u32 pio_words[MXS_PIO_WORDS];
};
#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
struct mxs_dma_chan {
struct mxs_dma_engine *mxs_dma;
struct dma_chan chan;
struct dma_async_tx_descriptor desc;
struct tasklet_struct tasklet;
int chan_irq;
struct mxs_dma_ccw *ccw;
dma_addr_t ccw_phys;
int desc_count;
enum dma_status status;
unsigned int flags;
#define MXS_DMA_SG_LOOP (1 << 0)
};
#define MXS_DMA_CHANNELS 16
#define MXS_DMA_CHANNELS_MASK 0xffff
struct mxs_dma_engine {
int dev_id;
unsigned int version;
void __iomem *base;
struct clk *clk;
struct dma_device dma_device;
struct device_dma_parameters dma_parms;
struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
};
static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
{
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
int chan_id = mxs_chan->chan.chan_id;
if (dma_is_apbh() && apbh_is_old())
writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
else
writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
}
static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
{
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
int chan_id = mxs_chan->chan.chan_id;
/* set cmd_addr up */
writel(mxs_chan->ccw_phys,
mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
/* write 1 to SEMA to kick off the channel */
writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
}
static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
{
mxs_chan->status = DMA_SUCCESS;
}
static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
{
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
int chan_id = mxs_chan->chan.chan_id;
/* freeze the channel */
if (dma_is_apbh() && apbh_is_old())
writel(1 << chan_id,
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
else
writel(1 << chan_id,
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
mxs_chan->status = DMA_PAUSED;
}
static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
{
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
int chan_id = mxs_chan->chan.chan_id;
/* unfreeze the channel */
if (dma_is_apbh() && apbh_is_old())
writel(1 << chan_id,
mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
else
writel(1 << chan_id,
mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
mxs_chan->status = DMA_IN_PROGRESS;
}
static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
{
return container_of(chan, struct mxs_dma_chan, chan);
}
static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
return dma_cookie_assign(tx);
}
static void mxs_dma_tasklet(unsigned long data)
{
struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
if (mxs_chan->desc.callback)
mxs_chan->desc.callback(mxs_chan->desc.callback_param);
}
static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
{
struct mxs_dma_engine *mxs_dma = dev_id;
u32 stat1, stat2;
/* completion status */
stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
stat1 &= MXS_DMA_CHANNELS_MASK;
writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
/* error status */
stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
/*
* When both completion and error of termination bits set at the
* same time, we do not take it as an error. IOW, it only becomes
* an error we need to handle here in case of either it's (1) a bus
* error or (2) a termination error with no completion.
*/
stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
/* combine error and completion status for checking */
stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
while (stat1) {
int channel = fls(stat1) - 1;
struct mxs_dma_chan *mxs_chan =
&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
if (channel >= MXS_DMA_CHANNELS) {
dev_dbg(mxs_dma->dma_device.dev,
"%s: error in channel %d\n", __func__,
channel - MXS_DMA_CHANNELS);
mxs_chan->status = DMA_ERROR;
mxs_dma_reset_chan(mxs_chan);
} else {
if (mxs_chan->flags & MXS_DMA_SG_LOOP)
mxs_chan->status = DMA_IN_PROGRESS;
else
mxs_chan->status = DMA_SUCCESS;
}
stat1 &= ~(1 << channel);
if (mxs_chan->status == DMA_SUCCESS)
dma_cookie_complete(&mxs_chan->desc);
/* schedule tasklet on this channel */
tasklet_schedule(&mxs_chan->tasklet);
}
return IRQ_HANDLED;
}
static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
struct mxs_dma_data *data = chan->private;
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
int ret;
if (!data)
return -EINVAL;
mxs_chan->chan_irq = data->chan_irq;
mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
&mxs_chan->ccw_phys, GFP_KERNEL);
if (!mxs_chan->ccw) {
ret = -ENOMEM;
goto err_alloc;
}
memset(mxs_chan->ccw, 0, PAGE_SIZE);
if (mxs_chan->chan_irq != NO_IRQ) {
ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
0, "mxs-dma", mxs_dma);
if (ret)
goto err_irq;
}
ret = clk_prepare_enable(mxs_dma->clk);
if (ret)
goto err_clk;
mxs_dma_reset_chan(mxs_chan);
dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
/* the descriptor is ready */
async_tx_ack(&mxs_chan->desc);
return 0;
err_clk:
free_irq(mxs_chan->chan_irq, mxs_dma);
err_irq:
dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
mxs_chan->ccw, mxs_chan->ccw_phys);
err_alloc:
return ret;
}
static void mxs_dma_free_chan_resources(struct dma_chan *chan)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
mxs_dma_disable_chan(mxs_chan);
free_irq(mxs_chan->chan_irq, mxs_dma);
dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
mxs_chan->ccw, mxs_chan->ccw_phys);
clk_disable_unprepare(mxs_dma->clk);
}
/*
* How to use the flags for ->device_prep_slave_sg() :
* [1] If there is only one DMA command in the DMA chain, the code should be:
* ......
* ->device_prep_slave_sg(DMA_CTRL_ACK);
* ......
* [2] If there are two DMA commands in the DMA chain, the code should be
* ......
* ->device_prep_slave_sg(0);
* ......
* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
* ......
* [3] If there are more than two DMA commands in the DMA chain, the code
* should be:
* ......
* ->device_prep_slave_sg(0); // First
* ......
* ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
* ......
* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
* ......
*/
static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl,
unsigned int sg_len, enum dma_transfer_direction direction,
unsigned long flags, void *context)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
struct mxs_dma_ccw *ccw;
struct scatterlist *sg;
int i, j;
u32 *pio;
bool append = flags & DMA_PREP_INTERRUPT;
int idx = append ? mxs_chan->desc_count : 0;
if (mxs_chan->status == DMA_IN_PROGRESS && !append)
return NULL;
if (sg_len + (append ? idx : 0) > NUM_CCW) {
dev_err(mxs_dma->dma_device.dev,
"maximum number of sg exceeded: %d > %d\n",
sg_len, NUM_CCW);
goto err_out;
}
mxs_chan->status = DMA_IN_PROGRESS;
mxs_chan->flags = 0;
/*
* If the sg is prepared with append flag set, the sg
* will be appended to the last prepared sg.
*/
if (append) {
BUG_ON(idx < 1);
ccw = &mxs_chan->ccw[idx - 1];
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
ccw->bits |= CCW_CHAIN;
ccw->bits &= ~CCW_IRQ;
ccw->bits &= ~CCW_DEC_SEM;
} else {
idx = 0;
}
if (direction == DMA_TRANS_NONE) {
ccw = &mxs_chan->ccw[idx++];
pio = (u32 *) sgl;
for (j = 0; j < sg_len;)
ccw->pio_words[j++] = *pio++;
ccw->bits = 0;
ccw->bits |= CCW_IRQ;
ccw->bits |= CCW_DEC_SEM;
if (flags & DMA_CTRL_ACK)
ccw->bits |= CCW_WAIT4END;
ccw->bits |= CCW_HALT_ON_TERM;
ccw->bits |= CCW_TERM_FLUSH;
ccw->bits |= BF_CCW(sg_len, PIO_NUM);
ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
} else {
for_each_sg(sgl, sg, sg_len, i) {
if (sg->length > MAX_XFER_BYTES) {
dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
sg->length, MAX_XFER_BYTES);
goto err_out;
}
ccw = &mxs_chan->ccw[idx++];
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
ccw->bufaddr = sg->dma_address;
ccw->xfer_bytes = sg->length;
ccw->bits = 0;
ccw->bits |= CCW_CHAIN;
ccw->bits |= CCW_HALT_ON_TERM;
ccw->bits |= CCW_TERM_FLUSH;
ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
COMMAND);
if (i + 1 == sg_len) {
ccw->bits &= ~CCW_CHAIN;
ccw->bits |= CCW_IRQ;
ccw->bits |= CCW_DEC_SEM;
if (flags & DMA_CTRL_ACK)
ccw->bits |= CCW_WAIT4END;
}
}
}
mxs_chan->desc_count = idx;
return &mxs_chan->desc;
err_out:
mxs_chan->status = DMA_ERROR;
return NULL;
}
static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
size_t period_len, enum dma_transfer_direction direction,
void *context)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
int num_periods = buf_len / period_len;
int i = 0, buf = 0;
if (mxs_chan->status == DMA_IN_PROGRESS)
return NULL;
mxs_chan->status = DMA_IN_PROGRESS;
mxs_chan->flags |= MXS_DMA_SG_LOOP;
if (num_periods > NUM_CCW) {
dev_err(mxs_dma->dma_device.dev,
"maximum number of sg exceeded: %d > %d\n",
num_periods, NUM_CCW);
goto err_out;
}
if (period_len > MAX_XFER_BYTES) {
dev_err(mxs_dma->dma_device.dev,
"maximum period size exceeded: %d > %d\n",
period_len, MAX_XFER_BYTES);
goto err_out;
}
while (buf < buf_len) {
struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
if (i + 1 == num_periods)
ccw->next = mxs_chan->ccw_phys;
else
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
ccw->bufaddr = dma_addr;
ccw->xfer_bytes = period_len;
ccw->bits = 0;
ccw->bits |= CCW_CHAIN;
ccw->bits |= CCW_IRQ;
ccw->bits |= CCW_HALT_ON_TERM;
ccw->bits |= CCW_TERM_FLUSH;
ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
dma_addr += period_len;
buf += period_len;
i++;
}
mxs_chan->desc_count = i;
return &mxs_chan->desc;
err_out:
mxs_chan->status = DMA_ERROR;
return NULL;
}
static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
unsigned long arg)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
int ret = 0;
switch (cmd) {
case DMA_TERMINATE_ALL:
mxs_dma_reset_chan(mxs_chan);
mxs_dma_disable_chan(mxs_chan);
break;
case DMA_PAUSE:
mxs_dma_pause_chan(mxs_chan);
break;
case DMA_RESUME:
mxs_dma_resume_chan(mxs_chan);
break;
default:
ret = -ENOSYS;
}
return ret;
}
static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie, struct dma_tx_state *txstate)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
dma_cookie_t last_used;
last_used = chan->cookie;
dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
return mxs_chan->status;
}
static void mxs_dma_issue_pending(struct dma_chan *chan)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
mxs_dma_enable_chan(mxs_chan);
}
static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
{
int ret;
ret = clk_prepare_enable(mxs_dma->clk);
if (ret)
return ret;
ret = mxs_reset_block(mxs_dma->base);
if (ret)
goto err_out;
/* only major version matters */
mxs_dma->version = readl(mxs_dma->base +
((mxs_dma->dev_id == MXS_DMA_APBX) ?
HW_APBX_VERSION : HW_APBH_VERSION)) >>
BP_APBHX_VERSION_MAJOR;
/* enable apbh burst */
if (dma_is_apbh()) {
writel(BM_APBH_CTRL0_APB_BURST_EN,
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
writel(BM_APBH_CTRL0_APB_BURST8_EN,
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
}
/* enable irq for all the channels */
writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
err_out:
clk_disable_unprepare(mxs_dma->clk);
return ret;
}
static int __init mxs_dma_probe(struct platform_device *pdev)
{
const struct platform_device_id *id_entry =
platform_get_device_id(pdev);
struct mxs_dma_engine *mxs_dma;
struct resource *iores;
int ret, i;
mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
if (!mxs_dma)
return -ENOMEM;
mxs_dma->dev_id = id_entry->driver_data;
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!request_mem_region(iores->start, resource_size(iores),
pdev->name)) {
ret = -EBUSY;
goto err_request_region;
}
mxs_dma->base = ioremap(iores->start, resource_size(iores));
if (!mxs_dma->base) {
ret = -ENOMEM;
goto err_ioremap;
}
mxs_dma->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(mxs_dma->clk)) {
ret = PTR_ERR(mxs_dma->clk);
goto err_clk;
}
dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
/* Initialize channel parameters */
for (i = 0; i < MXS_DMA_CHANNELS; i++) {
struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
mxs_chan->mxs_dma = mxs_dma;
mxs_chan->chan.device = &mxs_dma->dma_device;
dma_cookie_init(&mxs_chan->chan);
tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
(unsigned long) mxs_chan);
/* Add the channel to mxs_chan list */
list_add_tail(&mxs_chan->chan.device_node,
&mxs_dma->dma_device.channels);
}
ret = mxs_dma_init(mxs_dma);
if (ret)
goto err_init;
mxs_dma->dma_device.dev = &pdev->dev;
/* mxs_dma gets 65535 bytes maximum sg size */
mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
mxs_dma->dma_device.device_control = mxs_dma_control;
mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
ret = dma_async_device_register(&mxs_dma->dma_device);
if (ret) {
dev_err(mxs_dma->dma_device.dev, "unable to register\n");
goto err_init;
}
dev_info(mxs_dma->dma_device.dev, "initialized\n");
return 0;
err_init:
clk_put(mxs_dma->clk);
err_clk:
iounmap(mxs_dma->base);
err_ioremap:
release_mem_region(iores->start, resource_size(iores));
err_request_region:
kfree(mxs_dma);
return ret;
}
static struct platform_device_id mxs_dma_type[] = {
{
.name = "mxs-dma-apbh",
.driver_data = MXS_DMA_APBH,
}, {
.name = "mxs-dma-apbx",
.driver_data = MXS_DMA_APBX,
}, {
/* end of list */
}
};
static struct platform_driver mxs_dma_driver = {
.driver = {
.name = "mxs-dma",
},
.id_table = mxs_dma_type,
};
static int __init mxs_dma_module_init(void)
{
return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
}
subsys_initcall(mxs_dma_module_init);
| gpl-2.0 |
Technux/linux | arch/sh/boards/board-edosk7760.c | 4783 | 4603 | /*
* Renesas Europe EDOSK7760 Board Support
*
* Copyright (C) 2008 SPES Societa' Progettazione Elettronica e Software Ltd.
* Author: Luca Santini <luca.santini@spesonline.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <linux/interrupt.h>
#include <linux/sh_intc.h>
#include <linux/i2c.h>
#include <linux/mtd/physmap.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/delay.h>
#include <asm/i2c-sh7760.h>
#include <asm/sizes.h>
/* Bus state controller registers for CS4 area */
#define BSC_CS4BCR 0xA4FD0010
#define BSC_CS4WCR 0xA4FD0030
#define SMC_IOBASE 0xA2000000
#define SMC_IO_OFFSET 0x300
#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET)
/* NOR flash */
static struct mtd_partition edosk7760_nor_flash_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE, /* Read-only */
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
}, {
.name = "fs",
.offset = MTDPART_OFS_APPEND,
.size = (26 << 20),
}, {
.name = "other",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data edosk7760_nor_flash_data = {
.width = 4,
.parts = edosk7760_nor_flash_partitions,
.nr_parts = ARRAY_SIZE(edosk7760_nor_flash_partitions),
};
static struct resource edosk7760_nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x00000000 + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device edosk7760_nor_flash_device = {
.name = "physmap-flash",
.resource = edosk7760_nor_flash_resources,
.num_resources = ARRAY_SIZE(edosk7760_nor_flash_resources),
.dev = {
.platform_data = &edosk7760_nor_flash_data,
},
};
/* i2c initialization functions */
static struct sh7760_i2c_platdata i2c_pd = {
.speed_khz = 400,
};
static struct resource sh7760_i2c1_res[] = {
{
.start = SH7760_I2C1_MMIO,
.end = SH7760_I2C1_MMIOEND,
.flags = IORESOURCE_MEM,
},{
.start = evt2irq(0x9e0),
.end = evt2irq(0x9e0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sh7760_i2c1_dev = {
.dev = {
.platform_data = &i2c_pd,
},
.name = SH7760_I2C_DEVNAME,
.id = 1,
.resource = sh7760_i2c1_res,
.num_resources = ARRAY_SIZE(sh7760_i2c1_res),
};
static struct resource sh7760_i2c0_res[] = {
{
.start = SH7760_I2C0_MMIO,
.end = SH7760_I2C0_MMIOEND,
.flags = IORESOURCE_MEM,
}, {
.start = evt2irq(0x9c0),
.end = evt2irq(0x9c0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sh7760_i2c0_dev = {
.dev = {
.platform_data = &i2c_pd,
},
.name = SH7760_I2C_DEVNAME,
.id = 0,
.resource = sh7760_i2c0_res,
.num_resources = ARRAY_SIZE(sh7760_i2c0_res),
};
/* eth initialization functions */
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL,
};
static struct resource smc91x_res[] = {
[0] = {
.start = SMC_IOADDR,
.end = SMC_IOADDR + SZ_32 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x2a0),
.end = evt2irq(0x2a0),
.flags = IORESOURCE_IRQ ,
}
};
static struct platform_device smc91x_dev = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91x_res),
.resource = smc91x_res,
.dev = {
.platform_data = &smc91x_info,
},
};
/* platform init code */
static struct platform_device *edosk7760_devices[] __initdata = {
&smc91x_dev,
&edosk7760_nor_flash_device,
&sh7760_i2c0_dev,
&sh7760_i2c1_dev,
};
static int __init init_edosk7760_devices(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ);
return platform_add_devices(edosk7760_devices,
ARRAY_SIZE(edosk7760_devices));
}
device_initcall(init_edosk7760_devices);
/*
* The Machine Vector
*/
struct sh_machine_vector mv_edosk7760 __initmv = {
.mv_name = "EDOSK7760",
};
| gpl-2.0 |
abusnooze/mint-v3.2-psp26 | arch/mips/bcm47xx/prom.c | 7855 | 5194 | /*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/bootinfo.h>
#include <asm/fw/cfe/cfe_api.h>
#include <asm/fw/cfe/cfe_error.h>
static int cfe_cons_handle;
const char *get_system_type(void)
{
return "Broadcom BCM47XX";
}
void prom_putchar(char c)
{
while (cfe_write(cfe_cons_handle, &c, 1) == 0)
;
}
static __init void prom_init_cfe(void)
{
uint32_t cfe_ept;
uint32_t cfe_handle;
uint32_t cfe_eptseal;
int argc = fw_arg0;
char **envp = (char **) fw_arg2;
int *prom_vec = (int *) fw_arg3;
/*
* Check if a loader was used; if NOT, the 4 arguments are
* what CFE gives us (handle, 0, EPT and EPTSEAL)
*/
if (argc < 0) {
cfe_handle = (uint32_t)argc;
cfe_ept = (uint32_t)envp;
cfe_eptseal = (uint32_t)prom_vec;
} else {
if ((int)prom_vec < 0) {
/*
* Old loader; all it gives us is the handle,
* so use the "known" entrypoint and assume
* the seal.
*/
cfe_handle = (uint32_t)prom_vec;
cfe_ept = 0xBFC00500;
cfe_eptseal = CFE_EPTSEAL;
} else {
/*
* Newer loaders bundle the handle/ept/eptseal
* Note: prom_vec is in the loader's useg
* which is still alive in the TLB.
*/
cfe_handle = prom_vec[0];
cfe_ept = prom_vec[2];
cfe_eptseal = prom_vec[3];
}
}
if (cfe_eptseal != CFE_EPTSEAL) {
/* too early for panic to do any good */
printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
while (1) ;
}
cfe_init(cfe_handle, cfe_ept);
}
static __init void prom_init_console(void)
{
/* Initialize CFE console */
cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
}
static __init void prom_init_cmdline(void)
{
static char buf[COMMAND_LINE_SIZE] __initdata;
/* Get the kernel command line from CFE */
if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
buf[COMMAND_LINE_SIZE - 1] = 0;
strcpy(arcs_cmdline, buf);
}
/* Force a console handover by adding a console= argument if needed,
* as CFE is not available anymore later in the boot process. */
if ((strstr(arcs_cmdline, "console=")) == NULL) {
/* Try to read the default serial port used by CFE */
if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
|| (strncmp("uart", buf, 4)))
/* Default to uart0 */
strcpy(buf, "uart0");
/* Compute the new command line */
snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
arcs_cmdline, buf[4]);
}
}
static __init void prom_init_mem(void)
{
unsigned long mem;
unsigned long max;
/* Figure out memory size by finding aliases.
*
* We should theoretically use the mapping from CFE using cfe_enummem().
* However as the BCM47XX is mostly used on low-memory systems, we
* want to reuse the memory used by CFE (around 4MB). That means cfe_*
* functions stop to work at some point during the boot, we should only
* call them at the beginning of the boot.
*
* BCM47XX uses 128MB for addressing the ram, if the system contains
* less that that amount of ram it remaps the ram more often into the
* available space.
* Accessing memory after 128MB will cause an exception.
* max contains the biggest possible address supported by the platform.
* If the method wants to try something above we assume 128MB ram.
*/
max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
if (((unsigned long)(prom_init) + mem) > max) {
mem = (128 << 20);
printk(KERN_DEBUG "assume 128MB RAM\n");
break;
}
if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
*(unsigned long *)(prom_init))
break;
}
add_memory_region(0, mem, BOOT_MEM_RAM);
}
void __init prom_init(void)
{
prom_init_cfe();
prom_init_console();
prom_init_cmdline();
prom_init_mem();
}
void __init prom_free_prom_memory(void)
{
}
| gpl-2.0 |
coolbho3k/kernel-roth | drivers/net/ethernet/xscale/ixp2000/enp2611.c | 9647 | 6201 | /*
* IXP2400 MSF network device driver for the Radisys ENP2611
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/moduleparam.h>
#include <asm/hardware/uengine.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include "ixpdev.h"
#include "caleb.h"
#include "ixp2400-msf.h"
#include "pm3386.h"
/***********************************************************************
* The Radisys ENP2611 is a PCI form factor board with three SFP GBIC
* slots, connected via two PMC/Sierra 3386s and an SPI-3 bridge FPGA
* to the IXP2400.
*
* +-------------+
* SFP GBIC #0 ---+ | +---------+
* | PM3386 #0 +-------+ |
* SFP GBIC #1 ---+ | | "Caleb" | +---------+
* +-------------+ | | | |
* | SPI-3 +---------+ IXP2400 |
* +-------------+ | bridge | | |
* SFP GBIC #2 ---+ | | FPGA | +---------+
* | PM3386 #1 +-------+ |
* | | +---------+
* +-------------+
* ^ ^ ^
* | 1.25Gbaud | 104MHz | 104MHz
* | SERDES ea. | SPI-3 ea. | SPI-3
*
***********************************************************************/
static struct ixp2400_msf_parameters enp2611_msf_parameters =
{
.rx_mode = IXP2400_RX_MODE_UTOPIA_POS |
IXP2400_RX_MODE_1x32 |
IXP2400_RX_MODE_MPHY |
IXP2400_RX_MODE_MPHY_32 |
IXP2400_RX_MODE_MPHY_POLLED_STATUS |
IXP2400_RX_MODE_MPHY_LEVEL3 |
IXP2400_RX_MODE_RBUF_SIZE_64,
.rxclk01_multiplier = IXP2400_PLL_MULTIPLIER_16,
.rx_poll_ports = 3,
.rx_channel_mode = {
IXP2400_PORT_RX_MODE_MASTER |
IXP2400_PORT_RX_MODE_POS_PHY |
IXP2400_PORT_RX_MODE_POS_PHY_L3 |
IXP2400_PORT_RX_MODE_ODD_PARITY |
IXP2400_PORT_RX_MODE_2_CYCLE_DECODE,
IXP2400_PORT_RX_MODE_MASTER |
IXP2400_PORT_RX_MODE_POS_PHY |
IXP2400_PORT_RX_MODE_POS_PHY_L3 |
IXP2400_PORT_RX_MODE_ODD_PARITY |
IXP2400_PORT_RX_MODE_2_CYCLE_DECODE,
IXP2400_PORT_RX_MODE_MASTER |
IXP2400_PORT_RX_MODE_POS_PHY |
IXP2400_PORT_RX_MODE_POS_PHY_L3 |
IXP2400_PORT_RX_MODE_ODD_PARITY |
IXP2400_PORT_RX_MODE_2_CYCLE_DECODE,
IXP2400_PORT_RX_MODE_MASTER |
IXP2400_PORT_RX_MODE_POS_PHY |
IXP2400_PORT_RX_MODE_POS_PHY_L3 |
IXP2400_PORT_RX_MODE_ODD_PARITY |
IXP2400_PORT_RX_MODE_2_CYCLE_DECODE
},
.tx_mode = IXP2400_TX_MODE_UTOPIA_POS |
IXP2400_TX_MODE_1x32 |
IXP2400_TX_MODE_MPHY |
IXP2400_TX_MODE_MPHY_32 |
IXP2400_TX_MODE_MPHY_POLLED_STATUS |
IXP2400_TX_MODE_MPHY_LEVEL3 |
IXP2400_TX_MODE_TBUF_SIZE_64,
.txclk01_multiplier = IXP2400_PLL_MULTIPLIER_16,
.tx_poll_ports = 3,
.tx_channel_mode = {
IXP2400_PORT_TX_MODE_MASTER |
IXP2400_PORT_TX_MODE_POS_PHY |
IXP2400_PORT_TX_MODE_ODD_PARITY |
IXP2400_PORT_TX_MODE_2_CYCLE_DECODE,
IXP2400_PORT_TX_MODE_MASTER |
IXP2400_PORT_TX_MODE_POS_PHY |
IXP2400_PORT_TX_MODE_ODD_PARITY |
IXP2400_PORT_TX_MODE_2_CYCLE_DECODE,
IXP2400_PORT_TX_MODE_MASTER |
IXP2400_PORT_TX_MODE_POS_PHY |
IXP2400_PORT_TX_MODE_ODD_PARITY |
IXP2400_PORT_TX_MODE_2_CYCLE_DECODE,
IXP2400_PORT_TX_MODE_MASTER |
IXP2400_PORT_TX_MODE_POS_PHY |
IXP2400_PORT_TX_MODE_ODD_PARITY |
IXP2400_PORT_TX_MODE_2_CYCLE_DECODE
}
};
static struct net_device *nds[3];
static struct timer_list link_check_timer;
/* @@@ Poll the SFP moddef0 line too. */
/* @@@ Try to use the pm3386 DOOL interrupt as well. */
static void enp2611_check_link_status(unsigned long __dummy)
{
int i;
for (i = 0; i < 3; i++) {
struct net_device *dev;
int status;
dev = nds[i];
if (dev == NULL)
continue;
status = pm3386_is_link_up(i);
if (status && !netif_carrier_ok(dev)) {
/* @@@ Should report autonegotiation status. */
printk(KERN_INFO "%s: NIC Link is Up\n", dev->name);
pm3386_enable_tx(i);
caleb_enable_tx(i);
netif_carrier_on(dev);
} else if (!status && netif_carrier_ok(dev)) {
printk(KERN_INFO "%s: NIC Link is Down\n", dev->name);
netif_carrier_off(dev);
caleb_disable_tx(i);
pm3386_disable_tx(i);
}
}
link_check_timer.expires = jiffies + HZ / 10;
add_timer(&link_check_timer);
}
static void enp2611_set_port_admin_status(int port, int up)
{
if (up) {
caleb_enable_rx(port);
pm3386_set_carrier(port, 1);
pm3386_enable_rx(port);
} else {
caleb_disable_tx(port);
pm3386_disable_tx(port);
/* @@@ Flush out pending packets. */
pm3386_set_carrier(port, 0);
pm3386_disable_rx(port);
caleb_disable_rx(port);
}
}
static int __init enp2611_init_module(void)
{
int ports;
int i;
if (!machine_is_enp2611())
return -ENODEV;
caleb_reset();
pm3386_reset();
ports = pm3386_port_count();
for (i = 0; i < ports; i++) {
nds[i] = ixpdev_alloc(i, sizeof(struct ixpdev_priv));
if (nds[i] == NULL) {
while (--i >= 0)
free_netdev(nds[i]);
return -ENOMEM;
}
pm3386_init_port(i);
pm3386_get_mac(i, nds[i]->dev_addr);
}
ixp2400_msf_init(&enp2611_msf_parameters);
if (ixpdev_init(ports, nds, enp2611_set_port_admin_status)) {
for (i = 0; i < ports; i++)
if (nds[i])
free_netdev(nds[i]);
return -EINVAL;
}
init_timer(&link_check_timer);
link_check_timer.function = enp2611_check_link_status;
link_check_timer.expires = jiffies;
add_timer(&link_check_timer);
return 0;
}
static void __exit enp2611_cleanup_module(void)
{
int i;
del_timer_sync(&link_check_timer);
ixpdev_deinit();
for (i = 0; i < 3; i++)
free_netdev(nds[i]);
}
module_init(enp2611_init_module);
module_exit(enp2611_cleanup_module);
MODULE_LICENSE("GPL");
| gpl-2.0 |
S3neos/android_kernel_samsung_s3ve3g | Documentation/laptops/hpfall.c | 10927 | 2486 | /* Disk protection for HP machines.
*
* Copyright 2008 Eric Piel
* Copyright 2009 Pavel Machek <pavel@ucw.cz>
*
* GPLv2.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <string.h>
#include <stdint.h>
#include <errno.h>
#include <signal.h>
#include <sys/mman.h>
#include <sched.h>
char unload_heads_path[64];
int set_unload_heads_path(char *device)
{
char devname[64];
if (strlen(device) <= 5 || strncmp(device, "/dev/", 5) != 0)
return -EINVAL;
strncpy(devname, device + 5, sizeof(devname));
snprintf(unload_heads_path, sizeof(unload_heads_path),
"/sys/block/%s/device/unload_heads", devname);
return 0;
}
int valid_disk(void)
{
int fd = open(unload_heads_path, O_RDONLY);
if (fd < 0) {
perror(unload_heads_path);
return 0;
}
close(fd);
return 1;
}
void write_int(char *path, int i)
{
char buf[1024];
int fd = open(path, O_RDWR);
if (fd < 0) {
perror("open");
exit(1);
}
sprintf(buf, "%d", i);
if (write(fd, buf, strlen(buf)) != strlen(buf)) {
perror("write");
exit(1);
}
close(fd);
}
void set_led(int on)
{
write_int("/sys/class/leds/hp::hddprotect/brightness", on);
}
void protect(int seconds)
{
write_int(unload_heads_path, seconds*1000);
}
int on_ac(void)
{
// /sys/class/power_supply/AC0/online
}
int lid_open(void)
{
// /proc/acpi/button/lid/LID/state
}
void ignore_me(void)
{
protect(0);
set_led(0);
}
int main(int argc, char **argv)
{
int fd, ret;
struct sched_param param;
if (argc == 1)
ret = set_unload_heads_path("/dev/sda");
else if (argc == 2)
ret = set_unload_heads_path(argv[1]);
else
ret = -EINVAL;
if (ret || !valid_disk()) {
fprintf(stderr, "usage: %s <device> (default: /dev/sda)\n",
argv[0]);
exit(1);
}
fd = open("/dev/freefall", O_RDONLY);
if (fd < 0) {
perror("/dev/freefall");
return EXIT_FAILURE;
}
daemon(0, 0);
param.sched_priority = sched_get_priority_max(SCHED_FIFO);
sched_setscheduler(0, SCHED_FIFO, ¶m);
mlockall(MCL_CURRENT|MCL_FUTURE);
signal(SIGALRM, ignore_me);
for (;;) {
unsigned char count;
ret = read(fd, &count, sizeof(count));
alarm(0);
if ((ret == -1) && (errno == EINTR)) {
/* Alarm expired, time to unpark the heads */
continue;
}
if (ret != sizeof(count)) {
perror("read");
break;
}
protect(21);
set_led(1);
if (1 || on_ac() || lid_open())
alarm(2);
else
alarm(20);
}
close(fd);
return EXIT_SUCCESS;
}
| gpl-2.0 |
huz123/bricked.tenderloin | fs/nfs/nfs4proc.c | 432 | 147765 | /*
* fs/nfs/nfs4proc.c
*
* Client-side procedure declarations for NFSv4.
*
* Copyright (c) 2002 The Regents of the University of Michigan.
* All rights reserved.
*
* Kendrick Smith <kmsmith@umich.edu>
* Andy Adamson <andros@umich.edu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/sunrpc/clnt.h>
#include <linux/nfs.h>
#include <linux/nfs4.h>
#include <linux/nfs_fs.h>
#include <linux/nfs_page.h>
#include <linux/namei.h>
#include <linux/mount.h>
#include <linux/module.h>
#include <linux/sunrpc/bc_xprt.h>
#include "nfs4_fs.h"
#include "delegation.h"
#include "internal.h"
#include "iostat.h"
#include "callback.h"
#define NFSDBG_FACILITY NFSDBG_PROC
#define NFS4_POLL_RETRY_MIN (HZ/10)
#define NFS4_POLL_RETRY_MAX (15*HZ)
#define NFS4_MAX_LOOP_ON_RECOVER (10)
struct nfs4_opendata;
static int _nfs4_proc_open(struct nfs4_opendata *data);
static int _nfs4_recover_proc_open(struct nfs4_opendata *data);
static int nfs4_do_fsinfo(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);
static int nfs4_async_handle_error(struct rpc_task *, const struct nfs_server *, struct nfs4_state *);
static int _nfs4_proc_lookup(struct inode *dir, const struct qstr *name, struct nfs_fh *fhandle, struct nfs_fattr *fattr);
static int _nfs4_proc_getattr(struct nfs_server *server, struct nfs_fh *fhandle, struct nfs_fattr *fattr);
static int nfs4_do_setattr(struct inode *inode, struct rpc_cred *cred,
struct nfs_fattr *fattr, struct iattr *sattr,
struct nfs4_state *state);
/* Prevent leaks of NFSv4 errors into userland */
static int nfs4_map_errors(int err)
{
if (err >= -1000)
return err;
switch (err) {
case -NFS4ERR_RESOURCE:
return -EREMOTEIO;
default:
dprintk("%s could not handle NFSv4 error %d\n",
__func__, -err);
break;
}
return -EIO;
}
/*
* This is our standard bitmap for GETATTR requests.
*/
const u32 nfs4_fattr_bitmap[2] = {
FATTR4_WORD0_TYPE
| FATTR4_WORD0_CHANGE
| FATTR4_WORD0_SIZE
| FATTR4_WORD0_FSID
| FATTR4_WORD0_FILEID,
FATTR4_WORD1_MODE
| FATTR4_WORD1_NUMLINKS
| FATTR4_WORD1_OWNER
| FATTR4_WORD1_OWNER_GROUP
| FATTR4_WORD1_RAWDEV
| FATTR4_WORD1_SPACE_USED
| FATTR4_WORD1_TIME_ACCESS
| FATTR4_WORD1_TIME_METADATA
| FATTR4_WORD1_TIME_MODIFY
};
const u32 nfs4_statfs_bitmap[2] = {
FATTR4_WORD0_FILES_AVAIL
| FATTR4_WORD0_FILES_FREE
| FATTR4_WORD0_FILES_TOTAL,
FATTR4_WORD1_SPACE_AVAIL
| FATTR4_WORD1_SPACE_FREE
| FATTR4_WORD1_SPACE_TOTAL
};
const u32 nfs4_pathconf_bitmap[2] = {
FATTR4_WORD0_MAXLINK
| FATTR4_WORD0_MAXNAME,
0
};
const u32 nfs4_fsinfo_bitmap[2] = { FATTR4_WORD0_MAXFILESIZE
| FATTR4_WORD0_MAXREAD
| FATTR4_WORD0_MAXWRITE
| FATTR4_WORD0_LEASE_TIME,
0
};
const u32 nfs4_fs_locations_bitmap[2] = {
FATTR4_WORD0_TYPE
| FATTR4_WORD0_CHANGE
| FATTR4_WORD0_SIZE
| FATTR4_WORD0_FSID
| FATTR4_WORD0_FILEID
| FATTR4_WORD0_FS_LOCATIONS,
FATTR4_WORD1_MODE
| FATTR4_WORD1_NUMLINKS
| FATTR4_WORD1_OWNER
| FATTR4_WORD1_OWNER_GROUP
| FATTR4_WORD1_RAWDEV
| FATTR4_WORD1_SPACE_USED
| FATTR4_WORD1_TIME_ACCESS
| FATTR4_WORD1_TIME_METADATA
| FATTR4_WORD1_TIME_MODIFY
| FATTR4_WORD1_MOUNTED_ON_FILEID
};
static void nfs4_setup_readdir(u64 cookie, __be32 *verifier, struct dentry *dentry,
struct nfs4_readdir_arg *readdir)
{
__be32 *start, *p;
BUG_ON(readdir->count < 80);
if (cookie > 2) {
readdir->cookie = cookie;
memcpy(&readdir->verifier, verifier, sizeof(readdir->verifier));
return;
}
readdir->cookie = 0;
memset(&readdir->verifier, 0, sizeof(readdir->verifier));
if (cookie == 2)
return;
/*
* NFSv4 servers do not return entries for '.' and '..'
* Therefore, we fake these entries here. We let '.'
* have cookie 0 and '..' have cookie 1. Note that
* when talking to the server, we always send cookie 0
* instead of 1 or 2.
*/
start = p = kmap_atomic(*readdir->pages, KM_USER0);
if (cookie == 0) {
*p++ = xdr_one; /* next */
*p++ = xdr_zero; /* cookie, first word */
*p++ = xdr_one; /* cookie, second word */
*p++ = xdr_one; /* entry len */
memcpy(p, ".\0\0\0", 4); /* entry */
p++;
*p++ = xdr_one; /* bitmap length */
*p++ = htonl(FATTR4_WORD0_FILEID); /* bitmap */
*p++ = htonl(8); /* attribute buffer length */
p = xdr_encode_hyper(p, NFS_FILEID(dentry->d_inode));
}
*p++ = xdr_one; /* next */
*p++ = xdr_zero; /* cookie, first word */
*p++ = xdr_two; /* cookie, second word */
*p++ = xdr_two; /* entry len */
memcpy(p, "..\0\0", 4); /* entry */
p++;
*p++ = xdr_one; /* bitmap length */
*p++ = htonl(FATTR4_WORD0_FILEID); /* bitmap */
*p++ = htonl(8); /* attribute buffer length */
p = xdr_encode_hyper(p, NFS_FILEID(dentry->d_parent->d_inode));
readdir->pgbase = (char *)p - (char *)start;
readdir->count -= readdir->pgbase;
kunmap_atomic(start, KM_USER0);
}
static int nfs4_wait_clnt_recover(struct nfs_client *clp)
{
int res;
might_sleep();
res = wait_on_bit(&clp->cl_state, NFS4CLNT_MANAGER_RUNNING,
nfs_wait_bit_killable, TASK_KILLABLE);
return res;
}
static int nfs4_delay(struct rpc_clnt *clnt, long *timeout)
{
int res = 0;
might_sleep();
if (*timeout <= 0)
*timeout = NFS4_POLL_RETRY_MIN;
if (*timeout > NFS4_POLL_RETRY_MAX)
*timeout = NFS4_POLL_RETRY_MAX;
schedule_timeout_killable(*timeout);
if (fatal_signal_pending(current))
res = -ERESTARTSYS;
*timeout <<= 1;
return res;
}
/* This is the error handling routine for processes that are allowed
* to sleep.
*/
static int nfs4_handle_exception(const struct nfs_server *server, int errorcode, struct nfs4_exception *exception)
{
struct nfs_client *clp = server->nfs_client;
struct nfs4_state *state = exception->state;
int ret = errorcode;
exception->retry = 0;
switch(errorcode) {
case 0:
return 0;
case -NFS4ERR_ADMIN_REVOKED:
case -NFS4ERR_BAD_STATEID:
case -NFS4ERR_OPENMODE:
if (state == NULL)
break;
nfs4_state_mark_reclaim_nograce(clp, state);
goto do_state_recovery;
case -NFS4ERR_STALE_STATEID:
if (state == NULL)
break;
nfs4_state_mark_reclaim_reboot(clp, state);
case -NFS4ERR_STALE_CLIENTID:
case -NFS4ERR_EXPIRED:
goto do_state_recovery;
#if defined(CONFIG_NFS_V4_1)
case -NFS4ERR_BADSESSION:
case -NFS4ERR_BADSLOT:
case -NFS4ERR_BAD_HIGH_SLOT:
case -NFS4ERR_CONN_NOT_BOUND_TO_SESSION:
case -NFS4ERR_DEADSESSION:
case -NFS4ERR_SEQ_FALSE_RETRY:
case -NFS4ERR_SEQ_MISORDERED:
dprintk("%s ERROR: %d Reset session\n", __func__,
errorcode);
nfs4_schedule_state_recovery(clp);
exception->retry = 1;
break;
#endif /* defined(CONFIG_NFS_V4_1) */
case -NFS4ERR_FILE_OPEN:
if (exception->timeout > HZ) {
/* We have retried a decent amount, time to
* fail
*/
ret = -EBUSY;
break;
}
case -NFS4ERR_GRACE:
case -NFS4ERR_DELAY:
case -EKEYEXPIRED:
ret = nfs4_delay(server->client, &exception->timeout);
if (ret != 0)
break;
case -NFS4ERR_OLD_STATEID:
exception->retry = 1;
}
/* We failed to handle the error */
return nfs4_map_errors(ret);
do_state_recovery:
nfs4_schedule_state_recovery(clp);
ret = nfs4_wait_clnt_recover(clp);
if (ret == 0)
exception->retry = 1;
return ret;
}
static void renew_lease(const struct nfs_server *server, unsigned long timestamp)
{
struct nfs_client *clp = server->nfs_client;
spin_lock(&clp->cl_lock);
if (time_before(clp->cl_last_renewal,timestamp))
clp->cl_last_renewal = timestamp;
spin_unlock(&clp->cl_lock);
}
#if defined(CONFIG_NFS_V4_1)
/*
* nfs4_free_slot - free a slot and efficiently update slot table.
*
* freeing a slot is trivially done by clearing its respective bit
* in the bitmap.
* If the freed slotid equals highest_used_slotid we want to update it
* so that the server would be able to size down the slot table if needed,
* otherwise we know that the highest_used_slotid is still in use.
* When updating highest_used_slotid there may be "holes" in the bitmap
* so we need to scan down from highest_used_slotid to 0 looking for the now
* highest slotid in use.
* If none found, highest_used_slotid is set to -1.
*
* Must be called while holding tbl->slot_tbl_lock
*/
static void
nfs4_free_slot(struct nfs4_slot_table *tbl, u8 free_slotid)
{
int slotid = free_slotid;
/* clear used bit in bitmap */
__clear_bit(slotid, tbl->used_slots);
/* update highest_used_slotid when it is freed */
if (slotid == tbl->highest_used_slotid) {
slotid = find_last_bit(tbl->used_slots, tbl->max_slots);
if (slotid < tbl->max_slots)
tbl->highest_used_slotid = slotid;
else
tbl->highest_used_slotid = -1;
}
dprintk("%s: free_slotid %u highest_used_slotid %d\n", __func__,
free_slotid, tbl->highest_used_slotid);
}
/*
* Signal state manager thread if session is drained
*/
static void nfs41_check_drain_session_complete(struct nfs4_session *ses)
{
struct rpc_task *task;
if (!test_bit(NFS4CLNT_SESSION_DRAINING, &ses->clp->cl_state)) {
task = rpc_wake_up_next(&ses->fc_slot_table.slot_tbl_waitq);
if (task)
rpc_task_set_priority(task, RPC_PRIORITY_PRIVILEGED);
return;
}
if (ses->fc_slot_table.highest_used_slotid != -1)
return;
dprintk("%s COMPLETE: Session Drained\n", __func__);
complete(&ses->complete);
}
static void nfs41_sequence_free_slot(const struct nfs_client *clp,
struct nfs4_sequence_res *res)
{
struct nfs4_slot_table *tbl;
tbl = &clp->cl_session->fc_slot_table;
if (res->sr_slotid == NFS4_MAX_SLOT_TABLE) {
/* just wake up the next guy waiting since
* we may have not consumed a slot after all */
dprintk("%s: No slot\n", __func__);
return;
}
spin_lock(&tbl->slot_tbl_lock);
nfs4_free_slot(tbl, res->sr_slotid);
nfs41_check_drain_session_complete(clp->cl_session);
spin_unlock(&tbl->slot_tbl_lock);
res->sr_slotid = NFS4_MAX_SLOT_TABLE;
}
static void nfs41_sequence_done(struct nfs_client *clp,
struct nfs4_sequence_res *res,
int rpc_status)
{
unsigned long timestamp;
struct nfs4_slot_table *tbl;
struct nfs4_slot *slot;
/*
* sr_status remains 1 if an RPC level error occurred. The server
* may or may not have processed the sequence operation..
* Proceed as if the server received and processed the sequence
* operation.
*/
if (res->sr_status == 1)
res->sr_status = NFS_OK;
/* -ERESTARTSYS can result in skipping nfs41_sequence_setup */
if (res->sr_slotid == NFS4_MAX_SLOT_TABLE)
goto out;
/* Check the SEQUENCE operation status */
if (res->sr_status == 0) {
tbl = &clp->cl_session->fc_slot_table;
slot = tbl->slots + res->sr_slotid;
/* Update the slot's sequence and clientid lease timer */
++slot->seq_nr;
timestamp = res->sr_renewal_time;
spin_lock(&clp->cl_lock);
if (time_before(clp->cl_last_renewal, timestamp))
clp->cl_last_renewal = timestamp;
spin_unlock(&clp->cl_lock);
/* Check sequence flags */
if (atomic_read(&clp->cl_count) > 1)
nfs41_handle_sequence_flag_errors(clp, res->sr_status_flags);
}
out:
/* The session may be reset by one of the error handlers. */
dprintk("%s: Error %d free the slot \n", __func__, res->sr_status);
nfs41_sequence_free_slot(clp, res);
}
/*
* nfs4_find_slot - efficiently look for a free slot
*
* nfs4_find_slot looks for an unset bit in the used_slots bitmap.
* If found, we mark the slot as used, update the highest_used_slotid,
* and respectively set up the sequence operation args.
* The slot number is returned if found, or NFS4_MAX_SLOT_TABLE otherwise.
*
* Note: must be called with under the slot_tbl_lock.
*/
static u8
nfs4_find_slot(struct nfs4_slot_table *tbl)
{
int slotid;
u8 ret_id = NFS4_MAX_SLOT_TABLE;
BUILD_BUG_ON((u8)NFS4_MAX_SLOT_TABLE != (int)NFS4_MAX_SLOT_TABLE);
dprintk("--> %s used_slots=%04lx highest_used=%d max_slots=%d\n",
__func__, tbl->used_slots[0], tbl->highest_used_slotid,
tbl->max_slots);
slotid = find_first_zero_bit(tbl->used_slots, tbl->max_slots);
if (slotid >= tbl->max_slots)
goto out;
__set_bit(slotid, tbl->used_slots);
if (slotid > tbl->highest_used_slotid)
tbl->highest_used_slotid = slotid;
ret_id = slotid;
out:
dprintk("<-- %s used_slots=%04lx highest_used=%d slotid=%d \n",
__func__, tbl->used_slots[0], tbl->highest_used_slotid, ret_id);
return ret_id;
}
static int nfs41_setup_sequence(struct nfs4_session *session,
struct nfs4_sequence_args *args,
struct nfs4_sequence_res *res,
int cache_reply,
struct rpc_task *task)
{
struct nfs4_slot *slot;
struct nfs4_slot_table *tbl;
u8 slotid;
dprintk("--> %s\n", __func__);
/* slot already allocated? */
if (res->sr_slotid != NFS4_MAX_SLOT_TABLE)
return 0;
memset(res, 0, sizeof(*res));
res->sr_slotid = NFS4_MAX_SLOT_TABLE;
tbl = &session->fc_slot_table;
spin_lock(&tbl->slot_tbl_lock);
if (test_bit(NFS4CLNT_SESSION_DRAINING, &session->clp->cl_state) &&
!rpc_task_has_priority(task, RPC_PRIORITY_PRIVILEGED)) {
/*
* The state manager will wait until the slot table is empty.
* Schedule the reset thread
*/
rpc_sleep_on(&tbl->slot_tbl_waitq, task, NULL);
spin_unlock(&tbl->slot_tbl_lock);
dprintk("%s Schedule Session Reset\n", __func__);
return -EAGAIN;
}
if (!rpc_queue_empty(&tbl->slot_tbl_waitq) &&
!rpc_task_has_priority(task, RPC_PRIORITY_PRIVILEGED)) {
rpc_sleep_on(&tbl->slot_tbl_waitq, task, NULL);
spin_unlock(&tbl->slot_tbl_lock);
dprintk("%s enforce FIFO order\n", __func__);
return -EAGAIN;
}
slotid = nfs4_find_slot(tbl);
if (slotid == NFS4_MAX_SLOT_TABLE) {
rpc_sleep_on(&tbl->slot_tbl_waitq, task, NULL);
spin_unlock(&tbl->slot_tbl_lock);
dprintk("<-- %s: no free slots\n", __func__);
return -EAGAIN;
}
spin_unlock(&tbl->slot_tbl_lock);
rpc_task_set_priority(task, RPC_PRIORITY_NORMAL);
slot = tbl->slots + slotid;
args->sa_session = session;
args->sa_slotid = slotid;
args->sa_cache_this = cache_reply;
dprintk("<-- %s slotid=%d seqid=%d\n", __func__, slotid, slot->seq_nr);
res->sr_session = session;
res->sr_slotid = slotid;
res->sr_renewal_time = jiffies;
/*
* sr_status is only set in decode_sequence, and so will remain
* set to 1 if an rpc level failure occurs.
*/
res->sr_status = 1;
return 0;
}
int nfs4_setup_sequence(struct nfs_client *clp,
struct nfs4_sequence_args *args,
struct nfs4_sequence_res *res,
int cache_reply,
struct rpc_task *task)
{
int ret = 0;
dprintk("--> %s clp %p session %p sr_slotid %d\n",
__func__, clp, clp->cl_session, res->sr_slotid);
if (!nfs4_has_session(clp))
goto out;
ret = nfs41_setup_sequence(clp->cl_session, args, res, cache_reply,
task);
if (ret && ret != -EAGAIN) {
/* terminate rpc task */
task->tk_status = ret;
task->tk_action = NULL;
}
out:
dprintk("<-- %s status=%d\n", __func__, ret);
return ret;
}
struct nfs41_call_sync_data {
struct nfs_client *clp;
struct nfs4_sequence_args *seq_args;
struct nfs4_sequence_res *seq_res;
int cache_reply;
};
static void nfs41_call_sync_prepare(struct rpc_task *task, void *calldata)
{
struct nfs41_call_sync_data *data = calldata;
dprintk("--> %s data->clp->cl_session %p\n", __func__,
data->clp->cl_session);
if (nfs4_setup_sequence(data->clp, data->seq_args,
data->seq_res, data->cache_reply, task))
return;
rpc_call_start(task);
}
static void nfs41_call_priv_sync_prepare(struct rpc_task *task, void *calldata)
{
rpc_task_set_priority(task, RPC_PRIORITY_PRIVILEGED);
nfs41_call_sync_prepare(task, calldata);
}
static void nfs41_call_sync_done(struct rpc_task *task, void *calldata)
{
struct nfs41_call_sync_data *data = calldata;
nfs41_sequence_done(data->clp, data->seq_res, task->tk_status);
}
struct rpc_call_ops nfs41_call_sync_ops = {
.rpc_call_prepare = nfs41_call_sync_prepare,
.rpc_call_done = nfs41_call_sync_done,
};
struct rpc_call_ops nfs41_call_priv_sync_ops = {
.rpc_call_prepare = nfs41_call_priv_sync_prepare,
.rpc_call_done = nfs41_call_sync_done,
};
static int nfs4_call_sync_sequence(struct nfs_client *clp,
struct rpc_clnt *clnt,
struct rpc_message *msg,
struct nfs4_sequence_args *args,
struct nfs4_sequence_res *res,
int cache_reply,
int privileged)
{
int ret;
struct rpc_task *task;
struct nfs41_call_sync_data data = {
.clp = clp,
.seq_args = args,
.seq_res = res,
.cache_reply = cache_reply,
};
struct rpc_task_setup task_setup = {
.rpc_client = clnt,
.rpc_message = msg,
.callback_ops = &nfs41_call_sync_ops,
.callback_data = &data
};
res->sr_slotid = NFS4_MAX_SLOT_TABLE;
if (privileged)
task_setup.callback_ops = &nfs41_call_priv_sync_ops;
task = rpc_run_task(&task_setup);
if (IS_ERR(task))
ret = PTR_ERR(task);
else {
ret = task->tk_status;
rpc_put_task(task);
}
return ret;
}
int _nfs4_call_sync_session(struct nfs_server *server,
struct rpc_message *msg,
struct nfs4_sequence_args *args,
struct nfs4_sequence_res *res,
int cache_reply)
{
return nfs4_call_sync_sequence(server->nfs_client, server->client,
msg, args, res, cache_reply, 0);
}
#endif /* CONFIG_NFS_V4_1 */
int _nfs4_call_sync(struct nfs_server *server,
struct rpc_message *msg,
struct nfs4_sequence_args *args,
struct nfs4_sequence_res *res,
int cache_reply)
{
args->sa_session = res->sr_session = NULL;
return rpc_call_sync(server->client, msg, 0);
}
#define nfs4_call_sync(server, msg, args, res, cache_reply) \
(server)->nfs_client->cl_call_sync((server), (msg), &(args)->seq_args, \
&(res)->seq_res, (cache_reply))
static void nfs4_sequence_done(const struct nfs_server *server,
struct nfs4_sequence_res *res, int rpc_status)
{
#ifdef CONFIG_NFS_V4_1
if (nfs4_has_session(server->nfs_client))
nfs41_sequence_done(server->nfs_client, res, rpc_status);
#endif /* CONFIG_NFS_V4_1 */
}
static void update_changeattr(struct inode *dir, struct nfs4_change_info *cinfo)
{
struct nfs_inode *nfsi = NFS_I(dir);
spin_lock(&dir->i_lock);
nfsi->cache_validity |= NFS_INO_INVALID_ATTR|NFS_INO_REVAL_PAGECACHE|NFS_INO_INVALID_DATA;
if (!cinfo->atomic || cinfo->before != nfsi->change_attr)
nfs_force_lookup_revalidate(dir);
nfsi->change_attr = cinfo->after;
spin_unlock(&dir->i_lock);
}
struct nfs4_opendata {
struct kref kref;
struct nfs_openargs o_arg;
struct nfs_openres o_res;
struct nfs_open_confirmargs c_arg;
struct nfs_open_confirmres c_res;
struct nfs_fattr f_attr;
struct nfs_fattr dir_attr;
struct path path;
struct dentry *dir;
struct nfs4_state_owner *owner;
struct nfs4_state *state;
struct iattr attrs;
unsigned long timestamp;
unsigned int rpc_done : 1;
int rpc_status;
int cancelled;
};
static void nfs4_init_opendata_res(struct nfs4_opendata *p)
{
p->o_res.f_attr = &p->f_attr;
p->o_res.dir_attr = &p->dir_attr;
p->o_res.seqid = p->o_arg.seqid;
p->c_res.seqid = p->c_arg.seqid;
p->o_res.server = p->o_arg.server;
nfs_fattr_init(&p->f_attr);
nfs_fattr_init(&p->dir_attr);
p->o_res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
}
static struct nfs4_opendata *nfs4_opendata_alloc(struct path *path,
struct nfs4_state_owner *sp, fmode_t fmode, int flags,
const struct iattr *attrs,
gfp_t gfp_mask)
{
struct dentry *parent = dget_parent(path->dentry);
struct inode *dir = parent->d_inode;
struct nfs_server *server = NFS_SERVER(dir);
struct nfs4_opendata *p;
p = kzalloc(sizeof(*p), gfp_mask);
if (p == NULL)
goto err;
p->o_arg.seqid = nfs_alloc_seqid(&sp->so_seqid, gfp_mask);
if (p->o_arg.seqid == NULL)
goto err_free;
path_get(path);
p->path = *path;
p->dir = parent;
p->owner = sp;
atomic_inc(&sp->so_count);
p->o_arg.fh = NFS_FH(dir);
p->o_arg.open_flags = flags;
p->o_arg.fmode = fmode & (FMODE_READ|FMODE_WRITE);
p->o_arg.clientid = server->nfs_client->cl_clientid;
p->o_arg.id = sp->so_owner_id.id;
p->o_arg.name = &p->path.dentry->d_name;
p->o_arg.server = server;
p->o_arg.bitmask = server->attr_bitmask;
p->o_arg.claim = NFS4_OPEN_CLAIM_NULL;
if (flags & O_EXCL) {
if (nfs4_has_persistent_session(server->nfs_client)) {
/* GUARDED */
p->o_arg.u.attrs = &p->attrs;
memcpy(&p->attrs, attrs, sizeof(p->attrs));
} else { /* EXCLUSIVE4_1 */
u32 *s = (u32 *) p->o_arg.u.verifier.data;
s[0] = jiffies;
s[1] = current->pid;
}
} else if (flags & O_CREAT) {
p->o_arg.u.attrs = &p->attrs;
memcpy(&p->attrs, attrs, sizeof(p->attrs));
}
p->c_arg.fh = &p->o_res.fh;
p->c_arg.stateid = &p->o_res.stateid;
p->c_arg.seqid = p->o_arg.seqid;
nfs4_init_opendata_res(p);
kref_init(&p->kref);
return p;
err_free:
kfree(p);
err:
dput(parent);
return NULL;
}
static void nfs4_opendata_free(struct kref *kref)
{
struct nfs4_opendata *p = container_of(kref,
struct nfs4_opendata, kref);
nfs_free_seqid(p->o_arg.seqid);
if (p->state != NULL)
nfs4_put_open_state(p->state);
nfs4_put_state_owner(p->owner);
dput(p->dir);
path_put(&p->path);
kfree(p);
}
static void nfs4_opendata_put(struct nfs4_opendata *p)
{
if (p != NULL)
kref_put(&p->kref, nfs4_opendata_free);
}
static int nfs4_wait_for_completion_rpc_task(struct rpc_task *task)
{
int ret;
ret = rpc_wait_for_completion_task(task);
return ret;
}
static int can_open_cached(struct nfs4_state *state, fmode_t mode, int open_mode)
{
int ret = 0;
if (open_mode & O_EXCL)
goto out;
switch (mode & (FMODE_READ|FMODE_WRITE)) {
case FMODE_READ:
ret |= test_bit(NFS_O_RDONLY_STATE, &state->flags) != 0
&& state->n_rdonly != 0;
break;
case FMODE_WRITE:
ret |= test_bit(NFS_O_WRONLY_STATE, &state->flags) != 0
&& state->n_wronly != 0;
break;
case FMODE_READ|FMODE_WRITE:
ret |= test_bit(NFS_O_RDWR_STATE, &state->flags) != 0
&& state->n_rdwr != 0;
}
out:
return ret;
}
static int can_open_delegated(struct nfs_delegation *delegation, fmode_t fmode)
{
if ((delegation->type & fmode) != fmode)
return 0;
if (test_bit(NFS_DELEGATION_NEED_RECLAIM, &delegation->flags))
return 0;
nfs_mark_delegation_referenced(delegation);
return 1;
}
static void update_open_stateflags(struct nfs4_state *state, fmode_t fmode)
{
switch (fmode) {
case FMODE_WRITE:
state->n_wronly++;
break;
case FMODE_READ:
state->n_rdonly++;
break;
case FMODE_READ|FMODE_WRITE:
state->n_rdwr++;
}
nfs4_state_set_mode_locked(state, state->state | fmode);
}
static void nfs_set_open_stateid_locked(struct nfs4_state *state, nfs4_stateid *stateid, fmode_t fmode)
{
if (test_bit(NFS_DELEGATED_STATE, &state->flags) == 0)
memcpy(state->stateid.data, stateid->data, sizeof(state->stateid.data));
memcpy(state->open_stateid.data, stateid->data, sizeof(state->open_stateid.data));
switch (fmode) {
case FMODE_READ:
set_bit(NFS_O_RDONLY_STATE, &state->flags);
break;
case FMODE_WRITE:
set_bit(NFS_O_WRONLY_STATE, &state->flags);
break;
case FMODE_READ|FMODE_WRITE:
set_bit(NFS_O_RDWR_STATE, &state->flags);
}
}
static void nfs_set_open_stateid(struct nfs4_state *state, nfs4_stateid *stateid, fmode_t fmode)
{
write_seqlock(&state->seqlock);
nfs_set_open_stateid_locked(state, stateid, fmode);
write_sequnlock(&state->seqlock);
}
static void __update_open_stateid(struct nfs4_state *state, nfs4_stateid *open_stateid, const nfs4_stateid *deleg_stateid, fmode_t fmode)
{
/*
* Protect the call to nfs4_state_set_mode_locked and
* serialise the stateid update
*/
write_seqlock(&state->seqlock);
if (deleg_stateid != NULL) {
memcpy(state->stateid.data, deleg_stateid->data, sizeof(state->stateid.data));
set_bit(NFS_DELEGATED_STATE, &state->flags);
}
if (open_stateid != NULL)
nfs_set_open_stateid_locked(state, open_stateid, fmode);
write_sequnlock(&state->seqlock);
spin_lock(&state->owner->so_lock);
update_open_stateflags(state, fmode);
spin_unlock(&state->owner->so_lock);
}
static int update_open_stateid(struct nfs4_state *state, nfs4_stateid *open_stateid, nfs4_stateid *delegation, fmode_t fmode)
{
struct nfs_inode *nfsi = NFS_I(state->inode);
struct nfs_delegation *deleg_cur;
int ret = 0;
fmode &= (FMODE_READ|FMODE_WRITE);
rcu_read_lock();
deleg_cur = rcu_dereference(nfsi->delegation);
if (deleg_cur == NULL)
goto no_delegation;
spin_lock(&deleg_cur->lock);
if (nfsi->delegation != deleg_cur ||
(deleg_cur->type & fmode) != fmode)
goto no_delegation_unlock;
if (delegation == NULL)
delegation = &deleg_cur->stateid;
else if (memcmp(deleg_cur->stateid.data, delegation->data, NFS4_STATEID_SIZE) != 0)
goto no_delegation_unlock;
nfs_mark_delegation_referenced(deleg_cur);
__update_open_stateid(state, open_stateid, &deleg_cur->stateid, fmode);
ret = 1;
no_delegation_unlock:
spin_unlock(&deleg_cur->lock);
no_delegation:
rcu_read_unlock();
if (!ret && open_stateid != NULL) {
__update_open_stateid(state, open_stateid, NULL, fmode);
ret = 1;
}
return ret;
}
static void nfs4_return_incompatible_delegation(struct inode *inode, fmode_t fmode)
{
struct nfs_delegation *delegation;
rcu_read_lock();
delegation = rcu_dereference(NFS_I(inode)->delegation);
if (delegation == NULL || (delegation->type & fmode) == fmode) {
rcu_read_unlock();
return;
}
rcu_read_unlock();
nfs_inode_return_delegation(inode);
}
static struct nfs4_state *nfs4_try_open_cached(struct nfs4_opendata *opendata)
{
struct nfs4_state *state = opendata->state;
struct nfs_inode *nfsi = NFS_I(state->inode);
struct nfs_delegation *delegation;
int open_mode = opendata->o_arg.open_flags & O_EXCL;
fmode_t fmode = opendata->o_arg.fmode;
nfs4_stateid stateid;
int ret = -EAGAIN;
for (;;) {
if (can_open_cached(state, fmode, open_mode)) {
spin_lock(&state->owner->so_lock);
if (can_open_cached(state, fmode, open_mode)) {
update_open_stateflags(state, fmode);
spin_unlock(&state->owner->so_lock);
goto out_return_state;
}
spin_unlock(&state->owner->so_lock);
}
rcu_read_lock();
delegation = rcu_dereference(nfsi->delegation);
if (delegation == NULL ||
!can_open_delegated(delegation, fmode)) {
rcu_read_unlock();
break;
}
/* Save the delegation */
memcpy(stateid.data, delegation->stateid.data, sizeof(stateid.data));
rcu_read_unlock();
ret = nfs_may_open(state->inode, state->owner->so_cred, open_mode);
if (ret != 0)
goto out;
ret = -EAGAIN;
/* Try to update the stateid using the delegation */
if (update_open_stateid(state, NULL, &stateid, fmode))
goto out_return_state;
}
out:
return ERR_PTR(ret);
out_return_state:
atomic_inc(&state->count);
return state;
}
static struct nfs4_state *nfs4_opendata_to_nfs4_state(struct nfs4_opendata *data)
{
struct inode *inode;
struct nfs4_state *state = NULL;
struct nfs_delegation *delegation;
int ret;
if (!data->rpc_done) {
state = nfs4_try_open_cached(data);
goto out;
}
ret = -EAGAIN;
if (!(data->f_attr.valid & NFS_ATTR_FATTR))
goto err;
inode = nfs_fhget(data->dir->d_sb, &data->o_res.fh, &data->f_attr);
ret = PTR_ERR(inode);
if (IS_ERR(inode))
goto err;
ret = -ENOMEM;
state = nfs4_get_open_state(inode, data->owner);
if (state == NULL)
goto err_put_inode;
if (data->o_res.delegation_type != 0) {
int delegation_flags = 0;
rcu_read_lock();
delegation = rcu_dereference(NFS_I(inode)->delegation);
if (delegation)
delegation_flags = delegation->flags;
rcu_read_unlock();
if ((delegation_flags & 1UL<<NFS_DELEGATION_NEED_RECLAIM) == 0)
nfs_inode_set_delegation(state->inode,
data->owner->so_cred,
&data->o_res);
else
nfs_inode_reclaim_delegation(state->inode,
data->owner->so_cred,
&data->o_res);
}
update_open_stateid(state, &data->o_res.stateid, NULL,
data->o_arg.fmode);
iput(inode);
out:
return state;
err_put_inode:
iput(inode);
err:
return ERR_PTR(ret);
}
static struct nfs_open_context *nfs4_state_find_open_context(struct nfs4_state *state)
{
struct nfs_inode *nfsi = NFS_I(state->inode);
struct nfs_open_context *ctx;
spin_lock(&state->inode->i_lock);
list_for_each_entry(ctx, &nfsi->open_files, list) {
if (ctx->state != state)
continue;
get_nfs_open_context(ctx);
spin_unlock(&state->inode->i_lock);
return ctx;
}
spin_unlock(&state->inode->i_lock);
return ERR_PTR(-ENOENT);
}
static struct nfs4_opendata *nfs4_open_recoverdata_alloc(struct nfs_open_context *ctx, struct nfs4_state *state)
{
struct nfs4_opendata *opendata;
opendata = nfs4_opendata_alloc(&ctx->path, state->owner, 0, 0, NULL, GFP_NOFS);
if (opendata == NULL)
return ERR_PTR(-ENOMEM);
opendata->state = state;
atomic_inc(&state->count);
return opendata;
}
static int nfs4_open_recover_helper(struct nfs4_opendata *opendata, fmode_t fmode, struct nfs4_state **res)
{
struct nfs4_state *newstate;
int ret;
opendata->o_arg.open_flags = 0;
opendata->o_arg.fmode = fmode;
memset(&opendata->o_res, 0, sizeof(opendata->o_res));
memset(&opendata->c_res, 0, sizeof(opendata->c_res));
nfs4_init_opendata_res(opendata);
ret = _nfs4_recover_proc_open(opendata);
if (ret != 0)
return ret;
newstate = nfs4_opendata_to_nfs4_state(opendata);
if (IS_ERR(newstate))
return PTR_ERR(newstate);
nfs4_close_state(&opendata->path, newstate, fmode);
*res = newstate;
return 0;
}
static int nfs4_open_recover(struct nfs4_opendata *opendata, struct nfs4_state *state)
{
struct nfs4_state *newstate;
int ret;
/* memory barrier prior to reading state->n_* */
clear_bit(NFS_DELEGATED_STATE, &state->flags);
smp_rmb();
if (state->n_rdwr != 0) {
ret = nfs4_open_recover_helper(opendata, FMODE_READ|FMODE_WRITE, &newstate);
if (ret != 0)
return ret;
if (newstate != state)
return -ESTALE;
}
if (state->n_wronly != 0) {
ret = nfs4_open_recover_helper(opendata, FMODE_WRITE, &newstate);
if (ret != 0)
return ret;
if (newstate != state)
return -ESTALE;
}
if (state->n_rdonly != 0) {
ret = nfs4_open_recover_helper(opendata, FMODE_READ, &newstate);
if (ret != 0)
return ret;
if (newstate != state)
return -ESTALE;
}
/*
* We may have performed cached opens for all three recoveries.
* Check if we need to update the current stateid.
*/
if (test_bit(NFS_DELEGATED_STATE, &state->flags) == 0 &&
memcmp(state->stateid.data, state->open_stateid.data, sizeof(state->stateid.data)) != 0) {
write_seqlock(&state->seqlock);
if (test_bit(NFS_DELEGATED_STATE, &state->flags) == 0)
memcpy(state->stateid.data, state->open_stateid.data, sizeof(state->stateid.data));
write_sequnlock(&state->seqlock);
}
return 0;
}
/*
* OPEN_RECLAIM:
* reclaim state on the server after a reboot.
*/
static int _nfs4_do_open_reclaim(struct nfs_open_context *ctx, struct nfs4_state *state)
{
struct nfs_delegation *delegation;
struct nfs4_opendata *opendata;
fmode_t delegation_type = 0;
int status;
opendata = nfs4_open_recoverdata_alloc(ctx, state);
if (IS_ERR(opendata))
return PTR_ERR(opendata);
opendata->o_arg.claim = NFS4_OPEN_CLAIM_PREVIOUS;
opendata->o_arg.fh = NFS_FH(state->inode);
rcu_read_lock();
delegation = rcu_dereference(NFS_I(state->inode)->delegation);
if (delegation != NULL && test_bit(NFS_DELEGATION_NEED_RECLAIM, &delegation->flags) != 0)
delegation_type = delegation->type;
rcu_read_unlock();
opendata->o_arg.u.delegation_type = delegation_type;
status = nfs4_open_recover(opendata, state);
nfs4_opendata_put(opendata);
return status;
}
static int nfs4_do_open_reclaim(struct nfs_open_context *ctx, struct nfs4_state *state)
{
struct nfs_server *server = NFS_SERVER(state->inode);
struct nfs4_exception exception = { };
int err;
do {
err = _nfs4_do_open_reclaim(ctx, state);
if (err != -NFS4ERR_DELAY && err != -EKEYEXPIRED)
break;
nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
return err;
}
static int nfs4_open_reclaim(struct nfs4_state_owner *sp, struct nfs4_state *state)
{
struct nfs_open_context *ctx;
int ret;
ctx = nfs4_state_find_open_context(state);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
ret = nfs4_do_open_reclaim(ctx, state);
put_nfs_open_context(ctx);
return ret;
}
static int _nfs4_open_delegation_recall(struct nfs_open_context *ctx, struct nfs4_state *state, const nfs4_stateid *stateid)
{
struct nfs4_opendata *opendata;
int ret;
opendata = nfs4_open_recoverdata_alloc(ctx, state);
if (IS_ERR(opendata))
return PTR_ERR(opendata);
opendata->o_arg.claim = NFS4_OPEN_CLAIM_DELEGATE_CUR;
memcpy(opendata->o_arg.u.delegation.data, stateid->data,
sizeof(opendata->o_arg.u.delegation.data));
ret = nfs4_open_recover(opendata, state);
nfs4_opendata_put(opendata);
return ret;
}
int nfs4_open_delegation_recall(struct nfs_open_context *ctx, struct nfs4_state *state, const nfs4_stateid *stateid)
{
struct nfs4_exception exception = { };
struct nfs_server *server = NFS_SERVER(state->inode);
int err;
do {
err = _nfs4_open_delegation_recall(ctx, state, stateid);
switch (err) {
case 0:
case -ENOENT:
case -ESTALE:
goto out;
case -NFS4ERR_BADSESSION:
case -NFS4ERR_BADSLOT:
case -NFS4ERR_BAD_HIGH_SLOT:
case -NFS4ERR_CONN_NOT_BOUND_TO_SESSION:
case -NFS4ERR_DEADSESSION:
nfs4_schedule_state_recovery(
server->nfs_client);
goto out;
case -NFS4ERR_STALE_CLIENTID:
case -NFS4ERR_STALE_STATEID:
case -NFS4ERR_EXPIRED:
/* Don't recall a delegation if it was lost */
nfs4_schedule_state_recovery(server->nfs_client);
goto out;
case -ERESTARTSYS:
/*
* The show must go on: exit, but mark the
* stateid as needing recovery.
*/
case -NFS4ERR_ADMIN_REVOKED:
case -NFS4ERR_BAD_STATEID:
nfs4_state_mark_reclaim_nograce(server->nfs_client, state);
case -ENOMEM:
err = 0;
goto out;
}
err = nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
out:
return err;
}
static void nfs4_open_confirm_done(struct rpc_task *task, void *calldata)
{
struct nfs4_opendata *data = calldata;
data->rpc_status = task->tk_status;
if (RPC_ASSASSINATED(task))
return;
if (data->rpc_status == 0) {
memcpy(data->o_res.stateid.data, data->c_res.stateid.data,
sizeof(data->o_res.stateid.data));
nfs_confirm_seqid(&data->owner->so_seqid, 0);
renew_lease(data->o_res.server, data->timestamp);
data->rpc_done = 1;
}
}
static void nfs4_open_confirm_release(void *calldata)
{
struct nfs4_opendata *data = calldata;
struct nfs4_state *state = NULL;
/* If this request hasn't been cancelled, do nothing */
if (data->cancelled == 0)
goto out_free;
/* In case of error, no cleanup! */
if (!data->rpc_done)
goto out_free;
state = nfs4_opendata_to_nfs4_state(data);
if (!IS_ERR(state))
nfs4_close_state(&data->path, state, data->o_arg.fmode);
out_free:
nfs4_opendata_put(data);
}
static const struct rpc_call_ops nfs4_open_confirm_ops = {
.rpc_call_done = nfs4_open_confirm_done,
.rpc_release = nfs4_open_confirm_release,
};
/*
* Note: On error, nfs4_proc_open_confirm will free the struct nfs4_opendata
*/
static int _nfs4_proc_open_confirm(struct nfs4_opendata *data)
{
struct nfs_server *server = NFS_SERVER(data->dir->d_inode);
struct rpc_task *task;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OPEN_CONFIRM],
.rpc_argp = &data->c_arg,
.rpc_resp = &data->c_res,
.rpc_cred = data->owner->so_cred,
};
struct rpc_task_setup task_setup_data = {
.rpc_client = server->client,
.rpc_message = &msg,
.callback_ops = &nfs4_open_confirm_ops,
.callback_data = data,
.workqueue = nfsiod_workqueue,
.flags = RPC_TASK_ASYNC,
};
int status;
kref_get(&data->kref);
data->rpc_done = 0;
data->rpc_status = 0;
data->timestamp = jiffies;
task = rpc_run_task(&task_setup_data);
if (IS_ERR(task))
return PTR_ERR(task);
status = nfs4_wait_for_completion_rpc_task(task);
if (status != 0) {
data->cancelled = 1;
smp_wmb();
} else
status = data->rpc_status;
rpc_put_task(task);
return status;
}
static void nfs4_open_prepare(struct rpc_task *task, void *calldata)
{
struct nfs4_opendata *data = calldata;
struct nfs4_state_owner *sp = data->owner;
if (nfs_wait_on_sequence(data->o_arg.seqid, task) != 0)
return;
/*
* Check if we still need to send an OPEN call, or if we can use
* a delegation instead.
*/
if (data->state != NULL) {
struct nfs_delegation *delegation;
if (can_open_cached(data->state, data->o_arg.fmode, data->o_arg.open_flags))
goto out_no_action;
rcu_read_lock();
delegation = rcu_dereference(NFS_I(data->state->inode)->delegation);
if (delegation != NULL &&
test_bit(NFS_DELEGATION_NEED_RECLAIM, &delegation->flags) == 0) {
rcu_read_unlock();
goto out_no_action;
}
rcu_read_unlock();
}
/* Update sequence id. */
data->o_arg.id = sp->so_owner_id.id;
data->o_arg.clientid = sp->so_client->cl_clientid;
if (data->o_arg.claim == NFS4_OPEN_CLAIM_PREVIOUS) {
task->tk_msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OPEN_NOATTR];
nfs_copy_fh(&data->o_res.fh, data->o_arg.fh);
}
data->timestamp = jiffies;
if (nfs4_setup_sequence(data->o_arg.server->nfs_client,
&data->o_arg.seq_args,
&data->o_res.seq_res, 1, task))
return;
rpc_call_start(task);
return;
out_no_action:
task->tk_action = NULL;
}
static void nfs4_recover_open_prepare(struct rpc_task *task, void *calldata)
{
rpc_task_set_priority(task, RPC_PRIORITY_PRIVILEGED);
nfs4_open_prepare(task, calldata);
}
static void nfs4_open_done(struct rpc_task *task, void *calldata)
{
struct nfs4_opendata *data = calldata;
data->rpc_status = task->tk_status;
nfs4_sequence_done(data->o_arg.server, &data->o_res.seq_res,
task->tk_status);
if (RPC_ASSASSINATED(task))
return;
if (task->tk_status == 0) {
switch (data->o_res.f_attr->mode & S_IFMT) {
case S_IFREG:
break;
case S_IFLNK:
data->rpc_status = -ELOOP;
break;
case S_IFDIR:
data->rpc_status = -EISDIR;
break;
default:
data->rpc_status = -ENOTDIR;
}
renew_lease(data->o_res.server, data->timestamp);
if (!(data->o_res.rflags & NFS4_OPEN_RESULT_CONFIRM))
nfs_confirm_seqid(&data->owner->so_seqid, 0);
}
data->rpc_done = 1;
}
static void nfs4_open_release(void *calldata)
{
struct nfs4_opendata *data = calldata;
struct nfs4_state *state = NULL;
/* If this request hasn't been cancelled, do nothing */
if (data->cancelled == 0)
goto out_free;
/* In case of error, no cleanup! */
if (data->rpc_status != 0 || !data->rpc_done)
goto out_free;
/* In case we need an open_confirm, no cleanup! */
if (data->o_res.rflags & NFS4_OPEN_RESULT_CONFIRM)
goto out_free;
state = nfs4_opendata_to_nfs4_state(data);
if (!IS_ERR(state))
nfs4_close_state(&data->path, state, data->o_arg.fmode);
out_free:
nfs4_opendata_put(data);
}
static const struct rpc_call_ops nfs4_open_ops = {
.rpc_call_prepare = nfs4_open_prepare,
.rpc_call_done = nfs4_open_done,
.rpc_release = nfs4_open_release,
};
static const struct rpc_call_ops nfs4_recover_open_ops = {
.rpc_call_prepare = nfs4_recover_open_prepare,
.rpc_call_done = nfs4_open_done,
.rpc_release = nfs4_open_release,
};
static int nfs4_run_open_task(struct nfs4_opendata *data, int isrecover)
{
struct inode *dir = data->dir->d_inode;
struct nfs_server *server = NFS_SERVER(dir);
struct nfs_openargs *o_arg = &data->o_arg;
struct nfs_openres *o_res = &data->o_res;
struct rpc_task *task;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OPEN],
.rpc_argp = o_arg,
.rpc_resp = o_res,
.rpc_cred = data->owner->so_cred,
};
struct rpc_task_setup task_setup_data = {
.rpc_client = server->client,
.rpc_message = &msg,
.callback_ops = &nfs4_open_ops,
.callback_data = data,
.workqueue = nfsiod_workqueue,
.flags = RPC_TASK_ASYNC,
};
int status;
kref_get(&data->kref);
data->rpc_done = 0;
data->rpc_status = 0;
data->cancelled = 0;
if (isrecover)
task_setup_data.callback_ops = &nfs4_recover_open_ops;
task = rpc_run_task(&task_setup_data);
if (IS_ERR(task))
return PTR_ERR(task);
status = nfs4_wait_for_completion_rpc_task(task);
if (status != 0) {
data->cancelled = 1;
smp_wmb();
} else
status = data->rpc_status;
rpc_put_task(task);
return status;
}
static int _nfs4_recover_proc_open(struct nfs4_opendata *data)
{
struct inode *dir = data->dir->d_inode;
struct nfs_openres *o_res = &data->o_res;
int status;
status = nfs4_run_open_task(data, 1);
if (status != 0 || !data->rpc_done)
return status;
nfs_refresh_inode(dir, o_res->dir_attr);
if (o_res->rflags & NFS4_OPEN_RESULT_CONFIRM) {
status = _nfs4_proc_open_confirm(data);
if (status != 0)
return status;
}
return status;
}
/*
* Note: On error, nfs4_proc_open will free the struct nfs4_opendata
*/
static int _nfs4_proc_open(struct nfs4_opendata *data)
{
struct inode *dir = data->dir->d_inode;
struct nfs_server *server = NFS_SERVER(dir);
struct nfs_openargs *o_arg = &data->o_arg;
struct nfs_openres *o_res = &data->o_res;
int status;
status = nfs4_run_open_task(data, 0);
if (status != 0 || !data->rpc_done)
return status;
if (o_arg->open_flags & O_CREAT) {
update_changeattr(dir, &o_res->cinfo);
nfs_post_op_update_inode(dir, o_res->dir_attr);
} else
nfs_refresh_inode(dir, o_res->dir_attr);
if ((o_res->rflags & NFS4_OPEN_RESULT_LOCKTYPE_POSIX) == 0)
server->caps &= ~NFS_CAP_POSIX_LOCK;
if(o_res->rflags & NFS4_OPEN_RESULT_CONFIRM) {
status = _nfs4_proc_open_confirm(data);
if (status != 0)
return status;
}
if (!(o_res->f_attr->valid & NFS_ATTR_FATTR))
_nfs4_proc_getattr(server, &o_res->fh, o_res->f_attr);
return 0;
}
static int nfs4_recover_expired_lease(struct nfs_server *server)
{
struct nfs_client *clp = server->nfs_client;
unsigned int loop;
int ret;
for (loop = NFS4_MAX_LOOP_ON_RECOVER; loop != 0; loop--) {
ret = nfs4_wait_clnt_recover(clp);
if (ret != 0)
break;
if (!test_bit(NFS4CLNT_LEASE_EXPIRED, &clp->cl_state) &&
!test_bit(NFS4CLNT_CHECK_LEASE,&clp->cl_state))
break;
nfs4_schedule_state_recovery(clp);
ret = -EIO;
}
return ret;
}
/*
* OPEN_EXPIRED:
* reclaim state on the server after a network partition.
* Assumes caller holds the appropriate lock
*/
static int _nfs4_open_expired(struct nfs_open_context *ctx, struct nfs4_state *state)
{
struct nfs4_opendata *opendata;
int ret;
opendata = nfs4_open_recoverdata_alloc(ctx, state);
if (IS_ERR(opendata))
return PTR_ERR(opendata);
ret = nfs4_open_recover(opendata, state);
if (ret == -ESTALE)
d_drop(ctx->path.dentry);
nfs4_opendata_put(opendata);
return ret;
}
static int nfs4_do_open_expired(struct nfs_open_context *ctx, struct nfs4_state *state)
{
struct nfs_server *server = NFS_SERVER(state->inode);
struct nfs4_exception exception = { };
int err;
do {
err = _nfs4_open_expired(ctx, state);
switch (err) {
default:
goto out;
case -NFS4ERR_GRACE:
case -NFS4ERR_DELAY:
case -EKEYEXPIRED:
nfs4_handle_exception(server, err, &exception);
err = 0;
}
} while (exception.retry);
out:
return err;
}
static int nfs4_open_expired(struct nfs4_state_owner *sp, struct nfs4_state *state)
{
struct nfs_open_context *ctx;
int ret;
ctx = nfs4_state_find_open_context(state);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
ret = nfs4_do_open_expired(ctx, state);
put_nfs_open_context(ctx);
return ret;
}
/*
* on an EXCLUSIVE create, the server should send back a bitmask with FATTR4-*
* fields corresponding to attributes that were used to store the verifier.
* Make sure we clobber those fields in the later setattr call
*/
static inline void nfs4_exclusive_attrset(struct nfs4_opendata *opendata, struct iattr *sattr)
{
if ((opendata->o_res.attrset[1] & FATTR4_WORD1_TIME_ACCESS) &&
!(sattr->ia_valid & ATTR_ATIME_SET))
sattr->ia_valid |= ATTR_ATIME;
if ((opendata->o_res.attrset[1] & FATTR4_WORD1_TIME_MODIFY) &&
!(sattr->ia_valid & ATTR_MTIME_SET))
sattr->ia_valid |= ATTR_MTIME;
}
/*
* Returns a referenced nfs4_state
*/
static int _nfs4_do_open(struct inode *dir, struct path *path, fmode_t fmode, int flags, struct iattr *sattr, struct rpc_cred *cred, struct nfs4_state **res)
{
struct nfs4_state_owner *sp;
struct nfs4_state *state = NULL;
struct nfs_server *server = NFS_SERVER(dir);
struct nfs4_opendata *opendata;
int status;
/* Protect against reboot recovery conflicts */
status = -ENOMEM;
if (!(sp = nfs4_get_state_owner(server, cred))) {
dprintk("nfs4_do_open: nfs4_get_state_owner failed!\n");
goto out_err;
}
status = nfs4_recover_expired_lease(server);
if (status != 0)
goto err_put_state_owner;
if (path->dentry->d_inode != NULL)
nfs4_return_incompatible_delegation(path->dentry->d_inode, fmode);
status = -ENOMEM;
opendata = nfs4_opendata_alloc(path, sp, fmode, flags, sattr, GFP_KERNEL);
if (opendata == NULL)
goto err_put_state_owner;
if (path->dentry->d_inode != NULL)
opendata->state = nfs4_get_open_state(path->dentry->d_inode, sp);
status = _nfs4_proc_open(opendata);
if (status != 0)
goto err_opendata_put;
state = nfs4_opendata_to_nfs4_state(opendata);
status = PTR_ERR(state);
if (IS_ERR(state))
goto err_opendata_put;
if (server->caps & NFS_CAP_POSIX_LOCK)
set_bit(NFS_STATE_POSIX_LOCKS, &state->flags);
if (opendata->o_arg.open_flags & O_EXCL) {
nfs4_exclusive_attrset(opendata, sattr);
nfs_fattr_init(opendata->o_res.f_attr);
status = nfs4_do_setattr(state->inode, cred,
opendata->o_res.f_attr, sattr,
state);
if (status == 0)
nfs_setattr_update_inode(state->inode, sattr);
nfs_post_op_update_inode(state->inode, opendata->o_res.f_attr);
}
nfs4_opendata_put(opendata);
nfs4_put_state_owner(sp);
*res = state;
return 0;
err_opendata_put:
nfs4_opendata_put(opendata);
err_put_state_owner:
nfs4_put_state_owner(sp);
out_err:
*res = NULL;
return status;
}
static struct nfs4_state *nfs4_do_open(struct inode *dir, struct path *path, fmode_t fmode, int flags, struct iattr *sattr, struct rpc_cred *cred)
{
struct nfs4_exception exception = { };
struct nfs4_state *res;
int status;
do {
status = _nfs4_do_open(dir, path, fmode, flags, sattr, cred, &res);
if (status == 0)
break;
/* NOTE: BAD_SEQID means the server and client disagree about the
* book-keeping w.r.t. state-changing operations
* (OPEN/CLOSE/LOCK/LOCKU...)
* It is actually a sign of a bug on the client or on the server.
*
* If we receive a BAD_SEQID error in the particular case of
* doing an OPEN, we assume that nfs_increment_open_seqid() will
* have unhashed the old state_owner for us, and that we can
* therefore safely retry using a new one. We should still warn
* the user though...
*/
if (status == -NFS4ERR_BAD_SEQID) {
printk(KERN_WARNING "NFS: v4 server %s "
" returned a bad sequence-id error!\n",
NFS_SERVER(dir)->nfs_client->cl_hostname);
exception.retry = 1;
continue;
}
/*
* BAD_STATEID on OPEN means that the server cancelled our
* state before it received the OPEN_CONFIRM.
* Recover by retrying the request as per the discussion
* on Page 181 of RFC3530.
*/
if (status == -NFS4ERR_BAD_STATEID) {
exception.retry = 1;
continue;
}
if (status == -EAGAIN) {
/* We must have found a delegation */
exception.retry = 1;
continue;
}
res = ERR_PTR(nfs4_handle_exception(NFS_SERVER(dir),
status, &exception));
} while (exception.retry);
return res;
}
static int _nfs4_do_setattr(struct inode *inode, struct rpc_cred *cred,
struct nfs_fattr *fattr, struct iattr *sattr,
struct nfs4_state *state)
{
struct nfs_server *server = NFS_SERVER(inode);
struct nfs_setattrargs arg = {
.fh = NFS_FH(inode),
.iap = sattr,
.server = server,
.bitmask = server->attr_bitmask,
};
struct nfs_setattrres res = {
.fattr = fattr,
.server = server,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SETATTR],
.rpc_argp = &arg,
.rpc_resp = &res,
.rpc_cred = cred,
};
unsigned long timestamp = jiffies;
int status;
nfs_fattr_init(fattr);
if (nfs4_copy_delegation_stateid(&arg.stateid, inode)) {
/* Use that stateid */
} else if (state != NULL) {
nfs4_copy_stateid(&arg.stateid, state, current->files);
} else
memcpy(&arg.stateid, &zero_stateid, sizeof(arg.stateid));
status = nfs4_call_sync(server, &msg, &arg, &res, 1);
if (status == 0 && state != NULL)
renew_lease(server, timestamp);
return status;
}
static int nfs4_do_setattr(struct inode *inode, struct rpc_cred *cred,
struct nfs_fattr *fattr, struct iattr *sattr,
struct nfs4_state *state)
{
struct nfs_server *server = NFS_SERVER(inode);
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_do_setattr(inode, cred, fattr, sattr, state),
&exception);
} while (exception.retry);
return err;
}
struct nfs4_closedata {
struct path path;
struct inode *inode;
struct nfs4_state *state;
struct nfs_closeargs arg;
struct nfs_closeres res;
struct nfs_fattr fattr;
unsigned long timestamp;
};
static void nfs4_free_closedata(void *data)
{
struct nfs4_closedata *calldata = data;
struct nfs4_state_owner *sp = calldata->state->owner;
nfs4_put_open_state(calldata->state);
nfs_free_seqid(calldata->arg.seqid);
nfs4_put_state_owner(sp);
path_put(&calldata->path);
kfree(calldata);
}
static void nfs4_close_clear_stateid_flags(struct nfs4_state *state,
fmode_t fmode)
{
spin_lock(&state->owner->so_lock);
if (!(fmode & FMODE_READ))
clear_bit(NFS_O_RDONLY_STATE, &state->flags);
if (!(fmode & FMODE_WRITE))
clear_bit(NFS_O_WRONLY_STATE, &state->flags);
clear_bit(NFS_O_RDWR_STATE, &state->flags);
spin_unlock(&state->owner->so_lock);
}
static void nfs4_close_done(struct rpc_task *task, void *data)
{
struct nfs4_closedata *calldata = data;
struct nfs4_state *state = calldata->state;
struct nfs_server *server = NFS_SERVER(calldata->inode);
nfs4_sequence_done(server, &calldata->res.seq_res, task->tk_status);
if (RPC_ASSASSINATED(task))
return;
/* hmm. we are done with the inode, and in the process of freeing
* the state_owner. we keep this around to process errors
*/
switch (task->tk_status) {
case 0:
nfs_set_open_stateid(state, &calldata->res.stateid, 0);
renew_lease(server, calldata->timestamp);
nfs4_close_clear_stateid_flags(state,
calldata->arg.fmode);
break;
case -NFS4ERR_STALE_STATEID:
case -NFS4ERR_OLD_STATEID:
case -NFS4ERR_BAD_STATEID:
case -NFS4ERR_EXPIRED:
if (calldata->arg.fmode == 0)
break;
default:
if (nfs4_async_handle_error(task, server, state) == -EAGAIN)
rpc_restart_call_prepare(task);
}
nfs_release_seqid(calldata->arg.seqid);
nfs_refresh_inode(calldata->inode, calldata->res.fattr);
}
static void nfs4_close_prepare(struct rpc_task *task, void *data)
{
struct nfs4_closedata *calldata = data;
struct nfs4_state *state = calldata->state;
int call_close = 0;
if (nfs_wait_on_sequence(calldata->arg.seqid, task) != 0)
return;
task->tk_msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OPEN_DOWNGRADE];
calldata->arg.fmode = FMODE_READ|FMODE_WRITE;
spin_lock(&state->owner->so_lock);
/* Calculate the change in open mode */
if (state->n_rdwr == 0) {
if (state->n_rdonly == 0) {
call_close |= test_bit(NFS_O_RDONLY_STATE, &state->flags);
call_close |= test_bit(NFS_O_RDWR_STATE, &state->flags);
calldata->arg.fmode &= ~FMODE_READ;
}
if (state->n_wronly == 0) {
call_close |= test_bit(NFS_O_WRONLY_STATE, &state->flags);
call_close |= test_bit(NFS_O_RDWR_STATE, &state->flags);
calldata->arg.fmode &= ~FMODE_WRITE;
}
}
spin_unlock(&state->owner->so_lock);
if (!call_close) {
/* Note: exit _without_ calling nfs4_close_done */
task->tk_action = NULL;
return;
}
if (calldata->arg.fmode == 0)
task->tk_msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_CLOSE];
nfs_fattr_init(calldata->res.fattr);
calldata->timestamp = jiffies;
if (nfs4_setup_sequence((NFS_SERVER(calldata->inode))->nfs_client,
&calldata->arg.seq_args, &calldata->res.seq_res,
1, task))
return;
rpc_call_start(task);
}
static const struct rpc_call_ops nfs4_close_ops = {
.rpc_call_prepare = nfs4_close_prepare,
.rpc_call_done = nfs4_close_done,
.rpc_release = nfs4_free_closedata,
};
/*
* It is possible for data to be read/written from a mem-mapped file
* after the sys_close call (which hits the vfs layer as a flush).
* This means that we can't safely call nfsv4 close on a file until
* the inode is cleared. This in turn means that we are not good
* NFSv4 citizens - we do not indicate to the server to update the file's
* share state even when we are done with one of the three share
* stateid's in the inode.
*
* NOTE: Caller must be holding the sp->so_owner semaphore!
*/
int nfs4_do_close(struct path *path, struct nfs4_state *state, gfp_t gfp_mask, int wait)
{
struct nfs_server *server = NFS_SERVER(state->inode);
struct nfs4_closedata *calldata;
struct nfs4_state_owner *sp = state->owner;
struct rpc_task *task;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_CLOSE],
.rpc_cred = state->owner->so_cred,
};
struct rpc_task_setup task_setup_data = {
.rpc_client = server->client,
.rpc_message = &msg,
.callback_ops = &nfs4_close_ops,
.workqueue = nfsiod_workqueue,
.flags = RPC_TASK_ASYNC,
};
int status = -ENOMEM;
calldata = kzalloc(sizeof(*calldata), gfp_mask);
if (calldata == NULL)
goto out;
calldata->inode = state->inode;
calldata->state = state;
calldata->arg.fh = NFS_FH(state->inode);
calldata->arg.stateid = &state->open_stateid;
/* Serialization for the sequence id */
calldata->arg.seqid = nfs_alloc_seqid(&state->owner->so_seqid, gfp_mask);
if (calldata->arg.seqid == NULL)
goto out_free_calldata;
calldata->arg.fmode = 0;
calldata->arg.bitmask = server->cache_consistency_bitmask;
calldata->res.fattr = &calldata->fattr;
calldata->res.seqid = calldata->arg.seqid;
calldata->res.server = server;
calldata->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
path_get(path);
calldata->path = *path;
msg.rpc_argp = &calldata->arg,
msg.rpc_resp = &calldata->res,
task_setup_data.callback_data = calldata;
task = rpc_run_task(&task_setup_data);
if (IS_ERR(task))
return PTR_ERR(task);
status = 0;
if (wait)
status = rpc_wait_for_completion_task(task);
rpc_put_task(task);
return status;
out_free_calldata:
kfree(calldata);
out:
nfs4_put_open_state(state);
nfs4_put_state_owner(sp);
return status;
}
static int nfs4_intent_set_file(struct nameidata *nd, struct path *path, struct nfs4_state *state, fmode_t fmode)
{
struct file *filp;
int ret;
/* If the open_intent is for execute, we have an extra check to make */
if (fmode & FMODE_EXEC) {
ret = nfs_may_open(state->inode,
state->owner->so_cred,
nd->intent.open.flags);
if (ret < 0)
goto out_close;
}
filp = lookup_instantiate_filp(nd, path->dentry, NULL);
if (!IS_ERR(filp)) {
struct nfs_open_context *ctx;
ctx = nfs_file_open_context(filp);
ctx->state = state;
return 0;
}
ret = PTR_ERR(filp);
out_close:
nfs4_close_sync(path, state, fmode & (FMODE_READ|FMODE_WRITE));
return ret;
}
struct dentry *
nfs4_atomic_open(struct inode *dir, struct dentry *dentry, struct nameidata *nd)
{
struct path path = {
.mnt = nd->path.mnt,
.dentry = dentry,
};
struct dentry *parent;
struct iattr attr;
struct rpc_cred *cred;
struct nfs4_state *state;
struct dentry *res;
int open_flags = nd->intent.open.flags;
fmode_t fmode = open_flags & (FMODE_READ | FMODE_WRITE | FMODE_EXEC);
if (nd->flags & LOOKUP_CREATE) {
attr.ia_mode = nd->intent.open.create_mode;
attr.ia_valid = ATTR_MODE;
if (!IS_POSIXACL(dir))
attr.ia_mode &= ~current_umask();
} else {
open_flags &= ~O_EXCL;
attr.ia_valid = 0;
BUG_ON(open_flags & O_CREAT);
}
cred = rpc_lookup_cred();
if (IS_ERR(cred))
return (struct dentry *)cred;
parent = dentry->d_parent;
/* Protect against concurrent sillydeletes */
nfs_block_sillyrename(parent);
state = nfs4_do_open(dir, &path, fmode, open_flags, &attr, cred);
put_rpccred(cred);
if (IS_ERR(state)) {
if (PTR_ERR(state) == -ENOENT) {
d_add(dentry, NULL);
nfs_set_verifier(dentry, nfs_save_change_attribute(dir));
}
nfs_unblock_sillyrename(parent);
return (struct dentry *)state;
}
res = d_add_unique(dentry, igrab(state->inode));
if (res != NULL)
path.dentry = res;
nfs_set_verifier(path.dentry, nfs_save_change_attribute(dir));
nfs_unblock_sillyrename(parent);
nfs4_intent_set_file(nd, &path, state, fmode);
return res;
}
int
nfs4_open_revalidate(struct inode *dir, struct dentry *dentry, int openflags, struct nameidata *nd)
{
struct path path = {
.mnt = nd->path.mnt,
.dentry = dentry,
};
struct rpc_cred *cred;
struct nfs4_state *state;
fmode_t fmode = openflags & (FMODE_READ | FMODE_WRITE);
cred = rpc_lookup_cred();
if (IS_ERR(cred))
return PTR_ERR(cred);
state = nfs4_do_open(dir, &path, fmode, openflags, NULL, cred);
put_rpccred(cred);
if (IS_ERR(state)) {
switch (PTR_ERR(state)) {
case -EPERM:
case -EACCES:
case -EDQUOT:
case -ENOSPC:
case -EROFS:
return PTR_ERR(state);
default:
goto out_drop;
}
}
if (state->inode == dentry->d_inode) {
nfs_set_verifier(dentry, nfs_save_change_attribute(dir));
nfs4_intent_set_file(nd, &path, state, fmode);
return 1;
}
nfs4_close_sync(&path, state, fmode);
out_drop:
d_drop(dentry);
return 0;
}
static void nfs4_close_context(struct nfs_open_context *ctx, int is_sync)
{
if (ctx->state == NULL)
return;
if (is_sync)
nfs4_close_sync(&ctx->path, ctx->state, ctx->mode);
else
nfs4_close_state(&ctx->path, ctx->state, ctx->mode);
}
static int _nfs4_server_capabilities(struct nfs_server *server, struct nfs_fh *fhandle)
{
struct nfs4_server_caps_arg args = {
.fhandle = fhandle,
};
struct nfs4_server_caps_res res = {};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SERVER_CAPS],
.rpc_argp = &args,
.rpc_resp = &res,
};
int status;
status = nfs4_call_sync(server, &msg, &args, &res, 0);
if (status == 0) {
memcpy(server->attr_bitmask, res.attr_bitmask, sizeof(server->attr_bitmask));
server->caps &= ~(NFS_CAP_ACLS|NFS_CAP_HARDLINKS|
NFS_CAP_SYMLINKS|NFS_CAP_FILEID|
NFS_CAP_MODE|NFS_CAP_NLINK|NFS_CAP_OWNER|
NFS_CAP_OWNER_GROUP|NFS_CAP_ATIME|
NFS_CAP_CTIME|NFS_CAP_MTIME);
if (res.attr_bitmask[0] & FATTR4_WORD0_ACL)
server->caps |= NFS_CAP_ACLS;
if (res.has_links != 0)
server->caps |= NFS_CAP_HARDLINKS;
if (res.has_symlinks != 0)
server->caps |= NFS_CAP_SYMLINKS;
if (res.attr_bitmask[0] & FATTR4_WORD0_FILEID)
server->caps |= NFS_CAP_FILEID;
if (res.attr_bitmask[1] & FATTR4_WORD1_MODE)
server->caps |= NFS_CAP_MODE;
if (res.attr_bitmask[1] & FATTR4_WORD1_NUMLINKS)
server->caps |= NFS_CAP_NLINK;
if (res.attr_bitmask[1] & FATTR4_WORD1_OWNER)
server->caps |= NFS_CAP_OWNER;
if (res.attr_bitmask[1] & FATTR4_WORD1_OWNER_GROUP)
server->caps |= NFS_CAP_OWNER_GROUP;
if (res.attr_bitmask[1] & FATTR4_WORD1_TIME_ACCESS)
server->caps |= NFS_CAP_ATIME;
if (res.attr_bitmask[1] & FATTR4_WORD1_TIME_METADATA)
server->caps |= NFS_CAP_CTIME;
if (res.attr_bitmask[1] & FATTR4_WORD1_TIME_MODIFY)
server->caps |= NFS_CAP_MTIME;
memcpy(server->cache_consistency_bitmask, res.attr_bitmask, sizeof(server->cache_consistency_bitmask));
server->cache_consistency_bitmask[0] &= FATTR4_WORD0_CHANGE|FATTR4_WORD0_SIZE;
server->cache_consistency_bitmask[1] &= FATTR4_WORD1_TIME_METADATA|FATTR4_WORD1_TIME_MODIFY;
server->acl_bitmask = res.acl_bitmask;
}
return status;
}
int nfs4_server_capabilities(struct nfs_server *server, struct nfs_fh *fhandle)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_server_capabilities(server, fhandle),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_lookup_root(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_fsinfo *info)
{
struct nfs4_lookup_root_arg args = {
.bitmask = nfs4_fattr_bitmap,
};
struct nfs4_lookup_res res = {
.server = server,
.fattr = info->fattr,
.fh = fhandle,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_LOOKUP_ROOT],
.rpc_argp = &args,
.rpc_resp = &res,
};
nfs_fattr_init(info->fattr);
return nfs4_call_sync(server, &msg, &args, &res, 0);
}
static int nfs4_lookup_root(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_fsinfo *info)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_lookup_root(server, fhandle, info),
&exception);
} while (exception.retry);
return err;
}
/*
* get the file handle for the "/" directory on the server
*/
static int nfs4_proc_get_root(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_fsinfo *info)
{
int status;
status = nfs4_lookup_root(server, fhandle, info);
if (status == 0)
status = nfs4_server_capabilities(server, fhandle);
if (status == 0)
status = nfs4_do_fsinfo(server, fhandle, info);
return nfs4_map_errors(status);
}
/*
* Get locations and (maybe) other attributes of a referral.
* Note that we'll actually follow the referral later when
* we detect fsid mismatch in inode revalidation
*/
static int nfs4_get_referral(struct inode *dir, const struct qstr *name, struct nfs_fattr *fattr, struct nfs_fh *fhandle)
{
int status = -ENOMEM;
struct page *page = NULL;
struct nfs4_fs_locations *locations = NULL;
page = alloc_page(GFP_KERNEL);
if (page == NULL)
goto out;
locations = kmalloc(sizeof(struct nfs4_fs_locations), GFP_KERNEL);
if (locations == NULL)
goto out;
status = nfs4_proc_fs_locations(dir, name, locations, page);
if (status != 0)
goto out;
/* Make sure server returned a different fsid for the referral */
if (nfs_fsid_equal(&NFS_SERVER(dir)->fsid, &locations->fattr.fsid)) {
dprintk("%s: server did not return a different fsid for a referral at %s\n", __func__, name->name);
status = -EIO;
goto out;
}
memcpy(fattr, &locations->fattr, sizeof(struct nfs_fattr));
fattr->valid |= NFS_ATTR_FATTR_V4_REFERRAL;
if (!fattr->mode)
fattr->mode = S_IFDIR;
memset(fhandle, 0, sizeof(struct nfs_fh));
out:
if (page)
__free_page(page);
if (locations)
kfree(locations);
return status;
}
static int _nfs4_proc_getattr(struct nfs_server *server, struct nfs_fh *fhandle, struct nfs_fattr *fattr)
{
struct nfs4_getattr_arg args = {
.fh = fhandle,
.bitmask = server->attr_bitmask,
};
struct nfs4_getattr_res res = {
.fattr = fattr,
.server = server,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_GETATTR],
.rpc_argp = &args,
.rpc_resp = &res,
};
nfs_fattr_init(fattr);
return nfs4_call_sync(server, &msg, &args, &res, 0);
}
static int nfs4_proc_getattr(struct nfs_server *server, struct nfs_fh *fhandle, struct nfs_fattr *fattr)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_proc_getattr(server, fhandle, fattr),
&exception);
} while (exception.retry);
return err;
}
/*
* The file is not closed if it is opened due to the a request to change
* the size of the file. The open call will not be needed once the
* VFS layer lookup-intents are implemented.
*
* Close is called when the inode is destroyed.
* If we haven't opened the file for O_WRONLY, we
* need to in the size_change case to obtain a stateid.
*
* Got race?
* Because OPEN is always done by name in nfsv4, it is
* possible that we opened a different file by the same
* name. We can recognize this race condition, but we
* can't do anything about it besides returning an error.
*
* This will be fixed with VFS changes (lookup-intent).
*/
static int
nfs4_proc_setattr(struct dentry *dentry, struct nfs_fattr *fattr,
struct iattr *sattr)
{
struct inode *inode = dentry->d_inode;
struct rpc_cred *cred = NULL;
struct nfs4_state *state = NULL;
int status;
nfs_fattr_init(fattr);
/* Search for an existing open(O_WRITE) file */
if (sattr->ia_valid & ATTR_FILE) {
struct nfs_open_context *ctx;
ctx = nfs_file_open_context(sattr->ia_file);
if (ctx) {
cred = ctx->cred;
state = ctx->state;
}
}
status = nfs4_do_setattr(inode, cred, fattr, sattr, state);
if (status == 0)
nfs_setattr_update_inode(inode, sattr);
return status;
}
static int _nfs4_proc_lookupfh(struct nfs_server *server, const struct nfs_fh *dirfh,
const struct qstr *name, struct nfs_fh *fhandle,
struct nfs_fattr *fattr)
{
int status;
struct nfs4_lookup_arg args = {
.bitmask = server->attr_bitmask,
.dir_fh = dirfh,
.name = name,
};
struct nfs4_lookup_res res = {
.server = server,
.fattr = fattr,
.fh = fhandle,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_LOOKUP],
.rpc_argp = &args,
.rpc_resp = &res,
};
nfs_fattr_init(fattr);
dprintk("NFS call lookupfh %s\n", name->name);
status = nfs4_call_sync(server, &msg, &args, &res, 0);
dprintk("NFS reply lookupfh: %d\n", status);
return status;
}
static int nfs4_proc_lookupfh(struct nfs_server *server, struct nfs_fh *dirfh,
struct qstr *name, struct nfs_fh *fhandle,
struct nfs_fattr *fattr)
{
struct nfs4_exception exception = { };
int err;
do {
err = _nfs4_proc_lookupfh(server, dirfh, name, fhandle, fattr);
/* FIXME: !!!! */
if (err == -NFS4ERR_MOVED) {
err = -EREMOTE;
break;
}
err = nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_lookup(struct inode *dir, const struct qstr *name,
struct nfs_fh *fhandle, struct nfs_fattr *fattr)
{
int status;
dprintk("NFS call lookup %s\n", name->name);
status = _nfs4_proc_lookupfh(NFS_SERVER(dir), NFS_FH(dir), name, fhandle, fattr);
if (status == -NFS4ERR_MOVED)
status = nfs4_get_referral(dir, name, fattr, fhandle);
dprintk("NFS reply lookup: %d\n", status);
return status;
}
static int nfs4_proc_lookup(struct inode *dir, struct qstr *name, struct nfs_fh *fhandle, struct nfs_fattr *fattr)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(dir),
_nfs4_proc_lookup(dir, name, fhandle, fattr),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_access(struct inode *inode, struct nfs_access_entry *entry)
{
struct nfs_server *server = NFS_SERVER(inode);
struct nfs4_accessargs args = {
.fh = NFS_FH(inode),
.bitmask = server->attr_bitmask,
};
struct nfs4_accessres res = {
.server = server,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_ACCESS],
.rpc_argp = &args,
.rpc_resp = &res,
.rpc_cred = entry->cred,
};
int mode = entry->mask;
int status;
/*
* Determine which access bits we want to ask for...
*/
if (mode & MAY_READ)
args.access |= NFS4_ACCESS_READ;
if (S_ISDIR(inode->i_mode)) {
if (mode & MAY_WRITE)
args.access |= NFS4_ACCESS_MODIFY | NFS4_ACCESS_EXTEND | NFS4_ACCESS_DELETE;
if (mode & MAY_EXEC)
args.access |= NFS4_ACCESS_LOOKUP;
} else {
if (mode & MAY_WRITE)
args.access |= NFS4_ACCESS_MODIFY | NFS4_ACCESS_EXTEND;
if (mode & MAY_EXEC)
args.access |= NFS4_ACCESS_EXECUTE;
}
res.fattr = nfs_alloc_fattr();
if (res.fattr == NULL)
return -ENOMEM;
status = nfs4_call_sync(server, &msg, &args, &res, 0);
if (!status) {
entry->mask = 0;
if (res.access & NFS4_ACCESS_READ)
entry->mask |= MAY_READ;
if (res.access & (NFS4_ACCESS_MODIFY | NFS4_ACCESS_EXTEND | NFS4_ACCESS_DELETE))
entry->mask |= MAY_WRITE;
if (res.access & (NFS4_ACCESS_LOOKUP|NFS4_ACCESS_EXECUTE))
entry->mask |= MAY_EXEC;
nfs_refresh_inode(inode, res.fattr);
}
nfs_free_fattr(res.fattr);
return status;
}
static int nfs4_proc_access(struct inode *inode, struct nfs_access_entry *entry)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(inode),
_nfs4_proc_access(inode, entry),
&exception);
} while (exception.retry);
return err;
}
/*
* TODO: For the time being, we don't try to get any attributes
* along with any of the zero-copy operations READ, READDIR,
* READLINK, WRITE.
*
* In the case of the first three, we want to put the GETATTR
* after the read-type operation -- this is because it is hard
* to predict the length of a GETATTR response in v4, and thus
* align the READ data correctly. This means that the GETATTR
* may end up partially falling into the page cache, and we should
* shift it into the 'tail' of the xdr_buf before processing.
* To do this efficiently, we need to know the total length
* of data received, which doesn't seem to be available outside
* of the RPC layer.
*
* In the case of WRITE, we also want to put the GETATTR after
* the operation -- in this case because we want to make sure
* we get the post-operation mtime and size. This means that
* we can't use xdr_encode_pages() as written: we need a variant
* of it which would leave room in the 'tail' iovec.
*
* Both of these changes to the XDR layer would in fact be quite
* minor, but I decided to leave them for a subsequent patch.
*/
static int _nfs4_proc_readlink(struct inode *inode, struct page *page,
unsigned int pgbase, unsigned int pglen)
{
struct nfs4_readlink args = {
.fh = NFS_FH(inode),
.pgbase = pgbase,
.pglen = pglen,
.pages = &page,
};
struct nfs4_readlink_res res;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_READLINK],
.rpc_argp = &args,
.rpc_resp = &res,
};
return nfs4_call_sync(NFS_SERVER(inode), &msg, &args, &res, 0);
}
static int nfs4_proc_readlink(struct inode *inode, struct page *page,
unsigned int pgbase, unsigned int pglen)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(inode),
_nfs4_proc_readlink(inode, page, pgbase, pglen),
&exception);
} while (exception.retry);
return err;
}
/*
* Got race?
* We will need to arrange for the VFS layer to provide an atomic open.
* Until then, this create/open method is prone to inefficiency and race
* conditions due to the lookup, create, and open VFS calls from sys_open()
* placed on the wire.
*
* Given the above sorry state of affairs, I'm simply sending an OPEN.
* The file will be opened again in the subsequent VFS open call
* (nfs4_proc_file_open).
*
* The open for read will just hang around to be used by any process that
* opens the file O_RDONLY. This will all be resolved with the VFS changes.
*/
static int
nfs4_proc_create(struct inode *dir, struct dentry *dentry, struct iattr *sattr,
int flags, struct nameidata *nd)
{
struct path path = {
.mnt = nd->path.mnt,
.dentry = dentry,
};
struct nfs4_state *state;
struct rpc_cred *cred;
fmode_t fmode = flags & (FMODE_READ | FMODE_WRITE);
int status = 0;
cred = rpc_lookup_cred();
if (IS_ERR(cred)) {
status = PTR_ERR(cred);
goto out;
}
state = nfs4_do_open(dir, &path, fmode, flags, sattr, cred);
d_drop(dentry);
if (IS_ERR(state)) {
status = PTR_ERR(state);
goto out_putcred;
}
d_add(dentry, igrab(state->inode));
nfs_set_verifier(dentry, nfs_save_change_attribute(dir));
if (status == 0 && (nd->flags & LOOKUP_OPEN) != 0)
status = nfs4_intent_set_file(nd, &path, state, fmode);
else
nfs4_close_sync(&path, state, fmode);
out_putcred:
put_rpccred(cred);
out:
return status;
}
static int _nfs4_proc_remove(struct inode *dir, struct qstr *name)
{
struct nfs_server *server = NFS_SERVER(dir);
struct nfs_removeargs args = {
.fh = NFS_FH(dir),
.name.len = name->len,
.name.name = name->name,
.bitmask = server->attr_bitmask,
};
struct nfs_removeres res = {
.server = server,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_REMOVE],
.rpc_argp = &args,
.rpc_resp = &res,
};
int status = -ENOMEM;
res.dir_attr = nfs_alloc_fattr();
if (res.dir_attr == NULL)
goto out;
status = nfs4_call_sync(server, &msg, &args, &res, 1);
if (status == 0) {
update_changeattr(dir, &res.cinfo);
nfs_post_op_update_inode(dir, res.dir_attr);
}
nfs_free_fattr(res.dir_attr);
out:
return status;
}
static int nfs4_proc_remove(struct inode *dir, struct qstr *name)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(dir),
_nfs4_proc_remove(dir, name),
&exception);
} while (exception.retry);
return err;
}
static void nfs4_proc_unlink_setup(struct rpc_message *msg, struct inode *dir)
{
struct nfs_server *server = NFS_SERVER(dir);
struct nfs_removeargs *args = msg->rpc_argp;
struct nfs_removeres *res = msg->rpc_resp;
args->bitmask = server->cache_consistency_bitmask;
res->server = server;
msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_REMOVE];
}
static int nfs4_proc_unlink_done(struct rpc_task *task, struct inode *dir)
{
struct nfs_removeres *res = task->tk_msg.rpc_resp;
nfs4_sequence_done(res->server, &res->seq_res, task->tk_status);
if (nfs4_async_handle_error(task, res->server, NULL) == -EAGAIN)
return 0;
update_changeattr(dir, &res->cinfo);
nfs_post_op_update_inode(dir, res->dir_attr);
return 1;
}
static int _nfs4_proc_rename(struct inode *old_dir, struct qstr *old_name,
struct inode *new_dir, struct qstr *new_name)
{
struct nfs_server *server = NFS_SERVER(old_dir);
struct nfs4_rename_arg arg = {
.old_dir = NFS_FH(old_dir),
.new_dir = NFS_FH(new_dir),
.old_name = old_name,
.new_name = new_name,
.bitmask = server->attr_bitmask,
};
struct nfs4_rename_res res = {
.server = server,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_RENAME],
.rpc_argp = &arg,
.rpc_resp = &res,
};
int status = -ENOMEM;
res.old_fattr = nfs_alloc_fattr();
res.new_fattr = nfs_alloc_fattr();
if (res.old_fattr == NULL || res.new_fattr == NULL)
goto out;
status = nfs4_call_sync(server, &msg, &arg, &res, 1);
if (!status) {
update_changeattr(old_dir, &res.old_cinfo);
nfs_post_op_update_inode(old_dir, res.old_fattr);
update_changeattr(new_dir, &res.new_cinfo);
nfs_post_op_update_inode(new_dir, res.new_fattr);
}
out:
nfs_free_fattr(res.new_fattr);
nfs_free_fattr(res.old_fattr);
return status;
}
static int nfs4_proc_rename(struct inode *old_dir, struct qstr *old_name,
struct inode *new_dir, struct qstr *new_name)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(old_dir),
_nfs4_proc_rename(old_dir, old_name,
new_dir, new_name),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_link(struct inode *inode, struct inode *dir, struct qstr *name)
{
struct nfs_server *server = NFS_SERVER(inode);
struct nfs4_link_arg arg = {
.fh = NFS_FH(inode),
.dir_fh = NFS_FH(dir),
.name = name,
.bitmask = server->attr_bitmask,
};
struct nfs4_link_res res = {
.server = server,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_LINK],
.rpc_argp = &arg,
.rpc_resp = &res,
};
int status = -ENOMEM;
res.fattr = nfs_alloc_fattr();
res.dir_attr = nfs_alloc_fattr();
if (res.fattr == NULL || res.dir_attr == NULL)
goto out;
status = nfs4_call_sync(server, &msg, &arg, &res, 1);
if (!status) {
update_changeattr(dir, &res.cinfo);
nfs_post_op_update_inode(dir, res.dir_attr);
nfs_post_op_update_inode(inode, res.fattr);
}
out:
nfs_free_fattr(res.dir_attr);
nfs_free_fattr(res.fattr);
return status;
}
static int nfs4_proc_link(struct inode *inode, struct inode *dir, struct qstr *name)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(inode),
_nfs4_proc_link(inode, dir, name),
&exception);
} while (exception.retry);
return err;
}
struct nfs4_createdata {
struct rpc_message msg;
struct nfs4_create_arg arg;
struct nfs4_create_res res;
struct nfs_fh fh;
struct nfs_fattr fattr;
struct nfs_fattr dir_fattr;
};
static struct nfs4_createdata *nfs4_alloc_createdata(struct inode *dir,
struct qstr *name, struct iattr *sattr, u32 ftype)
{
struct nfs4_createdata *data;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (data != NULL) {
struct nfs_server *server = NFS_SERVER(dir);
data->msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_CREATE];
data->msg.rpc_argp = &data->arg;
data->msg.rpc_resp = &data->res;
data->arg.dir_fh = NFS_FH(dir);
data->arg.server = server;
data->arg.name = name;
data->arg.attrs = sattr;
data->arg.ftype = ftype;
data->arg.bitmask = server->attr_bitmask;
data->res.server = server;
data->res.fh = &data->fh;
data->res.fattr = &data->fattr;
data->res.dir_fattr = &data->dir_fattr;
nfs_fattr_init(data->res.fattr);
nfs_fattr_init(data->res.dir_fattr);
}
return data;
}
static int nfs4_do_create(struct inode *dir, struct dentry *dentry, struct nfs4_createdata *data)
{
int status = nfs4_call_sync(NFS_SERVER(dir), &data->msg,
&data->arg, &data->res, 1);
if (status == 0) {
update_changeattr(dir, &data->res.dir_cinfo);
nfs_post_op_update_inode(dir, data->res.dir_fattr);
status = nfs_instantiate(dentry, data->res.fh, data->res.fattr);
}
return status;
}
static void nfs4_free_createdata(struct nfs4_createdata *data)
{
kfree(data);
}
static int _nfs4_proc_symlink(struct inode *dir, struct dentry *dentry,
struct page *page, unsigned int len, struct iattr *sattr)
{
struct nfs4_createdata *data;
int status = -ENAMETOOLONG;
if (len > NFS4_MAXPATHLEN)
goto out;
status = -ENOMEM;
data = nfs4_alloc_createdata(dir, &dentry->d_name, sattr, NF4LNK);
if (data == NULL)
goto out;
data->msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SYMLINK];
data->arg.u.symlink.pages = &page;
data->arg.u.symlink.len = len;
status = nfs4_do_create(dir, dentry, data);
nfs4_free_createdata(data);
out:
return status;
}
static int nfs4_proc_symlink(struct inode *dir, struct dentry *dentry,
struct page *page, unsigned int len, struct iattr *sattr)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(dir),
_nfs4_proc_symlink(dir, dentry, page,
len, sattr),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_mkdir(struct inode *dir, struct dentry *dentry,
struct iattr *sattr)
{
struct nfs4_createdata *data;
int status = -ENOMEM;
data = nfs4_alloc_createdata(dir, &dentry->d_name, sattr, NF4DIR);
if (data == NULL)
goto out;
status = nfs4_do_create(dir, dentry, data);
nfs4_free_createdata(data);
out:
return status;
}
static int nfs4_proc_mkdir(struct inode *dir, struct dentry *dentry,
struct iattr *sattr)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(dir),
_nfs4_proc_mkdir(dir, dentry, sattr),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_readdir(struct dentry *dentry, struct rpc_cred *cred,
u64 cookie, struct page *page, unsigned int count, int plus)
{
struct inode *dir = dentry->d_inode;
struct nfs4_readdir_arg args = {
.fh = NFS_FH(dir),
.pages = &page,
.pgbase = 0,
.count = count,
.bitmask = NFS_SERVER(dentry->d_inode)->attr_bitmask,
};
struct nfs4_readdir_res res;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_READDIR],
.rpc_argp = &args,
.rpc_resp = &res,
.rpc_cred = cred,
};
int status;
dprintk("%s: dentry = %s/%s, cookie = %Lu\n", __func__,
dentry->d_parent->d_name.name,
dentry->d_name.name,
(unsigned long long)cookie);
nfs4_setup_readdir(cookie, NFS_COOKIEVERF(dir), dentry, &args);
res.pgbase = args.pgbase;
status = nfs4_call_sync(NFS_SERVER(dir), &msg, &args, &res, 0);
if (status == 0)
memcpy(NFS_COOKIEVERF(dir), res.verifier.data, NFS4_VERIFIER_SIZE);
nfs_invalidate_atime(dir);
dprintk("%s: returns %d\n", __func__, status);
return status;
}
static int nfs4_proc_readdir(struct dentry *dentry, struct rpc_cred *cred,
u64 cookie, struct page *page, unsigned int count, int plus)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(dentry->d_inode),
_nfs4_proc_readdir(dentry, cred, cookie,
page, count, plus),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_mknod(struct inode *dir, struct dentry *dentry,
struct iattr *sattr, dev_t rdev)
{
struct nfs4_createdata *data;
int mode = sattr->ia_mode;
int status = -ENOMEM;
BUG_ON(!(sattr->ia_valid & ATTR_MODE));
BUG_ON(!S_ISFIFO(mode) && !S_ISBLK(mode) && !S_ISCHR(mode) && !S_ISSOCK(mode));
data = nfs4_alloc_createdata(dir, &dentry->d_name, sattr, NF4SOCK);
if (data == NULL)
goto out;
if (S_ISFIFO(mode))
data->arg.ftype = NF4FIFO;
else if (S_ISBLK(mode)) {
data->arg.ftype = NF4BLK;
data->arg.u.device.specdata1 = MAJOR(rdev);
data->arg.u.device.specdata2 = MINOR(rdev);
}
else if (S_ISCHR(mode)) {
data->arg.ftype = NF4CHR;
data->arg.u.device.specdata1 = MAJOR(rdev);
data->arg.u.device.specdata2 = MINOR(rdev);
}
status = nfs4_do_create(dir, dentry, data);
nfs4_free_createdata(data);
out:
return status;
}
static int nfs4_proc_mknod(struct inode *dir, struct dentry *dentry,
struct iattr *sattr, dev_t rdev)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(dir),
_nfs4_proc_mknod(dir, dentry, sattr, rdev),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_proc_statfs(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_fsstat *fsstat)
{
struct nfs4_statfs_arg args = {
.fh = fhandle,
.bitmask = server->attr_bitmask,
};
struct nfs4_statfs_res res = {
.fsstat = fsstat,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_STATFS],
.rpc_argp = &args,
.rpc_resp = &res,
};
nfs_fattr_init(fsstat->fattr);
return nfs4_call_sync(server, &msg, &args, &res, 0);
}
static int nfs4_proc_statfs(struct nfs_server *server, struct nfs_fh *fhandle, struct nfs_fsstat *fsstat)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_proc_statfs(server, fhandle, fsstat),
&exception);
} while (exception.retry);
return err;
}
static int _nfs4_do_fsinfo(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_fsinfo *fsinfo)
{
struct nfs4_fsinfo_arg args = {
.fh = fhandle,
.bitmask = server->attr_bitmask,
};
struct nfs4_fsinfo_res res = {
.fsinfo = fsinfo,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_FSINFO],
.rpc_argp = &args,
.rpc_resp = &res,
};
return nfs4_call_sync(server, &msg, &args, &res, 0);
}
static int nfs4_do_fsinfo(struct nfs_server *server, struct nfs_fh *fhandle, struct nfs_fsinfo *fsinfo)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_do_fsinfo(server, fhandle, fsinfo),
&exception);
} while (exception.retry);
return err;
}
static int nfs4_proc_fsinfo(struct nfs_server *server, struct nfs_fh *fhandle, struct nfs_fsinfo *fsinfo)
{
nfs_fattr_init(fsinfo->fattr);
return nfs4_do_fsinfo(server, fhandle, fsinfo);
}
static int _nfs4_proc_pathconf(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_pathconf *pathconf)
{
struct nfs4_pathconf_arg args = {
.fh = fhandle,
.bitmask = server->attr_bitmask,
};
struct nfs4_pathconf_res res = {
.pathconf = pathconf,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_PATHCONF],
.rpc_argp = &args,
.rpc_resp = &res,
};
/* None of the pathconf attributes are mandatory to implement */
if ((args.bitmask[0] & nfs4_pathconf_bitmap[0]) == 0) {
memset(pathconf, 0, sizeof(*pathconf));
return 0;
}
nfs_fattr_init(pathconf->fattr);
return nfs4_call_sync(server, &msg, &args, &res, 0);
}
static int nfs4_proc_pathconf(struct nfs_server *server, struct nfs_fh *fhandle,
struct nfs_pathconf *pathconf)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(server,
_nfs4_proc_pathconf(server, fhandle, pathconf),
&exception);
} while (exception.retry);
return err;
}
static int nfs4_read_done(struct rpc_task *task, struct nfs_read_data *data)
{
struct nfs_server *server = NFS_SERVER(data->inode);
dprintk("--> %s\n", __func__);
nfs4_sequence_done(server, &data->res.seq_res, task->tk_status);
if (nfs4_async_handle_error(task, server, data->args.context->state) == -EAGAIN) {
nfs_restart_rpc(task, server->nfs_client);
return -EAGAIN;
}
nfs_invalidate_atime(data->inode);
if (task->tk_status > 0)
renew_lease(server, data->timestamp);
return 0;
}
static void nfs4_proc_read_setup(struct nfs_read_data *data, struct rpc_message *msg)
{
data->timestamp = jiffies;
msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_READ];
}
static int nfs4_write_done(struct rpc_task *task, struct nfs_write_data *data)
{
struct inode *inode = data->inode;
nfs4_sequence_done(NFS_SERVER(inode), &data->res.seq_res,
task->tk_status);
if (nfs4_async_handle_error(task, NFS_SERVER(inode), data->args.context->state) == -EAGAIN) {
nfs_restart_rpc(task, NFS_SERVER(inode)->nfs_client);
return -EAGAIN;
}
if (task->tk_status >= 0) {
renew_lease(NFS_SERVER(inode), data->timestamp);
nfs_post_op_update_inode_force_wcc(inode, data->res.fattr);
}
return 0;
}
static void nfs4_proc_write_setup(struct nfs_write_data *data, struct rpc_message *msg)
{
struct nfs_server *server = NFS_SERVER(data->inode);
data->args.bitmask = server->cache_consistency_bitmask;
data->res.server = server;
data->timestamp = jiffies;
msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_WRITE];
}
static int nfs4_commit_done(struct rpc_task *task, struct nfs_write_data *data)
{
struct inode *inode = data->inode;
nfs4_sequence_done(NFS_SERVER(inode), &data->res.seq_res,
task->tk_status);
if (nfs4_async_handle_error(task, NFS_SERVER(inode), NULL) == -EAGAIN) {
nfs_restart_rpc(task, NFS_SERVER(inode)->nfs_client);
return -EAGAIN;
}
nfs_refresh_inode(inode, data->res.fattr);
return 0;
}
static void nfs4_proc_commit_setup(struct nfs_write_data *data, struct rpc_message *msg)
{
struct nfs_server *server = NFS_SERVER(data->inode);
data->args.bitmask = server->cache_consistency_bitmask;
data->res.server = server;
msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_COMMIT];
}
struct nfs4_renewdata {
struct nfs_client *client;
unsigned long timestamp;
};
/*
* nfs4_proc_async_renew(): This is not one of the nfs_rpc_ops; it is a special
* standalone procedure for queueing an asynchronous RENEW.
*/
static void nfs4_renew_release(void *calldata)
{
struct nfs4_renewdata *data = calldata;
struct nfs_client *clp = data->client;
if (atomic_read(&clp->cl_count) > 1)
nfs4_schedule_state_renewal(clp);
nfs_put_client(clp);
kfree(data);
}
static void nfs4_renew_done(struct rpc_task *task, void *calldata)
{
struct nfs4_renewdata *data = calldata;
struct nfs_client *clp = data->client;
unsigned long timestamp = data->timestamp;
if (task->tk_status < 0) {
/* Unless we're shutting down, schedule state recovery! */
if (test_bit(NFS_CS_RENEWD, &clp->cl_res_state) != 0)
nfs4_schedule_state_recovery(clp);
return;
}
spin_lock(&clp->cl_lock);
if (time_before(clp->cl_last_renewal,timestamp))
clp->cl_last_renewal = timestamp;
spin_unlock(&clp->cl_lock);
}
static const struct rpc_call_ops nfs4_renew_ops = {
.rpc_call_done = nfs4_renew_done,
.rpc_release = nfs4_renew_release,
};
int nfs4_proc_async_renew(struct nfs_client *clp, struct rpc_cred *cred)
{
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_RENEW],
.rpc_argp = clp,
.rpc_cred = cred,
};
struct nfs4_renewdata *data;
if (!atomic_inc_not_zero(&clp->cl_count))
return -EIO;
data = kmalloc(sizeof(*data), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
data->client = clp;
data->timestamp = jiffies;
return rpc_call_async(clp->cl_rpcclient, &msg, RPC_TASK_SOFT,
&nfs4_renew_ops, data);
}
int nfs4_proc_renew(struct nfs_client *clp, struct rpc_cred *cred)
{
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_RENEW],
.rpc_argp = clp,
.rpc_cred = cred,
};
unsigned long now = jiffies;
int status;
status = rpc_call_sync(clp->cl_rpcclient, &msg, 0);
if (status < 0)
return status;
spin_lock(&clp->cl_lock);
if (time_before(clp->cl_last_renewal,now))
clp->cl_last_renewal = now;
spin_unlock(&clp->cl_lock);
return 0;
}
static inline int nfs4_server_supports_acls(struct nfs_server *server)
{
return (server->caps & NFS_CAP_ACLS)
&& (server->acl_bitmask & ACL4_SUPPORT_ALLOW_ACL)
&& (server->acl_bitmask & ACL4_SUPPORT_DENY_ACL);
}
/* Assuming that XATTR_SIZE_MAX is a multiple of PAGE_CACHE_SIZE, and that
* it's OK to put sizeof(void) * (XATTR_SIZE_MAX/PAGE_CACHE_SIZE) bytes on
* the stack.
*/
#define NFS4ACL_MAXPAGES (XATTR_SIZE_MAX >> PAGE_CACHE_SHIFT)
static void buf_to_pages(const void *buf, size_t buflen,
struct page **pages, unsigned int *pgbase)
{
const void *p = buf;
*pgbase = offset_in_page(buf);
p -= *pgbase;
while (p < buf + buflen) {
*(pages++) = virt_to_page(p);
p += PAGE_CACHE_SIZE;
}
}
struct nfs4_cached_acl {
int cached;
size_t len;
char data[0];
};
static void nfs4_set_cached_acl(struct inode *inode, struct nfs4_cached_acl *acl)
{
struct nfs_inode *nfsi = NFS_I(inode);
spin_lock(&inode->i_lock);
kfree(nfsi->nfs4_acl);
nfsi->nfs4_acl = acl;
spin_unlock(&inode->i_lock);
}
static void nfs4_zap_acl_attr(struct inode *inode)
{
nfs4_set_cached_acl(inode, NULL);
}
static inline ssize_t nfs4_read_cached_acl(struct inode *inode, char *buf, size_t buflen)
{
struct nfs_inode *nfsi = NFS_I(inode);
struct nfs4_cached_acl *acl;
int ret = -ENOENT;
spin_lock(&inode->i_lock);
acl = nfsi->nfs4_acl;
if (acl == NULL)
goto out;
if (buf == NULL) /* user is just asking for length */
goto out_len;
if (acl->cached == 0)
goto out;
ret = -ERANGE; /* see getxattr(2) man page */
if (acl->len > buflen)
goto out;
memcpy(buf, acl->data, acl->len);
out_len:
ret = acl->len;
out:
spin_unlock(&inode->i_lock);
return ret;
}
static void nfs4_write_cached_acl(struct inode *inode, const char *buf, size_t acl_len)
{
struct nfs4_cached_acl *acl;
if (buf && acl_len <= PAGE_SIZE) {
acl = kmalloc(sizeof(*acl) + acl_len, GFP_KERNEL);
if (acl == NULL)
goto out;
acl->cached = 1;
memcpy(acl->data, buf, acl_len);
} else {
acl = kmalloc(sizeof(*acl), GFP_KERNEL);
if (acl == NULL)
goto out;
acl->cached = 0;
}
acl->len = acl_len;
out:
nfs4_set_cached_acl(inode, acl);
}
static ssize_t __nfs4_get_acl_uncached(struct inode *inode, void *buf, size_t buflen)
{
struct page *pages[NFS4ACL_MAXPAGES];
struct nfs_getaclargs args = {
.fh = NFS_FH(inode),
.acl_pages = pages,
.acl_len = buflen,
};
struct nfs_getaclres res = {
.acl_len = buflen,
};
void *resp_buf;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_GETACL],
.rpc_argp = &args,
.rpc_resp = &res,
};
struct page *localpage = NULL;
int ret;
if (buflen < PAGE_SIZE) {
/* As long as we're doing a round trip to the server anyway,
* let's be prepared for a page of acl data. */
localpage = alloc_page(GFP_KERNEL);
resp_buf = page_address(localpage);
if (localpage == NULL)
return -ENOMEM;
args.acl_pages[0] = localpage;
args.acl_pgbase = 0;
args.acl_len = PAGE_SIZE;
} else {
resp_buf = buf;
buf_to_pages(buf, buflen, args.acl_pages, &args.acl_pgbase);
}
ret = nfs4_call_sync(NFS_SERVER(inode), &msg, &args, &res, 0);
if (ret)
goto out_free;
if (res.acl_len > args.acl_len)
nfs4_write_cached_acl(inode, NULL, res.acl_len);
else
nfs4_write_cached_acl(inode, resp_buf, res.acl_len);
if (buf) {
ret = -ERANGE;
if (res.acl_len > buflen)
goto out_free;
if (localpage)
memcpy(buf, resp_buf, res.acl_len);
}
ret = res.acl_len;
out_free:
if (localpage)
__free_page(localpage);
return ret;
}
static ssize_t nfs4_get_acl_uncached(struct inode *inode, void *buf, size_t buflen)
{
struct nfs4_exception exception = { };
ssize_t ret;
do {
ret = __nfs4_get_acl_uncached(inode, buf, buflen);
if (ret >= 0)
break;
ret = nfs4_handle_exception(NFS_SERVER(inode), ret, &exception);
} while (exception.retry);
return ret;
}
static ssize_t nfs4_proc_get_acl(struct inode *inode, void *buf, size_t buflen)
{
struct nfs_server *server = NFS_SERVER(inode);
int ret;
if (!nfs4_server_supports_acls(server))
return -EOPNOTSUPP;
ret = nfs_revalidate_inode(server, inode);
if (ret < 0)
return ret;
ret = nfs4_read_cached_acl(inode, buf, buflen);
if (ret != -ENOENT)
return ret;
return nfs4_get_acl_uncached(inode, buf, buflen);
}
static int __nfs4_proc_set_acl(struct inode *inode, const void *buf, size_t buflen)
{
struct nfs_server *server = NFS_SERVER(inode);
struct page *pages[NFS4ACL_MAXPAGES];
struct nfs_setaclargs arg = {
.fh = NFS_FH(inode),
.acl_pages = pages,
.acl_len = buflen,
};
struct nfs_setaclres res;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SETACL],
.rpc_argp = &arg,
.rpc_resp = &res,
};
int ret;
if (!nfs4_server_supports_acls(server))
return -EOPNOTSUPP;
nfs_inode_return_delegation(inode);
buf_to_pages(buf, buflen, arg.acl_pages, &arg.acl_pgbase);
ret = nfs4_call_sync(server, &msg, &arg, &res, 1);
nfs_access_zap_cache(inode);
nfs_zap_acl_cache(inode);
return ret;
}
static int nfs4_proc_set_acl(struct inode *inode, const void *buf, size_t buflen)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(inode),
__nfs4_proc_set_acl(inode, buf, buflen),
&exception);
} while (exception.retry);
return err;
}
static int
_nfs4_async_handle_error(struct rpc_task *task, const struct nfs_server *server, struct nfs_client *clp, struct nfs4_state *state)
{
if (!clp || task->tk_status >= 0)
return 0;
switch(task->tk_status) {
case -NFS4ERR_ADMIN_REVOKED:
case -NFS4ERR_BAD_STATEID:
case -NFS4ERR_OPENMODE:
if (state == NULL)
break;
nfs4_state_mark_reclaim_nograce(clp, state);
goto do_state_recovery;
case -NFS4ERR_STALE_STATEID:
if (state == NULL)
break;
nfs4_state_mark_reclaim_reboot(clp, state);
case -NFS4ERR_STALE_CLIENTID:
case -NFS4ERR_EXPIRED:
goto do_state_recovery;
#if defined(CONFIG_NFS_V4_1)
case -NFS4ERR_BADSESSION:
case -NFS4ERR_BADSLOT:
case -NFS4ERR_BAD_HIGH_SLOT:
case -NFS4ERR_DEADSESSION:
case -NFS4ERR_CONN_NOT_BOUND_TO_SESSION:
case -NFS4ERR_SEQ_FALSE_RETRY:
case -NFS4ERR_SEQ_MISORDERED:
dprintk("%s ERROR %d, Reset session\n", __func__,
task->tk_status);
nfs4_schedule_state_recovery(clp);
task->tk_status = 0;
return -EAGAIN;
#endif /* CONFIG_NFS_V4_1 */
case -NFS4ERR_DELAY:
if (server)
nfs_inc_server_stats(server, NFSIOS_DELAY);
case -NFS4ERR_GRACE:
case -EKEYEXPIRED:
rpc_delay(task, NFS4_POLL_RETRY_MAX);
task->tk_status = 0;
return -EAGAIN;
case -NFS4ERR_OLD_STATEID:
task->tk_status = 0;
return -EAGAIN;
}
task->tk_status = nfs4_map_errors(task->tk_status);
return 0;
do_state_recovery:
rpc_sleep_on(&clp->cl_rpcwaitq, task, NULL);
nfs4_schedule_state_recovery(clp);
if (test_bit(NFS4CLNT_MANAGER_RUNNING, &clp->cl_state) == 0)
rpc_wake_up_queued_task(&clp->cl_rpcwaitq, task);
task->tk_status = 0;
return -EAGAIN;
}
static int
nfs4_async_handle_error(struct rpc_task *task, const struct nfs_server *server, struct nfs4_state *state)
{
return _nfs4_async_handle_error(task, server, server->nfs_client, state);
}
int nfs4_proc_setclientid(struct nfs_client *clp, u32 program,
unsigned short port, struct rpc_cred *cred,
struct nfs4_setclientid_res *res)
{
nfs4_verifier sc_verifier;
struct nfs4_setclientid setclientid = {
.sc_verifier = &sc_verifier,
.sc_prog = program,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SETCLIENTID],
.rpc_argp = &setclientid,
.rpc_resp = res,
.rpc_cred = cred,
};
__be32 *p;
int loop = 0;
int status;
p = (__be32*)sc_verifier.data;
*p++ = htonl((u32)clp->cl_boot_time.tv_sec);
*p = htonl((u32)clp->cl_boot_time.tv_nsec);
for(;;) {
setclientid.sc_name_len = scnprintf(setclientid.sc_name,
sizeof(setclientid.sc_name), "%s/%s %s %s %u",
clp->cl_ipaddr,
rpc_peeraddr2str(clp->cl_rpcclient,
RPC_DISPLAY_ADDR),
rpc_peeraddr2str(clp->cl_rpcclient,
RPC_DISPLAY_PROTO),
clp->cl_rpcclient->cl_auth->au_ops->au_name,
clp->cl_id_uniquifier);
setclientid.sc_netid_len = scnprintf(setclientid.sc_netid,
sizeof(setclientid.sc_netid),
rpc_peeraddr2str(clp->cl_rpcclient,
RPC_DISPLAY_NETID));
setclientid.sc_uaddr_len = scnprintf(setclientid.sc_uaddr,
sizeof(setclientid.sc_uaddr), "%s.%u.%u",
clp->cl_ipaddr, port >> 8, port & 255);
status = rpc_call_sync(clp->cl_rpcclient, &msg, 0);
if (status != -NFS4ERR_CLID_INUSE)
break;
if (signalled())
break;
if (loop++ & 1)
ssleep(clp->cl_lease_time + 1);
else
if (++clp->cl_id_uniquifier == 0)
break;
}
return status;
}
static int _nfs4_proc_setclientid_confirm(struct nfs_client *clp,
struct nfs4_setclientid_res *arg,
struct rpc_cred *cred)
{
struct nfs_fsinfo fsinfo;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SETCLIENTID_CONFIRM],
.rpc_argp = arg,
.rpc_resp = &fsinfo,
.rpc_cred = cred,
};
unsigned long now;
int status;
now = jiffies;
status = rpc_call_sync(clp->cl_rpcclient, &msg, 0);
if (status == 0) {
spin_lock(&clp->cl_lock);
clp->cl_lease_time = fsinfo.lease_time * HZ;
clp->cl_last_renewal = now;
spin_unlock(&clp->cl_lock);
}
return status;
}
int nfs4_proc_setclientid_confirm(struct nfs_client *clp,
struct nfs4_setclientid_res *arg,
struct rpc_cred *cred)
{
long timeout = 0;
int err;
do {
err = _nfs4_proc_setclientid_confirm(clp, arg, cred);
switch (err) {
case 0:
return err;
case -NFS4ERR_RESOURCE:
/* The IBM lawyers misread another document! */
case -NFS4ERR_DELAY:
case -EKEYEXPIRED:
err = nfs4_delay(clp->cl_rpcclient, &timeout);
}
} while (err == 0);
return err;
}
struct nfs4_delegreturndata {
struct nfs4_delegreturnargs args;
struct nfs4_delegreturnres res;
struct nfs_fh fh;
nfs4_stateid stateid;
unsigned long timestamp;
struct nfs_fattr fattr;
int rpc_status;
};
static void nfs4_delegreturn_done(struct rpc_task *task, void *calldata)
{
struct nfs4_delegreturndata *data = calldata;
nfs4_sequence_done(data->res.server, &data->res.seq_res,
task->tk_status);
switch (task->tk_status) {
case -NFS4ERR_STALE_STATEID:
case -NFS4ERR_EXPIRED:
case 0:
renew_lease(data->res.server, data->timestamp);
break;
default:
if (nfs4_async_handle_error(task, data->res.server, NULL) ==
-EAGAIN) {
nfs_restart_rpc(task, data->res.server->nfs_client);
return;
}
}
data->rpc_status = task->tk_status;
}
static void nfs4_delegreturn_release(void *calldata)
{
kfree(calldata);
}
#if defined(CONFIG_NFS_V4_1)
static void nfs4_delegreturn_prepare(struct rpc_task *task, void *data)
{
struct nfs4_delegreturndata *d_data;
d_data = (struct nfs4_delegreturndata *)data;
if (nfs4_setup_sequence(d_data->res.server->nfs_client,
&d_data->args.seq_args,
&d_data->res.seq_res, 1, task))
return;
rpc_call_start(task);
}
#endif /* CONFIG_NFS_V4_1 */
static const struct rpc_call_ops nfs4_delegreturn_ops = {
#if defined(CONFIG_NFS_V4_1)
.rpc_call_prepare = nfs4_delegreturn_prepare,
#endif /* CONFIG_NFS_V4_1 */
.rpc_call_done = nfs4_delegreturn_done,
.rpc_release = nfs4_delegreturn_release,
};
static int _nfs4_proc_delegreturn(struct inode *inode, struct rpc_cred *cred, const nfs4_stateid *stateid, int issync)
{
struct nfs4_delegreturndata *data;
struct nfs_server *server = NFS_SERVER(inode);
struct rpc_task *task;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_DELEGRETURN],
.rpc_cred = cred,
};
struct rpc_task_setup task_setup_data = {
.rpc_client = server->client,
.rpc_message = &msg,
.callback_ops = &nfs4_delegreturn_ops,
.flags = RPC_TASK_ASYNC,
};
int status = 0;
data = kzalloc(sizeof(*data), GFP_NOFS);
if (data == NULL)
return -ENOMEM;
data->args.fhandle = &data->fh;
data->args.stateid = &data->stateid;
data->args.bitmask = server->attr_bitmask;
nfs_copy_fh(&data->fh, NFS_FH(inode));
memcpy(&data->stateid, stateid, sizeof(data->stateid));
data->res.fattr = &data->fattr;
data->res.server = server;
data->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
nfs_fattr_init(data->res.fattr);
data->timestamp = jiffies;
data->rpc_status = 0;
task_setup_data.callback_data = data;
msg.rpc_argp = &data->args,
msg.rpc_resp = &data->res,
task = rpc_run_task(&task_setup_data);
if (IS_ERR(task))
return PTR_ERR(task);
if (!issync)
goto out;
status = nfs4_wait_for_completion_rpc_task(task);
if (status != 0)
goto out;
status = data->rpc_status;
if (status != 0)
goto out;
nfs_refresh_inode(inode, &data->fattr);
out:
rpc_put_task(task);
return status;
}
int nfs4_proc_delegreturn(struct inode *inode, struct rpc_cred *cred, const nfs4_stateid *stateid, int issync)
{
struct nfs_server *server = NFS_SERVER(inode);
struct nfs4_exception exception = { };
int err;
do {
err = _nfs4_proc_delegreturn(inode, cred, stateid, issync);
switch (err) {
case -NFS4ERR_STALE_STATEID:
case -NFS4ERR_EXPIRED:
case 0:
return 0;
}
err = nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
return err;
}
#define NFS4_LOCK_MINTIMEOUT (1 * HZ)
#define NFS4_LOCK_MAXTIMEOUT (30 * HZ)
/*
* sleep, with exponential backoff, and retry the LOCK operation.
*/
static unsigned long
nfs4_set_lock_task_retry(unsigned long timeout)
{
schedule_timeout_killable(timeout);
timeout <<= 1;
if (timeout > NFS4_LOCK_MAXTIMEOUT)
return NFS4_LOCK_MAXTIMEOUT;
return timeout;
}
static int _nfs4_proc_getlk(struct nfs4_state *state, int cmd, struct file_lock *request)
{
struct inode *inode = state->inode;
struct nfs_server *server = NFS_SERVER(inode);
struct nfs_client *clp = server->nfs_client;
struct nfs_lockt_args arg = {
.fh = NFS_FH(inode),
.fl = request,
};
struct nfs_lockt_res res = {
.denied = request,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_LOCKT],
.rpc_argp = &arg,
.rpc_resp = &res,
.rpc_cred = state->owner->so_cred,
};
struct nfs4_lock_state *lsp;
int status;
arg.lock_owner.clientid = clp->cl_clientid;
status = nfs4_set_lock_state(state, request);
if (status != 0)
goto out;
lsp = request->fl_u.nfs4_fl.owner;
arg.lock_owner.id = lsp->ls_id.id;
status = nfs4_call_sync(server, &msg, &arg, &res, 1);
switch (status) {
case 0:
request->fl_type = F_UNLCK;
break;
case -NFS4ERR_DENIED:
status = 0;
}
request->fl_ops->fl_release_private(request);
out:
return status;
}
static int nfs4_proc_getlk(struct nfs4_state *state, int cmd, struct file_lock *request)
{
struct nfs4_exception exception = { };
int err;
do {
err = nfs4_handle_exception(NFS_SERVER(state->inode),
_nfs4_proc_getlk(state, cmd, request),
&exception);
} while (exception.retry);
return err;
}
static int do_vfs_lock(struct file *file, struct file_lock *fl)
{
int res = 0;
switch (fl->fl_flags & (FL_POSIX|FL_FLOCK)) {
case FL_POSIX:
res = posix_lock_file_wait(file, fl);
break;
case FL_FLOCK:
res = flock_lock_file_wait(file, fl);
break;
default:
BUG();
}
return res;
}
struct nfs4_unlockdata {
struct nfs_locku_args arg;
struct nfs_locku_res res;
struct nfs4_lock_state *lsp;
struct nfs_open_context *ctx;
struct file_lock fl;
const struct nfs_server *server;
unsigned long timestamp;
};
static struct nfs4_unlockdata *nfs4_alloc_unlockdata(struct file_lock *fl,
struct nfs_open_context *ctx,
struct nfs4_lock_state *lsp,
struct nfs_seqid *seqid)
{
struct nfs4_unlockdata *p;
struct inode *inode = lsp->ls_state->inode;
p = kzalloc(sizeof(*p), GFP_NOFS);
if (p == NULL)
return NULL;
p->arg.fh = NFS_FH(inode);
p->arg.fl = &p->fl;
p->arg.seqid = seqid;
p->res.seqid = seqid;
p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
p->arg.stateid = &lsp->ls_stateid;
p->lsp = lsp;
atomic_inc(&lsp->ls_count);
/* Ensure we don't close file until we're done freeing locks! */
p->ctx = get_nfs_open_context(ctx);
memcpy(&p->fl, fl, sizeof(p->fl));
p->server = NFS_SERVER(inode);
return p;
}
static void nfs4_locku_release_calldata(void *data)
{
struct nfs4_unlockdata *calldata = data;
nfs_free_seqid(calldata->arg.seqid);
nfs4_put_lock_state(calldata->lsp);
put_nfs_open_context(calldata->ctx);
kfree(calldata);
}
static void nfs4_locku_done(struct rpc_task *task, void *data)
{
struct nfs4_unlockdata *calldata = data;
nfs4_sequence_done(calldata->server, &calldata->res.seq_res,
task->tk_status);
if (RPC_ASSASSINATED(task))
return;
switch (task->tk_status) {
case 0:
memcpy(calldata->lsp->ls_stateid.data,
calldata->res.stateid.data,
sizeof(calldata->lsp->ls_stateid.data));
renew_lease(calldata->server, calldata->timestamp);
break;
case -NFS4ERR_BAD_STATEID:
case -NFS4ERR_OLD_STATEID:
case -NFS4ERR_STALE_STATEID:
case -NFS4ERR_EXPIRED:
break;
default:
if (nfs4_async_handle_error(task, calldata->server, NULL) == -EAGAIN)
nfs_restart_rpc(task,
calldata->server->nfs_client);
}
}
static void nfs4_locku_prepare(struct rpc_task *task, void *data)
{
struct nfs4_unlockdata *calldata = data;
if (nfs_wait_on_sequence(calldata->arg.seqid, task) != 0)
return;
if ((calldata->lsp->ls_flags & NFS_LOCK_INITIALIZED) == 0) {
/* Note: exit _without_ running nfs4_locku_done */
task->tk_action = NULL;
return;
}
calldata->timestamp = jiffies;
if (nfs4_setup_sequence(calldata->server->nfs_client,
&calldata->arg.seq_args,
&calldata->res.seq_res, 1, task))
return;
rpc_call_start(task);
}
static const struct rpc_call_ops nfs4_locku_ops = {
.rpc_call_prepare = nfs4_locku_prepare,
.rpc_call_done = nfs4_locku_done,
.rpc_release = nfs4_locku_release_calldata,
};
static struct rpc_task *nfs4_do_unlck(struct file_lock *fl,
struct nfs_open_context *ctx,
struct nfs4_lock_state *lsp,
struct nfs_seqid *seqid)
{
struct nfs4_unlockdata *data;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_LOCKU],
.rpc_cred = ctx->cred,
};
struct rpc_task_setup task_setup_data = {
.rpc_client = NFS_CLIENT(lsp->ls_state->inode),
.rpc_message = &msg,
.callback_ops = &nfs4_locku_ops,
.workqueue = nfsiod_workqueue,
.flags = RPC_TASK_ASYNC,
};
/* Ensure this is an unlock - when canceling a lock, the
* canceled lock is passed in, and it won't be an unlock.
*/
fl->fl_type = F_UNLCK;
data = nfs4_alloc_unlockdata(fl, ctx, lsp, seqid);
if (data == NULL) {
nfs_free_seqid(seqid);
return ERR_PTR(-ENOMEM);
}
msg.rpc_argp = &data->arg,
msg.rpc_resp = &data->res,
task_setup_data.callback_data = data;
return rpc_run_task(&task_setup_data);
}
static int nfs4_proc_unlck(struct nfs4_state *state, int cmd, struct file_lock *request)
{
struct nfs_inode *nfsi = NFS_I(state->inode);
struct nfs_seqid *seqid;
struct nfs4_lock_state *lsp;
struct rpc_task *task;
int status = 0;
unsigned char fl_flags = request->fl_flags;
status = nfs4_set_lock_state(state, request);
/* Unlock _before_ we do the RPC call */
request->fl_flags |= FL_EXISTS;
down_read(&nfsi->rwsem);
if (do_vfs_lock(request->fl_file, request) == -ENOENT) {
up_read(&nfsi->rwsem);
goto out;
}
up_read(&nfsi->rwsem);
if (status != 0)
goto out;
/* Is this a delegated lock? */
if (test_bit(NFS_DELEGATED_STATE, &state->flags))
goto out;
lsp = request->fl_u.nfs4_fl.owner;
seqid = nfs_alloc_seqid(&lsp->ls_seqid, GFP_KERNEL);
status = -ENOMEM;
if (seqid == NULL)
goto out;
task = nfs4_do_unlck(request, nfs_file_open_context(request->fl_file), lsp, seqid);
status = PTR_ERR(task);
if (IS_ERR(task))
goto out;
status = nfs4_wait_for_completion_rpc_task(task);
rpc_put_task(task);
out:
request->fl_flags = fl_flags;
return status;
}
struct nfs4_lockdata {
struct nfs_lock_args arg;
struct nfs_lock_res res;
struct nfs4_lock_state *lsp;
struct nfs_open_context *ctx;
struct file_lock fl;
unsigned long timestamp;
int rpc_status;
int cancelled;
struct nfs_server *server;
};
static struct nfs4_lockdata *nfs4_alloc_lockdata(struct file_lock *fl,
struct nfs_open_context *ctx, struct nfs4_lock_state *lsp,
gfp_t gfp_mask)
{
struct nfs4_lockdata *p;
struct inode *inode = lsp->ls_state->inode;
struct nfs_server *server = NFS_SERVER(inode);
p = kzalloc(sizeof(*p), gfp_mask);
if (p == NULL)
return NULL;
p->arg.fh = NFS_FH(inode);
p->arg.fl = &p->fl;
p->arg.open_seqid = nfs_alloc_seqid(&lsp->ls_state->owner->so_seqid, gfp_mask);
if (p->arg.open_seqid == NULL)
goto out_free;
p->arg.lock_seqid = nfs_alloc_seqid(&lsp->ls_seqid, gfp_mask);
if (p->arg.lock_seqid == NULL)
goto out_free_seqid;
p->arg.lock_stateid = &lsp->ls_stateid;
p->arg.lock_owner.clientid = server->nfs_client->cl_clientid;
p->arg.lock_owner.id = lsp->ls_id.id;
p->res.lock_seqid = p->arg.lock_seqid;
p->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
p->lsp = lsp;
p->server = server;
atomic_inc(&lsp->ls_count);
p->ctx = get_nfs_open_context(ctx);
memcpy(&p->fl, fl, sizeof(p->fl));
return p;
out_free_seqid:
nfs_free_seqid(p->arg.open_seqid);
out_free:
kfree(p);
return NULL;
}
static void nfs4_lock_prepare(struct rpc_task *task, void *calldata)
{
struct nfs4_lockdata *data = calldata;
struct nfs4_state *state = data->lsp->ls_state;
dprintk("%s: begin!\n", __func__);
if (nfs_wait_on_sequence(data->arg.lock_seqid, task) != 0)
return;
/* Do we need to do an open_to_lock_owner? */
if (!(data->arg.lock_seqid->sequence->flags & NFS_SEQID_CONFIRMED)) {
if (nfs_wait_on_sequence(data->arg.open_seqid, task) != 0)
return;
data->arg.open_stateid = &state->stateid;
data->arg.new_lock_owner = 1;
data->res.open_seqid = data->arg.open_seqid;
} else
data->arg.new_lock_owner = 0;
data->timestamp = jiffies;
if (nfs4_setup_sequence(data->server->nfs_client, &data->arg.seq_args,
&data->res.seq_res, 1, task))
return;
rpc_call_start(task);
dprintk("%s: done!, ret = %d\n", __func__, data->rpc_status);
}
static void nfs4_recover_lock_prepare(struct rpc_task *task, void *calldata)
{
rpc_task_set_priority(task, RPC_PRIORITY_PRIVILEGED);
nfs4_lock_prepare(task, calldata);
}
static void nfs4_lock_done(struct rpc_task *task, void *calldata)
{
struct nfs4_lockdata *data = calldata;
dprintk("%s: begin!\n", __func__);
nfs4_sequence_done(data->server, &data->res.seq_res,
task->tk_status);
data->rpc_status = task->tk_status;
if (RPC_ASSASSINATED(task))
goto out;
if (data->arg.new_lock_owner != 0) {
if (data->rpc_status == 0)
nfs_confirm_seqid(&data->lsp->ls_seqid, 0);
else
goto out;
}
if (data->rpc_status == 0) {
memcpy(data->lsp->ls_stateid.data, data->res.stateid.data,
sizeof(data->lsp->ls_stateid.data));
data->lsp->ls_flags |= NFS_LOCK_INITIALIZED;
renew_lease(NFS_SERVER(data->ctx->path.dentry->d_inode), data->timestamp);
}
out:
dprintk("%s: done, ret = %d!\n", __func__, data->rpc_status);
}
static void nfs4_lock_release(void *calldata)
{
struct nfs4_lockdata *data = calldata;
dprintk("%s: begin!\n", __func__);
nfs_free_seqid(data->arg.open_seqid);
if (data->cancelled != 0) {
struct rpc_task *task;
task = nfs4_do_unlck(&data->fl, data->ctx, data->lsp,
data->arg.lock_seqid);
if (!IS_ERR(task))
rpc_put_task(task);
dprintk("%s: cancelling lock!\n", __func__);
} else
nfs_free_seqid(data->arg.lock_seqid);
nfs4_put_lock_state(data->lsp);
put_nfs_open_context(data->ctx);
kfree(data);
dprintk("%s: done!\n", __func__);
}
static const struct rpc_call_ops nfs4_lock_ops = {
.rpc_call_prepare = nfs4_lock_prepare,
.rpc_call_done = nfs4_lock_done,
.rpc_release = nfs4_lock_release,
};
static const struct rpc_call_ops nfs4_recover_lock_ops = {
.rpc_call_prepare = nfs4_recover_lock_prepare,
.rpc_call_done = nfs4_lock_done,
.rpc_release = nfs4_lock_release,
};
static void nfs4_handle_setlk_error(struct nfs_server *server, struct nfs4_lock_state *lsp, int new_lock_owner, int error)
{
struct nfs_client *clp = server->nfs_client;
struct nfs4_state *state = lsp->ls_state;
switch (error) {
case -NFS4ERR_ADMIN_REVOKED:
case -NFS4ERR_BAD_STATEID:
case -NFS4ERR_EXPIRED:
if (new_lock_owner != 0 ||
(lsp->ls_flags & NFS_LOCK_INITIALIZED) != 0)
nfs4_state_mark_reclaim_nograce(clp, state);
lsp->ls_seqid.flags &= ~NFS_SEQID_CONFIRMED;
break;
case -NFS4ERR_STALE_STATEID:
if (new_lock_owner != 0 ||
(lsp->ls_flags & NFS_LOCK_INITIALIZED) != 0)
nfs4_state_mark_reclaim_reboot(clp, state);
lsp->ls_seqid.flags &= ~NFS_SEQID_CONFIRMED;
};
}
static int _nfs4_do_setlk(struct nfs4_state *state, int cmd, struct file_lock *fl, int recovery_type)
{
struct nfs4_lockdata *data;
struct rpc_task *task;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_LOCK],
.rpc_cred = state->owner->so_cred,
};
struct rpc_task_setup task_setup_data = {
.rpc_client = NFS_CLIENT(state->inode),
.rpc_message = &msg,
.callback_ops = &nfs4_lock_ops,
.workqueue = nfsiod_workqueue,
.flags = RPC_TASK_ASYNC,
};
int ret;
dprintk("%s: begin!\n", __func__);
data = nfs4_alloc_lockdata(fl, nfs_file_open_context(fl->fl_file),
fl->fl_u.nfs4_fl.owner,
recovery_type == NFS_LOCK_NEW ? GFP_KERNEL : GFP_NOFS);
if (data == NULL)
return -ENOMEM;
if (IS_SETLKW(cmd))
data->arg.block = 1;
if (recovery_type > NFS_LOCK_NEW) {
if (recovery_type == NFS_LOCK_RECLAIM)
data->arg.reclaim = NFS_LOCK_RECLAIM;
task_setup_data.callback_ops = &nfs4_recover_lock_ops;
}
msg.rpc_argp = &data->arg,
msg.rpc_resp = &data->res,
task_setup_data.callback_data = data;
task = rpc_run_task(&task_setup_data);
if (IS_ERR(task))
return PTR_ERR(task);
ret = nfs4_wait_for_completion_rpc_task(task);
if (ret == 0) {
ret = data->rpc_status;
if (ret)
nfs4_handle_setlk_error(data->server, data->lsp,
data->arg.new_lock_owner, ret);
} else
data->cancelled = 1;
rpc_put_task(task);
dprintk("%s: done, ret = %d!\n", __func__, ret);
return ret;
}
static int nfs4_lock_reclaim(struct nfs4_state *state, struct file_lock *request)
{
struct nfs_server *server = NFS_SERVER(state->inode);
struct nfs4_exception exception = { };
int err;
do {
/* Cache the lock if possible... */
if (test_bit(NFS_DELEGATED_STATE, &state->flags) != 0)
return 0;
err = _nfs4_do_setlk(state, F_SETLK, request, NFS_LOCK_RECLAIM);
if (err != -NFS4ERR_DELAY && err != -EKEYEXPIRED)
break;
nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
return err;
}
static int nfs4_lock_expired(struct nfs4_state *state, struct file_lock *request)
{
struct nfs_server *server = NFS_SERVER(state->inode);
struct nfs4_exception exception = { };
int err;
err = nfs4_set_lock_state(state, request);
if (err != 0)
return err;
do {
if (test_bit(NFS_DELEGATED_STATE, &state->flags) != 0)
return 0;
err = _nfs4_do_setlk(state, F_SETLK, request, NFS_LOCK_EXPIRED);
switch (err) {
default:
goto out;
case -NFS4ERR_GRACE:
case -NFS4ERR_DELAY:
case -EKEYEXPIRED:
nfs4_handle_exception(server, err, &exception);
err = 0;
}
} while (exception.retry);
out:
return err;
}
static int _nfs4_proc_setlk(struct nfs4_state *state, int cmd, struct file_lock *request)
{
struct nfs_inode *nfsi = NFS_I(state->inode);
unsigned char fl_flags = request->fl_flags;
int status = -ENOLCK;
if ((fl_flags & FL_POSIX) &&
!test_bit(NFS_STATE_POSIX_LOCKS, &state->flags))
goto out;
/* Is this a delegated open? */
status = nfs4_set_lock_state(state, request);
if (status != 0)
goto out;
request->fl_flags |= FL_ACCESS;
status = do_vfs_lock(request->fl_file, request);
if (status < 0)
goto out;
down_read(&nfsi->rwsem);
if (test_bit(NFS_DELEGATED_STATE, &state->flags)) {
/* Yes: cache locks! */
/* ...but avoid races with delegation recall... */
request->fl_flags = fl_flags & ~FL_SLEEP;
status = do_vfs_lock(request->fl_file, request);
goto out_unlock;
}
status = _nfs4_do_setlk(state, cmd, request, NFS_LOCK_NEW);
if (status != 0)
goto out_unlock;
/* Note: we always want to sleep here! */
request->fl_flags = fl_flags | FL_SLEEP;
if (do_vfs_lock(request->fl_file, request) < 0)
printk(KERN_WARNING "%s: VFS is out of sync with lock manager!\n", __func__);
out_unlock:
up_read(&nfsi->rwsem);
out:
request->fl_flags = fl_flags;
return status;
}
static int nfs4_proc_setlk(struct nfs4_state *state, int cmd, struct file_lock *request)
{
struct nfs4_exception exception = { };
int err;
do {
err = _nfs4_proc_setlk(state, cmd, request);
if (err == -NFS4ERR_DENIED)
err = -EAGAIN;
err = nfs4_handle_exception(NFS_SERVER(state->inode),
err, &exception);
} while (exception.retry);
return err;
}
static int
nfs4_proc_lock(struct file *filp, int cmd, struct file_lock *request)
{
struct nfs_open_context *ctx;
struct nfs4_state *state;
unsigned long timeout = NFS4_LOCK_MINTIMEOUT;
int status;
/* verify open state */
ctx = nfs_file_open_context(filp);
state = ctx->state;
if (request->fl_start < 0 || request->fl_end < 0)
return -EINVAL;
if (IS_GETLK(cmd)) {
if (state != NULL)
return nfs4_proc_getlk(state, F_GETLK, request);
return 0;
}
if (!(IS_SETLK(cmd) || IS_SETLKW(cmd)))
return -EINVAL;
if (request->fl_type == F_UNLCK) {
if (state != NULL)
return nfs4_proc_unlck(state, cmd, request);
return 0;
}
if (state == NULL)
return -ENOLCK;
do {
status = nfs4_proc_setlk(state, cmd, request);
if ((status != -EAGAIN) || IS_SETLK(cmd))
break;
timeout = nfs4_set_lock_task_retry(timeout);
status = -ERESTARTSYS;
if (signalled())
break;
} while(status < 0);
return status;
}
int nfs4_lock_delegation_recall(struct nfs4_state *state, struct file_lock *fl)
{
struct nfs_server *server = NFS_SERVER(state->inode);
struct nfs4_exception exception = { };
int err;
err = nfs4_set_lock_state(state, fl);
if (err != 0)
goto out;
do {
err = _nfs4_do_setlk(state, F_SETLK, fl, NFS_LOCK_NEW);
switch (err) {
default:
printk(KERN_ERR "%s: unhandled error %d.\n",
__func__, err);
case 0:
case -ESTALE:
goto out;
case -NFS4ERR_EXPIRED:
case -NFS4ERR_STALE_CLIENTID:
case -NFS4ERR_STALE_STATEID:
case -NFS4ERR_BADSESSION:
case -NFS4ERR_BADSLOT:
case -NFS4ERR_BAD_HIGH_SLOT:
case -NFS4ERR_CONN_NOT_BOUND_TO_SESSION:
case -NFS4ERR_DEADSESSION:
nfs4_schedule_state_recovery(server->nfs_client);
goto out;
case -ERESTARTSYS:
/*
* The show must go on: exit, but mark the
* stateid as needing recovery.
*/
case -NFS4ERR_ADMIN_REVOKED:
case -NFS4ERR_BAD_STATEID:
case -NFS4ERR_OPENMODE:
nfs4_state_mark_reclaim_nograce(server->nfs_client, state);
err = 0;
goto out;
case -ENOMEM:
case -NFS4ERR_DENIED:
/* kill_proc(fl->fl_pid, SIGLOST, 1); */
err = 0;
goto out;
case -NFS4ERR_DELAY:
case -EKEYEXPIRED:
break;
}
err = nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
out:
return err;
}
#define XATTR_NAME_NFSV4_ACL "system.nfs4_acl"
int nfs4_setxattr(struct dentry *dentry, const char *key, const void *buf,
size_t buflen, int flags)
{
struct inode *inode = dentry->d_inode;
if (strcmp(key, XATTR_NAME_NFSV4_ACL) != 0)
return -EOPNOTSUPP;
return nfs4_proc_set_acl(inode, buf, buflen);
}
/* The getxattr man page suggests returning -ENODATA for unknown attributes,
* and that's what we'll do for e.g. user attributes that haven't been set.
* But we'll follow ext2/ext3's lead by returning -EOPNOTSUPP for unsupported
* attributes in kernel-managed attribute namespaces. */
ssize_t nfs4_getxattr(struct dentry *dentry, const char *key, void *buf,
size_t buflen)
{
struct inode *inode = dentry->d_inode;
if (strcmp(key, XATTR_NAME_NFSV4_ACL) != 0)
return -EOPNOTSUPP;
return nfs4_proc_get_acl(inode, buf, buflen);
}
ssize_t nfs4_listxattr(struct dentry *dentry, char *buf, size_t buflen)
{
size_t len = strlen(XATTR_NAME_NFSV4_ACL) + 1;
if (!nfs4_server_supports_acls(NFS_SERVER(dentry->d_inode)))
return 0;
if (buf && buflen < len)
return -ERANGE;
if (buf)
memcpy(buf, XATTR_NAME_NFSV4_ACL, len);
return len;
}
static void nfs_fixup_referral_attributes(struct nfs_fattr *fattr)
{
if (!((fattr->valid & NFS_ATTR_FATTR_FILEID) &&
(fattr->valid & NFS_ATTR_FATTR_FSID) &&
(fattr->valid & NFS_ATTR_FATTR_V4_REFERRAL)))
return;
fattr->valid |= NFS_ATTR_FATTR_TYPE | NFS_ATTR_FATTR_MODE |
NFS_ATTR_FATTR_NLINK;
fattr->mode = S_IFDIR | S_IRUGO | S_IXUGO;
fattr->nlink = 2;
}
int nfs4_proc_fs_locations(struct inode *dir, const struct qstr *name,
struct nfs4_fs_locations *fs_locations, struct page *page)
{
struct nfs_server *server = NFS_SERVER(dir);
u32 bitmask[2] = {
[0] = FATTR4_WORD0_FSID | FATTR4_WORD0_FS_LOCATIONS,
[1] = FATTR4_WORD1_MOUNTED_ON_FILEID,
};
struct nfs4_fs_locations_arg args = {
.dir_fh = NFS_FH(dir),
.name = name,
.page = page,
.bitmask = bitmask,
};
struct nfs4_fs_locations_res res = {
.fs_locations = fs_locations,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_FS_LOCATIONS],
.rpc_argp = &args,
.rpc_resp = &res,
};
int status;
dprintk("%s: start\n", __func__);
nfs_fattr_init(&fs_locations->fattr);
fs_locations->server = server;
fs_locations->nlocations = 0;
status = nfs4_call_sync(server, &msg, &args, &res, 0);
nfs_fixup_referral_attributes(&fs_locations->fattr);
dprintk("%s: returned status = %d\n", __func__, status);
return status;
}
#ifdef CONFIG_NFS_V4_1
/*
* nfs4_proc_exchange_id()
*
* Since the clientid has expired, all compounds using sessions
* associated with the stale clientid will be returning
* NFS4ERR_BADSESSION in the sequence operation, and will therefore
* be in some phase of session reset.
*/
int nfs4_proc_exchange_id(struct nfs_client *clp, struct rpc_cred *cred)
{
nfs4_verifier verifier;
struct nfs41_exchange_id_args args = {
.client = clp,
.flags = clp->cl_exchange_flags,
};
struct nfs41_exchange_id_res res = {
.client = clp,
};
int status;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_EXCHANGE_ID],
.rpc_argp = &args,
.rpc_resp = &res,
.rpc_cred = cred,
};
__be32 *p;
dprintk("--> %s\n", __func__);
BUG_ON(clp == NULL);
/* Remove server-only flags */
args.flags &= ~EXCHGID4_FLAG_CONFIRMED_R;
p = (u32 *)verifier.data;
*p++ = htonl((u32)clp->cl_boot_time.tv_sec);
*p = htonl((u32)clp->cl_boot_time.tv_nsec);
args.verifier = &verifier;
while (1) {
args.id_len = scnprintf(args.id, sizeof(args.id),
"%s/%s %u",
clp->cl_ipaddr,
rpc_peeraddr2str(clp->cl_rpcclient,
RPC_DISPLAY_ADDR),
clp->cl_id_uniquifier);
status = rpc_call_sync(clp->cl_rpcclient, &msg, 0);
if (status != -NFS4ERR_CLID_INUSE)
break;
if (signalled())
break;
if (++clp->cl_id_uniquifier == 0)
break;
}
dprintk("<-- %s status= %d\n", __func__, status);
return status;
}
struct nfs4_get_lease_time_data {
struct nfs4_get_lease_time_args *args;
struct nfs4_get_lease_time_res *res;
struct nfs_client *clp;
};
static void nfs4_get_lease_time_prepare(struct rpc_task *task,
void *calldata)
{
int ret;
struct nfs4_get_lease_time_data *data =
(struct nfs4_get_lease_time_data *)calldata;
dprintk("--> %s\n", __func__);
rpc_task_set_priority(task, RPC_PRIORITY_PRIVILEGED);
/* just setup sequence, do not trigger session recovery
since we're invoked within one */
ret = nfs41_setup_sequence(data->clp->cl_session,
&data->args->la_seq_args,
&data->res->lr_seq_res, 0, task);
BUG_ON(ret == -EAGAIN);
rpc_call_start(task);
dprintk("<-- %s\n", __func__);
}
/*
* Called from nfs4_state_manager thread for session setup, so don't recover
* from sequence operation or clientid errors.
*/
static void nfs4_get_lease_time_done(struct rpc_task *task, void *calldata)
{
struct nfs4_get_lease_time_data *data =
(struct nfs4_get_lease_time_data *)calldata;
dprintk("--> %s\n", __func__);
nfs41_sequence_done(data->clp, &data->res->lr_seq_res, task->tk_status);
switch (task->tk_status) {
case -NFS4ERR_DELAY:
case -NFS4ERR_GRACE:
case -EKEYEXPIRED:
dprintk("%s Retry: tk_status %d\n", __func__, task->tk_status);
rpc_delay(task, NFS4_POLL_RETRY_MIN);
task->tk_status = 0;
nfs_restart_rpc(task, data->clp);
return;
}
dprintk("<-- %s\n", __func__);
}
struct rpc_call_ops nfs4_get_lease_time_ops = {
.rpc_call_prepare = nfs4_get_lease_time_prepare,
.rpc_call_done = nfs4_get_lease_time_done,
};
int nfs4_proc_get_lease_time(struct nfs_client *clp, struct nfs_fsinfo *fsinfo)
{
struct rpc_task *task;
struct nfs4_get_lease_time_args args;
struct nfs4_get_lease_time_res res = {
.lr_fsinfo = fsinfo,
};
struct nfs4_get_lease_time_data data = {
.args = &args,
.res = &res,
.clp = clp,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_GET_LEASE_TIME],
.rpc_argp = &args,
.rpc_resp = &res,
};
struct rpc_task_setup task_setup = {
.rpc_client = clp->cl_rpcclient,
.rpc_message = &msg,
.callback_ops = &nfs4_get_lease_time_ops,
.callback_data = &data
};
int status;
res.lr_seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
dprintk("--> %s\n", __func__);
task = rpc_run_task(&task_setup);
if (IS_ERR(task))
status = PTR_ERR(task);
else {
status = task->tk_status;
rpc_put_task(task);
}
dprintk("<-- %s return %d\n", __func__, status);
return status;
}
/*
* Reset a slot table
*/
static int nfs4_reset_slot_table(struct nfs4_slot_table *tbl, u32 max_reqs,
int ivalue)
{
struct nfs4_slot *new = NULL;
int i;
int ret = 0;
dprintk("--> %s: max_reqs=%u, tbl->max_slots %d\n", __func__,
max_reqs, tbl->max_slots);
/* Does the newly negotiated max_reqs match the existing slot table? */
if (max_reqs != tbl->max_slots) {
ret = -ENOMEM;
new = kmalloc(max_reqs * sizeof(struct nfs4_slot),
GFP_NOFS);
if (!new)
goto out;
ret = 0;
kfree(tbl->slots);
}
spin_lock(&tbl->slot_tbl_lock);
if (new) {
tbl->slots = new;
tbl->max_slots = max_reqs;
}
for (i = 0; i < tbl->max_slots; ++i)
tbl->slots[i].seq_nr = ivalue;
spin_unlock(&tbl->slot_tbl_lock);
dprintk("%s: tbl=%p slots=%p max_slots=%d\n", __func__,
tbl, tbl->slots, tbl->max_slots);
out:
dprintk("<-- %s: return %d\n", __func__, ret);
return ret;
}
/*
* Reset the forechannel and backchannel slot tables
*/
static int nfs4_reset_slot_tables(struct nfs4_session *session)
{
int status;
status = nfs4_reset_slot_table(&session->fc_slot_table,
session->fc_attrs.max_reqs, 1);
if (status)
return status;
status = nfs4_reset_slot_table(&session->bc_slot_table,
session->bc_attrs.max_reqs, 0);
return status;
}
/* Destroy the slot table */
static void nfs4_destroy_slot_tables(struct nfs4_session *session)
{
if (session->fc_slot_table.slots != NULL) {
kfree(session->fc_slot_table.slots);
session->fc_slot_table.slots = NULL;
}
if (session->bc_slot_table.slots != NULL) {
kfree(session->bc_slot_table.slots);
session->bc_slot_table.slots = NULL;
}
return;
}
/*
* Initialize slot table
*/
static int nfs4_init_slot_table(struct nfs4_slot_table *tbl,
int max_slots, int ivalue)
{
struct nfs4_slot *slot;
int ret = -ENOMEM;
BUG_ON(max_slots > NFS4_MAX_SLOT_TABLE);
dprintk("--> %s: max_reqs=%u\n", __func__, max_slots);
slot = kcalloc(max_slots, sizeof(struct nfs4_slot), GFP_NOFS);
if (!slot)
goto out;
ret = 0;
spin_lock(&tbl->slot_tbl_lock);
tbl->max_slots = max_slots;
tbl->slots = slot;
tbl->highest_used_slotid = -1; /* no slot is currently used */
spin_unlock(&tbl->slot_tbl_lock);
dprintk("%s: tbl=%p slots=%p max_slots=%d\n", __func__,
tbl, tbl->slots, tbl->max_slots);
out:
dprintk("<-- %s: return %d\n", __func__, ret);
return ret;
}
/*
* Initialize the forechannel and backchannel tables
*/
static int nfs4_init_slot_tables(struct nfs4_session *session)
{
struct nfs4_slot_table *tbl;
int status = 0;
tbl = &session->fc_slot_table;
if (tbl->slots == NULL) {
status = nfs4_init_slot_table(tbl,
session->fc_attrs.max_reqs, 1);
if (status)
return status;
}
tbl = &session->bc_slot_table;
if (tbl->slots == NULL) {
status = nfs4_init_slot_table(tbl,
session->bc_attrs.max_reqs, 0);
if (status)
nfs4_destroy_slot_tables(session);
}
return status;
}
struct nfs4_session *nfs4_alloc_session(struct nfs_client *clp)
{
struct nfs4_session *session;
struct nfs4_slot_table *tbl;
session = kzalloc(sizeof(struct nfs4_session), GFP_NOFS);
if (!session)
return NULL;
/*
* The create session reply races with the server back
* channel probe. Mark the client NFS_CS_SESSION_INITING
* so that the client back channel can find the
* nfs_client struct
*/
clp->cl_cons_state = NFS_CS_SESSION_INITING;
init_completion(&session->complete);
tbl = &session->fc_slot_table;
tbl->highest_used_slotid = -1;
spin_lock_init(&tbl->slot_tbl_lock);
rpc_init_priority_wait_queue(&tbl->slot_tbl_waitq, "ForeChannel Slot table");
tbl = &session->bc_slot_table;
tbl->highest_used_slotid = -1;
spin_lock_init(&tbl->slot_tbl_lock);
rpc_init_wait_queue(&tbl->slot_tbl_waitq, "BackChannel Slot table");
session->clp = clp;
return session;
}
void nfs4_destroy_session(struct nfs4_session *session)
{
nfs4_proc_destroy_session(session);
dprintk("%s Destroy backchannel for xprt %p\n",
__func__, session->clp->cl_rpcclient->cl_xprt);
xprt_destroy_backchannel(session->clp->cl_rpcclient->cl_xprt,
NFS41_BC_MIN_CALLBACKS);
nfs4_destroy_slot_tables(session);
kfree(session);
}
/*
* Initialize the values to be used by the client in CREATE_SESSION
* If nfs4_init_session set the fore channel request and response sizes,
* use them.
*
* Set the back channel max_resp_sz_cached to zero to force the client to
* always set csa_cachethis to FALSE because the current implementation
* of the back channel DRC only supports caching the CB_SEQUENCE operation.
*/
static void nfs4_init_channel_attrs(struct nfs41_create_session_args *args)
{
struct nfs4_session *session = args->client->cl_session;
unsigned int mxrqst_sz = session->fc_attrs.max_rqst_sz,
mxresp_sz = session->fc_attrs.max_resp_sz;
if (mxrqst_sz == 0)
mxrqst_sz = NFS_MAX_FILE_IO_SIZE;
if (mxresp_sz == 0)
mxresp_sz = NFS_MAX_FILE_IO_SIZE;
/* Fore channel attributes */
args->fc_attrs.headerpadsz = 0;
args->fc_attrs.max_rqst_sz = mxrqst_sz;
args->fc_attrs.max_resp_sz = mxresp_sz;
args->fc_attrs.max_ops = NFS4_MAX_OPS;
args->fc_attrs.max_reqs = session->clp->cl_rpcclient->cl_xprt->max_reqs;
dprintk("%s: Fore Channel : max_rqst_sz=%u max_resp_sz=%u "
"max_ops=%u max_reqs=%u\n",
__func__,
args->fc_attrs.max_rqst_sz, args->fc_attrs.max_resp_sz,
args->fc_attrs.max_ops, args->fc_attrs.max_reqs);
/* Back channel attributes */
args->bc_attrs.headerpadsz = 0;
args->bc_attrs.max_rqst_sz = PAGE_SIZE;
args->bc_attrs.max_resp_sz = PAGE_SIZE;
args->bc_attrs.max_resp_sz_cached = 0;
args->bc_attrs.max_ops = NFS4_MAX_BACK_CHANNEL_OPS;
args->bc_attrs.max_reqs = 1;
dprintk("%s: Back Channel : max_rqst_sz=%u max_resp_sz=%u "
"max_resp_sz_cached=%u max_ops=%u max_reqs=%u\n",
__func__,
args->bc_attrs.max_rqst_sz, args->bc_attrs.max_resp_sz,
args->bc_attrs.max_resp_sz_cached, args->bc_attrs.max_ops,
args->bc_attrs.max_reqs);
}
static int _verify_channel_attr(char *chan, char *attr_name, u32 sent, u32 rcvd)
{
if (rcvd <= sent)
return 0;
printk(KERN_WARNING "%s: Session INVALID: %s channel %s increased. "
"sent=%u rcvd=%u\n", __func__, chan, attr_name, sent, rcvd);
return -EINVAL;
}
#define _verify_fore_channel_attr(_name_) \
_verify_channel_attr("fore", #_name_, \
args->fc_attrs._name_, \
session->fc_attrs._name_)
#define _verify_back_channel_attr(_name_) \
_verify_channel_attr("back", #_name_, \
args->bc_attrs._name_, \
session->bc_attrs._name_)
/*
* The server is not allowed to increase the fore channel header pad size,
* maximum response size, or maximum number of operations.
*
* The back channel attributes are only negotiatied down: We send what the
* (back channel) server insists upon.
*/
static int nfs4_verify_channel_attrs(struct nfs41_create_session_args *args,
struct nfs4_session *session)
{
int ret = 0;
ret |= _verify_fore_channel_attr(headerpadsz);
ret |= _verify_fore_channel_attr(max_resp_sz);
ret |= _verify_fore_channel_attr(max_ops);
ret |= _verify_back_channel_attr(headerpadsz);
ret |= _verify_back_channel_attr(max_rqst_sz);
ret |= _verify_back_channel_attr(max_resp_sz);
ret |= _verify_back_channel_attr(max_resp_sz_cached);
ret |= _verify_back_channel_attr(max_ops);
ret |= _verify_back_channel_attr(max_reqs);
return ret;
}
static int _nfs4_proc_create_session(struct nfs_client *clp)
{
struct nfs4_session *session = clp->cl_session;
struct nfs41_create_session_args args = {
.client = clp,
.cb_program = NFS4_CALLBACK,
};
struct nfs41_create_session_res res = {
.client = clp,
};
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_CREATE_SESSION],
.rpc_argp = &args,
.rpc_resp = &res,
};
int status;
nfs4_init_channel_attrs(&args);
args.flags = (SESSION4_PERSIST | SESSION4_BACK_CHAN);
status = rpc_call_sync(session->clp->cl_rpcclient, &msg, 0);
if (!status)
/* Verify the session's negotiated channel_attrs values */
status = nfs4_verify_channel_attrs(&args, session);
if (!status) {
/* Increment the clientid slot sequence id */
clp->cl_seqid++;
}
return status;
}
/*
* Issues a CREATE_SESSION operation to the server.
* It is the responsibility of the caller to verify the session is
* expired before calling this routine.
*/
int nfs4_proc_create_session(struct nfs_client *clp)
{
int status;
unsigned *ptr;
struct nfs4_session *session = clp->cl_session;
dprintk("--> %s clp=%p session=%p\n", __func__, clp, session);
status = _nfs4_proc_create_session(clp);
if (status)
goto out;
/* Init and reset the fore channel */
status = nfs4_init_slot_tables(session);
dprintk("slot table initialization returned %d\n", status);
if (status)
goto out;
status = nfs4_reset_slot_tables(session);
dprintk("slot table reset returned %d\n", status);
if (status)
goto out;
ptr = (unsigned *)&session->sess_id.data[0];
dprintk("%s client>seqid %d sessionid %u:%u:%u:%u\n", __func__,
clp->cl_seqid, ptr[0], ptr[1], ptr[2], ptr[3]);
out:
dprintk("<-- %s\n", __func__);
return status;
}
/*
* Issue the over-the-wire RPC DESTROY_SESSION.
* The caller must serialize access to this routine.
*/
int nfs4_proc_destroy_session(struct nfs4_session *session)
{
int status = 0;
struct rpc_message msg;
dprintk("--> nfs4_proc_destroy_session\n");
/* session is still being setup */
if (session->clp->cl_cons_state != NFS_CS_READY)
return status;
msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_DESTROY_SESSION];
msg.rpc_argp = session;
msg.rpc_resp = NULL;
msg.rpc_cred = NULL;
status = rpc_call_sync(session->clp->cl_rpcclient, &msg, 0);
if (status)
printk(KERN_WARNING
"Got error %d from the server on DESTROY_SESSION. "
"Session has been destroyed regardless...\n", status);
dprintk("<-- nfs4_proc_destroy_session\n");
return status;
}
int nfs4_init_session(struct nfs_server *server)
{
struct nfs_client *clp = server->nfs_client;
struct nfs4_session *session;
unsigned int rsize, wsize;
int ret;
if (!nfs4_has_session(clp))
return 0;
rsize = server->rsize;
if (rsize == 0)
rsize = NFS_MAX_FILE_IO_SIZE;
wsize = server->wsize;
if (wsize == 0)
wsize = NFS_MAX_FILE_IO_SIZE;
session = clp->cl_session;
session->fc_attrs.max_rqst_sz = wsize + nfs41_maxwrite_overhead;
session->fc_attrs.max_resp_sz = rsize + nfs41_maxread_overhead;
ret = nfs4_recover_expired_lease(server);
if (!ret)
ret = nfs4_check_client_ready(clp);
return ret;
}
/*
* Renew the cl_session lease.
*/
static int nfs4_proc_sequence(struct nfs_client *clp, struct rpc_cred *cred)
{
struct nfs4_sequence_args args;
struct nfs4_sequence_res res;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SEQUENCE],
.rpc_argp = &args,
.rpc_resp = &res,
.rpc_cred = cred,
};
args.sa_cache_this = 0;
return nfs4_call_sync_sequence(clp, clp->cl_rpcclient, &msg, &args,
&res, args.sa_cache_this, 1);
}
static void nfs41_sequence_release(void *data)
{
struct nfs_client *clp = (struct nfs_client *)data;
if (atomic_read(&clp->cl_count) > 1)
nfs4_schedule_state_renewal(clp);
nfs_put_client(clp);
}
static void nfs41_sequence_call_done(struct rpc_task *task, void *data)
{
struct nfs_client *clp = (struct nfs_client *)data;
nfs41_sequence_done(clp, task->tk_msg.rpc_resp, task->tk_status);
if (task->tk_status < 0) {
dprintk("%s ERROR %d\n", __func__, task->tk_status);
if (atomic_read(&clp->cl_count) == 1)
goto out;
if (_nfs4_async_handle_error(task, NULL, clp, NULL)
== -EAGAIN) {
nfs_restart_rpc(task, clp);
return;
}
}
dprintk("%s rpc_cred %p\n", __func__, task->tk_msg.rpc_cred);
out:
kfree(task->tk_msg.rpc_argp);
kfree(task->tk_msg.rpc_resp);
dprintk("<-- %s\n", __func__);
}
static void nfs41_sequence_prepare(struct rpc_task *task, void *data)
{
struct nfs_client *clp;
struct nfs4_sequence_args *args;
struct nfs4_sequence_res *res;
clp = (struct nfs_client *)data;
args = task->tk_msg.rpc_argp;
res = task->tk_msg.rpc_resp;
if (nfs4_setup_sequence(clp, args, res, 0, task))
return;
rpc_call_start(task);
}
static const struct rpc_call_ops nfs41_sequence_ops = {
.rpc_call_done = nfs41_sequence_call_done,
.rpc_call_prepare = nfs41_sequence_prepare,
.rpc_release = nfs41_sequence_release,
};
static int nfs41_proc_async_sequence(struct nfs_client *clp,
struct rpc_cred *cred)
{
struct nfs4_sequence_args *args;
struct nfs4_sequence_res *res;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_SEQUENCE],
.rpc_cred = cred,
};
if (!atomic_inc_not_zero(&clp->cl_count))
return -EIO;
args = kzalloc(sizeof(*args), GFP_NOFS);
res = kzalloc(sizeof(*res), GFP_NOFS);
if (!args || !res) {
kfree(args);
kfree(res);
nfs_put_client(clp);
return -ENOMEM;
}
res->sr_slotid = NFS4_MAX_SLOT_TABLE;
msg.rpc_argp = args;
msg.rpc_resp = res;
return rpc_call_async(clp->cl_rpcclient, &msg, RPC_TASK_SOFT,
&nfs41_sequence_ops, (void *)clp);
}
struct nfs4_reclaim_complete_data {
struct nfs_client *clp;
struct nfs41_reclaim_complete_args arg;
struct nfs41_reclaim_complete_res res;
};
static void nfs4_reclaim_complete_prepare(struct rpc_task *task, void *data)
{
struct nfs4_reclaim_complete_data *calldata = data;
rpc_task_set_priority(task, RPC_PRIORITY_PRIVILEGED);
if (nfs4_setup_sequence(calldata->clp, &calldata->arg.seq_args,
&calldata->res.seq_res, 0, task))
return;
rpc_call_start(task);
}
static void nfs4_reclaim_complete_done(struct rpc_task *task, void *data)
{
struct nfs4_reclaim_complete_data *calldata = data;
struct nfs_client *clp = calldata->clp;
struct nfs4_sequence_res *res = &calldata->res.seq_res;
dprintk("--> %s\n", __func__);
nfs41_sequence_done(clp, res, task->tk_status);
switch (task->tk_status) {
case 0:
case -NFS4ERR_COMPLETE_ALREADY:
break;
case -NFS4ERR_BADSESSION:
case -NFS4ERR_DEADSESSION:
/*
* Handle the session error, but do not retry the operation, as
* we have no way of telling whether the clientid had to be
* reset before we got our reply. If reset, a new wave of
* reclaim operations will follow, containing their own reclaim
* complete. We don't want our retry to get on the way of
* recovery by incorrectly indicating to the server that we're
* done reclaiming state since the process had to be restarted.
*/
_nfs4_async_handle_error(task, NULL, clp, NULL);
break;
default:
if (_nfs4_async_handle_error(
task, NULL, clp, NULL) == -EAGAIN) {
rpc_restart_call_prepare(task);
return;
}
}
dprintk("<-- %s\n", __func__);
}
static void nfs4_free_reclaim_complete_data(void *data)
{
struct nfs4_reclaim_complete_data *calldata = data;
kfree(calldata);
}
static const struct rpc_call_ops nfs4_reclaim_complete_call_ops = {
.rpc_call_prepare = nfs4_reclaim_complete_prepare,
.rpc_call_done = nfs4_reclaim_complete_done,
.rpc_release = nfs4_free_reclaim_complete_data,
};
/*
* Issue a global reclaim complete.
*/
static int nfs41_proc_reclaim_complete(struct nfs_client *clp)
{
struct nfs4_reclaim_complete_data *calldata;
struct rpc_task *task;
struct rpc_message msg = {
.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_RECLAIM_COMPLETE],
};
struct rpc_task_setup task_setup_data = {
.rpc_client = clp->cl_rpcclient,
.rpc_message = &msg,
.callback_ops = &nfs4_reclaim_complete_call_ops,
.flags = RPC_TASK_ASYNC,
};
int status = -ENOMEM;
dprintk("--> %s\n", __func__);
calldata = kzalloc(sizeof(*calldata), GFP_NOFS);
if (calldata == NULL)
goto out;
calldata->clp = clp;
calldata->arg.one_fs = 0;
calldata->res.seq_res.sr_slotid = NFS4_MAX_SLOT_TABLE;
msg.rpc_argp = &calldata->arg;
msg.rpc_resp = &calldata->res;
task_setup_data.callback_data = calldata;
task = rpc_run_task(&task_setup_data);
if (IS_ERR(task)) {
status = PTR_ERR(task);
goto out;
}
rpc_put_task(task);
return 0;
out:
dprintk("<-- %s status=%d\n", __func__, status);
return status;
}
#endif /* CONFIG_NFS_V4_1 */
struct nfs4_state_recovery_ops nfs40_reboot_recovery_ops = {
.owner_flag_bit = NFS_OWNER_RECLAIM_REBOOT,
.state_flag_bit = NFS_STATE_RECLAIM_REBOOT,
.recover_open = nfs4_open_reclaim,
.recover_lock = nfs4_lock_reclaim,
.establish_clid = nfs4_init_clientid,
.get_clid_cred = nfs4_get_setclientid_cred,
};
#if defined(CONFIG_NFS_V4_1)
struct nfs4_state_recovery_ops nfs41_reboot_recovery_ops = {
.owner_flag_bit = NFS_OWNER_RECLAIM_REBOOT,
.state_flag_bit = NFS_STATE_RECLAIM_REBOOT,
.recover_open = nfs4_open_reclaim,
.recover_lock = nfs4_lock_reclaim,
.establish_clid = nfs41_init_clientid,
.get_clid_cred = nfs4_get_exchange_id_cred,
.reclaim_complete = nfs41_proc_reclaim_complete,
};
#endif /* CONFIG_NFS_V4_1 */
struct nfs4_state_recovery_ops nfs40_nograce_recovery_ops = {
.owner_flag_bit = NFS_OWNER_RECLAIM_NOGRACE,
.state_flag_bit = NFS_STATE_RECLAIM_NOGRACE,
.recover_open = nfs4_open_expired,
.recover_lock = nfs4_lock_expired,
.establish_clid = nfs4_init_clientid,
.get_clid_cred = nfs4_get_setclientid_cred,
};
#if defined(CONFIG_NFS_V4_1)
struct nfs4_state_recovery_ops nfs41_nograce_recovery_ops = {
.owner_flag_bit = NFS_OWNER_RECLAIM_NOGRACE,
.state_flag_bit = NFS_STATE_RECLAIM_NOGRACE,
.recover_open = nfs4_open_expired,
.recover_lock = nfs4_lock_expired,
.establish_clid = nfs41_init_clientid,
.get_clid_cred = nfs4_get_exchange_id_cred,
};
#endif /* CONFIG_NFS_V4_1 */
struct nfs4_state_maintenance_ops nfs40_state_renewal_ops = {
.sched_state_renewal = nfs4_proc_async_renew,
.get_state_renewal_cred_locked = nfs4_get_renew_cred_locked,
.renew_lease = nfs4_proc_renew,
};
#if defined(CONFIG_NFS_V4_1)
struct nfs4_state_maintenance_ops nfs41_state_renewal_ops = {
.sched_state_renewal = nfs41_proc_async_sequence,
.get_state_renewal_cred_locked = nfs4_get_machine_cred_locked,
.renew_lease = nfs4_proc_sequence,
};
#endif
/*
* Per minor version reboot and network partition recovery ops
*/
struct nfs4_state_recovery_ops *nfs4_reboot_recovery_ops[] = {
&nfs40_reboot_recovery_ops,
#if defined(CONFIG_NFS_V4_1)
&nfs41_reboot_recovery_ops,
#endif
};
struct nfs4_state_recovery_ops *nfs4_nograce_recovery_ops[] = {
&nfs40_nograce_recovery_ops,
#if defined(CONFIG_NFS_V4_1)
&nfs41_nograce_recovery_ops,
#endif
};
struct nfs4_state_maintenance_ops *nfs4_state_renewal_ops[] = {
&nfs40_state_renewal_ops,
#if defined(CONFIG_NFS_V4_1)
&nfs41_state_renewal_ops,
#endif
};
static const struct inode_operations nfs4_file_inode_operations = {
.permission = nfs_permission,
.getattr = nfs_getattr,
.setattr = nfs_setattr,
.getxattr = nfs4_getxattr,
.setxattr = nfs4_setxattr,
.listxattr = nfs4_listxattr,
};
const struct nfs_rpc_ops nfs_v4_clientops = {
.version = 4, /* protocol version */
.dentry_ops = &nfs4_dentry_operations,
.dir_inode_ops = &nfs4_dir_inode_operations,
.file_inode_ops = &nfs4_file_inode_operations,
.getroot = nfs4_proc_get_root,
.getattr = nfs4_proc_getattr,
.setattr = nfs4_proc_setattr,
.lookupfh = nfs4_proc_lookupfh,
.lookup = nfs4_proc_lookup,
.access = nfs4_proc_access,
.readlink = nfs4_proc_readlink,
.create = nfs4_proc_create,
.remove = nfs4_proc_remove,
.unlink_setup = nfs4_proc_unlink_setup,
.unlink_done = nfs4_proc_unlink_done,
.rename = nfs4_proc_rename,
.link = nfs4_proc_link,
.symlink = nfs4_proc_symlink,
.mkdir = nfs4_proc_mkdir,
.rmdir = nfs4_proc_remove,
.readdir = nfs4_proc_readdir,
.mknod = nfs4_proc_mknod,
.statfs = nfs4_proc_statfs,
.fsinfo = nfs4_proc_fsinfo,
.pathconf = nfs4_proc_pathconf,
.set_capabilities = nfs4_server_capabilities,
.decode_dirent = nfs4_decode_dirent,
.read_setup = nfs4_proc_read_setup,
.read_done = nfs4_read_done,
.write_setup = nfs4_proc_write_setup,
.write_done = nfs4_write_done,
.commit_setup = nfs4_proc_commit_setup,
.commit_done = nfs4_commit_done,
.lock = nfs4_proc_lock,
.clear_acl_cache = nfs4_zap_acl_attr,
.close_context = nfs4_close_context,
};
/*
* Local variables:
* c-basic-offset: 8
* End:
*/
| gpl-2.0 |
mirror-androidarmv6/android_kernel_huawei_msm7x25 | drivers/staging/rtl8187se/ieee80211/ieee80211_tx.c | 432 | 18858 | /******************************************************************************
Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of version 2 of the GNU General Public License as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
James P. Ketrenos <ipw2100-admin@linux.intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
******************************************************************************
Few modifications for Realtek's Wi-Fi drivers by
Andrea Merello <andreamrl@tiscali.it>
A special thanks goes to Realtek for their support !
******************************************************************************/
#include <linux/compiler.h>
//#include <linux/config.h>
#include <linux/errno.h>
#include <linux/if_arp.h>
#include <linux/in6.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/proc_fs.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <linux/tcp.h>
#include <linux/types.h>
#include <linux/version.h>
#include <linux/wireless.h>
#include <linux/etherdevice.h>
#include <asm/uaccess.h>
#include <linux/if_vlan.h>
#include "ieee80211.h"
/*
802.11 Data Frame
802.11 frame_contorl for data frames - 2 bytes
,-----------------------------------------------------------------------------------------.
bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b | c | d | e |
|----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|
val | 0 | 0 | 0 | 1 | x | 0 | 0 | 0 | 1 | 0 | x | x | x | x | x |
|----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------|
desc | ^-ver-^ | ^type-^ | ^-----subtype-----^ | to |from |more |retry| pwr |more |wep |
| | | x=0 data,x=1 data+ack | DS | DS |frag | | mgm |data | |
'-----------------------------------------------------------------------------------------'
/\
|
802.11 Data Frame |
,--------- 'ctrl' expands to >-----------'
|
,--'---,-------------------------------------------------------------.
Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
|------|------|---------|---------|---------|------|---------|------|
Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | Frame | fcs |
| | tion | (BSSID) | | | ence | data | |
`--------------------------------------------------| |------'
Total: 28 non-data bytes `----.----'
|
.- 'Frame data' expands to <---------------------------'
|
V
,---------------------------------------------------.
Bytes | 1 | 1 | 1 | 3 | 2 | 0-2304 |
|------|------|---------|----------|------|---------|
Desc. | SNAP | SNAP | Control |Eth Tunnel| Type | IP |
| DSAP | SSAP | | | | Packet |
| 0xAA | 0xAA |0x03 (UI)|0x00-00-F8| | |
`-----------------------------------------| |
Total: 8 non-data bytes `----.----'
|
.- 'IP Packet' expands, if WEP enabled, to <--'
|
V
,-----------------------.
Bytes | 4 | 0-2296 | 4 |
|-----|-----------|-----|
Desc. | IV | Encrypted | ICV |
| | IP Packet | |
`-----------------------'
Total: 8 non-data bytes
802.3 Ethernet Data Frame
,-----------------------------------------.
Bytes | 6 | 6 | 2 | Variable | 4 |
|-------|-------|------|-----------|------|
Desc. | Dest. | Source| Type | IP Packet | fcs |
| MAC | MAC | | | |
`-----------------------------------------'
Total: 18 non-data bytes
In the event that fragmentation is required, the incoming payload is split into
N parts of size ieee->fts. The first fragment contains the SNAP header and the
remaining packets are just data.
If encryption is enabled, each fragment payload size is reduced by enough space
to add the prefix and postfix (IV and ICV totalling 8 bytes in the case of WEP)
So if you have 1500 bytes of payload with ieee->fts set to 500 without
encryption it will take 3 frames. With WEP it will take 4 frames as the
payload of each frame is reduced to 492 bytes.
* SKB visualization
*
* ,- skb->data
* |
* | ETHERNET HEADER ,-<-- PAYLOAD
* | | 14 bytes from skb->data
* | 2 bytes for Type --> ,T. | (sizeof ethhdr)
* | | | |
* |,-Dest.--. ,--Src.---. | | |
* | 6 bytes| | 6 bytes | | | |
* v | | | | | |
* 0 | v 1 | v | v 2
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
* ^ | ^ | ^ |
* | | | | | |
* | | | | `T' <---- 2 bytes for Type
* | | | |
* | | '---SNAP--' <-------- 6 bytes for SNAP
* | |
* `-IV--' <-------------------- 4 bytes for IV (WEP)
*
* SNAP HEADER
*
*/
static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
static inline int ieee80211_put_snap(u8 *data, u16 h_proto)
{
struct ieee80211_snap_hdr *snap;
u8 *oui;
snap = (struct ieee80211_snap_hdr *)data;
snap->dsap = 0xaa;
snap->ssap = 0xaa;
snap->ctrl = 0x03;
if (h_proto == 0x8137 || h_proto == 0x80f3)
oui = P802_1H_OUI;
else
oui = RFC1042_OUI;
snap->oui[0] = oui[0];
snap->oui[1] = oui[1];
snap->oui[2] = oui[2];
*(u16 *)(data + SNAP_SIZE) = htons(h_proto);
return SNAP_SIZE + sizeof(u16);
}
int ieee80211_encrypt_fragment(
struct ieee80211_device *ieee,
struct sk_buff *frag,
int hdr_len)
{
struct ieee80211_crypt_data* crypt = ieee->crypt[ieee->tx_keyidx];
int res;
/*added to care about null crypt condition, to solve that system hangs when shared keys error*/
if (!crypt || !crypt->ops)
return -1;
#ifdef CONFIG_IEEE80211_CRYPT_TKIP
struct ieee80211_hdr_4addr *header;
if (ieee->tkip_countermeasures &&
crypt && crypt->ops && strcmp(crypt->ops->name, "TKIP") == 0) {
header = (struct ieee80211_hdr_4addr *)frag->data;
if (net_ratelimit()) {
printk(KERN_DEBUG "%s: TKIP countermeasures: dropped "
"TX packet to " MAC_FMT "\n",
ieee->dev->name, MAC_ARG(header->addr1));
}
return -1;
}
#endif
/* To encrypt, frame format is:
* IV (4 bytes), clear payload (including SNAP), ICV (4 bytes) */
// PR: FIXME: Copied from hostap. Check fragmentation/MSDU/MPDU encryption.
/* Host-based IEEE 802.11 fragmentation for TX is not yet supported, so
* call both MSDU and MPDU encryption functions from here. */
atomic_inc(&crypt->refcnt);
res = 0;
if (crypt->ops->encrypt_msdu)
res = crypt->ops->encrypt_msdu(frag, hdr_len, crypt->priv);
if (res == 0 && crypt->ops->encrypt_mpdu)
res = crypt->ops->encrypt_mpdu(frag, hdr_len, crypt->priv);
atomic_dec(&crypt->refcnt);
if (res < 0) {
printk(KERN_INFO "%s: Encryption failed: len=%d.\n",
ieee->dev->name, frag->len);
ieee->ieee_stats.tx_discards++;
return -1;
}
return 0;
}
void ieee80211_txb_free(struct ieee80211_txb *txb) {
int i;
if (unlikely(!txb))
return;
for (i = 0; i < txb->nr_frags; i++)
if (txb->fragments[i])
dev_kfree_skb_any(txb->fragments[i]);
kfree(txb);
}
struct ieee80211_txb *ieee80211_alloc_txb(int nr_frags, int txb_size,
int gfp_mask)
{
struct ieee80211_txb *txb;
int i;
txb = kmalloc(
sizeof(struct ieee80211_txb) + (sizeof(u8*) * nr_frags),
gfp_mask);
if (!txb)
return NULL;
memset(txb, 0, sizeof(struct ieee80211_txb));
txb->nr_frags = nr_frags;
txb->frag_size = txb_size;
for (i = 0; i < nr_frags; i++) {
txb->fragments[i] = dev_alloc_skb(txb_size);
if (unlikely(!txb->fragments[i])) {
i--;
break;
}
}
if (unlikely(i != nr_frags)) {
while (i >= 0)
dev_kfree_skb_any(txb->fragments[i--]);
kfree(txb);
return NULL;
}
return txb;
}
// Classify the to-be send data packet
// Need to acquire the sent queue index.
static int
ieee80211_classify(struct sk_buff *skb, struct ieee80211_network *network)
{
struct ether_header *eh = (struct ether_header*)skb->data;
unsigned int wme_UP = 0;
if(!network->QoS_Enable) {
skb->priority = 0;
return(wme_UP);
}
if(eh->ether_type == __constant_htons(ETHERTYPE_IP)) {
const struct iphdr *ih = (struct iphdr*)(skb->data + \
sizeof(struct ether_header));
wme_UP = (ih->tos >> 5)&0x07;
} else if (vlan_tx_tag_present(skb)) {//vtag packet
#ifndef VLAN_PRI_SHIFT
#define VLAN_PRI_SHIFT 13 /* Shift to find VLAN user priority */
#define VLAN_PRI_MASK 7 /* Mask for user priority bits in VLAN */
#endif
u32 tag = vlan_tx_tag_get(skb);
wme_UP = (tag >> VLAN_PRI_SHIFT) & VLAN_PRI_MASK;
} else if(ETH_P_PAE == ntohs(((struct ethhdr *)skb->data)->h_proto)) {
//printk(KERN_WARNING "type = normal packet\n");
wme_UP = 7;
}
skb->priority = wme_UP;
return(wme_UP);
}
/* SKBs are added to the ieee->tx_queue. */
int ieee80211_rtl_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct ieee80211_device *ieee = netdev_priv(dev);
struct ieee80211_txb *txb = NULL;
struct ieee80211_hdr_3addrqos *frag_hdr;
int i, bytes_per_frag, nr_frags, bytes_last_frag, frag_size;
unsigned long flags;
struct net_device_stats *stats = &ieee->stats;
int ether_type, encrypt;
int bytes, fc, qos_ctl, hdr_len;
struct sk_buff *skb_frag;
struct ieee80211_hdr_3addrqos header = { /* Ensure zero initialized */
.duration_id = 0,
.seq_ctl = 0,
.qos_ctl = 0
};
u8 dest[ETH_ALEN], src[ETH_ALEN];
struct ieee80211_crypt_data* crypt;
//printk(KERN_WARNING "upper layer packet!\n");
spin_lock_irqsave(&ieee->lock, flags);
/* If there is no driver handler to take the TXB, dont' bother
* creating it... */
if ((!ieee->hard_start_xmit && !(ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE))||
((!ieee->softmac_data_hard_start_xmit && (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)))) {
printk(KERN_WARNING "%s: No xmit handler.\n",
ieee->dev->name);
goto success;
}
ieee80211_classify(skb,&ieee->current_network);
if(likely(ieee->raw_tx == 0)){
if (unlikely(skb->len < SNAP_SIZE + sizeof(u16))) {
printk(KERN_WARNING "%s: skb too small (%d).\n",
ieee->dev->name, skb->len);
goto success;
}
ether_type = ntohs(((struct ethhdr *)skb->data)->h_proto);
crypt = ieee->crypt[ieee->tx_keyidx];
encrypt = !(ether_type == ETH_P_PAE && ieee->ieee802_1x) &&
ieee->host_encrypt && crypt && crypt->ops;
if (!encrypt && ieee->ieee802_1x &&
ieee->drop_unencrypted && ether_type != ETH_P_PAE) {
stats->tx_dropped++;
goto success;
}
#ifdef CONFIG_IEEE80211_DEBUG
if (crypt && !encrypt && ether_type == ETH_P_PAE) {
struct eapol *eap = (struct eapol *)(skb->data +
sizeof(struct ethhdr) - SNAP_SIZE - sizeof(u16));
IEEE80211_DEBUG_EAP("TX: IEEE 802.11 EAPOL frame: %s\n",
eap_get_type(eap->type));
}
#endif
/* Save source and destination addresses */
memcpy(&dest, skb->data, ETH_ALEN);
memcpy(&src, skb->data+ETH_ALEN, ETH_ALEN);
/* Advance the SKB to the start of the payload */
skb_pull(skb, sizeof(struct ethhdr));
/* Determine total amount of storage required for TXB packets */
bytes = skb->len + SNAP_SIZE + sizeof(u16);
if(ieee->current_network.QoS_Enable) {
if (encrypt)
fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA |
IEEE80211_FCTL_WEP;
else
fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA;
} else {
if (encrypt)
fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA |
IEEE80211_FCTL_WEP;
else
fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA;
}
if (ieee->iw_mode == IW_MODE_INFRA) {
fc |= IEEE80211_FCTL_TODS;
/* To DS: Addr1 = BSSID, Addr2 = SA,
Addr3 = DA */
memcpy(&header.addr1, ieee->current_network.bssid, ETH_ALEN);
memcpy(&header.addr2, &src, ETH_ALEN);
memcpy(&header.addr3, &dest, ETH_ALEN);
} else if (ieee->iw_mode == IW_MODE_ADHOC) {
/* not From/To DS: Addr1 = DA, Addr2 = SA,
Addr3 = BSSID */
memcpy(&header.addr1, dest, ETH_ALEN);
memcpy(&header.addr2, src, ETH_ALEN);
memcpy(&header.addr3, ieee->current_network.bssid, ETH_ALEN);
}
// printk(KERN_WARNING "essid MAC address is "MAC_FMT, MAC_ARG(&header.addr1));
header.frame_ctl = cpu_to_le16(fc);
//hdr_len = IEEE80211_3ADDR_LEN;
/* Determine fragmentation size based on destination (multicast
* and broadcast are not fragmented) */
// if (is_multicast_ether_addr(dest) ||
// is_broadcast_ether_addr(dest)) {
if (is_multicast_ether_addr(header.addr1) ||
is_broadcast_ether_addr(header.addr1)) {
frag_size = MAX_FRAG_THRESHOLD;
qos_ctl = QOS_CTL_NOTCONTAIN_ACK;
}
else {
//printk(KERN_WARNING "&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&frag_size = %d\n", frag_size);
frag_size = ieee->fts;//default:392
qos_ctl = 0;
}
if (ieee->current_network.QoS_Enable) {
hdr_len = IEEE80211_3ADDR_LEN + 2;
/* skb->priority is set in the ieee80211_classify() */
qos_ctl |= skb->priority;
header.qos_ctl = cpu_to_le16(qos_ctl);
} else {
hdr_len = IEEE80211_3ADDR_LEN;
}
/* Determine amount of payload per fragment. Regardless of if
* this stack is providing the full 802.11 header, one will
* eventually be affixed to this fragment -- so we must account for
* it when determining the amount of payload space. */
//bytes_per_frag = frag_size - (IEEE80211_3ADDR_LEN + (ieee->current_network->QoS_Enable ? 2:0));
bytes_per_frag = frag_size - hdr_len;
if (ieee->config &
(CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS))
bytes_per_frag -= IEEE80211_FCS_LEN;
/* Each fragment may need to have room for encryptiong pre/postfix */
if (encrypt)
bytes_per_frag -= crypt->ops->extra_prefix_len +
crypt->ops->extra_postfix_len;
/* Number of fragments is the total bytes_per_frag /
* payload_per_fragment */
nr_frags = bytes / bytes_per_frag;
bytes_last_frag = bytes % bytes_per_frag;
if (bytes_last_frag)
nr_frags++;
else
bytes_last_frag = bytes_per_frag;
/* When we allocate the TXB we allocate enough space for the reserve
* and full fragment bytes (bytes_per_frag doesn't include prefix,
* postfix, header, FCS, etc.) */
txb = ieee80211_alloc_txb(nr_frags, frag_size, GFP_ATOMIC);
if (unlikely(!txb)) {
printk(KERN_WARNING "%s: Could not allocate TXB\n",
ieee->dev->name);
goto failed;
}
txb->encrypted = encrypt;
txb->payload_size = bytes;
for (i = 0; i < nr_frags; i++) {
skb_frag = txb->fragments[i];
skb_frag->priority = UP2AC(skb->priority);
if (encrypt)
skb_reserve(skb_frag, crypt->ops->extra_prefix_len);
frag_hdr = (struct ieee80211_hdr_3addrqos *)skb_put(skb_frag, hdr_len);
memcpy(frag_hdr, &header, hdr_len);
/* If this is not the last fragment, then add the MOREFRAGS
* bit to the frame control */
if (i != nr_frags - 1) {
frag_hdr->frame_ctl = cpu_to_le16(
fc | IEEE80211_FCTL_MOREFRAGS);
bytes = bytes_per_frag;
} else {
/* The last fragment takes the remaining length */
bytes = bytes_last_frag;
}
if(ieee->current_network.QoS_Enable) {
// add 1 only indicate to corresponding seq number control 2006/7/12
frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[UP2AC(skb->priority)+1]<<4 | i);
//printk(KERN_WARNING "skb->priority = %d,", skb->priority);
//printk(KERN_WARNING "type:%d: seq = %d\n",UP2AC(skb->priority),ieee->seq_ctrl[UP2AC(skb->priority)+1]);
} else {
frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4 | i);
}
//frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl<<4 | i);
//
/* Put a SNAP header on the first fragment */
if (i == 0) {
ieee80211_put_snap(
skb_put(skb_frag, SNAP_SIZE + sizeof(u16)),
ether_type);
bytes -= SNAP_SIZE + sizeof(u16);
}
memcpy(skb_put(skb_frag, bytes), skb->data, bytes);
/* Advance the SKB... */
skb_pull(skb, bytes);
/* Encryption routine will move the header forward in order
* to insert the IV between the header and the payload */
if (encrypt)
ieee80211_encrypt_fragment(ieee, skb_frag, hdr_len);
if (ieee->config &
(CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS))
skb_put(skb_frag, 4);
}
// Advance sequence number in data frame.
//printk(KERN_WARNING "QoS Enalbed? %s\n", ieee->current_network.QoS_Enable?"Y":"N");
if (ieee->current_network.QoS_Enable) {
if (ieee->seq_ctrl[UP2AC(skb->priority) + 1] == 0xFFF)
ieee->seq_ctrl[UP2AC(skb->priority) + 1] = 0;
else
ieee->seq_ctrl[UP2AC(skb->priority) + 1]++;
} else {
if (ieee->seq_ctrl[0] == 0xFFF)
ieee->seq_ctrl[0] = 0;
else
ieee->seq_ctrl[0]++;
}
//---
}else{
if (unlikely(skb->len < sizeof(struct ieee80211_hdr_3addr))) {
printk(KERN_WARNING "%s: skb too small (%d).\n",
ieee->dev->name, skb->len);
goto success;
}
txb = ieee80211_alloc_txb(1, skb->len, GFP_ATOMIC);
if(!txb){
printk(KERN_WARNING "%s: Could not allocate TXB\n",
ieee->dev->name);
goto failed;
}
txb->encrypted = 0;
txb->payload_size = skb->len;
memcpy(skb_put(txb->fragments[0],skb->len), skb->data, skb->len);
}
success:
spin_unlock_irqrestore(&ieee->lock, flags);
dev_kfree_skb_any(skb);
if (txb) {
if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE){
ieee80211_softmac_xmit(txb, ieee);
}else{
if ((*ieee->hard_start_xmit)(txb, dev) == 0) {
stats->tx_packets++;
stats->tx_bytes += txb->payload_size;
return NETDEV_TX_OK;
}
ieee80211_txb_free(txb);
}
}
return NETDEV_TX_OK;
failed:
spin_unlock_irqrestore(&ieee->lock, flags);
netif_stop_queue(dev);
stats->tx_errors++;
return NETDEV_TX_BUSY;
}
| gpl-2.0 |
Channing-Y/kernel | drivers/dma/mv_xor.c | 432 | 36344 | /*
* offload engine driver for the Marvell XOR engine
* Copyright (C) 2007, 2008, Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/memory.h>
#include <plat/mv_xor.h>
#include "mv_xor.h"
static void mv_xor_issue_pending(struct dma_chan *chan);
#define to_mv_xor_chan(chan) \
container_of(chan, struct mv_xor_chan, common)
#define to_mv_xor_device(dev) \
container_of(dev, struct mv_xor_device, common)
#define to_mv_xor_slot(tx) \
container_of(tx, struct mv_xor_desc_slot, async_tx)
static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
hw_desc->status = (1 << 31);
hw_desc->phy_next_desc = 0;
hw_desc->desc_command = (1 << 31);
}
static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
return hw_desc->phy_dest_addr;
}
static u32 mv_desc_get_src_addr(struct mv_xor_desc_slot *desc,
int src_idx)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
return hw_desc->phy_src_addr[src_idx];
}
static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
u32 byte_count)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
hw_desc->byte_count = byte_count;
}
static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
u32 next_desc_addr)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
BUG_ON(hw_desc->phy_next_desc);
hw_desc->phy_next_desc = next_desc_addr;
}
static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
hw_desc->phy_next_desc = 0;
}
static void mv_desc_set_block_fill_val(struct mv_xor_desc_slot *desc, u32 val)
{
desc->value = val;
}
static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
dma_addr_t addr)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
hw_desc->phy_dest_addr = addr;
}
static int mv_chan_memset_slot_count(size_t len)
{
return 1;
}
#define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
int index, dma_addr_t addr)
{
struct mv_xor_desc *hw_desc = desc->hw_desc;
hw_desc->phy_src_addr[index] = addr;
if (desc->type == DMA_XOR)
hw_desc->desc_command |= (1 << index);
}
static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
{
return __raw_readl(XOR_CURR_DESC(chan));
}
static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
u32 next_desc_addr)
{
__raw_writel(next_desc_addr, XOR_NEXT_DESC(chan));
}
static void mv_chan_set_dest_pointer(struct mv_xor_chan *chan, u32 desc_addr)
{
__raw_writel(desc_addr, XOR_DEST_POINTER(chan));
}
static void mv_chan_set_block_size(struct mv_xor_chan *chan, u32 block_size)
{
__raw_writel(block_size, XOR_BLOCK_SIZE(chan));
}
static void mv_chan_set_value(struct mv_xor_chan *chan, u32 value)
{
__raw_writel(value, XOR_INIT_VALUE_LOW(chan));
__raw_writel(value, XOR_INIT_VALUE_HIGH(chan));
}
static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
{
u32 val = __raw_readl(XOR_INTR_MASK(chan));
val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
__raw_writel(val, XOR_INTR_MASK(chan));
}
static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
{
u32 intr_cause = __raw_readl(XOR_INTR_CAUSE(chan));
intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
return intr_cause;
}
static int mv_is_err_intr(u32 intr_cause)
{
if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
return 1;
return 0;
}
static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
{
u32 val = (1 << (1 + (chan->idx * 16)));
dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
__raw_writel(val, XOR_INTR_CAUSE(chan));
}
static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
{
u32 val = 0xFFFF0000 >> (chan->idx * 16);
__raw_writel(val, XOR_INTR_CAUSE(chan));
}
static int mv_can_chain(struct mv_xor_desc_slot *desc)
{
struct mv_xor_desc_slot *chain_old_tail = list_entry(
desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
if (chain_old_tail->type != desc->type)
return 0;
if (desc->type == DMA_MEMSET)
return 0;
return 1;
}
static void mv_set_mode(struct mv_xor_chan *chan,
enum dma_transaction_type type)
{
u32 op_mode;
u32 config = __raw_readl(XOR_CONFIG(chan));
switch (type) {
case DMA_XOR:
op_mode = XOR_OPERATION_MODE_XOR;
break;
case DMA_MEMCPY:
op_mode = XOR_OPERATION_MODE_MEMCPY;
break;
case DMA_MEMSET:
op_mode = XOR_OPERATION_MODE_MEMSET;
break;
default:
dev_printk(KERN_ERR, chan->device->common.dev,
"error: unsupported operation %d.\n",
type);
BUG();
return;
}
config &= ~0x7;
config |= op_mode;
__raw_writel(config, XOR_CONFIG(chan));
chan->current_type = type;
}
static void mv_chan_activate(struct mv_xor_chan *chan)
{
u32 activation;
dev_dbg(chan->device->common.dev, " activate chan.\n");
activation = __raw_readl(XOR_ACTIVATION(chan));
activation |= 0x1;
__raw_writel(activation, XOR_ACTIVATION(chan));
}
static char mv_chan_is_busy(struct mv_xor_chan *chan)
{
u32 state = __raw_readl(XOR_ACTIVATION(chan));
state = (state >> 4) & 0x3;
return (state == 1) ? 1 : 0;
}
static int mv_chan_xor_slot_count(size_t len, int src_cnt)
{
return 1;
}
/**
* mv_xor_free_slots - flags descriptor slots for reuse
* @slot: Slot to free
* Caller must hold &mv_chan->lock while calling this function
*/
static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
struct mv_xor_desc_slot *slot)
{
dev_dbg(mv_chan->device->common.dev, "%s %d slot %p\n",
__func__, __LINE__, slot);
slot->slots_per_op = 0;
}
/*
* mv_xor_start_new_chain - program the engine to operate on new chain headed by
* sw_desc
* Caller must hold &mv_chan->lock while calling this function
*/
static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
struct mv_xor_desc_slot *sw_desc)
{
dev_dbg(mv_chan->device->common.dev, "%s %d: sw_desc %p\n",
__func__, __LINE__, sw_desc);
if (sw_desc->type != mv_chan->current_type)
mv_set_mode(mv_chan, sw_desc->type);
if (sw_desc->type == DMA_MEMSET) {
/* for memset requests we need to program the engine, no
* descriptors used.
*/
struct mv_xor_desc *hw_desc = sw_desc->hw_desc;
mv_chan_set_dest_pointer(mv_chan, hw_desc->phy_dest_addr);
mv_chan_set_block_size(mv_chan, sw_desc->unmap_len);
mv_chan_set_value(mv_chan, sw_desc->value);
} else {
/* set the hardware chain */
mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
}
mv_chan->pending += sw_desc->slot_cnt;
mv_xor_issue_pending(&mv_chan->common);
}
static dma_cookie_t
mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
{
BUG_ON(desc->async_tx.cookie < 0);
if (desc->async_tx.cookie > 0) {
cookie = desc->async_tx.cookie;
/* call the callback (must not sleep or submit new
* operations to this channel)
*/
if (desc->async_tx.callback)
desc->async_tx.callback(
desc->async_tx.callback_param);
/* unmap dma addresses
* (unmap_single vs unmap_page?)
*/
if (desc->group_head && desc->unmap_len) {
struct mv_xor_desc_slot *unmap = desc->group_head;
struct device *dev =
&mv_chan->device->pdev->dev;
u32 len = unmap->unmap_len;
enum dma_ctrl_flags flags = desc->async_tx.flags;
u32 src_cnt;
dma_addr_t addr;
dma_addr_t dest;
src_cnt = unmap->unmap_src_cnt;
dest = mv_desc_get_dest_addr(unmap);
if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
enum dma_data_direction dir;
if (src_cnt > 1) /* is xor ? */
dir = DMA_BIDIRECTIONAL;
else
dir = DMA_FROM_DEVICE;
dma_unmap_page(dev, dest, len, dir);
}
if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
while (src_cnt--) {
addr = mv_desc_get_src_addr(unmap,
src_cnt);
if (addr == dest)
continue;
dma_unmap_page(dev, addr, len,
DMA_TO_DEVICE);
}
}
desc->group_head = NULL;
}
}
/* run dependent operations */
dma_run_dependencies(&desc->async_tx);
return cookie;
}
static int
mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
{
struct mv_xor_desc_slot *iter, *_iter;
dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
completed_node) {
if (async_tx_test_ack(&iter->async_tx)) {
list_del(&iter->completed_node);
mv_xor_free_slots(mv_chan, iter);
}
}
return 0;
}
static int
mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
struct mv_xor_chan *mv_chan)
{
dev_dbg(mv_chan->device->common.dev, "%s %d: desc %p flags %d\n",
__func__, __LINE__, desc, desc->async_tx.flags);
list_del(&desc->chain_node);
/* the client is allowed to attach dependent operations
* until 'ack' is set
*/
if (!async_tx_test_ack(&desc->async_tx)) {
/* move this slot to the completed_slots */
list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
return 0;
}
mv_xor_free_slots(mv_chan, desc);
return 0;
}
static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
{
struct mv_xor_desc_slot *iter, *_iter;
dma_cookie_t cookie = 0;
int busy = mv_chan_is_busy(mv_chan);
u32 current_desc = mv_chan_get_current_desc(mv_chan);
int seen_current = 0;
dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
dev_dbg(mv_chan->device->common.dev, "current_desc %x\n", current_desc);
mv_xor_clean_completed_slots(mv_chan);
/* free completed slots from the chain starting with
* the oldest descriptor
*/
list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
chain_node) {
prefetch(_iter);
prefetch(&_iter->async_tx);
/* do not advance past the current descriptor loaded into the
* hardware channel, subsequent descriptors are either in
* process or have not been submitted
*/
if (seen_current)
break;
/* stop the search if we reach the current descriptor and the
* channel is busy
*/
if (iter->async_tx.phys == current_desc) {
seen_current = 1;
if (busy)
break;
}
cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
if (mv_xor_clean_slot(iter, mv_chan))
break;
}
if ((busy == 0) && !list_empty(&mv_chan->chain)) {
struct mv_xor_desc_slot *chain_head;
chain_head = list_entry(mv_chan->chain.next,
struct mv_xor_desc_slot,
chain_node);
mv_xor_start_new_chain(mv_chan, chain_head);
}
if (cookie > 0)
mv_chan->completed_cookie = cookie;
}
static void
mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
{
spin_lock_bh(&mv_chan->lock);
__mv_xor_slot_cleanup(mv_chan);
spin_unlock_bh(&mv_chan->lock);
}
static void mv_xor_tasklet(unsigned long data)
{
struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
__mv_xor_slot_cleanup(chan);
}
static struct mv_xor_desc_slot *
mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
int slots_per_op)
{
struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
LIST_HEAD(chain);
int slots_found, retry = 0;
/* start search from the last allocated descrtiptor
* if a contiguous allocation can not be found start searching
* from the beginning of the list
*/
retry:
slots_found = 0;
if (retry == 0)
iter = mv_chan->last_used;
else
iter = list_entry(&mv_chan->all_slots,
struct mv_xor_desc_slot,
slot_node);
list_for_each_entry_safe_continue(
iter, _iter, &mv_chan->all_slots, slot_node) {
prefetch(_iter);
prefetch(&_iter->async_tx);
if (iter->slots_per_op) {
/* give up after finding the first busy slot
* on the second pass through the list
*/
if (retry)
break;
slots_found = 0;
continue;
}
/* start the allocation if the slot is correctly aligned */
if (!slots_found++)
alloc_start = iter;
if (slots_found == num_slots) {
struct mv_xor_desc_slot *alloc_tail = NULL;
struct mv_xor_desc_slot *last_used = NULL;
iter = alloc_start;
while (num_slots) {
int i;
/* pre-ack all but the last descriptor */
async_tx_ack(&iter->async_tx);
list_add_tail(&iter->chain_node, &chain);
alloc_tail = iter;
iter->async_tx.cookie = 0;
iter->slot_cnt = num_slots;
iter->xor_check_result = NULL;
for (i = 0; i < slots_per_op; i++) {
iter->slots_per_op = slots_per_op - i;
last_used = iter;
iter = list_entry(iter->slot_node.next,
struct mv_xor_desc_slot,
slot_node);
}
num_slots -= slots_per_op;
}
alloc_tail->group_head = alloc_start;
alloc_tail->async_tx.cookie = -EBUSY;
list_splice(&chain, &alloc_tail->tx_list);
mv_chan->last_used = last_used;
mv_desc_clear_next_desc(alloc_start);
mv_desc_clear_next_desc(alloc_tail);
return alloc_tail;
}
}
if (!retry++)
goto retry;
/* try to free some slots if the allocation fails */
tasklet_schedule(&mv_chan->irq_tasklet);
return NULL;
}
static dma_cookie_t
mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
struct mv_xor_desc_slot *desc)
{
dma_cookie_t cookie = mv_chan->common.cookie;
if (++cookie < 0)
cookie = 1;
mv_chan->common.cookie = desc->async_tx.cookie = cookie;
return cookie;
}
/************************ DMA engine API functions ****************************/
static dma_cookie_t
mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
struct mv_xor_desc_slot *grp_start, *old_chain_tail;
dma_cookie_t cookie;
int new_hw_chain = 1;
dev_dbg(mv_chan->device->common.dev,
"%s sw_desc %p: async_tx %p\n",
__func__, sw_desc, &sw_desc->async_tx);
grp_start = sw_desc->group_head;
spin_lock_bh(&mv_chan->lock);
cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
if (list_empty(&mv_chan->chain))
list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
else {
new_hw_chain = 0;
old_chain_tail = list_entry(mv_chan->chain.prev,
struct mv_xor_desc_slot,
chain_node);
list_splice_init(&grp_start->tx_list,
&old_chain_tail->chain_node);
if (!mv_can_chain(grp_start))
goto submit_done;
dev_dbg(mv_chan->device->common.dev, "Append to last desc %x\n",
old_chain_tail->async_tx.phys);
/* fix up the hardware chain */
mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
/* if the channel is not busy */
if (!mv_chan_is_busy(mv_chan)) {
u32 current_desc = mv_chan_get_current_desc(mv_chan);
/*
* and the curren desc is the end of the chain before
* the append, then we need to start the channel
*/
if (current_desc == old_chain_tail->async_tx.phys)
new_hw_chain = 1;
}
}
if (new_hw_chain)
mv_xor_start_new_chain(mv_chan, grp_start);
submit_done:
spin_unlock_bh(&mv_chan->lock);
return cookie;
}
/* returns the number of allocated descriptors */
static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
{
char *hw_desc;
int idx;
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
struct mv_xor_desc_slot *slot = NULL;
struct mv_xor_platform_data *plat_data =
mv_chan->device->pdev->dev.platform_data;
int num_descs_in_pool = plat_data->pool_size/MV_XOR_SLOT_SIZE;
/* Allocate descriptor slots */
idx = mv_chan->slots_allocated;
while (idx < num_descs_in_pool) {
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
if (!slot) {
printk(KERN_INFO "MV XOR Channel only initialized"
" %d descriptor slots", idx);
break;
}
hw_desc = (char *) mv_chan->device->dma_desc_pool_virt;
slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
dma_async_tx_descriptor_init(&slot->async_tx, chan);
slot->async_tx.tx_submit = mv_xor_tx_submit;
INIT_LIST_HEAD(&slot->chain_node);
INIT_LIST_HEAD(&slot->slot_node);
INIT_LIST_HEAD(&slot->tx_list);
hw_desc = (char *) mv_chan->device->dma_desc_pool;
slot->async_tx.phys =
(dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
slot->idx = idx++;
spin_lock_bh(&mv_chan->lock);
mv_chan->slots_allocated = idx;
list_add_tail(&slot->slot_node, &mv_chan->all_slots);
spin_unlock_bh(&mv_chan->lock);
}
if (mv_chan->slots_allocated && !mv_chan->last_used)
mv_chan->last_used = list_entry(mv_chan->all_slots.next,
struct mv_xor_desc_slot,
slot_node);
dev_dbg(mv_chan->device->common.dev,
"allocated %d descriptor slots last_used: %p\n",
mv_chan->slots_allocated, mv_chan->last_used);
return mv_chan->slots_allocated ? : -ENOMEM;
}
static struct dma_async_tx_descriptor *
mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
size_t len, unsigned long flags)
{
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
struct mv_xor_desc_slot *sw_desc, *grp_start;
int slot_cnt;
dev_dbg(mv_chan->device->common.dev,
"%s dest: %x src %x len: %u flags: %ld\n",
__func__, dest, src, len, flags);
if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
return NULL;
BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
spin_lock_bh(&mv_chan->lock);
slot_cnt = mv_chan_memcpy_slot_count(len);
sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
if (sw_desc) {
sw_desc->type = DMA_MEMCPY;
sw_desc->async_tx.flags = flags;
grp_start = sw_desc->group_head;
mv_desc_init(grp_start, flags);
mv_desc_set_byte_count(grp_start, len);
mv_desc_set_dest_addr(sw_desc->group_head, dest);
mv_desc_set_src_addr(grp_start, 0, src);
sw_desc->unmap_src_cnt = 1;
sw_desc->unmap_len = len;
}
spin_unlock_bh(&mv_chan->lock);
dev_dbg(mv_chan->device->common.dev,
"%s sw_desc %p async_tx %p\n",
__func__, sw_desc, sw_desc ? &sw_desc->async_tx : 0);
return sw_desc ? &sw_desc->async_tx : NULL;
}
static struct dma_async_tx_descriptor *
mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
size_t len, unsigned long flags)
{
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
struct mv_xor_desc_slot *sw_desc, *grp_start;
int slot_cnt;
dev_dbg(mv_chan->device->common.dev,
"%s dest: %x len: %u flags: %ld\n",
__func__, dest, len, flags);
if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
return NULL;
BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
spin_lock_bh(&mv_chan->lock);
slot_cnt = mv_chan_memset_slot_count(len);
sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
if (sw_desc) {
sw_desc->type = DMA_MEMSET;
sw_desc->async_tx.flags = flags;
grp_start = sw_desc->group_head;
mv_desc_init(grp_start, flags);
mv_desc_set_byte_count(grp_start, len);
mv_desc_set_dest_addr(sw_desc->group_head, dest);
mv_desc_set_block_fill_val(grp_start, value);
sw_desc->unmap_src_cnt = 1;
sw_desc->unmap_len = len;
}
spin_unlock_bh(&mv_chan->lock);
dev_dbg(mv_chan->device->common.dev,
"%s sw_desc %p async_tx %p \n",
__func__, sw_desc, &sw_desc->async_tx);
return sw_desc ? &sw_desc->async_tx : NULL;
}
static struct dma_async_tx_descriptor *
mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
unsigned int src_cnt, size_t len, unsigned long flags)
{
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
struct mv_xor_desc_slot *sw_desc, *grp_start;
int slot_cnt;
if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
return NULL;
BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
dev_dbg(mv_chan->device->common.dev,
"%s src_cnt: %d len: dest %x %u flags: %ld\n",
__func__, src_cnt, len, dest, flags);
spin_lock_bh(&mv_chan->lock);
slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
if (sw_desc) {
sw_desc->type = DMA_XOR;
sw_desc->async_tx.flags = flags;
grp_start = sw_desc->group_head;
mv_desc_init(grp_start, flags);
/* the byte count field is the same as in memcpy desc*/
mv_desc_set_byte_count(grp_start, len);
mv_desc_set_dest_addr(sw_desc->group_head, dest);
sw_desc->unmap_src_cnt = src_cnt;
sw_desc->unmap_len = len;
while (src_cnt--)
mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
}
spin_unlock_bh(&mv_chan->lock);
dev_dbg(mv_chan->device->common.dev,
"%s sw_desc %p async_tx %p \n",
__func__, sw_desc, &sw_desc->async_tx);
return sw_desc ? &sw_desc->async_tx : NULL;
}
static void mv_xor_free_chan_resources(struct dma_chan *chan)
{
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
struct mv_xor_desc_slot *iter, *_iter;
int in_use_descs = 0;
mv_xor_slot_cleanup(mv_chan);
spin_lock_bh(&mv_chan->lock);
list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
chain_node) {
in_use_descs++;
list_del(&iter->chain_node);
}
list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
completed_node) {
in_use_descs++;
list_del(&iter->completed_node);
}
list_for_each_entry_safe_reverse(
iter, _iter, &mv_chan->all_slots, slot_node) {
list_del(&iter->slot_node);
kfree(iter);
mv_chan->slots_allocated--;
}
mv_chan->last_used = NULL;
dev_dbg(mv_chan->device->common.dev, "%s slots_allocated %d\n",
__func__, mv_chan->slots_allocated);
spin_unlock_bh(&mv_chan->lock);
if (in_use_descs)
dev_err(mv_chan->device->common.dev,
"freeing %d in use descriptors!\n", in_use_descs);
}
/**
* mv_xor_status - poll the status of an XOR transaction
* @chan: XOR channel handle
* @cookie: XOR transaction identifier
* @txstate: XOR transactions state holder (or NULL)
*/
static enum dma_status mv_xor_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
dma_cookie_t last_used;
dma_cookie_t last_complete;
enum dma_status ret;
last_used = chan->cookie;
last_complete = mv_chan->completed_cookie;
mv_chan->is_complete_cookie = cookie;
dma_set_tx_state(txstate, last_complete, last_used, 0);
ret = dma_async_is_complete(cookie, last_complete, last_used);
if (ret == DMA_SUCCESS) {
mv_xor_clean_completed_slots(mv_chan);
return ret;
}
mv_xor_slot_cleanup(mv_chan);
last_used = chan->cookie;
last_complete = mv_chan->completed_cookie;
dma_set_tx_state(txstate, last_complete, last_used, 0);
return dma_async_is_complete(cookie, last_complete, last_used);
}
static void mv_dump_xor_regs(struct mv_xor_chan *chan)
{
u32 val;
val = __raw_readl(XOR_CONFIG(chan));
dev_printk(KERN_ERR, chan->device->common.dev,
"config 0x%08x.\n", val);
val = __raw_readl(XOR_ACTIVATION(chan));
dev_printk(KERN_ERR, chan->device->common.dev,
"activation 0x%08x.\n", val);
val = __raw_readl(XOR_INTR_CAUSE(chan));
dev_printk(KERN_ERR, chan->device->common.dev,
"intr cause 0x%08x.\n", val);
val = __raw_readl(XOR_INTR_MASK(chan));
dev_printk(KERN_ERR, chan->device->common.dev,
"intr mask 0x%08x.\n", val);
val = __raw_readl(XOR_ERROR_CAUSE(chan));
dev_printk(KERN_ERR, chan->device->common.dev,
"error cause 0x%08x.\n", val);
val = __raw_readl(XOR_ERROR_ADDR(chan));
dev_printk(KERN_ERR, chan->device->common.dev,
"error addr 0x%08x.\n", val);
}
static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
u32 intr_cause)
{
if (intr_cause & (1 << 4)) {
dev_dbg(chan->device->common.dev,
"ignore this error\n");
return;
}
dev_printk(KERN_ERR, chan->device->common.dev,
"error on chan %d. intr cause 0x%08x.\n",
chan->idx, intr_cause);
mv_dump_xor_regs(chan);
BUG();
}
static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
{
struct mv_xor_chan *chan = data;
u32 intr_cause = mv_chan_get_intr_cause(chan);
dev_dbg(chan->device->common.dev, "intr cause %x\n", intr_cause);
if (mv_is_err_intr(intr_cause))
mv_xor_err_interrupt_handler(chan, intr_cause);
tasklet_schedule(&chan->irq_tasklet);
mv_xor_device_clear_eoc_cause(chan);
return IRQ_HANDLED;
}
static void mv_xor_issue_pending(struct dma_chan *chan)
{
struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
if (mv_chan->pending >= MV_XOR_THRESHOLD) {
mv_chan->pending = 0;
mv_chan_activate(mv_chan);
}
}
/*
* Perform a transaction to verify the HW works.
*/
#define MV_XOR_TEST_SIZE 2000
static int __devinit mv_xor_memcpy_self_test(struct mv_xor_device *device)
{
int i;
void *src, *dest;
dma_addr_t src_dma, dest_dma;
struct dma_chan *dma_chan;
dma_cookie_t cookie;
struct dma_async_tx_descriptor *tx;
int err = 0;
struct mv_xor_chan *mv_chan;
src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
if (!src)
return -ENOMEM;
dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
if (!dest) {
kfree(src);
return -ENOMEM;
}
/* Fill in src buffer */
for (i = 0; i < MV_XOR_TEST_SIZE; i++)
((u8 *) src)[i] = (u8)i;
/* Start copy, using first DMA channel */
dma_chan = container_of(device->common.channels.next,
struct dma_chan,
device_node);
if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
err = -ENODEV;
goto out;
}
dest_dma = dma_map_single(dma_chan->device->dev, dest,
MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
src_dma = dma_map_single(dma_chan->device->dev, src,
MV_XOR_TEST_SIZE, DMA_TO_DEVICE);
tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
MV_XOR_TEST_SIZE, 0);
cookie = mv_xor_tx_submit(tx);
mv_xor_issue_pending(dma_chan);
async_tx_ack(tx);
msleep(1);
if (mv_xor_status(dma_chan, cookie, NULL) !=
DMA_SUCCESS) {
dev_printk(KERN_ERR, dma_chan->device->dev,
"Self-test copy timed out, disabling\n");
err = -ENODEV;
goto free_resources;
}
mv_chan = to_mv_xor_chan(dma_chan);
dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
dev_printk(KERN_ERR, dma_chan->device->dev,
"Self-test copy failed compare, disabling\n");
err = -ENODEV;
goto free_resources;
}
free_resources:
mv_xor_free_chan_resources(dma_chan);
out:
kfree(src);
kfree(dest);
return err;
}
#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
static int __devinit
mv_xor_xor_self_test(struct mv_xor_device *device)
{
int i, src_idx;
struct page *dest;
struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
dma_addr_t dest_dma;
struct dma_async_tx_descriptor *tx;
struct dma_chan *dma_chan;
dma_cookie_t cookie;
u8 cmp_byte = 0;
u32 cmp_word;
int err = 0;
struct mv_xor_chan *mv_chan;
for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
if (!xor_srcs[src_idx]) {
while (src_idx--)
__free_page(xor_srcs[src_idx]);
return -ENOMEM;
}
}
dest = alloc_page(GFP_KERNEL);
if (!dest) {
while (src_idx--)
__free_page(xor_srcs[src_idx]);
return -ENOMEM;
}
/* Fill in src buffers */
for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
u8 *ptr = page_address(xor_srcs[src_idx]);
for (i = 0; i < PAGE_SIZE; i++)
ptr[i] = (1 << src_idx);
}
for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++)
cmp_byte ^= (u8) (1 << src_idx);
cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
(cmp_byte << 8) | cmp_byte;
memset(page_address(dest), 0, PAGE_SIZE);
dma_chan = container_of(device->common.channels.next,
struct dma_chan,
device_node);
if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
err = -ENODEV;
goto out;
}
/* test xor */
dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
DMA_FROM_DEVICE);
for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++)
dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
0, PAGE_SIZE, DMA_TO_DEVICE);
tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0);
cookie = mv_xor_tx_submit(tx);
mv_xor_issue_pending(dma_chan);
async_tx_ack(tx);
msleep(8);
if (mv_xor_status(dma_chan, cookie, NULL) !=
DMA_SUCCESS) {
dev_printk(KERN_ERR, dma_chan->device->dev,
"Self-test xor timed out, disabling\n");
err = -ENODEV;
goto free_resources;
}
mv_chan = to_mv_xor_chan(dma_chan);
dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
PAGE_SIZE, DMA_FROM_DEVICE);
for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
u32 *ptr = page_address(dest);
if (ptr[i] != cmp_word) {
dev_printk(KERN_ERR, dma_chan->device->dev,
"Self-test xor failed compare, disabling."
" index %d, data %x, expected %x\n", i,
ptr[i], cmp_word);
err = -ENODEV;
goto free_resources;
}
}
free_resources:
mv_xor_free_chan_resources(dma_chan);
out:
src_idx = MV_XOR_NUM_SRC_TEST;
while (src_idx--)
__free_page(xor_srcs[src_idx]);
__free_page(dest);
return err;
}
static int __devexit mv_xor_remove(struct platform_device *dev)
{
struct mv_xor_device *device = platform_get_drvdata(dev);
struct dma_chan *chan, *_chan;
struct mv_xor_chan *mv_chan;
struct mv_xor_platform_data *plat_data = dev->dev.platform_data;
dma_async_device_unregister(&device->common);
dma_free_coherent(&dev->dev, plat_data->pool_size,
device->dma_desc_pool_virt, device->dma_desc_pool);
list_for_each_entry_safe(chan, _chan, &device->common.channels,
device_node) {
mv_chan = to_mv_xor_chan(chan);
list_del(&chan->device_node);
}
return 0;
}
static int __devinit mv_xor_probe(struct platform_device *pdev)
{
int ret = 0;
int irq;
struct mv_xor_device *adev;
struct mv_xor_chan *mv_chan;
struct dma_device *dma_dev;
struct mv_xor_platform_data *plat_data = pdev->dev.platform_data;
adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
if (!adev)
return -ENOMEM;
dma_dev = &adev->common;
/* allocate coherent memory for hardware descriptors
* note: writecombine gives slightly better performance, but
* requires that we explicitly flush the writes
*/
adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
plat_data->pool_size,
&adev->dma_desc_pool,
GFP_KERNEL);
if (!adev->dma_desc_pool_virt)
return -ENOMEM;
adev->id = plat_data->hw_id;
/* discover transaction capabilites from the platform data */
dma_dev->cap_mask = plat_data->cap_mask;
adev->pdev = pdev;
platform_set_drvdata(pdev, adev);
adev->shared = platform_get_drvdata(plat_data->shared);
INIT_LIST_HEAD(&dma_dev->channels);
/* set base routines */
dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
dma_dev->device_tx_status = mv_xor_status;
dma_dev->device_issue_pending = mv_xor_issue_pending;
dma_dev->dev = &pdev->dev;
/* set prep routines based on capability */
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
dma_dev->device_prep_dma_memset = mv_xor_prep_dma_memset;
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
dma_dev->max_xor = 8;
dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
}
mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
if (!mv_chan) {
ret = -ENOMEM;
goto err_free_dma;
}
mv_chan->device = adev;
mv_chan->idx = plat_data->hw_id;
mv_chan->mmr_base = adev->shared->xor_base;
if (!mv_chan->mmr_base) {
ret = -ENOMEM;
goto err_free_dma;
}
tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
mv_chan);
/* clear errors before enabling interrupts */
mv_xor_device_clear_err_status(mv_chan);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto err_free_dma;
}
ret = devm_request_irq(&pdev->dev, irq,
mv_xor_interrupt_handler,
0, dev_name(&pdev->dev), mv_chan);
if (ret)
goto err_free_dma;
mv_chan_unmask_interrupts(mv_chan);
mv_set_mode(mv_chan, DMA_MEMCPY);
spin_lock_init(&mv_chan->lock);
INIT_LIST_HEAD(&mv_chan->chain);
INIT_LIST_HEAD(&mv_chan->completed_slots);
INIT_LIST_HEAD(&mv_chan->all_slots);
mv_chan->common.device = dma_dev;
list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
ret = mv_xor_memcpy_self_test(adev);
dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
if (ret)
goto err_free_dma;
}
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
ret = mv_xor_xor_self_test(adev);
dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
if (ret)
goto err_free_dma;
}
dev_printk(KERN_INFO, &pdev->dev, "Marvell XOR: "
"( %s%s%s%s)\n",
dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
dma_async_device_register(dma_dev);
goto out;
err_free_dma:
dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
adev->dma_desc_pool_virt, adev->dma_desc_pool);
out:
return ret;
}
static void
mv_xor_conf_mbus_windows(struct mv_xor_shared_private *msp,
struct mbus_dram_target_info *dram)
{
void __iomem *base = msp->xor_base;
u32 win_enable = 0;
int i;
for (i = 0; i < 8; i++) {
writel(0, base + WINDOW_BASE(i));
writel(0, base + WINDOW_SIZE(i));
if (i < 4)
writel(0, base + WINDOW_REMAP_HIGH(i));
}
for (i = 0; i < dram->num_cs; i++) {
struct mbus_dram_window *cs = dram->cs + i;
writel((cs->base & 0xffff0000) |
(cs->mbus_attr << 8) |
dram->mbus_dram_target_id, base + WINDOW_BASE(i));
writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
win_enable |= (1 << i);
win_enable |= 3 << (16 + (2 * i));
}
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
}
static struct platform_driver mv_xor_driver = {
.probe = mv_xor_probe,
.remove = __devexit_p(mv_xor_remove),
.driver = {
.owner = THIS_MODULE,
.name = MV_XOR_NAME,
},
};
static int mv_xor_shared_probe(struct platform_device *pdev)
{
struct mv_xor_platform_shared_data *msd = pdev->dev.platform_data;
struct mv_xor_shared_private *msp;
struct resource *res;
dev_printk(KERN_NOTICE, &pdev->dev, "Marvell shared XOR driver\n");
msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
if (!msp)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
msp->xor_base = devm_ioremap(&pdev->dev, res->start,
res->end - res->start + 1);
if (!msp->xor_base)
return -EBUSY;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res)
return -ENODEV;
msp->xor_high_base = devm_ioremap(&pdev->dev, res->start,
res->end - res->start + 1);
if (!msp->xor_high_base)
return -EBUSY;
platform_set_drvdata(pdev, msp);
/*
* (Re-)program MBUS remapping windows if we are asked to.
*/
if (msd != NULL && msd->dram != NULL)
mv_xor_conf_mbus_windows(msp, msd->dram);
return 0;
}
static int mv_xor_shared_remove(struct platform_device *pdev)
{
return 0;
}
static struct platform_driver mv_xor_shared_driver = {
.probe = mv_xor_shared_probe,
.remove = mv_xor_shared_remove,
.driver = {
.owner = THIS_MODULE,
.name = MV_XOR_SHARED_NAME,
},
};
static int __init mv_xor_init(void)
{
int rc;
rc = platform_driver_register(&mv_xor_shared_driver);
if (!rc) {
rc = platform_driver_register(&mv_xor_driver);
if (rc)
platform_driver_unregister(&mv_xor_shared_driver);
}
return rc;
}
module_init(mv_xor_init);
/* it's currently unsafe to unload this module */
#if 0
static void __exit mv_xor_exit(void)
{
platform_driver_unregister(&mv_xor_driver);
platform_driver_unregister(&mv_xor_shared_driver);
return;
}
module_exit(mv_xor_exit);
#endif
MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
MODULE_LICENSE("GPL");
| gpl-2.0 |
MarginC/linux | fs/nfsd/nfscache.c | 688 | 16427 | /*
* Request reply cache. This is currently a global cache, but this may
* change in the future and be a per-client cache.
*
* This code is heavily inspired by the 44BSD implementation, although
* it does things a bit differently.
*
* Copyright (C) 1995, 1996 Olaf Kirch <okir@monad.swb.de>
*/
#include <linux/slab.h>
#include <linux/sunrpc/addr.h>
#include <linux/highmem.h>
#include <linux/log2.h>
#include <linux/hash.h>
#include <net/checksum.h>
#include "nfsd.h"
#include "cache.h"
#define NFSDDBG_FACILITY NFSDDBG_REPCACHE
/*
* We use this value to determine the number of hash buckets from the max
* cache size, the idea being that when the cache is at its maximum number
* of entries, then this should be the average number of entries per bucket.
*/
#define TARGET_BUCKET_SIZE 64
struct nfsd_drc_bucket {
struct list_head lru_head;
spinlock_t cache_lock;
};
static struct nfsd_drc_bucket *drc_hashtbl;
static struct kmem_cache *drc_slab;
/* max number of entries allowed in the cache */
static unsigned int max_drc_entries;
/* number of significant bits in the hash value */
static unsigned int maskbits;
static unsigned int drc_hashsize;
/*
* Stats and other tracking of on the duplicate reply cache. All of these and
* the "rc" fields in nfsdstats are protected by the cache_lock
*/
/* total number of entries */
static atomic_t num_drc_entries;
/* cache misses due only to checksum comparison failures */
static unsigned int payload_misses;
/* amount of memory (in bytes) currently consumed by the DRC */
static unsigned int drc_mem_usage;
/* longest hash chain seen */
static unsigned int longest_chain;
/* size of cache when we saw the longest hash chain */
static unsigned int longest_chain_cachesize;
static int nfsd_cache_append(struct svc_rqst *rqstp, struct kvec *vec);
static void cache_cleaner_func(struct work_struct *unused);
static unsigned long nfsd_reply_cache_count(struct shrinker *shrink,
struct shrink_control *sc);
static unsigned long nfsd_reply_cache_scan(struct shrinker *shrink,
struct shrink_control *sc);
static struct shrinker nfsd_reply_cache_shrinker = {
.scan_objects = nfsd_reply_cache_scan,
.count_objects = nfsd_reply_cache_count,
.seeks = 1,
};
/*
* locking for the reply cache:
* A cache entry is "single use" if c_state == RC_INPROG
* Otherwise, it when accessing _prev or _next, the lock must be held.
*/
static DECLARE_DELAYED_WORK(cache_cleaner, cache_cleaner_func);
/*
* Put a cap on the size of the DRC based on the amount of available
* low memory in the machine.
*
* 64MB: 8192
* 128MB: 11585
* 256MB: 16384
* 512MB: 23170
* 1GB: 32768
* 2GB: 46340
* 4GB: 65536
* 8GB: 92681
* 16GB: 131072
*
* ...with a hard cap of 256k entries. In the worst case, each entry will be
* ~1k, so the above numbers should give a rough max of the amount of memory
* used in k.
*/
static unsigned int
nfsd_cache_size_limit(void)
{
unsigned int limit;
unsigned long low_pages = totalram_pages - totalhigh_pages;
limit = (16 * int_sqrt(low_pages)) << (PAGE_SHIFT-10);
return min_t(unsigned int, limit, 256*1024);
}
/*
* Compute the number of hash buckets we need. Divide the max cachesize by
* the "target" max bucket size, and round up to next power of two.
*/
static unsigned int
nfsd_hashsize(unsigned int limit)
{
return roundup_pow_of_two(limit / TARGET_BUCKET_SIZE);
}
static u32
nfsd_cache_hash(__be32 xid)
{
return hash_32(be32_to_cpu(xid), maskbits);
}
static struct svc_cacherep *
nfsd_reply_cache_alloc(void)
{
struct svc_cacherep *rp;
rp = kmem_cache_alloc(drc_slab, GFP_KERNEL);
if (rp) {
rp->c_state = RC_UNUSED;
rp->c_type = RC_NOCACHE;
INIT_LIST_HEAD(&rp->c_lru);
}
return rp;
}
static void
nfsd_reply_cache_free_locked(struct svc_cacherep *rp)
{
if (rp->c_type == RC_REPLBUFF && rp->c_replvec.iov_base) {
drc_mem_usage -= rp->c_replvec.iov_len;
kfree(rp->c_replvec.iov_base);
}
list_del(&rp->c_lru);
atomic_dec(&num_drc_entries);
drc_mem_usage -= sizeof(*rp);
kmem_cache_free(drc_slab, rp);
}
static void
nfsd_reply_cache_free(struct nfsd_drc_bucket *b, struct svc_cacherep *rp)
{
spin_lock(&b->cache_lock);
nfsd_reply_cache_free_locked(rp);
spin_unlock(&b->cache_lock);
}
int nfsd_reply_cache_init(void)
{
unsigned int hashsize;
unsigned int i;
int status = 0;
max_drc_entries = nfsd_cache_size_limit();
atomic_set(&num_drc_entries, 0);
hashsize = nfsd_hashsize(max_drc_entries);
maskbits = ilog2(hashsize);
status = register_shrinker(&nfsd_reply_cache_shrinker);
if (status)
return status;
drc_slab = kmem_cache_create("nfsd_drc", sizeof(struct svc_cacherep),
0, 0, NULL);
if (!drc_slab)
goto out_nomem;
drc_hashtbl = kcalloc(hashsize, sizeof(*drc_hashtbl), GFP_KERNEL);
if (!drc_hashtbl)
goto out_nomem;
for (i = 0; i < hashsize; i++) {
INIT_LIST_HEAD(&drc_hashtbl[i].lru_head);
spin_lock_init(&drc_hashtbl[i].cache_lock);
}
drc_hashsize = hashsize;
return 0;
out_nomem:
printk(KERN_ERR "nfsd: failed to allocate reply cache\n");
nfsd_reply_cache_shutdown();
return -ENOMEM;
}
void nfsd_reply_cache_shutdown(void)
{
struct svc_cacherep *rp;
unsigned int i;
unregister_shrinker(&nfsd_reply_cache_shrinker);
cancel_delayed_work_sync(&cache_cleaner);
for (i = 0; i < drc_hashsize; i++) {
struct list_head *head = &drc_hashtbl[i].lru_head;
while (!list_empty(head)) {
rp = list_first_entry(head, struct svc_cacherep, c_lru);
nfsd_reply_cache_free_locked(rp);
}
}
kfree (drc_hashtbl);
drc_hashtbl = NULL;
drc_hashsize = 0;
if (drc_slab) {
kmem_cache_destroy(drc_slab);
drc_slab = NULL;
}
}
/*
* Move cache entry to end of LRU list, and queue the cleaner to run if it's
* not already scheduled.
*/
static void
lru_put_end(struct nfsd_drc_bucket *b, struct svc_cacherep *rp)
{
rp->c_timestamp = jiffies;
list_move_tail(&rp->c_lru, &b->lru_head);
schedule_delayed_work(&cache_cleaner, RC_EXPIRE);
}
static long
prune_bucket(struct nfsd_drc_bucket *b)
{
struct svc_cacherep *rp, *tmp;
long freed = 0;
list_for_each_entry_safe(rp, tmp, &b->lru_head, c_lru) {
/*
* Don't free entries attached to calls that are still
* in-progress, but do keep scanning the list.
*/
if (rp->c_state == RC_INPROG)
continue;
if (atomic_read(&num_drc_entries) <= max_drc_entries &&
time_before(jiffies, rp->c_timestamp + RC_EXPIRE))
break;
nfsd_reply_cache_free_locked(rp);
freed++;
}
return freed;
}
/*
* Walk the LRU list and prune off entries that are older than RC_EXPIRE.
* Also prune the oldest ones when the total exceeds the max number of entries.
*/
static long
prune_cache_entries(void)
{
unsigned int i;
long freed = 0;
bool cancel = true;
for (i = 0; i < drc_hashsize; i++) {
struct nfsd_drc_bucket *b = &drc_hashtbl[i];
if (list_empty(&b->lru_head))
continue;
spin_lock(&b->cache_lock);
freed += prune_bucket(b);
if (!list_empty(&b->lru_head))
cancel = false;
spin_unlock(&b->cache_lock);
}
/*
* Conditionally rearm the job to run in RC_EXPIRE since we just
* ran the pruner.
*/
if (!cancel)
mod_delayed_work(system_wq, &cache_cleaner, RC_EXPIRE);
return freed;
}
static void
cache_cleaner_func(struct work_struct *unused)
{
prune_cache_entries();
}
static unsigned long
nfsd_reply_cache_count(struct shrinker *shrink, struct shrink_control *sc)
{
return atomic_read(&num_drc_entries);
}
static unsigned long
nfsd_reply_cache_scan(struct shrinker *shrink, struct shrink_control *sc)
{
return prune_cache_entries();
}
/*
* Walk an xdr_buf and get a CRC for at most the first RC_CSUMLEN bytes
*/
static __wsum
nfsd_cache_csum(struct svc_rqst *rqstp)
{
int idx;
unsigned int base;
__wsum csum;
struct xdr_buf *buf = &rqstp->rq_arg;
const unsigned char *p = buf->head[0].iov_base;
size_t csum_len = min_t(size_t, buf->head[0].iov_len + buf->page_len,
RC_CSUMLEN);
size_t len = min(buf->head[0].iov_len, csum_len);
/* rq_arg.head first */
csum = csum_partial(p, len, 0);
csum_len -= len;
/* Continue into page array */
idx = buf->page_base / PAGE_SIZE;
base = buf->page_base & ~PAGE_MASK;
while (csum_len) {
p = page_address(buf->pages[idx]) + base;
len = min_t(size_t, PAGE_SIZE - base, csum_len);
csum = csum_partial(p, len, csum);
csum_len -= len;
base = 0;
++idx;
}
return csum;
}
static bool
nfsd_cache_match(struct svc_rqst *rqstp, __wsum csum, struct svc_cacherep *rp)
{
/* Check RPC XID first */
if (rqstp->rq_xid != rp->c_xid)
return false;
/* compare checksum of NFS data */
if (csum != rp->c_csum) {
++payload_misses;
return false;
}
/* Other discriminators */
if (rqstp->rq_proc != rp->c_proc ||
rqstp->rq_prot != rp->c_prot ||
rqstp->rq_vers != rp->c_vers ||
rqstp->rq_arg.len != rp->c_len ||
!rpc_cmp_addr(svc_addr(rqstp), (struct sockaddr *)&rp->c_addr) ||
rpc_get_port(svc_addr(rqstp)) != rpc_get_port((struct sockaddr *)&rp->c_addr))
return false;
return true;
}
/*
* Search the request hash for an entry that matches the given rqstp.
* Must be called with cache_lock held. Returns the found entry or
* NULL on failure.
*/
static struct svc_cacherep *
nfsd_cache_search(struct nfsd_drc_bucket *b, struct svc_rqst *rqstp,
__wsum csum)
{
struct svc_cacherep *rp, *ret = NULL;
struct list_head *rh = &b->lru_head;
unsigned int entries = 0;
list_for_each_entry(rp, rh, c_lru) {
++entries;
if (nfsd_cache_match(rqstp, csum, rp)) {
ret = rp;
break;
}
}
/* tally hash chain length stats */
if (entries > longest_chain) {
longest_chain = entries;
longest_chain_cachesize = atomic_read(&num_drc_entries);
} else if (entries == longest_chain) {
/* prefer to keep the smallest cachesize possible here */
longest_chain_cachesize = min_t(unsigned int,
longest_chain_cachesize,
atomic_read(&num_drc_entries));
}
return ret;
}
/*
* Try to find an entry matching the current call in the cache. When none
* is found, we try to grab the oldest expired entry off the LRU list. If
* a suitable one isn't there, then drop the cache_lock and allocate a
* new one, then search again in case one got inserted while this thread
* didn't hold the lock.
*/
int
nfsd_cache_lookup(struct svc_rqst *rqstp)
{
struct svc_cacherep *rp, *found;
__be32 xid = rqstp->rq_xid;
u32 proto = rqstp->rq_prot,
vers = rqstp->rq_vers,
proc = rqstp->rq_proc;
__wsum csum;
u32 hash = nfsd_cache_hash(xid);
struct nfsd_drc_bucket *b = &drc_hashtbl[hash];
unsigned long age;
int type = rqstp->rq_cachetype;
int rtn = RC_DOIT;
rqstp->rq_cacherep = NULL;
if (type == RC_NOCACHE) {
nfsdstats.rcnocache++;
return rtn;
}
csum = nfsd_cache_csum(rqstp);
/*
* Since the common case is a cache miss followed by an insert,
* preallocate an entry.
*/
rp = nfsd_reply_cache_alloc();
spin_lock(&b->cache_lock);
if (likely(rp)) {
atomic_inc(&num_drc_entries);
drc_mem_usage += sizeof(*rp);
}
/* go ahead and prune the cache */
prune_bucket(b);
found = nfsd_cache_search(b, rqstp, csum);
if (found) {
if (likely(rp))
nfsd_reply_cache_free_locked(rp);
rp = found;
goto found_entry;
}
if (!rp) {
dprintk("nfsd: unable to allocate DRC entry!\n");
goto out;
}
nfsdstats.rcmisses++;
rqstp->rq_cacherep = rp;
rp->c_state = RC_INPROG;
rp->c_xid = xid;
rp->c_proc = proc;
rpc_copy_addr((struct sockaddr *)&rp->c_addr, svc_addr(rqstp));
rpc_set_port((struct sockaddr *)&rp->c_addr, rpc_get_port(svc_addr(rqstp)));
rp->c_prot = proto;
rp->c_vers = vers;
rp->c_len = rqstp->rq_arg.len;
rp->c_csum = csum;
lru_put_end(b, rp);
/* release any buffer */
if (rp->c_type == RC_REPLBUFF) {
drc_mem_usage -= rp->c_replvec.iov_len;
kfree(rp->c_replvec.iov_base);
rp->c_replvec.iov_base = NULL;
}
rp->c_type = RC_NOCACHE;
out:
spin_unlock(&b->cache_lock);
return rtn;
found_entry:
nfsdstats.rchits++;
/* We found a matching entry which is either in progress or done. */
age = jiffies - rp->c_timestamp;
lru_put_end(b, rp);
rtn = RC_DROPIT;
/* Request being processed or excessive rexmits */
if (rp->c_state == RC_INPROG || age < RC_DELAY)
goto out;
/* From the hall of fame of impractical attacks:
* Is this a user who tries to snoop on the cache? */
rtn = RC_DOIT;
if (!test_bit(RQ_SECURE, &rqstp->rq_flags) && rp->c_secure)
goto out;
/* Compose RPC reply header */
switch (rp->c_type) {
case RC_NOCACHE:
break;
case RC_REPLSTAT:
svc_putu32(&rqstp->rq_res.head[0], rp->c_replstat);
rtn = RC_REPLY;
break;
case RC_REPLBUFF:
if (!nfsd_cache_append(rqstp, &rp->c_replvec))
goto out; /* should not happen */
rtn = RC_REPLY;
break;
default:
printk(KERN_WARNING "nfsd: bad repcache type %d\n", rp->c_type);
nfsd_reply_cache_free_locked(rp);
}
goto out;
}
/*
* Update a cache entry. This is called from nfsd_dispatch when
* the procedure has been executed and the complete reply is in
* rqstp->rq_res.
*
* We're copying around data here rather than swapping buffers because
* the toplevel loop requires max-sized buffers, which would be a waste
* of memory for a cache with a max reply size of 100 bytes (diropokres).
*
* If we should start to use different types of cache entries tailored
* specifically for attrstat and fh's, we may save even more space.
*
* Also note that a cachetype of RC_NOCACHE can legally be passed when
* nfsd failed to encode a reply that otherwise would have been cached.
* In this case, nfsd_cache_update is called with statp == NULL.
*/
void
nfsd_cache_update(struct svc_rqst *rqstp, int cachetype, __be32 *statp)
{
struct svc_cacherep *rp = rqstp->rq_cacherep;
struct kvec *resv = &rqstp->rq_res.head[0], *cachv;
u32 hash;
struct nfsd_drc_bucket *b;
int len;
size_t bufsize = 0;
if (!rp)
return;
hash = nfsd_cache_hash(rp->c_xid);
b = &drc_hashtbl[hash];
len = resv->iov_len - ((char*)statp - (char*)resv->iov_base);
len >>= 2;
/* Don't cache excessive amounts of data and XDR failures */
if (!statp || len > (256 >> 2)) {
nfsd_reply_cache_free(b, rp);
return;
}
switch (cachetype) {
case RC_REPLSTAT:
if (len != 1)
printk("nfsd: RC_REPLSTAT/reply len %d!\n",len);
rp->c_replstat = *statp;
break;
case RC_REPLBUFF:
cachv = &rp->c_replvec;
bufsize = len << 2;
cachv->iov_base = kmalloc(bufsize, GFP_KERNEL);
if (!cachv->iov_base) {
nfsd_reply_cache_free(b, rp);
return;
}
cachv->iov_len = bufsize;
memcpy(cachv->iov_base, statp, bufsize);
break;
case RC_NOCACHE:
nfsd_reply_cache_free(b, rp);
return;
}
spin_lock(&b->cache_lock);
drc_mem_usage += bufsize;
lru_put_end(b, rp);
rp->c_secure = test_bit(RQ_SECURE, &rqstp->rq_flags);
rp->c_type = cachetype;
rp->c_state = RC_DONE;
spin_unlock(&b->cache_lock);
return;
}
/*
* Copy cached reply to current reply buffer. Should always fit.
* FIXME as reply is in a page, we should just attach the page, and
* keep a refcount....
*/
static int
nfsd_cache_append(struct svc_rqst *rqstp, struct kvec *data)
{
struct kvec *vec = &rqstp->rq_res.head[0];
if (vec->iov_len + data->iov_len > PAGE_SIZE) {
printk(KERN_WARNING "nfsd: cached reply too large (%Zd).\n",
data->iov_len);
return 0;
}
memcpy((char*)vec->iov_base + vec->iov_len, data->iov_base, data->iov_len);
vec->iov_len += data->iov_len;
return 1;
}
/*
* Note that fields may be added, removed or reordered in the future. Programs
* scraping this file for info should test the labels to ensure they're
* getting the correct field.
*/
static int nfsd_reply_cache_stats_show(struct seq_file *m, void *v)
{
seq_printf(m, "max entries: %u\n", max_drc_entries);
seq_printf(m, "num entries: %u\n",
atomic_read(&num_drc_entries));
seq_printf(m, "hash buckets: %u\n", 1 << maskbits);
seq_printf(m, "mem usage: %u\n", drc_mem_usage);
seq_printf(m, "cache hits: %u\n", nfsdstats.rchits);
seq_printf(m, "cache misses: %u\n", nfsdstats.rcmisses);
seq_printf(m, "not cached: %u\n", nfsdstats.rcnocache);
seq_printf(m, "payload misses: %u\n", payload_misses);
seq_printf(m, "longest chain len: %u\n", longest_chain);
seq_printf(m, "cachesize at longest: %u\n", longest_chain_cachesize);
return 0;
}
int nfsd_reply_cache_stats_open(struct inode *inode, struct file *file)
{
return single_open(file, nfsd_reply_cache_stats_show, NULL);
}
| gpl-2.0 |
DarkPoe/AK-OnePone | drivers/rtc/alarm-dev.c | 688 | 8334 | /* drivers/rtc/alarm-dev.c
*
* Copyright (C) 2007-2009 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/module.h>
#include <linux/android_alarm.h>
#include <linux/device.h>
#include <linux/miscdevice.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/wakelock.h>
#include <asm/mach/time.h>
#define ANDROID_ALARM_PRINT_INFO (1U << 0)
#define ANDROID_ALARM_PRINT_IO (1U << 1)
#define ANDROID_ALARM_PRINT_INT (1U << 2)
static int debug_mask = ANDROID_ALARM_PRINT_INFO;
module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
#define pr_alarm(debug_level_mask, args...) \
do { \
if (debug_mask & ANDROID_ALARM_PRINT_##debug_level_mask) { \
pr_info(args); \
} \
} while (0)
#define ANDROID_ALARM_WAKEUP_MASK ( \
ANDROID_ALARM_RTC_WAKEUP_MASK | \
ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
/* support old usespace code */
#define ANDROID_ALARM_SET_OLD _IOW('a', 2, time_t) /* set alarm */
#define ANDROID_ALARM_SET_AND_WAIT_OLD _IOW('a', 3, time_t)
static int alarm_opened;
static DEFINE_MUTEX(alarm_mutex);
static DEFINE_SPINLOCK(alarm_slock);
static struct wake_lock alarm_wake_lock;
static DECLARE_WAIT_QUEUE_HEAD(alarm_wait_queue);
static uint32_t alarm_pending;
static uint32_t alarm_enabled;
static uint32_t wait_pending;
static struct alarm alarms[ANDROID_ALARM_TYPE_COUNT];
static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int rv = 0;
unsigned long flags;
struct timespec new_alarm_time;
struct timespec new_rtc_time;
struct timespec tmp_time;
enum android_alarm_type alarm_type = ANDROID_ALARM_IOCTL_TO_TYPE(cmd);
uint32_t alarm_type_mask = 1U << alarm_type;
if (alarm_type >= ANDROID_ALARM_TYPE_COUNT)
return -EINVAL;
if (ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_GET_TIME(0)) {
if ((file->f_flags & O_ACCMODE) == O_RDONLY)
return -EPERM;
if (file->private_data == NULL &&
cmd != ANDROID_ALARM_SET_RTC) {
spin_lock_irqsave(&alarm_slock, flags);
if (alarm_opened) {
spin_unlock_irqrestore(&alarm_slock, flags);
return -EBUSY;
}
alarm_opened = 1;
file->private_data = (void *)1;
spin_unlock_irqrestore(&alarm_slock, flags);
}
}
switch (ANDROID_ALARM_BASE_CMD(cmd)) {
case ANDROID_ALARM_CLEAR(0):
mutex_lock(&alarm_mutex);
spin_lock_irqsave(&alarm_slock, flags);
pr_alarm(IO, "alarm %d clear\n", alarm_type);
alarm_try_to_cancel(&alarms[alarm_type]);
if (alarm_pending) {
alarm_pending &= ~alarm_type_mask;
if (!alarm_pending && !wait_pending)
wake_unlock(&alarm_wake_lock);
}
alarm_enabled &= ~alarm_type_mask;
spin_unlock_irqrestore(&alarm_slock, flags);
if (alarm_type == ANDROID_ALARM_RTC_POWEROFF_WAKEUP)
if (!copy_from_user(&new_alarm_time,
(void __user *)arg, sizeof(new_alarm_time)))
set_power_on_alarm(new_alarm_time.tv_sec, 0);
mutex_unlock(&alarm_mutex);
break;
case ANDROID_ALARM_SET_OLD:
case ANDROID_ALARM_SET_AND_WAIT_OLD:
if (get_user(new_alarm_time.tv_sec, (int __user *)arg)) {
rv = -EFAULT;
goto err1;
}
new_alarm_time.tv_nsec = 0;
goto from_old_alarm_set;
case ANDROID_ALARM_SET_AND_WAIT(0):
case ANDROID_ALARM_SET(0):
if (copy_from_user(&new_alarm_time, (void __user *)arg,
sizeof(new_alarm_time))) {
rv = -EFAULT;
goto err1;
}
from_old_alarm_set:
mutex_lock(&alarm_mutex);
spin_lock_irqsave(&alarm_slock, flags);
pr_alarm(IO, "alarm %d set %ld.%09ld\n", alarm_type,
new_alarm_time.tv_sec, new_alarm_time.tv_nsec);
alarm_enabled |= alarm_type_mask;
alarm_start_range(&alarms[alarm_type],
timespec_to_ktime(new_alarm_time),
timespec_to_ktime(new_alarm_time));
spin_unlock_irqrestore(&alarm_slock, flags);
if ((alarm_type == ANDROID_ALARM_RTC_POWEROFF_WAKEUP) &&
(ANDROID_ALARM_BASE_CMD(cmd) ==
ANDROID_ALARM_SET(0)))
set_power_on_alarm(new_alarm_time.tv_sec, 1);
mutex_unlock(&alarm_mutex);
if (ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_SET_AND_WAIT(0)
&& cmd != ANDROID_ALARM_SET_AND_WAIT_OLD)
break;
/* fall though */
case ANDROID_ALARM_WAIT:
spin_lock_irqsave(&alarm_slock, flags);
pr_alarm(IO, "alarm wait\n");
if (!alarm_pending && wait_pending) {
wake_unlock(&alarm_wake_lock);
wait_pending = 0;
}
spin_unlock_irqrestore(&alarm_slock, flags);
rv = wait_event_interruptible(alarm_wait_queue, alarm_pending);
if (rv)
goto err1;
spin_lock_irqsave(&alarm_slock, flags);
rv = alarm_pending;
wait_pending = 1;
alarm_pending = 0;
spin_unlock_irqrestore(&alarm_slock, flags);
break;
case ANDROID_ALARM_SET_RTC:
if (copy_from_user(&new_rtc_time, (void __user *)arg,
sizeof(new_rtc_time))) {
rv = -EFAULT;
goto err1;
}
rv = alarm_set_rtc(new_rtc_time);
spin_lock_irqsave(&alarm_slock, flags);
alarm_pending |= ANDROID_ALARM_TIME_CHANGE_MASK;
wake_up(&alarm_wait_queue);
spin_unlock_irqrestore(&alarm_slock, flags);
if (rv < 0)
goto err1;
break;
case ANDROID_ALARM_GET_TIME(0):
switch (alarm_type) {
case ANDROID_ALARM_RTC_WAKEUP:
case ANDROID_ALARM_RTC:
case ANDROID_ALARM_RTC_POWEROFF_WAKEUP:
getnstimeofday(&tmp_time);
break;
case ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP:
case ANDROID_ALARM_ELAPSED_REALTIME:
tmp_time =
ktime_to_timespec(alarm_get_elapsed_realtime());
break;
case ANDROID_ALARM_TYPE_COUNT:
case ANDROID_ALARM_SYSTEMTIME:
ktime_get_ts(&tmp_time);
break;
}
if (copy_to_user((void __user *)arg, &tmp_time,
sizeof(tmp_time))) {
rv = -EFAULT;
goto err1;
}
break;
default:
rv = -EINVAL;
goto err1;
}
err1:
return rv;
}
static int alarm_open(struct inode *inode, struct file *file)
{
file->private_data = NULL;
return 0;
}
static int alarm_release(struct inode *inode, struct file *file)
{
int i;
unsigned long flags;
spin_lock_irqsave(&alarm_slock, flags);
if (file->private_data != 0) {
for (i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++) {
uint32_t alarm_type_mask = 1U << i;
if (alarm_enabled & alarm_type_mask) {
pr_alarm(INFO, "alarm_release: clear alarm, "
"pending %d\n",
!!(alarm_pending & alarm_type_mask));
alarm_enabled &= ~alarm_type_mask;
}
spin_unlock_irqrestore(&alarm_slock, flags);
alarm_cancel(&alarms[i]);
spin_lock_irqsave(&alarm_slock, flags);
}
if (alarm_pending | wait_pending) {
if (alarm_pending)
pr_alarm(INFO, "alarm_release: clear "
"pending alarms %x\n", alarm_pending);
wake_unlock(&alarm_wake_lock);
wait_pending = 0;
alarm_pending = 0;
}
alarm_opened = 0;
}
spin_unlock_irqrestore(&alarm_slock, flags);
return 0;
}
static void alarm_triggered(struct alarm *alarm)
{
unsigned long flags;
uint32_t alarm_type_mask = 1U << alarm->type;
pr_alarm(INT, "alarm_triggered type %d\n", alarm->type);
spin_lock_irqsave(&alarm_slock, flags);
if (alarm_enabled & alarm_type_mask) {
wake_lock_timeout(&alarm_wake_lock, 5 * HZ);
alarm_enabled &= ~alarm_type_mask;
alarm_pending |= alarm_type_mask;
wake_up(&alarm_wait_queue);
}
spin_unlock_irqrestore(&alarm_slock, flags);
}
static const struct file_operations alarm_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = alarm_ioctl,
.open = alarm_open,
.release = alarm_release,
};
static struct miscdevice alarm_device = {
.minor = MISC_DYNAMIC_MINOR,
.name = "alarm",
.fops = &alarm_fops,
};
static int __init alarm_dev_init(void)
{
int err;
int i;
err = misc_register(&alarm_device);
if (err)
return err;
for (i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++)
alarm_init(&alarms[i], i, alarm_triggered);
wake_lock_init(&alarm_wake_lock, WAKE_LOCK_SUSPEND, "alarm");
return 0;
}
static void __exit alarm_dev_exit(void)
{
misc_deregister(&alarm_device);
wake_lock_destroy(&alarm_wake_lock);
}
module_init(alarm_dev_init);
module_exit(alarm_dev_exit);
| gpl-2.0 |
argakon/lge-kernel-msm7x27-ICS-JB | fs/ntfs/mft.c | 944 | 101846 | /**
* mft.c - NTFS kernel mft record operations. Part of the Linux-NTFS project.
*
* Copyright (c) 2001-2006 Anton Altaparmakov
* Copyright (c) 2002 Richard Russon
*
* This program/include file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published
* by the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program/include file is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program (in the main directory of the Linux-NTFS
* distribution in the file COPYING); if not, write to the Free Software
* Foundation,Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/buffer_head.h>
#include <linux/slab.h>
#include <linux/swap.h>
#include "attrib.h"
#include "aops.h"
#include "bitmap.h"
#include "debug.h"
#include "dir.h"
#include "lcnalloc.h"
#include "malloc.h"
#include "mft.h"
#include "ntfs.h"
/**
* map_mft_record_page - map the page in which a specific mft record resides
* @ni: ntfs inode whose mft record page to map
*
* This maps the page in which the mft record of the ntfs inode @ni is situated
* and returns a pointer to the mft record within the mapped page.
*
* Return value needs to be checked with IS_ERR() and if that is true PTR_ERR()
* contains the negative error code returned.
*/
static inline MFT_RECORD *map_mft_record_page(ntfs_inode *ni)
{
loff_t i_size;
ntfs_volume *vol = ni->vol;
struct inode *mft_vi = vol->mft_ino;
struct page *page;
unsigned long index, end_index;
unsigned ofs;
BUG_ON(ni->page);
/*
* The index into the page cache and the offset within the page cache
* page of the wanted mft record. FIXME: We need to check for
* overflowing the unsigned long, but I don't think we would ever get
* here if the volume was that big...
*/
index = (u64)ni->mft_no << vol->mft_record_size_bits >>
PAGE_CACHE_SHIFT;
ofs = (ni->mft_no << vol->mft_record_size_bits) & ~PAGE_CACHE_MASK;
i_size = i_size_read(mft_vi);
/* The maximum valid index into the page cache for $MFT's data. */
end_index = i_size >> PAGE_CACHE_SHIFT;
/* If the wanted index is out of bounds the mft record doesn't exist. */
if (unlikely(index >= end_index)) {
if (index > end_index || (i_size & ~PAGE_CACHE_MASK) < ofs +
vol->mft_record_size) {
page = ERR_PTR(-ENOENT);
ntfs_error(vol->sb, "Attemt to read mft record 0x%lx, "
"which is beyond the end of the mft. "
"This is probably a bug in the ntfs "
"driver.", ni->mft_no);
goto err_out;
}
}
/* Read, map, and pin the page. */
page = ntfs_map_page(mft_vi->i_mapping, index);
if (likely(!IS_ERR(page))) {
/* Catch multi sector transfer fixup errors. */
if (likely(ntfs_is_mft_recordp((le32*)(page_address(page) +
ofs)))) {
ni->page = page;
ni->page_ofs = ofs;
return page_address(page) + ofs;
}
ntfs_error(vol->sb, "Mft record 0x%lx is corrupt. "
"Run chkdsk.", ni->mft_no);
ntfs_unmap_page(page);
page = ERR_PTR(-EIO);
NVolSetErrors(vol);
}
err_out:
ni->page = NULL;
ni->page_ofs = 0;
return (void*)page;
}
/**
* map_mft_record - map, pin and lock an mft record
* @ni: ntfs inode whose MFT record to map
*
* First, take the mrec_lock mutex. We might now be sleeping, while waiting
* for the mutex if it was already locked by someone else.
*
* The page of the record is mapped using map_mft_record_page() before being
* returned to the caller.
*
* This in turn uses ntfs_map_page() to get the page containing the wanted mft
* record (it in turn calls read_cache_page() which reads it in from disk if
* necessary, increments the use count on the page so that it cannot disappear
* under us and returns a reference to the page cache page).
*
* If read_cache_page() invokes ntfs_readpage() to load the page from disk, it
* sets PG_locked and clears PG_uptodate on the page. Once I/O has completed
* and the post-read mst fixups on each mft record in the page have been
* performed, the page gets PG_uptodate set and PG_locked cleared (this is done
* in our asynchronous I/O completion handler end_buffer_read_mft_async()).
* ntfs_map_page() waits for PG_locked to become clear and checks if
* PG_uptodate is set and returns an error code if not. This provides
* sufficient protection against races when reading/using the page.
*
* However there is the write mapping to think about. Doing the above described
* checking here will be fine, because when initiating the write we will set
* PG_locked and clear PG_uptodate making sure nobody is touching the page
* contents. Doing the locking this way means that the commit to disk code in
* the page cache code paths is automatically sufficiently locked with us as
* we will not touch a page that has been locked or is not uptodate. The only
* locking problem then is them locking the page while we are accessing it.
*
* So that code will end up having to own the mrec_lock of all mft
* records/inodes present in the page before I/O can proceed. In that case we
* wouldn't need to bother with PG_locked and PG_uptodate as nobody will be
* accessing anything without owning the mrec_lock mutex. But we do need to
* use them because of the read_cache_page() invocation and the code becomes so
* much simpler this way that it is well worth it.
*
* The mft record is now ours and we return a pointer to it. You need to check
* the returned pointer with IS_ERR() and if that is true, PTR_ERR() will return
* the error code.
*
* NOTE: Caller is responsible for setting the mft record dirty before calling
* unmap_mft_record(). This is obviously only necessary if the caller really
* modified the mft record...
* Q: Do we want to recycle one of the VFS inode state bits instead?
* A: No, the inode ones mean we want to change the mft record, not we want to
* write it out.
*/
MFT_RECORD *map_mft_record(ntfs_inode *ni)
{
MFT_RECORD *m;
ntfs_debug("Entering for mft_no 0x%lx.", ni->mft_no);
/* Make sure the ntfs inode doesn't go away. */
atomic_inc(&ni->count);
/* Serialize access to this mft record. */
mutex_lock(&ni->mrec_lock);
m = map_mft_record_page(ni);
if (likely(!IS_ERR(m)))
return m;
mutex_unlock(&ni->mrec_lock);
atomic_dec(&ni->count);
ntfs_error(ni->vol->sb, "Failed with error code %lu.", -PTR_ERR(m));
return m;
}
/**
* unmap_mft_record_page - unmap the page in which a specific mft record resides
* @ni: ntfs inode whose mft record page to unmap
*
* This unmaps the page in which the mft record of the ntfs inode @ni is
* situated and returns. This is a NOOP if highmem is not configured.
*
* The unmap happens via ntfs_unmap_page() which in turn decrements the use
* count on the page thus releasing it from the pinned state.
*
* We do not actually unmap the page from memory of course, as that will be
* done by the page cache code itself when memory pressure increases or
* whatever.
*/
static inline void unmap_mft_record_page(ntfs_inode *ni)
{
BUG_ON(!ni->page);
// TODO: If dirty, blah...
ntfs_unmap_page(ni->page);
ni->page = NULL;
ni->page_ofs = 0;
return;
}
/**
* unmap_mft_record - release a mapped mft record
* @ni: ntfs inode whose MFT record to unmap
*
* We release the page mapping and the mrec_lock mutex which unmaps the mft
* record and releases it for others to get hold of. We also release the ntfs
* inode by decrementing the ntfs inode reference count.
*
* NOTE: If caller has modified the mft record, it is imperative to set the mft
* record dirty BEFORE calling unmap_mft_record().
*/
void unmap_mft_record(ntfs_inode *ni)
{
struct page *page = ni->page;
BUG_ON(!page);
ntfs_debug("Entering for mft_no 0x%lx.", ni->mft_no);
unmap_mft_record_page(ni);
mutex_unlock(&ni->mrec_lock);
atomic_dec(&ni->count);
/*
* If pure ntfs_inode, i.e. no vfs inode attached, we leave it to
* ntfs_clear_extent_inode() in the extent inode case, and to the
* caller in the non-extent, yet pure ntfs inode case, to do the actual
* tear down of all structures and freeing of all allocated memory.
*/
return;
}
/**
* map_extent_mft_record - load an extent inode and attach it to its base
* @base_ni: base ntfs inode
* @mref: mft reference of the extent inode to load
* @ntfs_ino: on successful return, pointer to the ntfs_inode structure
*
* Load the extent mft record @mref and attach it to its base inode @base_ni.
* Return the mapped extent mft record if IS_ERR(result) is false. Otherwise
* PTR_ERR(result) gives the negative error code.
*
* On successful return, @ntfs_ino contains a pointer to the ntfs_inode
* structure of the mapped extent inode.
*/
MFT_RECORD *map_extent_mft_record(ntfs_inode *base_ni, MFT_REF mref,
ntfs_inode **ntfs_ino)
{
MFT_RECORD *m;
ntfs_inode *ni = NULL;
ntfs_inode **extent_nis = NULL;
int i;
unsigned long mft_no = MREF(mref);
u16 seq_no = MSEQNO(mref);
bool destroy_ni = false;
ntfs_debug("Mapping extent mft record 0x%lx (base mft record 0x%lx).",
mft_no, base_ni->mft_no);
/* Make sure the base ntfs inode doesn't go away. */
atomic_inc(&base_ni->count);
/*
* Check if this extent inode has already been added to the base inode,
* in which case just return it. If not found, add it to the base
* inode before returning it.
*/
mutex_lock(&base_ni->extent_lock);
if (base_ni->nr_extents > 0) {
extent_nis = base_ni->ext.extent_ntfs_inos;
for (i = 0; i < base_ni->nr_extents; i++) {
if (mft_no != extent_nis[i]->mft_no)
continue;
ni = extent_nis[i];
/* Make sure the ntfs inode doesn't go away. */
atomic_inc(&ni->count);
break;
}
}
if (likely(ni != NULL)) {
mutex_unlock(&base_ni->extent_lock);
atomic_dec(&base_ni->count);
/* We found the record; just have to map and return it. */
m = map_mft_record(ni);
/* map_mft_record() has incremented this on success. */
atomic_dec(&ni->count);
if (likely(!IS_ERR(m))) {
/* Verify the sequence number. */
if (likely(le16_to_cpu(m->sequence_number) == seq_no)) {
ntfs_debug("Done 1.");
*ntfs_ino = ni;
return m;
}
unmap_mft_record(ni);
ntfs_error(base_ni->vol->sb, "Found stale extent mft "
"reference! Corrupt filesystem. "
"Run chkdsk.");
return ERR_PTR(-EIO);
}
map_err_out:
ntfs_error(base_ni->vol->sb, "Failed to map extent "
"mft record, error code %ld.", -PTR_ERR(m));
return m;
}
/* Record wasn't there. Get a new ntfs inode and initialize it. */
ni = ntfs_new_extent_inode(base_ni->vol->sb, mft_no);
if (unlikely(!ni)) {
mutex_unlock(&base_ni->extent_lock);
atomic_dec(&base_ni->count);
return ERR_PTR(-ENOMEM);
}
ni->vol = base_ni->vol;
ni->seq_no = seq_no;
ni->nr_extents = -1;
ni->ext.base_ntfs_ino = base_ni;
/* Now map the record. */
m = map_mft_record(ni);
if (IS_ERR(m)) {
mutex_unlock(&base_ni->extent_lock);
atomic_dec(&base_ni->count);
ntfs_clear_extent_inode(ni);
goto map_err_out;
}
/* Verify the sequence number if it is present. */
if (seq_no && (le16_to_cpu(m->sequence_number) != seq_no)) {
ntfs_error(base_ni->vol->sb, "Found stale extent mft "
"reference! Corrupt filesystem. Run chkdsk.");
destroy_ni = true;
m = ERR_PTR(-EIO);
goto unm_err_out;
}
/* Attach extent inode to base inode, reallocating memory if needed. */
if (!(base_ni->nr_extents & 3)) {
ntfs_inode **tmp;
int new_size = (base_ni->nr_extents + 4) * sizeof(ntfs_inode *);
tmp = kmalloc(new_size, GFP_NOFS);
if (unlikely(!tmp)) {
ntfs_error(base_ni->vol->sb, "Failed to allocate "
"internal buffer.");
destroy_ni = true;
m = ERR_PTR(-ENOMEM);
goto unm_err_out;
}
if (base_ni->nr_extents) {
BUG_ON(!base_ni->ext.extent_ntfs_inos);
memcpy(tmp, base_ni->ext.extent_ntfs_inos, new_size -
4 * sizeof(ntfs_inode *));
kfree(base_ni->ext.extent_ntfs_inos);
}
base_ni->ext.extent_ntfs_inos = tmp;
}
base_ni->ext.extent_ntfs_inos[base_ni->nr_extents++] = ni;
mutex_unlock(&base_ni->extent_lock);
atomic_dec(&base_ni->count);
ntfs_debug("Done 2.");
*ntfs_ino = ni;
return m;
unm_err_out:
unmap_mft_record(ni);
mutex_unlock(&base_ni->extent_lock);
atomic_dec(&base_ni->count);
/*
* If the extent inode was not attached to the base inode we need to
* release it or we will leak memory.
*/
if (destroy_ni)
ntfs_clear_extent_inode(ni);
return m;
}
#ifdef NTFS_RW
/**
* __mark_mft_record_dirty - set the mft record and the page containing it dirty
* @ni: ntfs inode describing the mapped mft record
*
* Internal function. Users should call mark_mft_record_dirty() instead.
*
* Set the mapped (extent) mft record of the (base or extent) ntfs inode @ni,
* as well as the page containing the mft record, dirty. Also, mark the base
* vfs inode dirty. This ensures that any changes to the mft record are
* written out to disk.
*
* NOTE: We only set I_DIRTY_SYNC and I_DIRTY_DATASYNC (and not I_DIRTY_PAGES)
* on the base vfs inode, because even though file data may have been modified,
* it is dirty in the inode meta data rather than the data page cache of the
* inode, and thus there are no data pages that need writing out. Therefore, a
* full mark_inode_dirty() is overkill. A mark_inode_dirty_sync(), on the
* other hand, is not sufficient, because ->write_inode needs to be called even
* in case of fdatasync. This needs to happen or the file data would not
* necessarily hit the device synchronously, even though the vfs inode has the
* O_SYNC flag set. Also, I_DIRTY_DATASYNC simply "feels" better than just
* I_DIRTY_SYNC, since the file data has not actually hit the block device yet,
* which is not what I_DIRTY_SYNC on its own would suggest.
*/
void __mark_mft_record_dirty(ntfs_inode *ni)
{
ntfs_inode *base_ni;
ntfs_debug("Entering for inode 0x%lx.", ni->mft_no);
BUG_ON(NInoAttr(ni));
mark_ntfs_record_dirty(ni->page, ni->page_ofs);
/* Determine the base vfs inode and mark it dirty, too. */
mutex_lock(&ni->extent_lock);
if (likely(ni->nr_extents >= 0))
base_ni = ni;
else
base_ni = ni->ext.base_ntfs_ino;
mutex_unlock(&ni->extent_lock);
__mark_inode_dirty(VFS_I(base_ni), I_DIRTY_SYNC | I_DIRTY_DATASYNC);
}
static const char *ntfs_please_email = "Please email "
"linux-ntfs-dev@lists.sourceforge.net and say that you saw "
"this message. Thank you.";
/**
* ntfs_sync_mft_mirror_umount - synchronise an mft record to the mft mirror
* @vol: ntfs volume on which the mft record to synchronize resides
* @mft_no: mft record number of mft record to synchronize
* @m: mapped, mst protected (extent) mft record to synchronize
*
* Write the mapped, mst protected (extent) mft record @m with mft record
* number @mft_no to the mft mirror ($MFTMirr) of the ntfs volume @vol,
* bypassing the page cache and the $MFTMirr inode itself.
*
* This function is only for use at umount time when the mft mirror inode has
* already been disposed off. We BUG() if we are called while the mft mirror
* inode is still attached to the volume.
*
* On success return 0. On error return -errno.
*
* NOTE: This function is not implemented yet as I am not convinced it can
* actually be triggered considering the sequence of commits we do in super.c::
* ntfs_put_super(). But just in case we provide this place holder as the
* alternative would be either to BUG() or to get a NULL pointer dereference
* and Oops.
*/
static int ntfs_sync_mft_mirror_umount(ntfs_volume *vol,
const unsigned long mft_no, MFT_RECORD *m)
{
BUG_ON(vol->mftmirr_ino);
ntfs_error(vol->sb, "Umount time mft mirror syncing is not "
"implemented yet. %s", ntfs_please_email);
return -EOPNOTSUPP;
}
/**
* ntfs_sync_mft_mirror - synchronize an mft record to the mft mirror
* @vol: ntfs volume on which the mft record to synchronize resides
* @mft_no: mft record number of mft record to synchronize
* @m: mapped, mst protected (extent) mft record to synchronize
* @sync: if true, wait for i/o completion
*
* Write the mapped, mst protected (extent) mft record @m with mft record
* number @mft_no to the mft mirror ($MFTMirr) of the ntfs volume @vol.
*
* On success return 0. On error return -errno and set the volume errors flag
* in the ntfs volume @vol.
*
* NOTE: We always perform synchronous i/o and ignore the @sync parameter.
*
* TODO: If @sync is false, want to do truly asynchronous i/o, i.e. just
* schedule i/o via ->writepage or do it via kntfsd or whatever.
*/
int ntfs_sync_mft_mirror(ntfs_volume *vol, const unsigned long mft_no,
MFT_RECORD *m, int sync)
{
struct page *page;
unsigned int blocksize = vol->sb->s_blocksize;
int max_bhs = vol->mft_record_size / blocksize;
struct buffer_head *bhs[max_bhs];
struct buffer_head *bh, *head;
u8 *kmirr;
runlist_element *rl;
unsigned int block_start, block_end, m_start, m_end, page_ofs;
int i_bhs, nr_bhs, err = 0;
unsigned char blocksize_bits = vol->sb->s_blocksize_bits;
ntfs_debug("Entering for inode 0x%lx.", mft_no);
BUG_ON(!max_bhs);
if (unlikely(!vol->mftmirr_ino)) {
/* This could happen during umount... */
err = ntfs_sync_mft_mirror_umount(vol, mft_no, m);
if (likely(!err))
return err;
goto err_out;
}
/* Get the page containing the mirror copy of the mft record @m. */
page = ntfs_map_page(vol->mftmirr_ino->i_mapping, mft_no >>
(PAGE_CACHE_SHIFT - vol->mft_record_size_bits));
if (IS_ERR(page)) {
ntfs_error(vol->sb, "Failed to map mft mirror page.");
err = PTR_ERR(page);
goto err_out;
}
lock_page(page);
BUG_ON(!PageUptodate(page));
ClearPageUptodate(page);
/* Offset of the mft mirror record inside the page. */
page_ofs = (mft_no << vol->mft_record_size_bits) & ~PAGE_CACHE_MASK;
/* The address in the page of the mirror copy of the mft record @m. */
kmirr = page_address(page) + page_ofs;
/* Copy the mst protected mft record to the mirror. */
memcpy(kmirr, m, vol->mft_record_size);
/* Create uptodate buffers if not present. */
if (unlikely(!page_has_buffers(page))) {
struct buffer_head *tail;
bh = head = alloc_page_buffers(page, blocksize, 1);
do {
set_buffer_uptodate(bh);
tail = bh;
bh = bh->b_this_page;
} while (bh);
tail->b_this_page = head;
attach_page_buffers(page, head);
}
bh = head = page_buffers(page);
BUG_ON(!bh);
rl = NULL;
nr_bhs = 0;
block_start = 0;
m_start = kmirr - (u8*)page_address(page);
m_end = m_start + vol->mft_record_size;
do {
block_end = block_start + blocksize;
/* If the buffer is outside the mft record, skip it. */
if (block_end <= m_start)
continue;
if (unlikely(block_start >= m_end))
break;
/* Need to map the buffer if it is not mapped already. */
if (unlikely(!buffer_mapped(bh))) {
VCN vcn;
LCN lcn;
unsigned int vcn_ofs;
bh->b_bdev = vol->sb->s_bdev;
/* Obtain the vcn and offset of the current block. */
vcn = ((VCN)mft_no << vol->mft_record_size_bits) +
(block_start - m_start);
vcn_ofs = vcn & vol->cluster_size_mask;
vcn >>= vol->cluster_size_bits;
if (!rl) {
down_read(&NTFS_I(vol->mftmirr_ino)->
runlist.lock);
rl = NTFS_I(vol->mftmirr_ino)->runlist.rl;
/*
* $MFTMirr always has the whole of its runlist
* in memory.
*/
BUG_ON(!rl);
}
/* Seek to element containing target vcn. */
while (rl->length && rl[1].vcn <= vcn)
rl++;
lcn = ntfs_rl_vcn_to_lcn(rl, vcn);
/* For $MFTMirr, only lcn >= 0 is a successful remap. */
if (likely(lcn >= 0)) {
/* Setup buffer head to correct block. */
bh->b_blocknr = ((lcn <<
vol->cluster_size_bits) +
vcn_ofs) >> blocksize_bits;
set_buffer_mapped(bh);
} else {
bh->b_blocknr = -1;
ntfs_error(vol->sb, "Cannot write mft mirror "
"record 0x%lx because its "
"location on disk could not "
"be determined (error code "
"%lli).", mft_no,
(long long)lcn);
err = -EIO;
}
}
BUG_ON(!buffer_uptodate(bh));
BUG_ON(!nr_bhs && (m_start != block_start));
BUG_ON(nr_bhs >= max_bhs);
bhs[nr_bhs++] = bh;
BUG_ON((nr_bhs >= max_bhs) && (m_end != block_end));
} while (block_start = block_end, (bh = bh->b_this_page) != head);
if (unlikely(rl))
up_read(&NTFS_I(vol->mftmirr_ino)->runlist.lock);
if (likely(!err)) {
/* Lock buffers and start synchronous write i/o on them. */
for (i_bhs = 0; i_bhs < nr_bhs; i_bhs++) {
struct buffer_head *tbh = bhs[i_bhs];
if (!trylock_buffer(tbh))
BUG();
BUG_ON(!buffer_uptodate(tbh));
clear_buffer_dirty(tbh);
get_bh(tbh);
tbh->b_end_io = end_buffer_write_sync;
submit_bh(WRITE, tbh);
}
/* Wait on i/o completion of buffers. */
for (i_bhs = 0; i_bhs < nr_bhs; i_bhs++) {
struct buffer_head *tbh = bhs[i_bhs];
wait_on_buffer(tbh);
if (unlikely(!buffer_uptodate(tbh))) {
err = -EIO;
/*
* Set the buffer uptodate so the page and
* buffer states do not become out of sync.
*/
set_buffer_uptodate(tbh);
}
}
} else /* if (unlikely(err)) */ {
/* Clean the buffers. */
for (i_bhs = 0; i_bhs < nr_bhs; i_bhs++)
clear_buffer_dirty(bhs[i_bhs]);
}
/* Current state: all buffers are clean, unlocked, and uptodate. */
/* Remove the mst protection fixups again. */
post_write_mst_fixup((NTFS_RECORD*)kmirr);
flush_dcache_page(page);
SetPageUptodate(page);
unlock_page(page);
ntfs_unmap_page(page);
if (likely(!err)) {
ntfs_debug("Done.");
} else {
ntfs_error(vol->sb, "I/O error while writing mft mirror "
"record 0x%lx!", mft_no);
err_out:
ntfs_error(vol->sb, "Failed to synchronize $MFTMirr (error "
"code %i). Volume will be left marked dirty "
"on umount. Run ntfsfix on the partition "
"after umounting to correct this.", -err);
NVolSetErrors(vol);
}
return err;
}
/**
* write_mft_record_nolock - write out a mapped (extent) mft record
* @ni: ntfs inode describing the mapped (extent) mft record
* @m: mapped (extent) mft record to write
* @sync: if true, wait for i/o completion
*
* Write the mapped (extent) mft record @m described by the (regular or extent)
* ntfs inode @ni to backing store. If the mft record @m has a counterpart in
* the mft mirror, that is also updated.
*
* We only write the mft record if the ntfs inode @ni is dirty and the first
* buffer belonging to its mft record is dirty, too. We ignore the dirty state
* of subsequent buffers because we could have raced with
* fs/ntfs/aops.c::mark_ntfs_record_dirty().
*
* On success, clean the mft record and return 0. On error, leave the mft
* record dirty and return -errno.
*
* NOTE: We always perform synchronous i/o and ignore the @sync parameter.
* However, if the mft record has a counterpart in the mft mirror and @sync is
* true, we write the mft record, wait for i/o completion, and only then write
* the mft mirror copy. This ensures that if the system crashes either the mft
* or the mft mirror will contain a self-consistent mft record @m. If @sync is
* false on the other hand, we start i/o on both and then wait for completion
* on them. This provides a speedup but no longer guarantees that you will end
* up with a self-consistent mft record in the case of a crash but if you asked
* for asynchronous writing you probably do not care about that anyway.
*
* TODO: If @sync is false, want to do truly asynchronous i/o, i.e. just
* schedule i/o via ->writepage or do it via kntfsd or whatever.
*/
int write_mft_record_nolock(ntfs_inode *ni, MFT_RECORD *m, int sync)
{
ntfs_volume *vol = ni->vol;
struct page *page = ni->page;
unsigned int blocksize = vol->sb->s_blocksize;
unsigned char blocksize_bits = vol->sb->s_blocksize_bits;
int max_bhs = vol->mft_record_size / blocksize;
struct buffer_head *bhs[max_bhs];
struct buffer_head *bh, *head;
runlist_element *rl;
unsigned int block_start, block_end, m_start, m_end;
int i_bhs, nr_bhs, err = 0;
ntfs_debug("Entering for inode 0x%lx.", ni->mft_no);
BUG_ON(NInoAttr(ni));
BUG_ON(!max_bhs);
BUG_ON(!PageLocked(page));
/*
* If the ntfs_inode is clean no need to do anything. If it is dirty,
* mark it as clean now so that it can be redirtied later on if needed.
* There is no danger of races since the caller is holding the locks
* for the mft record @m and the page it is in.
*/
if (!NInoTestClearDirty(ni))
goto done;
bh = head = page_buffers(page);
BUG_ON(!bh);
rl = NULL;
nr_bhs = 0;
block_start = 0;
m_start = ni->page_ofs;
m_end = m_start + vol->mft_record_size;
do {
block_end = block_start + blocksize;
/* If the buffer is outside the mft record, skip it. */
if (block_end <= m_start)
continue;
if (unlikely(block_start >= m_end))
break;
/*
* If this block is not the first one in the record, we ignore
* the buffer's dirty state because we could have raced with a
* parallel mark_ntfs_record_dirty().
*/
if (block_start == m_start) {
/* This block is the first one in the record. */
if (!buffer_dirty(bh)) {
BUG_ON(nr_bhs);
/* Clean records are not written out. */
break;
}
}
/* Need to map the buffer if it is not mapped already. */
if (unlikely(!buffer_mapped(bh))) {
VCN vcn;
LCN lcn;
unsigned int vcn_ofs;
bh->b_bdev = vol->sb->s_bdev;
/* Obtain the vcn and offset of the current block. */
vcn = ((VCN)ni->mft_no << vol->mft_record_size_bits) +
(block_start - m_start);
vcn_ofs = vcn & vol->cluster_size_mask;
vcn >>= vol->cluster_size_bits;
if (!rl) {
down_read(&NTFS_I(vol->mft_ino)->runlist.lock);
rl = NTFS_I(vol->mft_ino)->runlist.rl;
BUG_ON(!rl);
}
/* Seek to element containing target vcn. */
while (rl->length && rl[1].vcn <= vcn)
rl++;
lcn = ntfs_rl_vcn_to_lcn(rl, vcn);
/* For $MFT, only lcn >= 0 is a successful remap. */
if (likely(lcn >= 0)) {
/* Setup buffer head to correct block. */
bh->b_blocknr = ((lcn <<
vol->cluster_size_bits) +
vcn_ofs) >> blocksize_bits;
set_buffer_mapped(bh);
} else {
bh->b_blocknr = -1;
ntfs_error(vol->sb, "Cannot write mft record "
"0x%lx because its location "
"on disk could not be "
"determined (error code %lli).",
ni->mft_no, (long long)lcn);
err = -EIO;
}
}
BUG_ON(!buffer_uptodate(bh));
BUG_ON(!nr_bhs && (m_start != block_start));
BUG_ON(nr_bhs >= max_bhs);
bhs[nr_bhs++] = bh;
BUG_ON((nr_bhs >= max_bhs) && (m_end != block_end));
} while (block_start = block_end, (bh = bh->b_this_page) != head);
if (unlikely(rl))
up_read(&NTFS_I(vol->mft_ino)->runlist.lock);
if (!nr_bhs)
goto done;
if (unlikely(err))
goto cleanup_out;
/* Apply the mst protection fixups. */
err = pre_write_mst_fixup((NTFS_RECORD*)m, vol->mft_record_size);
if (err) {
ntfs_error(vol->sb, "Failed to apply mst fixups!");
goto cleanup_out;
}
flush_dcache_mft_record_page(ni);
/* Lock buffers and start synchronous write i/o on them. */
for (i_bhs = 0; i_bhs < nr_bhs; i_bhs++) {
struct buffer_head *tbh = bhs[i_bhs];
if (!trylock_buffer(tbh))
BUG();
BUG_ON(!buffer_uptodate(tbh));
clear_buffer_dirty(tbh);
get_bh(tbh);
tbh->b_end_io = end_buffer_write_sync;
submit_bh(WRITE, tbh);
}
/* Synchronize the mft mirror now if not @sync. */
if (!sync && ni->mft_no < vol->mftmirr_size)
ntfs_sync_mft_mirror(vol, ni->mft_no, m, sync);
/* Wait on i/o completion of buffers. */
for (i_bhs = 0; i_bhs < nr_bhs; i_bhs++) {
struct buffer_head *tbh = bhs[i_bhs];
wait_on_buffer(tbh);
if (unlikely(!buffer_uptodate(tbh))) {
err = -EIO;
/*
* Set the buffer uptodate so the page and buffer
* states do not become out of sync.
*/
if (PageUptodate(page))
set_buffer_uptodate(tbh);
}
}
/* If @sync, now synchronize the mft mirror. */
if (sync && ni->mft_no < vol->mftmirr_size)
ntfs_sync_mft_mirror(vol, ni->mft_no, m, sync);
/* Remove the mst protection fixups again. */
post_write_mst_fixup((NTFS_RECORD*)m);
flush_dcache_mft_record_page(ni);
if (unlikely(err)) {
/* I/O error during writing. This is really bad! */
ntfs_error(vol->sb, "I/O error while writing mft record "
"0x%lx! Marking base inode as bad. You "
"should unmount the volume and run chkdsk.",
ni->mft_no);
goto err_out;
}
done:
ntfs_debug("Done.");
return 0;
cleanup_out:
/* Clean the buffers. */
for (i_bhs = 0; i_bhs < nr_bhs; i_bhs++)
clear_buffer_dirty(bhs[i_bhs]);
err_out:
/*
* Current state: all buffers are clean, unlocked, and uptodate.
* The caller should mark the base inode as bad so that no more i/o
* happens. ->clear_inode() will still be invoked so all extent inodes
* and other allocated memory will be freed.
*/
if (err == -ENOMEM) {
ntfs_error(vol->sb, "Not enough memory to write mft record. "
"Redirtying so the write is retried later.");
mark_mft_record_dirty(ni);
err = 0;
} else
NVolSetErrors(vol);
return err;
}
/**
* ntfs_may_write_mft_record - check if an mft record may be written out
* @vol: [IN] ntfs volume on which the mft record to check resides
* @mft_no: [IN] mft record number of the mft record to check
* @m: [IN] mapped mft record to check
* @locked_ni: [OUT] caller has to unlock this ntfs inode if one is returned
*
* Check if the mapped (base or extent) mft record @m with mft record number
* @mft_no belonging to the ntfs volume @vol may be written out. If necessary
* and possible the ntfs inode of the mft record is locked and the base vfs
* inode is pinned. The locked ntfs inode is then returned in @locked_ni. The
* caller is responsible for unlocking the ntfs inode and unpinning the base
* vfs inode.
*
* Return 'true' if the mft record may be written out and 'false' if not.
*
* The caller has locked the page and cleared the uptodate flag on it which
* means that we can safely write out any dirty mft records that do not have
* their inodes in icache as determined by ilookup5() as anyone
* opening/creating such an inode would block when attempting to map the mft
* record in read_cache_page() until we are finished with the write out.
*
* Here is a description of the tests we perform:
*
* If the inode is found in icache we know the mft record must be a base mft
* record. If it is dirty, we do not write it and return 'false' as the vfs
* inode write paths will result in the access times being updated which would
* cause the base mft record to be redirtied and written out again. (We know
* the access time update will modify the base mft record because Windows
* chkdsk complains if the standard information attribute is not in the base
* mft record.)
*
* If the inode is in icache and not dirty, we attempt to lock the mft record
* and if we find the lock was already taken, it is not safe to write the mft
* record and we return 'false'.
*
* If we manage to obtain the lock we have exclusive access to the mft record,
* which also allows us safe writeout of the mft record. We then set
* @locked_ni to the locked ntfs inode and return 'true'.
*
* Note we cannot just lock the mft record and sleep while waiting for the lock
* because this would deadlock due to lock reversal (normally the mft record is
* locked before the page is locked but we already have the page locked here
* when we try to lock the mft record).
*
* If the inode is not in icache we need to perform further checks.
*
* If the mft record is not a FILE record or it is a base mft record, we can
* safely write it and return 'true'.
*
* We now know the mft record is an extent mft record. We check if the inode
* corresponding to its base mft record is in icache and obtain a reference to
* it if it is. If it is not, we can safely write it and return 'true'.
*
* We now have the base inode for the extent mft record. We check if it has an
* ntfs inode for the extent mft record attached and if not it is safe to write
* the extent mft record and we return 'true'.
*
* The ntfs inode for the extent mft record is attached to the base inode so we
* attempt to lock the extent mft record and if we find the lock was already
* taken, it is not safe to write the extent mft record and we return 'false'.
*
* If we manage to obtain the lock we have exclusive access to the extent mft
* record, which also allows us safe writeout of the extent mft record. We
* set the ntfs inode of the extent mft record clean and then set @locked_ni to
* the now locked ntfs inode and return 'true'.
*
* Note, the reason for actually writing dirty mft records here and not just
* relying on the vfs inode dirty code paths is that we can have mft records
* modified without them ever having actual inodes in memory. Also we can have
* dirty mft records with clean ntfs inodes in memory. None of the described
* cases would result in the dirty mft records being written out if we only
* relied on the vfs inode dirty code paths. And these cases can really occur
* during allocation of new mft records and in particular when the
* initialized_size of the $MFT/$DATA attribute is extended and the new space
* is initialized using ntfs_mft_record_format(). The clean inode can then
* appear if the mft record is reused for a new inode before it got written
* out.
*/
bool ntfs_may_write_mft_record(ntfs_volume *vol, const unsigned long mft_no,
const MFT_RECORD *m, ntfs_inode **locked_ni)
{
struct super_block *sb = vol->sb;
struct inode *mft_vi = vol->mft_ino;
struct inode *vi;
ntfs_inode *ni, *eni, **extent_nis;
int i;
ntfs_attr na;
ntfs_debug("Entering for inode 0x%lx.", mft_no);
/*
* Normally we do not return a locked inode so set @locked_ni to NULL.
*/
BUG_ON(!locked_ni);
*locked_ni = NULL;
/*
* Check if the inode corresponding to this mft record is in the VFS
* inode cache and obtain a reference to it if it is.
*/
ntfs_debug("Looking for inode 0x%lx in icache.", mft_no);
na.mft_no = mft_no;
na.name = NULL;
na.name_len = 0;
na.type = AT_UNUSED;
/*
* Optimize inode 0, i.e. $MFT itself, since we have it in memory and
* we get here for it rather often.
*/
if (!mft_no) {
/* Balance the below iput(). */
vi = igrab(mft_vi);
BUG_ON(vi != mft_vi);
} else {
/*
* Have to use ilookup5_nowait() since ilookup5() waits for the
* inode lock which causes ntfs to deadlock when a concurrent
* inode write via the inode dirty code paths and the page
* dirty code path of the inode dirty code path when writing
* $MFT occurs.
*/
vi = ilookup5_nowait(sb, mft_no, (test_t)ntfs_test_inode, &na);
}
if (vi) {
ntfs_debug("Base inode 0x%lx is in icache.", mft_no);
/* The inode is in icache. */
ni = NTFS_I(vi);
/* Take a reference to the ntfs inode. */
atomic_inc(&ni->count);
/* If the inode is dirty, do not write this record. */
if (NInoDirty(ni)) {
ntfs_debug("Inode 0x%lx is dirty, do not write it.",
mft_no);
atomic_dec(&ni->count);
iput(vi);
return false;
}
ntfs_debug("Inode 0x%lx is not dirty.", mft_no);
/* The inode is not dirty, try to take the mft record lock. */
if (unlikely(!mutex_trylock(&ni->mrec_lock))) {
ntfs_debug("Mft record 0x%lx is already locked, do "
"not write it.", mft_no);
atomic_dec(&ni->count);
iput(vi);
return false;
}
ntfs_debug("Managed to lock mft record 0x%lx, write it.",
mft_no);
/*
* The write has to occur while we hold the mft record lock so
* return the locked ntfs inode.
*/
*locked_ni = ni;
return true;
}
ntfs_debug("Inode 0x%lx is not in icache.", mft_no);
/* The inode is not in icache. */
/* Write the record if it is not a mft record (type "FILE"). */
if (!ntfs_is_mft_record(m->magic)) {
ntfs_debug("Mft record 0x%lx is not a FILE record, write it.",
mft_no);
return true;
}
/* Write the mft record if it is a base inode. */
if (!m->base_mft_record) {
ntfs_debug("Mft record 0x%lx is a base record, write it.",
mft_no);
return true;
}
/*
* This is an extent mft record. Check if the inode corresponding to
* its base mft record is in icache and obtain a reference to it if it
* is.
*/
na.mft_no = MREF_LE(m->base_mft_record);
ntfs_debug("Mft record 0x%lx is an extent record. Looking for base "
"inode 0x%lx in icache.", mft_no, na.mft_no);
if (!na.mft_no) {
/* Balance the below iput(). */
vi = igrab(mft_vi);
BUG_ON(vi != mft_vi);
} else
vi = ilookup5_nowait(sb, na.mft_no, (test_t)ntfs_test_inode,
&na);
if (!vi) {
/*
* The base inode is not in icache, write this extent mft
* record.
*/
ntfs_debug("Base inode 0x%lx is not in icache, write the "
"extent record.", na.mft_no);
return true;
}
ntfs_debug("Base inode 0x%lx is in icache.", na.mft_no);
/*
* The base inode is in icache. Check if it has the extent inode
* corresponding to this extent mft record attached.
*/
ni = NTFS_I(vi);
mutex_lock(&ni->extent_lock);
if (ni->nr_extents <= 0) {
/*
* The base inode has no attached extent inodes, write this
* extent mft record.
*/
mutex_unlock(&ni->extent_lock);
iput(vi);
ntfs_debug("Base inode 0x%lx has no attached extent inodes, "
"write the extent record.", na.mft_no);
return true;
}
/* Iterate over the attached extent inodes. */
extent_nis = ni->ext.extent_ntfs_inos;
for (eni = NULL, i = 0; i < ni->nr_extents; ++i) {
if (mft_no == extent_nis[i]->mft_no) {
/*
* Found the extent inode corresponding to this extent
* mft record.
*/
eni = extent_nis[i];
break;
}
}
/*
* If the extent inode was not attached to the base inode, write this
* extent mft record.
*/
if (!eni) {
mutex_unlock(&ni->extent_lock);
iput(vi);
ntfs_debug("Extent inode 0x%lx is not attached to its base "
"inode 0x%lx, write the extent record.",
mft_no, na.mft_no);
return true;
}
ntfs_debug("Extent inode 0x%lx is attached to its base inode 0x%lx.",
mft_no, na.mft_no);
/* Take a reference to the extent ntfs inode. */
atomic_inc(&eni->count);
mutex_unlock(&ni->extent_lock);
/*
* Found the extent inode coresponding to this extent mft record.
* Try to take the mft record lock.
*/
if (unlikely(!mutex_trylock(&eni->mrec_lock))) {
atomic_dec(&eni->count);
iput(vi);
ntfs_debug("Extent mft record 0x%lx is already locked, do "
"not write it.", mft_no);
return false;
}
ntfs_debug("Managed to lock extent mft record 0x%lx, write it.",
mft_no);
if (NInoTestClearDirty(eni))
ntfs_debug("Extent inode 0x%lx is dirty, marking it clean.",
mft_no);
/*
* The write has to occur while we hold the mft record lock so return
* the locked extent ntfs inode.
*/
*locked_ni = eni;
return true;
}
static const char *es = " Leaving inconsistent metadata. Unmount and run "
"chkdsk.";
/**
* ntfs_mft_bitmap_find_and_alloc_free_rec_nolock - see name
* @vol: volume on which to search for a free mft record
* @base_ni: open base inode if allocating an extent mft record or NULL
*
* Search for a free mft record in the mft bitmap attribute on the ntfs volume
* @vol.
*
* If @base_ni is NULL start the search at the default allocator position.
*
* If @base_ni is not NULL start the search at the mft record after the base
* mft record @base_ni.
*
* Return the free mft record on success and -errno on error. An error code of
* -ENOSPC means that there are no free mft records in the currently
* initialized mft bitmap.
*
* Locking: Caller must hold vol->mftbmp_lock for writing.
*/
static int ntfs_mft_bitmap_find_and_alloc_free_rec_nolock(ntfs_volume *vol,
ntfs_inode *base_ni)
{
s64 pass_end, ll, data_pos, pass_start, ofs, bit;
unsigned long flags;
struct address_space *mftbmp_mapping;
u8 *buf, *byte;
struct page *page;
unsigned int page_ofs, size;
u8 pass, b;
ntfs_debug("Searching for free mft record in the currently "
"initialized mft bitmap.");
mftbmp_mapping = vol->mftbmp_ino->i_mapping;
/*
* Set the end of the pass making sure we do not overflow the mft
* bitmap.
*/
read_lock_irqsave(&NTFS_I(vol->mft_ino)->size_lock, flags);
pass_end = NTFS_I(vol->mft_ino)->allocated_size >>
vol->mft_record_size_bits;
read_unlock_irqrestore(&NTFS_I(vol->mft_ino)->size_lock, flags);
read_lock_irqsave(&NTFS_I(vol->mftbmp_ino)->size_lock, flags);
ll = NTFS_I(vol->mftbmp_ino)->initialized_size << 3;
read_unlock_irqrestore(&NTFS_I(vol->mftbmp_ino)->size_lock, flags);
if (pass_end > ll)
pass_end = ll;
pass = 1;
if (!base_ni)
data_pos = vol->mft_data_pos;
else
data_pos = base_ni->mft_no + 1;
if (data_pos < 24)
data_pos = 24;
if (data_pos >= pass_end) {
data_pos = 24;
pass = 2;
/* This happens on a freshly formatted volume. */
if (data_pos >= pass_end)
return -ENOSPC;
}
pass_start = data_pos;
ntfs_debug("Starting bitmap search: pass %u, pass_start 0x%llx, "
"pass_end 0x%llx, data_pos 0x%llx.", pass,
(long long)pass_start, (long long)pass_end,
(long long)data_pos);
/* Loop until a free mft record is found. */
for (; pass <= 2;) {
/* Cap size to pass_end. */
ofs = data_pos >> 3;
page_ofs = ofs & ~PAGE_CACHE_MASK;
size = PAGE_CACHE_SIZE - page_ofs;
ll = ((pass_end + 7) >> 3) - ofs;
if (size > ll)
size = ll;
size <<= 3;
/*
* If we are still within the active pass, search the next page
* for a zero bit.
*/
if (size) {
page = ntfs_map_page(mftbmp_mapping,
ofs >> PAGE_CACHE_SHIFT);
if (IS_ERR(page)) {
ntfs_error(vol->sb, "Failed to read mft "
"bitmap, aborting.");
return PTR_ERR(page);
}
buf = (u8*)page_address(page) + page_ofs;
bit = data_pos & 7;
data_pos &= ~7ull;
ntfs_debug("Before inner for loop: size 0x%x, "
"data_pos 0x%llx, bit 0x%llx", size,
(long long)data_pos, (long long)bit);
for (; bit < size && data_pos + bit < pass_end;
bit &= ~7ull, bit += 8) {
byte = buf + (bit >> 3);
if (*byte == 0xff)
continue;
b = ffz((unsigned long)*byte);
if (b < 8 && b >= (bit & 7)) {
ll = data_pos + (bit & ~7ull) + b;
if (unlikely(ll > (1ll << 32))) {
ntfs_unmap_page(page);
return -ENOSPC;
}
*byte |= 1 << b;
flush_dcache_page(page);
set_page_dirty(page);
ntfs_unmap_page(page);
ntfs_debug("Done. (Found and "
"allocated mft record "
"0x%llx.)",
(long long)ll);
return ll;
}
}
ntfs_debug("After inner for loop: size 0x%x, "
"data_pos 0x%llx, bit 0x%llx", size,
(long long)data_pos, (long long)bit);
data_pos += size;
ntfs_unmap_page(page);
/*
* If the end of the pass has not been reached yet,
* continue searching the mft bitmap for a zero bit.
*/
if (data_pos < pass_end)
continue;
}
/* Do the next pass. */
if (++pass == 2) {
/*
* Starting the second pass, in which we scan the first
* part of the zone which we omitted earlier.
*/
pass_end = pass_start;
data_pos = pass_start = 24;
ntfs_debug("pass %i, pass_start 0x%llx, pass_end "
"0x%llx.", pass, (long long)pass_start,
(long long)pass_end);
if (data_pos >= pass_end)
break;
}
}
/* No free mft records in currently initialized mft bitmap. */
ntfs_debug("Done. (No free mft records left in currently initialized "
"mft bitmap.)");
return -ENOSPC;
}
/**
* ntfs_mft_bitmap_extend_allocation_nolock - extend mft bitmap by a cluster
* @vol: volume on which to extend the mft bitmap attribute
*
* Extend the mft bitmap attribute on the ntfs volume @vol by one cluster.
*
* Note: Only changes allocated_size, i.e. does not touch initialized_size or
* data_size.
*
* Return 0 on success and -errno on error.
*
* Locking: - Caller must hold vol->mftbmp_lock for writing.
* - This function takes NTFS_I(vol->mftbmp_ino)->runlist.lock for
* writing and releases it before returning.
* - This function takes vol->lcnbmp_lock for writing and releases it
* before returning.
*/
static int ntfs_mft_bitmap_extend_allocation_nolock(ntfs_volume *vol)
{
LCN lcn;
s64 ll;
unsigned long flags;
struct page *page;
ntfs_inode *mft_ni, *mftbmp_ni;
runlist_element *rl, *rl2 = NULL;
ntfs_attr_search_ctx *ctx = NULL;
MFT_RECORD *mrec;
ATTR_RECORD *a = NULL;
int ret, mp_size;
u32 old_alen = 0;
u8 *b, tb;
struct {
u8 added_cluster:1;
u8 added_run:1;
u8 mp_rebuilt:1;
} status = { 0, 0, 0 };
ntfs_debug("Extending mft bitmap allocation.");
mft_ni = NTFS_I(vol->mft_ino);
mftbmp_ni = NTFS_I(vol->mftbmp_ino);
/*
* Determine the last lcn of the mft bitmap. The allocated size of the
* mft bitmap cannot be zero so we are ok to do this.
*/
down_write(&mftbmp_ni->runlist.lock);
read_lock_irqsave(&mftbmp_ni->size_lock, flags);
ll = mftbmp_ni->allocated_size;
read_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
rl = ntfs_attr_find_vcn_nolock(mftbmp_ni,
(ll - 1) >> vol->cluster_size_bits, NULL);
if (unlikely(IS_ERR(rl) || !rl->length || rl->lcn < 0)) {
up_write(&mftbmp_ni->runlist.lock);
ntfs_error(vol->sb, "Failed to determine last allocated "
"cluster of mft bitmap attribute.");
if (!IS_ERR(rl))
ret = -EIO;
else
ret = PTR_ERR(rl);
return ret;
}
lcn = rl->lcn + rl->length;
ntfs_debug("Last lcn of mft bitmap attribute is 0x%llx.",
(long long)lcn);
/*
* Attempt to get the cluster following the last allocated cluster by
* hand as it may be in the MFT zone so the allocator would not give it
* to us.
*/
ll = lcn >> 3;
page = ntfs_map_page(vol->lcnbmp_ino->i_mapping,
ll >> PAGE_CACHE_SHIFT);
if (IS_ERR(page)) {
up_write(&mftbmp_ni->runlist.lock);
ntfs_error(vol->sb, "Failed to read from lcn bitmap.");
return PTR_ERR(page);
}
b = (u8*)page_address(page) + (ll & ~PAGE_CACHE_MASK);
tb = 1 << (lcn & 7ull);
down_write(&vol->lcnbmp_lock);
if (*b != 0xff && !(*b & tb)) {
/* Next cluster is free, allocate it. */
*b |= tb;
flush_dcache_page(page);
set_page_dirty(page);
up_write(&vol->lcnbmp_lock);
ntfs_unmap_page(page);
/* Update the mft bitmap runlist. */
rl->length++;
rl[1].vcn++;
status.added_cluster = 1;
ntfs_debug("Appending one cluster to mft bitmap.");
} else {
up_write(&vol->lcnbmp_lock);
ntfs_unmap_page(page);
/* Allocate a cluster from the DATA_ZONE. */
rl2 = ntfs_cluster_alloc(vol, rl[1].vcn, 1, lcn, DATA_ZONE,
true);
if (IS_ERR(rl2)) {
up_write(&mftbmp_ni->runlist.lock);
ntfs_error(vol->sb, "Failed to allocate a cluster for "
"the mft bitmap.");
return PTR_ERR(rl2);
}
rl = ntfs_runlists_merge(mftbmp_ni->runlist.rl, rl2);
if (IS_ERR(rl)) {
up_write(&mftbmp_ni->runlist.lock);
ntfs_error(vol->sb, "Failed to merge runlists for mft "
"bitmap.");
if (ntfs_cluster_free_from_rl(vol, rl2)) {
ntfs_error(vol->sb, "Failed to dealocate "
"allocated cluster.%s", es);
NVolSetErrors(vol);
}
ntfs_free(rl2);
return PTR_ERR(rl);
}
mftbmp_ni->runlist.rl = rl;
status.added_run = 1;
ntfs_debug("Adding one run to mft bitmap.");
/* Find the last run in the new runlist. */
for (; rl[1].length; rl++)
;
}
/*
* Update the attribute record as well. Note: @rl is the last
* (non-terminator) runlist element of mft bitmap.
*/
mrec = map_mft_record(mft_ni);
if (IS_ERR(mrec)) {
ntfs_error(vol->sb, "Failed to map mft record.");
ret = PTR_ERR(mrec);
goto undo_alloc;
}
ctx = ntfs_attr_get_search_ctx(mft_ni, mrec);
if (unlikely(!ctx)) {
ntfs_error(vol->sb, "Failed to get search context.");
ret = -ENOMEM;
goto undo_alloc;
}
ret = ntfs_attr_lookup(mftbmp_ni->type, mftbmp_ni->name,
mftbmp_ni->name_len, CASE_SENSITIVE, rl[1].vcn, NULL,
0, ctx);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to find last attribute extent of "
"mft bitmap attribute.");
if (ret == -ENOENT)
ret = -EIO;
goto undo_alloc;
}
a = ctx->attr;
ll = sle64_to_cpu(a->data.non_resident.lowest_vcn);
/* Search back for the previous last allocated cluster of mft bitmap. */
for (rl2 = rl; rl2 > mftbmp_ni->runlist.rl; rl2--) {
if (ll >= rl2->vcn)
break;
}
BUG_ON(ll < rl2->vcn);
BUG_ON(ll >= rl2->vcn + rl2->length);
/* Get the size for the new mapping pairs array for this extent. */
mp_size = ntfs_get_size_for_mapping_pairs(vol, rl2, ll, -1);
if (unlikely(mp_size <= 0)) {
ntfs_error(vol->sb, "Get size for mapping pairs failed for "
"mft bitmap attribute extent.");
ret = mp_size;
if (!ret)
ret = -EIO;
goto undo_alloc;
}
/* Expand the attribute record if necessary. */
old_alen = le32_to_cpu(a->length);
ret = ntfs_attr_record_resize(ctx->mrec, a, mp_size +
le16_to_cpu(a->data.non_resident.mapping_pairs_offset));
if (unlikely(ret)) {
if (ret != -ENOSPC) {
ntfs_error(vol->sb, "Failed to resize attribute "
"record for mft bitmap attribute.");
goto undo_alloc;
}
// TODO: Deal with this by moving this extent to a new mft
// record or by starting a new extent in a new mft record or by
// moving other attributes out of this mft record.
// Note: It will need to be a special mft record and if none of
// those are available it gets rather complicated...
ntfs_error(vol->sb, "Not enough space in this mft record to "
"accomodate extended mft bitmap attribute "
"extent. Cannot handle this yet.");
ret = -EOPNOTSUPP;
goto undo_alloc;
}
status.mp_rebuilt = 1;
/* Generate the mapping pairs array directly into the attr record. */
ret = ntfs_mapping_pairs_build(vol, (u8*)a +
le16_to_cpu(a->data.non_resident.mapping_pairs_offset),
mp_size, rl2, ll, -1, NULL);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to build mapping pairs array for "
"mft bitmap attribute.");
goto undo_alloc;
}
/* Update the highest_vcn. */
a->data.non_resident.highest_vcn = cpu_to_sle64(rl[1].vcn - 1);
/*
* We now have extended the mft bitmap allocated_size by one cluster.
* Reflect this in the ntfs_inode structure and the attribute record.
*/
if (a->data.non_resident.lowest_vcn) {
/*
* We are not in the first attribute extent, switch to it, but
* first ensure the changes will make it to disk later.
*/
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_reinit_search_ctx(ctx);
ret = ntfs_attr_lookup(mftbmp_ni->type, mftbmp_ni->name,
mftbmp_ni->name_len, CASE_SENSITIVE, 0, NULL,
0, ctx);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to find first attribute "
"extent of mft bitmap attribute.");
goto restore_undo_alloc;
}
a = ctx->attr;
}
write_lock_irqsave(&mftbmp_ni->size_lock, flags);
mftbmp_ni->allocated_size += vol->cluster_size;
a->data.non_resident.allocated_size =
cpu_to_sle64(mftbmp_ni->allocated_size);
write_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
/* Ensure the changes make it to disk. */
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
up_write(&mftbmp_ni->runlist.lock);
ntfs_debug("Done.");
return 0;
restore_undo_alloc:
ntfs_attr_reinit_search_ctx(ctx);
if (ntfs_attr_lookup(mftbmp_ni->type, mftbmp_ni->name,
mftbmp_ni->name_len, CASE_SENSITIVE, rl[1].vcn, NULL,
0, ctx)) {
ntfs_error(vol->sb, "Failed to find last attribute extent of "
"mft bitmap attribute.%s", es);
write_lock_irqsave(&mftbmp_ni->size_lock, flags);
mftbmp_ni->allocated_size += vol->cluster_size;
write_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
up_write(&mftbmp_ni->runlist.lock);
/*
* The only thing that is now wrong is ->allocated_size of the
* base attribute extent which chkdsk should be able to fix.
*/
NVolSetErrors(vol);
return ret;
}
a = ctx->attr;
a->data.non_resident.highest_vcn = cpu_to_sle64(rl[1].vcn - 2);
undo_alloc:
if (status.added_cluster) {
/* Truncate the last run in the runlist by one cluster. */
rl->length--;
rl[1].vcn--;
} else if (status.added_run) {
lcn = rl->lcn;
/* Remove the last run from the runlist. */
rl->lcn = rl[1].lcn;
rl->length = 0;
}
/* Deallocate the cluster. */
down_write(&vol->lcnbmp_lock);
if (ntfs_bitmap_clear_bit(vol->lcnbmp_ino, lcn)) {
ntfs_error(vol->sb, "Failed to free allocated cluster.%s", es);
NVolSetErrors(vol);
}
up_write(&vol->lcnbmp_lock);
if (status.mp_rebuilt) {
if (ntfs_mapping_pairs_build(vol, (u8*)a + le16_to_cpu(
a->data.non_resident.mapping_pairs_offset),
old_alen - le16_to_cpu(
a->data.non_resident.mapping_pairs_offset),
rl2, ll, -1, NULL)) {
ntfs_error(vol->sb, "Failed to restore mapping pairs "
"array.%s", es);
NVolSetErrors(vol);
}
if (ntfs_attr_record_resize(ctx->mrec, a, old_alen)) {
ntfs_error(vol->sb, "Failed to restore attribute "
"record.%s", es);
NVolSetErrors(vol);
}
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
}
if (ctx)
ntfs_attr_put_search_ctx(ctx);
if (!IS_ERR(mrec))
unmap_mft_record(mft_ni);
up_write(&mftbmp_ni->runlist.lock);
return ret;
}
/**
* ntfs_mft_bitmap_extend_initialized_nolock - extend mftbmp initialized data
* @vol: volume on which to extend the mft bitmap attribute
*
* Extend the initialized portion of the mft bitmap attribute on the ntfs
* volume @vol by 8 bytes.
*
* Note: Only changes initialized_size and data_size, i.e. requires that
* allocated_size is big enough to fit the new initialized_size.
*
* Return 0 on success and -error on error.
*
* Locking: Caller must hold vol->mftbmp_lock for writing.
*/
static int ntfs_mft_bitmap_extend_initialized_nolock(ntfs_volume *vol)
{
s64 old_data_size, old_initialized_size;
unsigned long flags;
struct inode *mftbmp_vi;
ntfs_inode *mft_ni, *mftbmp_ni;
ntfs_attr_search_ctx *ctx;
MFT_RECORD *mrec;
ATTR_RECORD *a;
int ret;
ntfs_debug("Extending mft bitmap initiailized (and data) size.");
mft_ni = NTFS_I(vol->mft_ino);
mftbmp_vi = vol->mftbmp_ino;
mftbmp_ni = NTFS_I(mftbmp_vi);
/* Get the attribute record. */
mrec = map_mft_record(mft_ni);
if (IS_ERR(mrec)) {
ntfs_error(vol->sb, "Failed to map mft record.");
return PTR_ERR(mrec);
}
ctx = ntfs_attr_get_search_ctx(mft_ni, mrec);
if (unlikely(!ctx)) {
ntfs_error(vol->sb, "Failed to get search context.");
ret = -ENOMEM;
goto unm_err_out;
}
ret = ntfs_attr_lookup(mftbmp_ni->type, mftbmp_ni->name,
mftbmp_ni->name_len, CASE_SENSITIVE, 0, NULL, 0, ctx);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to find first attribute extent of "
"mft bitmap attribute.");
if (ret == -ENOENT)
ret = -EIO;
goto put_err_out;
}
a = ctx->attr;
write_lock_irqsave(&mftbmp_ni->size_lock, flags);
old_data_size = i_size_read(mftbmp_vi);
old_initialized_size = mftbmp_ni->initialized_size;
/*
* We can simply update the initialized_size before filling the space
* with zeroes because the caller is holding the mft bitmap lock for
* writing which ensures that no one else is trying to access the data.
*/
mftbmp_ni->initialized_size += 8;
a->data.non_resident.initialized_size =
cpu_to_sle64(mftbmp_ni->initialized_size);
if (mftbmp_ni->initialized_size > old_data_size) {
i_size_write(mftbmp_vi, mftbmp_ni->initialized_size);
a->data.non_resident.data_size =
cpu_to_sle64(mftbmp_ni->initialized_size);
}
write_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
/* Ensure the changes make it to disk. */
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
/* Initialize the mft bitmap attribute value with zeroes. */
ret = ntfs_attr_set(mftbmp_ni, old_initialized_size, 8, 0);
if (likely(!ret)) {
ntfs_debug("Done. (Wrote eight initialized bytes to mft "
"bitmap.");
return 0;
}
ntfs_error(vol->sb, "Failed to write to mft bitmap.");
/* Try to recover from the error. */
mrec = map_mft_record(mft_ni);
if (IS_ERR(mrec)) {
ntfs_error(vol->sb, "Failed to map mft record.%s", es);
NVolSetErrors(vol);
return ret;
}
ctx = ntfs_attr_get_search_ctx(mft_ni, mrec);
if (unlikely(!ctx)) {
ntfs_error(vol->sb, "Failed to get search context.%s", es);
NVolSetErrors(vol);
goto unm_err_out;
}
if (ntfs_attr_lookup(mftbmp_ni->type, mftbmp_ni->name,
mftbmp_ni->name_len, CASE_SENSITIVE, 0, NULL, 0, ctx)) {
ntfs_error(vol->sb, "Failed to find first attribute extent of "
"mft bitmap attribute.%s", es);
NVolSetErrors(vol);
put_err_out:
ntfs_attr_put_search_ctx(ctx);
unm_err_out:
unmap_mft_record(mft_ni);
goto err_out;
}
a = ctx->attr;
write_lock_irqsave(&mftbmp_ni->size_lock, flags);
mftbmp_ni->initialized_size = old_initialized_size;
a->data.non_resident.initialized_size =
cpu_to_sle64(old_initialized_size);
if (i_size_read(mftbmp_vi) != old_data_size) {
i_size_write(mftbmp_vi, old_data_size);
a->data.non_resident.data_size = cpu_to_sle64(old_data_size);
}
write_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
#ifdef DEBUG
read_lock_irqsave(&mftbmp_ni->size_lock, flags);
ntfs_debug("Restored status of mftbmp: allocated_size 0x%llx, "
"data_size 0x%llx, initialized_size 0x%llx.",
(long long)mftbmp_ni->allocated_size,
(long long)i_size_read(mftbmp_vi),
(long long)mftbmp_ni->initialized_size);
read_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
#endif /* DEBUG */
err_out:
return ret;
}
/**
* ntfs_mft_data_extend_allocation_nolock - extend mft data attribute
* @vol: volume on which to extend the mft data attribute
*
* Extend the mft data attribute on the ntfs volume @vol by 16 mft records
* worth of clusters or if not enough space for this by one mft record worth
* of clusters.
*
* Note: Only changes allocated_size, i.e. does not touch initialized_size or
* data_size.
*
* Return 0 on success and -errno on error.
*
* Locking: - Caller must hold vol->mftbmp_lock for writing.
* - This function takes NTFS_I(vol->mft_ino)->runlist.lock for
* writing and releases it before returning.
* - This function calls functions which take vol->lcnbmp_lock for
* writing and release it before returning.
*/
static int ntfs_mft_data_extend_allocation_nolock(ntfs_volume *vol)
{
LCN lcn;
VCN old_last_vcn;
s64 min_nr, nr, ll;
unsigned long flags;
ntfs_inode *mft_ni;
runlist_element *rl, *rl2;
ntfs_attr_search_ctx *ctx = NULL;
MFT_RECORD *mrec;
ATTR_RECORD *a = NULL;
int ret, mp_size;
u32 old_alen = 0;
bool mp_rebuilt = false;
ntfs_debug("Extending mft data allocation.");
mft_ni = NTFS_I(vol->mft_ino);
/*
* Determine the preferred allocation location, i.e. the last lcn of
* the mft data attribute. The allocated size of the mft data
* attribute cannot be zero so we are ok to do this.
*/
down_write(&mft_ni->runlist.lock);
read_lock_irqsave(&mft_ni->size_lock, flags);
ll = mft_ni->allocated_size;
read_unlock_irqrestore(&mft_ni->size_lock, flags);
rl = ntfs_attr_find_vcn_nolock(mft_ni,
(ll - 1) >> vol->cluster_size_bits, NULL);
if (unlikely(IS_ERR(rl) || !rl->length || rl->lcn < 0)) {
up_write(&mft_ni->runlist.lock);
ntfs_error(vol->sb, "Failed to determine last allocated "
"cluster of mft data attribute.");
if (!IS_ERR(rl))
ret = -EIO;
else
ret = PTR_ERR(rl);
return ret;
}
lcn = rl->lcn + rl->length;
ntfs_debug("Last lcn of mft data attribute is 0x%llx.", (long long)lcn);
/* Minimum allocation is one mft record worth of clusters. */
min_nr = vol->mft_record_size >> vol->cluster_size_bits;
if (!min_nr)
min_nr = 1;
/* Want to allocate 16 mft records worth of clusters. */
nr = vol->mft_record_size << 4 >> vol->cluster_size_bits;
if (!nr)
nr = min_nr;
/* Ensure we do not go above 2^32-1 mft records. */
read_lock_irqsave(&mft_ni->size_lock, flags);
ll = mft_ni->allocated_size;
read_unlock_irqrestore(&mft_ni->size_lock, flags);
if (unlikely((ll + (nr << vol->cluster_size_bits)) >>
vol->mft_record_size_bits >= (1ll << 32))) {
nr = min_nr;
if (unlikely((ll + (nr << vol->cluster_size_bits)) >>
vol->mft_record_size_bits >= (1ll << 32))) {
ntfs_warning(vol->sb, "Cannot allocate mft record "
"because the maximum number of inodes "
"(2^32) has already been reached.");
up_write(&mft_ni->runlist.lock);
return -ENOSPC;
}
}
ntfs_debug("Trying mft data allocation with %s cluster count %lli.",
nr > min_nr ? "default" : "minimal", (long long)nr);
old_last_vcn = rl[1].vcn;
do {
rl2 = ntfs_cluster_alloc(vol, old_last_vcn, nr, lcn, MFT_ZONE,
true);
if (likely(!IS_ERR(rl2)))
break;
if (PTR_ERR(rl2) != -ENOSPC || nr == min_nr) {
ntfs_error(vol->sb, "Failed to allocate the minimal "
"number of clusters (%lli) for the "
"mft data attribute.", (long long)nr);
up_write(&mft_ni->runlist.lock);
return PTR_ERR(rl2);
}
/*
* There is not enough space to do the allocation, but there
* might be enough space to do a minimal allocation so try that
* before failing.
*/
nr = min_nr;
ntfs_debug("Retrying mft data allocation with minimal cluster "
"count %lli.", (long long)nr);
} while (1);
rl = ntfs_runlists_merge(mft_ni->runlist.rl, rl2);
if (IS_ERR(rl)) {
up_write(&mft_ni->runlist.lock);
ntfs_error(vol->sb, "Failed to merge runlists for mft data "
"attribute.");
if (ntfs_cluster_free_from_rl(vol, rl2)) {
ntfs_error(vol->sb, "Failed to dealocate clusters "
"from the mft data attribute.%s", es);
NVolSetErrors(vol);
}
ntfs_free(rl2);
return PTR_ERR(rl);
}
mft_ni->runlist.rl = rl;
ntfs_debug("Allocated %lli clusters.", (long long)nr);
/* Find the last run in the new runlist. */
for (; rl[1].length; rl++)
;
/* Update the attribute record as well. */
mrec = map_mft_record(mft_ni);
if (IS_ERR(mrec)) {
ntfs_error(vol->sb, "Failed to map mft record.");
ret = PTR_ERR(mrec);
goto undo_alloc;
}
ctx = ntfs_attr_get_search_ctx(mft_ni, mrec);
if (unlikely(!ctx)) {
ntfs_error(vol->sb, "Failed to get search context.");
ret = -ENOMEM;
goto undo_alloc;
}
ret = ntfs_attr_lookup(mft_ni->type, mft_ni->name, mft_ni->name_len,
CASE_SENSITIVE, rl[1].vcn, NULL, 0, ctx);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to find last attribute extent of "
"mft data attribute.");
if (ret == -ENOENT)
ret = -EIO;
goto undo_alloc;
}
a = ctx->attr;
ll = sle64_to_cpu(a->data.non_resident.lowest_vcn);
/* Search back for the previous last allocated cluster of mft bitmap. */
for (rl2 = rl; rl2 > mft_ni->runlist.rl; rl2--) {
if (ll >= rl2->vcn)
break;
}
BUG_ON(ll < rl2->vcn);
BUG_ON(ll >= rl2->vcn + rl2->length);
/* Get the size for the new mapping pairs array for this extent. */
mp_size = ntfs_get_size_for_mapping_pairs(vol, rl2, ll, -1);
if (unlikely(mp_size <= 0)) {
ntfs_error(vol->sb, "Get size for mapping pairs failed for "
"mft data attribute extent.");
ret = mp_size;
if (!ret)
ret = -EIO;
goto undo_alloc;
}
/* Expand the attribute record if necessary. */
old_alen = le32_to_cpu(a->length);
ret = ntfs_attr_record_resize(ctx->mrec, a, mp_size +
le16_to_cpu(a->data.non_resident.mapping_pairs_offset));
if (unlikely(ret)) {
if (ret != -ENOSPC) {
ntfs_error(vol->sb, "Failed to resize attribute "
"record for mft data attribute.");
goto undo_alloc;
}
// TODO: Deal with this by moving this extent to a new mft
// record or by starting a new extent in a new mft record or by
// moving other attributes out of this mft record.
// Note: Use the special reserved mft records and ensure that
// this extent is not required to find the mft record in
// question. If no free special records left we would need to
// move an existing record away, insert ours in its place, and
// then place the moved record into the newly allocated space
// and we would then need to update all references to this mft
// record appropriately. This is rather complicated...
ntfs_error(vol->sb, "Not enough space in this mft record to "
"accomodate extended mft data attribute "
"extent. Cannot handle this yet.");
ret = -EOPNOTSUPP;
goto undo_alloc;
}
mp_rebuilt = true;
/* Generate the mapping pairs array directly into the attr record. */
ret = ntfs_mapping_pairs_build(vol, (u8*)a +
le16_to_cpu(a->data.non_resident.mapping_pairs_offset),
mp_size, rl2, ll, -1, NULL);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to build mapping pairs array of "
"mft data attribute.");
goto undo_alloc;
}
/* Update the highest_vcn. */
a->data.non_resident.highest_vcn = cpu_to_sle64(rl[1].vcn - 1);
/*
* We now have extended the mft data allocated_size by nr clusters.
* Reflect this in the ntfs_inode structure and the attribute record.
* @rl is the last (non-terminator) runlist element of mft data
* attribute.
*/
if (a->data.non_resident.lowest_vcn) {
/*
* We are not in the first attribute extent, switch to it, but
* first ensure the changes will make it to disk later.
*/
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_reinit_search_ctx(ctx);
ret = ntfs_attr_lookup(mft_ni->type, mft_ni->name,
mft_ni->name_len, CASE_SENSITIVE, 0, NULL, 0,
ctx);
if (unlikely(ret)) {
ntfs_error(vol->sb, "Failed to find first attribute "
"extent of mft data attribute.");
goto restore_undo_alloc;
}
a = ctx->attr;
}
write_lock_irqsave(&mft_ni->size_lock, flags);
mft_ni->allocated_size += nr << vol->cluster_size_bits;
a->data.non_resident.allocated_size =
cpu_to_sle64(mft_ni->allocated_size);
write_unlock_irqrestore(&mft_ni->size_lock, flags);
/* Ensure the changes make it to disk. */
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
up_write(&mft_ni->runlist.lock);
ntfs_debug("Done.");
return 0;
restore_undo_alloc:
ntfs_attr_reinit_search_ctx(ctx);
if (ntfs_attr_lookup(mft_ni->type, mft_ni->name, mft_ni->name_len,
CASE_SENSITIVE, rl[1].vcn, NULL, 0, ctx)) {
ntfs_error(vol->sb, "Failed to find last attribute extent of "
"mft data attribute.%s", es);
write_lock_irqsave(&mft_ni->size_lock, flags);
mft_ni->allocated_size += nr << vol->cluster_size_bits;
write_unlock_irqrestore(&mft_ni->size_lock, flags);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
up_write(&mft_ni->runlist.lock);
/*
* The only thing that is now wrong is ->allocated_size of the
* base attribute extent which chkdsk should be able to fix.
*/
NVolSetErrors(vol);
return ret;
}
ctx->attr->data.non_resident.highest_vcn =
cpu_to_sle64(old_last_vcn - 1);
undo_alloc:
if (ntfs_cluster_free(mft_ni, old_last_vcn, -1, ctx) < 0) {
ntfs_error(vol->sb, "Failed to free clusters from mft data "
"attribute.%s", es);
NVolSetErrors(vol);
}
a = ctx->attr;
if (ntfs_rl_truncate_nolock(vol, &mft_ni->runlist, old_last_vcn)) {
ntfs_error(vol->sb, "Failed to truncate mft data attribute "
"runlist.%s", es);
NVolSetErrors(vol);
}
if (mp_rebuilt && !IS_ERR(ctx->mrec)) {
if (ntfs_mapping_pairs_build(vol, (u8*)a + le16_to_cpu(
a->data.non_resident.mapping_pairs_offset),
old_alen - le16_to_cpu(
a->data.non_resident.mapping_pairs_offset),
rl2, ll, -1, NULL)) {
ntfs_error(vol->sb, "Failed to restore mapping pairs "
"array.%s", es);
NVolSetErrors(vol);
}
if (ntfs_attr_record_resize(ctx->mrec, a, old_alen)) {
ntfs_error(vol->sb, "Failed to restore attribute "
"record.%s", es);
NVolSetErrors(vol);
}
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
} else if (IS_ERR(ctx->mrec)) {
ntfs_error(vol->sb, "Failed to restore attribute search "
"context.%s", es);
NVolSetErrors(vol);
}
if (ctx)
ntfs_attr_put_search_ctx(ctx);
if (!IS_ERR(mrec))
unmap_mft_record(mft_ni);
up_write(&mft_ni->runlist.lock);
return ret;
}
/**
* ntfs_mft_record_layout - layout an mft record into a memory buffer
* @vol: volume to which the mft record will belong
* @mft_no: mft reference specifying the mft record number
* @m: destination buffer of size >= @vol->mft_record_size bytes
*
* Layout an empty, unused mft record with the mft record number @mft_no into
* the buffer @m. The volume @vol is needed because the mft record structure
* was modified in NTFS 3.1 so we need to know which volume version this mft
* record will be used on.
*
* Return 0 on success and -errno on error.
*/
static int ntfs_mft_record_layout(const ntfs_volume *vol, const s64 mft_no,
MFT_RECORD *m)
{
ATTR_RECORD *a;
ntfs_debug("Entering for mft record 0x%llx.", (long long)mft_no);
if (mft_no >= (1ll << 32)) {
ntfs_error(vol->sb, "Mft record number 0x%llx exceeds "
"maximum of 2^32.", (long long)mft_no);
return -ERANGE;
}
/* Start by clearing the whole mft record to gives us a clean slate. */
memset(m, 0, vol->mft_record_size);
/* Aligned to 2-byte boundary. */
if (vol->major_ver < 3 || (vol->major_ver == 3 && !vol->minor_ver))
m->usa_ofs = cpu_to_le16((sizeof(MFT_RECORD_OLD) + 1) & ~1);
else {
m->usa_ofs = cpu_to_le16((sizeof(MFT_RECORD) + 1) & ~1);
/*
* Set the NTFS 3.1+ specific fields while we know that the
* volume version is 3.1+.
*/
m->reserved = 0;
m->mft_record_number = cpu_to_le32((u32)mft_no);
}
m->magic = magic_FILE;
if (vol->mft_record_size >= NTFS_BLOCK_SIZE)
m->usa_count = cpu_to_le16(vol->mft_record_size /
NTFS_BLOCK_SIZE + 1);
else {
m->usa_count = cpu_to_le16(1);
ntfs_warning(vol->sb, "Sector size is bigger than mft record "
"size. Setting usa_count to 1. If chkdsk "
"reports this as corruption, please email "
"linux-ntfs-dev@lists.sourceforge.net stating "
"that you saw this message and that the "
"modified filesystem created was corrupt. "
"Thank you.");
}
/* Set the update sequence number to 1. */
*(le16*)((u8*)m + le16_to_cpu(m->usa_ofs)) = cpu_to_le16(1);
m->lsn = 0;
m->sequence_number = cpu_to_le16(1);
m->link_count = 0;
/*
* Place the attributes straight after the update sequence array,
* aligned to 8-byte boundary.
*/
m->attrs_offset = cpu_to_le16((le16_to_cpu(m->usa_ofs) +
(le16_to_cpu(m->usa_count) << 1) + 7) & ~7);
m->flags = 0;
/*
* Using attrs_offset plus eight bytes (for the termination attribute).
* attrs_offset is already aligned to 8-byte boundary, so no need to
* align again.
*/
m->bytes_in_use = cpu_to_le32(le16_to_cpu(m->attrs_offset) + 8);
m->bytes_allocated = cpu_to_le32(vol->mft_record_size);
m->base_mft_record = 0;
m->next_attr_instance = 0;
/* Add the termination attribute. */
a = (ATTR_RECORD*)((u8*)m + le16_to_cpu(m->attrs_offset));
a->type = AT_END;
a->length = 0;
ntfs_debug("Done.");
return 0;
}
/**
* ntfs_mft_record_format - format an mft record on an ntfs volume
* @vol: volume on which to format the mft record
* @mft_no: mft record number to format
*
* Format the mft record @mft_no in $MFT/$DATA, i.e. lay out an empty, unused
* mft record into the appropriate place of the mft data attribute. This is
* used when extending the mft data attribute.
*
* Return 0 on success and -errno on error.
*/
static int ntfs_mft_record_format(const ntfs_volume *vol, const s64 mft_no)
{
loff_t i_size;
struct inode *mft_vi = vol->mft_ino;
struct page *page;
MFT_RECORD *m;
pgoff_t index, end_index;
unsigned int ofs;
int err;
ntfs_debug("Entering for mft record 0x%llx.", (long long)mft_no);
/*
* The index into the page cache and the offset within the page cache
* page of the wanted mft record.
*/
index = mft_no << vol->mft_record_size_bits >> PAGE_CACHE_SHIFT;
ofs = (mft_no << vol->mft_record_size_bits) & ~PAGE_CACHE_MASK;
/* The maximum valid index into the page cache for $MFT's data. */
i_size = i_size_read(mft_vi);
end_index = i_size >> PAGE_CACHE_SHIFT;
if (unlikely(index >= end_index)) {
if (unlikely(index > end_index || ofs + vol->mft_record_size >=
(i_size & ~PAGE_CACHE_MASK))) {
ntfs_error(vol->sb, "Tried to format non-existing mft "
"record 0x%llx.", (long long)mft_no);
return -ENOENT;
}
}
/* Read, map, and pin the page containing the mft record. */
page = ntfs_map_page(mft_vi->i_mapping, index);
if (IS_ERR(page)) {
ntfs_error(vol->sb, "Failed to map page containing mft record "
"to format 0x%llx.", (long long)mft_no);
return PTR_ERR(page);
}
lock_page(page);
BUG_ON(!PageUptodate(page));
ClearPageUptodate(page);
m = (MFT_RECORD*)((u8*)page_address(page) + ofs);
err = ntfs_mft_record_layout(vol, mft_no, m);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to layout mft record 0x%llx.",
(long long)mft_no);
SetPageUptodate(page);
unlock_page(page);
ntfs_unmap_page(page);
return err;
}
flush_dcache_page(page);
SetPageUptodate(page);
unlock_page(page);
/*
* Make sure the mft record is written out to disk. We could use
* ilookup5() to check if an inode is in icache and so on but this is
* unnecessary as ntfs_writepage() will write the dirty record anyway.
*/
mark_ntfs_record_dirty(page, ofs);
ntfs_unmap_page(page);
ntfs_debug("Done.");
return 0;
}
/**
* ntfs_mft_record_alloc - allocate an mft record on an ntfs volume
* @vol: [IN] volume on which to allocate the mft record
* @mode: [IN] mode if want a file or directory, i.e. base inode or 0
* @base_ni: [IN] open base inode if allocating an extent mft record or NULL
* @mrec: [OUT] on successful return this is the mapped mft record
*
* Allocate an mft record in $MFT/$DATA of an open ntfs volume @vol.
*
* If @base_ni is NULL make the mft record a base mft record, i.e. a file or
* direvctory inode, and allocate it at the default allocator position. In
* this case @mode is the file mode as given to us by the caller. We in
* particular use @mode to distinguish whether a file or a directory is being
* created (S_IFDIR(mode) and S_IFREG(mode), respectively).
*
* If @base_ni is not NULL make the allocated mft record an extent record,
* allocate it starting at the mft record after the base mft record and attach
* the allocated and opened ntfs inode to the base inode @base_ni. In this
* case @mode must be 0 as it is meaningless for extent inodes.
*
* You need to check the return value with IS_ERR(). If false, the function
* was successful and the return value is the now opened ntfs inode of the
* allocated mft record. *@mrec is then set to the allocated, mapped, pinned,
* and locked mft record. If IS_ERR() is true, the function failed and the
* error code is obtained from PTR_ERR(return value). *@mrec is undefined in
* this case.
*
* Allocation strategy:
*
* To find a free mft record, we scan the mft bitmap for a zero bit. To
* optimize this we start scanning at the place specified by @base_ni or if
* @base_ni is NULL we start where we last stopped and we perform wrap around
* when we reach the end. Note, we do not try to allocate mft records below
* number 24 because numbers 0 to 15 are the defined system files anyway and 16
* to 24 are special in that they are used for storing extension mft records
* for the $DATA attribute of $MFT. This is required to avoid the possibility
* of creating a runlist with a circular dependency which once written to disk
* can never be read in again. Windows will only use records 16 to 24 for
* normal files if the volume is completely out of space. We never use them
* which means that when the volume is really out of space we cannot create any
* more files while Windows can still create up to 8 small files. We can start
* doing this at some later time, it does not matter much for now.
*
* When scanning the mft bitmap, we only search up to the last allocated mft
* record. If there are no free records left in the range 24 to number of
* allocated mft records, then we extend the $MFT/$DATA attribute in order to
* create free mft records. We extend the allocated size of $MFT/$DATA by 16
* records at a time or one cluster, if cluster size is above 16kiB. If there
* is not sufficient space to do this, we try to extend by a single mft record
* or one cluster, if cluster size is above the mft record size.
*
* No matter how many mft records we allocate, we initialize only the first
* allocated mft record, incrementing mft data size and initialized size
* accordingly, open an ntfs_inode for it and return it to the caller, unless
* there are less than 24 mft records, in which case we allocate and initialize
* mft records until we reach record 24 which we consider as the first free mft
* record for use by normal files.
*
* If during any stage we overflow the initialized data in the mft bitmap, we
* extend the initialized size (and data size) by 8 bytes, allocating another
* cluster if required. The bitmap data size has to be at least equal to the
* number of mft records in the mft, but it can be bigger, in which case the
* superflous bits are padded with zeroes.
*
* Thus, when we return successfully (IS_ERR() is false), we will have:
* - initialized / extended the mft bitmap if necessary,
* - initialized / extended the mft data if necessary,
* - set the bit corresponding to the mft record being allocated in the
* mft bitmap,
* - opened an ntfs_inode for the allocated mft record, and we will have
* - returned the ntfs_inode as well as the allocated mapped, pinned, and
* locked mft record.
*
* On error, the volume will be left in a consistent state and no record will
* be allocated. If rolling back a partial operation fails, we may leave some
* inconsistent metadata in which case we set NVolErrors() so the volume is
* left dirty when unmounted.
*
* Note, this function cannot make use of most of the normal functions, like
* for example for attribute resizing, etc, because when the run list overflows
* the base mft record and an attribute list is used, it is very important that
* the extension mft records used to store the $DATA attribute of $MFT can be
* reached without having to read the information contained inside them, as
* this would make it impossible to find them in the first place after the
* volume is unmounted. $MFT/$BITMAP probably does not need to follow this
* rule because the bitmap is not essential for finding the mft records, but on
* the other hand, handling the bitmap in this special way would make life
* easier because otherwise there might be circular invocations of functions
* when reading the bitmap.
*/
ntfs_inode *ntfs_mft_record_alloc(ntfs_volume *vol, const int mode,
ntfs_inode *base_ni, MFT_RECORD **mrec)
{
s64 ll, bit, old_data_initialized, old_data_size;
unsigned long flags;
struct inode *vi;
struct page *page;
ntfs_inode *mft_ni, *mftbmp_ni, *ni;
ntfs_attr_search_ctx *ctx;
MFT_RECORD *m;
ATTR_RECORD *a;
pgoff_t index;
unsigned int ofs;
int err;
le16 seq_no, usn;
bool record_formatted = false;
if (base_ni) {
ntfs_debug("Entering (allocating an extent mft record for "
"base mft record 0x%llx).",
(long long)base_ni->mft_no);
/* @mode and @base_ni are mutually exclusive. */
BUG_ON(mode);
} else
ntfs_debug("Entering (allocating a base mft record).");
if (mode) {
/* @mode and @base_ni are mutually exclusive. */
BUG_ON(base_ni);
/* We only support creation of normal files and directories. */
if (!S_ISREG(mode) && !S_ISDIR(mode))
return ERR_PTR(-EOPNOTSUPP);
}
BUG_ON(!mrec);
mft_ni = NTFS_I(vol->mft_ino);
mftbmp_ni = NTFS_I(vol->mftbmp_ino);
down_write(&vol->mftbmp_lock);
bit = ntfs_mft_bitmap_find_and_alloc_free_rec_nolock(vol, base_ni);
if (bit >= 0) {
ntfs_debug("Found and allocated free record (#1), bit 0x%llx.",
(long long)bit);
goto have_alloc_rec;
}
if (bit != -ENOSPC) {
up_write(&vol->mftbmp_lock);
return ERR_PTR(bit);
}
/*
* No free mft records left. If the mft bitmap already covers more
* than the currently used mft records, the next records are all free,
* so we can simply allocate the first unused mft record.
* Note: We also have to make sure that the mft bitmap at least covers
* the first 24 mft records as they are special and whilst they may not
* be in use, we do not allocate from them.
*/
read_lock_irqsave(&mft_ni->size_lock, flags);
ll = mft_ni->initialized_size >> vol->mft_record_size_bits;
read_unlock_irqrestore(&mft_ni->size_lock, flags);
read_lock_irqsave(&mftbmp_ni->size_lock, flags);
old_data_initialized = mftbmp_ni->initialized_size;
read_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
if (old_data_initialized << 3 > ll && old_data_initialized > 3) {
bit = ll;
if (bit < 24)
bit = 24;
if (unlikely(bit >= (1ll << 32)))
goto max_err_out;
ntfs_debug("Found free record (#2), bit 0x%llx.",
(long long)bit);
goto found_free_rec;
}
/*
* The mft bitmap needs to be expanded until it covers the first unused
* mft record that we can allocate.
* Note: The smallest mft record we allocate is mft record 24.
*/
bit = old_data_initialized << 3;
if (unlikely(bit >= (1ll << 32)))
goto max_err_out;
read_lock_irqsave(&mftbmp_ni->size_lock, flags);
old_data_size = mftbmp_ni->allocated_size;
ntfs_debug("Status of mftbmp before extension: allocated_size 0x%llx, "
"data_size 0x%llx, initialized_size 0x%llx.",
(long long)old_data_size,
(long long)i_size_read(vol->mftbmp_ino),
(long long)old_data_initialized);
read_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
if (old_data_initialized + 8 > old_data_size) {
/* Need to extend bitmap by one more cluster. */
ntfs_debug("mftbmp: initialized_size + 8 > allocated_size.");
err = ntfs_mft_bitmap_extend_allocation_nolock(vol);
if (unlikely(err)) {
up_write(&vol->mftbmp_lock);
goto err_out;
}
#ifdef DEBUG
read_lock_irqsave(&mftbmp_ni->size_lock, flags);
ntfs_debug("Status of mftbmp after allocation extension: "
"allocated_size 0x%llx, data_size 0x%llx, "
"initialized_size 0x%llx.",
(long long)mftbmp_ni->allocated_size,
(long long)i_size_read(vol->mftbmp_ino),
(long long)mftbmp_ni->initialized_size);
read_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
#endif /* DEBUG */
}
/*
* We now have sufficient allocated space, extend the initialized_size
* as well as the data_size if necessary and fill the new space with
* zeroes.
*/
err = ntfs_mft_bitmap_extend_initialized_nolock(vol);
if (unlikely(err)) {
up_write(&vol->mftbmp_lock);
goto err_out;
}
#ifdef DEBUG
read_lock_irqsave(&mftbmp_ni->size_lock, flags);
ntfs_debug("Status of mftbmp after initialized extention: "
"allocated_size 0x%llx, data_size 0x%llx, "
"initialized_size 0x%llx.",
(long long)mftbmp_ni->allocated_size,
(long long)i_size_read(vol->mftbmp_ino),
(long long)mftbmp_ni->initialized_size);
read_unlock_irqrestore(&mftbmp_ni->size_lock, flags);
#endif /* DEBUG */
ntfs_debug("Found free record (#3), bit 0x%llx.", (long long)bit);
found_free_rec:
/* @bit is the found free mft record, allocate it in the mft bitmap. */
ntfs_debug("At found_free_rec.");
err = ntfs_bitmap_set_bit(vol->mftbmp_ino, bit);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to allocate bit in mft bitmap.");
up_write(&vol->mftbmp_lock);
goto err_out;
}
ntfs_debug("Set bit 0x%llx in mft bitmap.", (long long)bit);
have_alloc_rec:
/*
* The mft bitmap is now uptodate. Deal with mft data attribute now.
* Note, we keep hold of the mft bitmap lock for writing until all
* modifications to the mft data attribute are complete, too, as they
* will impact decisions for mft bitmap and mft record allocation done
* by a parallel allocation and if the lock is not maintained a
* parallel allocation could allocate the same mft record as this one.
*/
ll = (bit + 1) << vol->mft_record_size_bits;
read_lock_irqsave(&mft_ni->size_lock, flags);
old_data_initialized = mft_ni->initialized_size;
read_unlock_irqrestore(&mft_ni->size_lock, flags);
if (ll <= old_data_initialized) {
ntfs_debug("Allocated mft record already initialized.");
goto mft_rec_already_initialized;
}
ntfs_debug("Initializing allocated mft record.");
/*
* The mft record is outside the initialized data. Extend the mft data
* attribute until it covers the allocated record. The loop is only
* actually traversed more than once when a freshly formatted volume is
* first written to so it optimizes away nicely in the common case.
*/
read_lock_irqsave(&mft_ni->size_lock, flags);
ntfs_debug("Status of mft data before extension: "
"allocated_size 0x%llx, data_size 0x%llx, "
"initialized_size 0x%llx.",
(long long)mft_ni->allocated_size,
(long long)i_size_read(vol->mft_ino),
(long long)mft_ni->initialized_size);
while (ll > mft_ni->allocated_size) {
read_unlock_irqrestore(&mft_ni->size_lock, flags);
err = ntfs_mft_data_extend_allocation_nolock(vol);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to extend mft data "
"allocation.");
goto undo_mftbmp_alloc_nolock;
}
read_lock_irqsave(&mft_ni->size_lock, flags);
ntfs_debug("Status of mft data after allocation extension: "
"allocated_size 0x%llx, data_size 0x%llx, "
"initialized_size 0x%llx.",
(long long)mft_ni->allocated_size,
(long long)i_size_read(vol->mft_ino),
(long long)mft_ni->initialized_size);
}
read_unlock_irqrestore(&mft_ni->size_lock, flags);
/*
* Extend mft data initialized size (and data size of course) to reach
* the allocated mft record, formatting the mft records allong the way.
* Note: We only modify the ntfs_inode structure as that is all that is
* needed by ntfs_mft_record_format(). We will update the attribute
* record itself in one fell swoop later on.
*/
write_lock_irqsave(&mft_ni->size_lock, flags);
old_data_initialized = mft_ni->initialized_size;
old_data_size = vol->mft_ino->i_size;
while (ll > mft_ni->initialized_size) {
s64 new_initialized_size, mft_no;
new_initialized_size = mft_ni->initialized_size +
vol->mft_record_size;
mft_no = mft_ni->initialized_size >> vol->mft_record_size_bits;
if (new_initialized_size > i_size_read(vol->mft_ino))
i_size_write(vol->mft_ino, new_initialized_size);
write_unlock_irqrestore(&mft_ni->size_lock, flags);
ntfs_debug("Initializing mft record 0x%llx.",
(long long)mft_no);
err = ntfs_mft_record_format(vol, mft_no);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to format mft record.");
goto undo_data_init;
}
write_lock_irqsave(&mft_ni->size_lock, flags);
mft_ni->initialized_size = new_initialized_size;
}
write_unlock_irqrestore(&mft_ni->size_lock, flags);
record_formatted = true;
/* Update the mft data attribute record to reflect the new sizes. */
m = map_mft_record(mft_ni);
if (IS_ERR(m)) {
ntfs_error(vol->sb, "Failed to map mft record.");
err = PTR_ERR(m);
goto undo_data_init;
}
ctx = ntfs_attr_get_search_ctx(mft_ni, m);
if (unlikely(!ctx)) {
ntfs_error(vol->sb, "Failed to get search context.");
err = -ENOMEM;
unmap_mft_record(mft_ni);
goto undo_data_init;
}
err = ntfs_attr_lookup(mft_ni->type, mft_ni->name, mft_ni->name_len,
CASE_SENSITIVE, 0, NULL, 0, ctx);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to find first attribute extent of "
"mft data attribute.");
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
goto undo_data_init;
}
a = ctx->attr;
read_lock_irqsave(&mft_ni->size_lock, flags);
a->data.non_resident.initialized_size =
cpu_to_sle64(mft_ni->initialized_size);
a->data.non_resident.data_size =
cpu_to_sle64(i_size_read(vol->mft_ino));
read_unlock_irqrestore(&mft_ni->size_lock, flags);
/* Ensure the changes make it to disk. */
flush_dcache_mft_record_page(ctx->ntfs_ino);
mark_mft_record_dirty(ctx->ntfs_ino);
ntfs_attr_put_search_ctx(ctx);
unmap_mft_record(mft_ni);
read_lock_irqsave(&mft_ni->size_lock, flags);
ntfs_debug("Status of mft data after mft record initialization: "
"allocated_size 0x%llx, data_size 0x%llx, "
"initialized_size 0x%llx.",
(long long)mft_ni->allocated_size,
(long long)i_size_read(vol->mft_ino),
(long long)mft_ni->initialized_size);
BUG_ON(i_size_read(vol->mft_ino) > mft_ni->allocated_size);
BUG_ON(mft_ni->initialized_size > i_size_read(vol->mft_ino));
read_unlock_irqrestore(&mft_ni->size_lock, flags);
mft_rec_already_initialized:
/*
* We can finally drop the mft bitmap lock as the mft data attribute
* has been fully updated. The only disparity left is that the
* allocated mft record still needs to be marked as in use to match the
* set bit in the mft bitmap but this is actually not a problem since
* this mft record is not referenced from anywhere yet and the fact
* that it is allocated in the mft bitmap means that no-one will try to
* allocate it either.
*/
up_write(&vol->mftbmp_lock);
/*
* We now have allocated and initialized the mft record. Calculate the
* index of and the offset within the page cache page the record is in.
*/
index = bit << vol->mft_record_size_bits >> PAGE_CACHE_SHIFT;
ofs = (bit << vol->mft_record_size_bits) & ~PAGE_CACHE_MASK;
/* Read, map, and pin the page containing the mft record. */
page = ntfs_map_page(vol->mft_ino->i_mapping, index);
if (IS_ERR(page)) {
ntfs_error(vol->sb, "Failed to map page containing allocated "
"mft record 0x%llx.", (long long)bit);
err = PTR_ERR(page);
goto undo_mftbmp_alloc;
}
lock_page(page);
BUG_ON(!PageUptodate(page));
ClearPageUptodate(page);
m = (MFT_RECORD*)((u8*)page_address(page) + ofs);
/* If we just formatted the mft record no need to do it again. */
if (!record_formatted) {
/* Sanity check that the mft record is really not in use. */
if (ntfs_is_file_record(m->magic) &&
(m->flags & MFT_RECORD_IN_USE)) {
ntfs_error(vol->sb, "Mft record 0x%llx was marked "
"free in mft bitmap but is marked "
"used itself. Corrupt filesystem. "
"Unmount and run chkdsk.",
(long long)bit);
err = -EIO;
SetPageUptodate(page);
unlock_page(page);
ntfs_unmap_page(page);
NVolSetErrors(vol);
goto undo_mftbmp_alloc;
}
/*
* We need to (re-)format the mft record, preserving the
* sequence number if it is not zero as well as the update
* sequence number if it is not zero or -1 (0xffff). This
* means we do not need to care whether or not something went
* wrong with the previous mft record.
*/
seq_no = m->sequence_number;
usn = *(le16*)((u8*)m + le16_to_cpu(m->usa_ofs));
err = ntfs_mft_record_layout(vol, bit, m);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to layout allocated mft "
"record 0x%llx.", (long long)bit);
SetPageUptodate(page);
unlock_page(page);
ntfs_unmap_page(page);
goto undo_mftbmp_alloc;
}
if (seq_no)
m->sequence_number = seq_no;
if (usn && le16_to_cpu(usn) != 0xffff)
*(le16*)((u8*)m + le16_to_cpu(m->usa_ofs)) = usn;
}
/* Set the mft record itself in use. */
m->flags |= MFT_RECORD_IN_USE;
if (S_ISDIR(mode))
m->flags |= MFT_RECORD_IS_DIRECTORY;
flush_dcache_page(page);
SetPageUptodate(page);
if (base_ni) {
/*
* Setup the base mft record in the extent mft record. This
* completes initialization of the allocated extent mft record
* and we can simply use it with map_extent_mft_record().
*/
m->base_mft_record = MK_LE_MREF(base_ni->mft_no,
base_ni->seq_no);
/*
* Allocate an extent inode structure for the new mft record,
* attach it to the base inode @base_ni and map, pin, and lock
* its, i.e. the allocated, mft record.
*/
m = map_extent_mft_record(base_ni, bit, &ni);
if (IS_ERR(m)) {
ntfs_error(vol->sb, "Failed to map allocated extent "
"mft record 0x%llx.", (long long)bit);
err = PTR_ERR(m);
/* Set the mft record itself not in use. */
m->flags &= cpu_to_le16(
~le16_to_cpu(MFT_RECORD_IN_USE));
flush_dcache_page(page);
/* Make sure the mft record is written out to disk. */
mark_ntfs_record_dirty(page, ofs);
unlock_page(page);
ntfs_unmap_page(page);
goto undo_mftbmp_alloc;
}
/*
* Make sure the allocated mft record is written out to disk.
* No need to set the inode dirty because the caller is going
* to do that anyway after finishing with the new extent mft
* record (e.g. at a minimum a new attribute will be added to
* the mft record.
*/
mark_ntfs_record_dirty(page, ofs);
unlock_page(page);
/*
* Need to unmap the page since map_extent_mft_record() mapped
* it as well so we have it mapped twice at the moment.
*/
ntfs_unmap_page(page);
} else {
/*
* Allocate a new VFS inode and set it up. NOTE: @vi->i_nlink
* is set to 1 but the mft record->link_count is 0. The caller
* needs to bear this in mind.
*/
vi = new_inode(vol->sb);
if (unlikely(!vi)) {
err = -ENOMEM;
/* Set the mft record itself not in use. */
m->flags &= cpu_to_le16(
~le16_to_cpu(MFT_RECORD_IN_USE));
flush_dcache_page(page);
/* Make sure the mft record is written out to disk. */
mark_ntfs_record_dirty(page, ofs);
unlock_page(page);
ntfs_unmap_page(page);
goto undo_mftbmp_alloc;
}
vi->i_ino = bit;
/*
* This is for checking whether an inode has changed w.r.t. a
* file so that the file can be updated if necessary (compare
* with f_version).
*/
vi->i_version = 1;
/* The owner and group come from the ntfs volume. */
vi->i_uid = vol->uid;
vi->i_gid = vol->gid;
/* Initialize the ntfs specific part of @vi. */
ntfs_init_big_inode(vi);
ni = NTFS_I(vi);
/*
* Set the appropriate mode, attribute type, and name. For
* directories, also setup the index values to the defaults.
*/
if (S_ISDIR(mode)) {
vi->i_mode = S_IFDIR | S_IRWXUGO;
vi->i_mode &= ~vol->dmask;
NInoSetMstProtected(ni);
ni->type = AT_INDEX_ALLOCATION;
ni->name = I30;
ni->name_len = 4;
ni->itype.index.block_size = 4096;
ni->itype.index.block_size_bits = ntfs_ffs(4096) - 1;
ni->itype.index.collation_rule = COLLATION_FILE_NAME;
if (vol->cluster_size <= ni->itype.index.block_size) {
ni->itype.index.vcn_size = vol->cluster_size;
ni->itype.index.vcn_size_bits =
vol->cluster_size_bits;
} else {
ni->itype.index.vcn_size = vol->sector_size;
ni->itype.index.vcn_size_bits =
vol->sector_size_bits;
}
} else {
vi->i_mode = S_IFREG | S_IRWXUGO;
vi->i_mode &= ~vol->fmask;
ni->type = AT_DATA;
ni->name = NULL;
ni->name_len = 0;
}
if (IS_RDONLY(vi))
vi->i_mode &= ~S_IWUGO;
/* Set the inode times to the current time. */
vi->i_atime = vi->i_mtime = vi->i_ctime =
current_fs_time(vi->i_sb);
/*
* Set the file size to 0, the ntfs inode sizes are set to 0 by
* the call to ntfs_init_big_inode() below.
*/
vi->i_size = 0;
vi->i_blocks = 0;
/* Set the sequence number. */
vi->i_generation = ni->seq_no = le16_to_cpu(m->sequence_number);
/*
* Manually map, pin, and lock the mft record as we already
* have its page mapped and it is very easy to do.
*/
atomic_inc(&ni->count);
mutex_lock(&ni->mrec_lock);
ni->page = page;
ni->page_ofs = ofs;
/*
* Make sure the allocated mft record is written out to disk.
* NOTE: We do not set the ntfs inode dirty because this would
* fail in ntfs_write_inode() because the inode does not have a
* standard information attribute yet. Also, there is no need
* to set the inode dirty because the caller is going to do
* that anyway after finishing with the new mft record (e.g. at
* a minimum some new attributes will be added to the mft
* record.
*/
mark_ntfs_record_dirty(page, ofs);
unlock_page(page);
/* Add the inode to the inode hash for the superblock. */
insert_inode_hash(vi);
/* Update the default mft allocation position. */
vol->mft_data_pos = bit + 1;
}
/*
* Return the opened, allocated inode of the allocated mft record as
* well as the mapped, pinned, and locked mft record.
*/
ntfs_debug("Returning opened, allocated %sinode 0x%llx.",
base_ni ? "extent " : "", (long long)bit);
*mrec = m;
return ni;
undo_data_init:
write_lock_irqsave(&mft_ni->size_lock, flags);
mft_ni->initialized_size = old_data_initialized;
i_size_write(vol->mft_ino, old_data_size);
write_unlock_irqrestore(&mft_ni->size_lock, flags);
goto undo_mftbmp_alloc_nolock;
undo_mftbmp_alloc:
down_write(&vol->mftbmp_lock);
undo_mftbmp_alloc_nolock:
if (ntfs_bitmap_clear_bit(vol->mftbmp_ino, bit)) {
ntfs_error(vol->sb, "Failed to clear bit in mft bitmap.%s", es);
NVolSetErrors(vol);
}
up_write(&vol->mftbmp_lock);
err_out:
return ERR_PTR(err);
max_err_out:
ntfs_warning(vol->sb, "Cannot allocate mft record because the maximum "
"number of inodes (2^32) has already been reached.");
up_write(&vol->mftbmp_lock);
return ERR_PTR(-ENOSPC);
}
/**
* ntfs_extent_mft_record_free - free an extent mft record on an ntfs volume
* @ni: ntfs inode of the mapped extent mft record to free
* @m: mapped extent mft record of the ntfs inode @ni
*
* Free the mapped extent mft record @m of the extent ntfs inode @ni.
*
* Note that this function unmaps the mft record and closes and destroys @ni
* internally and hence you cannot use either @ni nor @m any more after this
* function returns success.
*
* On success return 0 and on error return -errno. @ni and @m are still valid
* in this case and have not been freed.
*
* For some errors an error message is displayed and the success code 0 is
* returned and the volume is then left dirty on umount. This makes sense in
* case we could not rollback the changes that were already done since the
* caller no longer wants to reference this mft record so it does not matter to
* the caller if something is wrong with it as long as it is properly detached
* from the base inode.
*/
int ntfs_extent_mft_record_free(ntfs_inode *ni, MFT_RECORD *m)
{
unsigned long mft_no = ni->mft_no;
ntfs_volume *vol = ni->vol;
ntfs_inode *base_ni;
ntfs_inode **extent_nis;
int i, err;
le16 old_seq_no;
u16 seq_no;
BUG_ON(NInoAttr(ni));
BUG_ON(ni->nr_extents != -1);
mutex_lock(&ni->extent_lock);
base_ni = ni->ext.base_ntfs_ino;
mutex_unlock(&ni->extent_lock);
BUG_ON(base_ni->nr_extents <= 0);
ntfs_debug("Entering for extent inode 0x%lx, base inode 0x%lx.\n",
mft_no, base_ni->mft_no);
mutex_lock(&base_ni->extent_lock);
/* Make sure we are holding the only reference to the extent inode. */
if (atomic_read(&ni->count) > 2) {
ntfs_error(vol->sb, "Tried to free busy extent inode 0x%lx, "
"not freeing.", base_ni->mft_no);
mutex_unlock(&base_ni->extent_lock);
return -EBUSY;
}
/* Dissociate the ntfs inode from the base inode. */
extent_nis = base_ni->ext.extent_ntfs_inos;
err = -ENOENT;
for (i = 0; i < base_ni->nr_extents; i++) {
if (ni != extent_nis[i])
continue;
extent_nis += i;
base_ni->nr_extents--;
memmove(extent_nis, extent_nis + 1, (base_ni->nr_extents - i) *
sizeof(ntfs_inode*));
err = 0;
break;
}
mutex_unlock(&base_ni->extent_lock);
if (unlikely(err)) {
ntfs_error(vol->sb, "Extent inode 0x%lx is not attached to "
"its base inode 0x%lx.", mft_no,
base_ni->mft_no);
BUG();
}
/*
* The extent inode is no longer attached to the base inode so no one
* can get a reference to it any more.
*/
/* Mark the mft record as not in use. */
m->flags &= ~MFT_RECORD_IN_USE;
/* Increment the sequence number, skipping zero, if it is not zero. */
old_seq_no = m->sequence_number;
seq_no = le16_to_cpu(old_seq_no);
if (seq_no == 0xffff)
seq_no = 1;
else if (seq_no)
seq_no++;
m->sequence_number = cpu_to_le16(seq_no);
/*
* Set the ntfs inode dirty and write it out. We do not need to worry
* about the base inode here since whatever caused the extent mft
* record to be freed is guaranteed to do it already.
*/
NInoSetDirty(ni);
err = write_mft_record(ni, m, 0);
if (unlikely(err)) {
ntfs_error(vol->sb, "Failed to write mft record 0x%lx, not "
"freeing.", mft_no);
goto rollback;
}
rollback_error:
/* Unmap and throw away the now freed extent inode. */
unmap_extent_mft_record(ni);
ntfs_clear_extent_inode(ni);
/* Clear the bit in the $MFT/$BITMAP corresponding to this record. */
down_write(&vol->mftbmp_lock);
err = ntfs_bitmap_clear_bit(vol->mftbmp_ino, mft_no);
up_write(&vol->mftbmp_lock);
if (unlikely(err)) {
/*
* The extent inode is gone but we failed to deallocate it in
* the mft bitmap. Just emit a warning and leave the volume
* dirty on umount.
*/
ntfs_error(vol->sb, "Failed to clear bit in mft bitmap.%s", es);
NVolSetErrors(vol);
}
return 0;
rollback:
/* Rollback what we did... */
mutex_lock(&base_ni->extent_lock);
extent_nis = base_ni->ext.extent_ntfs_inos;
if (!(base_ni->nr_extents & 3)) {
int new_size = (base_ni->nr_extents + 4) * sizeof(ntfs_inode*);
extent_nis = kmalloc(new_size, GFP_NOFS);
if (unlikely(!extent_nis)) {
ntfs_error(vol->sb, "Failed to allocate internal "
"buffer during rollback.%s", es);
mutex_unlock(&base_ni->extent_lock);
NVolSetErrors(vol);
goto rollback_error;
}
if (base_ni->nr_extents) {
BUG_ON(!base_ni->ext.extent_ntfs_inos);
memcpy(extent_nis, base_ni->ext.extent_ntfs_inos,
new_size - 4 * sizeof(ntfs_inode*));
kfree(base_ni->ext.extent_ntfs_inos);
}
base_ni->ext.extent_ntfs_inos = extent_nis;
}
m->flags |= MFT_RECORD_IN_USE;
m->sequence_number = old_seq_no;
extent_nis[base_ni->nr_extents++] = ni;
mutex_unlock(&base_ni->extent_lock);
mark_mft_record_dirty(ni);
return err;
}
#endif /* NTFS_RW */
| gpl-2.0 |
dh-harald/amlogic-kernel | drivers/scsi/bnx2i/bnx2i_hwi.c | 944 | 80020 | /* bnx2i_hwi.c: Broadcom NetXtreme II iSCSI driver.
*
* Copyright (c) 2006 - 2010 Broadcom Corporation
* Copyright (c) 2007, 2008 Red Hat, Inc. All rights reserved.
* Copyright (c) 2007, 2008 Mike Christie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Written by: Anil Veerabhadrappa (anilgv@broadcom.com)
* Maintained by: Eddie Wai (eddie.wai@broadcom.com)
*/
#include <linux/gfp.h>
#include <scsi/scsi_tcq.h>
#include <scsi/libiscsi.h>
#include "bnx2i.h"
/**
* bnx2i_get_cid_num - get cid from ep
* @ep: endpoint pointer
*
* Only applicable to 57710 family of devices
*/
static u32 bnx2i_get_cid_num(struct bnx2i_endpoint *ep)
{
u32 cid;
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type))
cid = ep->ep_cid;
else
cid = GET_CID_NUM(ep->ep_cid);
return cid;
}
/**
* bnx2i_adjust_qp_size - Adjust SQ/RQ/CQ size for 57710 device type
* @hba: Adapter for which adjustments is to be made
*
* Only applicable to 57710 family of devices
*/
static void bnx2i_adjust_qp_size(struct bnx2i_hba *hba)
{
u32 num_elements_per_pg;
if (test_bit(BNX2I_NX2_DEV_5706, &hba->cnic_dev_type) ||
test_bit(BNX2I_NX2_DEV_5708, &hba->cnic_dev_type) ||
test_bit(BNX2I_NX2_DEV_5709, &hba->cnic_dev_type)) {
if (!is_power_of_2(hba->max_sqes))
hba->max_sqes = rounddown_pow_of_two(hba->max_sqes);
if (!is_power_of_2(hba->max_rqes))
hba->max_rqes = rounddown_pow_of_two(hba->max_rqes);
}
/* Adjust each queue size if the user selection does not
* yield integral num of page buffers
*/
/* adjust SQ */
num_elements_per_pg = PAGE_SIZE / BNX2I_SQ_WQE_SIZE;
if (hba->max_sqes < num_elements_per_pg)
hba->max_sqes = num_elements_per_pg;
else if (hba->max_sqes % num_elements_per_pg)
hba->max_sqes = (hba->max_sqes + num_elements_per_pg - 1) &
~(num_elements_per_pg - 1);
/* adjust CQ */
num_elements_per_pg = PAGE_SIZE / BNX2I_CQE_SIZE;
if (hba->max_cqes < num_elements_per_pg)
hba->max_cqes = num_elements_per_pg;
else if (hba->max_cqes % num_elements_per_pg)
hba->max_cqes = (hba->max_cqes + num_elements_per_pg - 1) &
~(num_elements_per_pg - 1);
/* adjust RQ */
num_elements_per_pg = PAGE_SIZE / BNX2I_RQ_WQE_SIZE;
if (hba->max_rqes < num_elements_per_pg)
hba->max_rqes = num_elements_per_pg;
else if (hba->max_rqes % num_elements_per_pg)
hba->max_rqes = (hba->max_rqes + num_elements_per_pg - 1) &
~(num_elements_per_pg - 1);
}
/**
* bnx2i_get_link_state - get network interface link state
* @hba: adapter instance pointer
*
* updates adapter structure flag based on netdev state
*/
static void bnx2i_get_link_state(struct bnx2i_hba *hba)
{
if (test_bit(__LINK_STATE_NOCARRIER, &hba->netdev->state))
set_bit(ADAPTER_STATE_LINK_DOWN, &hba->adapter_state);
else
clear_bit(ADAPTER_STATE_LINK_DOWN, &hba->adapter_state);
}
/**
* bnx2i_iscsi_license_error - displays iscsi license related error message
* @hba: adapter instance pointer
* @error_code: error classification
*
* Puts out an error log when driver is unable to offload iscsi connection
* due to license restrictions
*/
static void bnx2i_iscsi_license_error(struct bnx2i_hba *hba, u32 error_code)
{
if (error_code == ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED)
/* iSCSI offload not supported on this device */
printk(KERN_ERR "bnx2i: iSCSI not supported, dev=%s\n",
hba->netdev->name);
if (error_code == ISCSI_KCQE_COMPLETION_STATUS_LOM_ISCSI_NOT_ENABLED)
/* iSCSI offload not supported on this LOM device */
printk(KERN_ERR "bnx2i: LOM is not enable to "
"offload iSCSI connections, dev=%s\n",
hba->netdev->name);
set_bit(ADAPTER_STATE_INIT_FAILED, &hba->adapter_state);
}
/**
* bnx2i_arm_cq_event_coalescing - arms CQ to enable EQ notification
* @ep: endpoint (transport indentifier) structure
* @action: action, ARM or DISARM. For now only ARM_CQE is used
*
* Arm'ing CQ will enable chip to generate global EQ events inorder to interrupt
* the driver. EQ event is generated CQ index is hit or at least 1 CQ is
* outstanding and on chip timer expires
*/
void bnx2i_arm_cq_event_coalescing(struct bnx2i_endpoint *ep, u8 action)
{
struct bnx2i_5771x_cq_db *cq_db;
u16 cq_index;
u16 next_index;
u32 num_active_cmds;
/* Coalesce CQ entries only on 10G devices */
if (!test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type))
return;
/* Do not update CQ DB multiple times before firmware writes
* '0xFFFF' to CQDB->SQN field. Deviation may cause spurious
* interrupts and other unwanted results
*/
cq_db = (struct bnx2i_5771x_cq_db *) ep->qp.cq_pgtbl_virt;
if (action != CNIC_ARM_CQE_FP)
if (cq_db->sqn[0] && cq_db->sqn[0] != 0xFFFF)
return;
if (action == CNIC_ARM_CQE || action == CNIC_ARM_CQE_FP) {
num_active_cmds = ep->num_active_cmds;
if (num_active_cmds <= event_coal_min)
next_index = 1;
else
next_index = event_coal_min +
((num_active_cmds - event_coal_min) >>
ep->ec_shift);
if (!next_index)
next_index = 1;
cq_index = ep->qp.cqe_exp_seq_sn + next_index - 1;
if (cq_index > ep->qp.cqe_size * 2)
cq_index -= ep->qp.cqe_size * 2;
if (!cq_index)
cq_index = 1;
cq_db->sqn[0] = cq_index;
}
}
/**
* bnx2i_get_rq_buf - copy RQ buffer contents to driver buffer
* @conn: iscsi connection on which RQ event occurred
* @ptr: driver buffer to which RQ buffer contents is to
* be copied
* @len: length of valid data inside RQ buf
*
* Copies RQ buffer contents from shared (DMA'able) memory region to
* driver buffer. RQ is used to DMA unsolicitated iscsi pdu's and
* scsi sense info
*/
void bnx2i_get_rq_buf(struct bnx2i_conn *bnx2i_conn, char *ptr, int len)
{
if (!bnx2i_conn->ep->qp.rqe_left)
return;
bnx2i_conn->ep->qp.rqe_left--;
memcpy(ptr, (u8 *) bnx2i_conn->ep->qp.rq_cons_qe, len);
if (bnx2i_conn->ep->qp.rq_cons_qe == bnx2i_conn->ep->qp.rq_last_qe) {
bnx2i_conn->ep->qp.rq_cons_qe = bnx2i_conn->ep->qp.rq_first_qe;
bnx2i_conn->ep->qp.rq_cons_idx = 0;
} else {
bnx2i_conn->ep->qp.rq_cons_qe++;
bnx2i_conn->ep->qp.rq_cons_idx++;
}
}
static void bnx2i_ring_577xx_doorbell(struct bnx2i_conn *conn)
{
struct bnx2i_5771x_dbell dbell;
u32 msg;
memset(&dbell, 0, sizeof(dbell));
dbell.dbell.header = (B577XX_ISCSI_CONNECTION_TYPE <<
B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT);
msg = *((u32 *)&dbell);
/* TODO : get doorbell register mapping */
writel(cpu_to_le32(msg), conn->ep->qp.ctx_base);
}
/**
* bnx2i_put_rq_buf - Replenish RQ buffer, if required ring on chip doorbell
* @conn: iscsi connection on which event to post
* @count: number of RQ buffer being posted to chip
*
* No need to ring hardware doorbell for 57710 family of devices
*/
void bnx2i_put_rq_buf(struct bnx2i_conn *bnx2i_conn, int count)
{
struct bnx2i_5771x_sq_rq_db *rq_db;
u16 hi_bit = (bnx2i_conn->ep->qp.rq_prod_idx & 0x8000);
struct bnx2i_endpoint *ep = bnx2i_conn->ep;
ep->qp.rqe_left += count;
ep->qp.rq_prod_idx &= 0x7FFF;
ep->qp.rq_prod_idx += count;
if (ep->qp.rq_prod_idx > bnx2i_conn->hba->max_rqes) {
ep->qp.rq_prod_idx %= bnx2i_conn->hba->max_rqes;
if (!hi_bit)
ep->qp.rq_prod_idx |= 0x8000;
} else
ep->qp.rq_prod_idx |= hi_bit;
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) {
rq_db = (struct bnx2i_5771x_sq_rq_db *) ep->qp.rq_pgtbl_virt;
rq_db->prod_idx = ep->qp.rq_prod_idx;
/* no need to ring hardware doorbell for 57710 */
} else {
writew(ep->qp.rq_prod_idx,
ep->qp.ctx_base + CNIC_RECV_DOORBELL);
}
mmiowb();
}
/**
* bnx2i_ring_sq_dbell - Ring SQ doorbell to wake-up the processing engine
* @conn: iscsi connection to which new SQ entries belong
* @count: number of SQ WQEs to post
*
* SQ DB is updated in host memory and TX Doorbell is rung for 57710 family
* of devices. For 5706/5708/5709 new SQ WQE count is written into the
* doorbell register
*/
static void bnx2i_ring_sq_dbell(struct bnx2i_conn *bnx2i_conn, int count)
{
struct bnx2i_5771x_sq_rq_db *sq_db;
struct bnx2i_endpoint *ep = bnx2i_conn->ep;
ep->num_active_cmds++;
wmb(); /* flush SQ WQE memory before the doorbell is rung */
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) {
sq_db = (struct bnx2i_5771x_sq_rq_db *) ep->qp.sq_pgtbl_virt;
sq_db->prod_idx = ep->qp.sq_prod_idx;
bnx2i_ring_577xx_doorbell(bnx2i_conn);
} else
writew(count, ep->qp.ctx_base + CNIC_SEND_DOORBELL);
mmiowb(); /* flush posted PCI writes */
}
/**
* bnx2i_ring_dbell_update_sq_params - update SQ driver parameters
* @conn: iscsi connection to which new SQ entries belong
* @count: number of SQ WQEs to post
*
* this routine will update SQ driver parameters and ring the doorbell
*/
static void bnx2i_ring_dbell_update_sq_params(struct bnx2i_conn *bnx2i_conn,
int count)
{
int tmp_cnt;
if (count == 1) {
if (bnx2i_conn->ep->qp.sq_prod_qe ==
bnx2i_conn->ep->qp.sq_last_qe)
bnx2i_conn->ep->qp.sq_prod_qe =
bnx2i_conn->ep->qp.sq_first_qe;
else
bnx2i_conn->ep->qp.sq_prod_qe++;
} else {
if ((bnx2i_conn->ep->qp.sq_prod_qe + count) <=
bnx2i_conn->ep->qp.sq_last_qe)
bnx2i_conn->ep->qp.sq_prod_qe += count;
else {
tmp_cnt = bnx2i_conn->ep->qp.sq_last_qe -
bnx2i_conn->ep->qp.sq_prod_qe;
bnx2i_conn->ep->qp.sq_prod_qe =
&bnx2i_conn->ep->qp.sq_first_qe[count -
(tmp_cnt + 1)];
}
}
bnx2i_conn->ep->qp.sq_prod_idx += count;
/* Ring the doorbell */
bnx2i_ring_sq_dbell(bnx2i_conn, bnx2i_conn->ep->qp.sq_prod_idx);
}
/**
* bnx2i_send_iscsi_login - post iSCSI login request MP WQE to hardware
* @conn: iscsi connection
* @cmd: driver command structure which is requesting
* a WQE to sent to chip for further processing
*
* prepare and post an iSCSI Login request WQE to CNIC firmware
*/
int bnx2i_send_iscsi_login(struct bnx2i_conn *bnx2i_conn,
struct iscsi_task *task)
{
struct bnx2i_cmd *bnx2i_cmd;
struct bnx2i_login_request *login_wqe;
struct iscsi_login *login_hdr;
u32 dword;
bnx2i_cmd = (struct bnx2i_cmd *)task->dd_data;
login_hdr = (struct iscsi_login *)task->hdr;
login_wqe = (struct bnx2i_login_request *)
bnx2i_conn->ep->qp.sq_prod_qe;
login_wqe->op_code = login_hdr->opcode;
login_wqe->op_attr = login_hdr->flags;
login_wqe->version_max = login_hdr->max_version;
login_wqe->version_min = login_hdr->min_version;
login_wqe->data_length = ntoh24(login_hdr->dlength);
login_wqe->isid_lo = *((u32 *) login_hdr->isid);
login_wqe->isid_hi = *((u16 *) login_hdr->isid + 2);
login_wqe->tsih = login_hdr->tsih;
login_wqe->itt = task->itt |
(ISCSI_TASK_TYPE_MPATH << ISCSI_LOGIN_REQUEST_TYPE_SHIFT);
login_wqe->cid = login_hdr->cid;
login_wqe->cmd_sn = be32_to_cpu(login_hdr->cmdsn);
login_wqe->exp_stat_sn = be32_to_cpu(login_hdr->exp_statsn);
login_wqe->flags = ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN;
login_wqe->resp_bd_list_addr_lo = (u32) bnx2i_conn->gen_pdu.resp_bd_dma;
login_wqe->resp_bd_list_addr_hi =
(u32) ((u64) bnx2i_conn->gen_pdu.resp_bd_dma >> 32);
dword = ((1 << ISCSI_LOGIN_REQUEST_NUM_RESP_BDS_SHIFT) |
(bnx2i_conn->gen_pdu.resp_buf_size <<
ISCSI_LOGIN_REQUEST_RESP_BUFFER_LENGTH_SHIFT));
login_wqe->resp_buffer = dword;
login_wqe->bd_list_addr_lo = (u32) bnx2i_conn->gen_pdu.req_bd_dma;
login_wqe->bd_list_addr_hi =
(u32) ((u64) bnx2i_conn->gen_pdu.req_bd_dma >> 32);
login_wqe->num_bds = 1;
login_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_ring_dbell_update_sq_params(bnx2i_conn, 1);
return 0;
}
/**
* bnx2i_send_iscsi_tmf - post iSCSI task management request MP WQE to hardware
* @conn: iscsi connection
* @mtask: driver command structure which is requesting
* a WQE to sent to chip for further processing
*
* prepare and post an iSCSI Login request WQE to CNIC firmware
*/
int bnx2i_send_iscsi_tmf(struct bnx2i_conn *bnx2i_conn,
struct iscsi_task *mtask)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_tm *tmfabort_hdr;
struct scsi_cmnd *ref_sc;
struct iscsi_task *ctask;
struct bnx2i_cmd *bnx2i_cmd;
struct bnx2i_tmf_request *tmfabort_wqe;
u32 dword;
u32 scsi_lun[2];
bnx2i_cmd = (struct bnx2i_cmd *)mtask->dd_data;
tmfabort_hdr = (struct iscsi_tm *)mtask->hdr;
tmfabort_wqe = (struct bnx2i_tmf_request *)
bnx2i_conn->ep->qp.sq_prod_qe;
tmfabort_wqe->op_code = tmfabort_hdr->opcode;
tmfabort_wqe->op_attr = tmfabort_hdr->flags;
tmfabort_wqe->itt = (mtask->itt | (ISCSI_TASK_TYPE_MPATH << 14));
tmfabort_wqe->reserved2 = 0;
tmfabort_wqe->cmd_sn = be32_to_cpu(tmfabort_hdr->cmdsn);
switch (tmfabort_hdr->flags & ISCSI_FLAG_TM_FUNC_MASK) {
case ISCSI_TM_FUNC_ABORT_TASK:
case ISCSI_TM_FUNC_TASK_REASSIGN:
ctask = iscsi_itt_to_task(conn, tmfabort_hdr->rtt);
if (!ctask || !ctask->sc)
/*
* the iscsi layer must have completed the cmd while
* was starting up.
*
* Note: In the case of a SCSI cmd timeout, the task's
* sc is still active; hence ctask->sc != 0
* In this case, the task must be aborted
*/
return 0;
ref_sc = ctask->sc;
if (ref_sc->sc_data_direction == DMA_TO_DEVICE)
dword = (ISCSI_TASK_TYPE_WRITE <<
ISCSI_CMD_REQUEST_TYPE_SHIFT);
else
dword = (ISCSI_TASK_TYPE_READ <<
ISCSI_CMD_REQUEST_TYPE_SHIFT);
tmfabort_wqe->ref_itt = (dword |
(tmfabort_hdr->rtt & ISCSI_ITT_MASK));
break;
default:
tmfabort_wqe->ref_itt = RESERVED_ITT;
}
memcpy(scsi_lun, tmfabort_hdr->lun, sizeof(struct scsi_lun));
tmfabort_wqe->lun[0] = be32_to_cpu(scsi_lun[0]);
tmfabort_wqe->lun[1] = be32_to_cpu(scsi_lun[1]);
tmfabort_wqe->ref_cmd_sn = be32_to_cpu(tmfabort_hdr->refcmdsn);
tmfabort_wqe->bd_list_addr_lo = (u32) bnx2i_conn->hba->mp_bd_dma;
tmfabort_wqe->bd_list_addr_hi = (u32)
((u64) bnx2i_conn->hba->mp_bd_dma >> 32);
tmfabort_wqe->num_bds = 1;
tmfabort_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_ring_dbell_update_sq_params(bnx2i_conn, 1);
return 0;
}
/**
* bnx2i_send_iscsi_text - post iSCSI text WQE to hardware
* @conn: iscsi connection
* @mtask: driver command structure which is requesting
* a WQE to sent to chip for further processing
*
* prepare and post an iSCSI Text request WQE to CNIC firmware
*/
int bnx2i_send_iscsi_text(struct bnx2i_conn *bnx2i_conn,
struct iscsi_task *mtask)
{
struct bnx2i_cmd *bnx2i_cmd;
struct bnx2i_text_request *text_wqe;
struct iscsi_text *text_hdr;
u32 dword;
bnx2i_cmd = (struct bnx2i_cmd *)mtask->dd_data;
text_hdr = (struct iscsi_text *)mtask->hdr;
text_wqe = (struct bnx2i_text_request *) bnx2i_conn->ep->qp.sq_prod_qe;
memset(text_wqe, 0, sizeof(struct bnx2i_text_request));
text_wqe->op_code = text_hdr->opcode;
text_wqe->op_attr = text_hdr->flags;
text_wqe->data_length = ntoh24(text_hdr->dlength);
text_wqe->itt = mtask->itt |
(ISCSI_TASK_TYPE_MPATH << ISCSI_TEXT_REQUEST_TYPE_SHIFT);
text_wqe->ttt = be32_to_cpu(text_hdr->ttt);
text_wqe->cmd_sn = be32_to_cpu(text_hdr->cmdsn);
text_wqe->resp_bd_list_addr_lo = (u32) bnx2i_conn->gen_pdu.resp_bd_dma;
text_wqe->resp_bd_list_addr_hi =
(u32) ((u64) bnx2i_conn->gen_pdu.resp_bd_dma >> 32);
dword = ((1 << ISCSI_TEXT_REQUEST_NUM_RESP_BDS_SHIFT) |
(bnx2i_conn->gen_pdu.resp_buf_size <<
ISCSI_TEXT_REQUEST_RESP_BUFFER_LENGTH_SHIFT));
text_wqe->resp_buffer = dword;
text_wqe->bd_list_addr_lo = (u32) bnx2i_conn->gen_pdu.req_bd_dma;
text_wqe->bd_list_addr_hi =
(u32) ((u64) bnx2i_conn->gen_pdu.req_bd_dma >> 32);
text_wqe->num_bds = 1;
text_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_ring_dbell_update_sq_params(bnx2i_conn, 1);
return 0;
}
/**
* bnx2i_send_iscsi_scsicmd - post iSCSI scsicmd request WQE to hardware
* @conn: iscsi connection
* @cmd: driver command structure which is requesting
* a WQE to sent to chip for further processing
*
* prepare and post an iSCSI SCSI-CMD request WQE to CNIC firmware
*/
int bnx2i_send_iscsi_scsicmd(struct bnx2i_conn *bnx2i_conn,
struct bnx2i_cmd *cmd)
{
struct bnx2i_cmd_request *scsi_cmd_wqe;
scsi_cmd_wqe = (struct bnx2i_cmd_request *)
bnx2i_conn->ep->qp.sq_prod_qe;
memcpy(scsi_cmd_wqe, &cmd->req, sizeof(struct bnx2i_cmd_request));
scsi_cmd_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_ring_dbell_update_sq_params(bnx2i_conn, 1);
return 0;
}
/**
* bnx2i_send_iscsi_nopout - post iSCSI NOPOUT request WQE to hardware
* @conn: iscsi connection
* @cmd: driver command structure which is requesting
* a WQE to sent to chip for further processing
* @datap: payload buffer pointer
* @data_len: payload data length
* @unsol: indicated whether nopout pdu is unsolicited pdu or
* in response to target's NOPIN w/ TTT != FFFFFFFF
*
* prepare and post a nopout request WQE to CNIC firmware
*/
int bnx2i_send_iscsi_nopout(struct bnx2i_conn *bnx2i_conn,
struct iscsi_task *task,
char *datap, int data_len, int unsol)
{
struct bnx2i_endpoint *ep = bnx2i_conn->ep;
struct bnx2i_cmd *bnx2i_cmd;
struct bnx2i_nop_out_request *nopout_wqe;
struct iscsi_nopout *nopout_hdr;
bnx2i_cmd = (struct bnx2i_cmd *)task->dd_data;
nopout_hdr = (struct iscsi_nopout *)task->hdr;
nopout_wqe = (struct bnx2i_nop_out_request *)ep->qp.sq_prod_qe;
memset(nopout_wqe, 0x00, sizeof(struct bnx2i_nop_out_request));
nopout_wqe->op_code = nopout_hdr->opcode;
nopout_wqe->op_attr = ISCSI_FLAG_CMD_FINAL;
memcpy(nopout_wqe->lun, nopout_hdr->lun, 8);
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) {
u32 tmp = nopout_wqe->lun[0];
/* 57710 requires LUN field to be swapped */
nopout_wqe->lun[0] = nopout_wqe->lun[1];
nopout_wqe->lun[1] = tmp;
}
nopout_wqe->itt = ((u16)task->itt |
(ISCSI_TASK_TYPE_MPATH <<
ISCSI_TMF_REQUEST_TYPE_SHIFT));
nopout_wqe->ttt = nopout_hdr->ttt;
nopout_wqe->flags = 0;
if (!unsol)
nopout_wqe->flags = ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION;
else if (nopout_hdr->itt == RESERVED_ITT)
nopout_wqe->flags = ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION;
nopout_wqe->cmd_sn = be32_to_cpu(nopout_hdr->cmdsn);
nopout_wqe->data_length = data_len;
if (data_len) {
/* handle payload data, not required in first release */
printk(KERN_ALERT "NOPOUT: WARNING!! payload len != 0\n");
} else {
nopout_wqe->bd_list_addr_lo = (u32)
bnx2i_conn->hba->mp_bd_dma;
nopout_wqe->bd_list_addr_hi =
(u32) ((u64) bnx2i_conn->hba->mp_bd_dma >> 32);
nopout_wqe->num_bds = 1;
}
nopout_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_ring_dbell_update_sq_params(bnx2i_conn, 1);
return 0;
}
/**
* bnx2i_send_iscsi_logout - post iSCSI logout request WQE to hardware
* @conn: iscsi connection
* @cmd: driver command structure which is requesting
* a WQE to sent to chip for further processing
*
* prepare and post logout request WQE to CNIC firmware
*/
int bnx2i_send_iscsi_logout(struct bnx2i_conn *bnx2i_conn,
struct iscsi_task *task)
{
struct bnx2i_cmd *bnx2i_cmd;
struct bnx2i_logout_request *logout_wqe;
struct iscsi_logout *logout_hdr;
bnx2i_cmd = (struct bnx2i_cmd *)task->dd_data;
logout_hdr = (struct iscsi_logout *)task->hdr;
logout_wqe = (struct bnx2i_logout_request *)
bnx2i_conn->ep->qp.sq_prod_qe;
memset(logout_wqe, 0x00, sizeof(struct bnx2i_logout_request));
logout_wqe->op_code = logout_hdr->opcode;
logout_wqe->cmd_sn = be32_to_cpu(logout_hdr->cmdsn);
logout_wqe->op_attr =
logout_hdr->flags | ISCSI_LOGOUT_REQUEST_ALWAYS_ONE;
logout_wqe->itt = ((u16)task->itt |
(ISCSI_TASK_TYPE_MPATH <<
ISCSI_LOGOUT_REQUEST_TYPE_SHIFT));
logout_wqe->data_length = 0;
logout_wqe->cid = 0;
logout_wqe->bd_list_addr_lo = (u32) bnx2i_conn->hba->mp_bd_dma;
logout_wqe->bd_list_addr_hi = (u32)
((u64) bnx2i_conn->hba->mp_bd_dma >> 32);
logout_wqe->num_bds = 1;
logout_wqe->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_conn->ep->state = EP_STATE_LOGOUT_SENT;
bnx2i_ring_dbell_update_sq_params(bnx2i_conn, 1);
return 0;
}
/**
* bnx2i_update_iscsi_conn - post iSCSI logout request WQE to hardware
* @conn: iscsi connection which requires iscsi parameter update
*
* sends down iSCSI Conn Update request to move iSCSI conn to FFP
*/
void bnx2i_update_iscsi_conn(struct iscsi_conn *conn)
{
struct bnx2i_conn *bnx2i_conn = conn->dd_data;
struct bnx2i_hba *hba = bnx2i_conn->hba;
struct kwqe *kwqe_arr[2];
struct iscsi_kwqe_conn_update *update_wqe;
struct iscsi_kwqe_conn_update conn_update_kwqe;
update_wqe = &conn_update_kwqe;
update_wqe->hdr.op_code = ISCSI_KWQE_OPCODE_UPDATE_CONN;
update_wqe->hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
/* 5771x requires conn context id to be passed as is */
if (test_bit(BNX2I_NX2_DEV_57710, &bnx2i_conn->ep->hba->cnic_dev_type))
update_wqe->context_id = bnx2i_conn->ep->ep_cid;
else
update_wqe->context_id = (bnx2i_conn->ep->ep_cid >> 7);
update_wqe->conn_flags = 0;
if (conn->hdrdgst_en)
update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST;
if (conn->datadgst_en)
update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST;
if (conn->session->initial_r2t_en)
update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T;
if (conn->session->imm_data_en)
update_wqe->conn_flags |= ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA;
update_wqe->max_send_pdu_length = conn->max_xmit_dlength;
update_wqe->max_recv_pdu_length = conn->max_recv_dlength;
update_wqe->first_burst_length = conn->session->first_burst;
update_wqe->max_burst_length = conn->session->max_burst;
update_wqe->exp_stat_sn = conn->exp_statsn;
update_wqe->max_outstanding_r2ts = conn->session->max_r2t;
update_wqe->session_error_recovery_level = conn->session->erl;
iscsi_conn_printk(KERN_ALERT, conn,
"bnx2i: conn update - MBL 0x%x FBL 0x%x"
"MRDSL_I 0x%x MRDSL_T 0x%x \n",
update_wqe->max_burst_length,
update_wqe->first_burst_length,
update_wqe->max_recv_pdu_length,
update_wqe->max_send_pdu_length);
kwqe_arr[0] = (struct kwqe *) update_wqe;
if (hba->cnic && hba->cnic->submit_kwqes)
hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, 1);
}
/**
* bnx2i_ep_ofld_timer - post iSCSI logout request WQE to hardware
* @data: endpoint (transport handle) structure pointer
*
* routine to handle connection offload/destroy request timeout
*/
void bnx2i_ep_ofld_timer(unsigned long data)
{
struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) data;
if (ep->state == EP_STATE_OFLD_START) {
printk(KERN_ALERT "ofld_timer: CONN_OFLD timeout\n");
ep->state = EP_STATE_OFLD_FAILED;
} else if (ep->state == EP_STATE_DISCONN_START) {
printk(KERN_ALERT "ofld_timer: CONN_DISCON timeout\n");
ep->state = EP_STATE_DISCONN_TIMEDOUT;
} else if (ep->state == EP_STATE_CLEANUP_START) {
printk(KERN_ALERT "ofld_timer: CONN_CLEANUP timeout\n");
ep->state = EP_STATE_CLEANUP_FAILED;
}
wake_up_interruptible(&ep->ofld_wait);
}
static int bnx2i_power_of2(u32 val)
{
u32 power = 0;
if (val & (val - 1))
return power;
val--;
while (val) {
val = val >> 1;
power++;
}
return power;
}
/**
* bnx2i_send_cmd_cleanup_req - send iscsi cmd context clean-up request
* @hba: adapter structure pointer
* @cmd: driver command structure which is requesting
* a WQE to sent to chip for further processing
*
* prepares and posts CONN_OFLD_REQ1/2 KWQE
*/
void bnx2i_send_cmd_cleanup_req(struct bnx2i_hba *hba, struct bnx2i_cmd *cmd)
{
struct bnx2i_cleanup_request *cmd_cleanup;
cmd_cleanup =
(struct bnx2i_cleanup_request *)cmd->conn->ep->qp.sq_prod_qe;
memset(cmd_cleanup, 0x00, sizeof(struct bnx2i_cleanup_request));
cmd_cleanup->op_code = ISCSI_OPCODE_CLEANUP_REQUEST;
cmd_cleanup->itt = cmd->req.itt;
cmd_cleanup->cq_index = 0; /* CQ# used for completion, 5771x only */
bnx2i_ring_dbell_update_sq_params(cmd->conn, 1);
}
/**
* bnx2i_send_conn_destroy - initiates iscsi connection teardown process
* @hba: adapter structure pointer
* @ep: endpoint (transport indentifier) structure
*
* this routine prepares and posts CONN_OFLD_REQ1/2 KWQE to initiate
* iscsi connection context clean-up process
*/
int bnx2i_send_conn_destroy(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep)
{
struct kwqe *kwqe_arr[2];
struct iscsi_kwqe_conn_destroy conn_cleanup;
int rc = -EINVAL;
memset(&conn_cleanup, 0x00, sizeof(struct iscsi_kwqe_conn_destroy));
conn_cleanup.hdr.op_code = ISCSI_KWQE_OPCODE_DESTROY_CONN;
conn_cleanup.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
/* 5771x requires conn context id to be passed as is */
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type))
conn_cleanup.context_id = ep->ep_cid;
else
conn_cleanup.context_id = (ep->ep_cid >> 7);
conn_cleanup.reserved0 = (u16)ep->ep_iscsi_cid;
kwqe_arr[0] = (struct kwqe *) &conn_cleanup;
if (hba->cnic && hba->cnic->submit_kwqes)
rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, 1);
return rc;
}
/**
* bnx2i_570x_send_conn_ofld_req - initiates iscsi conn context setup process
* @hba: adapter structure pointer
* @ep: endpoint (transport indentifier) structure
*
* 5706/5708/5709 specific - prepares and posts CONN_OFLD_REQ1/2 KWQE
*/
static int bnx2i_570x_send_conn_ofld_req(struct bnx2i_hba *hba,
struct bnx2i_endpoint *ep)
{
struct kwqe *kwqe_arr[2];
struct iscsi_kwqe_conn_offload1 ofld_req1;
struct iscsi_kwqe_conn_offload2 ofld_req2;
dma_addr_t dma_addr;
int num_kwqes = 2;
u32 *ptbl;
int rc = -EINVAL;
ofld_req1.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN1;
ofld_req1.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
ofld_req1.iscsi_conn_id = (u16) ep->ep_iscsi_cid;
dma_addr = ep->qp.sq_pgtbl_phys;
ofld_req1.sq_page_table_addr_lo = (u32) dma_addr;
ofld_req1.sq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32);
dma_addr = ep->qp.cq_pgtbl_phys;
ofld_req1.cq_page_table_addr_lo = (u32) dma_addr;
ofld_req1.cq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32);
ofld_req2.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN2;
ofld_req2.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
dma_addr = ep->qp.rq_pgtbl_phys;
ofld_req2.rq_page_table_addr_lo = (u32) dma_addr;
ofld_req2.rq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32);
ptbl = (u32 *) ep->qp.sq_pgtbl_virt;
ofld_req2.sq_first_pte.hi = *ptbl++;
ofld_req2.sq_first_pte.lo = *ptbl;
ptbl = (u32 *) ep->qp.cq_pgtbl_virt;
ofld_req2.cq_first_pte.hi = *ptbl++;
ofld_req2.cq_first_pte.lo = *ptbl;
kwqe_arr[0] = (struct kwqe *) &ofld_req1;
kwqe_arr[1] = (struct kwqe *) &ofld_req2;
ofld_req2.num_additional_wqes = 0;
if (hba->cnic && hba->cnic->submit_kwqes)
rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
return rc;
}
/**
* bnx2i_5771x_send_conn_ofld_req - initiates iscsi connection context creation
* @hba: adapter structure pointer
* @ep: endpoint (transport indentifier) structure
*
* 57710 specific - prepares and posts CONN_OFLD_REQ1/2 KWQE
*/
static int bnx2i_5771x_send_conn_ofld_req(struct bnx2i_hba *hba,
struct bnx2i_endpoint *ep)
{
struct kwqe *kwqe_arr[5];
struct iscsi_kwqe_conn_offload1 ofld_req1;
struct iscsi_kwqe_conn_offload2 ofld_req2;
struct iscsi_kwqe_conn_offload3 ofld_req3[1];
dma_addr_t dma_addr;
int num_kwqes = 2;
u32 *ptbl;
int rc = -EINVAL;
ofld_req1.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN1;
ofld_req1.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
ofld_req1.iscsi_conn_id = (u16) ep->ep_iscsi_cid;
dma_addr = ep->qp.sq_pgtbl_phys + ISCSI_SQ_DB_SIZE;
ofld_req1.sq_page_table_addr_lo = (u32) dma_addr;
ofld_req1.sq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32);
dma_addr = ep->qp.cq_pgtbl_phys + ISCSI_CQ_DB_SIZE;
ofld_req1.cq_page_table_addr_lo = (u32) dma_addr;
ofld_req1.cq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32);
ofld_req2.hdr.op_code = ISCSI_KWQE_OPCODE_OFFLOAD_CONN2;
ofld_req2.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
dma_addr = ep->qp.rq_pgtbl_phys + ISCSI_RQ_DB_SIZE;
ofld_req2.rq_page_table_addr_lo = (u32) dma_addr;
ofld_req2.rq_page_table_addr_hi = (u32) ((u64) dma_addr >> 32);
ptbl = (u32 *)((u8 *)ep->qp.sq_pgtbl_virt + ISCSI_SQ_DB_SIZE);
ofld_req2.sq_first_pte.hi = *ptbl++;
ofld_req2.sq_first_pte.lo = *ptbl;
ptbl = (u32 *)((u8 *)ep->qp.cq_pgtbl_virt + ISCSI_CQ_DB_SIZE);
ofld_req2.cq_first_pte.hi = *ptbl++;
ofld_req2.cq_first_pte.lo = *ptbl;
kwqe_arr[0] = (struct kwqe *) &ofld_req1;
kwqe_arr[1] = (struct kwqe *) &ofld_req2;
ofld_req2.num_additional_wqes = 1;
memset(ofld_req3, 0x00, sizeof(ofld_req3[0]));
ptbl = (u32 *)((u8 *)ep->qp.rq_pgtbl_virt + ISCSI_RQ_DB_SIZE);
ofld_req3[0].qp_first_pte[0].hi = *ptbl++;
ofld_req3[0].qp_first_pte[0].lo = *ptbl;
kwqe_arr[2] = (struct kwqe *) ofld_req3;
/* need if we decide to go with multiple KCQE's per conn */
num_kwqes += 1;
if (hba->cnic && hba->cnic->submit_kwqes)
rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
return rc;
}
/**
* bnx2i_send_conn_ofld_req - initiates iscsi connection context setup process
*
* @hba: adapter structure pointer
* @ep: endpoint (transport indentifier) structure
*
* this routine prepares and posts CONN_OFLD_REQ1/2 KWQE
*/
int bnx2i_send_conn_ofld_req(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep)
{
int rc;
if (test_bit(BNX2I_NX2_DEV_57710, &hba->cnic_dev_type))
rc = bnx2i_5771x_send_conn_ofld_req(hba, ep);
else
rc = bnx2i_570x_send_conn_ofld_req(hba, ep);
return rc;
}
/**
* setup_qp_page_tables - iscsi QP page table setup function
* @ep: endpoint (transport indentifier) structure
*
* Sets up page tables for SQ/RQ/CQ, 1G/sec (5706/5708/5709) devices requires
* 64-bit address in big endian format. Whereas 10G/sec (57710) requires
* PT in little endian format
*/
static void setup_qp_page_tables(struct bnx2i_endpoint *ep)
{
int num_pages;
u32 *ptbl;
dma_addr_t page;
int cnic_dev_10g;
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type))
cnic_dev_10g = 1;
else
cnic_dev_10g = 0;
/* SQ page table */
memset(ep->qp.sq_pgtbl_virt, 0, ep->qp.sq_pgtbl_size);
num_pages = ep->qp.sq_mem_size / PAGE_SIZE;
page = ep->qp.sq_phys;
if (cnic_dev_10g)
ptbl = (u32 *)((u8 *)ep->qp.sq_pgtbl_virt + ISCSI_SQ_DB_SIZE);
else
ptbl = (u32 *) ep->qp.sq_pgtbl_virt;
while (num_pages--) {
if (cnic_dev_10g) {
/* PTE is written in little endian format for 57710 */
*ptbl = (u32) page;
ptbl++;
*ptbl = (u32) ((u64) page >> 32);
ptbl++;
page += PAGE_SIZE;
} else {
/* PTE is written in big endian format for
* 5706/5708/5709 devices */
*ptbl = (u32) ((u64) page >> 32);
ptbl++;
*ptbl = (u32) page;
ptbl++;
page += PAGE_SIZE;
}
}
/* RQ page table */
memset(ep->qp.rq_pgtbl_virt, 0, ep->qp.rq_pgtbl_size);
num_pages = ep->qp.rq_mem_size / PAGE_SIZE;
page = ep->qp.rq_phys;
if (cnic_dev_10g)
ptbl = (u32 *)((u8 *)ep->qp.rq_pgtbl_virt + ISCSI_RQ_DB_SIZE);
else
ptbl = (u32 *) ep->qp.rq_pgtbl_virt;
while (num_pages--) {
if (cnic_dev_10g) {
/* PTE is written in little endian format for 57710 */
*ptbl = (u32) page;
ptbl++;
*ptbl = (u32) ((u64) page >> 32);
ptbl++;
page += PAGE_SIZE;
} else {
/* PTE is written in big endian format for
* 5706/5708/5709 devices */
*ptbl = (u32) ((u64) page >> 32);
ptbl++;
*ptbl = (u32) page;
ptbl++;
page += PAGE_SIZE;
}
}
/* CQ page table */
memset(ep->qp.cq_pgtbl_virt, 0, ep->qp.cq_pgtbl_size);
num_pages = ep->qp.cq_mem_size / PAGE_SIZE;
page = ep->qp.cq_phys;
if (cnic_dev_10g)
ptbl = (u32 *)((u8 *)ep->qp.cq_pgtbl_virt + ISCSI_CQ_DB_SIZE);
else
ptbl = (u32 *) ep->qp.cq_pgtbl_virt;
while (num_pages--) {
if (cnic_dev_10g) {
/* PTE is written in little endian format for 57710 */
*ptbl = (u32) page;
ptbl++;
*ptbl = (u32) ((u64) page >> 32);
ptbl++;
page += PAGE_SIZE;
} else {
/* PTE is written in big endian format for
* 5706/5708/5709 devices */
*ptbl = (u32) ((u64) page >> 32);
ptbl++;
*ptbl = (u32) page;
ptbl++;
page += PAGE_SIZE;
}
}
}
/**
* bnx2i_alloc_qp_resc - allocates required resources for QP.
* @hba: adapter structure pointer
* @ep: endpoint (transport indentifier) structure
*
* Allocate QP (transport layer for iSCSI connection) resources, DMA'able
* memory for SQ/RQ/CQ and page tables. EP structure elements such
* as producer/consumer indexes/pointers, queue sizes and page table
* contents are setup
*/
int bnx2i_alloc_qp_resc(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep)
{
struct bnx2i_5771x_cq_db *cq_db;
ep->hba = hba;
ep->conn = NULL;
ep->ep_cid = ep->ep_iscsi_cid = ep->ep_pg_cid = 0;
/* Allocate page table memory for SQ which is page aligned */
ep->qp.sq_mem_size = hba->max_sqes * BNX2I_SQ_WQE_SIZE;
ep->qp.sq_mem_size =
(ep->qp.sq_mem_size + (PAGE_SIZE - 1)) & PAGE_MASK;
ep->qp.sq_pgtbl_size =
(ep->qp.sq_mem_size / PAGE_SIZE) * sizeof(void *);
ep->qp.sq_pgtbl_size =
(ep->qp.sq_pgtbl_size + (PAGE_SIZE - 1)) & PAGE_MASK;
ep->qp.sq_pgtbl_virt =
dma_alloc_coherent(&hba->pcidev->dev, ep->qp.sq_pgtbl_size,
&ep->qp.sq_pgtbl_phys, GFP_KERNEL);
if (!ep->qp.sq_pgtbl_virt) {
printk(KERN_ALERT "bnx2i: unable to alloc SQ PT mem (%d)\n",
ep->qp.sq_pgtbl_size);
goto mem_alloc_err;
}
/* Allocate memory area for actual SQ element */
ep->qp.sq_virt =
dma_alloc_coherent(&hba->pcidev->dev, ep->qp.sq_mem_size,
&ep->qp.sq_phys, GFP_KERNEL);
if (!ep->qp.sq_virt) {
printk(KERN_ALERT "bnx2i: unable to alloc SQ BD memory %d\n",
ep->qp.sq_mem_size);
goto mem_alloc_err;
}
memset(ep->qp.sq_virt, 0x00, ep->qp.sq_mem_size);
ep->qp.sq_first_qe = ep->qp.sq_virt;
ep->qp.sq_prod_qe = ep->qp.sq_first_qe;
ep->qp.sq_cons_qe = ep->qp.sq_first_qe;
ep->qp.sq_last_qe = &ep->qp.sq_first_qe[hba->max_sqes - 1];
ep->qp.sq_prod_idx = 0;
ep->qp.sq_cons_idx = 0;
ep->qp.sqe_left = hba->max_sqes;
/* Allocate page table memory for CQ which is page aligned */
ep->qp.cq_mem_size = hba->max_cqes * BNX2I_CQE_SIZE;
ep->qp.cq_mem_size =
(ep->qp.cq_mem_size + (PAGE_SIZE - 1)) & PAGE_MASK;
ep->qp.cq_pgtbl_size =
(ep->qp.cq_mem_size / PAGE_SIZE) * sizeof(void *);
ep->qp.cq_pgtbl_size =
(ep->qp.cq_pgtbl_size + (PAGE_SIZE - 1)) & PAGE_MASK;
ep->qp.cq_pgtbl_virt =
dma_alloc_coherent(&hba->pcidev->dev, ep->qp.cq_pgtbl_size,
&ep->qp.cq_pgtbl_phys, GFP_KERNEL);
if (!ep->qp.cq_pgtbl_virt) {
printk(KERN_ALERT "bnx2i: unable to alloc CQ PT memory %d\n",
ep->qp.cq_pgtbl_size);
goto mem_alloc_err;
}
/* Allocate memory area for actual CQ element */
ep->qp.cq_virt =
dma_alloc_coherent(&hba->pcidev->dev, ep->qp.cq_mem_size,
&ep->qp.cq_phys, GFP_KERNEL);
if (!ep->qp.cq_virt) {
printk(KERN_ALERT "bnx2i: unable to alloc CQ BD memory %d\n",
ep->qp.cq_mem_size);
goto mem_alloc_err;
}
memset(ep->qp.cq_virt, 0x00, ep->qp.cq_mem_size);
ep->qp.cq_first_qe = ep->qp.cq_virt;
ep->qp.cq_prod_qe = ep->qp.cq_first_qe;
ep->qp.cq_cons_qe = ep->qp.cq_first_qe;
ep->qp.cq_last_qe = &ep->qp.cq_first_qe[hba->max_cqes - 1];
ep->qp.cq_prod_idx = 0;
ep->qp.cq_cons_idx = 0;
ep->qp.cqe_left = hba->max_cqes;
ep->qp.cqe_exp_seq_sn = ISCSI_INITIAL_SN;
ep->qp.cqe_size = hba->max_cqes;
/* Invalidate all EQ CQE index, req only for 57710 */
cq_db = (struct bnx2i_5771x_cq_db *) ep->qp.cq_pgtbl_virt;
memset(cq_db->sqn, 0xFF, sizeof(cq_db->sqn[0]) * BNX2X_MAX_CQS);
/* Allocate page table memory for RQ which is page aligned */
ep->qp.rq_mem_size = hba->max_rqes * BNX2I_RQ_WQE_SIZE;
ep->qp.rq_mem_size =
(ep->qp.rq_mem_size + (PAGE_SIZE - 1)) & PAGE_MASK;
ep->qp.rq_pgtbl_size =
(ep->qp.rq_mem_size / PAGE_SIZE) * sizeof(void *);
ep->qp.rq_pgtbl_size =
(ep->qp.rq_pgtbl_size + (PAGE_SIZE - 1)) & PAGE_MASK;
ep->qp.rq_pgtbl_virt =
dma_alloc_coherent(&hba->pcidev->dev, ep->qp.rq_pgtbl_size,
&ep->qp.rq_pgtbl_phys, GFP_KERNEL);
if (!ep->qp.rq_pgtbl_virt) {
printk(KERN_ALERT "bnx2i: unable to alloc RQ PT mem %d\n",
ep->qp.rq_pgtbl_size);
goto mem_alloc_err;
}
/* Allocate memory area for actual RQ element */
ep->qp.rq_virt =
dma_alloc_coherent(&hba->pcidev->dev, ep->qp.rq_mem_size,
&ep->qp.rq_phys, GFP_KERNEL);
if (!ep->qp.rq_virt) {
printk(KERN_ALERT "bnx2i: unable to alloc RQ BD memory %d\n",
ep->qp.rq_mem_size);
goto mem_alloc_err;
}
ep->qp.rq_first_qe = ep->qp.rq_virt;
ep->qp.rq_prod_qe = ep->qp.rq_first_qe;
ep->qp.rq_cons_qe = ep->qp.rq_first_qe;
ep->qp.rq_last_qe = &ep->qp.rq_first_qe[hba->max_rqes - 1];
ep->qp.rq_prod_idx = 0x8000;
ep->qp.rq_cons_idx = 0;
ep->qp.rqe_left = hba->max_rqes;
setup_qp_page_tables(ep);
return 0;
mem_alloc_err:
bnx2i_free_qp_resc(hba, ep);
return -ENOMEM;
}
/**
* bnx2i_free_qp_resc - free memory resources held by QP
* @hba: adapter structure pointer
* @ep: endpoint (transport indentifier) structure
*
* Free QP resources - SQ/RQ/CQ memory and page tables.
*/
void bnx2i_free_qp_resc(struct bnx2i_hba *hba, struct bnx2i_endpoint *ep)
{
if (ep->qp.ctx_base) {
iounmap(ep->qp.ctx_base);
ep->qp.ctx_base = NULL;
}
/* Free SQ mem */
if (ep->qp.sq_pgtbl_virt) {
dma_free_coherent(&hba->pcidev->dev, ep->qp.sq_pgtbl_size,
ep->qp.sq_pgtbl_virt, ep->qp.sq_pgtbl_phys);
ep->qp.sq_pgtbl_virt = NULL;
ep->qp.sq_pgtbl_phys = 0;
}
if (ep->qp.sq_virt) {
dma_free_coherent(&hba->pcidev->dev, ep->qp.sq_mem_size,
ep->qp.sq_virt, ep->qp.sq_phys);
ep->qp.sq_virt = NULL;
ep->qp.sq_phys = 0;
}
/* Free RQ mem */
if (ep->qp.rq_pgtbl_virt) {
dma_free_coherent(&hba->pcidev->dev, ep->qp.rq_pgtbl_size,
ep->qp.rq_pgtbl_virt, ep->qp.rq_pgtbl_phys);
ep->qp.rq_pgtbl_virt = NULL;
ep->qp.rq_pgtbl_phys = 0;
}
if (ep->qp.rq_virt) {
dma_free_coherent(&hba->pcidev->dev, ep->qp.rq_mem_size,
ep->qp.rq_virt, ep->qp.rq_phys);
ep->qp.rq_virt = NULL;
ep->qp.rq_phys = 0;
}
/* Free CQ mem */
if (ep->qp.cq_pgtbl_virt) {
dma_free_coherent(&hba->pcidev->dev, ep->qp.cq_pgtbl_size,
ep->qp.cq_pgtbl_virt, ep->qp.cq_pgtbl_phys);
ep->qp.cq_pgtbl_virt = NULL;
ep->qp.cq_pgtbl_phys = 0;
}
if (ep->qp.cq_virt) {
dma_free_coherent(&hba->pcidev->dev, ep->qp.cq_mem_size,
ep->qp.cq_virt, ep->qp.cq_phys);
ep->qp.cq_virt = NULL;
ep->qp.cq_phys = 0;
}
}
/**
* bnx2i_send_fw_iscsi_init_msg - initiates initial handshake with iscsi f/w
* @hba: adapter structure pointer
*
* Send down iscsi_init KWQEs which initiates the initial handshake with the f/w
* This results in iSCSi support validation and on-chip context manager
* initialization. Firmware completes this handshake with a CQE carrying
* the result of iscsi support validation. Parameter carried by
* iscsi init request determines the number of offloaded connection and
* tolerance level for iscsi protocol violation this hba/chip can support
*/
int bnx2i_send_fw_iscsi_init_msg(struct bnx2i_hba *hba)
{
struct kwqe *kwqe_arr[3];
struct iscsi_kwqe_init1 iscsi_init;
struct iscsi_kwqe_init2 iscsi_init2;
int rc = 0;
u64 mask64;
memset(&iscsi_init, 0x00, sizeof(struct iscsi_kwqe_init1));
memset(&iscsi_init2, 0x00, sizeof(struct iscsi_kwqe_init2));
bnx2i_adjust_qp_size(hba);
iscsi_init.flags =
ISCSI_PAGE_SIZE_4K << ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT;
if (en_tcp_dack)
iscsi_init.flags |= ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE;
iscsi_init.reserved0 = 0;
iscsi_init.num_cqs = 1;
iscsi_init.hdr.op_code = ISCSI_KWQE_OPCODE_INIT1;
iscsi_init.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
iscsi_init.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
iscsi_init.dummy_buffer_addr_hi =
(u32) ((u64) hba->dummy_buf_dma >> 32);
hba->num_ccell = hba->max_sqes >> 1;
hba->ctx_ccell_tasks =
((hba->num_ccell & 0xFFFF) | (hba->max_sqes << 16));
iscsi_init.num_ccells_per_conn = hba->num_ccell;
iscsi_init.num_tasks_per_conn = hba->max_sqes;
iscsi_init.sq_wqes_per_page = PAGE_SIZE / BNX2I_SQ_WQE_SIZE;
iscsi_init.sq_num_wqes = hba->max_sqes;
iscsi_init.cq_log_wqes_per_page =
(u8) bnx2i_power_of2(PAGE_SIZE / BNX2I_CQE_SIZE);
iscsi_init.cq_num_wqes = hba->max_cqes;
iscsi_init.cq_num_pages = (hba->max_cqes * BNX2I_CQE_SIZE +
(PAGE_SIZE - 1)) / PAGE_SIZE;
iscsi_init.sq_num_pages = (hba->max_sqes * BNX2I_SQ_WQE_SIZE +
(PAGE_SIZE - 1)) / PAGE_SIZE;
iscsi_init.rq_buffer_size = BNX2I_RQ_WQE_SIZE;
iscsi_init.rq_num_wqes = hba->max_rqes;
iscsi_init2.hdr.op_code = ISCSI_KWQE_OPCODE_INIT2;
iscsi_init2.hdr.flags =
(ISCSI_KWQE_LAYER_CODE << ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT);
iscsi_init2.max_cq_sqn = hba->max_cqes * 2 + 1;
mask64 = 0x0ULL;
mask64 |= (
/* CISCO MDS */
(1UL <<
ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV) |
/* HP MSA1510i */
(1UL <<
ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN) |
/* EMC */
(1ULL << ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN));
if (error_mask1)
iscsi_init2.error_bit_map[0] = error_mask1;
else
iscsi_init2.error_bit_map[0] = (u32) mask64;
if (error_mask2)
iscsi_init2.error_bit_map[1] = error_mask2;
else
iscsi_init2.error_bit_map[1] = (u32) (mask64 >> 32);
iscsi_error_mask = mask64;
kwqe_arr[0] = (struct kwqe *) &iscsi_init;
kwqe_arr[1] = (struct kwqe *) &iscsi_init2;
if (hba->cnic && hba->cnic->submit_kwqes)
rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, 2);
return rc;
}
/**
* bnx2i_process_scsi_cmd_resp - this function handles scsi cmd completion.
* @conn: iscsi connection
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process SCSI CMD Response CQE & complete the request to SCSI-ML
*/
static int bnx2i_process_scsi_cmd_resp(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct bnx2i_cmd_response *resp_cqe;
struct bnx2i_cmd *bnx2i_cmd;
struct iscsi_task *task;
struct iscsi_cmd_rsp *hdr;
u32 datalen = 0;
resp_cqe = (struct bnx2i_cmd_response *)cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn,
resp_cqe->itt & ISCSI_CMD_RESPONSE_INDEX);
if (!task)
goto fail;
bnx2i_cmd = task->dd_data;
if (bnx2i_cmd->req.op_attr & ISCSI_CMD_REQUEST_READ) {
conn->datain_pdus_cnt +=
resp_cqe->task_stat.read_stat.num_data_outs;
conn->rxdata_octets +=
bnx2i_cmd->req.total_data_transfer_length;
} else {
conn->dataout_pdus_cnt +=
resp_cqe->task_stat.read_stat.num_data_outs;
conn->r2t_pdus_cnt +=
resp_cqe->task_stat.read_stat.num_r2ts;
conn->txdata_octets +=
bnx2i_cmd->req.total_data_transfer_length;
}
bnx2i_iscsi_unmap_sg_list(bnx2i_cmd);
hdr = (struct iscsi_cmd_rsp *)task->hdr;
resp_cqe = (struct bnx2i_cmd_response *)cqe;
hdr->opcode = resp_cqe->op_code;
hdr->max_cmdsn = cpu_to_be32(resp_cqe->max_cmd_sn);
hdr->exp_cmdsn = cpu_to_be32(resp_cqe->exp_cmd_sn);
hdr->response = resp_cqe->response;
hdr->cmd_status = resp_cqe->status;
hdr->flags = resp_cqe->response_flags;
hdr->residual_count = cpu_to_be32(resp_cqe->residual_count);
if (resp_cqe->op_code == ISCSI_OP_SCSI_DATA_IN)
goto done;
if (resp_cqe->status == SAM_STAT_CHECK_CONDITION) {
datalen = resp_cqe->data_length;
if (datalen < 2)
goto done;
if (datalen > BNX2I_RQ_WQE_SIZE) {
iscsi_conn_printk(KERN_ERR, conn,
"sense data len %d > RQ sz\n",
datalen);
datalen = BNX2I_RQ_WQE_SIZE;
} else if (datalen > ISCSI_DEF_MAX_RECV_SEG_LEN) {
iscsi_conn_printk(KERN_ERR, conn,
"sense data len %d > conn data\n",
datalen);
datalen = ISCSI_DEF_MAX_RECV_SEG_LEN;
}
bnx2i_get_rq_buf(bnx2i_cmd->conn, conn->data, datalen);
bnx2i_put_rq_buf(bnx2i_cmd->conn, 1);
}
done:
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr,
conn->data, datalen);
fail:
spin_unlock(&session->lock);
return 0;
}
/**
* bnx2i_process_login_resp - this function handles iscsi login response
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process Login Response CQE & complete it to open-iscsi user daemon
*/
static int bnx2i_process_login_resp(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_task *task;
struct bnx2i_login_response *login;
struct iscsi_login_rsp *resp_hdr;
int pld_len;
int pad_len;
login = (struct bnx2i_login_response *) cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn,
login->itt & ISCSI_LOGIN_RESPONSE_INDEX);
if (!task)
goto done;
resp_hdr = (struct iscsi_login_rsp *) &bnx2i_conn->gen_pdu.resp_hdr;
memset(resp_hdr, 0, sizeof(struct iscsi_hdr));
resp_hdr->opcode = login->op_code;
resp_hdr->flags = login->response_flags;
resp_hdr->max_version = login->version_max;
resp_hdr->active_version = login->version_active;
resp_hdr->hlength = 0;
hton24(resp_hdr->dlength, login->data_length);
memcpy(resp_hdr->isid, &login->isid_lo, 6);
resp_hdr->tsih = cpu_to_be16(login->tsih);
resp_hdr->itt = task->hdr->itt;
resp_hdr->statsn = cpu_to_be32(login->stat_sn);
resp_hdr->exp_cmdsn = cpu_to_be32(login->exp_cmd_sn);
resp_hdr->max_cmdsn = cpu_to_be32(login->max_cmd_sn);
resp_hdr->status_class = login->status_class;
resp_hdr->status_detail = login->status_detail;
pld_len = login->data_length;
bnx2i_conn->gen_pdu.resp_wr_ptr =
bnx2i_conn->gen_pdu.resp_buf + pld_len;
pad_len = 0;
if (pld_len & 0x3)
pad_len = 4 - (pld_len % 4);
if (pad_len) {
int i = 0;
for (i = 0; i < pad_len; i++) {
bnx2i_conn->gen_pdu.resp_wr_ptr[0] = 0;
bnx2i_conn->gen_pdu.resp_wr_ptr++;
}
}
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)resp_hdr,
bnx2i_conn->gen_pdu.resp_buf,
bnx2i_conn->gen_pdu.resp_wr_ptr - bnx2i_conn->gen_pdu.resp_buf);
done:
spin_unlock(&session->lock);
return 0;
}
/**
* bnx2i_process_text_resp - this function handles iscsi text response
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI Text Response CQE& complete it to open-iscsi user daemon
*/
static int bnx2i_process_text_resp(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_task *task;
struct bnx2i_text_response *text;
struct iscsi_text_rsp *resp_hdr;
int pld_len;
int pad_len;
text = (struct bnx2i_text_response *) cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn, text->itt & ISCSI_LOGIN_RESPONSE_INDEX);
if (!task)
goto done;
resp_hdr = (struct iscsi_text_rsp *)&bnx2i_conn->gen_pdu.resp_hdr;
memset(resp_hdr, 0, sizeof(struct iscsi_hdr));
resp_hdr->opcode = text->op_code;
resp_hdr->flags = text->response_flags;
resp_hdr->hlength = 0;
hton24(resp_hdr->dlength, text->data_length);
resp_hdr->itt = task->hdr->itt;
resp_hdr->ttt = cpu_to_be32(text->ttt);
resp_hdr->statsn = task->hdr->exp_statsn;
resp_hdr->exp_cmdsn = cpu_to_be32(text->exp_cmd_sn);
resp_hdr->max_cmdsn = cpu_to_be32(text->max_cmd_sn);
pld_len = text->data_length;
bnx2i_conn->gen_pdu.resp_wr_ptr = bnx2i_conn->gen_pdu.resp_buf +
pld_len;
pad_len = 0;
if (pld_len & 0x3)
pad_len = 4 - (pld_len % 4);
if (pad_len) {
int i = 0;
for (i = 0; i < pad_len; i++) {
bnx2i_conn->gen_pdu.resp_wr_ptr[0] = 0;
bnx2i_conn->gen_pdu.resp_wr_ptr++;
}
}
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)resp_hdr,
bnx2i_conn->gen_pdu.resp_buf,
bnx2i_conn->gen_pdu.resp_wr_ptr -
bnx2i_conn->gen_pdu.resp_buf);
done:
spin_unlock(&session->lock);
return 0;
}
/**
* bnx2i_process_tmf_resp - this function handles iscsi TMF response
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI TMF Response CQE and wake up the driver eh thread.
*/
static int bnx2i_process_tmf_resp(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_task *task;
struct bnx2i_tmf_response *tmf_cqe;
struct iscsi_tm_rsp *resp_hdr;
tmf_cqe = (struct bnx2i_tmf_response *)cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn,
tmf_cqe->itt & ISCSI_TMF_RESPONSE_INDEX);
if (!task)
goto done;
resp_hdr = (struct iscsi_tm_rsp *) &bnx2i_conn->gen_pdu.resp_hdr;
memset(resp_hdr, 0, sizeof(struct iscsi_hdr));
resp_hdr->opcode = tmf_cqe->op_code;
resp_hdr->max_cmdsn = cpu_to_be32(tmf_cqe->max_cmd_sn);
resp_hdr->exp_cmdsn = cpu_to_be32(tmf_cqe->exp_cmd_sn);
resp_hdr->itt = task->hdr->itt;
resp_hdr->response = tmf_cqe->response;
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)resp_hdr, NULL, 0);
done:
spin_unlock(&session->lock);
return 0;
}
/**
* bnx2i_process_logout_resp - this function handles iscsi logout response
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI Logout Response CQE & make function call to
* notify the user daemon.
*/
static int bnx2i_process_logout_resp(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_task *task;
struct bnx2i_logout_response *logout;
struct iscsi_logout_rsp *resp_hdr;
logout = (struct bnx2i_logout_response *) cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn,
logout->itt & ISCSI_LOGOUT_RESPONSE_INDEX);
if (!task)
goto done;
resp_hdr = (struct iscsi_logout_rsp *) &bnx2i_conn->gen_pdu.resp_hdr;
memset(resp_hdr, 0, sizeof(struct iscsi_hdr));
resp_hdr->opcode = logout->op_code;
resp_hdr->flags = logout->response;
resp_hdr->hlength = 0;
resp_hdr->itt = task->hdr->itt;
resp_hdr->statsn = task->hdr->exp_statsn;
resp_hdr->exp_cmdsn = cpu_to_be32(logout->exp_cmd_sn);
resp_hdr->max_cmdsn = cpu_to_be32(logout->max_cmd_sn);
resp_hdr->t2wait = cpu_to_be32(logout->time_to_wait);
resp_hdr->t2retain = cpu_to_be32(logout->time_to_retain);
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)resp_hdr, NULL, 0);
bnx2i_conn->ep->state = EP_STATE_LOGOUT_RESP_RCVD;
done:
spin_unlock(&session->lock);
return 0;
}
/**
* bnx2i_process_nopin_local_cmpl - this function handles iscsi nopin CQE
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI NOPIN local completion CQE, frees IIT and command structures
*/
static void bnx2i_process_nopin_local_cmpl(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct bnx2i_nop_in_msg *nop_in;
struct iscsi_task *task;
nop_in = (struct bnx2i_nop_in_msg *)cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn,
nop_in->itt & ISCSI_NOP_IN_MSG_INDEX);
if (task)
__iscsi_put_task(task);
spin_unlock(&session->lock);
}
/**
* bnx2i_unsol_pdu_adjust_rq - makes adjustments to RQ after unsol pdu is recvd
* @conn: iscsi connection
*
* Firmware advances RQ producer index for every unsolicited PDU even if
* payload data length is '0'. This function makes corresponding
* adjustments on the driver side to match this f/w behavior
*/
static void bnx2i_unsol_pdu_adjust_rq(struct bnx2i_conn *bnx2i_conn)
{
char dummy_rq_data[2];
bnx2i_get_rq_buf(bnx2i_conn, dummy_rq_data, 1);
bnx2i_put_rq_buf(bnx2i_conn, 1);
}
/**
* bnx2i_process_nopin_mesg - this function handles iscsi nopin CQE
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI target's proactive iSCSI NOPIN request
*/
static int bnx2i_process_nopin_mesg(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_task *task;
struct bnx2i_nop_in_msg *nop_in;
struct iscsi_nopin *hdr;
int tgt_async_nop = 0;
nop_in = (struct bnx2i_nop_in_msg *)cqe;
spin_lock(&session->lock);
hdr = (struct iscsi_nopin *)&bnx2i_conn->gen_pdu.resp_hdr;
memset(hdr, 0, sizeof(struct iscsi_hdr));
hdr->opcode = nop_in->op_code;
hdr->max_cmdsn = cpu_to_be32(nop_in->max_cmd_sn);
hdr->exp_cmdsn = cpu_to_be32(nop_in->exp_cmd_sn);
hdr->ttt = cpu_to_be32(nop_in->ttt);
if (nop_in->itt == (u16) RESERVED_ITT) {
bnx2i_unsol_pdu_adjust_rq(bnx2i_conn);
hdr->itt = RESERVED_ITT;
tgt_async_nop = 1;
goto done;
}
/* this is a response to one of our nop-outs */
task = iscsi_itt_to_task(conn,
(itt_t) (nop_in->itt & ISCSI_NOP_IN_MSG_INDEX));
if (task) {
hdr->flags = ISCSI_FLAG_CMD_FINAL;
hdr->itt = task->hdr->itt;
hdr->ttt = cpu_to_be32(nop_in->ttt);
memcpy(hdr->lun, nop_in->lun, 8);
}
done:
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
spin_unlock(&session->lock);
return tgt_async_nop;
}
/**
* bnx2i_process_async_mesg - this function handles iscsi async message
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI ASYNC Message
*/
static void bnx2i_process_async_mesg(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct bnx2i_async_msg *async_cqe;
struct iscsi_async *resp_hdr;
u8 async_event;
bnx2i_unsol_pdu_adjust_rq(bnx2i_conn);
async_cqe = (struct bnx2i_async_msg *)cqe;
async_event = async_cqe->async_event;
if (async_event == ISCSI_ASYNC_MSG_SCSI_EVENT) {
iscsi_conn_printk(KERN_ALERT, bnx2i_conn->cls_conn->dd_data,
"async: scsi events not supported\n");
return;
}
spin_lock(&session->lock);
resp_hdr = (struct iscsi_async *) &bnx2i_conn->gen_pdu.resp_hdr;
memset(resp_hdr, 0, sizeof(struct iscsi_hdr));
resp_hdr->opcode = async_cqe->op_code;
resp_hdr->flags = 0x80;
memcpy(resp_hdr->lun, async_cqe->lun, 8);
resp_hdr->exp_cmdsn = cpu_to_be32(async_cqe->exp_cmd_sn);
resp_hdr->max_cmdsn = cpu_to_be32(async_cqe->max_cmd_sn);
resp_hdr->async_event = async_cqe->async_event;
resp_hdr->async_vcode = async_cqe->async_vcode;
resp_hdr->param1 = cpu_to_be16(async_cqe->param1);
resp_hdr->param2 = cpu_to_be16(async_cqe->param2);
resp_hdr->param3 = cpu_to_be16(async_cqe->param3);
__iscsi_complete_pdu(bnx2i_conn->cls_conn->dd_data,
(struct iscsi_hdr *)resp_hdr, NULL, 0);
spin_unlock(&session->lock);
}
/**
* bnx2i_process_reject_mesg - process iscsi reject pdu
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process iSCSI REJECT message
*/
static void bnx2i_process_reject_mesg(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct bnx2i_reject_msg *reject;
struct iscsi_reject *hdr;
reject = (struct bnx2i_reject_msg *) cqe;
if (reject->data_length) {
bnx2i_get_rq_buf(bnx2i_conn, conn->data, reject->data_length);
bnx2i_put_rq_buf(bnx2i_conn, 1);
} else
bnx2i_unsol_pdu_adjust_rq(bnx2i_conn);
spin_lock(&session->lock);
hdr = (struct iscsi_reject *) &bnx2i_conn->gen_pdu.resp_hdr;
memset(hdr, 0, sizeof(struct iscsi_hdr));
hdr->opcode = reject->op_code;
hdr->reason = reject->reason;
hton24(hdr->dlength, reject->data_length);
hdr->max_cmdsn = cpu_to_be32(reject->max_cmd_sn);
hdr->exp_cmdsn = cpu_to_be32(reject->exp_cmd_sn);
hdr->ffffffff = cpu_to_be32(RESERVED_ITT);
__iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, conn->data,
reject->data_length);
spin_unlock(&session->lock);
}
/**
* bnx2i_process_cmd_cleanup_resp - process scsi command clean-up completion
* @session: iscsi session pointer
* @bnx2i_conn: iscsi connection pointer
* @cqe: pointer to newly DMA'ed CQE entry for processing
*
* process command cleanup response CQE during conn shutdown or error recovery
*/
static void bnx2i_process_cmd_cleanup_resp(struct iscsi_session *session,
struct bnx2i_conn *bnx2i_conn,
struct cqe *cqe)
{
struct bnx2i_cleanup_response *cmd_clean_rsp;
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_task *task;
cmd_clean_rsp = (struct bnx2i_cleanup_response *)cqe;
spin_lock(&session->lock);
task = iscsi_itt_to_task(conn,
cmd_clean_rsp->itt & ISCSI_CLEANUP_RESPONSE_INDEX);
if (!task)
printk(KERN_ALERT "bnx2i: cmd clean ITT %x not active\n",
cmd_clean_rsp->itt & ISCSI_CLEANUP_RESPONSE_INDEX);
spin_unlock(&session->lock);
complete(&bnx2i_conn->cmd_cleanup_cmpl);
}
/**
* bnx2i_process_new_cqes - process newly DMA'ed CQE's
* @bnx2i_conn: iscsi connection
*
* this function is called by generic KCQ handler to process all pending CQE's
*/
static void bnx2i_process_new_cqes(struct bnx2i_conn *bnx2i_conn)
{
struct iscsi_conn *conn = bnx2i_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
struct qp_info *qp = &bnx2i_conn->ep->qp;
struct bnx2i_nop_in_msg *nopin;
int tgt_async_msg;
while (1) {
nopin = (struct bnx2i_nop_in_msg *) qp->cq_cons_qe;
if (nopin->cq_req_sn != qp->cqe_exp_seq_sn)
break;
if (unlikely(test_bit(ISCSI_SUSPEND_BIT, &conn->suspend_rx))) {
if (nopin->op_code == ISCSI_OP_NOOP_IN &&
nopin->itt == (u16) RESERVED_ITT) {
printk(KERN_ALERT "bnx2i: Unsolicited "
"NOP-In detected for suspended "
"connection dev=%s!\n",
bnx2i_conn->hba->netdev->name);
bnx2i_unsol_pdu_adjust_rq(bnx2i_conn);
goto cqe_out;
}
break;
}
tgt_async_msg = 0;
switch (nopin->op_code) {
case ISCSI_OP_SCSI_CMD_RSP:
case ISCSI_OP_SCSI_DATA_IN:
bnx2i_process_scsi_cmd_resp(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OP_LOGIN_RSP:
bnx2i_process_login_resp(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OP_SCSI_TMFUNC_RSP:
bnx2i_process_tmf_resp(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OP_TEXT_RSP:
bnx2i_process_text_resp(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OP_LOGOUT_RSP:
bnx2i_process_logout_resp(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OP_NOOP_IN:
if (bnx2i_process_nopin_mesg(session, bnx2i_conn,
qp->cq_cons_qe))
tgt_async_msg = 1;
break;
case ISCSI_OPCODE_NOPOUT_LOCAL_COMPLETION:
bnx2i_process_nopin_local_cmpl(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OP_ASYNC_EVENT:
bnx2i_process_async_mesg(session, bnx2i_conn,
qp->cq_cons_qe);
tgt_async_msg = 1;
break;
case ISCSI_OP_REJECT:
bnx2i_process_reject_mesg(session, bnx2i_conn,
qp->cq_cons_qe);
break;
case ISCSI_OPCODE_CLEANUP_RESPONSE:
bnx2i_process_cmd_cleanup_resp(session, bnx2i_conn,
qp->cq_cons_qe);
break;
default:
printk(KERN_ALERT "bnx2i: unknown opcode 0x%x\n",
nopin->op_code);
}
if (!tgt_async_msg)
bnx2i_conn->ep->num_active_cmds--;
cqe_out:
/* clear out in production version only, till beta keep opcode
* field intact, will be helpful in debugging (context dump)
* nopin->op_code = 0;
*/
qp->cqe_exp_seq_sn++;
if (qp->cqe_exp_seq_sn == (qp->cqe_size * 2 + 1))
qp->cqe_exp_seq_sn = ISCSI_INITIAL_SN;
if (qp->cq_cons_qe == qp->cq_last_qe) {
qp->cq_cons_qe = qp->cq_first_qe;
qp->cq_cons_idx = 0;
} else {
qp->cq_cons_qe++;
qp->cq_cons_idx++;
}
}
}
/**
* bnx2i_fastpath_notification - process global event queue (KCQ)
* @hba: adapter structure pointer
* @new_cqe_kcqe: pointer to newly DMA'ed KCQE entry
*
* Fast path event notification handler, KCQ entry carries context id
* of the connection that has 1 or more pending CQ entries
*/
static void bnx2i_fastpath_notification(struct bnx2i_hba *hba,
struct iscsi_kcqe *new_cqe_kcqe)
{
struct bnx2i_conn *bnx2i_conn;
u32 iscsi_cid;
iscsi_cid = new_cqe_kcqe->iscsi_conn_id;
bnx2i_conn = bnx2i_get_conn_from_id(hba, iscsi_cid);
if (!bnx2i_conn) {
printk(KERN_ALERT "cid #%x not valid\n", iscsi_cid);
return;
}
if (!bnx2i_conn->ep) {
printk(KERN_ALERT "cid #%x - ep not bound\n", iscsi_cid);
return;
}
bnx2i_process_new_cqes(bnx2i_conn);
bnx2i_arm_cq_event_coalescing(bnx2i_conn->ep, CNIC_ARM_CQE_FP);
bnx2i_process_new_cqes(bnx2i_conn);
}
/**
* bnx2i_process_update_conn_cmpl - process iscsi conn update completion KCQE
* @hba: adapter structure pointer
* @update_kcqe: kcqe pointer
*
* CONN_UPDATE completion handler, this completes iSCSI connection FFP migration
*/
static void bnx2i_process_update_conn_cmpl(struct bnx2i_hba *hba,
struct iscsi_kcqe *update_kcqe)
{
struct bnx2i_conn *conn;
u32 iscsi_cid;
iscsi_cid = update_kcqe->iscsi_conn_id;
conn = bnx2i_get_conn_from_id(hba, iscsi_cid);
if (!conn) {
printk(KERN_ALERT "conn_update: cid %x not valid\n", iscsi_cid);
return;
}
if (!conn->ep) {
printk(KERN_ALERT "cid %x does not have ep bound\n", iscsi_cid);
return;
}
if (update_kcqe->completion_status) {
printk(KERN_ALERT "request failed cid %x\n", iscsi_cid);
conn->ep->state = EP_STATE_ULP_UPDATE_FAILED;
} else
conn->ep->state = EP_STATE_ULP_UPDATE_COMPL;
wake_up_interruptible(&conn->ep->ofld_wait);
}
/**
* bnx2i_recovery_que_add_conn - add connection to recovery queue
* @hba: adapter structure pointer
* @bnx2i_conn: iscsi connection
*
* Add connection to recovery queue and schedule adapter eh worker
*/
static void bnx2i_recovery_que_add_conn(struct bnx2i_hba *hba,
struct bnx2i_conn *bnx2i_conn)
{
iscsi_conn_failure(bnx2i_conn->cls_conn->dd_data,
ISCSI_ERR_CONN_FAILED);
}
/**
* bnx2i_process_tcp_error - process error notification on a given connection
*
* @hba: adapter structure pointer
* @tcp_err: tcp error kcqe pointer
*
* handles tcp level error notifications from FW.
*/
static void bnx2i_process_tcp_error(struct bnx2i_hba *hba,
struct iscsi_kcqe *tcp_err)
{
struct bnx2i_conn *bnx2i_conn;
u32 iscsi_cid;
iscsi_cid = tcp_err->iscsi_conn_id;
bnx2i_conn = bnx2i_get_conn_from_id(hba, iscsi_cid);
if (!bnx2i_conn) {
printk(KERN_ALERT "bnx2i - cid 0x%x not valid\n", iscsi_cid);
return;
}
printk(KERN_ALERT "bnx2i - cid 0x%x had TCP errors, error code 0x%x\n",
iscsi_cid, tcp_err->completion_status);
bnx2i_recovery_que_add_conn(bnx2i_conn->hba, bnx2i_conn);
}
/**
* bnx2i_process_iscsi_error - process error notification on a given connection
* @hba: adapter structure pointer
* @iscsi_err: iscsi error kcqe pointer
*
* handles iscsi error notifications from the FW. Firmware based in initial
* handshake classifies iscsi protocol / TCP rfc violation into either
* warning or error indications. If indication is of "Error" type, driver
* will initiate session recovery for that connection/session. For
* "Warning" type indication, driver will put out a system log message
* (there will be only one message for each type for the life of the
* session, this is to avoid un-necessarily overloading the system)
*/
static void bnx2i_process_iscsi_error(struct bnx2i_hba *hba,
struct iscsi_kcqe *iscsi_err)
{
struct bnx2i_conn *bnx2i_conn;
u32 iscsi_cid;
char warn_notice[] = "iscsi_warning";
char error_notice[] = "iscsi_error";
char additional_notice[64];
char *message;
int need_recovery;
u64 err_mask64;
iscsi_cid = iscsi_err->iscsi_conn_id;
bnx2i_conn = bnx2i_get_conn_from_id(hba, iscsi_cid);
if (!bnx2i_conn) {
printk(KERN_ALERT "bnx2i - cid 0x%x not valid\n", iscsi_cid);
return;
}
err_mask64 = (0x1ULL << iscsi_err->completion_status);
if (err_mask64 & iscsi_error_mask) {
need_recovery = 0;
message = warn_notice;
} else {
need_recovery = 1;
message = error_notice;
}
switch (iscsi_err->completion_status) {
case ISCSI_KCQE_COMPLETION_STATUS_HDR_DIG_ERR:
strcpy(additional_notice, "hdr digest err");
break;
case ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR:
strcpy(additional_notice, "data digest err");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_OPCODE:
strcpy(additional_notice, "wrong opcode rcvd");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_AHS_LEN:
strcpy(additional_notice, "AHS len > 0 rcvd");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ITT:
strcpy(additional_notice, "invalid ITT rcvd");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_STATSN:
strcpy(additional_notice, "wrong StatSN rcvd");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN:
strcpy(additional_notice, "wrong DataSN rcvd");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T:
strcpy(additional_notice, "pend R2T violation");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_0:
strcpy(additional_notice, "ERL0, UO");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_1:
strcpy(additional_notice, "ERL0, U1");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_2:
strcpy(additional_notice, "ERL0, U2");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_3:
strcpy(additional_notice, "ERL0, U3");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_4:
strcpy(additional_notice, "ERL0, U4");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_5:
strcpy(additional_notice, "ERL0, U5");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_6:
strcpy(additional_notice, "ERL0, U6");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_RCV_LEN:
strcpy(additional_notice, "invalid resi len");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_RCV_PDU_LEN:
strcpy(additional_notice, "MRDSL violation");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_F_BIT_ZERO:
strcpy(additional_notice, "F-bit not set");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV:
strcpy(additional_notice, "invalid TTT");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATASN:
strcpy(additional_notice, "invalid DataSN");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_BURST_LEN:
strcpy(additional_notice, "burst len violation");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_BUFFER_OFF:
strcpy(additional_notice, "buf offset violation");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN:
strcpy(additional_notice, "invalid LUN field");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_R2TSN:
strcpy(additional_notice, "invalid R2TSN field");
break;
#define BNX2I_ERR_DESIRED_DATA_TRNS_LEN_0 \
ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0
case BNX2I_ERR_DESIRED_DATA_TRNS_LEN_0:
strcpy(additional_notice, "invalid cmd len1");
break;
#define BNX2I_ERR_DESIRED_DATA_TRNS_LEN_1 \
ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1
case BNX2I_ERR_DESIRED_DATA_TRNS_LEN_1:
strcpy(additional_notice, "invalid cmd len2");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_EXCEED:
strcpy(additional_notice,
"pend r2t exceeds MaxOutstandingR2T value");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_IS_RSRV:
strcpy(additional_notice, "TTT is rsvd");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_BURST_LEN:
strcpy(additional_notice, "MBL violation");
break;
#define BNX2I_ERR_DATA_SEG_LEN_NOT_ZERO \
ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_NOT_ZERO
case BNX2I_ERR_DATA_SEG_LEN_NOT_ZERO:
strcpy(additional_notice, "data seg len != 0");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REJECT_PDU_LEN:
strcpy(additional_notice, "reject pdu len error");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ASYNC_PDU_LEN:
strcpy(additional_notice, "async pdu len error");
break;
case ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_NOPIN_PDU_LEN:
strcpy(additional_notice, "nopin pdu len error");
break;
#define BNX2_ERR_PEND_R2T_IN_CLEANUP \
ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_IN_CLEANUP
case BNX2_ERR_PEND_R2T_IN_CLEANUP:
strcpy(additional_notice, "pend r2t in cleanup");
break;
case ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_FRAGMENT:
strcpy(additional_notice, "IP fragments rcvd");
break;
case ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_OPTIONS:
strcpy(additional_notice, "IP options error");
break;
case ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_URGENT_FLAG:
strcpy(additional_notice, "urgent flag error");
break;
default:
printk(KERN_ALERT "iscsi_err - unknown err %x\n",
iscsi_err->completion_status);
}
if (need_recovery) {
iscsi_conn_printk(KERN_ALERT,
bnx2i_conn->cls_conn->dd_data,
"bnx2i: %s - %s\n",
message, additional_notice);
iscsi_conn_printk(KERN_ALERT,
bnx2i_conn->cls_conn->dd_data,
"conn_err - hostno %d conn %p, "
"iscsi_cid %x cid %x\n",
bnx2i_conn->hba->shost->host_no,
bnx2i_conn, bnx2i_conn->ep->ep_iscsi_cid,
bnx2i_conn->ep->ep_cid);
bnx2i_recovery_que_add_conn(bnx2i_conn->hba, bnx2i_conn);
} else
if (!test_and_set_bit(iscsi_err->completion_status,
(void *) &bnx2i_conn->violation_notified))
iscsi_conn_printk(KERN_ALERT,
bnx2i_conn->cls_conn->dd_data,
"bnx2i: %s - %s\n",
message, additional_notice);
}
/**
* bnx2i_process_conn_destroy_cmpl - process iscsi conn destroy completion
* @hba: adapter structure pointer
* @conn_destroy: conn destroy kcqe pointer
*
* handles connection destroy completion request.
*/
static void bnx2i_process_conn_destroy_cmpl(struct bnx2i_hba *hba,
struct iscsi_kcqe *conn_destroy)
{
struct bnx2i_endpoint *ep;
ep = bnx2i_find_ep_in_destroy_list(hba, conn_destroy->iscsi_conn_id);
if (!ep) {
printk(KERN_ALERT "bnx2i_conn_destroy_cmpl: no pending "
"offload request, unexpected complection\n");
return;
}
if (hba != ep->hba) {
printk(KERN_ALERT "conn destroy- error hba mis-match\n");
return;
}
if (conn_destroy->completion_status) {
printk(KERN_ALERT "conn_destroy_cmpl: op failed\n");
ep->state = EP_STATE_CLEANUP_FAILED;
} else
ep->state = EP_STATE_CLEANUP_CMPL;
wake_up_interruptible(&ep->ofld_wait);
}
/**
* bnx2i_process_ofld_cmpl - process initial iscsi conn offload completion
* @hba: adapter structure pointer
* @ofld_kcqe: conn offload kcqe pointer
*
* handles initial connection offload completion, ep_connect() thread is
* woken-up to continue with LLP connect process
*/
static void bnx2i_process_ofld_cmpl(struct bnx2i_hba *hba,
struct iscsi_kcqe *ofld_kcqe)
{
u32 cid_addr;
struct bnx2i_endpoint *ep;
u32 cid_num;
ep = bnx2i_find_ep_in_ofld_list(hba, ofld_kcqe->iscsi_conn_id);
if (!ep) {
printk(KERN_ALERT "ofld_cmpl: no pend offload request\n");
return;
}
if (hba != ep->hba) {
printk(KERN_ALERT "ofld_cmpl: error hba mis-match\n");
return;
}
if (ofld_kcqe->completion_status) {
ep->state = EP_STATE_OFLD_FAILED;
if (ofld_kcqe->completion_status ==
ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE)
printk(KERN_ALERT "bnx2i (%s): ofld1 cmpl - unable "
"to allocate iSCSI context resources\n",
hba->netdev->name);
else if (ofld_kcqe->completion_status ==
ISCSI_KCQE_COMPLETION_STATUS_INVALID_OPCODE)
printk(KERN_ALERT "bnx2i (%s): ofld1 cmpl - invalid "
"opcode\n", hba->netdev->name);
else if (ofld_kcqe->completion_status ==
ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY)
/* error status code valid only for 5771x chipset */
ep->state = EP_STATE_OFLD_FAILED_CID_BUSY;
else
printk(KERN_ALERT "bnx2i (%s): ofld1 cmpl - invalid "
"error code %d\n", hba->netdev->name,
ofld_kcqe->completion_status);
} else {
ep->state = EP_STATE_OFLD_COMPL;
cid_addr = ofld_kcqe->iscsi_conn_context_id;
cid_num = bnx2i_get_cid_num(ep);
ep->ep_cid = cid_addr;
ep->qp.ctx_base = NULL;
}
wake_up_interruptible(&ep->ofld_wait);
}
/**
* bnx2i_indicate_kcqe - process iscsi conn update completion KCQE
* @hba: adapter structure pointer
* @update_kcqe: kcqe pointer
*
* Generic KCQ event handler/dispatcher
*/
static void bnx2i_indicate_kcqe(void *context, struct kcqe *kcqe[],
u32 num_cqe)
{
struct bnx2i_hba *hba = context;
int i = 0;
struct iscsi_kcqe *ikcqe = NULL;
while (i < num_cqe) {
ikcqe = (struct iscsi_kcqe *) kcqe[i++];
if (ikcqe->op_code ==
ISCSI_KCQE_OPCODE_CQ_EVENT_NOTIFICATION)
bnx2i_fastpath_notification(hba, ikcqe);
else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_OFFLOAD_CONN)
bnx2i_process_ofld_cmpl(hba, ikcqe);
else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_UPDATE_CONN)
bnx2i_process_update_conn_cmpl(hba, ikcqe);
else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_INIT) {
if (ikcqe->completion_status !=
ISCSI_KCQE_COMPLETION_STATUS_SUCCESS)
bnx2i_iscsi_license_error(hba, ikcqe->\
completion_status);
else {
set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
bnx2i_get_link_state(hba);
printk(KERN_INFO "bnx2i [%.2x:%.2x.%.2x]: "
"ISCSI_INIT passed\n",
(u8)hba->pcidev->bus->number,
hba->pci_devno,
(u8)hba->pci_func);
}
} else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_DESTROY_CONN)
bnx2i_process_conn_destroy_cmpl(hba, ikcqe);
else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_ISCSI_ERROR)
bnx2i_process_iscsi_error(hba, ikcqe);
else if (ikcqe->op_code == ISCSI_KCQE_OPCODE_TCP_ERROR)
bnx2i_process_tcp_error(hba, ikcqe);
else
printk(KERN_ALERT "bnx2i: unknown opcode 0x%x\n",
ikcqe->op_code);
}
}
/**
* bnx2i_indicate_netevent - Generic netdev event handler
* @context: adapter structure pointer
* @event: event type
*
* Handles four netdev events, NETDEV_UP, NETDEV_DOWN,
* NETDEV_GOING_DOWN and NETDEV_CHANGE
*/
static void bnx2i_indicate_netevent(void *context, unsigned long event)
{
struct bnx2i_hba *hba = context;
switch (event) {
case NETDEV_UP:
if (!test_bit(ADAPTER_STATE_UP, &hba->adapter_state))
bnx2i_send_fw_iscsi_init_msg(hba);
break;
case NETDEV_DOWN:
clear_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state);
clear_bit(ADAPTER_STATE_UP, &hba->adapter_state);
break;
case NETDEV_GOING_DOWN:
set_bit(ADAPTER_STATE_GOING_DOWN, &hba->adapter_state);
iscsi_host_for_each_session(hba->shost,
bnx2i_drop_session);
break;
case NETDEV_CHANGE:
bnx2i_get_link_state(hba);
break;
default:
;
}
}
/**
* bnx2i_cm_connect_cmpl - process iscsi conn establishment completion
* @cm_sk: cnic sock structure pointer
*
* function callback exported via bnx2i - cnic driver interface to
* indicate completion of option-2 TCP connect request.
*/
static void bnx2i_cm_connect_cmpl(struct cnic_sock *cm_sk)
{
struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context;
if (test_bit(ADAPTER_STATE_GOING_DOWN, &ep->hba->adapter_state))
ep->state = EP_STATE_CONNECT_FAILED;
else if (test_bit(SK_F_OFFLD_COMPLETE, &cm_sk->flags))
ep->state = EP_STATE_CONNECT_COMPL;
else
ep->state = EP_STATE_CONNECT_FAILED;
wake_up_interruptible(&ep->ofld_wait);
}
/**
* bnx2i_cm_close_cmpl - process tcp conn close completion
* @cm_sk: cnic sock structure pointer
*
* function callback exported via bnx2i - cnic driver interface to
* indicate completion of option-2 graceful TCP connect shutdown
*/
static void bnx2i_cm_close_cmpl(struct cnic_sock *cm_sk)
{
struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context;
ep->state = EP_STATE_DISCONN_COMPL;
wake_up_interruptible(&ep->ofld_wait);
}
/**
* bnx2i_cm_abort_cmpl - process abortive tcp conn teardown completion
* @cm_sk: cnic sock structure pointer
*
* function callback exported via bnx2i - cnic driver interface to
* indicate completion of option-2 abortive TCP connect termination
*/
static void bnx2i_cm_abort_cmpl(struct cnic_sock *cm_sk)
{
struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context;
ep->state = EP_STATE_DISCONN_COMPL;
wake_up_interruptible(&ep->ofld_wait);
}
/**
* bnx2i_cm_remote_close - process received TCP FIN
* @hba: adapter structure pointer
* @update_kcqe: kcqe pointer
*
* function callback exported via bnx2i - cnic driver interface to indicate
* async TCP events such as FIN
*/
static void bnx2i_cm_remote_close(struct cnic_sock *cm_sk)
{
struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context;
ep->state = EP_STATE_TCP_FIN_RCVD;
if (ep->conn)
bnx2i_recovery_que_add_conn(ep->hba, ep->conn);
}
/**
* bnx2i_cm_remote_abort - process TCP RST and start conn cleanup
* @hba: adapter structure pointer
* @update_kcqe: kcqe pointer
*
* function callback exported via bnx2i - cnic driver interface to
* indicate async TCP events (RST) sent by the peer.
*/
static void bnx2i_cm_remote_abort(struct cnic_sock *cm_sk)
{
struct bnx2i_endpoint *ep = (struct bnx2i_endpoint *) cm_sk->context;
u32 old_state = ep->state;
ep->state = EP_STATE_TCP_RST_RCVD;
if (old_state == EP_STATE_DISCONN_START)
wake_up_interruptible(&ep->ofld_wait);
else
if (ep->conn)
bnx2i_recovery_que_add_conn(ep->hba, ep->conn);
}
static int bnx2i_send_nl_mesg(void *context, u32 msg_type,
char *buf, u16 buflen)
{
struct bnx2i_hba *hba = context;
int rc;
if (!hba)
return -ENODEV;
rc = iscsi_offload_mesg(hba->shost, &bnx2i_iscsi_transport,
msg_type, buf, buflen);
if (rc)
printk(KERN_ALERT "bnx2i: private nl message send error\n");
return rc;
}
/**
* bnx2i_cnic_cb - global template of bnx2i - cnic driver interface structure
* carrying callback function pointers
*
*/
struct cnic_ulp_ops bnx2i_cnic_cb = {
.cnic_init = bnx2i_ulp_init,
.cnic_exit = bnx2i_ulp_exit,
.cnic_start = bnx2i_start,
.cnic_stop = bnx2i_stop,
.indicate_kcqes = bnx2i_indicate_kcqe,
.indicate_netevent = bnx2i_indicate_netevent,
.cm_connect_complete = bnx2i_cm_connect_cmpl,
.cm_close_complete = bnx2i_cm_close_cmpl,
.cm_abort_complete = bnx2i_cm_abort_cmpl,
.cm_remote_close = bnx2i_cm_remote_close,
.cm_remote_abort = bnx2i_cm_remote_abort,
.iscsi_nl_send_msg = bnx2i_send_nl_mesg,
.owner = THIS_MODULE
};
/**
* bnx2i_map_ep_dbell_regs - map connection doorbell registers
* @ep: bnx2i endpoint
*
* maps connection's SQ and RQ doorbell registers, 5706/5708/5709 hosts these
* register in BAR #0. Whereas in 57710 these register are accessed by
* mapping BAR #1
*/
int bnx2i_map_ep_dbell_regs(struct bnx2i_endpoint *ep)
{
u32 cid_num;
u32 reg_off;
u32 first_l4l5;
u32 ctx_sz;
u32 config2;
resource_size_t reg_base;
cid_num = bnx2i_get_cid_num(ep);
if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) {
reg_base = pci_resource_start(ep->hba->pcidev,
BNX2X_DOORBELL_PCI_BAR);
reg_off = BNX2I_5771X_DBELL_PAGE_SIZE * (cid_num & 0x1FFFF) +
DPM_TRIGER_TYPE;
ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4);
goto arm_cq;
}
reg_base = ep->hba->netdev->base_addr;
if ((test_bit(BNX2I_NX2_DEV_5709, &ep->hba->cnic_dev_type)) &&
(ep->hba->mail_queue_access == BNX2I_MQ_BIN_MODE)) {
config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2);
first_l4l5 = config2 & BNX2_MQ_CONFIG2_FIRST_L4L5;
ctx_sz = (config2 & BNX2_MQ_CONFIG2_CONT_SZ) >> 3;
if (ctx_sz)
reg_off = CTX_OFFSET + MAX_CID_CNT * MB_KERNEL_CTX_SIZE
+ BNX2I_570X_PAGE_SIZE_DEFAULT *
(((cid_num - first_l4l5) / ctx_sz) + 256);
else
reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num);
} else
/* 5709 device in normal node and 5706/5708 devices */
reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num);
ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off,
MB_KERNEL_CTX_SIZE);
if (!ep->qp.ctx_base)
return -ENOMEM;
arm_cq:
bnx2i_arm_cq_event_coalescing(ep, CNIC_ARM_CQE);
return 0;
}
| gpl-2.0 |
faux123/Endeavoru | arch/mips/mm/tlb-r4k.c | 1200 | 11011 | /*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/system.h>
extern void build_tlb_refill_handler(void);
/*
* Make sure all entries differ. If they're not different
* MIPS32 will take revenge ...
*/
#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
/* Atomicity and interruptability */
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/smtc.h>
#include <asm/mipsmtregs.h>
#define ENTER_CRITICAL(flags) \
{ \
unsigned int mvpflags; \
local_irq_save(flags);\
mvpflags = dvpe()
#define EXIT_CRITICAL(flags) \
evpe(mvpflags); \
local_irq_restore(flags); \
}
#else
#define ENTER_CRITICAL(flags) local_irq_save(flags)
#define EXIT_CRITICAL(flags) local_irq_restore(flags)
#endif /* CONFIG_MIPS_MT_SMTC */
#if defined(CONFIG_CPU_LOONGSON2)
/*
* LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
* unfortrunately, itlb is not totally transparent to software.
*/
#define FLUSH_ITLB write_c0_diag(4);
#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
#else
#define FLUSH_ITLB
#define FLUSH_ITLB_VM(vma)
#endif
void local_flush_tlb_all(void)
{
unsigned long flags;
unsigned long old_ctx;
int entry;
ENTER_CRITICAL(flags);
/* Save old context and create impossible VPN2 value */
old_ctx = read_c0_entryhi();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
entry = read_c0_wired();
/* Blast 'em all away. */
while (entry < current_cpu_data.tlbsize) {
/* Make sure all entries differ. */
write_c0_entryhi(UNIQUE_ENTRYHI(entry));
write_c0_index(entry);
mtc0_tlbw_hazard();
tlb_write_indexed();
entry++;
}
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
/* All entries common to a mm share an asid. To effectively flush
these entries, we just bump the asid. */
void local_flush_tlb_mm(struct mm_struct *mm)
{
int cpu;
preempt_disable();
cpu = smp_processor_id();
if (cpu_context(cpu, mm) != 0) {
drop_mmu_context(mm, cpu);
}
preempt_enable();
}
void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
struct mm_struct *mm = vma->vm_mm;
int cpu = smp_processor_id();
if (cpu_context(cpu, mm) != 0) {
unsigned long size, flags;
ENTER_CRITICAL(flags);
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
size = (size + 1) >> 1;
if (size <= current_cpu_data.tlbsize/2) {
int oldpid = read_c0_entryhi();
int newpid = cpu_asid(cpu, mm);
start &= (PAGE_MASK << 1);
end += ((PAGE_SIZE << 1) - 1);
end &= (PAGE_MASK << 1);
while (start < end) {
int idx;
write_c0_entryhi(start | newpid);
start += (PAGE_SIZE << 1);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
if (idx < 0)
continue;
/* Make sure all entries differ. */
write_c0_entryhi(UNIQUE_ENTRYHI(idx));
mtc0_tlbw_hazard();
tlb_write_indexed();
}
tlbw_use_hazard();
write_c0_entryhi(oldpid);
} else {
drop_mmu_context(mm, cpu);
}
FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
}
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
unsigned long size, flags;
ENTER_CRITICAL(flags);
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
size = (size + 1) >> 1;
if (size <= current_cpu_data.tlbsize / 2) {
int pid = read_c0_entryhi();
start &= (PAGE_MASK << 1);
end += ((PAGE_SIZE << 1) - 1);
end &= (PAGE_MASK << 1);
while (start < end) {
int idx;
write_c0_entryhi(start);
start += (PAGE_SIZE << 1);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
if (idx < 0)
continue;
/* Make sure all entries differ. */
write_c0_entryhi(UNIQUE_ENTRYHI(idx));
mtc0_tlbw_hazard();
tlb_write_indexed();
}
tlbw_use_hazard();
write_c0_entryhi(pid);
} else {
local_flush_tlb_all();
}
FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
int cpu = smp_processor_id();
if (cpu_context(cpu, vma->vm_mm) != 0) {
unsigned long flags;
int oldpid, newpid, idx;
newpid = cpu_asid(cpu, vma->vm_mm);
page &= (PAGE_MASK << 1);
ENTER_CRITICAL(flags);
oldpid = read_c0_entryhi();
write_c0_entryhi(page | newpid);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
if (idx < 0)
goto finish;
/* Make sure all entries differ. */
write_c0_entryhi(UNIQUE_ENTRYHI(idx));
mtc0_tlbw_hazard();
tlb_write_indexed();
tlbw_use_hazard();
finish:
write_c0_entryhi(oldpid);
FLUSH_ITLB_VM(vma);
EXIT_CRITICAL(flags);
}
}
/*
* This one is only used for pages with the global bit set so we don't care
* much about the ASID.
*/
void local_flush_tlb_one(unsigned long page)
{
unsigned long flags;
int oldpid, idx;
ENTER_CRITICAL(flags);
oldpid = read_c0_entryhi();
page &= (PAGE_MASK << 1);
write_c0_entryhi(page);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
if (idx >= 0) {
/* Make sure all entries differ. */
write_c0_entryhi(UNIQUE_ENTRYHI(idx));
mtc0_tlbw_hazard();
tlb_write_indexed();
tlbw_use_hazard();
}
write_c0_entryhi(oldpid);
FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
/*
* We will need multiple versions of update_mmu_cache(), one that just
* updates the TLB with the new pte(s), and another which also checks
* for the R4k "end of page" hardware bug and does the needy.
*/
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
unsigned long flags;
pgd_t *pgdp;
pud_t *pudp;
pmd_t *pmdp;
pte_t *ptep;
int idx, pid;
/*
* Handle debugger faulting in for debugee.
*/
if (current->active_mm != vma->vm_mm)
return;
ENTER_CRITICAL(flags);
pid = read_c0_entryhi() & ASID_MASK;
address &= (PAGE_MASK << 1);
write_c0_entryhi(address | pid);
pgdp = pgd_offset(vma->vm_mm, address);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
pudp = pud_offset(pgdp, address);
pmdp = pmd_offset(pudp, address);
idx = read_c0_index();
#ifdef CONFIG_HUGETLB_PAGE
/* this could be a huge page */
if (pmd_huge(*pmdp)) {
unsigned long lo;
write_c0_pagemask(PM_HUGE_MASK);
ptep = (pte_t *)pmdp;
lo = pte_to_entrylo(pte_val(*ptep));
write_c0_entrylo0(lo);
write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
mtc0_tlbw_hazard();
if (idx < 0)
tlb_write_random();
else
tlb_write_indexed();
write_c0_pagemask(PM_DEFAULT_MASK);
} else
#endif
{
ptep = pte_offset_map(pmdp, address);
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
write_c0_entrylo0(ptep->pte_high);
ptep++;
write_c0_entrylo1(ptep->pte_high);
#else
write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
#endif
mtc0_tlbw_hazard();
if (idx < 0)
tlb_write_random();
else
tlb_write_indexed();
}
tlbw_use_hazard();
FLUSH_ITLB_VM(vma);
EXIT_CRITICAL(flags);
}
void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
{
unsigned long flags;
unsigned long wired;
unsigned long old_pagemask;
unsigned long old_ctx;
ENTER_CRITICAL(flags);
/* Save old context and create impossible VPN2 value */
old_ctx = read_c0_entryhi();
old_pagemask = read_c0_pagemask();
wired = read_c0_wired();
write_c0_wired(wired + 1);
write_c0_index(wired);
tlbw_use_hazard(); /* What is the hazard here? */
write_c0_pagemask(pagemask);
write_c0_entryhi(entryhi);
write_c0_entrylo0(entrylo0);
write_c0_entrylo1(entrylo1);
mtc0_tlbw_hazard();
tlb_write_indexed();
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
tlbw_use_hazard(); /* What is the hazard here? */
write_c0_pagemask(old_pagemask);
local_flush_tlb_all();
EXIT_CRITICAL(flags);
}
/*
* Used for loading TLB entries before trap_init() has started, when we
* don't actually want to add a wired entry which remains throughout the
* lifetime of the system
*/
static int temp_tlb_entry __cpuinitdata;
__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
{
int ret = 0;
unsigned long flags;
unsigned long wired;
unsigned long old_pagemask;
unsigned long old_ctx;
ENTER_CRITICAL(flags);
/* Save old context and create impossible VPN2 value */
old_ctx = read_c0_entryhi();
old_pagemask = read_c0_pagemask();
wired = read_c0_wired();
if (--temp_tlb_entry < wired) {
printk(KERN_WARNING
"No TLB space left for add_temporary_entry\n");
ret = -ENOSPC;
goto out;
}
write_c0_index(temp_tlb_entry);
write_c0_pagemask(pagemask);
write_c0_entryhi(entryhi);
write_c0_entrylo0(entrylo0);
write_c0_entrylo1(entrylo1);
mtc0_tlbw_hazard();
tlb_write_indexed();
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
write_c0_pagemask(old_pagemask);
out:
EXIT_CRITICAL(flags);
return ret;
}
static int __cpuinitdata ntlb;
static int __init set_ntlb(char *str)
{
get_option(&str, &ntlb);
return 1;
}
__setup("ntlb=", set_ntlb);
void __cpuinit tlb_init(void)
{
/*
* You should never change this register:
* - On R4600 1.7 the tlbp never hits for pages smaller than
* the value in the c0_pagemask register.
* - The entire mm handling assumes the c0_pagemask register to
* be set to fixed-size pages.
*/
write_c0_pagemask(PM_DEFAULT_MASK);
write_c0_wired(0);
if (current_cpu_type() == CPU_R10000 ||
current_cpu_type() == CPU_R12000 ||
current_cpu_type() == CPU_R14000)
write_c0_framemask(0);
if (kernel_uses_smartmips_rixi) {
/*
* Enable the no read, no exec bits, and enable large virtual
* address.
*/
u32 pg = PG_RIE | PG_XIE;
#ifdef CONFIG_64BIT
pg |= PG_ELPA;
#endif
write_c0_pagegrain(pg);
}
temp_tlb_entry = current_cpu_data.tlbsize - 1;
/* From this point on the ARC firmware is dead. */
local_flush_tlb_all();
/* Did I tell you that ARC SUCKS? */
if (ntlb) {
if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
int wired = current_cpu_data.tlbsize - ntlb;
write_c0_wired(wired);
write_c0_index(wired-1);
printk("Restricting TLB to %d entries\n", ntlb);
} else
printk("Ignoring invalid argument ntlb=%d\n", ntlb);
}
build_tlb_refill_handler();
}
| gpl-2.0 |
1nv4d3r5/linux | drivers/net/ethernet/chelsio/cxgb/subr.c | 2480 | 31391 | /*****************************************************************************
* *
* File: subr.c *
* $Revision: 1.27 $ *
* $Date: 2005/06/22 01:08:36 $ *
* Description: *
* Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
* part of the Chelsio 10Gb Ethernet Driver. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License, version 2, as *
* published by the Free Software Foundation. *
* *
* You should have received a copy of the GNU General Public License along *
* with this program; if not, write to the Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
* *
* http://www.chelsio.com *
* *
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
* All rights reserved. *
* *
* Maintainers: maintainers@chelsio.com *
* *
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
* Tina Yang <tainay@chelsio.com> *
* Felix Marti <felix@chelsio.com> *
* Scott Bardone <sbardone@chelsio.com> *
* Kurt Ottaway <kottaway@chelsio.com> *
* Frank DiMambro <frank@chelsio.com> *
* *
* History: *
* *
****************************************************************************/
#include "common.h"
#include "elmer0.h"
#include "regs.h"
#include "gmac.h"
#include "cphy.h"
#include "sge.h"
#include "tp.h"
#include "espi.h"
/**
* t1_wait_op_done - wait until an operation is completed
* @adapter: the adapter performing the operation
* @reg: the register to check for completion
* @mask: a single-bit field within @reg that indicates completion
* @polarity: the value of the field when the operation is completed
* @attempts: number of check iterations
* @delay: delay in usecs between iterations
*
* Wait until an operation is completed by checking a bit in a register
* up to @attempts times. Returns %0 if the operation completes and %1
* otherwise.
*/
static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
int attempts, int delay)
{
while (1) {
u32 val = readl(adapter->regs + reg) & mask;
if (!!val == polarity)
return 0;
if (--attempts == 0)
return 1;
if (delay)
udelay(delay);
}
}
#define TPI_ATTEMPTS 50
/*
* Write a register over the TPI interface (unlocked and locked versions).
*/
int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
{
int tpi_busy;
writel(addr, adapter->regs + A_TPI_ADDR);
writel(value, adapter->regs + A_TPI_WR_DATA);
writel(F_TPIWR, adapter->regs + A_TPI_CSR);
tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
TPI_ATTEMPTS, 3);
if (tpi_busy)
pr_alert("%s: TPI write to 0x%x failed\n",
adapter->name, addr);
return tpi_busy;
}
int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
{
int ret;
spin_lock(&adapter->tpi_lock);
ret = __t1_tpi_write(adapter, addr, value);
spin_unlock(&adapter->tpi_lock);
return ret;
}
/*
* Read a register over the TPI interface (unlocked and locked versions).
*/
int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
{
int tpi_busy;
writel(addr, adapter->regs + A_TPI_ADDR);
writel(0, adapter->regs + A_TPI_CSR);
tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
TPI_ATTEMPTS, 3);
if (tpi_busy)
pr_alert("%s: TPI read from 0x%x failed\n",
adapter->name, addr);
else
*valp = readl(adapter->regs + A_TPI_RD_DATA);
return tpi_busy;
}
int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
{
int ret;
spin_lock(&adapter->tpi_lock);
ret = __t1_tpi_read(adapter, addr, valp);
spin_unlock(&adapter->tpi_lock);
return ret;
}
/*
* Set a TPI parameter.
*/
static void t1_tpi_par(adapter_t *adapter, u32 value)
{
writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
}
/*
* Called when a port's link settings change to propagate the new values to the
* associated PHY and MAC. After performing the common tasks it invokes an
* OS-specific handler.
*/
void t1_link_changed(adapter_t *adapter, int port_id)
{
int link_ok, speed, duplex, fc;
struct cphy *phy = adapter->port[port_id].phy;
struct link_config *lc = &adapter->port[port_id].link_config;
phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
lc->speed = speed < 0 ? SPEED_INVALID : speed;
lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
if (!(lc->requested_fc & PAUSE_AUTONEG))
fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
/* Set MAC speed, duplex, and flow control to match PHY. */
struct cmac *mac = adapter->port[port_id].mac;
mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
lc->fc = (unsigned char)fc;
}
t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
}
static int t1_pci_intr_handler(adapter_t *adapter)
{
u32 pcix_cause;
pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
if (pcix_cause) {
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
pcix_cause);
t1_fatal_err(adapter); /* PCI errors are fatal */
}
return 0;
}
#ifdef CONFIG_CHELSIO_T1_1G
#include "fpga_defs.h"
/*
* PHY interrupt handler for FPGA boards.
*/
static int fpga_phy_intr_handler(adapter_t *adapter)
{
int p;
u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
for_each_port(adapter, p)
if (cause & (1 << p)) {
struct cphy *phy = adapter->port[p].phy;
int phy_cause = phy->ops->interrupt_handler(phy);
if (phy_cause & cphy_cause_link_change)
t1_link_changed(adapter, p);
}
writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
return 0;
}
/*
* Slow path interrupt handler for FPGAs.
*/
static int fpga_slow_intr(adapter_t *adapter)
{
u32 cause = readl(adapter->regs + A_PL_CAUSE);
cause &= ~F_PL_INTR_SGE_DATA;
if (cause & F_PL_INTR_SGE_ERR)
t1_sge_intr_error_handler(adapter->sge);
if (cause & FPGA_PCIX_INTERRUPT_GMAC)
fpga_phy_intr_handler(adapter);
if (cause & FPGA_PCIX_INTERRUPT_TP) {
/*
* FPGA doesn't support MC4 interrupts and it requires
* this odd layer of indirection for MC5.
*/
u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
/* Clear TP interrupt */
writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
}
if (cause & FPGA_PCIX_INTERRUPT_PCIX)
t1_pci_intr_handler(adapter);
/* Clear the interrupts just processed. */
if (cause)
writel(cause, adapter->regs + A_PL_CAUSE);
return cause != 0;
}
#endif
/*
* Wait until Elmer's MI1 interface is ready for new operations.
*/
static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
{
int attempts = 100, busy;
do {
u32 val;
__t1_tpi_read(adapter, mi1_reg, &val);
busy = val & F_MI1_OP_BUSY;
if (busy)
udelay(10);
} while (busy && --attempts);
if (busy)
pr_alert("%s: MDIO operation timed out\n", adapter->name);
return busy;
}
/*
* MI1 MDIO initialization.
*/
static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
{
u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
if (!(bi->caps & SUPPORTED_10000baseT_Full))
val |= V_MI1_SOF(1);
t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
}
#if defined(CONFIG_CHELSIO_T1_1G)
/*
* Elmer MI1 MDIO read/write operations.
*/
static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr)
{
struct adapter *adapter = dev->ml_priv;
u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
unsigned int val;
spin_lock(&adapter->tpi_lock);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
__t1_tpi_write(adapter,
A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
spin_unlock(&adapter->tpi_lock);
return val;
}
static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr, u16 val)
{
struct adapter *adapter = dev->ml_priv;
u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
spin_lock(&adapter->tpi_lock);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
__t1_tpi_write(adapter,
A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
spin_unlock(&adapter->tpi_lock);
return 0;
}
static const struct mdio_ops mi1_mdio_ops = {
.init = mi1_mdio_init,
.read = mi1_mdio_read,
.write = mi1_mdio_write,
.mode_support = MDIO_SUPPORTS_C22
};
#endif
static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr)
{
struct adapter *adapter = dev->ml_priv;
u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
unsigned int val;
spin_lock(&adapter->tpi_lock);
/* Write the address we want. */
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
MI1_OP_INDIRECT_ADDRESS);
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
/* Write the operation we want. */
__t1_tpi_write(adapter,
A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
/* Read the data. */
__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
spin_unlock(&adapter->tpi_lock);
return val;
}
static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr,
int mmd_addr, u16 reg_addr, u16 val)
{
struct adapter *adapter = dev->ml_priv;
u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
spin_lock(&adapter->tpi_lock);
/* Write the address we want. */
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
MI1_OP_INDIRECT_ADDRESS);
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
/* Write the data. */
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
spin_unlock(&adapter->tpi_lock);
return 0;
}
static const struct mdio_ops mi1_mdio_ext_ops = {
.init = mi1_mdio_init,
.read = mi1_mdio_ext_read,
.write = mi1_mdio_ext_write,
.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
};
enum {
CH_BRD_T110_1CU,
CH_BRD_N110_1F,
CH_BRD_N210_1F,
CH_BRD_T210_1F,
CH_BRD_T210_1CU,
CH_BRD_N204_4CU,
};
static const struct board_info t1_board[] = {
{
.board = CHBT_BOARD_CHT110,
.port_number = 1,
.caps = SUPPORTED_10000baseT_Full,
.chip_term = CHBT_TERM_T1,
.chip_mac = CHBT_MAC_PM3393,
.chip_phy = CHBT_PHY_MY3126,
.clock_core = 125000000,
.clock_mc3 = 150000000,
.clock_mc4 = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 1,
.mdio_mdiinv = 1,
.mdio_mdc = 1,
.mdio_phybaseaddr = 1,
.gmac = &t1_pm3393_ops,
.gphy = &t1_my3126_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio T110 1x10GBase-CX4 TOE",
},
{
.board = CHBT_BOARD_N110,
.port_number = 1,
.caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
.chip_term = CHBT_TERM_T1,
.chip_mac = CHBT_MAC_PM3393,
.chip_phy = CHBT_PHY_88X2010,
.clock_core = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 1,
.mdio_phybaseaddr = 0,
.gmac = &t1_pm3393_ops,
.gphy = &t1_mv88x201x_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio N110 1x10GBaseX NIC",
},
{
.board = CHBT_BOARD_N210,
.port_number = 1,
.caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
.chip_term = CHBT_TERM_T2,
.chip_mac = CHBT_MAC_PM3393,
.chip_phy = CHBT_PHY_88X2010,
.clock_core = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 1,
.mdio_phybaseaddr = 0,
.gmac = &t1_pm3393_ops,
.gphy = &t1_mv88x201x_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio N210 1x10GBaseX NIC",
},
{
.board = CHBT_BOARD_CHT210,
.port_number = 1,
.caps = SUPPORTED_10000baseT_Full,
.chip_term = CHBT_TERM_T2,
.chip_mac = CHBT_MAC_PM3393,
.chip_phy = CHBT_PHY_88X2010,
.clock_core = 125000000,
.clock_mc3 = 133000000,
.clock_mc4 = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 1,
.mdio_phybaseaddr = 0,
.gmac = &t1_pm3393_ops,
.gphy = &t1_mv88x201x_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio T210 1x10GBaseX TOE",
},
{
.board = CHBT_BOARD_CHT210,
.port_number = 1,
.caps = SUPPORTED_10000baseT_Full,
.chip_term = CHBT_TERM_T2,
.chip_mac = CHBT_MAC_PM3393,
.chip_phy = CHBT_PHY_MY3126,
.clock_core = 125000000,
.clock_mc3 = 133000000,
.clock_mc4 = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 1,
.mdio_mdiinv = 1,
.mdio_mdc = 1,
.mdio_phybaseaddr = 1,
.gmac = &t1_pm3393_ops,
.gphy = &t1_my3126_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio T210 1x10GBase-CX4 TOE",
},
#ifdef CONFIG_CHELSIO_T1_1G
{
.board = CHBT_BOARD_CHN204,
.port_number = 4,
.caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
| SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
SUPPORTED_PAUSE | SUPPORTED_TP,
.chip_term = CHBT_TERM_T2,
.chip_mac = CHBT_MAC_VSC7321,
.chip_phy = CHBT_PHY_88E1111,
.clock_core = 100000000,
.espi_nports = 4,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 0,
.mdio_phybaseaddr = 4,
.gmac = &t1_vsc7326_ops,
.gphy = &t1_mv88e1xxx_ops,
.mdio_ops = &mi1_mdio_ops,
.desc = "Chelsio N204 4x100/1000BaseT NIC",
},
#endif
};
DEFINE_PCI_DEVICE_TABLE(t1_pci_tbl) = {
CH_DEVICE(8, 0, CH_BRD_T110_1CU),
CH_DEVICE(8, 1, CH_BRD_T110_1CU),
CH_DEVICE(7, 0, CH_BRD_N110_1F),
CH_DEVICE(10, 1, CH_BRD_N210_1F),
CH_DEVICE(11, 1, CH_BRD_T210_1F),
CH_DEVICE(14, 1, CH_BRD_T210_1CU),
CH_DEVICE(16, 1, CH_BRD_N204_4CU),
{ 0 }
};
MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
/*
* Return the board_info structure with a given index. Out-of-range indices
* return NULL.
*/
const struct board_info *t1_get_board_info(unsigned int board_id)
{
return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
}
struct chelsio_vpd_t {
u32 format_version;
u8 serial_number[16];
u8 mac_base_address[6];
u8 pad[2]; /* make multiple-of-4 size requirement explicit */
};
#define EEPROMSIZE (8 * 1024)
#define EEPROM_MAX_POLL 4
/*
* Read SEEPROM. A zero is written to the flag register when the address is
* written to the Control register. The hardware device will set the flag to a
* one when 4B have been transferred to the Data register.
*/
int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
{
int i = EEPROM_MAX_POLL;
u16 val;
u32 v;
if (addr >= EEPROMSIZE || (addr & 3))
return -EINVAL;
pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
do {
udelay(50);
pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
} while (!(val & F_VPD_OP_FLAG) && --i);
if (!(val & F_VPD_OP_FLAG)) {
pr_err("%s: reading EEPROM address 0x%x failed\n",
adapter->name, addr);
return -EIO;
}
pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
*data = cpu_to_le32(v);
return 0;
}
static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
{
int addr, ret = 0;
for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
ret = t1_seeprom_read(adapter, addr,
(__le32 *)((u8 *)vpd + addr));
return ret;
}
/*
* Read a port's MAC address from the VPD ROM.
*/
static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
{
struct chelsio_vpd_t vpd;
if (t1_eeprom_vpd_get(adapter, &vpd))
return 1;
memcpy(mac_addr, vpd.mac_base_address, 5);
mac_addr[5] = vpd.mac_base_address[5] + index;
return 0;
}
/*
* Set up the MAC/PHY according to the requested link settings.
*
* If the PHY can auto-negotiate first decide what to advertise, then
* enable/disable auto-negotiation as desired and reset.
*
* If the PHY does not auto-negotiate we just reset it.
*
* If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
* otherwise do it later based on the outcome of auto-negotiation.
*/
int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
{
unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
if (lc->supported & SUPPORTED_Autoneg) {
lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
if (fc) {
if (fc == ((PAUSE_RX | PAUSE_TX) &
(mac->adapter->params.nports < 2)))
lc->advertising |= ADVERTISED_PAUSE;
else {
lc->advertising |= ADVERTISED_ASYM_PAUSE;
if (fc == PAUSE_RX)
lc->advertising |= ADVERTISED_PAUSE;
}
}
phy->ops->advertise(phy, lc->advertising);
if (lc->autoneg == AUTONEG_DISABLE) {
lc->speed = lc->requested_speed;
lc->duplex = lc->requested_duplex;
lc->fc = (unsigned char)fc;
mac->ops->set_speed_duplex_fc(mac, lc->speed,
lc->duplex, fc);
/* Also disables autoneg */
phy->state = PHY_AUTONEG_RDY;
phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
phy->ops->reset(phy, 0);
} else {
phy->state = PHY_AUTONEG_EN;
phy->ops->autoneg_enable(phy); /* also resets PHY */
}
} else {
phy->state = PHY_AUTONEG_RDY;
mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
lc->fc = (unsigned char)fc;
phy->ops->reset(phy, 0);
}
return 0;
}
/*
* External interrupt handler for boards using elmer0.
*/
int t1_elmer0_ext_intr_handler(adapter_t *adapter)
{
struct cphy *phy;
int phy_cause;
u32 cause;
t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
switch (board_info(adapter)->board) {
#ifdef CONFIG_CHELSIO_T1_1G
case CHBT_BOARD_CHT204:
case CHBT_BOARD_CHT204E:
case CHBT_BOARD_CHN204:
case CHBT_BOARD_CHT204V: {
int i, port_bit;
for_each_port(adapter, i) {
port_bit = i + 1;
if (!(cause & (1 << port_bit)))
continue;
phy = adapter->port[i].phy;
phy_cause = phy->ops->interrupt_handler(phy);
if (phy_cause & cphy_cause_link_change)
t1_link_changed(adapter, i);
}
break;
}
case CHBT_BOARD_CHT101:
if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
phy = adapter->port[0].phy;
phy_cause = phy->ops->interrupt_handler(phy);
if (phy_cause & cphy_cause_link_change)
t1_link_changed(adapter, 0);
}
break;
case CHBT_BOARD_7500: {
int p;
/*
* Elmer0's interrupt cause isn't useful here because there is
* only one bit that can be set for all 4 ports. This means
* we are forced to check every PHY's interrupt status
* register to see who initiated the interrupt.
*/
for_each_port(adapter, p) {
phy = adapter->port[p].phy;
phy_cause = phy->ops->interrupt_handler(phy);
if (phy_cause & cphy_cause_link_change)
t1_link_changed(adapter, p);
}
break;
}
#endif
case CHBT_BOARD_CHT210:
case CHBT_BOARD_N210:
case CHBT_BOARD_N110:
if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
phy = adapter->port[0].phy;
phy_cause = phy->ops->interrupt_handler(phy);
if (phy_cause & cphy_cause_link_change)
t1_link_changed(adapter, 0);
}
break;
case CHBT_BOARD_8000:
case CHBT_BOARD_CHT110:
if (netif_msg_intr(adapter))
dev_dbg(&adapter->pdev->dev,
"External interrupt cause 0x%x\n", cause);
if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
struct cmac *mac = adapter->port[0].mac;
mac->ops->interrupt_handler(mac);
}
if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
u32 mod_detect;
t1_tpi_read(adapter,
A_ELMER0_GPI_STAT, &mod_detect);
if (netif_msg_link(adapter))
dev_info(&adapter->pdev->dev, "XPAK %s\n",
mod_detect ? "removed" : "inserted");
}
break;
}
t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
return 0;
}
/* Enables all interrupts. */
void t1_interrupts_enable(adapter_t *adapter)
{
unsigned int i;
adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
t1_sge_intr_enable(adapter->sge);
t1_tp_intr_enable(adapter->tp);
if (adapter->espi) {
adapter->slow_intr_mask |= F_PL_INTR_ESPI;
t1_espi_intr_enable(adapter->espi);
}
/* Enable MAC/PHY interrupts for each port. */
for_each_port(adapter, i) {
adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
}
/* Enable PCIX & external chip interrupts on ASIC boards. */
if (t1_is_asic(adapter)) {
u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
/* PCI-X interrupts */
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
0xffffffff);
adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
writel(pl_intr, adapter->regs + A_PL_ENABLE);
}
}
/* Disables all interrupts. */
void t1_interrupts_disable(adapter_t* adapter)
{
unsigned int i;
t1_sge_intr_disable(adapter->sge);
t1_tp_intr_disable(adapter->tp);
if (adapter->espi)
t1_espi_intr_disable(adapter->espi);
/* Disable MAC/PHY interrupts for each port. */
for_each_port(adapter, i) {
adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
}
/* Disable PCIX & external chip interrupts. */
if (t1_is_asic(adapter))
writel(0, adapter->regs + A_PL_ENABLE);
/* PCI-X interrupts */
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
adapter->slow_intr_mask = 0;
}
/* Clears all interrupts */
void t1_interrupts_clear(adapter_t* adapter)
{
unsigned int i;
t1_sge_intr_clear(adapter->sge);
t1_tp_intr_clear(adapter->tp);
if (adapter->espi)
t1_espi_intr_clear(adapter->espi);
/* Clear MAC/PHY interrupts for each port. */
for_each_port(adapter, i) {
adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
}
/* Enable interrupts for external devices. */
if (t1_is_asic(adapter)) {
u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
adapter->regs + A_PL_CAUSE);
}
/* PCI-X interrupts */
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
}
/*
* Slow path interrupt handler for ASICs.
*/
static int asic_slow_intr(adapter_t *adapter)
{
u32 cause = readl(adapter->regs + A_PL_CAUSE);
cause &= adapter->slow_intr_mask;
if (!cause)
return 0;
if (cause & F_PL_INTR_SGE_ERR)
t1_sge_intr_error_handler(adapter->sge);
if (cause & F_PL_INTR_TP)
t1_tp_intr_handler(adapter->tp);
if (cause & F_PL_INTR_ESPI)
t1_espi_intr_handler(adapter->espi);
if (cause & F_PL_INTR_PCIX)
t1_pci_intr_handler(adapter);
if (cause & F_PL_INTR_EXT)
t1_elmer0_ext_intr(adapter);
/* Clear the interrupts just processed. */
writel(cause, adapter->regs + A_PL_CAUSE);
readl(adapter->regs + A_PL_CAUSE); /* flush writes */
return 1;
}
int t1_slow_intr_handler(adapter_t *adapter)
{
#ifdef CONFIG_CHELSIO_T1_1G
if (!t1_is_asic(adapter))
return fpga_slow_intr(adapter);
#endif
return asic_slow_intr(adapter);
}
/* Power sequencing is a work-around for Intel's XPAKs. */
static void power_sequence_xpak(adapter_t* adapter)
{
u32 mod_detect;
u32 gpo;
/* Check for XPAK */
t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
if (!(ELMER0_GP_BIT5 & mod_detect)) {
/* XPAK is present */
t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
gpo |= ELMER0_GP_BIT18;
t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
}
}
int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
struct adapter_params *p)
{
p->chip_version = bi->chip_term;
p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
if (p->chip_version == CHBT_TERM_T1 ||
p->chip_version == CHBT_TERM_T2 ||
p->chip_version == CHBT_TERM_FPGA) {
u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
val = G_TP_PC_REV(val);
if (val == 2)
p->chip_revision = TERM_T1B;
else if (val == 3)
p->chip_revision = TERM_T2;
else
return -1;
} else
return -1;
return 0;
}
/*
* Enable board components other than the Chelsio chip, such as external MAC
* and PHY.
*/
static int board_init(adapter_t *adapter, const struct board_info *bi)
{
switch (bi->board) {
case CHBT_BOARD_8000:
case CHBT_BOARD_N110:
case CHBT_BOARD_N210:
case CHBT_BOARD_CHT210:
t1_tpi_par(adapter, 0xf);
t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
break;
case CHBT_BOARD_CHT110:
t1_tpi_par(adapter, 0xf);
t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
/* TBD XXX Might not need. This fixes a problem
* described in the Intel SR XPAK errata.
*/
power_sequence_xpak(adapter);
break;
#ifdef CONFIG_CHELSIO_T1_1G
case CHBT_BOARD_CHT204E:
/* add config space write here */
case CHBT_BOARD_CHT204:
case CHBT_BOARD_CHT204V:
case CHBT_BOARD_CHN204:
t1_tpi_par(adapter, 0xf);
t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
break;
case CHBT_BOARD_CHT101:
case CHBT_BOARD_7500:
t1_tpi_par(adapter, 0xf);
t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
break;
#endif
}
return 0;
}
/*
* Initialize and configure the Terminator HW modules. Note that external
* MAC and PHYs are initialized separately.
*/
int t1_init_hw_modules(adapter_t *adapter)
{
int err = -EIO;
const struct board_info *bi = board_info(adapter);
if (!bi->clock_mc4) {
u32 val = readl(adapter->regs + A_MC4_CFG);
writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
writel(F_M_BUS_ENABLE | F_TCAM_RESET,
adapter->regs + A_MC5_CONFIG);
}
if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
bi->espi_nports))
goto out_err;
if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
goto out_err;
err = t1_sge_configure(adapter->sge, &adapter->params.sge);
if (err)
goto out_err;
err = 0;
out_err:
return err;
}
/*
* Determine a card's PCI mode.
*/
static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
{
static const unsigned short speed_map[] = { 33, 66, 100, 133 };
u32 pci_mode;
pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
}
/*
* Release the structures holding the SW per-Terminator-HW-module state.
*/
void t1_free_sw_modules(adapter_t *adapter)
{
unsigned int i;
for_each_port(adapter, i) {
struct cmac *mac = adapter->port[i].mac;
struct cphy *phy = adapter->port[i].phy;
if (mac)
mac->ops->destroy(mac);
if (phy)
phy->ops->destroy(phy);
}
if (adapter->sge)
t1_sge_destroy(adapter->sge);
if (adapter->tp)
t1_tp_destroy(adapter->tp);
if (adapter->espi)
t1_espi_destroy(adapter->espi);
}
static void init_link_config(struct link_config *lc,
const struct board_info *bi)
{
lc->supported = bi->caps;
lc->requested_speed = lc->speed = SPEED_INVALID;
lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
if (lc->supported & SUPPORTED_Autoneg) {
lc->advertising = lc->supported;
lc->autoneg = AUTONEG_ENABLE;
lc->requested_fc |= PAUSE_AUTONEG;
} else {
lc->advertising = 0;
lc->autoneg = AUTONEG_DISABLE;
}
}
/*
* Allocate and initialize the data structures that hold the SW state of
* the Terminator HW modules.
*/
int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)
{
unsigned int i;
adapter->params.brd_info = bi;
adapter->params.nports = bi->port_number;
adapter->params.stats_update_period = bi->gmac->stats_update_period;
adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
if (!adapter->sge) {
pr_err("%s: SGE initialization failed\n",
adapter->name);
goto error;
}
if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
pr_err("%s: ESPI initialization failed\n",
adapter->name);
goto error;
}
adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
if (!adapter->tp) {
pr_err("%s: TP initialization failed\n",
adapter->name);
goto error;
}
board_init(adapter, bi);
bi->mdio_ops->init(adapter, bi);
if (bi->gphy->reset)
bi->gphy->reset(adapter);
if (bi->gmac->reset)
bi->gmac->reset(adapter);
for_each_port(adapter, i) {
u8 hw_addr[6];
struct cmac *mac;
int phy_addr = bi->mdio_phybaseaddr + i;
adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
phy_addr, bi->mdio_ops);
if (!adapter->port[i].phy) {
pr_err("%s: PHY %d initialization failed\n",
adapter->name, i);
goto error;
}
adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
if (!mac) {
pr_err("%s: MAC %d initialization failed\n",
adapter->name, i);
goto error;
}
/*
* Get the port's MAC addresses either from the EEPROM if one
* exists or the one hardcoded in the MAC.
*/
if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
mac->ops->macaddress_get(mac, hw_addr);
else if (vpd_macaddress_get(adapter, i, hw_addr)) {
pr_err("%s: could not read MAC address from VPD ROM\n",
adapter->port[i].dev->name);
goto error;
}
memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
init_link_config(&adapter->port[i].link_config, bi);
}
get_pci_mode(adapter, &adapter->params.pci);
t1_interrupts_clear(adapter);
return 0;
error:
t1_free_sw_modules(adapter);
return -1;
}
| gpl-2.0 |
touchpro/android_kernel_lge_voltuno | arch/arm/kernel/bios32.c | 4784 | 15535 | /*
* linux/arch/arm/kernel/bios32.c
*
* PCI bios-type initialisation for PCI machines
*
* Bits taken from various places.
*/
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/pci.h>
static int debug_pci;
/*
* We can't use pci_find_device() here since we are
* called from interrupt context.
*/
static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
u16 status;
/*
* ignore host bridge - we handle
* that separately
*/
if (dev->bus->number == 0 && dev->devfn == 0)
continue;
pci_read_config_word(dev, PCI_STATUS, &status);
if (status == 0xffff)
continue;
if ((status & status_mask) == 0)
continue;
/* clear the status errors */
pci_write_config_word(dev, PCI_STATUS, status & status_mask);
if (warn)
printk("(%s: %04X) ", pci_name(dev), status);
}
list_for_each_entry(dev, &bus->devices, bus_list)
if (dev->subordinate)
pcibios_bus_report_status(dev->subordinate, status_mask, warn);
}
void pcibios_report_status(u_int status_mask, int warn)
{
struct list_head *l;
list_for_each(l, &pci_root_buses) {
struct pci_bus *bus = pci_bus_b(l);
pcibios_bus_report_status(bus, status_mask, warn);
}
}
/*
* We don't use this to fix the device, but initialisation of it.
* It's not the correct use for this, but it works.
* Note that the arbiter/ISA bridge appears to be buggy, specifically in
* the following area:
* 1. park on CPU
* 2. ISA bridge ping-pong
* 3. ISA bridge master handling of target RETRY
*
* Bug 3 is responsible for the sound DMA grinding to a halt. We now
* live with bug 2.
*/
static void __devinit pci_fixup_83c553(struct pci_dev *dev)
{
/*
* Set memory region to start at address 0, and enable IO
*/
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
dev->resource[0].end -= dev->resource[0].start;
dev->resource[0].start = 0;
/*
* All memory requests from ISA to be channelled to PCI
*/
pci_write_config_byte(dev, 0x48, 0xff);
/*
* Enable ping-pong on bus master to ISA bridge transactions.
* This improves the sound DMA substantially. The fixed
* priority arbiter also helps (see below).
*/
pci_write_config_byte(dev, 0x42, 0x01);
/*
* Enable PCI retry
*/
pci_write_config_byte(dev, 0x40, 0x22);
/*
* We used to set the arbiter to "park on last master" (bit
* 1 set), but unfortunately the CyberPro does not park the
* bus. We must therefore park on CPU. Unfortunately, this
* may trigger yet another bug in the 553.
*/
pci_write_config_byte(dev, 0x83, 0x02);
/*
* Make the ISA DMA request lowest priority, and disable
* rotating priorities completely.
*/
pci_write_config_byte(dev, 0x80, 0x11);
pci_write_config_byte(dev, 0x81, 0x00);
/*
* Route INTA input to IRQ 11, and set IRQ11 to be level
* sensitive.
*/
pci_write_config_word(dev, 0x44, 0xb000);
outb(0x08, 0x4d1);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
static void __devinit pci_fixup_unassign(struct pci_dev *dev)
{
dev->resource[0].end -= dev->resource[0].start;
dev->resource[0].start = 0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
/*
* Prevent the PCI layer from seeing the resources allocated to this device
* if it is the host bridge by marking it as such. These resources are of
* no consequence to the PCI layer (they are handled elsewhere).
*/
static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
{
int i;
if (dev->devfn == 0) {
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
/*
* PCI IDE controllers use non-standard I/O port decoding, respect it.
*/
static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
{
struct resource *r;
int i;
if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
return;
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
r = dev->resource + i;
if ((r->start & ~0x80) == 0x374) {
r->start |= 2;
r->end = r->start;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
/*
* Put the DEC21142 to sleep
*/
static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
{
pci_write_config_dword(dev, 0x40, 0x80000000);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
/*
* The CY82C693 needs some rather major fixups to ensure that it does
* the right thing. Idea from the Alpha people, with a few additions.
*
* We ensure that the IDE base registers are set to 1f0/3f4 for the
* primary bus, and 170/374 for the secondary bus. Also, hide them
* from the PCI subsystem view as well so we won't try to perform
* our own auto-configuration on them.
*
* In addition, we ensure that the PCI IDE interrupts are routed to
* IRQ 14 and IRQ 15 respectively.
*
* The above gets us to a point where the IDE on this device is
* functional. However, The CY82C693U _does not work_ in bus
* master mode without locking the PCI bus solid.
*/
static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
{
if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
u32 base0, base1;
if (dev->class & 0x80) { /* primary */
base0 = 0x1f0;
base1 = 0x3f4;
} else { /* secondary */
base0 = 0x170;
base1 = 0x374;
}
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
base0 | PCI_BASE_ADDRESS_SPACE_IO);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
base1 | PCI_BASE_ADDRESS_SPACE_IO);
dev->resource[0].start = 0;
dev->resource[0].end = 0;
dev->resource[0].flags = 0;
dev->resource[1].start = 0;
dev->resource[1].end = 0;
dev->resource[1].flags = 0;
} else if (PCI_FUNC(dev->devfn) == 0) {
/*
* Setup IDE IRQ routing.
*/
pci_write_config_byte(dev, 0x4b, 14);
pci_write_config_byte(dev, 0x4c, 15);
/*
* Disable FREQACK handshake, enable USB.
*/
pci_write_config_byte(dev, 0x4d, 0x41);
/*
* Enable PCI retry, and PCI post-write buffer.
*/
pci_write_config_byte(dev, 0x44, 0x17);
/*
* Enable ISA master and DMA post write buffering.
*/
pci_write_config_byte(dev, 0x45, 0x03);
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
static void __init pci_fixup_it8152(struct pci_dev *dev)
{
int i;
/* fixup for ITE 8152 devices */
/* FIXME: add defines for class 0x68000 and 0x80103 */
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
dev->class == 0x68000 ||
dev->class == 0x80103) {
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
{
if (debug_pci)
printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
/*
* If the bus contains any of these devices, then we must not turn on
* parity checking of any kind. Currently this is CyberPro 20x0 only.
*/
static inline int pdev_bad_for_parity(struct pci_dev *dev)
{
return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
(dev->vendor == PCI_VENDOR_ID_ITE &&
dev->device == PCI_DEVICE_ID_ITE_8152));
}
/*
* pcibios_fixup_bus - Called after each bus is probed,
* but before its children are examined.
*/
void pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev;
u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
/*
* Walk the devices on this bus, working out what we can
* and can't support.
*/
list_for_each_entry(dev, &bus->devices, bus_list) {
u16 status;
pci_read_config_word(dev, PCI_STATUS, &status);
/*
* If any device on this bus does not support fast back
* to back transfers, then the bus as a whole is not able
* to support them. Having fast back to back transfers
* on saves us one PCI cycle per transaction.
*/
if (!(status & PCI_STATUS_FAST_BACK))
features &= ~PCI_COMMAND_FAST_BACK;
if (pdev_bad_for_parity(dev))
features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
switch (dev->class >> 8) {
case PCI_CLASS_BRIDGE_PCI:
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
break;
case PCI_CLASS_BRIDGE_CARDBUS:
pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
break;
}
}
/*
* Now walk the devices again, this time setting them up.
*/
list_for_each_entry(dev, &bus->devices, bus_list) {
u16 cmd;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd |= features;
pci_write_config_word(dev, PCI_COMMAND, cmd);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
L1_CACHE_BYTES >> 2);
}
/*
* Propagate the flags to the PCI bridge.
*/
if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
if (features & PCI_COMMAND_FAST_BACK)
bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
if (features & PCI_COMMAND_PARITY)
bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
}
/*
* Report what we did for this bus
*/
printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
}
#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_fixup_bus);
#endif
/*
* Swizzle the device pin each time we cross a bridge.
* This might update pin and returns the slot number.
*/
static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
{
struct pci_sys_data *sys = dev->sysdata;
int slot = 0, oldpin = *pin;
if (sys->swizzle)
slot = sys->swizzle(dev, pin);
if (debug_pci)
printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
pci_name(dev), oldpin, *pin, slot);
return slot;
}
/*
* Map a slot/pin to an IRQ.
*/
static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pci_sys_data *sys = dev->sysdata;
int irq = -1;
if (sys->map_irq)
irq = sys->map_irq(dev, slot, pin);
if (debug_pci)
printk("PCI: %s mapping slot %d pin %d => irq %d\n",
pci_name(dev), slot, pin, irq);
return irq;
}
static void __init pcibios_init_hw(struct hw_pci *hw)
{
struct pci_sys_data *sys = NULL;
int ret;
int nr, busnr;
for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
if (!sys)
panic("PCI: unable to allocate sys data!");
#ifdef CONFIG_PCI_DOMAINS
sys->domain = hw->domain;
#endif
sys->hw = hw;
sys->busnr = busnr;
sys->swizzle = hw->swizzle;
sys->map_irq = hw->map_irq;
INIT_LIST_HEAD(&sys->resources);
ret = hw->setup(nr, sys);
if (ret > 0) {
if (list_empty(&sys->resources)) {
pci_add_resource_offset(&sys->resources,
&ioport_resource, sys->io_offset);
pci_add_resource_offset(&sys->resources,
&iomem_resource, sys->mem_offset);
}
sys->bus = hw->scan(nr, sys);
if (!sys->bus)
panic("PCI: unable to scan bus!");
busnr = sys->bus->subordinate + 1;
list_add(&sys->node, &hw->buses);
} else {
kfree(sys);
if (ret < 0)
break;
}
}
}
void __init pci_common_init(struct hw_pci *hw)
{
struct pci_sys_data *sys;
INIT_LIST_HEAD(&hw->buses);
pci_add_flags(PCI_REASSIGN_ALL_RSRC);
if (hw->preinit)
hw->preinit();
pcibios_init_hw(hw);
if (hw->postinit)
hw->postinit();
pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
list_for_each_entry(sys, &hw->buses, node) {
struct pci_bus *bus = sys->bus;
if (!pci_has_flag(PCI_PROBE_ONLY)) {
/*
* Size the bridge windows.
*/
pci_bus_size_bridges(bus);
/*
* Assign resources.
*/
pci_bus_assign_resources(bus);
/*
* Enable bridges
*/
pci_enable_bridges(bus);
}
/*
* Tell drivers about devices found.
*/
pci_bus_add_devices(bus);
}
}
#ifndef CONFIG_PCI_HOST_ITE8152
void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
}
#endif
char * __init pcibios_setup(char *str)
{
if (!strcmp(str, "debug")) {
debug_pci = 1;
return NULL;
} else if (!strcmp(str, "firmware")) {
pci_add_flags(PCI_PROBE_ONLY);
return NULL;
}
return str;
}
/*
* From arch/i386/kernel/pci-i386.c:
*
* We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the
* addresses to be allocated in the 0x000-0x0ff region
* modulo 0x400.
*
* Why? Because some silly external IO cards only decode
* the low 10 bits of the IO address. The 0x00-0xff region
* is reserved for motherboard devices that decode all 16
* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
* but we want to try to avoid allocating at 0x2900-0x2bff
* which might be mirrored at 0x0100-0x03ff..
*/
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
{
resource_size_t start = res->start;
if (res->flags & IORESOURCE_IO && start & 0x300)
start = (start + 0x3ff) & ~0x3ff;
start = (start + align - 1) & ~(align - 1);
return start;
}
/**
* pcibios_enable_device - Enable I/O and memory.
* @dev: PCI device to be enabled
*/
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int idx;
struct resource *r;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx = 0; idx < 6; idx++) {
/* Only set up the requested stuff */
if (!(mask & (1 << idx)))
continue;
r = dev->resource + idx;
if (!r->start && r->end) {
printk(KERN_ERR "PCI: Device %s not available because"
" of resource collisions\n", pci_name(dev));
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
/*
* Bridges (eg, cardbus bridges) need to be fully enabled
*/
if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
if (cmd != old_cmd) {
printk("PCI: enabling device %s (%04x -> %04x)\n",
pci_name(dev), old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
}
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state, int write_combine)
{
struct pci_sys_data *root = dev->sysdata;
unsigned long phys;
if (mmap_state == pci_mmap_io) {
return -EINVAL;
} else {
phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
}
/*
* Mark this as IO
*/
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
if (remap_pfn_range(vma, vma->vm_start, phys,
vma->vm_end - vma->vm_start,
vma->vm_page_prot))
return -EAGAIN;
return 0;
}
| gpl-2.0 |
yoyoliyang/linux-sunxi | fs/yaffs2/yaffs_nand.c | 7856 | 3100 | /*
* YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
*
* Copyright (C) 2002-2010 Aleph One Ltd.
* for Toby Churchill Ltd and Brightstar Engineering
*
* Created by Charles Manning <charles@aleph1.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "yaffs_nand.h"
#include "yaffs_tagscompat.h"
#include "yaffs_tagsvalidity.h"
#include "yaffs_getblockinfo.h"
int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk,
u8 * buffer, struct yaffs_ext_tags *tags)
{
int result;
struct yaffs_ext_tags local_tags;
int realigned_chunk = nand_chunk - dev->chunk_offset;
dev->n_page_reads++;
/* If there are no tags provided, use local tags to get prioritised gc working */
if (!tags)
tags = &local_tags;
if (dev->param.read_chunk_tags_fn)
result =
dev->param.read_chunk_tags_fn(dev, realigned_chunk, buffer,
tags);
else
result = yaffs_tags_compat_rd(dev,
realigned_chunk, buffer, tags);
if (tags && tags->ecc_result > YAFFS_ECC_RESULT_NO_ERROR) {
struct yaffs_block_info *bi;
bi = yaffs_get_block_info(dev,
nand_chunk /
dev->param.chunks_per_block);
yaffs_handle_chunk_error(dev, bi);
}
return result;
}
int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev,
int nand_chunk,
const u8 * buffer, struct yaffs_ext_tags *tags)
{
dev->n_page_writes++;
nand_chunk -= dev->chunk_offset;
if (tags) {
tags->seq_number = dev->seq_number;
tags->chunk_used = 1;
if (!yaffs_validate_tags(tags)) {
yaffs_trace(YAFFS_TRACE_ERROR, "Writing uninitialised tags");
YBUG();
}
yaffs_trace(YAFFS_TRACE_WRITE,
"Writing chunk %d tags %d %d",
nand_chunk, tags->obj_id, tags->chunk_id);
} else {
yaffs_trace(YAFFS_TRACE_ERROR, "Writing with no tags");
YBUG();
}
if (dev->param.write_chunk_tags_fn)
return dev->param.write_chunk_tags_fn(dev, nand_chunk, buffer,
tags);
else
return yaffs_tags_compat_wr(dev, nand_chunk, buffer, tags);
}
int yaffs_mark_bad(struct yaffs_dev *dev, int block_no)
{
block_no -= dev->block_offset;
if (dev->param.bad_block_fn)
return dev->param.bad_block_fn(dev, block_no);
else
return yaffs_tags_compat_mark_bad(dev, block_no);
}
int yaffs_query_init_block_state(struct yaffs_dev *dev,
int block_no,
enum yaffs_block_state *state,
u32 * seq_number)
{
block_no -= dev->block_offset;
if (dev->param.query_block_fn)
return dev->param.query_block_fn(dev, block_no, state,
seq_number);
else
return yaffs_tags_compat_query_block(dev, block_no,
state, seq_number);
}
int yaffs_erase_block(struct yaffs_dev *dev, int flash_block)
{
int result;
flash_block -= dev->block_offset;
dev->n_erasures++;
result = dev->param.erase_fn(dev, flash_block);
return result;
}
int yaffs_init_nand(struct yaffs_dev *dev)
{
if (dev->param.initialise_flash_fn)
return dev->param.initialise_flash_fn(dev);
return YAFFS_OK;
}
| gpl-2.0 |
rudij7/android_kernel_oneplus_one | arch/parisc/lib/iomap.c | 8880 | 10309 | /*
* iomap.c - Implement iomap interface for PA-RISC
* Copyright (c) 2004 Matthew Wilcox
*/
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/export.h>
#include <asm/io.h>
/*
* The iomap space on 32-bit PA-RISC is intended to look like this:
* 00000000-7fffffff virtual mapped IO
* 80000000-8fffffff ISA/EISA port space that can't be virtually mapped
* 90000000-9fffffff Dino port space
* a0000000-afffffff Astro port space
* b0000000-bfffffff PAT port space
* c0000000-cfffffff non-swapped memory IO
* f0000000-ffffffff legacy IO memory pointers
*
* For the moment, here's what it looks like:
* 80000000-8fffffff All ISA/EISA port space
* f0000000-ffffffff legacy IO memory pointers
*
* On 64-bit, everything is extended, so:
* 8000000000000000-8fffffffffffffff All ISA/EISA port space
* f000000000000000-ffffffffffffffff legacy IO memory pointers
*/
/*
* Technically, this should be 'if (VMALLOC_START < addr < VMALLOC_END),
* but that's slow and we know it'll be within the first 2GB.
*/
#ifdef CONFIG_64BIT
#define INDIRECT_ADDR(addr) (((unsigned long)(addr) & 1UL<<63) != 0)
#define ADDR_TO_REGION(addr) (((unsigned long)addr >> 60) & 7)
#define IOPORT_MAP_BASE (8UL << 60)
#else
#define INDIRECT_ADDR(addr) (((unsigned long)(addr) & 1UL<<31) != 0)
#define ADDR_TO_REGION(addr) (((unsigned long)addr >> 28) & 7)
#define IOPORT_MAP_BASE (8UL << 28)
#endif
struct iomap_ops {
unsigned int (*read8)(void __iomem *);
unsigned int (*read16)(void __iomem *);
unsigned int (*read16be)(void __iomem *);
unsigned int (*read32)(void __iomem *);
unsigned int (*read32be)(void __iomem *);
void (*write8)(u8, void __iomem *);
void (*write16)(u16, void __iomem *);
void (*write16be)(u16, void __iomem *);
void (*write32)(u32, void __iomem *);
void (*write32be)(u32, void __iomem *);
void (*read8r)(void __iomem *, void *, unsigned long);
void (*read16r)(void __iomem *, void *, unsigned long);
void (*read32r)(void __iomem *, void *, unsigned long);
void (*write8r)(void __iomem *, const void *, unsigned long);
void (*write16r)(void __iomem *, const void *, unsigned long);
void (*write32r)(void __iomem *, const void *, unsigned long);
};
/* Generic ioport ops. To be replaced later by specific dino/elroy/wax code */
#define ADDR2PORT(addr) ((unsigned long __force)(addr) & 0xffffff)
static unsigned int ioport_read8(void __iomem *addr)
{
return inb(ADDR2PORT(addr));
}
static unsigned int ioport_read16(void __iomem *addr)
{
return inw(ADDR2PORT(addr));
}
static unsigned int ioport_read32(void __iomem *addr)
{
return inl(ADDR2PORT(addr));
}
static void ioport_write8(u8 datum, void __iomem *addr)
{
outb(datum, ADDR2PORT(addr));
}
static void ioport_write16(u16 datum, void __iomem *addr)
{
outw(datum, ADDR2PORT(addr));
}
static void ioport_write32(u32 datum, void __iomem *addr)
{
outl(datum, ADDR2PORT(addr));
}
static void ioport_read8r(void __iomem *addr, void *dst, unsigned long count)
{
insb(ADDR2PORT(addr), dst, count);
}
static void ioport_read16r(void __iomem *addr, void *dst, unsigned long count)
{
insw(ADDR2PORT(addr), dst, count);
}
static void ioport_read32r(void __iomem *addr, void *dst, unsigned long count)
{
insl(ADDR2PORT(addr), dst, count);
}
static void ioport_write8r(void __iomem *addr, const void *s, unsigned long n)
{
outsb(ADDR2PORT(addr), s, n);
}
static void ioport_write16r(void __iomem *addr, const void *s, unsigned long n)
{
outsw(ADDR2PORT(addr), s, n);
}
static void ioport_write32r(void __iomem *addr, const void *s, unsigned long n)
{
outsl(ADDR2PORT(addr), s, n);
}
static const struct iomap_ops ioport_ops = {
ioport_read8,
ioport_read16,
ioport_read16,
ioport_read32,
ioport_read32,
ioport_write8,
ioport_write16,
ioport_write16,
ioport_write32,
ioport_write32,
ioport_read8r,
ioport_read16r,
ioport_read32r,
ioport_write8r,
ioport_write16r,
ioport_write32r,
};
/* Legacy I/O memory ops */
static unsigned int iomem_read8(void __iomem *addr)
{
return readb(addr);
}
static unsigned int iomem_read16(void __iomem *addr)
{
return readw(addr);
}
static unsigned int iomem_read16be(void __iomem *addr)
{
return __raw_readw(addr);
}
static unsigned int iomem_read32(void __iomem *addr)
{
return readl(addr);
}
static unsigned int iomem_read32be(void __iomem *addr)
{
return __raw_readl(addr);
}
static void iomem_write8(u8 datum, void __iomem *addr)
{
writeb(datum, addr);
}
static void iomem_write16(u16 datum, void __iomem *addr)
{
writew(datum, addr);
}
static void iomem_write16be(u16 datum, void __iomem *addr)
{
__raw_writew(datum, addr);
}
static void iomem_write32(u32 datum, void __iomem *addr)
{
writel(datum, addr);
}
static void iomem_write32be(u32 datum, void __iomem *addr)
{
__raw_writel(datum, addr);
}
static void iomem_read8r(void __iomem *addr, void *dst, unsigned long count)
{
while (count--) {
*(u8 *)dst = __raw_readb(addr);
dst++;
}
}
static void iomem_read16r(void __iomem *addr, void *dst, unsigned long count)
{
while (count--) {
*(u16 *)dst = __raw_readw(addr);
dst += 2;
}
}
static void iomem_read32r(void __iomem *addr, void *dst, unsigned long count)
{
while (count--) {
*(u32 *)dst = __raw_readl(addr);
dst += 4;
}
}
static void iomem_write8r(void __iomem *addr, const void *s, unsigned long n)
{
while (n--) {
__raw_writeb(*(u8 *)s, addr);
s++;
}
}
static void iomem_write16r(void __iomem *addr, const void *s, unsigned long n)
{
while (n--) {
__raw_writew(*(u16 *)s, addr);
s += 2;
}
}
static void iomem_write32r(void __iomem *addr, const void *s, unsigned long n)
{
while (n--) {
__raw_writel(*(u32 *)s, addr);
s += 4;
}
}
static const struct iomap_ops iomem_ops = {
iomem_read8,
iomem_read16,
iomem_read16be,
iomem_read32,
iomem_read32be,
iomem_write8,
iomem_write16,
iomem_write16be,
iomem_write32,
iomem_write32be,
iomem_read8r,
iomem_read16r,
iomem_read32r,
iomem_write8r,
iomem_write16r,
iomem_write32r,
};
static const struct iomap_ops *iomap_ops[8] = {
[0] = &ioport_ops,
[7] = &iomem_ops
};
unsigned int ioread8(void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr)))
return iomap_ops[ADDR_TO_REGION(addr)]->read8(addr);
return *((u8 *)addr);
}
unsigned int ioread16(void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr)))
return iomap_ops[ADDR_TO_REGION(addr)]->read16(addr);
return le16_to_cpup((u16 *)addr);
}
unsigned int ioread16be(void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr)))
return iomap_ops[ADDR_TO_REGION(addr)]->read16be(addr);
return *((u16 *)addr);
}
unsigned int ioread32(void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr)))
return iomap_ops[ADDR_TO_REGION(addr)]->read32(addr);
return le32_to_cpup((u32 *)addr);
}
unsigned int ioread32be(void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr)))
return iomap_ops[ADDR_TO_REGION(addr)]->read32be(addr);
return *((u32 *)addr);
}
void iowrite8(u8 datum, void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write8(datum, addr);
} else {
*((u8 *)addr) = datum;
}
}
void iowrite16(u16 datum, void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write16(datum, addr);
} else {
*((u16 *)addr) = cpu_to_le16(datum);
}
}
void iowrite16be(u16 datum, void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write16be(datum, addr);
} else {
*((u16 *)addr) = datum;
}
}
void iowrite32(u32 datum, void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write32(datum, addr);
} else {
*((u32 *)addr) = cpu_to_le32(datum);
}
}
void iowrite32be(u32 datum, void __iomem *addr)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write32be(datum, addr);
} else {
*((u32 *)addr) = datum;
}
}
/* Repeating interfaces */
void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->read8r(addr, dst, count);
} else {
while (count--) {
*(u8 *)dst = *(u8 *)addr;
dst++;
}
}
}
void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->read16r(addr, dst, count);
} else {
while (count--) {
*(u16 *)dst = *(u16 *)addr;
dst += 2;
}
}
}
void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->read32r(addr, dst, count);
} else {
while (count--) {
*(u32 *)dst = *(u32 *)addr;
dst += 4;
}
}
}
void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write8r(addr, src, count);
} else {
while (count--) {
*(u8 *)addr = *(u8 *)src;
src++;
}
}
}
void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write16r(addr, src, count);
} else {
while (count--) {
*(u16 *)addr = *(u16 *)src;
src += 2;
}
}
}
void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
{
if (unlikely(INDIRECT_ADDR(addr))) {
iomap_ops[ADDR_TO_REGION(addr)]->write32r(addr, src, count);
} else {
while (count--) {
*(u32 *)addr = *(u32 *)src;
src += 4;
}
}
}
/* Mapping interfaces */
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *)(IOPORT_MAP_BASE | port);
}
void ioport_unmap(void __iomem *addr)
{
if (!INDIRECT_ADDR(addr)) {
iounmap(addr);
}
}
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
{
if (!INDIRECT_ADDR(addr)) {
iounmap(addr);
}
}
EXPORT_SYMBOL(ioread8);
EXPORT_SYMBOL(ioread16);
EXPORT_SYMBOL(ioread16be);
EXPORT_SYMBOL(ioread32);
EXPORT_SYMBOL(ioread32be);
EXPORT_SYMBOL(iowrite8);
EXPORT_SYMBOL(iowrite16);
EXPORT_SYMBOL(iowrite16be);
EXPORT_SYMBOL(iowrite32);
EXPORT_SYMBOL(iowrite32be);
EXPORT_SYMBOL(ioread8_rep);
EXPORT_SYMBOL(ioread16_rep);
EXPORT_SYMBOL(ioread32_rep);
EXPORT_SYMBOL(iowrite8_rep);
EXPORT_SYMBOL(iowrite16_rep);
EXPORT_SYMBOL(iowrite32_rep);
EXPORT_SYMBOL(ioport_map);
EXPORT_SYMBOL(ioport_unmap);
EXPORT_SYMBOL(pci_iounmap);
| gpl-2.0 |
HelllGuest/boom_kernel_sprout_kk | net/netfilter/xt_ecn.c | 9392 | 4541 | /*
* Xtables module for matching the value of the IPv4/IPv6 and TCP ECN bits
*
* (C) 2002 by Harald Welte <laforge@gnumonks.org>
* (C) 2011 Patrick McHardy <kaber@trash.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/in.h>
#include <linux/ip.h>
#include <net/ip.h>
#include <linux/module.h>
#include <linux/skbuff.h>
#include <linux/tcp.h>
#include <linux/netfilter/x_tables.h>
#include <linux/netfilter/xt_ecn.h>
#include <linux/netfilter_ipv4/ip_tables.h>
#include <linux/netfilter_ipv6/ip6_tables.h>
MODULE_AUTHOR("Harald Welte <laforge@netfilter.org>");
MODULE_DESCRIPTION("Xtables: Explicit Congestion Notification (ECN) flag match");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ipt_ecn");
MODULE_ALIAS("ip6t_ecn");
static bool match_tcp(const struct sk_buff *skb, struct xt_action_param *par)
{
const struct xt_ecn_info *einfo = par->matchinfo;
struct tcphdr _tcph;
const struct tcphdr *th;
/* In practice, TCP match does this, so can't fail. But let's
* be good citizens.
*/
th = skb_header_pointer(skb, par->thoff, sizeof(_tcph), &_tcph);
if (th == NULL)
return false;
if (einfo->operation & XT_ECN_OP_MATCH_ECE) {
if (einfo->invert & XT_ECN_OP_MATCH_ECE) {
if (th->ece == 1)
return false;
} else {
if (th->ece == 0)
return false;
}
}
if (einfo->operation & XT_ECN_OP_MATCH_CWR) {
if (einfo->invert & XT_ECN_OP_MATCH_CWR) {
if (th->cwr == 1)
return false;
} else {
if (th->cwr == 0)
return false;
}
}
return true;
}
static inline bool match_ip(const struct sk_buff *skb,
const struct xt_ecn_info *einfo)
{
return ((ip_hdr(skb)->tos & XT_ECN_IP_MASK) == einfo->ip_ect) ^
!!(einfo->invert & XT_ECN_OP_MATCH_IP);
}
static bool ecn_mt4(const struct sk_buff *skb, struct xt_action_param *par)
{
const struct xt_ecn_info *info = par->matchinfo;
if (info->operation & XT_ECN_OP_MATCH_IP && !match_ip(skb, info))
return false;
if (info->operation & (XT_ECN_OP_MATCH_ECE | XT_ECN_OP_MATCH_CWR) &&
!match_tcp(skb, par))
return false;
return true;
}
static int ecn_mt_check4(const struct xt_mtchk_param *par)
{
const struct xt_ecn_info *info = par->matchinfo;
const struct ipt_ip *ip = par->entryinfo;
if (info->operation & XT_ECN_OP_MATCH_MASK)
return -EINVAL;
if (info->invert & XT_ECN_OP_MATCH_MASK)
return -EINVAL;
if (info->operation & (XT_ECN_OP_MATCH_ECE | XT_ECN_OP_MATCH_CWR) &&
(ip->proto != IPPROTO_TCP || ip->invflags & IPT_INV_PROTO)) {
pr_info("cannot match TCP bits in rule for non-tcp packets\n");
return -EINVAL;
}
return 0;
}
static inline bool match_ipv6(const struct sk_buff *skb,
const struct xt_ecn_info *einfo)
{
return (((ipv6_hdr(skb)->flow_lbl[0] >> 4) & XT_ECN_IP_MASK) ==
einfo->ip_ect) ^
!!(einfo->invert & XT_ECN_OP_MATCH_IP);
}
static bool ecn_mt6(const struct sk_buff *skb, struct xt_action_param *par)
{
const struct xt_ecn_info *info = par->matchinfo;
if (info->operation & XT_ECN_OP_MATCH_IP && !match_ipv6(skb, info))
return false;
if (info->operation & (XT_ECN_OP_MATCH_ECE | XT_ECN_OP_MATCH_CWR) &&
!match_tcp(skb, par))
return false;
return true;
}
static int ecn_mt_check6(const struct xt_mtchk_param *par)
{
const struct xt_ecn_info *info = par->matchinfo;
const struct ip6t_ip6 *ip = par->entryinfo;
if (info->operation & XT_ECN_OP_MATCH_MASK)
return -EINVAL;
if (info->invert & XT_ECN_OP_MATCH_MASK)
return -EINVAL;
if (info->operation & (XT_ECN_OP_MATCH_ECE | XT_ECN_OP_MATCH_CWR) &&
(ip->proto != IPPROTO_TCP || ip->invflags & IP6T_INV_PROTO)) {
pr_info("cannot match TCP bits in rule for non-tcp packets\n");
return -EINVAL;
}
return 0;
}
static struct xt_match ecn_mt_reg[] __read_mostly = {
{
.name = "ecn",
.family = NFPROTO_IPV4,
.match = ecn_mt4,
.matchsize = sizeof(struct xt_ecn_info),
.checkentry = ecn_mt_check4,
.me = THIS_MODULE,
},
{
.name = "ecn",
.family = NFPROTO_IPV6,
.match = ecn_mt6,
.matchsize = sizeof(struct xt_ecn_info),
.checkentry = ecn_mt_check6,
.me = THIS_MODULE,
},
};
static int __init ecn_mt_init(void)
{
return xt_register_matches(ecn_mt_reg, ARRAY_SIZE(ecn_mt_reg));
}
static void __exit ecn_mt_exit(void)
{
xt_unregister_matches(ecn_mt_reg, ARRAY_SIZE(ecn_mt_reg));
}
module_init(ecn_mt_init);
module_exit(ecn_mt_exit);
| gpl-2.0 |
OneEducation/kernel-rk310-lollipop-firefly | arch/x86/boot/video.c | 12464 | 7286 | /* -*- linux-c -*- ------------------------------------------------------- *
*
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright 2007 rPath, Inc. - All Rights Reserved
* Copyright 2009 Intel Corporation; author H. Peter Anvin
*
* This file is part of the Linux kernel, and is made available under
* the terms of the GNU General Public License version 2.
*
* ----------------------------------------------------------------------- */
/*
* Select video mode
*/
#include "boot.h"
#include "video.h"
#include "vesa.h"
static void store_cursor_position(void)
{
struct biosregs ireg, oreg;
initregs(&ireg);
ireg.ah = 0x03;
intcall(0x10, &ireg, &oreg);
boot_params.screen_info.orig_x = oreg.dl;
boot_params.screen_info.orig_y = oreg.dh;
if (oreg.ch & 0x20)
boot_params.screen_info.flags |= VIDEO_FLAGS_NOCURSOR;
if ((oreg.ch & 0x1f) > (oreg.cl & 0x1f))
boot_params.screen_info.flags |= VIDEO_FLAGS_NOCURSOR;
}
static void store_video_mode(void)
{
struct biosregs ireg, oreg;
/* N.B.: the saving of the video page here is a bit silly,
since we pretty much assume page 0 everywhere. */
initregs(&ireg);
ireg.ah = 0x0f;
intcall(0x10, &ireg, &oreg);
/* Not all BIOSes are clean with respect to the top bit */
boot_params.screen_info.orig_video_mode = oreg.al & 0x7f;
boot_params.screen_info.orig_video_page = oreg.bh;
}
/*
* Store the video mode parameters for later usage by the kernel.
* This is done by asking the BIOS except for the rows/columns
* parameters in the default 80x25 mode -- these are set directly,
* because some very obscure BIOSes supply insane values.
*/
static void store_mode_params(void)
{
u16 font_size;
int x, y;
/* For graphics mode, it is up to the mode-setting driver
(currently only video-vesa.c) to store the parameters */
if (graphic_mode)
return;
store_cursor_position();
store_video_mode();
if (boot_params.screen_info.orig_video_mode == 0x07) {
/* MDA, HGC, or VGA in monochrome mode */
video_segment = 0xb000;
} else {
/* CGA, EGA, VGA and so forth */
video_segment = 0xb800;
}
set_fs(0);
font_size = rdfs16(0x485); /* Font size, BIOS area */
boot_params.screen_info.orig_video_points = font_size;
x = rdfs16(0x44a);
y = (adapter == ADAPTER_CGA) ? 25 : rdfs8(0x484)+1;
if (force_x)
x = force_x;
if (force_y)
y = force_y;
boot_params.screen_info.orig_video_cols = x;
boot_params.screen_info.orig_video_lines = y;
}
static unsigned int get_entry(void)
{
char entry_buf[4];
int i, len = 0;
int key;
unsigned int v;
do {
key = getchar();
if (key == '\b') {
if (len > 0) {
puts("\b \b");
len--;
}
} else if ((key >= '0' && key <= '9') ||
(key >= 'A' && key <= 'Z') ||
(key >= 'a' && key <= 'z')) {
if (len < sizeof entry_buf) {
entry_buf[len++] = key;
putchar(key);
}
}
} while (key != '\r');
putchar('\n');
if (len == 0)
return VIDEO_CURRENT_MODE; /* Default */
v = 0;
for (i = 0; i < len; i++) {
v <<= 4;
key = entry_buf[i] | 0x20;
v += (key > '9') ? key-'a'+10 : key-'0';
}
return v;
}
static void display_menu(void)
{
struct card_info *card;
struct mode_info *mi;
char ch;
int i;
int nmodes;
int modes_per_line;
int col;
nmodes = 0;
for (card = video_cards; card < video_cards_end; card++)
nmodes += card->nmodes;
modes_per_line = 1;
if (nmodes >= 20)
modes_per_line = 3;
for (col = 0; col < modes_per_line; col++)
puts("Mode: Resolution: Type: ");
putchar('\n');
col = 0;
ch = '0';
for (card = video_cards; card < video_cards_end; card++) {
mi = card->modes;
for (i = 0; i < card->nmodes; i++, mi++) {
char resbuf[32];
int visible = mi->x && mi->y;
u16 mode_id = mi->mode ? mi->mode :
(mi->y << 8)+mi->x;
if (!visible)
continue; /* Hidden mode */
if (mi->depth)
sprintf(resbuf, "%dx%d", mi->y, mi->depth);
else
sprintf(resbuf, "%d", mi->y);
printf("%c %03X %4dx%-7s %-6s",
ch, mode_id, mi->x, resbuf, card->card_name);
col++;
if (col >= modes_per_line) {
putchar('\n');
col = 0;
}
if (ch == '9')
ch = 'a';
else if (ch == 'z' || ch == ' ')
ch = ' '; /* Out of keys... */
else
ch++;
}
}
if (col)
putchar('\n');
}
#define H(x) ((x)-'a'+10)
#define SCAN ((H('s')<<12)+(H('c')<<8)+(H('a')<<4)+H('n'))
static unsigned int mode_menu(void)
{
int key;
unsigned int sel;
puts("Press <ENTER> to see video modes available, "
"<SPACE> to continue, or wait 30 sec\n");
kbd_flush();
while (1) {
key = getchar_timeout();
if (key == ' ' || key == 0)
return VIDEO_CURRENT_MODE; /* Default */
if (key == '\r')
break;
putchar('\a'); /* Beep! */
}
for (;;) {
display_menu();
puts("Enter a video mode or \"scan\" to scan for "
"additional modes: ");
sel = get_entry();
if (sel != SCAN)
return sel;
probe_cards(1);
}
}
/* Save screen content to the heap */
static struct saved_screen {
int x, y;
int curx, cury;
u16 *data;
} saved;
static void save_screen(void)
{
/* Should be called after store_mode_params() */
saved.x = boot_params.screen_info.orig_video_cols;
saved.y = boot_params.screen_info.orig_video_lines;
saved.curx = boot_params.screen_info.orig_x;
saved.cury = boot_params.screen_info.orig_y;
if (!heap_free(saved.x*saved.y*sizeof(u16)+512))
return; /* Not enough heap to save the screen */
saved.data = GET_HEAP(u16, saved.x*saved.y);
set_fs(video_segment);
copy_from_fs(saved.data, 0, saved.x*saved.y*sizeof(u16));
}
static void restore_screen(void)
{
/* Should be called after store_mode_params() */
int xs = boot_params.screen_info.orig_video_cols;
int ys = boot_params.screen_info.orig_video_lines;
int y;
addr_t dst = 0;
u16 *src = saved.data;
struct biosregs ireg;
if (graphic_mode)
return; /* Can't restore onto a graphic mode */
if (!src)
return; /* No saved screen contents */
/* Restore screen contents */
set_fs(video_segment);
for (y = 0; y < ys; y++) {
int npad;
if (y < saved.y) {
int copy = (xs < saved.x) ? xs : saved.x;
copy_to_fs(dst, src, copy*sizeof(u16));
dst += copy*sizeof(u16);
src += saved.x;
npad = (xs < saved.x) ? 0 : xs-saved.x;
} else {
npad = xs;
}
/* Writes "npad" blank characters to
video_segment:dst and advances dst */
asm volatile("pushw %%es ; "
"movw %2,%%es ; "
"shrw %%cx ; "
"jnc 1f ; "
"stosw \n\t"
"1: rep;stosl ; "
"popw %%es"
: "+D" (dst), "+c" (npad)
: "bdS" (video_segment),
"a" (0x07200720));
}
/* Restore cursor position */
if (saved.curx >= xs)
saved.curx = xs-1;
if (saved.cury >= ys)
saved.cury = ys-1;
initregs(&ireg);
ireg.ah = 0x02; /* Set cursor position */
ireg.dh = saved.cury;
ireg.dl = saved.curx;
intcall(0x10, &ireg, NULL);
store_cursor_position();
}
void set_video(void)
{
u16 mode = boot_params.hdr.vid_mode;
RESET_HEAP();
store_mode_params();
save_screen();
probe_cards(0);
for (;;) {
if (mode == ASK_VGA)
mode = mode_menu();
if (!set_mode(mode))
break;
printf("Undefined video mode number: %x\n", mode);
mode = ASK_VGA;
}
boot_params.hdr.vid_mode = mode;
vesa_store_edid();
store_mode_params();
if (do_restore)
restore_screen();
}
| gpl-2.0 |
Tepira/linux-sunxi | lib/xz/xz_crc32.c | 13232 | 1261 | /*
* CRC32 using the polynomial from IEEE-802.3
*
* Authors: Lasse Collin <lasse.collin@tukaani.org>
* Igor Pavlov <http://7-zip.org/>
*
* This file has been put into the public domain.
* You can do whatever you want with this file.
*/
/*
* This is not the fastest implementation, but it is pretty compact.
* The fastest versions of xz_crc32() on modern CPUs without hardware
* accelerated CRC instruction are 3-5 times as fast as this version,
* but they are bigger and use more memory for the lookup table.
*/
#include "xz_private.h"
/*
* STATIC_RW_DATA is used in the pre-boot environment on some architectures.
* See <linux/decompress/mm.h> for details.
*/
#ifndef STATIC_RW_DATA
# define STATIC_RW_DATA static
#endif
STATIC_RW_DATA uint32_t xz_crc32_table[256];
XZ_EXTERN void xz_crc32_init(void)
{
const uint32_t poly = 0xEDB88320;
uint32_t i;
uint32_t j;
uint32_t r;
for (i = 0; i < 256; ++i) {
r = i;
for (j = 0; j < 8; ++j)
r = (r >> 1) ^ (poly & ~((r & 1) - 1));
xz_crc32_table[i] = r;
}
return;
}
XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc)
{
crc = ~crc;
while (size != 0) {
crc = xz_crc32_table[*buf++ ^ (crc & 0xFF)] ^ (crc >> 8);
--size;
}
return ~crc;
}
| gpl-2.0 |
HeydayGuan/linux-3.6.7 | drivers/platform/x86/hp-wmi.c | 177 | 22817 | /*
* HP WMI hotkeys
*
* Copyright (C) 2008 Red Hat <mjg@redhat.com>
* Copyright (C) 2010, 2011 Anssi Hannula <anssi.hannula@iki.fi>
*
* Portions based on wistron_btns.c:
* Copyright (C) 2005 Miloslav Trmac <mitr@volny.cz>
* Copyright (C) 2005 Bernhard Rosenkraenzer <bero@arklinux.org>
* Copyright (C) 2005 Dmitry Torokhov <dtor@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/input.h>
#include <linux/input/sparse-keymap.h>
#include <linux/platform_device.h>
#include <linux/acpi.h>
#include <linux/rfkill.h>
#include <linux/string.h>
MODULE_AUTHOR("Matthew Garrett <mjg59@srcf.ucam.org>");
MODULE_DESCRIPTION("HP laptop WMI hotkeys driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("wmi:95F24279-4D7B-4334-9387-ACCDC67EF61C");
MODULE_ALIAS("wmi:5FB7F034-2C63-45e9-BE91-3D44E2C707E4");
#define HPWMI_EVENT_GUID "95F24279-4D7B-4334-9387-ACCDC67EF61C"
#define HPWMI_BIOS_GUID "5FB7F034-2C63-45e9-BE91-3D44E2C707E4"
#define HPWMI_DISPLAY_QUERY 0x1
#define HPWMI_HDDTEMP_QUERY 0x2
#define HPWMI_ALS_QUERY 0x3
#define HPWMI_HARDWARE_QUERY 0x4
#define HPWMI_WIRELESS_QUERY 0x5
#define HPWMI_HOTKEY_QUERY 0xc
#define HPWMI_WIRELESS2_QUERY 0x1b
enum hp_wmi_radio {
HPWMI_WIFI = 0,
HPWMI_BLUETOOTH = 1,
HPWMI_WWAN = 2,
};
enum hp_wmi_event_ids {
HPWMI_DOCK_EVENT = 1,
HPWMI_PARK_HDD = 2,
HPWMI_SMART_ADAPTER = 3,
HPWMI_BEZEL_BUTTON = 4,
HPWMI_WIRELESS = 5,
HPWMI_CPU_BATTERY_THROTTLE = 6,
HPWMI_LOCK_SWITCH = 7,
};
static int __devinit hp_wmi_bios_setup(struct platform_device *device);
static int __exit hp_wmi_bios_remove(struct platform_device *device);
static int hp_wmi_resume_handler(struct device *device);
struct bios_args {
u32 signature;
u32 command;
u32 commandtype;
u32 datasize;
u32 data;
};
struct bios_return {
u32 sigpass;
u32 return_code;
};
enum hp_return_value {
HPWMI_RET_WRONG_SIGNATURE = 0x02,
HPWMI_RET_UNKNOWN_COMMAND = 0x03,
HPWMI_RET_UNKNOWN_CMDTYPE = 0x04,
HPWMI_RET_INVALID_PARAMETERS = 0x05,
};
enum hp_wireless2_bits {
HPWMI_POWER_STATE = 0x01,
HPWMI_POWER_SOFT = 0x02,
HPWMI_POWER_BIOS = 0x04,
HPWMI_POWER_HARD = 0x08,
};
#define IS_HWBLOCKED(x) ((x & (HPWMI_POWER_BIOS | HPWMI_POWER_HARD)) \
!= (HPWMI_POWER_BIOS | HPWMI_POWER_HARD))
#define IS_SWBLOCKED(x) !(x & HPWMI_POWER_SOFT)
struct bios_rfkill2_device_state {
u8 radio_type;
u8 bus_type;
u16 vendor_id;
u16 product_id;
u16 subsys_vendor_id;
u16 subsys_product_id;
u8 rfkill_id;
u8 power;
u8 unknown[4];
};
/* 7 devices fit into the 128 byte buffer */
#define HPWMI_MAX_RFKILL2_DEVICES 7
struct bios_rfkill2_state {
u8 unknown[7];
u8 count;
u8 pad[8];
struct bios_rfkill2_device_state device[HPWMI_MAX_RFKILL2_DEVICES];
};
static const struct key_entry hp_wmi_keymap[] = {
{ KE_KEY, 0x02, { KEY_BRIGHTNESSUP } },
{ KE_KEY, 0x03, { KEY_BRIGHTNESSDOWN } },
{ KE_KEY, 0x20e6, { KEY_PROG1 } },
{ KE_KEY, 0x20e8, { KEY_MEDIA } },
{ KE_KEY, 0x2142, { KEY_MEDIA } },
{ KE_KEY, 0x213b, { KEY_INFO } },
{ KE_KEY, 0x2169, { KEY_DIRECTION } },
{ KE_KEY, 0x231b, { KEY_HELP } },
{ KE_END, 0 }
};
static struct input_dev *hp_wmi_input_dev;
static struct platform_device *hp_wmi_platform_dev;
static struct rfkill *wifi_rfkill;
static struct rfkill *bluetooth_rfkill;
static struct rfkill *wwan_rfkill;
struct rfkill2_device {
u8 id;
int num;
struct rfkill *rfkill;
};
static int rfkill2_count;
static struct rfkill2_device rfkill2[HPWMI_MAX_RFKILL2_DEVICES];
static const struct dev_pm_ops hp_wmi_pm_ops = {
.resume = hp_wmi_resume_handler,
.restore = hp_wmi_resume_handler,
};
static struct platform_driver hp_wmi_driver = {
.driver = {
.name = "hp-wmi",
.owner = THIS_MODULE,
.pm = &hp_wmi_pm_ops,
},
.probe = hp_wmi_bios_setup,
.remove = hp_wmi_bios_remove,
};
/*
* hp_wmi_perform_query
*
* query: The commandtype -> What should be queried
* write: The command -> 0 read, 1 write, 3 ODM specific
* buffer: Buffer used as input and/or output
* insize: Size of input buffer
* outsize: Size of output buffer
*
* returns zero on success
* an HP WMI query specific error code (which is positive)
* -EINVAL if the query was not successful at all
* -EINVAL if the output buffer size exceeds buffersize
*
* Note: The buffersize must at least be the maximum of the input and output
* size. E.g. Battery info query (0x7) is defined to have 1 byte input
* and 128 byte output. The caller would do:
* buffer = kzalloc(128, GFP_KERNEL);
* ret = hp_wmi_perform_query(0x7, 0, buffer, 1, 128)
*/
static int hp_wmi_perform_query(int query, int write, void *buffer,
int insize, int outsize)
{
struct bios_return *bios_return;
int actual_outsize;
union acpi_object *obj;
struct bios_args args = {
.signature = 0x55434553,
.command = write ? 0x2 : 0x1,
.commandtype = query,
.datasize = insize,
.data = 0,
};
struct acpi_buffer input = { sizeof(struct bios_args), &args };
struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
u32 rc;
if (WARN_ON(insize > sizeof(args.data)))
return -EINVAL;
memcpy(&args.data, buffer, insize);
wmi_evaluate_method(HPWMI_BIOS_GUID, 0, 0x3, &input, &output);
obj = output.pointer;
if (!obj)
return -EINVAL;
else if (obj->type != ACPI_TYPE_BUFFER) {
kfree(obj);
return -EINVAL;
}
bios_return = (struct bios_return *)obj->buffer.pointer;
rc = bios_return->return_code;
if (rc) {
if (rc != HPWMI_RET_UNKNOWN_CMDTYPE)
pr_warn("query 0x%x returned error 0x%x\n", query, rc);
kfree(obj);
return rc;
}
if (!outsize) {
/* ignore output data */
kfree(obj);
return 0;
}
actual_outsize = min(outsize, (int)(obj->buffer.length - sizeof(*bios_return)));
memcpy(buffer, obj->buffer.pointer + sizeof(*bios_return), actual_outsize);
memset(buffer + actual_outsize, 0, outsize - actual_outsize);
kfree(obj);
return 0;
}
static int hp_wmi_display_state(void)
{
int state = 0;
int ret = hp_wmi_perform_query(HPWMI_DISPLAY_QUERY, 0, &state,
sizeof(state), sizeof(state));
if (ret)
return -EINVAL;
return state;
}
static int hp_wmi_hddtemp_state(void)
{
int state = 0;
int ret = hp_wmi_perform_query(HPWMI_HDDTEMP_QUERY, 0, &state,
sizeof(state), sizeof(state));
if (ret)
return -EINVAL;
return state;
}
static int hp_wmi_als_state(void)
{
int state = 0;
int ret = hp_wmi_perform_query(HPWMI_ALS_QUERY, 0, &state,
sizeof(state), sizeof(state));
if (ret)
return -EINVAL;
return state;
}
static int hp_wmi_dock_state(void)
{
int state = 0;
int ret = hp_wmi_perform_query(HPWMI_HARDWARE_QUERY, 0, &state,
sizeof(state), sizeof(state));
if (ret)
return -EINVAL;
return state & 0x1;
}
static int hp_wmi_tablet_state(void)
{
int state = 0;
int ret = hp_wmi_perform_query(HPWMI_HARDWARE_QUERY, 0, &state,
sizeof(state), sizeof(state));
if (ret)
return ret;
return (state & 0x4) ? 1 : 0;
}
static int hp_wmi_set_block(void *data, bool blocked)
{
enum hp_wmi_radio r = (enum hp_wmi_radio) data;
int query = BIT(r + 8) | ((!blocked) << r);
int ret;
ret = hp_wmi_perform_query(HPWMI_WIRELESS_QUERY, 1,
&query, sizeof(query), 0);
if (ret)
return -EINVAL;
return 0;
}
static const struct rfkill_ops hp_wmi_rfkill_ops = {
.set_block = hp_wmi_set_block,
};
static bool hp_wmi_get_sw_state(enum hp_wmi_radio r)
{
int wireless = 0;
int mask;
hp_wmi_perform_query(HPWMI_WIRELESS_QUERY, 0,
&wireless, sizeof(wireless),
sizeof(wireless));
/* TBD: Pass error */
mask = 0x200 << (r * 8);
if (wireless & mask)
return false;
else
return true;
}
static bool hp_wmi_get_hw_state(enum hp_wmi_radio r)
{
int wireless = 0;
int mask;
hp_wmi_perform_query(HPWMI_WIRELESS_QUERY, 0,
&wireless, sizeof(wireless),
sizeof(wireless));
/* TBD: Pass error */
mask = 0x800 << (r * 8);
if (wireless & mask)
return false;
else
return true;
}
static int hp_wmi_rfkill2_set_block(void *data, bool blocked)
{
int rfkill_id = (int)(long)data;
char buffer[4] = { 0x01, 0x00, rfkill_id, !blocked };
if (hp_wmi_perform_query(HPWMI_WIRELESS2_QUERY, 1,
buffer, sizeof(buffer), 0))
return -EINVAL;
return 0;
}
static const struct rfkill_ops hp_wmi_rfkill2_ops = {
.set_block = hp_wmi_rfkill2_set_block,
};
static int hp_wmi_rfkill2_refresh(void)
{
int err, i;
struct bios_rfkill2_state state;
err = hp_wmi_perform_query(HPWMI_WIRELESS2_QUERY, 0, &state,
0, sizeof(state));
if (err)
return err;
for (i = 0; i < rfkill2_count; i++) {
int num = rfkill2[i].num;
struct bios_rfkill2_device_state *devstate;
devstate = &state.device[num];
if (num >= state.count ||
devstate->rfkill_id != rfkill2[i].id) {
pr_warn("power configuration of the wireless devices unexpectedly changed\n");
continue;
}
rfkill_set_states(rfkill2[i].rfkill,
IS_SWBLOCKED(devstate->power),
IS_HWBLOCKED(devstate->power));
}
return 0;
}
static ssize_t show_display(struct device *dev, struct device_attribute *attr,
char *buf)
{
int value = hp_wmi_display_state();
if (value < 0)
return -EINVAL;
return sprintf(buf, "%d\n", value);
}
static ssize_t show_hddtemp(struct device *dev, struct device_attribute *attr,
char *buf)
{
int value = hp_wmi_hddtemp_state();
if (value < 0)
return -EINVAL;
return sprintf(buf, "%d\n", value);
}
static ssize_t show_als(struct device *dev, struct device_attribute *attr,
char *buf)
{
int value = hp_wmi_als_state();
if (value < 0)
return -EINVAL;
return sprintf(buf, "%d\n", value);
}
static ssize_t show_dock(struct device *dev, struct device_attribute *attr,
char *buf)
{
int value = hp_wmi_dock_state();
if (value < 0)
return -EINVAL;
return sprintf(buf, "%d\n", value);
}
static ssize_t show_tablet(struct device *dev, struct device_attribute *attr,
char *buf)
{
int value = hp_wmi_tablet_state();
if (value < 0)
return -EINVAL;
return sprintf(buf, "%d\n", value);
}
static ssize_t set_als(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
u32 tmp = simple_strtoul(buf, NULL, 10);
int ret = hp_wmi_perform_query(HPWMI_ALS_QUERY, 1, &tmp,
sizeof(tmp), sizeof(tmp));
if (ret)
return -EINVAL;
return count;
}
static DEVICE_ATTR(display, S_IRUGO, show_display, NULL);
static DEVICE_ATTR(hddtemp, S_IRUGO, show_hddtemp, NULL);
static DEVICE_ATTR(als, S_IRUGO | S_IWUSR, show_als, set_als);
static DEVICE_ATTR(dock, S_IRUGO, show_dock, NULL);
static DEVICE_ATTR(tablet, S_IRUGO, show_tablet, NULL);
static void hp_wmi_notify(u32 value, void *context)
{
struct acpi_buffer response = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *obj;
u32 event_id, event_data;
int key_code = 0, ret;
u32 *location;
acpi_status status;
status = wmi_get_event_data(value, &response);
if (status != AE_OK) {
pr_info("bad event status 0x%x\n", status);
return;
}
obj = (union acpi_object *)response.pointer;
if (!obj)
return;
if (obj->type != ACPI_TYPE_BUFFER) {
pr_info("Unknown response received %d\n", obj->type);
kfree(obj);
return;
}
/*
* Depending on ACPI version the concatenation of id and event data
* inside _WED function will result in a 8 or 16 byte buffer.
*/
location = (u32 *)obj->buffer.pointer;
if (obj->buffer.length == 8) {
event_id = *location;
event_data = *(location + 1);
} else if (obj->buffer.length == 16) {
event_id = *location;
event_data = *(location + 2);
} else {
pr_info("Unknown buffer length %d\n", obj->buffer.length);
kfree(obj);
return;
}
kfree(obj);
switch (event_id) {
case HPWMI_DOCK_EVENT:
input_report_switch(hp_wmi_input_dev, SW_DOCK,
hp_wmi_dock_state());
input_report_switch(hp_wmi_input_dev, SW_TABLET_MODE,
hp_wmi_tablet_state());
input_sync(hp_wmi_input_dev);
break;
case HPWMI_PARK_HDD:
break;
case HPWMI_SMART_ADAPTER:
break;
case HPWMI_BEZEL_BUTTON:
ret = hp_wmi_perform_query(HPWMI_HOTKEY_QUERY, 0,
&key_code,
sizeof(key_code),
sizeof(key_code));
if (ret)
break;
if (!sparse_keymap_report_event(hp_wmi_input_dev,
key_code, 1, true))
pr_info("Unknown key code - 0x%x\n", key_code);
break;
case HPWMI_WIRELESS:
if (rfkill2_count) {
hp_wmi_rfkill2_refresh();
break;
}
if (wifi_rfkill)
rfkill_set_states(wifi_rfkill,
hp_wmi_get_sw_state(HPWMI_WIFI),
hp_wmi_get_hw_state(HPWMI_WIFI));
if (bluetooth_rfkill)
rfkill_set_states(bluetooth_rfkill,
hp_wmi_get_sw_state(HPWMI_BLUETOOTH),
hp_wmi_get_hw_state(HPWMI_BLUETOOTH));
if (wwan_rfkill)
rfkill_set_states(wwan_rfkill,
hp_wmi_get_sw_state(HPWMI_WWAN),
hp_wmi_get_hw_state(HPWMI_WWAN));
break;
case HPWMI_CPU_BATTERY_THROTTLE:
pr_info("Unimplemented CPU throttle because of 3 Cell battery event detected\n");
break;
case HPWMI_LOCK_SWITCH:
break;
default:
pr_info("Unknown event_id - %d - 0x%x\n", event_id, event_data);
break;
}
}
static int __init hp_wmi_input_setup(void)
{
acpi_status status;
int err;
hp_wmi_input_dev = input_allocate_device();
if (!hp_wmi_input_dev)
return -ENOMEM;
hp_wmi_input_dev->name = "HP WMI hotkeys";
hp_wmi_input_dev->phys = "wmi/input0";
hp_wmi_input_dev->id.bustype = BUS_HOST;
__set_bit(EV_SW, hp_wmi_input_dev->evbit);
__set_bit(SW_DOCK, hp_wmi_input_dev->swbit);
__set_bit(SW_TABLET_MODE, hp_wmi_input_dev->swbit);
err = sparse_keymap_setup(hp_wmi_input_dev, hp_wmi_keymap, NULL);
if (err)
goto err_free_dev;
/* Set initial hardware state */
input_report_switch(hp_wmi_input_dev, SW_DOCK, hp_wmi_dock_state());
input_report_switch(hp_wmi_input_dev, SW_TABLET_MODE,
hp_wmi_tablet_state());
input_sync(hp_wmi_input_dev);
status = wmi_install_notify_handler(HPWMI_EVENT_GUID, hp_wmi_notify, NULL);
if (ACPI_FAILURE(status)) {
err = -EIO;
goto err_free_keymap;
}
err = input_register_device(hp_wmi_input_dev);
if (err)
goto err_uninstall_notifier;
return 0;
err_uninstall_notifier:
wmi_remove_notify_handler(HPWMI_EVENT_GUID);
err_free_keymap:
sparse_keymap_free(hp_wmi_input_dev);
err_free_dev:
input_free_device(hp_wmi_input_dev);
return err;
}
static void hp_wmi_input_destroy(void)
{
wmi_remove_notify_handler(HPWMI_EVENT_GUID);
sparse_keymap_free(hp_wmi_input_dev);
input_unregister_device(hp_wmi_input_dev);
}
static void cleanup_sysfs(struct platform_device *device)
{
device_remove_file(&device->dev, &dev_attr_display);
device_remove_file(&device->dev, &dev_attr_hddtemp);
device_remove_file(&device->dev, &dev_attr_als);
device_remove_file(&device->dev, &dev_attr_dock);
device_remove_file(&device->dev, &dev_attr_tablet);
}
static int __devinit hp_wmi_rfkill_setup(struct platform_device *device)
{
int err;
int wireless = 0;
err = hp_wmi_perform_query(HPWMI_WIRELESS_QUERY, 0, &wireless,
sizeof(wireless), sizeof(wireless));
if (err)
return err;
if (wireless & 0x1) {
wifi_rfkill = rfkill_alloc("hp-wifi", &device->dev,
RFKILL_TYPE_WLAN,
&hp_wmi_rfkill_ops,
(void *) HPWMI_WIFI);
if (!wifi_rfkill)
return -ENOMEM;
rfkill_init_sw_state(wifi_rfkill,
hp_wmi_get_sw_state(HPWMI_WIFI));
rfkill_set_hw_state(wifi_rfkill,
hp_wmi_get_hw_state(HPWMI_WIFI));
err = rfkill_register(wifi_rfkill);
if (err)
goto register_wifi_error;
}
if (wireless & 0x2) {
bluetooth_rfkill = rfkill_alloc("hp-bluetooth", &device->dev,
RFKILL_TYPE_BLUETOOTH,
&hp_wmi_rfkill_ops,
(void *) HPWMI_BLUETOOTH);
if (!bluetooth_rfkill) {
err = -ENOMEM;
goto register_wifi_error;
}
rfkill_init_sw_state(bluetooth_rfkill,
hp_wmi_get_sw_state(HPWMI_BLUETOOTH));
rfkill_set_hw_state(bluetooth_rfkill,
hp_wmi_get_hw_state(HPWMI_BLUETOOTH));
err = rfkill_register(bluetooth_rfkill);
if (err)
goto register_bluetooth_error;
}
if (wireless & 0x4) {
wwan_rfkill = rfkill_alloc("hp-wwan", &device->dev,
RFKILL_TYPE_WWAN,
&hp_wmi_rfkill_ops,
(void *) HPWMI_WWAN);
if (!wwan_rfkill) {
err = -ENOMEM;
goto register_bluetooth_error;
}
rfkill_init_sw_state(wwan_rfkill,
hp_wmi_get_sw_state(HPWMI_WWAN));
rfkill_set_hw_state(wwan_rfkill,
hp_wmi_get_hw_state(HPWMI_WWAN));
err = rfkill_register(wwan_rfkill);
if (err)
goto register_wwan_err;
}
return 0;
register_wwan_err:
rfkill_destroy(wwan_rfkill);
wwan_rfkill = NULL;
if (bluetooth_rfkill)
rfkill_unregister(bluetooth_rfkill);
register_bluetooth_error:
rfkill_destroy(bluetooth_rfkill);
bluetooth_rfkill = NULL;
if (wifi_rfkill)
rfkill_unregister(wifi_rfkill);
register_wifi_error:
rfkill_destroy(wifi_rfkill);
wifi_rfkill = NULL;
return err;
}
static int __devinit hp_wmi_rfkill2_setup(struct platform_device *device)
{
int err, i;
struct bios_rfkill2_state state;
err = hp_wmi_perform_query(HPWMI_WIRELESS2_QUERY, 0, &state,
0, sizeof(state));
if (err)
return err;
if (state.count > HPWMI_MAX_RFKILL2_DEVICES) {
pr_warn("unable to parse 0x1b query output\n");
return -EINVAL;
}
for (i = 0; i < state.count; i++) {
struct rfkill *rfkill;
enum rfkill_type type;
char *name;
switch (state.device[i].radio_type) {
case HPWMI_WIFI:
type = RFKILL_TYPE_WLAN;
name = "hp-wifi";
break;
case HPWMI_BLUETOOTH:
type = RFKILL_TYPE_BLUETOOTH;
name = "hp-bluetooth";
break;
case HPWMI_WWAN:
type = RFKILL_TYPE_WWAN;
name = "hp-wwan";
break;
default:
pr_warn("unknown device type 0x%x\n",
state.device[i].radio_type);
continue;
}
if (!state.device[i].vendor_id) {
pr_warn("zero device %d while %d reported\n",
i, state.count);
continue;
}
rfkill = rfkill_alloc(name, &device->dev, type,
&hp_wmi_rfkill2_ops, (void *)(long)i);
if (!rfkill) {
err = -ENOMEM;
goto fail;
}
rfkill2[rfkill2_count].id = state.device[i].rfkill_id;
rfkill2[rfkill2_count].num = i;
rfkill2[rfkill2_count].rfkill = rfkill;
rfkill_init_sw_state(rfkill,
IS_SWBLOCKED(state.device[i].power));
rfkill_set_hw_state(rfkill,
IS_HWBLOCKED(state.device[i].power));
if (!(state.device[i].power & HPWMI_POWER_BIOS))
pr_info("device %s blocked by BIOS\n", name);
err = rfkill_register(rfkill);
if (err) {
rfkill_destroy(rfkill);
goto fail;
}
rfkill2_count++;
}
return 0;
fail:
for (; rfkill2_count > 0; rfkill2_count--) {
rfkill_unregister(rfkill2[rfkill2_count - 1].rfkill);
rfkill_destroy(rfkill2[rfkill2_count - 1].rfkill);
}
return err;
}
static int __devinit hp_wmi_bios_setup(struct platform_device *device)
{
int err;
/* clear detected rfkill devices */
wifi_rfkill = NULL;
bluetooth_rfkill = NULL;
wwan_rfkill = NULL;
rfkill2_count = 0;
if (hp_wmi_rfkill_setup(device))
hp_wmi_rfkill2_setup(device);
err = device_create_file(&device->dev, &dev_attr_display);
if (err)
goto add_sysfs_error;
err = device_create_file(&device->dev, &dev_attr_hddtemp);
if (err)
goto add_sysfs_error;
err = device_create_file(&device->dev, &dev_attr_als);
if (err)
goto add_sysfs_error;
err = device_create_file(&device->dev, &dev_attr_dock);
if (err)
goto add_sysfs_error;
err = device_create_file(&device->dev, &dev_attr_tablet);
if (err)
goto add_sysfs_error;
return 0;
add_sysfs_error:
cleanup_sysfs(device);
return err;
}
static int __exit hp_wmi_bios_remove(struct platform_device *device)
{
int i;
cleanup_sysfs(device);
for (i = 0; i < rfkill2_count; i++) {
rfkill_unregister(rfkill2[i].rfkill);
rfkill_destroy(rfkill2[i].rfkill);
}
if (wifi_rfkill) {
rfkill_unregister(wifi_rfkill);
rfkill_destroy(wifi_rfkill);
}
if (bluetooth_rfkill) {
rfkill_unregister(bluetooth_rfkill);
rfkill_destroy(bluetooth_rfkill);
}
if (wwan_rfkill) {
rfkill_unregister(wwan_rfkill);
rfkill_destroy(wwan_rfkill);
}
return 0;
}
static int hp_wmi_resume_handler(struct device *device)
{
/*
* Hardware state may have changed while suspended, so trigger
* input events for the current state. As this is a switch,
* the input layer will only actually pass it on if the state
* changed.
*/
if (hp_wmi_input_dev) {
input_report_switch(hp_wmi_input_dev, SW_DOCK,
hp_wmi_dock_state());
input_report_switch(hp_wmi_input_dev, SW_TABLET_MODE,
hp_wmi_tablet_state());
input_sync(hp_wmi_input_dev);
}
if (rfkill2_count)
hp_wmi_rfkill2_refresh();
if (wifi_rfkill)
rfkill_set_states(wifi_rfkill,
hp_wmi_get_sw_state(HPWMI_WIFI),
hp_wmi_get_hw_state(HPWMI_WIFI));
if (bluetooth_rfkill)
rfkill_set_states(bluetooth_rfkill,
hp_wmi_get_sw_state(HPWMI_BLUETOOTH),
hp_wmi_get_hw_state(HPWMI_BLUETOOTH));
if (wwan_rfkill)
rfkill_set_states(wwan_rfkill,
hp_wmi_get_sw_state(HPWMI_WWAN),
hp_wmi_get_hw_state(HPWMI_WWAN));
return 0;
}
static int __init hp_wmi_init(void)
{
int err;
int event_capable = wmi_has_guid(HPWMI_EVENT_GUID);
int bios_capable = wmi_has_guid(HPWMI_BIOS_GUID);
if (event_capable) {
err = hp_wmi_input_setup();
if (err)
return err;
}
if (bios_capable) {
err = platform_driver_register(&hp_wmi_driver);
if (err)
goto err_driver_reg;
hp_wmi_platform_dev = platform_device_alloc("hp-wmi", -1);
if (!hp_wmi_platform_dev) {
err = -ENOMEM;
goto err_device_alloc;
}
err = platform_device_add(hp_wmi_platform_dev);
if (err)
goto err_device_add;
}
if (!bios_capable && !event_capable)
return -ENODEV;
return 0;
err_device_add:
platform_device_put(hp_wmi_platform_dev);
err_device_alloc:
platform_driver_unregister(&hp_wmi_driver);
err_driver_reg:
if (event_capable)
hp_wmi_input_destroy();
return err;
}
static void __exit hp_wmi_exit(void)
{
if (wmi_has_guid(HPWMI_EVENT_GUID))
hp_wmi_input_destroy();
if (hp_wmi_platform_dev) {
platform_device_unregister(hp_wmi_platform_dev);
platform_driver_unregister(&hp_wmi_driver);
}
}
module_init(hp_wmi_init);
module_exit(hp_wmi_exit);
| gpl-2.0 |
neobuddy89/android_kernel_cyanogen_msm8916 | drivers/char/hw_random/msm_rng.c | 689 | 15189 | /*
* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/hw_random.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/types.h>
#include <soc/qcom/socinfo.h>
#include <linux/msm-bus.h>
#include <linux/qrng.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/delay.h>
#include <linux/platform_data/qcom_crypto_device.h>
#include "msm_rng.h"
#include "ctr_drbg.h"
#include "fips_drbg.h"
#include "msm_fips_selftest.h"
#define DRIVER_NAME "msm_rng"
/* Device specific register offsets */
#define PRNG_DATA_OUT_OFFSET 0x0000
#define PRNG_STATUS_OFFSET 0x0004
#define PRNG_LFSR_CFG_OFFSET 0x0100
#define PRNG_CONFIG_OFFSET 0x0104
/* Device specific register masks and config values */
#define PRNG_LFSR_CFG_MASK 0xFFFF0000
#define PRNG_LFSR_CFG_CLOCKS 0x0000DDDD
#define PRNG_CONFIG_MASK 0xFFFFFFFD
#define PRNG_HW_ENABLE 0x00000002
#define MAX_HW_FIFO_DEPTH 16 /* FIFO is 16 words deep */
#define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4) /* FIFO is 32 bits wide */
/* Global FIPS status */
#ifdef CONFIG_FIPS_ENABLE
enum fips_status g_fips140_status = FIPS140_STATUS_FAIL;
EXPORT_SYMBOL(g_fips140_status);
#else
enum fips_status g_fips140_status = FIPS140_STATUS_NA;
EXPORT_SYMBOL(g_fips140_status);
#endif
/*FIPS140-2 call back for DRBG self test */
void *drbg_call_back;
EXPORT_SYMBOL(drbg_call_back);
enum {
FIPS_NOT_STARTED = 0,
DRBG_FIPS_STARTED
};
struct msm_rng_device msm_rng_device_info;
#ifdef CONFIG_FIPS_ENABLE
static int fips_mode_enabled = FIPS_NOT_STARTED;
#endif
static long msm_rng_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg)
{
long ret = 0;
pr_debug("ioctl: cmd = %d\n", cmd);
switch (cmd) {
case QRNG_IOCTL_RESET_BUS_BANDWIDTH:
pr_info("calling msm_rng_bus_scale(LOW)\n");
ret = msm_bus_scale_client_update_request(
msm_rng_device_info.qrng_perf_client, 0);
if (ret)
pr_err("failed qrng_reset_bus_bw, ret = %ld\n", ret);
break;
default:
pr_err("Unsupported IOCTL call");
break;
}
return ret;
}
/*
*
* This function calls hardware random bit generator directory and retuns it
* back to caller
*
*/
int msm_rng_direct_read(struct msm_rng_device *msm_rng_dev, void *data)
{
struct platform_device *pdev;
void __iomem *base;
size_t currsize = 0;
u32 val;
u32 *retdata = data;
int ret;
int failed = 0;
pdev = msm_rng_dev->pdev;
base = msm_rng_dev->base;
mutex_lock(&msm_rng_dev->rng_lock);
if (msm_rng_dev->qrng_perf_client) {
ret = msm_bus_scale_client_update_request(
msm_rng_dev->qrng_perf_client, 1);
if (ret)
pr_err("bus_scale_client_update_req failed!\n");
}
/* enable PRNG clock */
ret = clk_prepare_enable(msm_rng_dev->prng_clk);
if (ret) {
dev_err(&pdev->dev, "failed to enable clock in callback\n");
goto err;
}
/* read random data from h/w */
do {
/* check status bit if data is available */
while (!(readl_relaxed(base + PRNG_STATUS_OFFSET)
& 0x00000001)) {
if (failed == 10) {
pr_err("Data not available after retry\n");
break;
}
pr_err("msm_rng:Data not available!\n");
msleep_interruptible(10);
failed++;
}
/* read FIFO */
val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET);
if (!val)
break; /* no data to read so just bail */
/* write data back to callers pointer */
*(retdata++) = val;
currsize += 4;
} while (currsize < Q_HW_DRBG_BLOCK_BYTES);
/* vote to turn off clock */
clk_disable_unprepare(msm_rng_dev->prng_clk);
err:
if (msm_rng_dev->qrng_perf_client) {
ret = msm_bus_scale_client_update_request(
msm_rng_dev->qrng_perf_client, 0);
if (ret)
pr_err("bus_scale_client_update_req failed!\n");
}
mutex_unlock(&msm_rng_dev->rng_lock);
val = 0L;
return currsize;
}
static int msm_rng_drbg_read(struct hwrng *rng,
void *data, size_t max, bool wait)
{
struct msm_rng_device *msm_rng_dev;
struct platform_device *pdev;
void __iomem *base;
size_t currsize = 0;
u32 val;
u32 *retdata = data;
int ret, ret1;
int failed = 0;
msm_rng_dev = (struct msm_rng_device *)rng->priv;
pdev = msm_rng_dev->pdev;
base = msm_rng_dev->base;
/* no room for word data */
if (max < 4)
return 0;
mutex_lock(&msm_rng_dev->rng_lock);
/* read random data from CTR-AES based DRBG */
if (FIPS140_DRBG_ENABLED == msm_rng_dev->fips140_drbg_enabled) {
ret1 = fips_drbg_gen(msm_rng_dev->drbg_ctx, data, max);
if (FIPS140_PRNG_ERR == ret1)
panic("random number generator generator error.\n");
} else
ret1 = 1;
if (msm_rng_dev->qrng_perf_client) {
ret = msm_bus_scale_client_update_request(
msm_rng_dev->qrng_perf_client, 1);
if (ret)
pr_err("bus_scale_client_update_req failed!\n");
}
/* read random data from h/w */
/* enable PRNG clock */
ret = clk_prepare_enable(msm_rng_dev->prng_clk);
if (ret) {
dev_err(&pdev->dev, "failed to enable clock in callback\n");
goto err;
}
/* read random data from h/w */
do {
/* check status bit if data is available */
while (!(readl_relaxed(base + PRNG_STATUS_OFFSET)
& 0x00000001)) {
if (failed == 10) {
pr_err("Data not available after retry\n");
break;
}
pr_err("msm_rng:Data not available!\n");
msleep_interruptible(10);
failed++;
}
/* read FIFO */
val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET);
if (!val)
break; /* no data to read so just bail */
/* write data back to callers pointer */
if (0 != ret1)
*(retdata++) = val;
currsize += 4;
/* make sure we stay on 32bit boundary */
if ((max - currsize) < 4)
break;
} while (currsize < max);
/* vote to turn off clock */
clk_disable_unprepare(msm_rng_dev->prng_clk);
err:
if (msm_rng_dev->qrng_perf_client) {
ret = msm_bus_scale_client_update_request(
msm_rng_dev->qrng_perf_client, 0);
if (ret)
pr_err("bus_scale_client_update_req failed!\n");
}
mutex_unlock(&msm_rng_dev->rng_lock);
return currsize;
}
#ifdef CONFIG_FIPS_ENABLE
static void _fips_drbg_init_error(struct msm_rng_device *msm_rng_dev)
{
unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
clk_put(msm_rng_dev->prng_clk);
iounmap(msm_rng_dev->base);
kzfree(msm_rng_dev->drbg_ctx);
kzfree(msm_rng_dev);
panic("software random number generator initialization error.\n");
}
#else
static inline void _fips_drbg_init_error(struct msm_rng_device *msm_rng_dev)
{
return;
}
#endif
#ifdef CONFIG_FIPS_ENABLE
int _do_msm_fips_drbg_init(void *rng_dev)
{
struct msm_rng_device *msm_rng_dev = (struct msm_rng_device *) rng_dev;
int ret;
if (NULL == msm_rng_dev)
return 1;
ret = fips_drbg_init(msm_rng_dev);
if (0 == ret) {
pr_debug("start fips self test\n");
ret = fips_self_test();
if (ret) {
msm_rng_dev->fips140_drbg_enabled =
FIPS140_DRBG_DISABLED;
_fips_drbg_init_error(msm_rng_dev);
} else {
msm_rng_dev->fips140_drbg_enabled =
FIPS140_DRBG_ENABLED;
}
} else {
msm_rng_dev->fips140_drbg_enabled = FIPS140_DRBG_DISABLED;
_fips_drbg_init_error(msm_rng_dev);
}
return ret;
}
#else
int _do_msm_fips_drbg_init(void *rng_dev)
{
return 0;
}
#endif
#ifdef CONFIG_FIPS_ENABLE
static int msm_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
{
struct msm_rng_device *msm_rng_dev = (struct msm_rng_device *)rng->priv;
unsigned char a[Q_HW_DRBG_BLOCK_BYTES];
int read_size;
unsigned char *p = data;
switch (fips_mode_enabled) {
case DRBG_FIPS_STARTED:
return msm_rng_drbg_read(rng, data, max, wait);
break;
case FIPS_NOT_STARTED:
if (g_fips140_status != FIPS140_STATUS_PASS) {
do {
read_size = msm_rng_direct_read(msm_rng_dev, a);
if (read_size <= 0)
break;
if ((max - read_size > 0)) {
memcpy(p, a, read_size);
p += read_size;
max -= read_size;
} else {
memcpy(p, a, max);
break;
}
} while (1);
return p - (unsigned char *)data;
} else {
fips_mode_enabled = DRBG_FIPS_STARTED;
return msm_rng_drbg_read(rng, data, max, wait);
}
break;
default:
return 0;
break;
}
return 0;
}
#else
static int msm_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
{
return msm_rng_drbg_read(rng, data, max, wait);
}
#endif
static struct hwrng msm_rng = {
.name = DRIVER_NAME,
.read = msm_rng_read,
};
static int msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev)
{
unsigned long val = 0;
unsigned long reg_val = 0;
int ret = 0;
if (msm_rng_dev->qrng_perf_client) {
ret = msm_bus_scale_client_update_request(
msm_rng_dev->qrng_perf_client, 1);
if (ret)
pr_err("bus_scale_client_update_req failed!\n");
}
/* Enable the PRNG CLK */
ret = clk_prepare_enable(msm_rng_dev->prng_clk);
if (ret) {
dev_err(&(msm_rng_dev->pdev)->dev,
"failed to enable clock in probe\n");
return -EPERM;
}
/* Enable PRNG h/w only if it is NOT ON */
val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
PRNG_HW_ENABLE;
/* PRNG H/W is not ON */
if (val != PRNG_HW_ENABLE) {
val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
val &= PRNG_LFSR_CFG_MASK;
val |= PRNG_LFSR_CFG_CLOCKS;
writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
/* The PRNG CONFIG register should be first written */
mb();
reg_val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET)
& PRNG_CONFIG_MASK;
reg_val |= PRNG_HW_ENABLE;
writel_relaxed(reg_val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
/* The PRNG clk should be disabled only after we enable the
* PRNG h/w by writing to the PRNG CONFIG register.
*/
mb();
}
clk_disable_unprepare(msm_rng_dev->prng_clk);
if (msm_rng_dev->qrng_perf_client) {
ret = msm_bus_scale_client_update_request(
msm_rng_dev->qrng_perf_client, 0);
if (ret)
pr_err("bus_scale_client_update_req failed!\n");
}
return 0;
}
static const struct file_operations msm_rng_fops = {
.unlocked_ioctl = msm_rng_ioctl,
};
static struct class *msm_rng_class;
static struct cdev msm_rng_cdev;
#ifdef CONFIG_FIPS_ENABLE
static void _first_msm_drbg_init(struct msm_rng_device *msm_rng_dev)
{
fips_reg_drbg_callback((void *)msm_rng_dev);
return;
}
#else
static void _first_msm_drbg_init(struct msm_rng_device *msm_rng_dev)
{
_do_msm_fips_drbg_init(msm_rng_dev);
}
#endif
static int msm_rng_probe(struct platform_device *pdev)
{
struct resource *res;
struct msm_rng_device *msm_rng_dev = NULL;
void __iomem *base = NULL;
int error = 0;
int ret = 0;
struct device *dev;
struct msm_bus_scale_pdata *qrng_platform_support = NULL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "invalid address\n");
error = -EFAULT;
goto err_exit;
}
msm_rng_dev = kzalloc(sizeof(struct msm_rng_device), GFP_KERNEL);
if (!msm_rng_dev) {
dev_err(&pdev->dev, "cannot allocate memory\n");
error = -ENOMEM;
goto err_exit;
}
base = ioremap(res->start, resource_size(res));
if (!base) {
dev_err(&pdev->dev, "ioremap failed\n");
error = -ENOMEM;
goto err_iomap;
}
msm_rng_dev->base = base;
msm_rng_dev->drbg_ctx = kzalloc(sizeof(struct fips_drbg_ctx_s),
GFP_KERNEL);
if (!msm_rng_dev->drbg_ctx) {
dev_err(&pdev->dev, "cannot allocate memory\n");
error = -ENOMEM;
goto err_clk_get;
}
/* create a handle for clock control */
if ((pdev->dev.of_node) && (of_property_read_bool(pdev->dev.of_node,
"qcom,msm-rng-iface-clk")))
msm_rng_dev->prng_clk = clk_get(&pdev->dev,
"iface_clk");
else
msm_rng_dev->prng_clk = clk_get(&pdev->dev, "core_clk");
if (IS_ERR(msm_rng_dev->prng_clk)) {
dev_err(&pdev->dev, "failed to register clock source\n");
error = -EPERM;
goto err_clk_get;
}
/* save away pdev and register driver data */
msm_rng_dev->pdev = pdev;
platform_set_drvdata(pdev, msm_rng_dev);
if (pdev->dev.of_node) {
/* Register bus client */
qrng_platform_support = msm_bus_cl_get_pdata(pdev);
msm_rng_dev->qrng_perf_client = msm_bus_scale_register_client(
qrng_platform_support);
msm_rng_device_info.qrng_perf_client =
msm_rng_dev->qrng_perf_client;
if (!msm_rng_dev->qrng_perf_client)
pr_err("Unable to register bus client\n");
}
/* Enable rng h/w */
error = msm_rng_enable_hw(msm_rng_dev);
if (error)
goto rollback_clk;
mutex_init(&msm_rng_dev->rng_lock);
/* register with hwrng framework */
msm_rng.priv = (unsigned long) msm_rng_dev;
error = hwrng_register(&msm_rng);
if (error) {
dev_err(&pdev->dev, "failed to register hwrng\n");
error = -EPERM;
goto rollback_clk;
}
ret = register_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME, &msm_rng_fops);
msm_rng_class = class_create(THIS_MODULE, "msm-rng");
if (IS_ERR(msm_rng_class)) {
pr_err("class_create failed\n");
return PTR_ERR(msm_rng_class);
}
dev = device_create(msm_rng_class, NULL, MKDEV(QRNG_IOC_MAGIC, 0),
NULL, "msm-rng");
if (IS_ERR(dev)) {
pr_err("Device create failed\n");
error = PTR_ERR(dev);
goto unregister_chrdev;
}
cdev_init(&msm_rng_cdev, &msm_rng_fops);
_first_msm_drbg_init(msm_rng_dev);
return error;
unregister_chrdev:
unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
rollback_clk:
clk_put(msm_rng_dev->prng_clk);
err_clk_get:
iounmap(msm_rng_dev->base);
err_iomap:
kzfree(msm_rng_dev->drbg_ctx);
kzfree(msm_rng_dev);
err_exit:
return error;
}
static int msm_rng_remove(struct platform_device *pdev)
{
struct msm_rng_device *msm_rng_dev = platform_get_drvdata(pdev);
unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
hwrng_unregister(&msm_rng);
clk_put(msm_rng_dev->prng_clk);
iounmap(msm_rng_dev->base);
platform_set_drvdata(pdev, NULL);
if (msm_rng_dev->qrng_perf_client)
msm_bus_scale_unregister_client(msm_rng_dev->qrng_perf_client);
if (msm_rng_dev->drbg_ctx) {
fips_drbg_final(msm_rng_dev->drbg_ctx);
kzfree(msm_rng_dev->drbg_ctx);
msm_rng_dev->drbg_ctx = NULL;
}
kzfree(msm_rng_dev);
return 0;
}
static struct of_device_id qrng_match[] = {
{ .compatible = "qcom,msm-rng",
},
{}
};
static struct platform_driver rng_driver = {
.probe = msm_rng_probe,
.remove = msm_rng_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = qrng_match,
}
};
static int __init msm_rng_init(void)
{
return platform_driver_register(&rng_driver);
}
module_init(msm_rng_init);
static void __exit msm_rng_exit(void)
{
platform_driver_unregister(&rng_driver);
}
module_exit(msm_rng_exit);
#ifdef CONFIG_FIPS_ENABLE
EXPORT_SYMBOL(fips_ctraes128_df_known_answer_test);
#endif
EXPORT_SYMBOL(_do_msm_fips_drbg_init);
MODULE_AUTHOR("The Linux Foundation");
MODULE_DESCRIPTION("Qualcomm MSM Random Number Driver");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
yuzaipiaofei/android_kernel_cyanogen_msm8916 | drivers/staging/prima/CORE/WDA/src/wlan_nv.c | 945 | 588547 | /*
* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/** ------------------------------------------------------------------------- *
------------------------------------------------------------------------- *
\file wlan_nv.c
\brief Contains collection of table default values to use in
case a table is not found in NV
$Id$
========================================================================== */
#ifndef WLAN_NV_C
#define WLAN_NV_C
#include "wlan_nv2.h"
#include "wlan_hal_msg.h"
const sHalNv nvDefaults =
{
{
0, // tANI_U16 productId;
1, // tANI_U8 productBands;
2, // tANI_U8 wlanNvRevId; //0: WCN1312, 1: WCN1314, 2: WCN3660
1, // tANI_U8 numOfTxChains;
1, // tANI_U8 numOfRxChains;
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ "\0" },
0, // tANI_U8 couplerType;
WLAN_NV_VERSION, // tANI_U8 nvVersion;
}, //fields
{
// NV_TABLE_RATE_POWER_SETTINGS
{
// typedef tANI_S16 tPowerdBm;
//typedef tPowerdBm tRateGroupPwr[NUM_HAL_PHY_RATES];
//tRateGroupPwr pwrOptimum[NUM_RF_SUBBANDS];
//2.4G
{
//802.11b Rates
{1900}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{1900}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{1900}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{1900}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{1900}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{1900}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{1900}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
//11A 20MHz Rates
{1700}, // HAL_PHY_RATE_11A_6_MBPS,
{1700}, // HAL_PHY_RATE_11A_9_MBPS,
{1700}, // HAL_PHY_RATE_11A_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_18_MBPS,
{1600}, // HAL_PHY_RATE_11A_24_MBPS,
{1550}, // HAL_PHY_RATE_11A_36_MBPS,
{1550}, // HAL_PHY_RATE_11A_48_MBPS,
{1550}, // HAL_PHY_RATE_11A_54_MBPS,
//DUP 11A 40MHz Rates
{1700}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
//MCS Index #0-7(20/40MHz)
{1700}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
//MCS Index #8-15(20/40MHz)
{1700}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATURE_11AC
//11AC rates
//11A duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
//11ac 20MHZ NG, SG
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
//11ac 80MHZ NG, SG
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_2_4_GHZ
// 5G Low
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DUP 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_11AC
///11AC rates
///11A duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11ac 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
//11ac 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_5_LOW_GHZ
// 5G Mid
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DU P 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCSS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCSS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_111AC
///11CAC rates
///11Ad duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11a c 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
///11a c 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // // RF_SUBBAND_5_MID_GHZ
// 5G High
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DU P 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCSS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCSS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_11AC
///11CAC rates
///11Ad duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11a c 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
///11a c 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_5_HIGH_GHZ,
// 4.9G
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DU P 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCSS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCSS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_11AC
///11CAC rates
///11Ad duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11a c 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
///11a c 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_4_9_GHZ
},
// NV_TABLE_REGULATORY_DOMAINS
{
// typedef struct
// {
// tANI_BOOLEAN enabled;
// tPowerdBm pwrLimit;
// }sRegulatoryChannel;
// typedef struct
// {
// sRegulatoryChannel channels[NUM_RF_CHANNELS];
// uAbsPwrPrecision antennaGain[NUM_RF_SUBBANDS];
// uAbsPwrPrecision bRatePowerOffset[NUM_2_4GHZ_CHANNELS];
// }sRegulatoryDomains;
//sRegulatoryDomains regDomains[NUM_REG_DOMAINS];
{ // REG_DOMAIN_FCC start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_11,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_12,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_52,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_56,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_60,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DFS, 22}, //RF_CHAN_100,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_104,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_108,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_112,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_132,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_136,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{0}, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_FCC end
{ // REG_DOMAIN_ETSI start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 19}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 19}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_149,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_153,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_157,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_161,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_ETSI end
{ // REG_DOMAIN_JAPAN start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_13,
{NV_CHANNEL_ENABLE, 18}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_52,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_56,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_60,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DFS, 22}, //RF_CHAN_100,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_104,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_108,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_112,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_116,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_120,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_124,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_128,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_132,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_136,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_JAPAN end
{ // REG_DOMAIN_WORLD start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_52,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_56,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_60,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DFS, 22}, //RF_CHAN_100,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_104,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_108,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_112,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_116,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_120,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_124,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_128,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_132,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_136,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{0}, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_WORLD end
{ // REG_DOMAIN_N_AMER_EXC_FCC start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_11,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_12,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_N_AMER_EXC_FCC end
{ // REG_DOMAIN_APAC start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{0}, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_APAC end
{ // REG_DOMAIN_KOREA start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{0}, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_KOREA end
{ // REG_DOMAIN_HI_5GHZ start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{0}, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_HI_5GHZ end
{ // REG_DOMAIN_NO_5GHZ start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
}, //sRegulatoryChannel end
{
{0}, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
} // REG_DOMAIN_NO_5GHZ end
},
// NV_TABLE_DEFAULT_COUNTRY
{
// typedef struct
// {
// tANI_U8 regDomain; //from eRegDomainId
// tANI_U8 countryCode[NV_FIELD_COUNTRY_CODE_SIZE]; // string identifier
// }sDefaultCountry;
0, // regDomain
{ 'U', 'S', 'I' } // countryCode
},
//NV_TABLE_TPC_POWER_TABLE
{
//ch 1
{
{
0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 2 , 2 , 3 , 3 , 4 , 5 , 5 , 6 , 7 , 8 , 8 , 9 , 10 , 10 , 11 , 13 , 14 , 15 , 17 ,
19 , 20 , 21 , 22 , 23 , 25 , 26 , 27 , 28 , 29 , 30 , 30 , 31 , 32 , 33 , 34 , 35 , 35 , 36 , 37 , 38 , 39 , 40 ,
40 , 41 , 42 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 48 , 48 , 49 , 49 , 50 , 50 , 51 , 51 , 52 , 52 , 53 , 53 ,
54 , 54 , 55 , 55 , 56 , 56 , 57 , 57 , 58 , 58 , 58 , 59 , 59 , 59 , 60 , 60 , 60 , 61 , 61 , 61 , 62 , 62 , 62 ,
63 , 63 , 63 , 64 , 64 , 65 , 65 , 65 , 66 , 66 , 66 , 67 , 67 , 67 , 68 , 68 , 68 , 69 , 69 , 69 , 69 , 70 , 70 ,
70 , 70 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 76 ,
76 , 76 , 76 , 76 , 77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 81 ,
81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 83 , 84 , 84 , 84 , 84 , 84 , 84 , 85 , 85 , 85 ,
85 , 85 , 85 , 86 , 86 , 86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 88 , 88 , 89 ,
89 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 90 , 90 , 90 , 91 , 91 , 91 , 91 , 91 , 91 , 92 , 92 , 92 , 92 , 92 ,
92 , 92 , 93 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 95 , 95 , 96 , 96
}
}, //RF_CHAN_1
//ch 2
{
{
0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 2 , 2 , 3 , 3 , 4 , 5 , 5 , 6 , 7 , 8 , 8 , 9 , 10 , 10 , 11 , 13 , 14 , 15 , 17 ,
19 , 20 , 21 , 22 , 23 , 25 , 26 , 27 , 28 , 29 , 30 , 30 , 31 , 32 , 33 , 34 , 35 , 35 , 36 , 37 , 38 , 39 , 40 ,
40 , 41 , 42 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 48 , 48 , 49 , 49 , 50 , 50 , 51 , 51 , 52 , 52 , 53 , 53 ,
54 , 54 , 55 , 55 , 56 , 56 , 57 , 57 , 58 , 58 , 58 , 59 , 59 , 59 , 60 , 60 , 60 , 61 , 61 , 61 , 62 , 62 , 62 ,
63 , 63 , 63 , 64 , 64 , 65 , 65 , 65 , 66 , 66 , 66 , 67 , 67 , 67 , 68 , 68 , 68 , 69 , 69 , 69 , 69 , 70 , 70 ,
70 , 70 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 76 ,
76 , 76 , 76 , 76 , 77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 81 ,
81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 83 , 84 , 84 , 84 , 84 , 84 , 84 , 85 , 85 , 85 ,
85 , 85 , 85 , 86 , 86 , 86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 88 , 88 , 89 ,
89 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 90 , 90 , 90 , 91 , 91 , 91 , 91 , 91 , 91 , 92 , 92 , 92 , 92 , 92 ,
92 , 92 , 93 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 95 , 95 , 96 , 96
}
}, //RF_CHAN_2
//ch 3
{
{
0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 2 , 2 , 3 , 3 , 4 , 5 , 5 , 6 , 7 , 8 , 8 , 9 , 10 , 10 , 11 , 13 , 14 , 15 , 17 ,
19 , 20 , 21 , 22 , 23 , 25 , 26 , 27 , 28 , 29 , 30 , 30 , 31 , 32 , 33 , 34 , 35 , 35 , 36 , 37 , 38 , 39 , 40 ,
40 , 41 , 42 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 48 , 48 , 49 , 49 , 50 , 50 , 51 , 51 , 52 , 52 , 53 , 53 ,
54 , 54 , 55 , 55 , 56 , 56 , 57 , 57 , 58 , 58 , 58 , 59 , 59 , 59 , 60 , 60 , 60 , 61 , 61 , 61 , 62 , 62 , 62 ,
63 , 63 , 63 , 64 , 64 , 65 , 65 , 65 , 66 , 66 , 66 , 67 , 67 , 67 , 68 , 68 , 68 , 69 , 69 , 69 , 69 , 70 , 70 ,
70 , 70 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 76 ,
76 , 76 , 76 , 76 , 77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 81 ,
81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 83 , 84 , 84 , 84 , 84 , 84 , 84 , 85 , 85 , 85 ,
85 , 85 , 85 , 86 , 86 , 86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 88 , 88 , 89 ,
89 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 90 , 90 , 90 , 91 , 91 , 91 , 91 , 91 , 91 , 92 , 92 , 92 , 92 , 92 ,
92 , 92 , 93 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 95 , 95 , 96 , 96
}
}, //RF_CHAN_3
//ch 4
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_4
//ch 5
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_5
//ch 6
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_6
//ch 7
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_7
//ch 8
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_8
//ch 9
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_9
//ch 10
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_10
//ch 11
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_11
//ch 12
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_12
//ch 13
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_13
//ch 14
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_14
//5200 base: ch240
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_240
//5200 base: ch244
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_244
//5200 base: ch248
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_248
//5200 base: ch252
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
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//5500: ch 64
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//5500: ch 100
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//5500: ch 104
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//5500: ch 108
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31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_108
//5500: ch 112
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_112
//5500: ch 116
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_116
//5500: ch 120
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_120
//5500: ch 124
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_124
//5500: ch 128
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_128
//5500: ch 132
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_132
//5500: ch 136
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_136
//5500: ch 140
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_140
#ifdef FEATURE_WLAN_CH144
//5500: ch 144
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_144
#endif /* FEATURE_WLAN_CH144 */
//5500: ch 149
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_149
//5500: ch 153
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_153
//5500: ch 157
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_157
//5500: ch 161
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_161
//5500: ch 165
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_165
// CB starts
//ch 3
{
{
0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 2 , 2 , 3 , 3 , 4 , 5 , 5 , 6 , 7 , 8 , 8 , 9 , 10 , 10 , 11 , 13 , 14 , 15 , 17 ,
19 , 20 , 21 , 22 , 23 , 25 , 26 , 27 , 28 , 29 , 30 , 30 , 31 , 32 , 33 , 34 , 35 , 35 , 36 , 37 , 38 , 39 , 40 ,
40 , 41 , 42 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 48 , 48 , 49 , 49 , 50 , 50 , 51 , 51 , 52 , 52 , 53 , 53 ,
54 , 54 , 55 , 55 , 56 , 56 , 57 , 57 , 58 , 58 , 58 , 59 , 59 , 59 , 60 , 60 , 60 , 61 , 61 , 61 , 62 , 62 , 62 ,
63 , 63 , 63 , 64 , 64 , 65 , 65 , 65 , 66 , 66 , 66 , 67 , 67 , 67 , 68 , 68 , 68 , 69 , 69 , 69 , 69 , 70 , 70 ,
70 , 70 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 76 ,
76 , 76 , 76 , 76 , 77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 81 ,
81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 83 , 84 , 84 , 84 , 84 , 84 , 84 , 85 , 85 , 85 ,
85 , 85 , 85 , 86 , 86 , 86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 88 , 88 , 89 ,
89 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 90 , 90 , 90 , 91 , 91 , 91 , 91 , 91 , 91 , 92 , 92 , 92 , 92 , 92 ,
92 , 92 , 93 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 95 , 95 , 96 , 96
}
}, //RF_CHAN_BOND_3
//ch 4
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_BOND_4
//ch 5
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_BOND_5
//ch 6
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_BOND_6
//ch 7
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_BOND_7
//ch 8
{
{
10 , 10 , 11 , 12 , 12 , 13 , 14 , 15 , 15 , 16 , 17 , 17 , 18 , 19 , 20 , 20 , 22 , 23 , 25 , 26 , 28 , 29 , 31 ,
33 , 34 , 36 , 37 , 38 , 40 , 41 , 42 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 52 , 53 , 54 , 55 , 55 , 56 ,
57 , 57 , 58 , 59 , 59 , 60 , 61 , 61 , 62 , 62 , 63 , 64 , 64 , 65 , 66 , 66 , 67 , 67 , 68 , 68 , 69 , 69 , 70 ,
70 , 71 , 71 , 71 , 72 , 72 , 72 , 73 , 73 , 73 , 73 , 74 , 74 , 74 , 75 , 75 , 76 , 76 , 76 , 77 , 77 , 77 , 78 ,
78 , 78 , 79 , 79 , 79 , 80 , 80 , 80 , 81 , 81 , 81 , 82 , 82 , 82 , 83 , 83 , 83 , 84 , 84 , 84 , 85 , 85 , 85 ,
86 , 86 , 86 , 86 , 87 , 87 , 87 , 87 , 88 , 88 , 88 , 88 , 88 , 89 , 89 , 89 , 89 , 90 , 90 , 90 , 90 , 91 , 91 ,
91 , 91 , 91 , 92 , 92 , 92 , 92 , 93 , 93 , 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 , 95 , 95 , 96 , 96 , 96 ,
96 , 97 , 97 , 97 , 97 , 97 , 98 , 98 , 98 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99 , 99 , 100 , 100 , 100 ,
100 , 101 , 101 , 101 , 101 , 101 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 102 , 103 , 103 , 103 , 103 ,
103 , 103 , 104 , 104 , 104 , 104 , 104 , 105 , 105 , 105 , 105 , 105 , 106 , 106 , 106 , 106 , 106 , 106 , 107 ,
107 , 107 , 107 , 107 , 107 , 107 , 108 , 108 , 108 , 108 , 108 , 108 , 109 , 109 , 109 , 109 , 109 , 109 , 109 ,
110 , 110 , 110 , 110 , 110 , 110 , 110 , 110 , 111 , 111 , 111 , 111 , 111 , 112 , 112 , 112
}
}, //RF_CHAN_BOND_8
//ch 9
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_BOND_9
//ch 10
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_BOND_10
//ch 11
{
{
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 2 , 2 , 3 , 5 , 6 , 7 , 9 , 10 , 11 , 13 ,
14 , 15 , 16 , 17 , 18 , 20 , 21 , 22 , 22 , 23 , 23 , 24 , 24 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 28 , 29 , 29 ,
30 , 30 , 31 , 31 , 32 , 32 , 33 , 33 , 34 , 34 , 35 , 36 , 36 , 37 , 37 , 38 , 38 , 39 , 39 , 40 , 40 , 41 , 41 ,
42 , 42 , 43 , 43 , 44 , 44 , 45 , 45 , 46 , 46 , 47 , 47 , 47 , 48 , 48 , 49 , 49 , 49 , 50 , 50 , 50 , 51 , 51 ,
51 , 51 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 56 , 56 , 56 , 57 , 57 , 57 , 57 , 58 ,
58 , 58 , 59 , 59 , 59 , 59 , 60 , 60 , 60 , 60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 ,
64 , 64 , 64 , 64 , 65 , 65 , 65 , 65 , 65 , 66 , 66 , 66 , 66 , 67 , 67 , 67 , 67 , 67 , 68 , 68 , 68 , 68 , 69 ,
69 , 69 , 69 , 70 , 70 , 70 , 70 , 70 , 71 , 71 , 71 , 71 , 71 , 72 , 72 , 72 , 72 , 72 , 72 , 73 , 73 , 73 , 73 ,
73 , 73 , 74 , 74 , 74 , 74 , 74 , 74 , 75 , 75 , 75 , 75 , 75 , 75 , 76 , 76 , 76 , 76 , 76 , 76 , 76 , 77 , 77 ,
77 , 77 , 77 , 77 , 78 , 78 , 78 , 78 , 78 , 78 , 78 , 79 , 79 , 79 , 79 , 79 , 79 , 80 , 80 , 80 , 80 , 80 , 80 ,
81 , 81 , 81 , 81 , 81 , 81 , 81 , 82 , 82 , 82 , 82 , 82 , 82 , 83 , 83 , 83 , 83 , 84 , 84 , 85 , 85
}
}, //RF_CHAN_BOND_11
//5200 base: ch242
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_242
//5200 base: ch246
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_246
//5200 base: ch250
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_250
//5200 base: ch210
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_210
//5200 base: ch214
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_214
//5200 base: ch38
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_38
//5200 base: ch42
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_42
//5200 base: ch46
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_46
//5200 base: ch50
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_50
//5200 base: ch54
{
{
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 2 , 2 , 2 , 2 , 2 , 3 , 3 , 3 , 3 , 4 , 4 , 4 , 4 , 4 , 5 , 5 , 5 , 5 , 6,
6 , 6 , 6 , 7 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 10 , 11 , 11 , 11 , 11 , 12 ,
12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 16 , 16 , 16 , 17 , 17 , 17 , 18 , 18 , 18 , 19 , 19 ,
19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 23 , 24 , 24 , 24 , 24 , 25 , 25 , 25 , 25 , 26 ,
26 , 26 , 26 , 27 , 27 , 27 , 27 , 28 , 28 , 28 , 28 , 29 , 29 , 29 , 29 , 29 , 30 , 30 , 30 , 30 , 31 , 31 , 31 ,
31 , 32 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 ,
37 , 37 , 37 , 37 , 37 , 37 , 37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 ,
40 , 40 , 41 , 41 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 42 , 42 , 43 , 43 , 43 , 43 , 43 , 44 , 44 , 44 , 44 ,
44 , 44 , 45 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 47 , 47 , 48 , 48 ,
48 , 48 , 48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 ,
51 , 52 , 52 , 52 , 52 , 52 , 53 , 53 , 53 , 54 , 55 , 56 , 57 , 57 , 58 , 59 , 60
}
}, //RF_CHAN_BOND_54
//5500: ch 58
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_58
//5500: ch 62
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_62
//5500: ch 102
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_102
//5500: ch 106
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_106
//5500: ch 110
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_110
//5500: ch 114
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_114
//5500: ch 118
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
0 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_118
//5500: ch 122
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_122
//5500: ch 126
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_126
//5500: ch 130
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_130
//5500: ch 134
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_134
//5500: ch 138
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
//5500: ch 142
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
//5500: ch 151
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_151
//5500: ch 155
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_155
//5500: ch 159
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_159
//5500: ch 163
{
{
4 , 4 , 5 , 5 , 5 , 5 , 5 , 6 , 6 , 6 , 6 , 7 , 7 , 7 , 7 , 8 , 8 , 8 , 8 , 9 , 9 , 9 , 9 , 10 , 10 , 10 , 11 , 11,
11 , 11 , 12 , 12 , 12 , 12 , 12 , 12 , 13 , 13 , 13 , 14 , 14 , 14 , 15 , 15 , 15 , 15 , 15 , 16 , 16 , 16 , 16,
16 , 16 , 17 , 17 , 18 , 18 , 18 , 19 , 19 , 19 , 20 , 20 , 20 , 21 , 21 , 21 , 22 , 22 , 22 , 23 , 23 , 23 , 24,
24 , 24 , 25 , 25 , 25 , 26 , 26 , 26 , 27 , 27 , 27 , 28 , 28 , 28 , 29 , 29 , 29 , 30 , 30 , 30 , 31 , 31 , 31,
31 , 32 , 32 , 32 , 33 , 33 , 33 , 33 , 34 , 34 , 34 , 34 , 35 , 35 , 35 , 35 , 36 , 36 , 36 , 36 , 37 , 37 , 37,
37 , 38 , 38 , 38 , 38 , 39 , 39 , 39 , 39 , 40 , 40 , 40 , 40 , 41 , 41 , 41 , 41 , 42 , 42 , 42 , 42 , 43 , 43,
43 , 43 , 44 , 44 , 44 , 45 , 45 , 45 , 45 , 45 , 46 , 46 , 46 , 46 , 46 , 46 , 47 , 47 , 47 , 47 , 47 , 48 , 48,
48 , 48 , 48 , 49 , 49 , 49 , 49 , 49 , 49 , 50 , 50 , 50 , 50 , 50 , 51 , 51 , 51 , 51 , 51 , 52 , 52 , 52 , 52,
52 , 52 , 53 , 53 , 53 , 53 , 53 , 53 , 54 , 54 , 54 , 54 , 54 , 54 , 55 , 55 , 55 , 55 , 55 , 55 , 56 , 56 , 56,
56 , 56 , 56 , 57 , 57 , 57 , 57 , 57 , 57 , 58 , 58 , 58 , 58 , 58 , 58 , 59 , 59 , 59 , 59 , 59 , 59 , 60 , 60,
60 , 61 , 61 , 61 , 61 , 62 , 62 , 62 , 62 , 62 , 63 , 63 , 63 , 63 , 63 , 64 , 64 , 64 , 65 , 66 , 66
}
}, //RF_CHAN_BOND_163
},
//NV_TABLE_TPC_PDADC_OFFSETS
{
98, // RF_CHAN_1
101, // RF_CHAN_2
101, // RF_CHAN_3
100, // RF_CHAN_4
98, // RF_CHAN_5
97, // RF_CHAN_6
94, // RF_CHAN_7
94, // RF_CHAN_8
92, // RF_CHAN_9
90, // RF_CHAN_10
94, // RF_CHAN_11
95, // RF_CHAN_12
97, // RF_CHAN_13
104, // RF_CHAN_14
100, // RF_CHAN_240
100, // RF_CHAN_244
100, // RF_CHAN_248
100, // RF_CHAN_252
100, // RF_CHAN_208
100, // RF_CHAN_212
100, // RF_CHAN_216
100, // RF_CHAN_36
100, // RF_CHAN_40
100, // RF_CHAN_44
100, // RF_CHAN_48
100, // RF_CHAN_52
100, // RF_CHAN_56
100, // RF_CHAN_60
100, // RF_CHAN_64
100, // RF_CHAN_100
100, // RF_CHAN_104
100, // RF_CHAN_108
100, // RF_CHAN_112
100, // RF_CHAN_116
100, // RF_CHAN_120
100, // RF_CHAN_124
100, // RF_CHAN_128
100, // RF_CHAN_132
100, // RF_CHAN_136
100, // RF_CHAN_140
#ifdef FEATURE_WLAN_CH144
100, // RF_CHAN_144
#endif /* FEATURE_WLAN_CH144 */
100, // RF_CHAN_149
100, // RF_CHAN_153
100, // RF_CHAN_157
100, // RF_CHAN_161
100, // RF_CHAN_165
//CHANNEL BONDED CHANNELS
100, // RF_CHAN_BOND_3
100, // RF_CHAN_BOND_4
100, // RF_CHAN_BOND_5
100, // RF_CHAN_BOND_6
100, // RF_CHAN_BOND_7
100, // RF_CHAN_BOND_8
100, // RF_CHAN_BOND_9
100, // RF_CHAN_BOND_10
100, // RF_CHAN_BOND_11
100, // RF_CHAN_BOND_242
100, // RF_CHAN_BOND_246
100, // RF_CHAN_BOND_250
100, // RF_CHAN_BOND_210
100, // RF_CHAN_BOND_214
100, // RF_CHAN_BOND_38
100, // RF_CHAN_BOND_42
100, // RF_CHAN_BOND_46
100, // RF_CHAN_BOND_50
100, // RF_CHAN_BOND_54
100, // RF_CHAN_BOND_58
100, // RF_CHAN_BOND_62
100, // RF_CHAN_BOND_102
100, // RF_CHAN_BOND_106
100, // RF_CHAN_BOND_110
100, // RF_CHAN_BOND_114
100, // RF_CHAN_BOND_118
100, // RF_CHAN_BOND_122
100, // RF_CHAN_BOND_126
100, // RF_CHAN_BOND_130
100, // RF_CHAN_BOND_134
100, // RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
100, // RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
100, // RF_CHAN_BOND_151
100, // RF_CHAN_BOND_155
100, // RF_CHAN_BOND_159
100, // RF_CHAN_BOND_163
},
//NV_TABLE_VIRTUAL_RATE
// typedef tANI_S16 tPowerdBm;
//typedef tPowerdBm tRateGroupPwr[NUM_HAL_PHY_RATES];
//tRateGroupPwr pwrOptimum[NUM_RF_SUBBANDS];
{
// 2.4G RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 5G Low RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 5G Middle RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 5G High RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 4.9G RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
}
},
#if 0 //FIXME_PRIMA
//NV_TABLE_CAL_MEMORY
{
0x7FFF, // tANI_U16 process_monitor;
0x00, // tANI_U8 hdet_cal_code;
0x00, // tANI_U8 rxfe_gm_2;
0x00, // tANI_U8 tx_bbf_rtune;
0x00, // tANI_U8 pa_rtune_reg;
0x00, // tANI_U8 rt_code;
0x00, // tANI_U8 bias_rtune;
0x00, // tANI_U8 bb_bw1;
0x00, // tANI_U8 bb_bw2;
{ 0x00, 0x00 }, // tANI_U8 reserved[2];
0x00, // tANI_U8 bb_bw3;
0x00, // tANI_U8 bb_bw4;
0x00, // tANI_U8 bb_bw5;
0x00, // tANI_U8 bb_bw6;
0x7FFF, // tANI_U16 rcMeasured;
0x00, // tANI_U8 tx_bbf_ct;
0x00, // tANI_U8 tx_bbf_ctr;
0x00, // tANI_U8 csh_maxgain_reg;
0x00, // tANI_U8 csh_0db_reg;
0x00, // tANI_U8 csh_m3db_reg;
0x00, // tANI_U8 csh_m6db_reg;
0x00, // tANI_U8 cff_0db_reg;
0x00, // tANI_U8 cff_m3db_reg;
0x00, // tANI_U8 cff_m6db_reg;
0x00, // tANI_U8 rxfe_gpio_ctl_1;
0x00, // tANI_U8 mix_bal_cnt_2;
0x00, // tANI_S8 rxfe_lna_highgain_bias_ctl_delta;
0x00, // tANI_U8 rxfe_lna_load_ctune;
0x00, // tANI_U8 rxfe_lna_ngm_rtune;
0x00, // tANI_U8 rx_im2_i_cfg0;
0x00, // tANI_U8 rx_im2_i_cfg1;
0x00, // tANI_U8 rx_im2_q_cfg0;
0x00, // tANI_U8 rx_im2_q_cfg1;
0x00, // tANI_U8 pll_vfc_reg3_b0;
0x00, // tANI_U8 pll_vfc_reg3_b1;
0x00, // tANI_U8 pll_vfc_reg3_b2;
0x00, // tANI_U8 pll_vfc_reg3_b3;
0x7FFF, // tANI_U16 tempStart;
0x7FFF, // tANI_U16 tempFinish;
{ //txLoCorrections
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_1
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_2
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_3
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_4
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_5
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_6
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_7
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_8
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_9
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_10
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_11
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_12
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_13
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
} //RF_CHAN_14
}, // tTxLoCorrections txLoValues;
{ //sTxIQChannel
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_1
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_2
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_3
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_4
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_5
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_6
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_7
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_8
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_9
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_10
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_11
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_12
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_13
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
} //RF_CHAN_14
}, // sTxIQChannel txIqValues;
{ //sRxIQChannel
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_1
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_2
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_3
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_4
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_5
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_6
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_7
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_8
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_9
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_10
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_11
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_12
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_13
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
} //RF_CHAN_14
}, // sRxIQChannel rxIqValues;
{ // tTpcConfig clpcData[MAX_TPC_CHANNELS]
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_1
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_2
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_3
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_4
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_5
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_6
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_7
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_8
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_9
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_10
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_11
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_12
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_13
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
} // RF_CHAN_14
}, // tTpcConfig clpcData[MAX_TPC_CHANNELS];
{
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_1: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_2: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_3: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_4: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_5: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_6: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_7: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_8: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_9: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_10: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_11: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_12: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_13: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } } // RF_CHAN_14: pdadc_offset, reserved[2]
} // tTpcParams clpcParams[MAX_TPC_CHANNELS];
}, //NV_TABLE_CAL_MEMORY
#endif
//NV_TABLE_FW_CONFIG
{
0, //skuID
0, //tpcMode2G
0, //tpcMode5G
0, //reserved1
0, //xPA2G
0, //xPA5G;
0, //paPolarityTx;
0, //paPolarityRx;
0, //xLNA2G;
0, //xLNA5G;
0, //xCoupler2G;
0, //xCoupler5G;
0, //xPdet2G;
0, //xPdet5G;
0, //enableDPD2G;
1, //enableDPD5G;
1, //pdadcSelect2G;
1, //pdadcSelect5GLow;
1, //pdadcSelect5GMid;
1, //pdadcSelect5GHigh;
0, //reserved2
0, //reserved3
0, //reserved4
},
//NV_TABLE_RSSI_CHANNEL_OFFSETS
{
//PHY_RX_CHAIN_0
{
//bRssiOffset
{
240, //RF_CHAN_1,
240, //RF_CHAN_2,
240, //RF_CHAN_3,
240, //RF_CHAN_4,
240, //RF_CHAN_5,
240, //RF_CHAN_6,
240, //RF_CHAN_7,
240, //RF_CHAN_8,
240, //RF_CHAN_9,
240, //RF_CHAN_10,
240, //RF_CHAN_11,
240, //RF_CHAN_12,
240, //RF_CHAN_13,
240, //RF_CHAN_14,
180, //RF_CHAN_240,
180, //RF_CHAN_244,
180, //RF_CHAN_248,
180, //RF_CHAN_252,
180, //RF_CHAN_208,
180, //RF_CHAN_212,
180, //RF_CHAN_216,
180, //RF_CHAN_36,
180, //RF_CHAN_40,
180, //RF_CHAN_44,
180, //RF_CHAN_48,
180, //RF_CHAN_52,
180, //RF_CHAN_56,
180, //RF_CHAN_60,
180, //RF_CHAN_64,
180, //RF_CHAN_100,
180, //RF_CHAN_104,
180, //RF_CHAN_108,
180, //RF_CHAN_112,
180, //RF_CHAN_116,
180, //RF_CHAN_120,
180, //RF_CHAN_124,
180, //RF_CHAN_128,
180, //RF_CHAN_132,
180, //RF_CHAN_136,
180, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
180, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
180, //RF_CHAN_149,
180, //RF_CHAN_153,
180, //RF_CHAN_157,
180, //RF_CHAN_161,
180, //RF_CHAN_165,
240, //RF_CHAN_BOND_3
240, //RF_CHAN_BOND_4
240, //RF_CHAN_BOND_5
240, //RF_CHAN_BOND_6
240, //RF_CHAN_BOND_7
240, //RF_CHAN_BOND_8
240, //RF_CHAN_BOND_9
240, //RF_CHAN_BOND_10
240, //RF_CHAN_BOND_11
180, //RF_CHAN_BOND_242
180, //RF_CHAN_BOND_246
180, //RF_CHAN_BOND_250
180, //RF_CHAN_BOND_210
180, //RF_CHAN_BOND_214
180, //RF_CHAN_BOND_38,
180, //RF_CHAN_BOND_42,
180, //RF_CHAN_BOND_46,
180, //RF_CHAN_BOND_50,
180, //RF_CHAN_BOND_54
180, //RF_CHAN_BOND_58
180, //RF_CHAN_BOND_62
180, //RF_CHAN_BOND_102
180, //RF_CHAN_BOND_106
180, //RF_CHAN_BOND_110
180, //RF_CHAN_BOND_114
180, //RF_CHAN_BOND_118
180, //RF_CHAN_BOND_122
180, //RF_CHAN_BOND_126
180, //RF_CHAN_BOND_130
180, //RF_CHAN_BOND_134
180, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
180, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
180, //RF_CHAN_BOND_151
180, //RF_CHAN_BOND_155
180, //RF_CHAN_BOND_159
180, //RF_CHAN_BOND_163
},
//gnRssiOffset
{
240, //RF_CHAN_1,
240, //RF_CHAN_2,
240, //RF_CHAN_3,
240, //RF_CHAN_4,
240, //RF_CHAN_5,
240, //RF_CHAN_6,
240, //RF_CHAN_7,
240, //RF_CHAN_8,
240, //RF_CHAN_9,
240, //RF_CHAN_10,
240, //RF_CHAN_11,
240, //RF_CHAN_12,
240, //RF_CHAN_13,
240, //RF_CHAN_14,
180, //RF_CHAN_240,
180, //RF_CHAN_244,
180, //RF_CHAN_248,
180, //RF_CHAN_252,
180, //RF_CHAN_208,
180, //RF_CHAN_212,
180, //RF_CHAN_216,
180, //RF_CHAN_36,
180, //RF_CHAN_40,
180, //RF_CHAN_44,
180, //RF_CHAN_48,
180, //RF_CHAN_52,
180, //RF_CHAN_56,
180, //RF_CHAN_60,
180, //RF_CHAN_64,
180, //RF_CHAN_100,
180, //RF_CHAN_104,
180, //RF_CHAN_108,
180, //RF_CHAN_112,
180, //RF_CHAN_116,
180, //RF_CHAN_120,
180, //RF_CHAN_124,
180, //RF_CHAN_128,
180, //RF_CHAN_132,
180, //RF_CHAN_136,
180, //RF_CHAN_140,
#ifdef FEATURE_WLAN_CH144
180, //RF_CHAN_144,
#endif /* FEATURE_WLAN_CH144 */
180, //RF_CHAN_149,
180, //RF_CHAN_153,
180, //RF_CHAN_157,
180, //RF_CHAN_161,
180, //RF_CHAN_165,
240, //RF_CHAN_BOND_3
240, //RF_CHAN_BOND_4
240, //RF_CHAN_BOND_5
240, //RF_CHAN_BOND_6
240, //RF_CHAN_BOND_7
240, //RF_CHAN_BOND_8
240, //RF_CHAN_BOND_9
240, //RF_CHAN_BOND_10
240, //RF_CHAN_BOND_11
180, //RF_CHAN_BOND_242
180, //RF_CHAN_BOND_246
180, //RF_CHAN_BOND_250
180, //RF_CHAN_BOND_210
180, //RF_CHAN_BOND_214
180, //RF_CHAN_BOND_38,
180, //RF_CHAN_BOND_42,
180, //RF_CHAN_BOND_46,
180, //RF_CHAN_BOND_50,
180, //RF_CHAN_BOND_54
180, //RF_CHAN_BOND_58
180, //RF_CHAN_BOND_62
180, //RF_CHAN_BOND_102
180, //RF_CHAN_BOND_106
180, //RF_CHAN_BOND_110
180, //RF_CHAN_BOND_114
180, //RF_CHAN_BOND_118
180, //RF_CHAN_BOND_122
180, //RF_CHAN_BOND_126
180, //RF_CHAN_BOND_130
180, //RF_CHAN_BOND_134
180, //RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
180, //RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
180, //RF_CHAN_BOND_151
180, //RF_CHAN_BOND_155
180, //RF_CHAN_BOND_159
180, //RF_CHAN_BOND_163
},
},
//rsvd
{
//bRssiOffset
{0}, // apply to all channles
//gnRssiOffset
{0} // apply to all channles
}
},
//NV_TABLE_HW_CAL_VALUES
{
0x0, //validBmap
{
1400, //psSlpTimeOvrHd2G;
1400, //psSlpTimeOvrHd5G;
1600, //psSlpTimeOvrHdxLNA5G;
0, //nv_TxBBFSel9MHz
0, //hwParam1
0, //hwParam2
0x1B, //custom_tcxo_reg8
0xFF, //custom_tcxo_reg9
0, //hwParam3;
0, //hwParam4;
0, //hwParam5;
0, //hwParam6;
0, //hwParam7;
0, //hwParam8;
0, //hwParam9;
0, //hwParam10;
0, //hwParam11;
}
},
//NV_TABLE_ANTENNA_PATH_LOSS
{
280, // RF_CHAN_1
270, // RF_CHAN_2
270, // RF_CHAN_3
270, // RF_CHAN_4
270, // RF_CHAN_5
270, // RF_CHAN_6
280, // RF_CHAN_7
280, // RF_CHAN_8
290, // RF_CHAN_9
300, // RF_CHAN_10
300, // RF_CHAN_11
310, // RF_CHAN_12
310, // RF_CHAN_13
310, // RF_CHAN_14
280, // RF_CHAN_240
280, // RF_CHAN_244
280, // RF_CHAN_248
280, // RF_CHAN_252
280, // RF_CHAN_208
280, // RF_CHAN_212
280, // RF_CHAN_216
280, // RF_CHAN_36
280, // RF_CHAN_40
280, // RF_CHAN_44
280, // RF_CHAN_48
280, // RF_CHAN_52
280, // RF_CHAN_56
280, // RF_CHAN_60
280, // RF_CHAN_64
280, // RF_CHAN_100
280, // RF_CHAN_104
280, // RF_CHAN_108
280, // RF_CHAN_112
280, // RF_CHAN_116
280, // RF_CHAN_120
280, // RF_CHAN_124
280, // RF_CHAN_128
280, // RF_CHAN_132
280, // RF_CHAN_136
280, // RF_CHAN_140
#ifdef FEATURE_WLAN_CH144
280, // RF_CHAN_144
#endif /* FEATURE_WLAN_CH144 */
280, // RF_CHAN_149
280, // RF_CHAN_153
280, // RF_CHAN_157
280, // RF_CHAN_161
280, // RF_CHAN_165
//CHANNEL BONDED CHANNELS
280, // RF_CHAN_BOND_3
280, // RF_CHAN_BOND_4
280, // RF_CHAN_BOND_5
280, // RF_CHAN_BOND_6
280, // RF_CHAN_BOND_7
280, // RF_CHAN_BOND_8
280, // RF_CHAN_BOND_9
280, // RF_CHAN_BOND_10
280, // RF_CHAN_BOND_11
280, // RF_CHAN_BOND_242
280, // RF_CHAN_BOND_246
280, // RF_CHAN_BOND_250
280, // RF_CHAN_BOND_210
280, // RF_CHAN_BOND_214
280, // RF_CHAN_BOND_38
280, // RF_CHAN_BOND_42
280, // RF_CHAN_BOND_46
280, // RF_CHAN_BOND_50
280, // RF_CHAN_BOND_54
280, // RF_CHAN_BOND_58
280, // RF_CHAN_BOND_62
280, // RF_CHAN_BOND_102
280, // RF_CHAN_BOND_106
280, // RF_CHAN_BOND_110
280, // RF_CHAN_BOND_114
280, // RF_CHAN_BOND_118
280, // RF_CHAN_BOND_122
280, // RF_CHAN_BOND_126
280, // RF_CHAN_BOND_130
280, // RF_CHAN_BOND_134
280, // RF_CHAN_BOND_138
#ifdef FEATURE_WLAN_CH144
280, // RF_CHAN_BOND_142
#endif /* FEATURE_WLAN_CH144 */
280, // RF_CHAN_BOND_151
280, // RF_CHAN_BOND_155
280, // RF_CHAN_BOND_159
280, // RF_CHAN_BOND_163
},
//NV_TABLE_PACKET_TYPE_POWER_LIMITS
{
{ 2150 }, // applied to all channels, MODE_802_11B
{ 1850 }, // applied to all channels,MODE_802_11AG
{ 1750 } // applied to all channels,MODE_802_11N
},
//NV_TABLE_OFDM_CMD_PWR_OFFSET
{
0, 0
},
//NV_TABLE_TX_BB_FILTER_MODE
{
0
}
} // tables
};
const sHalNvV2 nvDefaultsV2 =
{
{
0, // tANI_U16 productId;
1, // tANI_U8 productBands;
2, // tANI_U8 wlanNvRevId; //0: WCN1312, 1: WCN1314, 2: WCN3660
1, // tANI_U8 numOfTxChains;
1, // tANI_U8 numOfRxChains;
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // tANI_U8 macAddr[NV_FIELD_MAC_ADDR_SIZE];
{ "\0" },
0, // tANI_U8 couplerType;
WLAN_NV_VERSION, // tANI_U8 nvVersion;
}, //fields
{
// NV_TABLE_RATE_POWER_SETTINGS
{
// typedef tANI_S16 tPowerdBm;
//typedef tPowerdBm tRateGroupPwr[NUM_HAL_PHY_RATES];
//tRateGroupPwr pwrOptimum[NUM_RF_SUBBANDS];
//2.4G
{
//802.11b Rates
{1900}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{1900}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{1900}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{1900}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{1900}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{1900}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{1900}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
//11A 20MHz Rates
{1700}, // HAL_PHY_RATE_11A_6_MBPS,
{1700}, // HAL_PHY_RATE_11A_9_MBPS,
{1700}, // HAL_PHY_RATE_11A_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_18_MBPS,
{1600}, // HAL_PHY_RATE_11A_24_MBPS,
{1550}, // HAL_PHY_RATE_11A_36_MBPS,
{1550}, // HAL_PHY_RATE_11A_48_MBPS,
{1550}, // HAL_PHY_RATE_11A_54_MBPS,
//DUP 11A 40MHz Rates
{1700}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
//MCS Index #0-7(20/40MHz)
{1700}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
//MCS Index #8-15(20/40MHz)
{1700}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1700}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1650}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATURE_11AC
//11AC rates
//11A duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
//11ac 20MHZ NG, SG
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{0000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{0000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
//11ac 80MHZ NG, SG
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{0000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_2_4_GHZ
// 5G Low
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DUP 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_11AC
///11AC rates
///11A duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11ac 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
//11ac 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_5_LOW_GHZ
// 5G Mid
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DU P 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCSS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCSS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_111AC
///11CAC rates
///11Ad duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11a c 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
///11a c 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // // RF_SUBBAND_5_MID_GHZ
// 5G High
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DU P 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCSS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCSS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_11AC
///11CAC rates
///11Ad duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11a c 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
///11a c 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_5_HIGH_GHZ,
// 4.9G
{
//802.11b Rates
{0}, // HAL_PHY_RATE_11B_LONG_1_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_2_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_LONG_11_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_2_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_5_5_MBPS,
{0}, // HAL_PHY_RATE_11B_SHORT_11_MBPS,
///11A 20MHz Rates
{1600}, // HAL_PHY_RATE_11A_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_12_MBPS,
{1550}, // HAL_PHY_RATE_11A_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_54_MBPS,
///DU P 11A 40MHz Rates
{1600}, // HAL_PHY_RATE_11A_DUP_6_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_9_MBPS,
{1600}, // HAL_PHY_RATE_11A_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11A_DUP_18_MBPS,
{1550}, // HAL_PHY_RATE_11A_DUP_24_MBPS,
{1450}, // HAL_PHY_RATE_11A_DUP_36_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_48_MBPS,
{1400}, // HAL_PHY_RATE_11A_DUP_54_MBPS,
///MCSS Index #0-7(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_6_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_13_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_19_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_26_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_39_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_52_MBPS,
{1350}, // HAL_PHY_RATE_MCS_1NSS_58_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_65_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_7_2_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_14_4_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_21_7_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_28_9_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_43_3_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_57_8_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_65_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_72_2_MBPS,
///MCSS Index #8-15(20/40MHz)
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_13_5_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_CB_27_MBPS,
{1550}, // HAL_PHY_RATE_MCS_1NSS_CB_40_5_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_CB_54_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_CB_81_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_CB_108_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_CB_121_5_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_CB_135_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_15_MBPS,
{1600}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_30_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_45_MBPS,
{1500}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_60_MBPS,
{1450}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_90_MBPS,
{1400}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_120_MBPS,
{1300}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_135_MBPS,
{1200}, // HAL_PHY_RATE_MCS_1NSS_MM_SG_CB_150_MBPS,
#ifdef WLAN_FEATUURE_11AC
///11CAC rates
///11Ad duplicate 80MHz Rates
{1700}, // HAL_PHY_RATE_11AC_DUP_6_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_9_MBPS,
{1700}, // HAL_PHY_RATE_11AC_DUP_12_MBPS,
{1650}, // HAL_PHY_RATE_11AC_DUP_18_MBPS,
{1600}, // HAL_PHY_RATE_11AC_DUP_24_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_36_MBPS,
{1550}, // HAL_PHY_RATE_11AC_DUP_48_MBPS,
{1500}, // HAL_PHY_RATE_11AC_DUP_54_MBPS,
///11a c 20MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_6_5_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_13_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_19_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_26_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_39_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_52_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_65_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_NGI_78_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_NGI_86_5_MBPS,
#endif
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_7_2_MBPS,
{1400}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_14_4_MBPS,
{1350}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_21_6_MBPS,
{1300}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_28_8_MBPS,
{1250}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_43_3_MBPS,
{1200}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_57_7_MBPS,
{1100}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_72_2_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_CB_SGI_86_6_MBPS,
#ifdef WCN_PRONTO
{ 800}, // HAL_PHY_RATE_VHT_20MHZ_MCS_1NSS_SGI_96_1_MBPS,
#endif
//11ac 40MHZ NG, SG
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_13_5_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_27_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_40_5_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_54_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_81_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_108_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_121_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_135_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_162_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_NGI_180_MBPS,
{1400}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_15_MBPS,
{1300}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_30_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_45_MBPS,
{1250}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_60_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_90_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_120_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_135_MBPS,
{1000}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_150_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_180_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_40MHZ_MCS_1NSS_CB_SGI_200_MBPS,
///11a c 80MHZ NG, SG
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_29_3_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_58_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_87_8_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_117_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_175_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_234_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_263_3_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_292_5_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_351_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_NGI_390_MBPS,
{1300}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_32_5_MBPS,
{1100}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_65_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_97_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_130_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_195_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_260_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_292_5_MBPS,
{1000}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_325_MBPS,
{ 900}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_390_MBPS,
{ 800}, // HAL_PHY_RATE_VHT_80MHZ_MCS_1NSS_CB_SGI_433_3_MBPS,
#endif
}, // RF_SUBBAND_4_9_GHZ
},
// NV_TABLE_REGULATORY_DOMAINS
{
// typedef struct
// {
// tANI_BOOLEAN enabled;
// tPowerdBm pwrLimit;
// }sRegulatoryChannel;
// typedef struct
// {
// sRegulatoryChannel channels[NUM_RF_CHANNELS];
// uAbsPwrPrecision antennaGain[NUM_RF_SUBBANDS];
// uAbsPwrPrecision bRatePowerOffset[NUM_2_4GHZ_CHANNELS];
// }sRegulatoryDomains;
//sRegulatoryDomains regDomains[NUM_REG_DOMAINS];
{ // REG_DOMAIN_FCC start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_11,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_12,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_52,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_56,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_60,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DFS, 22}, //RF_CHAN_100,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_104,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_108,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_112,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_132,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_136,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_FCC end
{ // REG_DOMAIN_ETSI start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 19}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 19}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_149,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_153,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_157,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_161,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 23}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_ETSI end
{ // REG_DOMAIN_JAPAN start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_13,
{NV_CHANNEL_ENABLE, 18}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_52,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_56,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_60,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DFS, 22}, //RF_CHAN_100,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_104,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_108,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_112,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_116,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_120,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_124,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_128,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_132,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_136,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_JAPAN end
{ // REG_DOMAIN_WORLD start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_52,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_56,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_60,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DFS, 22}, //RF_CHAN_100,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_104,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_108,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_112,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_116,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_120,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_124,
{NV_CHANNEL_DFS, 0}, //RF_CHAN_128,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_132,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_136,
{NV_CHANNEL_DFS, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_WORLD end
{ // REG_DOMAIN_N_AMER_EXC_FCC start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_11,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_12,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_N_AMER_EXC_FCC end
{ // REG_DOMAIN_APAC start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 26}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 16}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_APAC end
{ // REG_DOMAIN_KOREA start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 15}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_KOREA end
{ // REG_DOMAIN_HI_5GHZ start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band, none CB
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 14}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
//4.9GHz Band, none CB
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_240,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_244,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_248,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_252,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_208,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_212,
{NV_CHANNEL_DISABLE, 23}, //RF_CHAN_216,
//5GHz Low & Mid U-NII Band, none CB
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_36,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_40,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_44,
{NV_CHANNEL_ENABLE, 17}, //RF_CHAN_48,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_52,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_56,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_60,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_64,
//5GHz Mid Band - ETSI, none CB
{NV_CHANNEL_DISABLE, 22}, //RF_CHAN_100,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_104,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_108,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_112,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_116,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_120,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_124,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_128,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_132,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_136,
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_140,
//5GHz High U-NII Band, none CB
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_149,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_153,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_157,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_161,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_165,
//2.4GHz Band, channel bonded channels
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_3,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_4,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_5,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_6,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_7,
{NV_CHANNEL_ENABLE, 30}, //RF_CHAN_BOND_8,
{NV_CHANNEL_ENABLE, 22}, //RF_CHAN_BOND_9,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_10,
{NV_CHANNEL_ENABLE, 0}, //RF_CHAN_BOND_11,
// 4.9GHz Band, channel bonded channels
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_242,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_246,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_250,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_210,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_214,
//5GHz Low & Mid U-NII Band, channel bonded channels
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_38,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_42,
{NV_CHANNEL_ENABLE, 20}, //RF_CHAN_BOND_46,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_50,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_54,
{NV_CHANNEL_ENABLE, 27}, //RF_CHAN_BOND_58,
{NV_CHANNEL_ENABLE, 25}, //RF_CHAN_BOND_62,
//5GHz Mid Band - ETSI, channel bonded channels
{NV_CHANNEL_DISABLE, 24}, //RF_CHAN_BOND_102
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_106
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_110
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_114
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_118
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_122
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_126
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_130
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_134
{NV_CHANNEL_DISABLE, 27}, //RF_CHAN_BOND_138
//5GHz High U-NII Band, channel bonded channels
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_151,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_155,
{NV_CHANNEL_DISABLE, 30}, //RF_CHAN_BOND_159,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_BOND_163
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
}, // REG_DOMAIN_HI_5GHZ end
{ // REG_DOMAIN_NO_5GHZ start
{ //sRegulatoryChannel start
//enabled, pwrLimit
//2.4GHz Band
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_1,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_2,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_3,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_4,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_5,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_6,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_7,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_8,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_9,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_10,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_11,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_12,
{NV_CHANNEL_ENABLE, 12}, //RF_CHAN_13,
{NV_CHANNEL_DISABLE, 0}, //RF_CHAN_14,
}, //sRegulatoryChannel end
{
{ 0 }, // RF_SUBBAND_2_4_GHZ
{0}, // RF_SUBBAND_5_LOW_GHZ
{0}, // RF_SUBBAND_5_MID_GHZ
{0}, // RF_SUBBAND_5_HIGH_GHZ
{0} // RF_SUBBAND_4_9_GHZ
},
{ // bRatePowerOffset start
//2.4GHz Band
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
}, // bRatePowerOffset end
{ // gnRatePowerOffset start
//apply to all 2.4 and 5G channels
{ 0 }, //RF_CHAN_1,
{ 0 }, //RF_CHAN_2,
{ 0 }, //RF_CHAN_3,
{ 0 }, //RF_CHAN_4,
{ 0 }, //RF_CHAN_5,
{ 0 }, //RF_CHAN_6,
{ 0 }, //RF_CHAN_7,
{ 0 }, //RF_CHAN_8,
{ 0 }, //RF_CHAN_9,
{ 0 }, //RF_CHAN_10,
{ 0 }, //RF_CHAN_11,
{ 0 }, //RF_CHAN_12,
{ 0 }, //RF_CHAN_13,
{ 0 }, //RF_CHAN_14,
} // gnRatePowerOffset end
} // REG_DOMAIN_NO_5GHZ end
},
// NV_TABLE_DEFAULT_COUNTRY
{
// typedef struct
// {
// tANI_U8 regDomain; //from eRegDomainId
// tANI_U8 countryCode[NV_FIELD_COUNTRY_CODE_SIZE]; // string identifier
// }sDefaultCountry;
0, // regDomain
{ 'U', 'S', 'I' } // countryCode
},
//NV_TABLE_TPC_POWER_TABLE
{
{
{
0 , //0
41 , //1
43 , //2
45 , //3
47 , //4
49 , //5
51 , //6
53 , //7
55 , //8
56 , //9
58 , //10
59 , //11
60 , //12
62 , //13
63 , //14
64 , //15
65 , //16
67 , //17
68 , //18
69 , //19
70 , //20
71 , //21
72 , //22
73 , //23
74 , //24
75 , //25
75 , //26
76 , //27
77 , //28
78 , //29
78 , //30
79 , //31
80 , //32
81 , //33
82 , //34
82 , //35
83 , //36
83 , //37
84 , //38
85 , //39
86 , //40
86 , //41
87 , //42
88 , //43
89 , //44
89 , //45
90 , //46
91 , //47
91 , //48
92 , //49
92 , //50
93 , //51
93 , //52
94 , //53
94 , //54
95 , //55
95 , //56
95 , //57
96 , //58
96 , //59
97 , //60
97 , //61
98 , //62
98 , //63
98 , //64
99 , //65
99 , //66
99 , //67
100, //68
100, //69
100, //70
101, //71
101, //72
102, //73
102, //74
102, //75
102, //76
103, //77
103, //78
103, //79
103, //80
104, //81
104, //82
104, //83
104, //84
105, //85
105, //86
105, //87
105, //88
105, //89
106, //90
106, //91
106, //92
106, //93
106, //94
106, //95
106, //96
106, //97
106, //98
106, //99
106, //100
106, //101
106, //102
106, //103
106, //104
106, //105
107, //106
107, //107
107, //108
107, //109
107, //110
107, //111
107, //112
107, //113
107, //114
107, //115
107, //116
107, //117
107, //118
107, //119
107, //120
107, //121
107, //122
107, //123
107, //124
107, //125
107, //126
107, //127
107,
}
}, //RF_CHAN_1
{
{
0 , //0
41 , //1
43 , //2
45 , //3
47 , //4
49 , //5
51 , //6
52 , //7
54 , //8
56 , //9
57 , //10
59 , //11
60 , //12
61 , //13
62 , //14
64 , //15
65 , //16
66 , //17
67 , //18
68 , //19
69 , //20
70 , //21
71 , //22
72 , //23
73 , //24
74 , //25
75 , //26
75 , //27
76 , //28
77 , //29
78 , //30
79 , //31
79 , //32
80 , //33
81 , //34
82 , //35
82 , //36
83 , //37
84 , //38
85 , //39
85 , //40
86 , //41
87 , //42
88 , //43
88 , //44
89 , //45
89 , //46
90 , //47
91 , //48
91 , //49
92 , //50
92 , //51
93 , //52
93 , //53
94 , //54
94 , //55
95 , //56
95 , //57
96 , //58
96 , //59
96 , //60
97 , //61
97 , //62
98 , //63
98 , //64
98 , //65
99 , //66
99 , //67
99 , //68
100, //69
100, //70
101, //71
101, //72
101, //73
101, //74
102, //75
102, //76
102, //77
103, //78
103, //79
103, //80
104, //81
104, //82
104, //83
104, //84
105, //85
105, //86
105, //87
105, //88
105, //89
106, //90
106, //91
106, //92
106, //93
106, //94
106, //95
106, //96
106, //97
106, //98
106, //99
106, //100
106, //101
106, //102
107, //103
107, //104
107, //105
107, //106
107, //107
107, //108
107, //109
107, //110
107, //111
107, //112
107, //113
107, //114
107, //115
107, //116
107, //117
107, //118
107, //119
107, //120
107, //121
107, //122
107, //123
107, //124
107, //125
107, //126
107, //127
107,
}
}, //RF_CHAN_2
{
{
0 , //0
41 , //1
43 , //2
45 , //3
47 , //4
49 , //5
51 , //6
52 , //7
54 , //8
55 , //9
57 , //10
58 , //11
60 , //12
61 , //13
62 , //14
64 , //15
65 , //16
66 , //17
67 , //18
68 , //19
69 , //20
70 , //21
71 , //22
72 , //23
73 , //24
74 , //25
75 , //26
75 , //27
76 , //28
77 , //29
78 , //30
78 , //31
79 , //32
80 , //33
81 , //34
82 , //35
82 , //36
83 , //37
84 , //38
84 , //39
85 , //40
86 , //41
87 , //42
87 , //43
88 , //44
89 , //45
89 , //46
90 , //47
90 , //48
91 , //49
91 , //50
92 , //51
93 , //52
93 , //53
94 , //54
94 , //55
94 , //56
95 , //57
95 , //58
96 , //59
96 , //60
97 , //61
97 , //62
97 , //63
98 , //64
98 , //65
99 , //66
99 , //67
99 , //68
100, //69
100, //70
100, //71
101, //72
101, //73
101, //74
102, //75
102, //76
102, //77
103, //78
103, //79
103, //80
103, //81
104, //82
104, //83
104, //84
104, //85
104, //86
105, //87
105, //88
105, //89
105, //90
105, //91
105, //92
105, //93
105, //94
105, //95
105, //96
105, //97
105, //98
106, //99
106, //100
106, //101
106, //102
106, //103
106, //104
106, //105
106, //106
106, //107
106, //108
106, //109
106, //110
106, //111
106, //112
106, //113
106, //114
106, //115
106, //116
106, //117
106, //118
106, //119
106, //120
106, //121
106, //122
106, //123
106, //124
106, //125
106, //126
106, //127
107,
}
}, //RF_CHAN_3
{
{
0 , //0
42 , //1
44 , //2
46 , //3
48 , //4
49 , //5
51 , //6
53 , //7
55 , //8
57 , //9
58 , //10
60 , //11
61 , //12
62 , //13
63 , //14
64 , //15
66 , //16
67 , //17
68 , //18
69 , //19
70 , //20
71 , //21
72 , //22
73 , //23
74 , //24
75 , //25
75 , //26
76 , //27
77 , //28
78 , //29
78 , //30
79 , //31
80 , //32
81 , //33
82 , //34
82 , //35
83 , //36
84 , //37
84 , //38
85 , //39
86 , //40
87 , //41
87 , //42
88 , //43
88 , //44
89 , //45
90 , //46
90 , //47
91 , //48
91 , //49
92 , //50
92 , //51
93 , //52
93 , //53
94 , //54
94 , //55
95 , //56
95 , //57
95 , //58
96 , //59
96 , //60
97 , //61
97 , //62
98 , //63
98 , //64
98 , //65
99 , //66
99 , //67
99 , //68
100, //69
100, //70
100, //71
101, //72
101, //73
101, //74
102, //75
102, //76
102, //77
103, //78
103, //79
103, //80
103, //81
104, //82
104, //83
104, //84
104, //85
104, //86
104, //87
104, //88
104, //89
105, //90
105, //91
105, //92
105, //93
105, //94
105, //95
105, //96
105, //97
105, //98
105, //99
105, //100
105, //101
105, //102
105, //103
105, //104
106, //105
106, //106
106, //107
106, //108
106, //109
106, //110
106, //111
106, //112
106, //113
106, //114
106, //115
106, //116
106, //117
106, //118
106, //119
106, //120
106, //121
106, //122
106, //123
106, //124
106, //125
106, //126
106, //127
106,
}
}, //RF_CHAN_4
{
{
0 , //0
41 , //1
43 , //2
45 , //3
47 , //4
49 , //5
51 , //6
53 , //7
54 , //8
56 , //9
57 , //10
59 , //11
60 , //12
62 , //13
63 , //14
65 , //15
66 , //16
67 , //17
68 , //18
69 , //19
69 , //20
71 , //21
72 , //22
72 , //23
73 , //24
74 , //25
75 , //26
76 , //27
77 , //28
78 , //29
79 , //30
79 , //31
80 , //32
81 , //33
82 , //34
83 , //35
83 , //36
84 , //37
85 , //38
86 , //39
87 , //40
87 , //41
88 , //42
89 , //43
89 , //44
90 , //45
91 , //46
91 , //47
92 , //48
92 , //49
93 , //50
93 , //51
94 , //52
94 , //53
95 , //54
95 , //55
96 , //56
96 , //57
96 , //58
97 , //59
97 , //60
98 , //61
98 , //62
98 , //63
99 , //64
99 , //65
100, //66
100, //67
100, //68
101, //69
101, //70
101, //71
102, //72
102, //73
102, //74
103, //75
103, //76
103, //77
103, //78
104, //79
104, //80
104, //81
104, //82
105, //83
105, //84
105, //85
105, //86
105, //87
105, //88
105, //89
105, //90
105, //91
106, //92
106, //93
106, //94
106, //95
106, //96
106, //97
106, //98
106, //99
106, //100
106, //101
106, //102
106, //103
106, //104
106, //105
106, //106
106, //107
106, //108
106, //109
106, //110
106, //111
106, //112
106, //113
106, //114
106, //115
106, //116
106, //117
106, //118
106, //119
106, //120
106, //121
106, //122
106, //123
106, //124
106, //125
106, //126
106, //127
106,
}
}, //RF_CHAN_5
{
{
0 , //0
41 , //1
43 , //2
45 , //3
47 , //4
49 , //5
51 , //6
53 , //7
55 , //8
56 , //9
58 , //10
59 , //11
61 , //12
62 , //13
63 , //14
64 , //15
65 , //16
66 , //17
68 , //18
69 , //19
70 , //20
71 , //21
72 , //22
73 , //23
74 , //24
75 , //25
76 , //26
77 , //27
77 , //28
78 , //29
79 , //30
80 , //31
80 , //32
81 , //33
82 , //34
83 , //35
83 , //36
84 , //37
85 , //38
86 , //39
87 , //40
87 , //41
88 , //42
89 , //43
89 , //44
90 , //45
91 , //46
91 , //47
92 , //48
92 , //49
93 , //50
93 , //51
94 , //52
94 , //53
95 , //54
95 , //55
96 , //56
96 , //57
97 , //58
97 , //59
98 , //60
98 , //61
98 , //62
99 , //63
99 , //64
100, //65
100, //66
100, //67
101, //68
101, //69
101, //70
102, //71
102, //72
102, //73
103, //74
103, //75
103, //76
103, //77
104, //78
104, //79
104, //80
104, //81
104, //82
105, //83
105, //84
105, //85
105, //86
105, //87
105, //88
105, //89
106, //90
106, //91
106, //92
106, //93
106, //94
106, //95
106, //96
106, //97
106, //98
106, //99
106, //100
106, //101
106, //102
106, //103
106, //104
106, //105
106, //106
106, //107
106, //108
106, //109
106, //110
107, //111
107, //112
107, //113
107, //114
107, //115
107, //116
107, //117
107, //118
107, //119
107, //120
107, //121
107, //122
107, //123
107, //124
107, //125
107, //126
107, //127
107,
}
}, //RF_CHAN_6
{
{
0 , //0
41 , //1
43 , //2
45 , //3
47 , //4
49 , //5
51 , //6
53 , //7
55 , //8
56 , //9
58 , //10
60 , //11
61 , //12
62 , //13
63 , //14
64 , //15
66 , //16
67 , //17
68 , //18
69 , //19
70 , //20
71 , //21
72 , //22
73 , //23
74 , //24
75 , //25
76 , //26
77 , //27
77 , //28
78 , //29
79 , //30
80 , //31
80 , //32
81 , //33
82 , //34
83 , //35
84 , //36
84 , //37
85 , //38
86 , //39
87 , //40
87 , //41
88 , //42
88 , //43
89 , //44
90 , //45
90 , //46
91 , //47
91 , //48
92 , //49
92 , //50
93 , //51
93 , //52
94 , //53
94 , //54
95 , //55
95 , //56
96 , //57
96 , //58
97 , //59
97 , //60
97 , //61
98 , //62
98 , //63
99 , //64
99 , //65
99 , //66
100, //67
100, //68
100, //69
101, //70
101, //71
101, //72
102, //73
102, //74
102, //75
103, //76
103, //77
103, //78
103, //79
104, //80
104, //81
104, //82
104, //83
104, //84
104, //85
105, //86
105, //87
105, //88
105, //89
105, //90
105, //91
105, //92
105, //93
105, //94
105, //95
105, //96
105, //97
106, //98
106, //99
106, //100
106, //101
106, //102
106, //103
106, //104
106, //105
106, //106
106, //107
106, //108
106, //109
106, //110
106, //111
106, //112
106, //113
106, //114
106, //115
106, //116
106, //117
106, //118
106, //119
106, //120
106, //121
106, //122
106, //123
106, //124
106, //125
106, //126
106, //127
106,
}
}, //RF_CHAN_7
{
{
0 , //0
40 , //1
42 , //2
45 , //3
47 , //4
49 , //5
51 , //6
52 , //7
54 , //8
56 , //9
58 , //10
59 , //11
61 , //12
62 , //13
63 , //14
65 , //15
66 , //16
67 , //17
68 , //18
69 , //19
70 , //20
71 , //21
72 , //22
73 , //23
74 , //24
75 , //25
76 , //26
77 , //27
77 , //28
78 , //29
79 , //30
80 , //31
81 , //32
81 , //33
82 , //34
83 , //35
84 , //36
85 , //37
86 , //38
86 , //39
87 , //40
88 , //41
89 , //42
89 , //43
90 , //44
91 , //45
91 , //46
92 , //47
92 , //48
93 , //49
93 , //50
94 , //51
94 , //52
95 , //53
95 , //54
96 , //55
96 , //56
97 , //57
97 , //58
97 , //59
98 , //60
98 , //61
99 , //62
99 , //63
99 , //64
100, //65
100, //66
100, //67
101, //68
101, //69
102, //70
102, //71
102, //72
103, //73
103, //74
103, //75
104, //76
104, //77
104, //78
104, //79
105, //80
105, //81
105, //82
105, //83
105, //84
105, //85
105, //86
105, //87
106, //88
106, //89
106, //90
106, //91
106, //92
106, //93
106, //94
106, //95
106, //96
106, //97
106, //98
106, //99
106, //100
106, //101
106, //102
106, //103
106, //104
107, //105
107, //106
107, //107
107, //108
107, //109
107, //110
107, //111
107, //112
107, //113
107, //114
107, //115
107, //116
107, //117
107, //118
107, //119
107, //120
107, //121
107, //122
107, //123
107, //124
107, //125
107, //126
107, //127
107,
}
}, //RF_CHAN_8
{
{
0 , //0
41 , //1
44 , //2
46 , //3
48 , //4
50 , //5
52 , //6
54 , //7
56 , //8
58 , //9
59 , //10
60 , //11
62 , //12
63 , //13
64 , //14
66 , //15
67 , //16
68 , //17
69 , //18
70 , //19
71 , //20
72 , //21
73 , //22
74 , //23
75 , //24
76 , //25
77 , //26
78 , //27
79 , //28
79 , //29
80 , //30
81 , //31
82 , //32
83 , //33
83 , //34
84 , //35
85 , //36
86 , //37
87 , //38
87 , //39
88 , //40
89 , //41
89 , //42
90 , //43
91 , //44
91 , //45
92 , //46
92 , //47
93 , //48
93 , //49
94 , //50
94 , //51
95 , //52
95 , //53
96 , //54
96 , //55
97 , //56
97 , //57
98 , //58
98 , //59
98 , //60
99 , //61
99 , //62
100, //63
100, //64
100, //65
101, //66
101, //67
101, //68
102, //69
102, //70
103, //71
103, //72
103, //73
104, //74
104, //75
104, //76
104, //77
105, //78
105, //79
105, //80
105, //81
105, //82
105, //83
106, //84
106, //85
106, //86
106, //87
106, //88
106, //89
106, //90
106, //91
106, //92
106, //93
106, //94
106, //95
106, //96
106, //97
106, //98
107, //99
107, //100
107, //101
107, //102
107, //103
107, //104
107, //105
107, //106
107, //107
107, //108
107, //109
107, //110
107, //111
107, //112
107, //113
107, //114
107, //115
107, //116
107, //117
107, //118
107, //119
107, //120
107, //121
107, //122
107, //123
107, //124
107, //125
107, //126
107, //127
107,
}
}, //RF_CHAN_9
{
{
0 , //0
41 , //1
43 , //2
47 , //3
48 , //4
50 , //5
52 , //6
53 , //7
55 , //8
57 , //9
58 , //10
60 , //11
62 , //12
63 , //13
64 , //14
65 , //15
67 , //16
68 , //17
69 , //18
70 , //19
71 , //20
72 , //21
73 , //22
74 , //23
75 , //24
76 , //25
77 , //26
77 , //27
78 , //28
79 , //29
80 , //30
81 , //31
82 , //32
83 , //33
84 , //34
85 , //35
85 , //36
86 , //37
87 , //38
88 , //39
89 , //40
89 , //41
90 , //42
90 , //43
91 , //44
92 , //45
92 , //46
93 , //47
94 , //48
94 , //49
95 , //50
95 , //51
96 , //52
96 , //53
96 , //54
97 , //55
97 , //56
98 , //57
98 , //58
99 , //59
99 , //60
99 , //61
100, //62
100, //63
101, //64
101, //65
102, //66
102, //67
102, //68
103, //69
103, //70
103, //71
104, //72
104, //73
104, //74
105, //75
105, //76
105, //77
105, //78
105, //79
106, //80
106, //81
106, //82
106, //83
106, //84
106, //85
106, //86
106, //87
106, //88
107, //89
107, //90
107, //91
107, //92
107, //93
107, //94
107, //95
107, //96
107, //97
107, //98
107, //99
107, //100
107, //101
107, //102
107, //103
107, //104
107, //105
107, //106
107, //107
107, //108
107, //109
107, //110
107, //111
107, //112
107, //113
107, //114
107, //115
107, //116
107, //117
107, //118
107, //119
107, //120
107, //121
107, //122
107, //123
107, //124
107, //125
107, //126
107, //127
107,
}
}, //RF_CHAN_10
{
{
0 , //0
42 , //1
44 , //2
47 , //3
49 , //4
51 , //5
52 , //6
54 , //7
55 , //8
57 , //9
58 , //10
60 , //11
61 , //12
63 , //13
64 , //14
65 , //15
66 , //16
67 , //17
69 , //18
70 , //19
71 , //20
72 , //21
73 , //22
74 , //23
75 , //24
76 , //25
77 , //26
77 , //27
78 , //28
79 , //29
80 , //30
81 , //31
82 , //32
82 , //33
83 , //34
84 , //35
85 , //36
86 , //37
86 , //38
87 , //39
88 , //40
89 , //41
90 , //42
90 , //43
91 , //44
91 , //45
92 , //46
92 , //47
93 , //48
93 , //49
94 , //50
94 , //51
95 , //52
96 , //53
96 , //54
97 , //55
97 , //56
97 , //57
98 , //58
98 , //59
99 , //60
99 , //61
100, //62
100, //63
100, //64
101, //65
101, //66
101, //67
102, //68
102, //69
102, //70
103, //71
103, //72
103, //73
103, //74
103, //75
103, //76
104, //77
104, //78
104, //79
104, //80
104, //81
104, //82
104, //83
104, //84
104, //85
104, //86
104, //87
105, //88
105, //89
105, //90
105, //91
105, //92
105, //93
105, //94
105, //95
105, //96
105, //97
105, //98
105, //99
105, //100
105, //101
105, //102
105, //103
105, //104
105, //105
105, //106
105, //107
105, //108
105, //109
105, //110
105, //111
105, //112
105, //113
105, //114
105, //115
105, //116
105, //117
105, //118
105, //119
105, //120
105, //121
105, //122
105, //123
105, //124
105, //125
105, //126
105, //127
}
}, //RF_CHAN_11
{
{
0 , //0
41 , //1
44 , //2
46 , //3
48 , //4
50 , //5
52 , //6
54 , //7
56 , //8
57 , //9
59 , //10
60 , //11
61 , //12
63 , //13
64 , //14
65 , //15
66 , //16
67 , //17
69 , //18
70 , //19
71 , //20
72 , //21
73 , //22
74 , //23
75 , //24
76 , //25
77 , //26
77 , //27
78 , //28
79 , //29
80 , //30
80 , //31
81 , //32
82 , //33
83 , //34
83 , //35
84 , //36
85 , //37
86 , //38
86 , //39
87 , //40
88 , //41
88 , //42
89 , //43
90 , //44
90 , //45
91 , //46
92 , //47
92 , //48
93 , //49
93 , //50
94 , //51
94 , //52
95 , //53
95 , //54
96 , //55
96 , //56
96 , //57
97 , //58
97 , //59
98 , //60
98 , //61
99 , //62
99 , //63
99 , //64
100, //65
100, //66
100, //67
101, //68
101, //69
101, //70
102, //71
102, //72
102, //73
103, //74
103, //75
103, //76
103, //77
103, //78
103, //79
103, //80
104, //81
104, //82
104, //83
104, //84
104, //85
104, //86
104, //87
104, //88
104, //89
104, //90
104, //91
104, //92
104, //93
105, //94
105, //95
105, //96
105, //97
105, //98
105, //99
105, //100
105, //101
105, //102
105, //103
105, //104
105, //105
105, //106
105, //107
105, //108
105, //109
105, //110
105, //111
105, //112
105, //113
105, //114
105, //115
105, //116
105, //117
105, //118
105, //119
105, //120
105, //121
105, //122
105, //123
105, //124
105, //125
105, //126
105, //127
105,
}
}, //RF_CHAN_12
{
{
0 , //0
42 , //1
44 , //2
46 , //3
48 , //4
50 , //5
52 , //6
54 , //7
56 , //8
58 , //9
59 , //10
60 , //11
61 , //12
63 , //13
64 , //14
65 , //15
66 , //16
68 , //17
69 , //18
70 , //19
71 , //20
72 , //21
73 , //22
74 , //23
75 , //24
75 , //25
76 , //26
77 , //27
78 , //28
79 , //29
80 , //30
80 , //31
81 , //32
82 , //33
83 , //34
83 , //35
84 , //36
85 , //37
86 , //38
86 , //39
87 , //40
88 , //41
89 , //42
89 , //43
90 , //44
91 , //45
91 , //46
92 , //47
93 , //48
93 , //49
94 , //50
94 , //51
95 , //52
95 , //53
96 , //54
96 , //55
97 , //56
97 , //57
97 , //58
98 , //59
98 , //60
99 , //61
99 , //62
100, //63
100, //64
100, //65
101, //66
101, //67
101, //68
102, //69
102, //70
102, //71
103, //72
103, //73
103, //74
103, //75
103, //76
103, //77
104, //78
104, //79
104, //80
104, //81
104, //82
104, //83
104, //84
104, //85
104, //86
104, //87
104, //88
104, //89
105, //90
105, //91
105, //92
105, //93
105, //94
105, //95
105, //96
105, //97
105, //98
105, //99
105, //100
105, //101
105, //102
105, //103
105, //104
105, //105
105, //106
105, //107
105, //108
105, //109
105, //110
105, //111
105, //112
105, //113
105, //114
105, //115
105, //116
105, //117
105, //118
105, //119
105, //120
105, //121
105, //122
105, //123
105, //124
105, //125
105, //126
105, //127
105,
}
}, //RF_CHAN_13
{
{
0, //0
40, //1
43, //2
45, //3
47, //4
49, //5
50, //6
52, //7
54, //8
56, //9
57, //10
58, //11
59, //12
60, //13
62, //14
63, //15
64, //16
65, //17
66, //18
67, //19
68, //20
69, //21
70, //22
71, //23
72, //24
73, //25
74, //26
74, //27
75, //28
76, //29
77, //30
78, //31
78, //32
79, //33
80, //34
81, //35
82, //36
83, //37
83, //38
84, //39
85, //40
85, //41
86, //42
87, //43
87, //44
88, //45
89, //46
89, //47
90, //48
90, //49
91, //50
91, //51
92, //52
92, //53
93, //54
93, //55
94, //56
94, //57
95, //58
95, //59
96, //60
96, //61
96, //62
97, //63
97, //64
97, //65
98, //66
98, //67
98, //68
98, //69
99, //70
99, //71
99, //72
99, //73
99, //74
99, //75
99, //76
99, //77
99, //78
99, //79
100, //80
100, //81
100, //82
100, //83
100, //84
100, //85
100, //86
100, //87
100, //88
100, //89
100, //90
100, //91
100, //92
100, //93
100, //94
100, //95
100, //96
100, //97
100, //98
100, //99
100, //100
100, //101
100, //102
100, //103
100, //104
100, //105
100, //106
100, //107
100, //108
100, //109
100, //110
100, //111
100, //112
100, //113
100, //114
100, //115
100, //116
100, //117
100, //118
100, //119
100, //120
100, //121
100, //122
100, //123
100, //124
100, //125
100, //126
100, //127
100,
}
}, //RF_CHAN_14
},
//NV_TABLE_TPC_PDADC_OFFSETS
{
98, // RF_CHAN_1
101, // RF_CHAN_2
101, // RF_CHAN_3
100, // RF_CHAN_4
98, // RF_CHAN_5
97, // RF_CHAN_6
94, // RF_CHAN_7
94, // RF_CHAN_8
92, // RF_CHAN_9
90, // RF_CHAN_10
94, // RF_CHAN_11
95, // RF_CHAN_12
97, // RF_CHAN_13
104, // RF_CHAN_14
100, // RF_CHAN_240
100, // RF_CHAN_244
100, // RF_CHAN_248
100, // RF_CHAN_252
100, // RF_CHAN_208
100, // RF_CHAN_212
100, // RF_CHAN_216
100, // RF_CHAN_36
100, // RF_CHAN_40
100, // RF_CHAN_44
100, // RF_CHAN_48
100, // RF_CHAN_52
100, // RF_CHAN_56
100, // RF_CHAN_60
100, // RF_CHAN_64
100, // RF_CHAN_100
100, // RF_CHAN_104
100, // RF_CHAN_108
100, // RF_CHAN_112
100, // RF_CHAN_116
100, // RF_CHAN_120
100, // RF_CHAN_124
100, // RF_CHAN_128
100, // RF_CHAN_132
100, // RF_CHAN_136
100, // RF_CHAN_140
100, // RF_CHAN_149
100, // RF_CHAN_153
100, // RF_CHAN_157
100, // RF_CHAN_161
100, // RF_CHAN_165
//CHANNEL BONDED CHANNELS
100, // RF_CHAN_BOND_3
100, // RF_CHAN_BOND_4
100, // RF_CHAN_BOND_5
100, // RF_CHAN_BOND_6
100, // RF_CHAN_BOND_7
100, // RF_CHAN_BOND_8
100, // RF_CHAN_BOND_9
100, // RF_CHAN_BOND_10
100, // RF_CHAN_BOND_11
100, // RF_CHAN_BOND_242
100, // RF_CHAN_BOND_246
100, // RF_CHAN_BOND_250
100, // RF_CHAN_BOND_210
100, // RF_CHAN_BOND_214
100, // RF_CHAN_BOND_38
100, // RF_CHAN_BOND_42
100, // RF_CHAN_BOND_46
100, // RF_CHAN_BOND_50
100, // RF_CHAN_BOND_54
100, // RF_CHAN_BOND_58
100, // RF_CHAN_BOND_62
100, // RF_CHAN_BOND_102
100, // RF_CHAN_BOND_106
100, // RF_CHAN_BOND_110
100, // RF_CHAN_BOND_114
100, // RF_CHAN_BOND_118
100, // RF_CHAN_BOND_122
100, // RF_CHAN_BOND_126
100, // RF_CHAN_BOND_130
100, // RF_CHAN_BOND_134
100, // RF_CHAN_BOND_138
100, // RF_CHAN_BOND_151
100, // RF_CHAN_BOND_155
100, // RF_CHAN_BOND_159
100, // RF_CHAN_BOND_163
},
//NV_TABLE_VIRTUAL_RATE
// typedef tANI_S16 tPowerdBm;
//typedef tPowerdBm tRateGroupPwr[NUM_HAL_PHY_RATES];
//tRateGroupPwr pwrOptimum[NUM_RF_SUBBANDS];
{
// 2.4G RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 5G Low RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 5G Middle RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 5G High RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
},
// 4.9G RF Subband
{
//802.11b Rates
{100}, // HAL_PHY_VRATE_11A_54_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_65_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_72_2_MBPS,
{100}, // HAL_PHY_VRATE_MCS_1NSS_CB_135_MBPS
{100}, // HAL_PHY_VRATE_MCS_1NSS_MM_SG_CB_150_MBPS,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
{100}, // RESERVED,
}
},
#if 0 //FIXME_PRIMA
//NV_TABLE_CAL_MEMORY
{
0x7FFF, // tANI_U16 process_monitor;
0x00, // tANI_U8 hdet_cal_code;
0x00, // tANI_U8 rxfe_gm_2;
0x00, // tANI_U8 tx_bbf_rtune;
0x00, // tANI_U8 pa_rtune_reg;
0x00, // tANI_U8 rt_code;
0x00, // tANI_U8 bias_rtune;
0x00, // tANI_U8 bb_bw1;
0x00, // tANI_U8 bb_bw2;
{ 0x00, 0x00 }, // tANI_U8 reserved[2];
0x00, // tANI_U8 bb_bw3;
0x00, // tANI_U8 bb_bw4;
0x00, // tANI_U8 bb_bw5;
0x00, // tANI_U8 bb_bw6;
0x7FFF, // tANI_U16 rcMeasured;
0x00, // tANI_U8 tx_bbf_ct;
0x00, // tANI_U8 tx_bbf_ctr;
0x00, // tANI_U8 csh_maxgain_reg;
0x00, // tANI_U8 csh_0db_reg;
0x00, // tANI_U8 csh_m3db_reg;
0x00, // tANI_U8 csh_m6db_reg;
0x00, // tANI_U8 cff_0db_reg;
0x00, // tANI_U8 cff_m3db_reg;
0x00, // tANI_U8 cff_m6db_reg;
0x00, // tANI_U8 rxfe_gpio_ctl_1;
0x00, // tANI_U8 mix_bal_cnt_2;
0x00, // tANI_S8 rxfe_lna_highgain_bias_ctl_delta;
0x00, // tANI_U8 rxfe_lna_load_ctune;
0x00, // tANI_U8 rxfe_lna_ngm_rtune;
0x00, // tANI_U8 rx_im2_i_cfg0;
0x00, // tANI_U8 rx_im2_i_cfg1;
0x00, // tANI_U8 rx_im2_q_cfg0;
0x00, // tANI_U8 rx_im2_q_cfg1;
0x00, // tANI_U8 pll_vfc_reg3_b0;
0x00, // tANI_U8 pll_vfc_reg3_b1;
0x00, // tANI_U8 pll_vfc_reg3_b2;
0x00, // tANI_U8 pll_vfc_reg3_b3;
0x7FFF, // tANI_U16 tempStart;
0x7FFF, // tANI_U16 tempFinish;
{ //txLoCorrections
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_1
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_2
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_3
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_4
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_5
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_6
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_7
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_8
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_9
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_10
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_11
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_12
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
}, //RF_CHAN_13
{
{ 0x00, 0x00 }, // TX_GAIN_STEP_0
{ 0x00, 0x00 }, // TX_GAIN_STEP_1
{ 0x00, 0x00 }, // TX_GAIN_STEP_2
{ 0x00, 0x00 }, // TX_GAIN_STEP_3
{ 0x00, 0x00 }, // TX_GAIN_STEP_4
{ 0x00, 0x00 }, // TX_GAIN_STEP_5
{ 0x00, 0x00 }, // TX_GAIN_STEP_6
{ 0x00, 0x00 }, // TX_GAIN_STEP_7
{ 0x00, 0x00 }, // TX_GAIN_STEP_8
{ 0x00, 0x00 }, // TX_GAIN_STEP_9
{ 0x00, 0x00 }, // TX_GAIN_STEP_10
{ 0x00, 0x00 }, // TX_GAIN_STEP_11
{ 0x00, 0x00 }, // TX_GAIN_STEP_12
{ 0x00, 0x00 }, // TX_GAIN_STEP_13
{ 0x00, 0x00 }, // TX_GAIN_STEP_14
{ 0x00, 0x00 } // TX_GAIN_STEP_15
} //RF_CHAN_14
}, // tTxLoCorrections txLoValues;
{ //sTxIQChannel
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_1
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_2
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_3
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_4
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_5
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_6
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_7
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_8
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_9
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_10
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_11
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_12
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
}, //RF_CHAN_13
{
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // TX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // TX_GAIN_STEP_15
} //RF_CHAN_14
}, // sTxIQChannel txIqValues;
{ //sRxIQChannel
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_1
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_2
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_3
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_4
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_5
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_6
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_7
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_8
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_9
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_10
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_11
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_12
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
}, //RF_CHAN_13
{
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_0
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_1
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_2
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_3
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_4
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_5
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_6
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_7
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_8
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_9
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_10
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_11
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_12
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_13
{ 0x0000, 0x0000, 0x0000 }, // RX_GAIN_STEP_14
{ 0x0000, 0x0000, 0x0000 } // RX_GAIN_STEP_15
} //RF_CHAN_14
}, // sRxIQChannel rxIqValues;
{ // tTpcConfig clpcData[MAX_TPC_CHANNELS]
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_1
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_2
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_3
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_4
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_5
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_6
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_7
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_8
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_9
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_10
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_11
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_12
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
}, // RF_CHAN_13
{
{
{
{ 0x00, 0x00 }, //CAL_POINT_0
{ 0x00, 0x00 }, //CAL_POINT_1
{ 0x00, 0x00 }, //CAL_POINT_2
{ 0x00, 0x00 }, //CAL_POINT_3
{ 0x00, 0x00 }, //CAL_POINT_4
{ 0x00, 0x00 }, //CAL_POINT_5
{ 0x00, 0x00 }, //CAL_POINT_6
{ 0x00, 0x00 } //CAL_POINT_7
} // PHY_TX_CHAIN_0
} // empirical
} // RF_CHAN_14
}, // tTpcConfig clpcData[MAX_TPC_CHANNELS];
{
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_1: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_2: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_3: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_4: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_5: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_6: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_7: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_8: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_9: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_10: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_11: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_12: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } }, // RF_CHAN_13: pdadc_offset, reserved[2]
{ 0x0000, { 0x00, 0x00 } } // RF_CHAN_14: pdadc_offset, reserved[2]
} // tTpcParams clpcParams[MAX_TPC_CHANNELS];
}, //NV_TABLE_CAL_MEMORY
#endif
//NV_TABLE_FW_CONFIG
{
0, //skuID
0, //tpcMode2G
0, //tpcMode5G
0, //reserved1
0, //xPA2G
0, //xPA5G;
0, //paPolarityTx;
0, //paPolarityRx;
0, //xLNA2G;
0, //xLNA5G;
0, //xCoupler2G;
0, //xCoupler5G;
0, //xPdet2G;
0, //xPdet5G;
0, //enableDPD2G;
1, //enableDPD5G;
1, //pdadcSelect2G;
1, //pdadcSelect5GLow;
1, //pdadcSelect5GMid;
1, //pdadcSelect5GHigh;
0, //reserved2
0, //reserved3
0, //reserved4
},
//NV_TABLE_RSSI_CHANNEL_OFFSETS
{
//PHY_RX_CHAIN_0
{
//bRssiOffset
{300}, // apply to all channles
//gnRssiOffset
{300} // apply to all channles
},
//rsvd
{
//bRssiOffset
{0}, // apply to all channles
//gnRssiOffset
{0} // apply to all channles
}
},
//NV_TABLE_HW_CAL_VALUES
{
0x0, //validBmap
{
1400, //psSlpTimeOvrHd2G;
1400, //psSlpTimeOvrHd5G;
1600, //psSlpTimeOvrHdxLNA5G;
0, //nv_TxBBFSel9MHz
0, //hwParam1
0, //hwParam2
0x1B, //custom_tcxo_reg8
0xFF, //custom_tcxo_reg9
0, //hwParam3;
0, //hwParam4;
0, //hwParam5;
0, //hwParam6;
0, //hwParam7;
0, //hwParam8;
0, //hwParam9;
0, //hwParam10;
0, //hwParam11;
}
},
//NV_TABLE_ANTENNA_PATH_LOSS
{
280, // RF_CHAN_1
270, // RF_CHAN_2
270, // RF_CHAN_3
270, // RF_CHAN_4
270, // RF_CHAN_5
270, // RF_CHAN_6
280, // RF_CHAN_7
280, // RF_CHAN_8
290, // RF_CHAN_9
300, // RF_CHAN_10
300, // RF_CHAN_11
310, // RF_CHAN_12
310, // RF_CHAN_13
310, // RF_CHAN_14
280, // RF_CHAN_240
280, // RF_CHAN_244
280, // RF_CHAN_248
280, // RF_CHAN_252
280, // RF_CHAN_208
280, // RF_CHAN_212
280, // RF_CHAN_216
280, // RF_CHAN_36
280, // RF_CHAN_40
280, // RF_CHAN_44
280, // RF_CHAN_48
280, // RF_CHAN_52
280, // RF_CHAN_56
280, // RF_CHAN_60
280, // RF_CHAN_64
280, // RF_CHAN_100
280, // RF_CHAN_104
280, // RF_CHAN_108
280, // RF_CHAN_112
280, // RF_CHAN_116
280, // RF_CHAN_120
280, // RF_CHAN_124
280, // RF_CHAN_128
280, // RF_CHAN_132
280, // RF_CHAN_136
280, // RF_CHAN_140
280, // RF_CHAN_149
280, // RF_CHAN_153
280, // RF_CHAN_157
280, // RF_CHAN_161
280, // RF_CHAN_165
//CHANNEL BONDED CHANNELS
280, // RF_CHAN_BOND_3
280, // RF_CHAN_BOND_4
280, // RF_CHAN_BOND_5
280, // RF_CHAN_BOND_6
280, // RF_CHAN_BOND_7
280, // RF_CHAN_BOND_8
280, // RF_CHAN_BOND_9
280, // RF_CHAN_BOND_10
280, // RF_CHAN_BOND_11
280, // RF_CHAN_BOND_242
280, // RF_CHAN_BOND_246
280, // RF_CHAN_BOND_250
280, // RF_CHAN_BOND_210
280, // RF_CHAN_BOND_214
280, // RF_CHAN_BOND_38
280, // RF_CHAN_BOND_42
280, // RF_CHAN_BOND_46
280, // RF_CHAN_BOND_50
280, // RF_CHAN_BOND_54
280, // RF_CHAN_BOND_58
280, // RF_CHAN_BOND_62
280, // RF_CHAN_BOND_102
280, // RF_CHAN_BOND_106
280, // RF_CHAN_BOND_110
280, // RF_CHAN_BOND_114
280, // RF_CHAN_BOND_118
280, // RF_CHAN_BOND_122
280, // RF_CHAN_BOND_126
280, // RF_CHAN_BOND_130
280, // RF_CHAN_BOND_134
280, // RF_CHAN_BOND_138
280, // RF_CHAN_BOND_151
280, // RF_CHAN_BOND_155
280, // RF_CHAN_BOND_159
280, // RF_CHAN_BOND_163
},
//NV_TABLE_PACKET_TYPE_POWER_LIMITS
{
{ 2150 }, // applied to all channels, MODE_802_11B
{ 1850 }, // applied to all channels,MODE_802_11AG
{ 1750 } // applied to all channels,MODE_802_11N
},
//NV_TABLE_OFDM_CMD_PWR_OFFSET
{
0, 0
},
//NV_TABLE_TX_BB_FILTER_MODE
{
0
}
} // tables
};
#endif
| gpl-2.0 |
sudeepdutt/mic | drivers/staging/rtl8723au/hal/HalDMOutSrc8723A_CE.c | 945 | 33608 | /******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/* Description: */
/* This file is for 92CE/92CU dynamic mechanism only */
/* include files */
#include "odm_precomp.h"
#include <usb_ops_linux.h>
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
/* 091212 chiyokolin */
static void
odm_TXPowerTrackingCallback_ThermalMeter_92C(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, delta_HP;
int ele_A, ele_D, TempCCk, X, value32;
int Y, ele_C;
s8 OFDM_index[2], CCK_index = 0, OFDM_index_old[2] = {0};
s8 CCK_index_old = 0;
int i = 0;
u8 OFDM_min_index = 6, rf; /* OFDM BB Swing should be less than +3.0dB*/
u8 ThermalValue_HP_count = 0;
u32 ThermalValue_HP = 0;
s32 index_mapping_HP[index_mapping_HP_NUM] = {
0, 1, 3, 4, 6,
7, 9, 10, 12, 13,
15, 16, 18, 19, 21
};
s8 index_HP;
pdmpriv->TXPowerTrackingCallbackCnt++; /* cosa add for debug */
pdmpriv->bTXPowerTrackingInit = true;
if (pHalData->CurrentChannel == 14 && !pdmpriv->bCCKinCH14)
pdmpriv->bCCKinCH14 = true;
else if (pHalData->CurrentChannel != 14 && pdmpriv->bCCKinCH14)
pdmpriv->bCCKinCH14 = false;
ThermalValue = (u8)PHY_QueryRFReg(Adapter, RF_PATH_A, RF_T_METER,
0x1f);/* 0x24: RF Reg[4:0] */
rtl8723a_phy_ap_calibrate(Adapter, (ThermalValue -
pHalData->EEPROMThermalMeter));
if (pHalData->rf_type == RF_2T2R)
rf = 2;
else
rf = 1;
if (ThermalValue) {
/* Query OFDM path A default setting */
ele_D = rtl8723au_read32(Adapter, rOFDM0_XATxIQImbalance) &
bMaskOFDM_D;
for (i = 0; i < OFDM_TABLE_SIZE_92C; i++) {
/* find the index */
if (ele_D == (OFDMSwingTable23A[i]&bMaskOFDM_D)) {
OFDM_index_old[0] = (u8)i;
break;
}
}
/* Query OFDM path B default setting */
if (pHalData->rf_type == RF_2T2R) {
ele_D = rtl8723au_read32(Adapter,
rOFDM0_XBTxIQImbalance);
ele_D &= bMaskOFDM_D;
for (i = 0; i < OFDM_TABLE_SIZE_92C; i++) { /* find the index */
if (ele_D == (OFDMSwingTable23A[i]&bMaskOFDM_D)) {
OFDM_index_old[1] = (u8)i;
break;
}
}
}
/* Query CCK default setting From 0xa24 */
TempCCk = rtl8723au_read32(Adapter, rCCK0_TxFilter2) & bMaskCCK;
for (i = 0 ; i < CCK_TABLE_SIZE ; i++) {
if (pdmpriv->bCCKinCH14) {
if (!memcmp(&TempCCk,
&CCKSwingTable_Ch1423A[i][2], 4)) {
CCK_index_old = (u8)i;
break;
}
} else {
if (!memcmp(&TempCCk,
&CCKSwingTable_Ch1_Ch1323A[i][2], 4)) {
CCK_index_old = (u8)i;
break;
}
}
}
if (!pdmpriv->ThermalValue) {
pdmpriv->ThermalValue = pHalData->EEPROMThermalMeter;
pdmpriv->ThermalValue_LCK = ThermalValue;
pdmpriv->ThermalValue_IQK = ThermalValue;
pdmpriv->ThermalValue_DPK = pHalData->EEPROMThermalMeter;
for (i = 0; i < rf; i++) {
pdmpriv->OFDM_index_HP[i] = OFDM_index_old[i];
pdmpriv->OFDM_index[i] = OFDM_index_old[i];
}
pdmpriv->CCK_index_HP = CCK_index_old;
pdmpriv->CCK_index = CCK_index_old;
}
if (pHalData->BoardType == BOARD_USB_High_PA) {
pdmpriv->ThermalValue_HP[pdmpriv->ThermalValue_HP_index] = ThermalValue;
pdmpriv->ThermalValue_HP_index++;
if (pdmpriv->ThermalValue_HP_index == HP_THERMAL_NUM)
pdmpriv->ThermalValue_HP_index = 0;
for (i = 0; i < HP_THERMAL_NUM; i++) {
if (pdmpriv->ThermalValue_HP[i]) {
ThermalValue_HP += pdmpriv->ThermalValue_HP[i];
ThermalValue_HP_count++;
}
}
if (ThermalValue_HP_count)
ThermalValue = (u8)(ThermalValue_HP / ThermalValue_HP_count);
}
delta = (ThermalValue > pdmpriv->ThermalValue) ?
(ThermalValue - pdmpriv->ThermalValue) :
(pdmpriv->ThermalValue - ThermalValue);
if (pHalData->BoardType == BOARD_USB_High_PA) {
if (pdmpriv->bDoneTxpower)
delta_HP = (ThermalValue > pdmpriv->ThermalValue) ?
(ThermalValue - pdmpriv->ThermalValue) :
(pdmpriv->ThermalValue - ThermalValue);
else
delta_HP = ThermalValue > pHalData->EEPROMThermalMeter ?
(ThermalValue - pHalData->EEPROMThermalMeter) :
(pHalData->EEPROMThermalMeter - ThermalValue);
} else {
delta_HP = 0;
}
delta_LCK = (ThermalValue > pdmpriv->ThermalValue_LCK) ?
(ThermalValue - pdmpriv->ThermalValue_LCK) :
(pdmpriv->ThermalValue_LCK - ThermalValue);
delta_IQK = (ThermalValue > pdmpriv->ThermalValue_IQK) ?
(ThermalValue - pdmpriv->ThermalValue_IQK) :
(pdmpriv->ThermalValue_IQK - ThermalValue);
if (delta_LCK > 1) {
pdmpriv->ThermalValue_LCK = ThermalValue;
rtl8723a_phy_lc_calibrate(Adapter);
}
if ((delta > 0 || delta_HP > 0) && pdmpriv->TxPowerTrackControl) {
if (pHalData->BoardType == BOARD_USB_High_PA) {
pdmpriv->bDoneTxpower = true;
delta_HP = ThermalValue > pHalData->EEPROMThermalMeter ?
(ThermalValue - pHalData->EEPROMThermalMeter) :
(pHalData->EEPROMThermalMeter - ThermalValue);
if (delta_HP > index_mapping_HP_NUM-1)
index_HP = index_mapping_HP[index_mapping_HP_NUM-1];
else
index_HP = index_mapping_HP[delta_HP];
if (ThermalValue > pHalData->EEPROMThermalMeter) {
/* set larger Tx power */
for (i = 0; i < rf; i++)
OFDM_index[i] = pdmpriv->OFDM_index_HP[i] - index_HP;
CCK_index = pdmpriv->CCK_index_HP - index_HP;
} else {
for (i = 0; i < rf; i++)
OFDM_index[i] = pdmpriv->OFDM_index_HP[i] + index_HP;
CCK_index = pdmpriv->CCK_index_HP + index_HP;
}
delta_HP = (ThermalValue > pdmpriv->ThermalValue) ?
(ThermalValue - pdmpriv->ThermalValue) :
(pdmpriv->ThermalValue - ThermalValue);
} else {
if (ThermalValue > pdmpriv->ThermalValue) {
for (i = 0; i < rf; i++)
pdmpriv->OFDM_index[i] -= delta;
pdmpriv->CCK_index -= delta;
} else {
for (i = 0; i < rf; i++)
pdmpriv->OFDM_index[i] += delta;
pdmpriv->CCK_index += delta;
}
}
/* no adjust */
if (pHalData->BoardType != BOARD_USB_High_PA) {
if (ThermalValue > pHalData->EEPROMThermalMeter) {
for (i = 0; i < rf; i++)
OFDM_index[i] = pdmpriv->OFDM_index[i]+1;
CCK_index = pdmpriv->CCK_index+1;
} else {
for (i = 0; i < rf; i++)
OFDM_index[i] = pdmpriv->OFDM_index[i];
CCK_index = pdmpriv->CCK_index;
}
}
for (i = 0; i < rf; i++) {
if (OFDM_index[i] > (OFDM_TABLE_SIZE_92C-1))
OFDM_index[i] = (OFDM_TABLE_SIZE_92C-1);
else if (OFDM_index[i] < OFDM_min_index)
OFDM_index[i] = OFDM_min_index;
}
if (CCK_index > (CCK_TABLE_SIZE-1))
CCK_index = CCK_TABLE_SIZE-1;
else if (CCK_index < 0)
CCK_index = 0;
}
if (pdmpriv->TxPowerTrackControl &&
(delta != 0 || delta_HP != 0)) {
/* Adujst OFDM Ant_A according to IQK result */
ele_D = (OFDMSwingTable23A[OFDM_index[0]] & 0xFFC00000)>>22;
X = pdmpriv->RegE94;
Y = pdmpriv->RegE9C;
if (X != 0) {
if ((X & 0x00000200) != 0)
X = X | 0xFFFFFC00;
ele_A = ((X * ele_D)>>8)&0x000003FF;
/* new element C = element D x Y */
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
ele_C = ((Y * ele_D)>>8)&0x000003FF;
/* write new elements A, C, D to regC80 and regC94, element B is always 0 */
value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
rtl8723au_write32(Adapter,
rOFDM0_XATxIQImbalance,
value32);
value32 = (ele_C&0x000003C0)>>6;
PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
value32 = ((X * ele_D)>>7)&0x01;
PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold,
BIT(31), value32);
value32 = ((Y * ele_D)>>7)&0x01;
PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold,
BIT(29), value32);
} else {
rtl8723au_write32(Adapter,
rOFDM0_XATxIQImbalance,
OFDMSwingTable23A[OFDM_index[0]]);
PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE,
bMaskH4Bits, 0x00);
PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold,
BIT(31) | BIT(29), 0x00);
}
/* Adjust CCK according to IQK result */
if (!pdmpriv->bCCKinCH14) {
rtl8723au_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch1323A[CCK_index][0]);
rtl8723au_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch1323A[CCK_index][1]);
rtl8723au_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch1323A[CCK_index][2]);
rtl8723au_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch1323A[CCK_index][3]);
rtl8723au_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch1323A[CCK_index][4]);
rtl8723au_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch1323A[CCK_index][5]);
rtl8723au_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch1323A[CCK_index][6]);
rtl8723au_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch1323A[CCK_index][7]);
} else {
rtl8723au_write8(Adapter, 0xa22, CCKSwingTable_Ch1423A[CCK_index][0]);
rtl8723au_write8(Adapter, 0xa23, CCKSwingTable_Ch1423A[CCK_index][1]);
rtl8723au_write8(Adapter, 0xa24, CCKSwingTable_Ch1423A[CCK_index][2]);
rtl8723au_write8(Adapter, 0xa25, CCKSwingTable_Ch1423A[CCK_index][3]);
rtl8723au_write8(Adapter, 0xa26, CCKSwingTable_Ch1423A[CCK_index][4]);
rtl8723au_write8(Adapter, 0xa27, CCKSwingTable_Ch1423A[CCK_index][5]);
rtl8723au_write8(Adapter, 0xa28, CCKSwingTable_Ch1423A[CCK_index][6]);
rtl8723au_write8(Adapter, 0xa29, CCKSwingTable_Ch1423A[CCK_index][7]);
}
if (pHalData->rf_type == RF_2T2R) {
ele_D = (OFDMSwingTable23A[(u8)OFDM_index[1]] & 0xFFC00000)>>22;
/* new element A = element D x X */
X = pdmpriv->RegEB4;
Y = pdmpriv->RegEBC;
if (X != 0) {
if ((X & 0x00000200) != 0) /* consider minus */
X = X | 0xFFFFFC00;
ele_A = ((X * ele_D)>>8)&0x000003FF;
/* new element C = element D x Y */
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
ele_C = ((Y * ele_D)>>8)&0x00003FF;
/* write new elements A, C, D to regC88 and regC9C, element B is always 0 */
value32 = (ele_D<<22)|((ele_C&0x3F)<<16) | ele_A;
rtl8723au_write32(Adapter, rOFDM0_XBTxIQImbalance, value32);
value32 = (ele_C&0x000003C0)>>6;
PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
value32 = ((X * ele_D)>>7)&0x01;
PHY_SetBBReg(Adapter,
rOFDM0_ECCAThreshold,
BIT(27), value32);
value32 = ((Y * ele_D)>>7)&0x01;
PHY_SetBBReg(Adapter,
rOFDM0_ECCAThreshold,
BIT(25), value32);
} else {
rtl8723au_write32(Adapter,
rOFDM0_XBTxIQImbalance,
OFDMSwingTable23A[OFDM_index[1]]);
PHY_SetBBReg(Adapter,
rOFDM0_XDTxAFE,
bMaskH4Bits, 0x00);
PHY_SetBBReg(Adapter,
rOFDM0_ECCAThreshold,
BIT(27) | BIT(25), 0x00);
}
}
}
if (delta_IQK > 3) {
pdmpriv->ThermalValue_IQK = ThermalValue;
rtl8723a_phy_iq_calibrate(Adapter, false);
}
/* update thermal meter value */
if (pdmpriv->TxPowerTrackControl)
pdmpriv->ThermalValue = ThermalValue;
}
pdmpriv->TXPowercount = 0;
}
/* Description: */
/* - Dispatch TxPower Tracking direct call ONLY for 92s. */
/* - We shall NOT schedule Workitem within PASSIVE LEVEL, which will cause system resource */
/* leakage under some platform. */
/* Assumption: */
/* PASSIVE_LEVEL when this routine is called. */
static void ODM_TXPowerTracking92CDirectCall(struct rtw_adapter *Adapter)
{
odm_TXPowerTrackingCallback_ThermalMeter_92C(Adapter);
}
void rtl8723a_odm_check_tx_power_tracking(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
if (!pdmpriv->TM_Trigger) { /* at least delay 1 sec */
PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
pdmpriv->TM_Trigger = 1;
return;
} else {
ODM_TXPowerTracking92CDirectCall(Adapter);
pdmpriv->TM_Trigger = 0;
}
}
/* IQK */
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 /* ms */
static u8 _PHY_PathA_IQK(struct rtw_adapter *pAdapter, bool configPathB)
{
u32 regEAC, regE94, regE9C, regEA4;
u8 result = 0x00;
struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
/* path-A IQK setting */
rtl8723au_write32(pAdapter, rTx_IQK_Tone_A, 0x10008c1f);
rtl8723au_write32(pAdapter, rRx_IQK_Tone_A, 0x10008c1f);
rtl8723au_write32(pAdapter, rTx_IQK_PI_A, 0x82140102);
rtl8723au_write32(pAdapter, rRx_IQK_PI_A, configPathB ? 0x28160202 :
IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
/* path-B IQK setting */
if (configPathB) {
rtl8723au_write32(pAdapter, rTx_IQK_Tone_B, 0x10008c22);
rtl8723au_write32(pAdapter, rRx_IQK_Tone_B, 0x10008c22);
rtl8723au_write32(pAdapter, rTx_IQK_PI_B, 0x82140102);
rtl8723au_write32(pAdapter, rRx_IQK_PI_B, 0x28160202);
}
/* LO calibration setting */
rtl8723au_write32(pAdapter, rIQK_AGC_Rsp, 0x001028d1);
/* One shot, path A LOK & IQK */
rtl8723au_write32(pAdapter, rIQK_AGC_Pts, 0xf9000000);
rtl8723au_write32(pAdapter, rIQK_AGC_Pts, 0xf8000000);
/* delay x ms */
/* PlatformStallExecution(IQK_DELAY_TIME*1000); */
udelay(IQK_DELAY_TIME*1000);
/* Check failed */
regEAC = rtl8723au_read32(pAdapter, rRx_Power_After_IQK_A_2);
regE94 = rtl8723au_read32(pAdapter, rTx_Power_Before_IQK_A);
regE9C = rtl8723au_read32(pAdapter, rTx_Power_After_IQK_A);
regEA4 = rtl8723au_read32(pAdapter, rRx_Power_Before_IQK_A_2);
if (!(regEAC & BIT(28)) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42))
result |= 0x01;
else /* if Tx not OK, ignore Rx */
return result;
if (!(regEAC & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
else
DBG_8723A("Path A Rx IQK fail!!\n");
return result;
}
static u8 _PHY_PathB_IQK(struct rtw_adapter *pAdapter)
{
u32 regEAC, regEB4, regEBC, regEC4, regECC;
u8 result = 0x00;
/* One shot, path B LOK & IQK */
rtl8723au_write32(pAdapter, rIQK_AGC_Cont, 0x00000002);
rtl8723au_write32(pAdapter, rIQK_AGC_Cont, 0x00000000);
/* delay x ms */
udelay(IQK_DELAY_TIME*1000);
/* Check failed */
regEAC = rtl8723au_read32(pAdapter, rRx_Power_After_IQK_A_2);
regEB4 = rtl8723au_read32(pAdapter, rTx_Power_Before_IQK_B);
regEBC = rtl8723au_read32(pAdapter, rTx_Power_After_IQK_B);
regEC4 = rtl8723au_read32(pAdapter, rRx_Power_Before_IQK_B_2);
regECC = rtl8723au_read32(pAdapter, rRx_Power_After_IQK_B_2);
if (!(regEAC & BIT(31)) &&
(((regEB4 & 0x03FF0000)>>16) != 0x142) &&
(((regEBC & 0x03FF0000)>>16) != 0x42))
result |= 0x01;
else
return result;
if (!(regEAC & BIT(30)) &&
(((regEC4 & 0x03FF0000)>>16) != 0x132) &&
(((regECC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
else
DBG_8723A("Path B Rx IQK fail!!\n");
return result;
}
static void _PHY_PathAFillIQKMatrix(struct rtw_adapter *pAdapter,
bool bIQKOK,
int result[][8],
u8 final_candidate,
bool bTxOnly
)
{
u32 Oldval_0, X, TX0_A, reg;
s32 Y, TX0_C;
DBG_8723A("Path A IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed");
if (final_candidate == 0xFF) {
return;
} else if (bIQKOK) {
Oldval_0 = rtl8723au_read32(pAdapter, rOFDM0_XATxIQImbalance);
Oldval_0 = (Oldval_0 >> 22) & 0x3FF;
X = result[final_candidate][0];
if ((X & 0x00000200) != 0)
X = X | 0xFFFFFC00;
TX0_A = (X * Oldval_0) >> 8;
PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31),
((X * Oldval_0>>7) & 0x1));
Y = result[final_candidate][1];
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
TX0_C = (Y * Oldval_0) >> 8;
PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000,
((TX0_C&0x3C0)>>6));
PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000,
(TX0_C&0x3F));
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29),
((Y * Oldval_0>>7) & 0x1));
if (bTxOnly) {
DBG_8723A("_PHY_PathAFillIQKMatrix only Tx OK\n");
return;
}
reg = result[final_candidate][2];
PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
reg = result[final_candidate][3] & 0x3F;
PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
reg = (result[final_candidate][3] >> 6) & 0xF;
PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
}
}
static void _PHY_PathBFillIQKMatrix(struct rtw_adapter *pAdapter, bool bIQKOK, int result[][8], u8 final_candidate, bool bTxOnly)
{
u32 Oldval_1, X, TX1_A, reg;
s32 Y, TX1_C;
DBG_8723A("Path B IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed");
if (final_candidate == 0xFF) {
return;
} else if (bIQKOK) {
Oldval_1 = rtl8723au_read32(pAdapter, rOFDM0_XBTxIQImbalance);
Oldval_1 = (Oldval_1 >> 22) & 0x3FF;
X = result[final_candidate][4];
if ((X & 0x00000200) != 0)
X = X | 0xFFFFFC00;
TX1_A = (X * Oldval_1) >> 8;
PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27),
((X * Oldval_1 >> 7) & 0x1));
Y = result[final_candidate][5];
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
TX1_C = (Y * Oldval_1) >> 8;
PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000,
((TX1_C & 0x3C0) >> 6));
PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000,
(TX1_C & 0x3F));
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25),
((Y * Oldval_1 >> 7) & 0x1));
if (bTxOnly)
return;
reg = result[final_candidate][6];
PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
reg = result[final_candidate][7] & 0x3F;
PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
reg = (result[final_candidate][7] >> 6) & 0xF;
PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg);
}
}
static void _PHY_SaveADDARegisters(struct rtw_adapter *pAdapter, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum)
{
u32 i;
for (i = 0 ; i < RegisterNum ; i++) {
ADDABackup[i] = rtl8723au_read32(pAdapter, ADDAReg[i]);
}
}
static void _PHY_SaveMACRegisters(struct rtw_adapter *pAdapter, u32 *MACReg,
u32 *MACBackup)
{
u32 i;
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
MACBackup[i] = rtl8723au_read8(pAdapter, MACReg[i]);
}
MACBackup[i] = rtl8723au_read32(pAdapter, MACReg[i]);
}
static void _PHY_ReloadADDARegisters(struct rtw_adapter *pAdapter,
u32 *ADDAReg, u32 *ADDABackup,
u32 RegiesterNum)
{
u32 i;
for (i = 0 ; i < RegiesterNum ; i++) {
rtl8723au_write32(pAdapter, ADDAReg[i], ADDABackup[i]);
}
}
static void _PHY_ReloadMACRegisters(struct rtw_adapter *pAdapter,
u32 *MACReg, u32 *MACBackup)
{
u32 i;
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++)
rtl8723au_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
rtl8723au_write32(pAdapter, MACReg[i], MACBackup[i]);
}
static void _PHY_PathADDAOn(struct rtw_adapter *pAdapter, u32 *ADDAReg,
bool isPathAOn, bool is2T)
{
u32 pathOn;
u32 i;
pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
if (!is2T) {
pathOn = 0x0bdb25a0;
rtl8723au_write32(pAdapter, ADDAReg[0], 0x0b1b25a0);
} else {
rtl8723au_write32(pAdapter, ADDAReg[0], pathOn);
}
for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++)
rtl8723au_write32(pAdapter, ADDAReg[i], pathOn);
}
static void _PHY_MACSettingCalibration(struct rtw_adapter *pAdapter,
u32 *MACReg, u32 *MACBackup)
{
u32 i = 0;
rtl8723au_write8(pAdapter, MACReg[i], 0x3F);
for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
rtl8723au_write8(pAdapter, MACReg[i],
(u8)(MACBackup[i] & ~BIT(3)));
}
rtl8723au_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(5)));
}
static void _PHY_PathAStandBy(struct rtw_adapter *pAdapter)
{
rtl8723au_write32(pAdapter, rFPGA0_IQK, 0x0);
rtl8723au_write32(pAdapter, 0x840, 0x00010000);
rtl8723au_write32(pAdapter, rFPGA0_IQK, 0x80800000);
}
static void _PHY_PIModeSwitch(struct rtw_adapter *pAdapter, bool PIMode)
{
u32 mode;
mode = PIMode ? 0x01000100 : 0x01000000;
rtl8723au_write32(pAdapter, 0x820, mode);
rtl8723au_write32(pAdapter, 0x828, mode);
}
/*
return false => do IQK again
*/
static bool _PHY_SimularityCompare(struct rtw_adapter *pAdapter, int result[][8], u8 c1, u8 c2)
{
u32 i, j, diff, SimularityBitMap, bound = 0;
struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
bool bResult = true;
if (pHalData->rf_type == RF_2T2R)
bound = 8;
else
bound = 4;
SimularityBitMap = 0;
for (i = 0; i < bound; i++) {
diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
if (diff > MAX_TOLERANCE) {
if ((i == 2 || i == 6) && !SimularityBitMap) {
if (result[c1][i]+result[c1][i+1] == 0)
final_candidate[(i/4)] = c2;
else if (result[c2][i]+result[c2][i+1] == 0)
final_candidate[(i/4)] = c1;
else
SimularityBitMap = SimularityBitMap|(1<<i);
} else {
SimularityBitMap = SimularityBitMap|(1<<i);
}
}
}
if (SimularityBitMap == 0) {
for (i = 0; i < (bound/4); i++) {
if (final_candidate[i] != 0xFF) {
for (j = i*4; j < (i+1)*4-2; j++)
result[3][j] = result[final_candidate[i]][j];
bResult = false;
}
}
return bResult;
} else if (!(SimularityBitMap & 0x0F)) {
/* path A OK */
for (i = 0; i < 4; i++)
result[3][i] = result[c1][i];
return false;
} else if (!(SimularityBitMap & 0xF0) && pHalData->rf_type == RF_2T2R) {
/* path B OK */
for (i = 4; i < 8; i++)
result[3][i] = result[c1][i];
return false;
} else {
return false;
}
}
static void _PHY_IQCalibrate(struct rtw_adapter *pAdapter, int result[][8], u8 t, bool is2T)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u32 i;
u8 PathAOK, PathBOK;
u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN
};
u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
};
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
};
const u32 retryCount = 2;
/* Note: IQ calibration must be performed after loading */
/* PHY_REG.txt , and radio_a, radio_b.txt */
u32 bbvalue;
if (t == 0) {
bbvalue = rtl8723au_read32(pAdapter, rFPGA0_RFMOD);
/* Save ADDA parameters, turn Path A ADDA on */
_PHY_SaveADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
_PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
}
_PHY_PathADDAOn(pAdapter, ADDA_REG, true, is2T);
if (t == 0)
pdmpriv->bRfPiEnable = (u8)
PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1,
BIT(8));
if (!pdmpriv->bRfPiEnable) {
/* Switch BB to PI mode to do IQ Calibration. */
_PHY_PIModeSwitch(pAdapter, true);
}
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT(24), 0x00);
rtl8723au_write32(pAdapter, rOFDM0_TRxPathEnable, 0x03a05600);
rtl8723au_write32(pAdapter, rOFDM0_TRMuxPar, 0x000800e4);
rtl8723au_write32(pAdapter, rFPGA0_XCD_RFInterfaceSW, 0x22204000);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
if (is2T) {
rtl8723au_write32(pAdapter,
rFPGA0_XA_LSSIParameter, 0x00010000);
rtl8723au_write32(pAdapter,
rFPGA0_XB_LSSIParameter, 0x00010000);
}
/* MAC settings */
_PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
/* Page B init */
rtl8723au_write32(pAdapter, rConfig_AntA, 0x00080000);
if (is2T)
rtl8723au_write32(pAdapter, rConfig_AntB, 0x00080000);
/* IQ calibration setting */
rtl8723au_write32(pAdapter, rFPGA0_IQK, 0x80800000);
rtl8723au_write32(pAdapter, rTx_IQK, 0x01007c00);
rtl8723au_write32(pAdapter, rRx_IQK, 0x01004800);
for (i = 0 ; i < retryCount ; i++) {
PathAOK = _PHY_PathA_IQK(pAdapter, is2T);
if (PathAOK == 0x03) {
DBG_8723A("Path A IQK Success!!\n");
result[t][0] = (rtl8723au_read32(pAdapter, rTx_Power_Before_IQK_A)&0x3FF0000)>>16;
result[t][1] = (rtl8723au_read32(pAdapter, rTx_Power_After_IQK_A)&0x3FF0000)>>16;
result[t][2] = (rtl8723au_read32(pAdapter, rRx_Power_Before_IQK_A_2)&0x3FF0000)>>16;
result[t][3] = (rtl8723au_read32(pAdapter, rRx_Power_After_IQK_A_2)&0x3FF0000)>>16;
break;
} else if (i == (retryCount-1) && PathAOK == 0x01) {
/* Tx IQK OK */
DBG_8723A("Path A IQK Only Tx Success!!\n");
result[t][0] = (rtl8723au_read32(pAdapter, rTx_Power_Before_IQK_A)&0x3FF0000)>>16;
result[t][1] = (rtl8723au_read32(pAdapter, rTx_Power_After_IQK_A)&0x3FF0000)>>16;
}
}
if (0x00 == PathAOK) {
DBG_8723A("Path A IQK failed!!\n");
}
if (is2T) {
_PHY_PathAStandBy(pAdapter);
/* Turn Path B ADDA on */
_PHY_PathADDAOn(pAdapter, ADDA_REG, false, is2T);
for (i = 0 ; i < retryCount ; i++) {
PathBOK = _PHY_PathB_IQK(pAdapter);
if (PathBOK == 0x03) {
DBG_8723A("Path B IQK Success!!\n");
result[t][4] = (rtl8723au_read32(pAdapter, rTx_Power_Before_IQK_B)&0x3FF0000)>>16;
result[t][5] = (rtl8723au_read32(pAdapter, rTx_Power_After_IQK_B)&0x3FF0000)>>16;
result[t][6] = (rtl8723au_read32(pAdapter, rRx_Power_Before_IQK_B_2)&0x3FF0000)>>16;
result[t][7] = (rtl8723au_read32(pAdapter, rRx_Power_After_IQK_B_2)&0x3FF0000)>>16;
break;
} else if (i == (retryCount - 1) && PathBOK == 0x01) {
/* Tx IQK OK */
DBG_8723A("Path B Only Tx IQK Success!!\n");
result[t][4] = (rtl8723au_read32(pAdapter, rTx_Power_Before_IQK_B)&0x3FF0000)>>16;
result[t][5] = (rtl8723au_read32(pAdapter, rTx_Power_After_IQK_B)&0x3FF0000)>>16;
}
}
if (0x00 == PathBOK) {
DBG_8723A("Path B IQK failed!!\n");
}
}
/* Back to BB mode, load original value */
rtl8723au_write32(pAdapter, rFPGA0_IQK, 0);
if (t != 0) {
if (!pdmpriv->bRfPiEnable) {
/* Switch back BB to SI mode after finish IQ Calibration. */
_PHY_PIModeSwitch(pAdapter, false);
}
/* Reload ADDA power saving parameters */
_PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup, IQK_ADDA_REG_NUM);
/* Reload MAC parameters */
_PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
/* Reload BB parameters */
_PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
/* Restore RX initial gain */
rtl8723au_write32(pAdapter,
rFPGA0_XA_LSSIParameter, 0x00032ed3);
if (is2T) {
rtl8723au_write32(pAdapter,
rFPGA0_XB_LSSIParameter, 0x00032ed3);
}
/* load 0xe30 IQC default value */
rtl8723au_write32(pAdapter, rTx_IQK_Tone_A, 0x01008c00);
rtl8723au_write32(pAdapter, rRx_IQK_Tone_A, 0x01008c00);
}
}
static void _PHY_LCCalibrate(struct rtw_adapter *pAdapter, bool is2T)
{
u8 tmpReg;
u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
/* Check continuous TX and Packet TX */
tmpReg = rtl8723au_read8(pAdapter, 0xd03);
if ((tmpReg&0x70) != 0) {
/* Deal with contisuous TX case */
/* disable all continuous TX */
rtl8723au_write8(pAdapter, 0xd03, tmpReg&0x8F);
} else {
/* Deal with Packet TX case */
/* block all queues */
rtl8723au_write8(pAdapter, REG_TXPAUSE, 0xFF);
}
if ((tmpReg&0x70) != 0) {
/* 1. Read original RF mode */
/* Path-A */
RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
/* Path-B */
if (is2T)
RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
/* 2. Set RF mode = standby mode */
/* Path-A */
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
/* Path-B */
if (is2T)
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
}
/* 3. Read RF reg18 */
LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
/* 4. Set LC calibration begin */
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
msleep(100);
/* Restore original situation */
if ((tmpReg&0x70) != 0) { /* Deal with contuous TX case */
/* Path-A */
rtl8723au_write8(pAdapter, 0xd03, tmpReg);
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
/* Path-B */
if (is2T)
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
} else /* Deal with Packet TX case */
rtl8723au_write8(pAdapter, REG_TXPAUSE, 0x00);
}
/* Analog Pre-distortion calibration */
#define APK_BB_REG_NUM 8
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
void rtl8723a_phy_iq_calibrate(struct rtw_adapter *pAdapter, bool bReCovery)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
s32 result[4][8]; /* last is final result */
u8 i, final_candidate;
bool bPathAOK, bPathBOK;
s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4;
s32 RegECC, RegTmp = 0;
bool is12simular, is13simular, is23simular;
bool bStartContTx = false, bSingleTone = false;
bool bCarrierSuppression = false;
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_RxIQExtAnta
};
/* ignore IQK when continuous Tx */
if (bStartContTx || bSingleTone || bCarrierSuppression)
return;
if (bReCovery) {
_PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
return;
}
DBG_8723A("IQK:Start!!!\n");
for (i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
result[2][i] = 0;
result[3][i] = 0;
}
final_candidate = 0xff;
bPathAOK = false;
bPathBOK = false;
is12simular = false;
is23simular = false;
is13simular = false;
for (i = 0; i < 3; i++) {
if (pHalData->rf_type == RF_2T2R)
_PHY_IQCalibrate(pAdapter, result, i, true);
else /* For 88C 1T1R */
_PHY_IQCalibrate(pAdapter, result, i, false);
if (i == 1) {
is12simular = _PHY_SimularityCompare(pAdapter, result, 0, 1);
if (is12simular) {
final_candidate = 0;
break;
}
}
if (i == 2) {
is13simular = _PHY_SimularityCompare(pAdapter, result, 0, 2);
if (is13simular) {
final_candidate = 0;
break;
}
is23simular = _PHY_SimularityCompare(pAdapter, result, 1, 2);
if (is23simular) {
final_candidate = 1;
} else {
for (i = 0; i < 8; i++)
RegTmp += result[3][i];
if (RegTmp != 0)
final_candidate = 3;
else
final_candidate = 0xFF;
}
}
}
for (i = 0; i < 4; i++) {
RegE94 = result[i][0];
RegE9C = result[i][1];
RegEA4 = result[i][2];
RegEAC = result[i][3];
RegEB4 = result[i][4];
RegEBC = result[i][5];
RegEC4 = result[i][6];
RegECC = result[i][7];
}
if (final_candidate != 0xff) {
RegE94 = result[final_candidate][0];
pdmpriv->RegE94 = RegE94;
RegE9C = result[final_candidate][1];
pdmpriv->RegE9C = RegE9C;
RegEA4 = result[final_candidate][2];
RegEAC = result[final_candidate][3];
RegEB4 = result[final_candidate][4];
pdmpriv->RegEB4 = RegEB4;
RegEBC = result[final_candidate][5];
pdmpriv->RegEBC = RegEBC;
RegEC4 = result[final_candidate][6];
RegECC = result[final_candidate][7];
DBG_8723A("IQK: final_candidate is %x\n", final_candidate);
DBG_8723A("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ",
RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC);
bPathAOK = bPathBOK = true;
} else {
RegE94 = RegEB4 = pdmpriv->RegE94 = pdmpriv->RegEB4 = 0x100; /* X default value */
RegE9C = RegEBC = pdmpriv->RegE9C = pdmpriv->RegEBC = 0x0; /* Y default value */
}
if ((RegE94 != 0)/*&&(RegEA4 != 0)*/)
_PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
if (pHalData->rf_type == RF_2T2R) {
if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
_PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result,
final_candidate, (RegEC4 == 0));
}
_PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
}
void rtl8723a_phy_lc_calibrate(struct rtw_adapter *pAdapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
struct mlme_ext_priv *pmlmeext = &pAdapter->mlmeextpriv;
bool bStartContTx = false, bSingleTone = false, bCarrierSuppression = false;
/* ignore IQK when continuous Tx */
if (bStartContTx || bSingleTone || bCarrierSuppression)
return;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
return;
if (pHalData->rf_type == RF_2T2R)
_PHY_LCCalibrate(pAdapter, true);
else /* For 88C 1T1R */
_PHY_LCCalibrate(pAdapter, false);
}
void
rtl8723a_phy_ap_calibrate(struct rtw_adapter *pAdapter, char delta)
{
}
| gpl-2.0 |
HealthyMarshmallow/android_kernel_lge_g2 | drivers/staging/prima/CORE/SYS/legacy/src/pal/src/palTimer.c | 945 | 6713 | /*
* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
This file contains function implementations for the Platform
Abstration Layer.
*/
#include <halTypes.h>
#include <palTimer.h>
#include <vos_timer.h>
#include <vos_memory.h>
#ifndef FEATURE_WLAN_PAL_TIMER_DISABLE
typedef struct sPalTimer
{
palTimerCallback timerCallback;
void *pContext;
tHddHandle hHdd; // not really needed when mapping to vos timers
tANI_U32 uTimerInterval; //meaningful only is fRestart is true
tANI_BOOLEAN fRestart;
vos_timer_t vosTimer;
} tPalTimer, *tpPalTimer;
v_VOID_t internalTimerCallback( v_PVOID_t userData )
{
tPalTimer *pPalTimer = (tPalTimer *)userData;
if ( pPalTimer )
{
if ( pPalTimer->timerCallback )
{
pPalTimer->timerCallback( pPalTimer->pContext );
}
if ( pPalTimer->fRestart )
{
palTimerStart( pPalTimer->hHdd, pPalTimer, pPalTimer->uTimerInterval, eANI_BOOLEAN_TRUE );
}
}
}
#ifdef TIMER_MANAGER
eHalStatus palTimerAlloc_debug( tHddHandle hHdd, tPalTimerHandle *phPalTimer,
palTimerCallback pCallback, void *pContext, char* fileName, v_U32_t lineNum )
{
eHalStatus halStatus = eHAL_STATUS_FAILURE;
tPalTimer *pPalTimer = NULL;
VOS_STATUS vosStatus;
do
{
// allocate the internal timer structure.
pPalTimer = vos_mem_malloc( sizeof( tPalTimer ) );
if ( NULL == pPalTimer ) break;
// initialize the vos Timer that underlies the pal Timer.
vosStatus = vos_timer_init_debug( &pPalTimer->vosTimer, VOS_TIMER_TYPE_SW,
internalTimerCallback, pPalTimer, fileName, lineNum );
if ( !VOS_IS_STATUS_SUCCESS( vosStatus ) )
{
// if fail to init the vos timer, free the memory and bail out.
vos_mem_free( pPalTimer );
break;
}
// initialize the info in the internal palTimer struct so we can
pPalTimer->timerCallback = pCallback;
pPalTimer->pContext = pContext;
pPalTimer->hHdd = hHdd;
// return a 'handle' to the caller.
*phPalTimer = pPalTimer;
halStatus = eHAL_STATUS_SUCCESS;
} while( 0 );
return( halStatus );
}
#else
eHalStatus palTimerAlloc( tHddHandle hHdd, tPalTimerHandle *phPalTimer,
palTimerCallback pCallback, void *pContext )
{
eHalStatus halStatus = eHAL_STATUS_FAILURE;
tPalTimer *pPalTimer = NULL;
VOS_STATUS vosStatus;
do
{
// allocate the internal timer structure.
pPalTimer = vos_mem_malloc( sizeof( tPalTimer ) );
if ( NULL == pPalTimer ) break;
// initialize the vos Timer that underlies the pal Timer.
vosStatus = vos_timer_init( &pPalTimer->vosTimer, VOS_TIMER_TYPE_SW,
internalTimerCallback, pPalTimer );
if ( !VOS_IS_STATUS_SUCCESS( vosStatus ) )
{
// if fail to init the vos timer, free the memory and bail out.
vos_mem_free( pPalTimer );
break;
}
// initialize the info in the internal palTimer struct so we can
pPalTimer->timerCallback = pCallback;
pPalTimer->pContext = pContext;
pPalTimer->hHdd = hHdd;
// return a 'handle' to the caller.
*phPalTimer = pPalTimer;
halStatus = eHAL_STATUS_SUCCESS;
} while( 0 );
return( halStatus );
}
#endif
eHalStatus palTimerFree( tHddHandle hHdd, tPalTimerHandle hPalTimer )
{
eHalStatus status = eHAL_STATUS_INVALID_PARAMETER;
VOS_STATUS vosStatus;
tPalTimer *pPalTimer = (tPalTimer *)hPalTimer;
do
{
if ( NULL == pPalTimer ) break;
// Destroy the vos timer...
vosStatus = vos_timer_destroy( &pPalTimer->vosTimer );
if ( !VOS_IS_STATUS_SUCCESS( vosStatus ) ) break;
// Free the memory for the intrnal timer struct...
vos_mem_free( pPalTimer );
status = eHAL_STATUS_SUCCESS;
} while( 0 );
return( status );
}
eHalStatus palTimerStart(tHddHandle hHdd, tPalTimerHandle hPalTimer, tANI_U32 uExpireTime, tANI_BOOLEAN fRestart)
{
eHalStatus status = eHAL_STATUS_INVALID_PARAMETER;
VOS_STATUS vosStatus;
tANI_U32 expireTimeInMS = 0;
tPalTimer *pPalTimer = (tPalTimer *)hPalTimer;
do
{
if ( NULL == pPalTimer ) break;
pPalTimer->fRestart = fRestart;
pPalTimer->uTimerInterval = uExpireTime;
// vos Timer takes expiration time in milliseconds. palTimerStart and
// the uTimerIntervl in tPalTimer struct have expiration tiem in
// microseconds. Make and adjustment from microseconds to milliseconds
// before calling the vos_timer_start().
expireTimeInMS = uExpireTime / 1000;
vosStatus = vos_timer_start( &pPalTimer->vosTimer, expireTimeInMS );
if ( !VOS_IS_STATUS_SUCCESS( vosStatus ) )
{
status = eHAL_STATUS_FAILURE;
break;
}
status = eHAL_STATUS_SUCCESS;
} while( 0 );
return( status );
}
eHalStatus palTimerStop(tHddHandle hHdd, tPalTimerHandle hPalTimer)
{
eHalStatus status = eHAL_STATUS_INVALID_PARAMETER;
tPalTimer *pPalTimer = (tPalTimer *)hPalTimer;
do
{
if ( NULL == pPalTimer ) break;
vos_timer_stop( &pPalTimer->vosTimer );
// make sure the timer is not re-started.
pPalTimer->fRestart = eANI_BOOLEAN_FALSE;
status = eHAL_STATUS_SUCCESS;
} while( 0 );
return( status );
}
#endif
| gpl-2.0 |
aatjitra/OPO | drivers/staging/prima/CORE/SYS/legacy/src/utils/src/utilsApi.c | 945 | 2583 | /*
* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
//==================================================================
//
// File: utilsApi.cc
//
// Description: Implemention of a few utility routines.
//
// Author: Neelay Das
//
//
//
// Change gHistory:
// 12/15/2003 - NDA - Initial version.
//
//===================================================================
#include "utilsApi.h"
// -------------------------------------------------------------------
/**
* sirDumpBuf()
*
* FUNCTION:
* This function is called to dump a buffer with a certain level
*
* LOGIC:
*
* ASSUMPTIONS:
* None.
*
* NOTE:
*
* @param pBuf: buffer pointer
* @return None.
*/
void
sirDumpBuf(tpAniSirGlobal pMac, tANI_U8 modId, tANI_U32 level, tANI_U8 *buf, tANI_U32 size)
{
tANI_U32 i;
if (level > pMac->utils.gLogDbgLevel[LOG_INDEX_FOR_MODULE(modId)])
return;
logDbg(pMac, modId, level, FL("Dumping %d bytes in host order\n"), size);
for (i=0; (i+7)<size; i+=8)
{
logDbg(pMac, modId, level,
"%02x %02x %02x %02x %02x %02x %02x %02x \n",
buf[i],
buf[i+1],
buf[i+2],
buf[i+3],
buf[i+4],
buf[i+5],
buf[i+6],
buf[i+7]);
}
// Dump the bytes in the last line
for (; i < size; i++)
{
logDbg(pMac, modId, level, "%02x ", buf[i]);
if((i+1) == size)
logDbg(pMac, modId, level, "\n");
}
}/*** end sirDumpBuf() ***/
| gpl-2.0 |
garrikus/o3_linux | net/sctp/proc.c | 1201 | 13843 | /* SCTP kernel implementation
* Copyright (c) 2003 International Business Machines, Corp.
*
* This file is part of the SCTP kernel implementation
*
* This SCTP implementation is free software;
* you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This SCTP implementation is distributed in the hope that it
* will be useful, but WITHOUT ANY WARRANTY; without even the implied
* ************************
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU CC; see the file COPYING. If not, write to
* the Free Software Foundation, 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA.
*
* Please send any bug reports or fixes you make to the
* email address(es):
* lksctp developers <lksctp-developers@lists.sourceforge.net>
*
* Or submit a bug report through the following website:
* http://www.sf.net/projects/lksctp
*
* Written or modified by:
* Sridhar Samudrala <sri@us.ibm.com>
*
* Any bugs reported given to us we will try to fix... any fixes shared will
* be incorporated into the next SCTP release.
*/
#include <linux/types.h>
#include <linux/seq_file.h>
#include <linux/init.h>
#include <net/sctp/sctp.h>
#include <net/ip.h> /* for snmp_fold_field */
static const struct snmp_mib sctp_snmp_list[] = {
SNMP_MIB_ITEM("SctpCurrEstab", SCTP_MIB_CURRESTAB),
SNMP_MIB_ITEM("SctpActiveEstabs", SCTP_MIB_ACTIVEESTABS),
SNMP_MIB_ITEM("SctpPassiveEstabs", SCTP_MIB_PASSIVEESTABS),
SNMP_MIB_ITEM("SctpAborteds", SCTP_MIB_ABORTEDS),
SNMP_MIB_ITEM("SctpShutdowns", SCTP_MIB_SHUTDOWNS),
SNMP_MIB_ITEM("SctpOutOfBlues", SCTP_MIB_OUTOFBLUES),
SNMP_MIB_ITEM("SctpChecksumErrors", SCTP_MIB_CHECKSUMERRORS),
SNMP_MIB_ITEM("SctpOutCtrlChunks", SCTP_MIB_OUTCTRLCHUNKS),
SNMP_MIB_ITEM("SctpOutOrderChunks", SCTP_MIB_OUTORDERCHUNKS),
SNMP_MIB_ITEM("SctpOutUnorderChunks", SCTP_MIB_OUTUNORDERCHUNKS),
SNMP_MIB_ITEM("SctpInCtrlChunks", SCTP_MIB_INCTRLCHUNKS),
SNMP_MIB_ITEM("SctpInOrderChunks", SCTP_MIB_INORDERCHUNKS),
SNMP_MIB_ITEM("SctpInUnorderChunks", SCTP_MIB_INUNORDERCHUNKS),
SNMP_MIB_ITEM("SctpFragUsrMsgs", SCTP_MIB_FRAGUSRMSGS),
SNMP_MIB_ITEM("SctpReasmUsrMsgs", SCTP_MIB_REASMUSRMSGS),
SNMP_MIB_ITEM("SctpOutSCTPPacks", SCTP_MIB_OUTSCTPPACKS),
SNMP_MIB_ITEM("SctpInSCTPPacks", SCTP_MIB_INSCTPPACKS),
SNMP_MIB_ITEM("SctpT1InitExpireds", SCTP_MIB_T1_INIT_EXPIREDS),
SNMP_MIB_ITEM("SctpT1CookieExpireds", SCTP_MIB_T1_COOKIE_EXPIREDS),
SNMP_MIB_ITEM("SctpT2ShutdownExpireds", SCTP_MIB_T2_SHUTDOWN_EXPIREDS),
SNMP_MIB_ITEM("SctpT3RtxExpireds", SCTP_MIB_T3_RTX_EXPIREDS),
SNMP_MIB_ITEM("SctpT4RtoExpireds", SCTP_MIB_T4_RTO_EXPIREDS),
SNMP_MIB_ITEM("SctpT5ShutdownGuardExpireds", SCTP_MIB_T5_SHUTDOWN_GUARD_EXPIREDS),
SNMP_MIB_ITEM("SctpDelaySackExpireds", SCTP_MIB_DELAY_SACK_EXPIREDS),
SNMP_MIB_ITEM("SctpAutocloseExpireds", SCTP_MIB_AUTOCLOSE_EXPIREDS),
SNMP_MIB_ITEM("SctpT3Retransmits", SCTP_MIB_T3_RETRANSMITS),
SNMP_MIB_ITEM("SctpPmtudRetransmits", SCTP_MIB_PMTUD_RETRANSMITS),
SNMP_MIB_ITEM("SctpFastRetransmits", SCTP_MIB_FAST_RETRANSMITS),
SNMP_MIB_ITEM("SctpInPktSoftirq", SCTP_MIB_IN_PKT_SOFTIRQ),
SNMP_MIB_ITEM("SctpInPktBacklog", SCTP_MIB_IN_PKT_BACKLOG),
SNMP_MIB_ITEM("SctpInPktDiscards", SCTP_MIB_IN_PKT_DISCARDS),
SNMP_MIB_ITEM("SctpInDataChunkDiscards", SCTP_MIB_IN_DATA_CHUNK_DISCARDS),
SNMP_MIB_SENTINEL
};
/* Display sctp snmp mib statistics(/proc/net/sctp/snmp). */
static int sctp_snmp_seq_show(struct seq_file *seq, void *v)
{
int i;
for (i = 0; sctp_snmp_list[i].name != NULL; i++)
seq_printf(seq, "%-32s\t%ld\n", sctp_snmp_list[i].name,
snmp_fold_field((void __percpu **)sctp_statistics,
sctp_snmp_list[i].entry));
return 0;
}
/* Initialize the seq file operations for 'snmp' object. */
static int sctp_snmp_seq_open(struct inode *inode, struct file *file)
{
return single_open(file, sctp_snmp_seq_show, NULL);
}
static const struct file_operations sctp_snmp_seq_fops = {
.owner = THIS_MODULE,
.open = sctp_snmp_seq_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
/* Set up the proc fs entry for 'snmp' object. */
int __init sctp_snmp_proc_init(void)
{
struct proc_dir_entry *p;
p = proc_create("snmp", S_IRUGO, proc_net_sctp, &sctp_snmp_seq_fops);
if (!p)
return -ENOMEM;
return 0;
}
/* Cleanup the proc fs entry for 'snmp' object. */
void sctp_snmp_proc_exit(void)
{
remove_proc_entry("snmp", proc_net_sctp);
}
/* Dump local addresses of an association/endpoint. */
static void sctp_seq_dump_local_addrs(struct seq_file *seq, struct sctp_ep_common *epb)
{
struct sctp_association *asoc;
struct sctp_sockaddr_entry *laddr;
struct sctp_transport *peer;
union sctp_addr *addr, *primary = NULL;
struct sctp_af *af;
if (epb->type == SCTP_EP_TYPE_ASSOCIATION) {
asoc = sctp_assoc(epb);
peer = asoc->peer.primary_path;
primary = &peer->saddr;
}
list_for_each_entry(laddr, &epb->bind_addr.address_list, list) {
addr = &laddr->a;
af = sctp_get_af_specific(addr->sa.sa_family);
if (primary && af->cmp_addr(addr, primary)) {
seq_printf(seq, "*");
}
af->seq_dump_addr(seq, addr);
}
}
/* Dump remote addresses of an association. */
static void sctp_seq_dump_remote_addrs(struct seq_file *seq, struct sctp_association *assoc)
{
struct sctp_transport *transport;
union sctp_addr *addr, *primary;
struct sctp_af *af;
primary = &assoc->peer.primary_addr;
list_for_each_entry(transport, &assoc->peer.transport_addr_list,
transports) {
addr = &transport->ipaddr;
af = sctp_get_af_specific(addr->sa.sa_family);
if (af->cmp_addr(addr, primary)) {
seq_printf(seq, "*");
}
af->seq_dump_addr(seq, addr);
}
}
static void * sctp_eps_seq_start(struct seq_file *seq, loff_t *pos)
{
if (*pos >= sctp_ep_hashsize)
return NULL;
if (*pos < 0)
*pos = 0;
if (*pos == 0)
seq_printf(seq, " ENDPT SOCK STY SST HBKT LPORT UID INODE LADDRS\n");
return (void *)pos;
}
static void sctp_eps_seq_stop(struct seq_file *seq, void *v)
{
}
static void * sctp_eps_seq_next(struct seq_file *seq, void *v, loff_t *pos)
{
if (++*pos >= sctp_ep_hashsize)
return NULL;
return pos;
}
/* Display sctp endpoints (/proc/net/sctp/eps). */
static int sctp_eps_seq_show(struct seq_file *seq, void *v)
{
struct sctp_hashbucket *head;
struct sctp_ep_common *epb;
struct sctp_endpoint *ep;
struct sock *sk;
struct hlist_node *node;
int hash = *(loff_t *)v;
if (hash >= sctp_ep_hashsize)
return -ENOMEM;
head = &sctp_ep_hashtable[hash];
sctp_local_bh_disable();
read_lock(&head->lock);
sctp_for_each_hentry(epb, node, &head->chain) {
ep = sctp_ep(epb);
sk = epb->sk;
seq_printf(seq, "%8p %8p %-3d %-3d %-4d %-5d %5d %5lu ", ep, sk,
sctp_sk(sk)->type, sk->sk_state, hash,
epb->bind_addr.port,
sock_i_uid(sk), sock_i_ino(sk));
sctp_seq_dump_local_addrs(seq, epb);
seq_printf(seq, "\n");
}
read_unlock(&head->lock);
sctp_local_bh_enable();
return 0;
}
static const struct seq_operations sctp_eps_ops = {
.start = sctp_eps_seq_start,
.next = sctp_eps_seq_next,
.stop = sctp_eps_seq_stop,
.show = sctp_eps_seq_show,
};
/* Initialize the seq file operations for 'eps' object. */
static int sctp_eps_seq_open(struct inode *inode, struct file *file)
{
return seq_open(file, &sctp_eps_ops);
}
static const struct file_operations sctp_eps_seq_fops = {
.open = sctp_eps_seq_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
/* Set up the proc fs entry for 'eps' object. */
int __init sctp_eps_proc_init(void)
{
struct proc_dir_entry *p;
p = proc_create("eps", S_IRUGO, proc_net_sctp, &sctp_eps_seq_fops);
if (!p)
return -ENOMEM;
return 0;
}
/* Cleanup the proc fs entry for 'eps' object. */
void sctp_eps_proc_exit(void)
{
remove_proc_entry("eps", proc_net_sctp);
}
static void * sctp_assocs_seq_start(struct seq_file *seq, loff_t *pos)
{
if (*pos >= sctp_assoc_hashsize)
return NULL;
if (*pos < 0)
*pos = 0;
if (*pos == 0)
seq_printf(seq, " ASSOC SOCK STY SST ST HBKT "
"ASSOC-ID TX_QUEUE RX_QUEUE UID INODE LPORT "
"RPORT LADDRS <-> RADDRS "
"HBINT INS OUTS MAXRT T1X T2X RTXC\n");
return (void *)pos;
}
static void sctp_assocs_seq_stop(struct seq_file *seq, void *v)
{
}
static void * sctp_assocs_seq_next(struct seq_file *seq, void *v, loff_t *pos)
{
if (++*pos >= sctp_assoc_hashsize)
return NULL;
return pos;
}
/* Display sctp associations (/proc/net/sctp/assocs). */
static int sctp_assocs_seq_show(struct seq_file *seq, void *v)
{
struct sctp_hashbucket *head;
struct sctp_ep_common *epb;
struct sctp_association *assoc;
struct sock *sk;
struct hlist_node *node;
int hash = *(loff_t *)v;
if (hash >= sctp_assoc_hashsize)
return -ENOMEM;
head = &sctp_assoc_hashtable[hash];
sctp_local_bh_disable();
read_lock(&head->lock);
sctp_for_each_hentry(epb, node, &head->chain) {
assoc = sctp_assoc(epb);
sk = epb->sk;
seq_printf(seq,
"%8p %8p %-3d %-3d %-2d %-4d "
"%4d %8d %8d %7d %5lu %-5d %5d ",
assoc, sk, sctp_sk(sk)->type, sk->sk_state,
assoc->state, hash,
assoc->assoc_id,
assoc->sndbuf_used,
atomic_read(&assoc->rmem_alloc),
sock_i_uid(sk), sock_i_ino(sk),
epb->bind_addr.port,
assoc->peer.port);
seq_printf(seq, " ");
sctp_seq_dump_local_addrs(seq, epb);
seq_printf(seq, "<-> ");
sctp_seq_dump_remote_addrs(seq, assoc);
seq_printf(seq, "\t%8lu %5d %5d %4d %4d %4d %8d ",
assoc->hbinterval, assoc->c.sinit_max_instreams,
assoc->c.sinit_num_ostreams, assoc->max_retrans,
assoc->init_retries, assoc->shutdown_retries,
assoc->rtx_data_chunks);
seq_printf(seq, "\n");
}
read_unlock(&head->lock);
sctp_local_bh_enable();
return 0;
}
static const struct seq_operations sctp_assoc_ops = {
.start = sctp_assocs_seq_start,
.next = sctp_assocs_seq_next,
.stop = sctp_assocs_seq_stop,
.show = sctp_assocs_seq_show,
};
/* Initialize the seq file operations for 'assocs' object. */
static int sctp_assocs_seq_open(struct inode *inode, struct file *file)
{
return seq_open(file, &sctp_assoc_ops);
}
static const struct file_operations sctp_assocs_seq_fops = {
.open = sctp_assocs_seq_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
/* Set up the proc fs entry for 'assocs' object. */
int __init sctp_assocs_proc_init(void)
{
struct proc_dir_entry *p;
p = proc_create("assocs", S_IRUGO, proc_net_sctp,
&sctp_assocs_seq_fops);
if (!p)
return -ENOMEM;
return 0;
}
/* Cleanup the proc fs entry for 'assocs' object. */
void sctp_assocs_proc_exit(void)
{
remove_proc_entry("assocs", proc_net_sctp);
}
static void *sctp_remaddr_seq_start(struct seq_file *seq, loff_t *pos)
{
if (*pos >= sctp_assoc_hashsize)
return NULL;
if (*pos < 0)
*pos = 0;
if (*pos == 0)
seq_printf(seq, "ADDR ASSOC_ID HB_ACT RTO MAX_PATH_RTX "
"REM_ADDR_RTX START\n");
return (void *)pos;
}
static void *sctp_remaddr_seq_next(struct seq_file *seq, void *v, loff_t *pos)
{
if (++*pos >= sctp_assoc_hashsize)
return NULL;
return pos;
}
static void sctp_remaddr_seq_stop(struct seq_file *seq, void *v)
{
}
static int sctp_remaddr_seq_show(struct seq_file *seq, void *v)
{
struct sctp_hashbucket *head;
struct sctp_ep_common *epb;
struct sctp_association *assoc;
struct hlist_node *node;
struct sctp_transport *tsp;
int hash = *(loff_t *)v;
if (hash >= sctp_assoc_hashsize)
return -ENOMEM;
head = &sctp_assoc_hashtable[hash];
sctp_local_bh_disable();
read_lock(&head->lock);
sctp_for_each_hentry(epb, node, &head->chain) {
assoc = sctp_assoc(epb);
list_for_each_entry(tsp, &assoc->peer.transport_addr_list,
transports) {
/*
* The remote address (ADDR)
*/
tsp->af_specific->seq_dump_addr(seq, &tsp->ipaddr);
seq_printf(seq, " ");
/*
* The association ID (ASSOC_ID)
*/
seq_printf(seq, "%d ", tsp->asoc->assoc_id);
/*
* If the Heartbeat is active (HB_ACT)
* Note: 1 = Active, 0 = Inactive
*/
seq_printf(seq, "%d ", timer_pending(&tsp->hb_timer));
/*
* Retransmit time out (RTO)
*/
seq_printf(seq, "%lu ", tsp->rto);
/*
* Maximum path retransmit count (PATH_MAX_RTX)
*/
seq_printf(seq, "%d ", tsp->pathmaxrxt);
/*
* remote address retransmit count (REM_ADDR_RTX)
* Note: We don't have a way to tally this at the moment
* so lets just leave it as zero for the moment
*/
seq_printf(seq, "0 ");
/*
* remote address start time (START). This is also not
* currently implemented, but we can record it with a
* jiffies marker in a subsequent patch
*/
seq_printf(seq, "0");
seq_printf(seq, "\n");
}
}
read_unlock(&head->lock);
sctp_local_bh_enable();
return 0;
}
static const struct seq_operations sctp_remaddr_ops = {
.start = sctp_remaddr_seq_start,
.next = sctp_remaddr_seq_next,
.stop = sctp_remaddr_seq_stop,
.show = sctp_remaddr_seq_show,
};
/* Cleanup the proc fs entry for 'remaddr' object. */
void sctp_remaddr_proc_exit(void)
{
remove_proc_entry("remaddr", proc_net_sctp);
}
static int sctp_remaddr_seq_open(struct inode *inode, struct file *file)
{
return seq_open(file, &sctp_remaddr_ops);
}
static const struct file_operations sctp_remaddr_seq_fops = {
.open = sctp_remaddr_seq_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
int __init sctp_remaddr_proc_init(void)
{
struct proc_dir_entry *p;
p = proc_create("remaddr", S_IRUGO, proc_net_sctp, &sctp_remaddr_seq_fops);
if (!p)
return -ENOMEM;
return 0;
}
| gpl-2.0 |
dzo/kernel_ville | arch/mips/alchemy/devboards/pb1550/board_setup.c | 2737 | 2881 | /*
*
* BRIEF MODULE DESCRIPTION
* Alchemy Pb1550 board setup.
*
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1550.h>
#include <asm/mach-db1x00/bcsr.h>
#include <asm/mach-au1x00/gpio.h>
#include <prom.h>
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
};
const char *get_system_type(void)
{
return "Alchemy Pb1550";
}
void __init board_setup(void)
{
u32 pin_func;
bcsr_init(PB1550_BCSR_PHYS_ADDR,
PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
alchemy_gpio2_enable();
/*
* Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
* but it is board specific code, so put it here.
*/
pin_func = au_readl(SYS_PINFUNC);
au_sync();
pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
au_writel(pin_func, SYS_PINFUNC);
bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
}
static int __init pb1550_init_irq(void)
{
irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
/* enable both PCMCIA card irqs in the shared line */
alchemy_gpio2_enable_int(201);
alchemy_gpio2_enable_int(202);
return 0;
}
arch_initcall(pb1550_init_irq);
| gpl-2.0 |
dennes544/aosp_kernel_lge_hammerhead_dennes544 | arch/x86/platform/uv/tlb_uv.c | 2737 | 56946 | /*
* SGI UltraViolet TLB flush routines.
*
* (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI.
*
* This code is released under the GNU General Public License version 2 or
* later.
*/
#include <linux/seq_file.h>
#include <linux/proc_fs.h>
#include <linux/debugfs.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <asm/mmu_context.h>
#include <asm/uv/uv.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/uv_bau.h>
#include <asm/apic.h>
#include <asm/idle.h>
#include <asm/tsc.h>
#include <asm/irq_vectors.h>
#include <asm/timer.h>
/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
static int timeout_base_ns[] = {
20,
160,
1280,
10240,
81920,
655360,
5242880,
167772160
};
static int timeout_us;
static int nobau;
static int baudisabled;
static spinlock_t disable_lock;
static cycles_t congested_cycles;
/* tunables: */
static int max_concurr = MAX_BAU_CONCURRENT;
static int max_concurr_const = MAX_BAU_CONCURRENT;
static int plugged_delay = PLUGGED_DELAY;
static int plugsb4reset = PLUGSB4RESET;
static int timeoutsb4reset = TIMEOUTSB4RESET;
static int ipi_reset_limit = IPI_RESET_LIMIT;
static int complete_threshold = COMPLETE_THRESHOLD;
static int congested_respns_us = CONGESTED_RESPONSE_US;
static int congested_reps = CONGESTED_REPS;
static int congested_period = CONGESTED_PERIOD;
static struct tunables tunables[] = {
{&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
{&plugged_delay, PLUGGED_DELAY},
{&plugsb4reset, PLUGSB4RESET},
{&timeoutsb4reset, TIMEOUTSB4RESET},
{&ipi_reset_limit, IPI_RESET_LIMIT},
{&complete_threshold, COMPLETE_THRESHOLD},
{&congested_respns_us, CONGESTED_RESPONSE_US},
{&congested_reps, CONGESTED_REPS},
{&congested_period, CONGESTED_PERIOD}
};
static struct dentry *tunables_dir;
static struct dentry *tunables_file;
/* these correspond to the statistics printed by ptc_seq_show() */
static char *stat_description[] = {
"sent: number of shootdown messages sent",
"stime: time spent sending messages",
"numuvhubs: number of hubs targeted with shootdown",
"numuvhubs16: number times 16 or more hubs targeted",
"numuvhubs8: number times 8 or more hubs targeted",
"numuvhubs4: number times 4 or more hubs targeted",
"numuvhubs2: number times 2 or more hubs targeted",
"numuvhubs1: number times 1 hub targeted",
"numcpus: number of cpus targeted with shootdown",
"dto: number of destination timeouts",
"retries: destination timeout retries sent",
"rok: : destination timeouts successfully retried",
"resetp: ipi-style resource resets for plugs",
"resett: ipi-style resource resets for timeouts",
"giveup: fall-backs to ipi-style shootdowns",
"sto: number of source timeouts",
"bz: number of stay-busy's",
"throt: number times spun in throttle",
"swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
"recv: shootdown messages received",
"rtime: time spent processing messages",
"all: shootdown all-tlb messages",
"one: shootdown one-tlb messages",
"mult: interrupts that found multiple messages",
"none: interrupts that found no messages",
"retry: number of retry messages processed",
"canc: number messages canceled by retries",
"nocan: number retries that found nothing to cancel",
"reset: number of ipi-style reset requests processed",
"rcan: number messages canceled by reset requests",
"disable: number times use of the BAU was disabled",
"enable: number times use of the BAU was re-enabled"
};
static int __init
setup_nobau(char *arg)
{
nobau = 1;
return 0;
}
early_param("nobau", setup_nobau);
/* base pnode in this partition */
static int uv_base_pnode __read_mostly;
static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
static DEFINE_PER_CPU(struct bau_control, bau_control);
static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
/*
* Determine the first node on a uvhub. 'Nodes' are used for kernel
* memory allocation.
*/
static int __init uvhub_to_first_node(int uvhub)
{
int node, b;
for_each_online_node(node) {
b = uv_node_to_blade_id(node);
if (uvhub == b)
return node;
}
return -1;
}
/*
* Determine the apicid of the first cpu on a uvhub.
*/
static int __init uvhub_to_first_apicid(int uvhub)
{
int cpu;
for_each_present_cpu(cpu)
if (uvhub == uv_cpu_to_blade_id(cpu))
return per_cpu(x86_cpu_to_apicid, cpu);
return -1;
}
/*
* Free a software acknowledge hardware resource by clearing its Pending
* bit. This will return a reply to the sender.
* If the message has timed out, a reply has already been sent by the
* hardware but the resource has not been released. In that case our
* clear of the Timeout bit (as well) will free the resource. No reply will
* be sent (the hardware will only do one reply per message).
*/
static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
int do_acknowledge)
{
unsigned long dw;
struct bau_pq_entry *msg;
msg = mdp->msg;
if (!msg->canceled && do_acknowledge) {
dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
write_mmr_sw_ack(dw);
}
msg->replied_to = 1;
msg->swack_vec = 0;
}
/*
* Process the receipt of a RETRY message
*/
static void bau_process_retry_msg(struct msg_desc *mdp,
struct bau_control *bcp)
{
int i;
int cancel_count = 0;
unsigned long msg_res;
unsigned long mmr = 0;
struct bau_pq_entry *msg = mdp->msg;
struct bau_pq_entry *msg2;
struct ptc_stats *stat = bcp->statp;
stat->d_retries++;
/*
* cancel any message from msg+1 to the retry itself
*/
for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
if (msg2 > mdp->queue_last)
msg2 = mdp->queue_first;
if (msg2 == msg)
break;
/* same conditions for cancellation as do_reset */
if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
(msg2->swack_vec) && ((msg2->swack_vec &
msg->swack_vec) == 0) &&
(msg2->sending_cpu == msg->sending_cpu) &&
(msg2->msg_type != MSG_NOOP)) {
mmr = read_mmr_sw_ack();
msg_res = msg2->swack_vec;
/*
* This is a message retry; clear the resources held
* by the previous message only if they timed out.
* If it has not timed out we have an unexpected
* situation to report.
*/
if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
unsigned long mr;
/*
* Is the resource timed out?
* Make everyone ignore the cancelled message.
*/
msg2->canceled = 1;
stat->d_canceled++;
cancel_count++;
mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
write_mmr_sw_ack(mr);
}
}
}
if (!cancel_count)
stat->d_nocanceled++;
}
/*
* Do all the things a cpu should do for a TLB shootdown message.
* Other cpu's may come here at the same time for this message.
*/
static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
int do_acknowledge)
{
short socket_ack_count = 0;
short *sp;
struct atomic_short *asp;
struct ptc_stats *stat = bcp->statp;
struct bau_pq_entry *msg = mdp->msg;
struct bau_control *smaster = bcp->socket_master;
/*
* This must be a normal message, or retry of a normal message
*/
if (msg->address == TLB_FLUSH_ALL) {
local_flush_tlb();
stat->d_alltlb++;
} else {
__flush_tlb_one(msg->address);
stat->d_onetlb++;
}
stat->d_requestee++;
/*
* One cpu on each uvhub has the additional job on a RETRY
* of releasing the resource held by the message that is
* being retried. That message is identified by sending
* cpu number.
*/
if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
bau_process_retry_msg(mdp, bcp);
/*
* This is a swack message, so we have to reply to it.
* Count each responding cpu on the socket. This avoids
* pinging the count's cache line back and forth between
* the sockets.
*/
sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
asp = (struct atomic_short *)sp;
socket_ack_count = atom_asr(1, asp);
if (socket_ack_count == bcp->cpus_in_socket) {
int msg_ack_count;
/*
* Both sockets dump their completed count total into
* the message's count.
*/
smaster->socket_acknowledge_count[mdp->msg_slot] = 0;
asp = (struct atomic_short *)&msg->acknowledge_count;
msg_ack_count = atom_asr(socket_ack_count, asp);
if (msg_ack_count == bcp->cpus_in_uvhub) {
/*
* All cpus in uvhub saw it; reply
* (unless we are in the UV2 workaround)
*/
reply_to_message(mdp, bcp, do_acknowledge);
}
}
return;
}
/*
* Determine the first cpu on a pnode.
*/
static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
{
int cpu;
struct hub_and_pnode *hpp;
for_each_present_cpu(cpu) {
hpp = &smaster->thp[cpu];
if (pnode == hpp->pnode)
return cpu;
}
return -1;
}
/*
* Last resort when we get a large number of destination timeouts is
* to clear resources held by a given cpu.
* Do this with IPI so that all messages in the BAU message queue
* can be identified by their nonzero swack_vec field.
*
* This is entered for a single cpu on the uvhub.
* The sender want's this uvhub to free a specific message's
* swack resources.
*/
static void do_reset(void *ptr)
{
int i;
struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
struct reset_args *rap = (struct reset_args *)ptr;
struct bau_pq_entry *msg;
struct ptc_stats *stat = bcp->statp;
stat->d_resets++;
/*
* We're looking for the given sender, and
* will free its swack resource.
* If all cpu's finally responded after the timeout, its
* message 'replied_to' was set.
*/
for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
unsigned long msg_res;
/* do_reset: same conditions for cancellation as
bau_process_retry_msg() */
if ((msg->replied_to == 0) &&
(msg->canceled == 0) &&
(msg->sending_cpu == rap->sender) &&
(msg->swack_vec) &&
(msg->msg_type != MSG_NOOP)) {
unsigned long mmr;
unsigned long mr;
/*
* make everyone else ignore this message
*/
msg->canceled = 1;
/*
* only reset the resource if it is still pending
*/
mmr = read_mmr_sw_ack();
msg_res = msg->swack_vec;
mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
if (mmr & msg_res) {
stat->d_rcanceled++;
write_mmr_sw_ack(mr);
}
}
}
return;
}
/*
* Use IPI to get all target uvhubs to release resources held by
* a given sending cpu number.
*/
static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
{
int pnode;
int apnode;
int maskbits;
int sender = bcp->cpu;
cpumask_t *mask = bcp->uvhub_master->cpumask;
struct bau_control *smaster = bcp->socket_master;
struct reset_args reset_args;
reset_args.sender = sender;
cpus_clear(*mask);
/* find a single cpu for each uvhub in this distribution mask */
maskbits = sizeof(struct pnmask) * BITSPERBYTE;
/* each bit is a pnode relative to the partition base pnode */
for (pnode = 0; pnode < maskbits; pnode++) {
int cpu;
if (!bau_uvhub_isset(pnode, distribution))
continue;
apnode = pnode + bcp->partition_base_pnode;
cpu = pnode_to_first_cpu(apnode, smaster);
cpu_set(cpu, *mask);
}
/* IPI all cpus; preemption is already disabled */
smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
return;
}
static inline unsigned long cycles_2_us(unsigned long long cyc)
{
unsigned long long ns;
unsigned long us;
int cpu = smp_processor_id();
ns = (cyc * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR;
us = ns / 1000;
return us;
}
/*
* wait for all cpus on this hub to finish their sends and go quiet
* leaves uvhub_quiesce set so that no new broadcasts are started by
* bau_flush_send_and_wait()
*/
static inline void quiesce_local_uvhub(struct bau_control *hmaster)
{
atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
}
/*
* mark this quiet-requestor as done
*/
static inline void end_uvhub_quiesce(struct bau_control *hmaster)
{
atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
}
static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
{
unsigned long descriptor_status;
descriptor_status = uv_read_local_mmr(mmr_offset);
descriptor_status >>= right_shift;
descriptor_status &= UV_ACT_STATUS_MASK;
return descriptor_status;
}
/*
* Wait for completion of a broadcast software ack message
* return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
*/
static int uv1_wait_completion(struct bau_desc *bau_desc,
unsigned long mmr_offset, int right_shift,
struct bau_control *bcp, long try)
{
unsigned long descriptor_status;
cycles_t ttm;
struct ptc_stats *stat = bcp->statp;
descriptor_status = uv1_read_status(mmr_offset, right_shift);
/* spin on the status MMR, waiting for it to go idle */
while ((descriptor_status != DS_IDLE)) {
/*
* Our software ack messages may be blocked because
* there are no swack resources available. As long
* as none of them has timed out hardware will NACK
* our message and its state will stay IDLE.
*/
if (descriptor_status == DS_SOURCE_TIMEOUT) {
stat->s_stimeout++;
return FLUSH_GIVEUP;
} else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
stat->s_dtimeout++;
ttm = get_cycles();
/*
* Our retries may be blocked by all destination
* swack resources being consumed, and a timeout
* pending. In that case hardware returns the
* ERROR that looks like a destination timeout.
*/
if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
bcp->conseccompletes = 0;
return FLUSH_RETRY_PLUGGED;
}
bcp->conseccompletes = 0;
return FLUSH_RETRY_TIMEOUT;
} else {
/*
* descriptor_status is still BUSY
*/
cpu_relax();
}
descriptor_status = uv1_read_status(mmr_offset, right_shift);
}
bcp->conseccompletes++;
return FLUSH_COMPLETE;
}
/*
* UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register.
*/
static unsigned long uv2_read_status(unsigned long offset, int rshft, int desc)
{
unsigned long descriptor_status;
unsigned long descriptor_status2;
descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK);
descriptor_status2 = (read_mmr_uv2_status() >> desc) & 0x1UL;
descriptor_status = (descriptor_status << 1) | descriptor_status2;
return descriptor_status;
}
/*
* Return whether the status of the descriptor that is normally used for this
* cpu (the one indexed by its hub-relative cpu number) is busy.
* The status of the original 32 descriptors is always reflected in the 64
* bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0.
* The bit provided by the activation_status_2 register is irrelevant to
* the status if it is only being tested for busy or not busy.
*/
int normal_busy(struct bau_control *bcp)
{
int cpu = bcp->uvhub_cpu;
int mmr_offset;
int right_shift;
mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
right_shift = cpu * UV_ACT_STATUS_SIZE;
return (((((read_lmmr(mmr_offset) >> right_shift) &
UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY);
}
/*
* Entered when a bau descriptor has gone into a permanent busy wait because
* of a hardware bug.
* Workaround the bug.
*/
int handle_uv2_busy(struct bau_control *bcp)
{
int busy_one = bcp->using_desc;
int normal = bcp->uvhub_cpu;
int selected = -1;
int i;
unsigned long descriptor_status;
unsigned long status;
int mmr_offset;
struct bau_desc *bau_desc_old;
struct bau_desc *bau_desc_new;
struct bau_control *hmaster = bcp->uvhub_master;
struct ptc_stats *stat = bcp->statp;
cycles_t ttm;
stat->s_uv2_wars++;
spin_lock(&hmaster->uvhub_lock);
/* try for the original first */
if (busy_one != normal) {
if (!normal_busy(bcp))
selected = normal;
}
if (selected < 0) {
/* can't use the normal, select an alternate */
mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
descriptor_status = read_lmmr(mmr_offset);
/* scan available descriptors 32-63 */
for (i = 0; i < UV_CPUS_PER_AS; i++) {
if ((hmaster->inuse_map & (1 << i)) == 0) {
status = ((descriptor_status >>
(i * UV_ACT_STATUS_SIZE)) &
UV_ACT_STATUS_MASK) << 1;
if (status != UV2H_DESC_BUSY) {
selected = i + UV_CPUS_PER_AS;
break;
}
}
}
}
if (busy_one != normal)
/* mark the busy alternate as not in-use */
hmaster->inuse_map &= ~(1 << (busy_one - UV_CPUS_PER_AS));
if (selected >= 0) {
/* switch to the selected descriptor */
if (selected != normal) {
/* set the selected alternate as in-use */
hmaster->inuse_map |=
(1 << (selected - UV_CPUS_PER_AS));
if (selected > stat->s_uv2_wars_hw)
stat->s_uv2_wars_hw = selected;
}
bau_desc_old = bcp->descriptor_base;
bau_desc_old += (ITEMS_PER_DESC * busy_one);
bcp->using_desc = selected;
bau_desc_new = bcp->descriptor_base;
bau_desc_new += (ITEMS_PER_DESC * selected);
*bau_desc_new = *bau_desc_old;
} else {
/*
* All are busy. Wait for the normal one for this cpu to
* free up.
*/
stat->s_uv2_war_waits++;
spin_unlock(&hmaster->uvhub_lock);
ttm = get_cycles();
do {
cpu_relax();
} while (normal_busy(bcp));
spin_lock(&hmaster->uvhub_lock);
/* switch to the original descriptor */
bcp->using_desc = normal;
bau_desc_old = bcp->descriptor_base;
bau_desc_old += (ITEMS_PER_DESC * bcp->using_desc);
bcp->using_desc = (ITEMS_PER_DESC * normal);
bau_desc_new = bcp->descriptor_base;
bau_desc_new += (ITEMS_PER_DESC * normal);
*bau_desc_new = *bau_desc_old; /* copy the entire descriptor */
}
spin_unlock(&hmaster->uvhub_lock);
return FLUSH_RETRY_BUSYBUG;
}
static int uv2_wait_completion(struct bau_desc *bau_desc,
unsigned long mmr_offset, int right_shift,
struct bau_control *bcp, long try)
{
unsigned long descriptor_stat;
cycles_t ttm;
int desc = bcp->using_desc;
long busy_reps = 0;
struct ptc_stats *stat = bcp->statp;
descriptor_stat = uv2_read_status(mmr_offset, right_shift, desc);
/* spin on the status MMR, waiting for it to go idle */
while (descriptor_stat != UV2H_DESC_IDLE) {
/*
* Our software ack messages may be blocked because
* there are no swack resources available. As long
* as none of them has timed out hardware will NACK
* our message and its state will stay IDLE.
*/
if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) ||
(descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) {
stat->s_stimeout++;
return FLUSH_GIVEUP;
} else if (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) {
stat->s_strongnacks++;
bcp->conseccompletes = 0;
return FLUSH_GIVEUP;
} else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
stat->s_dtimeout++;
bcp->conseccompletes = 0;
return FLUSH_RETRY_TIMEOUT;
} else {
busy_reps++;
if (busy_reps > 1000000) {
/* not to hammer on the clock */
busy_reps = 0;
ttm = get_cycles();
if ((ttm - bcp->send_message) >
(bcp->clocks_per_100_usec)) {
return handle_uv2_busy(bcp);
}
}
/*
* descriptor_stat is still BUSY
*/
cpu_relax();
}
descriptor_stat = uv2_read_status(mmr_offset, right_shift,
desc);
}
bcp->conseccompletes++;
return FLUSH_COMPLETE;
}
/*
* There are 2 status registers; each and array[32] of 2 bits. Set up for
* which register to read and position in that register based on cpu in
* current hub.
*/
static int wait_completion(struct bau_desc *bau_desc,
struct bau_control *bcp, long try)
{
int right_shift;
unsigned long mmr_offset;
int desc = bcp->using_desc;
if (desc < UV_CPUS_PER_AS) {
mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
right_shift = desc * UV_ACT_STATUS_SIZE;
} else {
mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
}
if (bcp->uvhub_version == 1)
return uv1_wait_completion(bau_desc, mmr_offset, right_shift,
bcp, try);
else
return uv2_wait_completion(bau_desc, mmr_offset, right_shift,
bcp, try);
}
static inline cycles_t sec_2_cycles(unsigned long sec)
{
unsigned long ns;
cycles_t cyc;
ns = sec * 1000000000;
cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
return cyc;
}
/*
* Our retries are blocked by all destination sw ack resources being
* in use, and a timeout is pending. In that case hardware immediately
* returns the ERROR that looks like a destination timeout.
*/
static void destination_plugged(struct bau_desc *bau_desc,
struct bau_control *bcp,
struct bau_control *hmaster, struct ptc_stats *stat)
{
udelay(bcp->plugged_delay);
bcp->plugged_tries++;
if (bcp->plugged_tries >= bcp->plugsb4reset) {
bcp->plugged_tries = 0;
quiesce_local_uvhub(hmaster);
spin_lock(&hmaster->queue_lock);
reset_with_ipi(&bau_desc->distribution, bcp);
spin_unlock(&hmaster->queue_lock);
end_uvhub_quiesce(hmaster);
bcp->ipi_attempts++;
stat->s_resets_plug++;
}
}
static void destination_timeout(struct bau_desc *bau_desc,
struct bau_control *bcp, struct bau_control *hmaster,
struct ptc_stats *stat)
{
hmaster->max_concurr = 1;
bcp->timeout_tries++;
if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
bcp->timeout_tries = 0;
quiesce_local_uvhub(hmaster);
spin_lock(&hmaster->queue_lock);
reset_with_ipi(&bau_desc->distribution, bcp);
spin_unlock(&hmaster->queue_lock);
end_uvhub_quiesce(hmaster);
bcp->ipi_attempts++;
stat->s_resets_timeout++;
}
}
/*
* Completions are taking a very long time due to a congested numalink
* network.
*/
static void disable_for_congestion(struct bau_control *bcp,
struct ptc_stats *stat)
{
/* let only one cpu do this disabling */
spin_lock(&disable_lock);
if (!baudisabled && bcp->period_requests &&
((bcp->period_time / bcp->period_requests) > congested_cycles)) {
int tcpu;
struct bau_control *tbcp;
/* it becomes this cpu's job to turn on the use of the
BAU again */
baudisabled = 1;
bcp->set_bau_off = 1;
bcp->set_bau_on_time = get_cycles();
bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period);
stat->s_bau_disabled++;
for_each_present_cpu(tcpu) {
tbcp = &per_cpu(bau_control, tcpu);
tbcp->baudisabled = 1;
}
}
spin_unlock(&disable_lock);
}
static void count_max_concurr(int stat, struct bau_control *bcp,
struct bau_control *hmaster)
{
bcp->plugged_tries = 0;
bcp->timeout_tries = 0;
if (stat != FLUSH_COMPLETE)
return;
if (bcp->conseccompletes <= bcp->complete_threshold)
return;
if (hmaster->max_concurr >= hmaster->max_concurr_const)
return;
hmaster->max_concurr++;
}
static void record_send_stats(cycles_t time1, cycles_t time2,
struct bau_control *bcp, struct ptc_stats *stat,
int completion_status, int try)
{
cycles_t elapsed;
if (time2 > time1) {
elapsed = time2 - time1;
stat->s_time += elapsed;
if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
bcp->period_requests++;
bcp->period_time += elapsed;
if ((elapsed > congested_cycles) &&
(bcp->period_requests > bcp->cong_reps))
disable_for_congestion(bcp, stat);
}
} else
stat->s_requestor--;
if (completion_status == FLUSH_COMPLETE && try > 1)
stat->s_retriesok++;
else if (completion_status == FLUSH_GIVEUP)
stat->s_giveup++;
}
/*
* Because of a uv1 hardware bug only a limited number of concurrent
* requests can be made.
*/
static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
{
spinlock_t *lock = &hmaster->uvhub_lock;
atomic_t *v;
v = &hmaster->active_descriptor_count;
if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
stat->s_throttles++;
do {
cpu_relax();
} while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
}
}
/*
* Handle the completion status of a message send.
*/
static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
struct bau_control *bcp, struct bau_control *hmaster,
struct ptc_stats *stat)
{
if (completion_status == FLUSH_RETRY_PLUGGED)
destination_plugged(bau_desc, bcp, hmaster, stat);
else if (completion_status == FLUSH_RETRY_TIMEOUT)
destination_timeout(bau_desc, bcp, hmaster, stat);
}
/*
* Send a broadcast and wait for it to complete.
*
* The flush_mask contains the cpus the broadcast is to be sent to including
* cpus that are on the local uvhub.
*
* Returns 0 if all flushing represented in the mask was done.
* Returns 1 if it gives up entirely and the original cpu mask is to be
* returned to the kernel.
*/
int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp)
{
int seq_number = 0;
int completion_stat = 0;
int uv1 = 0;
long try = 0;
unsigned long index;
cycles_t time1;
cycles_t time2;
struct ptc_stats *stat = bcp->statp;
struct bau_control *hmaster = bcp->uvhub_master;
struct uv1_bau_msg_header *uv1_hdr = NULL;
struct uv2_bau_msg_header *uv2_hdr = NULL;
struct bau_desc *bau_desc;
if (bcp->uvhub_version == 1)
uv1_throttle(hmaster, stat);
while (hmaster->uvhub_quiesce)
cpu_relax();
time1 = get_cycles();
do {
bau_desc = bcp->descriptor_base;
bau_desc += (ITEMS_PER_DESC * bcp->using_desc);
if (bcp->uvhub_version == 1) {
uv1 = 1;
uv1_hdr = &bau_desc->header.uv1_hdr;
} else
uv2_hdr = &bau_desc->header.uv2_hdr;
if ((try == 0) || (completion_stat == FLUSH_RETRY_BUSYBUG)) {
if (uv1)
uv1_hdr->msg_type = MSG_REGULAR;
else
uv2_hdr->msg_type = MSG_REGULAR;
seq_number = bcp->message_number++;
} else {
if (uv1)
uv1_hdr->msg_type = MSG_RETRY;
else
uv2_hdr->msg_type = MSG_RETRY;
stat->s_retry_messages++;
}
if (uv1)
uv1_hdr->sequence = seq_number;
else
uv2_hdr->sequence = seq_number;
index = (1UL << AS_PUSH_SHIFT) | bcp->using_desc;
bcp->send_message = get_cycles();
write_mmr_activation(index);
try++;
completion_stat = wait_completion(bau_desc, bcp, try);
/* UV2: wait_completion() may change the bcp->using_desc */
handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
bcp->ipi_attempts = 0;
completion_stat = FLUSH_GIVEUP;
break;
}
cpu_relax();
} while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
(completion_stat == FLUSH_RETRY_BUSYBUG) ||
(completion_stat == FLUSH_RETRY_TIMEOUT));
time2 = get_cycles();
count_max_concurr(completion_stat, bcp, hmaster);
while (hmaster->uvhub_quiesce)
cpu_relax();
atomic_dec(&hmaster->active_descriptor_count);
record_send_stats(time1, time2, bcp, stat, completion_stat, try);
if (completion_stat == FLUSH_GIVEUP)
/* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
return 1;
return 0;
}
/*
* The BAU is disabled. When the disabled time period has expired, the cpu
* that disabled it must re-enable it.
* Return 0 if it is re-enabled for all cpus.
*/
static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
{
int tcpu;
struct bau_control *tbcp;
if (bcp->set_bau_off) {
if (get_cycles() >= bcp->set_bau_on_time) {
stat->s_bau_reenabled++;
baudisabled = 0;
for_each_present_cpu(tcpu) {
tbcp = &per_cpu(bau_control, tcpu);
tbcp->baudisabled = 0;
tbcp->period_requests = 0;
tbcp->period_time = 0;
}
return 0;
}
}
return -1;
}
static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
int remotes, struct bau_desc *bau_desc)
{
stat->s_requestor++;
stat->s_ntargcpu += remotes + locals;
stat->s_ntargremotes += remotes;
stat->s_ntarglocals += locals;
/* uvhub statistics */
hubs = bau_uvhub_weight(&bau_desc->distribution);
if (locals) {
stat->s_ntarglocaluvhub++;
stat->s_ntargremoteuvhub += (hubs - 1);
} else
stat->s_ntargremoteuvhub += hubs;
stat->s_ntarguvhub += hubs;
if (hubs >= 16)
stat->s_ntarguvhub16++;
else if (hubs >= 8)
stat->s_ntarguvhub8++;
else if (hubs >= 4)
stat->s_ntarguvhub4++;
else if (hubs >= 2)
stat->s_ntarguvhub2++;
else
stat->s_ntarguvhub1++;
}
/*
* Translate a cpu mask to the uvhub distribution mask in the BAU
* activation descriptor.
*/
static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
struct bau_desc *bau_desc, int *localsp, int *remotesp)
{
int cpu;
int pnode;
int cnt = 0;
struct hub_and_pnode *hpp;
for_each_cpu(cpu, flush_mask) {
/*
* The distribution vector is a bit map of pnodes, relative
* to the partition base pnode (and the partition base nasid
* in the header).
* Translate cpu to pnode and hub using a local memory array.
*/
hpp = &bcp->socket_master->thp[cpu];
pnode = hpp->pnode - bcp->partition_base_pnode;
bau_uvhub_set(pnode, &bau_desc->distribution);
cnt++;
if (hpp->uvhub == bcp->uvhub)
(*localsp)++;
else
(*remotesp)++;
}
if (!cnt)
return 1;
return 0;
}
/*
* globally purge translation cache of a virtual address or all TLB's
* @cpumask: mask of all cpu's in which the address is to be removed
* @mm: mm_struct containing virtual address range
* @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
* @cpu: the current cpu
*
* This is the entry point for initiating any UV global TLB shootdown.
*
* Purges the translation caches of all specified processors of the given
* virtual address, or purges all TLB's on specified processors.
*
* The caller has derived the cpumask from the mm_struct. This function
* is called only if there are bits set in the mask. (e.g. flush_tlb_page())
*
* The cpumask is converted into a uvhubmask of the uvhubs containing
* those cpus.
*
* Note that this function should be called with preemption disabled.
*
* Returns NULL if all remote flushing was done.
* Returns pointer to cpumask if some remote flushing remains to be
* done. The returned pointer is valid till preemption is re-enabled.
*/
const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
struct mm_struct *mm, unsigned long va,
unsigned int cpu)
{
int locals = 0;
int remotes = 0;
int hubs = 0;
struct bau_desc *bau_desc;
struct cpumask *flush_mask;
struct ptc_stats *stat;
struct bau_control *bcp;
/* kernel was booted 'nobau' */
if (nobau)
return cpumask;
bcp = &per_cpu(bau_control, cpu);
stat = bcp->statp;
/* bau was disabled due to slow response */
if (bcp->baudisabled) {
if (check_enable(bcp, stat))
return cpumask;
}
/*
* Each sending cpu has a per-cpu mask which it fills from the caller's
* cpu mask. All cpus are converted to uvhubs and copied to the
* activation descriptor.
*/
flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
/* don't actually do a shootdown of the local cpu */
cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
if (cpu_isset(cpu, *cpumask))
stat->s_ntargself++;
bau_desc = bcp->descriptor_base;
bau_desc += (ITEMS_PER_DESC * bcp->using_desc);
bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
return NULL;
record_send_statistics(stat, locals, hubs, remotes, bau_desc);
bau_desc->payload.address = va;
bau_desc->payload.sending_cpu = cpu;
/*
* uv_flush_send_and_wait returns 0 if all cpu's were messaged,
* or 1 if it gave up and the original cpumask should be returned.
*/
if (!uv_flush_send_and_wait(flush_mask, bcp))
return NULL;
else
return cpumask;
}
/*
* Search the message queue for any 'other' message with the same software
* acknowledge resource bit vector.
*/
struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
struct bau_control *bcp, unsigned char swack_vec)
{
struct bau_pq_entry *msg_next = msg + 1;
if (msg_next > bcp->queue_last)
msg_next = bcp->queue_first;
while ((msg_next->swack_vec != 0) && (msg_next != msg)) {
if (msg_next->swack_vec == swack_vec)
return msg_next;
msg_next++;
if (msg_next > bcp->queue_last)
msg_next = bcp->queue_first;
}
return NULL;
}
/*
* UV2 needs to work around a bug in which an arriving message has not
* set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
* Such a message must be ignored.
*/
void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
{
unsigned long mmr_image;
unsigned char swack_vec;
struct bau_pq_entry *msg = mdp->msg;
struct bau_pq_entry *other_msg;
mmr_image = read_mmr_sw_ack();
swack_vec = msg->swack_vec;
if ((swack_vec & mmr_image) == 0) {
/*
* This message was assigned a swack resource, but no
* reserved acknowlegment is pending.
* The bug has prevented this message from setting the MMR.
* And no other message has used the same sw_ack resource.
* Do the requested shootdown but do not reply to the msg.
* (the 0 means make no acknowledge)
*/
bau_process_message(mdp, bcp, 0);
return;
}
/*
* Some message has set the MMR 'pending' bit; it might have been
* another message. Look for that message.
*/
other_msg = find_another_by_swack(msg, bcp, msg->swack_vec);
if (other_msg) {
/* There is another. Do not ack the current one. */
bau_process_message(mdp, bcp, 0);
/*
* Let the natural processing of that message acknowledge
* it. Don't get the processing of sw_ack's out of order.
*/
return;
}
/*
* There is no other message using this sw_ack, so it is safe to
* acknowledge it.
*/
bau_process_message(mdp, bcp, 1);
return;
}
/*
* The BAU message interrupt comes here. (registered by set_intr_gate)
* See entry_64.S
*
* We received a broadcast assist message.
*
* Interrupts are disabled; this interrupt could represent
* the receipt of several messages.
*
* All cores/threads on this hub get this interrupt.
* The last one to see it does the software ack.
* (the resource will not be freed until noninterruptable cpus see this
* interrupt; hardware may timeout the s/w ack and reply ERROR)
*/
void uv_bau_message_interrupt(struct pt_regs *regs)
{
int count = 0;
cycles_t time_start;
struct bau_pq_entry *msg;
struct bau_control *bcp;
struct ptc_stats *stat;
struct msg_desc msgdesc;
ack_APIC_irq();
time_start = get_cycles();
bcp = &per_cpu(bau_control, smp_processor_id());
stat = bcp->statp;
msgdesc.queue_first = bcp->queue_first;
msgdesc.queue_last = bcp->queue_last;
msg = bcp->bau_msg_head;
while (msg->swack_vec) {
count++;
msgdesc.msg_slot = msg - msgdesc.queue_first;
msgdesc.msg = msg;
if (bcp->uvhub_version == 2)
process_uv2_message(&msgdesc, bcp);
else
bau_process_message(&msgdesc, bcp, 1);
msg++;
if (msg > msgdesc.queue_last)
msg = msgdesc.queue_first;
bcp->bau_msg_head = msg;
}
stat->d_time += (get_cycles() - time_start);
if (!count)
stat->d_nomsg++;
else if (count > 1)
stat->d_multmsg++;
}
/*
* Each target uvhub (i.e. a uvhub that has cpu's) needs to have
* shootdown message timeouts enabled. The timeout does not cause
* an interrupt, but causes an error message to be returned to
* the sender.
*/
static void __init enable_timeouts(void)
{
int uvhub;
int nuvhubs;
int pnode;
unsigned long mmr_image;
nuvhubs = uv_num_possible_blades();
for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
if (!uv_blade_nr_possible_cpus(uvhub))
continue;
pnode = uv_blade_to_pnode(uvhub);
mmr_image = read_mmr_misc_control(pnode);
/*
* Set the timeout period and then lock it in, in three
* steps; captures and locks in the period.
*
* To program the period, the SOFT_ACK_MODE must be off.
*/
mmr_image &= ~(1L << SOFTACK_MSHIFT);
write_mmr_misc_control(pnode, mmr_image);
/*
* Set the 4-bit period.
*/
mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
write_mmr_misc_control(pnode, mmr_image);
/*
* UV1:
* Subsequent reversals of the timebase bit (3) cause an
* immediate timeout of one or all INTD resources as
* indicated in bits 2:0 (7 causes all of them to timeout).
*/
mmr_image |= (1L << SOFTACK_MSHIFT);
if (is_uv2_hub()) {
mmr_image &= ~(1L << UV2_LEG_SHFT);
mmr_image |= (1L << UV2_EXT_SHFT);
}
write_mmr_misc_control(pnode, mmr_image);
}
}
static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
{
if (*offset < num_possible_cpus())
return offset;
return NULL;
}
static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
{
(*offset)++;
if (*offset < num_possible_cpus())
return offset;
return NULL;
}
static void ptc_seq_stop(struct seq_file *file, void *data)
{
}
static inline unsigned long long usec_2_cycles(unsigned long microsec)
{
unsigned long ns;
unsigned long long cyc;
ns = microsec * 1000;
cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
return cyc;
}
/*
* Display the statistics thru /proc/sgi_uv/ptc_statistics
* 'data' points to the cpu number
* Note: see the descriptions in stat_description[].
*/
static int ptc_seq_show(struct seq_file *file, void *data)
{
struct ptc_stats *stat;
int cpu;
cpu = *(loff_t *)data;
if (!cpu) {
seq_printf(file,
"# cpu sent stime self locals remotes ncpus localhub ");
seq_printf(file,
"remotehub numuvhubs numuvhubs16 numuvhubs8 ");
seq_printf(file,
"numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries rok ");
seq_printf(file,
"resetp resett giveup sto bz throt swack recv rtime ");
seq_printf(file,
"all one mult none retry canc nocan reset rcan ");
seq_printf(file,
"disable enable wars warshw warwaits\n");
}
if (cpu < num_possible_cpus() && cpu_online(cpu)) {
stat = &per_cpu(ptcstats, cpu);
/* source side statistics */
seq_printf(file,
"cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
cpu, stat->s_requestor, cycles_2_us(stat->s_time),
stat->s_ntargself, stat->s_ntarglocals,
stat->s_ntargremotes, stat->s_ntargcpu,
stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
stat->s_ntarguvhub, stat->s_ntarguvhub16);
seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
stat->s_ntarguvhub8, stat->s_ntarguvhub4,
stat->s_ntarguvhub2, stat->s_ntarguvhub1,
stat->s_dtimeout, stat->s_strongnacks);
seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
stat->s_retry_messages, stat->s_retriesok,
stat->s_resets_plug, stat->s_resets_timeout,
stat->s_giveup, stat->s_stimeout,
stat->s_busy, stat->s_throttles);
/* destination side statistics */
seq_printf(file,
"%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
stat->d_requestee, cycles_2_us(stat->d_time),
stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
stat->d_nomsg, stat->d_retries, stat->d_canceled,
stat->d_nocanceled, stat->d_resets,
stat->d_rcanceled);
seq_printf(file, "%ld %ld %ld %ld %ld\n",
stat->s_bau_disabled, stat->s_bau_reenabled,
stat->s_uv2_wars, stat->s_uv2_wars_hw,
stat->s_uv2_war_waits);
}
return 0;
}
/*
* Display the tunables thru debugfs
*/
static ssize_t tunables_read(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char *buf;
int ret;
buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n",
"max_concur plugged_delay plugsb4reset",
"timeoutsb4reset ipi_reset_limit complete_threshold",
"congested_response_us congested_reps congested_period",
max_concurr, plugged_delay, plugsb4reset,
timeoutsb4reset, ipi_reset_limit, complete_threshold,
congested_respns_us, congested_reps, congested_period);
if (!buf)
return -ENOMEM;
ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
kfree(buf);
return ret;
}
/*
* handle a write to /proc/sgi_uv/ptc_statistics
* -1: reset the statistics
* 0: display meaning of the statistics
*/
static ssize_t ptc_proc_write(struct file *file, const char __user *user,
size_t count, loff_t *data)
{
int cpu;
int i;
int elements;
long input_arg;
char optstr[64];
struct ptc_stats *stat;
if (count == 0 || count > sizeof(optstr))
return -EINVAL;
if (copy_from_user(optstr, user, count))
return -EFAULT;
optstr[count - 1] = '\0';
if (strict_strtol(optstr, 10, &input_arg) < 0) {
printk(KERN_DEBUG "%s is invalid\n", optstr);
return -EINVAL;
}
if (input_arg == 0) {
elements = sizeof(stat_description)/sizeof(*stat_description);
printk(KERN_DEBUG "# cpu: cpu number\n");
printk(KERN_DEBUG "Sender statistics:\n");
for (i = 0; i < elements; i++)
printk(KERN_DEBUG "%s\n", stat_description[i]);
} else if (input_arg == -1) {
for_each_present_cpu(cpu) {
stat = &per_cpu(ptcstats, cpu);
memset(stat, 0, sizeof(struct ptc_stats));
}
}
return count;
}
static int local_atoi(const char *name)
{
int val = 0;
for (;; name++) {
switch (*name) {
case '0' ... '9':
val = 10*val+(*name-'0');
break;
default:
return val;
}
}
}
/*
* Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
* Zero values reset them to defaults.
*/
static int parse_tunables_write(struct bau_control *bcp, char *instr,
int count)
{
char *p;
char *q;
int cnt = 0;
int val;
int e = sizeof(tunables) / sizeof(*tunables);
p = instr + strspn(instr, WHITESPACE);
q = p;
for (; *p; p = q + strspn(q, WHITESPACE)) {
q = p + strcspn(p, WHITESPACE);
cnt++;
if (q == p)
break;
}
if (cnt != e) {
printk(KERN_INFO "bau tunable error: should be %d values\n", e);
return -EINVAL;
}
p = instr + strspn(instr, WHITESPACE);
q = p;
for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
q = p + strcspn(p, WHITESPACE);
val = local_atoi(p);
switch (cnt) {
case 0:
if (val == 0) {
max_concurr = MAX_BAU_CONCURRENT;
max_concurr_const = MAX_BAU_CONCURRENT;
continue;
}
if (val < 1 || val > bcp->cpus_in_uvhub) {
printk(KERN_DEBUG
"Error: BAU max concurrent %d is invalid\n",
val);
return -EINVAL;
}
max_concurr = val;
max_concurr_const = val;
continue;
default:
if (val == 0)
*tunables[cnt].tunp = tunables[cnt].deflt;
else
*tunables[cnt].tunp = val;
continue;
}
if (q == p)
break;
}
return 0;
}
/*
* Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
*/
static ssize_t tunables_write(struct file *file, const char __user *user,
size_t count, loff_t *data)
{
int cpu;
int ret;
char instr[100];
struct bau_control *bcp;
if (count == 0 || count > sizeof(instr)-1)
return -EINVAL;
if (copy_from_user(instr, user, count))
return -EFAULT;
instr[count] = '\0';
cpu = get_cpu();
bcp = &per_cpu(bau_control, cpu);
ret = parse_tunables_write(bcp, instr, count);
put_cpu();
if (ret)
return ret;
for_each_present_cpu(cpu) {
bcp = &per_cpu(bau_control, cpu);
bcp->max_concurr = max_concurr;
bcp->max_concurr_const = max_concurr;
bcp->plugged_delay = plugged_delay;
bcp->plugsb4reset = plugsb4reset;
bcp->timeoutsb4reset = timeoutsb4reset;
bcp->ipi_reset_limit = ipi_reset_limit;
bcp->complete_threshold = complete_threshold;
bcp->cong_response_us = congested_respns_us;
bcp->cong_reps = congested_reps;
bcp->cong_period = congested_period;
}
return count;
}
static const struct seq_operations uv_ptc_seq_ops = {
.start = ptc_seq_start,
.next = ptc_seq_next,
.stop = ptc_seq_stop,
.show = ptc_seq_show
};
static int ptc_proc_open(struct inode *inode, struct file *file)
{
return seq_open(file, &uv_ptc_seq_ops);
}
static int tunables_open(struct inode *inode, struct file *file)
{
return 0;
}
static const struct file_operations proc_uv_ptc_operations = {
.open = ptc_proc_open,
.read = seq_read,
.write = ptc_proc_write,
.llseek = seq_lseek,
.release = seq_release,
};
static const struct file_operations tunables_fops = {
.open = tunables_open,
.read = tunables_read,
.write = tunables_write,
.llseek = default_llseek,
};
static int __init uv_ptc_init(void)
{
struct proc_dir_entry *proc_uv_ptc;
if (!is_uv_system())
return 0;
proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
&proc_uv_ptc_operations);
if (!proc_uv_ptc) {
printk(KERN_ERR "unable to create %s proc entry\n",
UV_PTC_BASENAME);
return -EINVAL;
}
tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
if (!tunables_dir) {
printk(KERN_ERR "unable to create debugfs directory %s\n",
UV_BAU_TUNABLES_DIR);
return -EINVAL;
}
tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
tunables_dir, NULL, &tunables_fops);
if (!tunables_file) {
printk(KERN_ERR "unable to create debugfs file %s\n",
UV_BAU_TUNABLES_FILE);
return -EINVAL;
}
return 0;
}
/*
* Initialize the sending side's sending buffers.
*/
static void activation_descriptor_init(int node, int pnode, int base_pnode)
{
int i;
int cpu;
int uv1 = 0;
unsigned long gpa;
unsigned long m;
unsigned long n;
size_t dsize;
struct bau_desc *bau_desc;
struct bau_desc *bd2;
struct uv1_bau_msg_header *uv1_hdr;
struct uv2_bau_msg_header *uv2_hdr;
struct bau_control *bcp;
/*
* each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
* per cpu; and one per cpu on the uvhub (ADP_SZ)
*/
dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
BUG_ON(!bau_desc);
gpa = uv_gpa(bau_desc);
n = uv_gpa_to_gnode(gpa);
m = uv_gpa_to_offset(gpa);
if (is_uv1_hub())
uv1 = 1;
/* the 14-bit pnode */
write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
/*
* Initializing all 8 (ITEMS_PER_DESC) descriptors for each
* cpu even though we only use the first one; one descriptor can
* describe a broadcast to 256 uv hubs.
*/
for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
memset(bd2, 0, sizeof(struct bau_desc));
if (uv1) {
uv1_hdr = &bd2->header.uv1_hdr;
uv1_hdr->swack_flag = 1;
/*
* The base_dest_nasid set in the message header
* is the nasid of the first uvhub in the partition.
* The bit map will indicate destination pnode numbers
* relative to that base. They may not be consecutive
* if nasid striding is being used.
*/
uv1_hdr->base_dest_nasid =
UV_PNODE_TO_NASID(base_pnode);
uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
uv1_hdr->command = UV_NET_ENDPOINT_INTD;
uv1_hdr->int_both = 1;
/*
* all others need to be set to zero:
* fairness chaining multilevel count replied_to
*/
} else {
uv2_hdr = &bd2->header.uv2_hdr;
uv2_hdr->swack_flag = 1;
uv2_hdr->base_dest_nasid =
UV_PNODE_TO_NASID(base_pnode);
uv2_hdr->dest_subnodeid = UV_LB_SUBNODEID;
uv2_hdr->command = UV_NET_ENDPOINT_INTD;
}
}
for_each_present_cpu(cpu) {
if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
continue;
bcp = &per_cpu(bau_control, cpu);
bcp->descriptor_base = bau_desc;
}
}
/*
* initialize the destination side's receiving buffers
* entered for each uvhub in the partition
* - node is first node (kernel memory notion) on the uvhub
* - pnode is the uvhub's physical identifier
*/
static void pq_init(int node, int pnode)
{
int cpu;
size_t plsize;
char *cp;
void *vp;
unsigned long pn;
unsigned long first;
unsigned long pn_first;
unsigned long last;
struct bau_pq_entry *pqp;
struct bau_control *bcp;
plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
vp = kmalloc_node(plsize, GFP_KERNEL, node);
pqp = (struct bau_pq_entry *)vp;
BUG_ON(!pqp);
cp = (char *)pqp + 31;
pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
for_each_present_cpu(cpu) {
if (pnode != uv_cpu_to_pnode(cpu))
continue;
/* for every cpu on this pnode: */
bcp = &per_cpu(bau_control, cpu);
bcp->queue_first = pqp;
bcp->bau_msg_head = pqp;
bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
}
/*
* need the gnode of where the memory was really allocated
*/
pn = uv_gpa_to_gnode(uv_gpa(pqp));
first = uv_physnodeaddr(pqp);
pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first;
last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1));
write_mmr_payload_first(pnode, pn_first);
write_mmr_payload_tail(pnode, first);
write_mmr_payload_last(pnode, last);
write_gmmr_sw_ack(pnode, 0xffffUL);
/* in effect, all msg_type's are set to MSG_NOOP */
memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
}
/*
* Initialization of each UV hub's structures
*/
static void __init init_uvhub(int uvhub, int vector, int base_pnode)
{
int node;
int pnode;
unsigned long apicid;
node = uvhub_to_first_node(uvhub);
pnode = uv_blade_to_pnode(uvhub);
activation_descriptor_init(node, pnode, base_pnode);
pq_init(node, pnode);
/*
* The below initialization can't be in firmware because the
* messaging IRQ will be determined by the OS.
*/
apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
write_mmr_data_config(pnode, ((apicid << 32) | vector));
}
/*
* We will set BAU_MISC_CONTROL with a timeout period.
* But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
* So the destination timeout period has to be calculated from them.
*/
static int calculate_destination_timeout(void)
{
unsigned long mmr_image;
int mult1;
int mult2;
int index;
int base;
int ret;
unsigned long ts_ns;
if (is_uv1_hub()) {
mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
base = timeout_base_ns[index];
ts_ns = base * mult1 * mult2;
ret = ts_ns / 1000;
} else {
/* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
base = 80;
else
base = 10;
mult1 = mmr_image & UV2_ACK_MASK;
ret = mult1 * base;
}
return ret;
}
static void __init init_per_cpu_tunables(void)
{
int cpu;
struct bau_control *bcp;
for_each_present_cpu(cpu) {
bcp = &per_cpu(bau_control, cpu);
bcp->baudisabled = 0;
bcp->statp = &per_cpu(ptcstats, cpu);
/* time interval to catch a hardware stay-busy bug */
bcp->timeout_interval = usec_2_cycles(2*timeout_us);
bcp->max_concurr = max_concurr;
bcp->max_concurr_const = max_concurr;
bcp->plugged_delay = plugged_delay;
bcp->plugsb4reset = plugsb4reset;
bcp->timeoutsb4reset = timeoutsb4reset;
bcp->ipi_reset_limit = ipi_reset_limit;
bcp->complete_threshold = complete_threshold;
bcp->cong_response_us = congested_respns_us;
bcp->cong_reps = congested_reps;
bcp->cong_period = congested_period;
bcp->clocks_per_100_usec = usec_2_cycles(100);
spin_lock_init(&bcp->queue_lock);
spin_lock_init(&bcp->uvhub_lock);
}
}
/*
* Scan all cpus to collect blade and socket summaries.
*/
static int __init get_cpu_topology(int base_pnode,
struct uvhub_desc *uvhub_descs,
unsigned char *uvhub_mask)
{
int cpu;
int pnode;
int uvhub;
int socket;
struct bau_control *bcp;
struct uvhub_desc *bdp;
struct socket_desc *sdp;
for_each_present_cpu(cpu) {
bcp = &per_cpu(bau_control, cpu);
memset(bcp, 0, sizeof(struct bau_control));
pnode = uv_cpu_hub_info(cpu)->pnode;
if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
printk(KERN_EMERG
"cpu %d pnode %d-%d beyond %d; BAU disabled\n",
cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
return 1;
}
bcp->osnode = cpu_to_node(cpu);
bcp->partition_base_pnode = base_pnode;
uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
*(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
bdp = &uvhub_descs[uvhub];
bdp->num_cpus++;
bdp->uvhub = uvhub;
bdp->pnode = pnode;
/* kludge: 'assuming' one node per socket, and assuming that
disabling a socket just leaves a gap in node numbers */
socket = bcp->osnode & 1;
bdp->socket_mask |= (1 << socket);
sdp = &bdp->socket[socket];
sdp->cpu_number[sdp->num_cpus] = cpu;
sdp->num_cpus++;
if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
printk(KERN_EMERG "%d cpus per socket invalid\n",
sdp->num_cpus);
return 1;
}
}
return 0;
}
/*
* Each socket is to get a local array of pnodes/hubs.
*/
static void make_per_cpu_thp(struct bau_control *smaster)
{
int cpu;
size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
memset(smaster->thp, 0, hpsz);
for_each_present_cpu(cpu) {
smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
}
}
/*
* Each uvhub is to get a local cpumask.
*/
static void make_per_hub_cpumask(struct bau_control *hmaster)
{
int sz = sizeof(cpumask_t);
hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
}
/*
* Initialize all the per_cpu information for the cpu's on a given socket,
* given what has been gathered into the socket_desc struct.
* And reports the chosen hub and socket masters back to the caller.
*/
static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
struct bau_control **smasterp,
struct bau_control **hmasterp)
{
int i;
int cpu;
struct bau_control *bcp;
for (i = 0; i < sdp->num_cpus; i++) {
cpu = sdp->cpu_number[i];
bcp = &per_cpu(bau_control, cpu);
bcp->cpu = cpu;
if (i == 0) {
*smasterp = bcp;
if (!(*hmasterp))
*hmasterp = bcp;
}
bcp->cpus_in_uvhub = bdp->num_cpus;
bcp->cpus_in_socket = sdp->num_cpus;
bcp->socket_master = *smasterp;
bcp->uvhub = bdp->uvhub;
if (is_uv1_hub())
bcp->uvhub_version = 1;
else if (is_uv2_hub())
bcp->uvhub_version = 2;
else {
printk(KERN_EMERG "uvhub version not 1 or 2\n");
return 1;
}
bcp->uvhub_master = *hmasterp;
bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
bcp->using_desc = bcp->uvhub_cpu;
if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
printk(KERN_EMERG "%d cpus per uvhub invalid\n",
bcp->uvhub_cpu);
return 1;
}
}
return 0;
}
/*
* Summarize the blade and socket topology into the per_cpu structures.
*/
static int __init summarize_uvhub_sockets(int nuvhubs,
struct uvhub_desc *uvhub_descs,
unsigned char *uvhub_mask)
{
int socket;
int uvhub;
unsigned short socket_mask;
for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
struct uvhub_desc *bdp;
struct bau_control *smaster = NULL;
struct bau_control *hmaster = NULL;
if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
continue;
bdp = &uvhub_descs[uvhub];
socket_mask = bdp->socket_mask;
socket = 0;
while (socket_mask) {
struct socket_desc *sdp;
if ((socket_mask & 1)) {
sdp = &bdp->socket[socket];
if (scan_sock(sdp, bdp, &smaster, &hmaster))
return 1;
make_per_cpu_thp(smaster);
}
socket++;
socket_mask = (socket_mask >> 1);
}
make_per_hub_cpumask(hmaster);
}
return 0;
}
/*
* initialize the bau_control structure for each cpu
*/
static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
{
unsigned char *uvhub_mask;
void *vp;
struct uvhub_desc *uvhub_descs;
timeout_us = calculate_destination_timeout();
vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
uvhub_descs = (struct uvhub_desc *)vp;
memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
goto fail;
if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
goto fail;
kfree(uvhub_descs);
kfree(uvhub_mask);
init_per_cpu_tunables();
return 0;
fail:
kfree(uvhub_descs);
kfree(uvhub_mask);
return 1;
}
/*
* Initialization of BAU-related structures
*/
static int __init uv_bau_init(void)
{
int uvhub;
int pnode;
int nuvhubs;
int cur_cpu;
int cpus;
int vector;
cpumask_var_t *mask;
if (!is_uv_system())
return 0;
if (nobau)
return 0;
for_each_possible_cpu(cur_cpu) {
mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
}
nuvhubs = uv_num_possible_blades();
spin_lock_init(&disable_lock);
congested_cycles = usec_2_cycles(congested_respns_us);
uv_base_pnode = 0x7fffffff;
for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
cpus = uv_blade_nr_possible_cpus(uvhub);
if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
uv_base_pnode = uv_blade_to_pnode(uvhub);
}
enable_timeouts();
if (init_per_cpu(nuvhubs, uv_base_pnode)) {
nobau = 1;
return 0;
}
vector = UV_BAU_MESSAGE;
for_each_possible_blade(uvhub)
if (uv_blade_nr_possible_cpus(uvhub))
init_uvhub(uvhub, vector, uv_base_pnode);
alloc_intr_gate(vector, uv_bau_message_intr1);
for_each_possible_blade(uvhub) {
if (uv_blade_nr_possible_cpus(uvhub)) {
unsigned long val;
unsigned long mmr;
pnode = uv_blade_to_pnode(uvhub);
/* INIT the bau */
val = 1L << 63;
write_gmmr_activation(pnode, val);
mmr = 1; /* should be 1 to broadcast to both sockets */
if (!is_uv1_hub())
write_mmr_data_broadcast(pnode, mmr);
}
}
return 0;
}
core_initcall(uv_bau_init);
fs_initcall(uv_ptc_init);
| gpl-2.0 |
ysat0/linux-ysato | drivers/video/omap/lcd_inn1510.c | 3249 | 2764 | /*
* LCD panel support for the TI OMAP1510 Innovator board
*
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include "omapfb.h"
static int innovator1510_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
return 0;
}
static void innovator1510_panel_cleanup(struct lcd_panel *panel)
{
}
static int innovator1510_panel_enable(struct lcd_panel *panel)
{
__raw_writeb(0x7, OMAP1510_FPGA_LCD_PANEL_CONTROL);
return 0;
}
static void innovator1510_panel_disable(struct lcd_panel *panel)
{
__raw_writeb(0x0, OMAP1510_FPGA_LCD_PANEL_CONTROL);
}
static unsigned long innovator1510_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
struct lcd_panel innovator1510_panel = {
.name = "inn1510",
.config = OMAP_LCDC_PANEL_TFT,
.bpp = 16,
.data_lines = 16,
.x_res = 240,
.y_res = 320,
.pixel_clock = 12500,
.hsw = 40,
.hfp = 40,
.hbp = 72,
.vsw = 1,
.vfp = 1,
.vbp = 0,
.pcd = 12,
.init = innovator1510_panel_init,
.cleanup = innovator1510_panel_cleanup,
.enable = innovator1510_panel_enable,
.disable = innovator1510_panel_disable,
.get_caps = innovator1510_panel_get_caps,
};
static int innovator1510_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&innovator1510_panel);
return 0;
}
static int innovator1510_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int innovator1510_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int innovator1510_panel_resume(struct platform_device *pdev)
{
return 0;
}
static struct platform_driver innovator1510_panel_driver = {
.probe = innovator1510_panel_probe,
.remove = innovator1510_panel_remove,
.suspend = innovator1510_panel_suspend,
.resume = innovator1510_panel_resume,
.driver = {
.name = "lcd_inn1510",
.owner = THIS_MODULE,
},
};
module_platform_driver(innovator1510_panel_driver);
| gpl-2.0 |
kashifmin/BLU_LIFE_ONE | drivers/mtd/nand/omap2.c | 3249 | 31821 | /*
* Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
* Copyright © 2004 Micron Technology Inc.
* Copyright © 2004 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <plat/dma.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
#define DRIVER_NAME "omap2-nand"
#define OMAP_NAND_TIMEOUT_MS 5000
#define NAND_Ecc_P1e (1 << 0)
#define NAND_Ecc_P2e (1 << 1)
#define NAND_Ecc_P4e (1 << 2)
#define NAND_Ecc_P8e (1 << 3)
#define NAND_Ecc_P16e (1 << 4)
#define NAND_Ecc_P32e (1 << 5)
#define NAND_Ecc_P64e (1 << 6)
#define NAND_Ecc_P128e (1 << 7)
#define NAND_Ecc_P256e (1 << 8)
#define NAND_Ecc_P512e (1 << 9)
#define NAND_Ecc_P1024e (1 << 10)
#define NAND_Ecc_P2048e (1 << 11)
#define NAND_Ecc_P1o (1 << 16)
#define NAND_Ecc_P2o (1 << 17)
#define NAND_Ecc_P4o (1 << 18)
#define NAND_Ecc_P8o (1 << 19)
#define NAND_Ecc_P16o (1 << 20)
#define NAND_Ecc_P32o (1 << 21)
#define NAND_Ecc_P64o (1 << 22)
#define NAND_Ecc_P128o (1 << 23)
#define NAND_Ecc_P256o (1 << 24)
#define NAND_Ecc_P512o (1 << 25)
#define NAND_Ecc_P1024o (1 << 26)
#define NAND_Ecc_P2048o (1 << 27)
#define TF(value) (value ? 1 : 0)
#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
/* oob info generated runtime depending on ecc algorithm and layout selected */
static struct nand_ecclayout omap_oobinfo;
/* Define some generic bad / good block scan pattern which are used
* while scanning a device for factory marked good / bad blocks
*/
static uint8_t scan_ff_pattern[] = { 0xff };
static struct nand_bbt_descr bb_descrip_flashbased = {
.options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
.offs = 0,
.len = 1,
.pattern = scan_ff_pattern,
};
struct omap_nand_info {
struct nand_hw_control controller;
struct omap_nand_platform_data *pdata;
struct mtd_info mtd;
struct nand_chip nand;
struct platform_device *pdev;
int gpmc_cs;
unsigned long phys_base;
struct completion comp;
int dma_ch;
int gpmc_irq;
enum {
OMAP_NAND_IO_READ = 0, /* read */
OMAP_NAND_IO_WRITE, /* write */
} iomode;
u_char *buf;
int buf_len;
};
/**
* omap_hwcontrol - hardware specific access to control-lines
* @mtd: MTD device structure
* @cmd: command to device
* @ctrl:
* NAND_NCE: bit 0 -> don't care
* NAND_CLE: bit 1 -> Command Latch
* NAND_ALE: bit 2 -> Address Latch
*
* NOTE: boards may use different bits for these!!
*/
static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
if (cmd != NAND_CMD_NONE) {
if (ctrl & NAND_CLE)
gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
else if (ctrl & NAND_ALE)
gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
else /* NAND_NCE */
gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
}
}
/**
* omap_read_buf8 - read data from NAND controller into buffer
* @mtd: MTD device structure
* @buf: buffer to store date
* @len: number of bytes to read
*/
static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
{
struct nand_chip *nand = mtd->priv;
ioread8_rep(nand->IO_ADDR_R, buf, len);
}
/**
* omap_write_buf8 - write buffer to NAND controller
* @mtd: MTD device structure
* @buf: data buffer
* @len: number of bytes to write
*/
static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
u_char *p = (u_char *)buf;
u32 status = 0;
while (len--) {
iowrite8(*p++, info->nand.IO_ADDR_W);
/* wait until buffer is available for write */
do {
status = gpmc_read_status(GPMC_STATUS_BUFFER);
} while (!status);
}
}
/**
* omap_read_buf16 - read data from NAND controller into buffer
* @mtd: MTD device structure
* @buf: buffer to store date
* @len: number of bytes to read
*/
static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
{
struct nand_chip *nand = mtd->priv;
ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
}
/**
* omap_write_buf16 - write buffer to NAND controller
* @mtd: MTD device structure
* @buf: data buffer
* @len: number of bytes to write
*/
static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
u16 *p = (u16 *) buf;
u32 status = 0;
/* FIXME try bursts of writesw() or DMA ... */
len >>= 1;
while (len--) {
iowrite16(*p++, info->nand.IO_ADDR_W);
/* wait until buffer is available for write */
do {
status = gpmc_read_status(GPMC_STATUS_BUFFER);
} while (!status);
}
}
/**
* omap_read_buf_pref - read data from NAND controller into buffer
* @mtd: MTD device structure
* @buf: buffer to store date
* @len: number of bytes to read
*/
static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
uint32_t r_count = 0;
int ret = 0;
u32 *p = (u32 *)buf;
/* take care of subpage reads */
if (len % 4) {
if (info->nand.options & NAND_BUSWIDTH_16)
omap_read_buf16(mtd, buf, len % 4);
else
omap_read_buf8(mtd, buf, len % 4);
p = (u32 *) (buf + len % 4);
len -= len % 4;
}
/* configure and start prefetch transfer */
ret = gpmc_prefetch_enable(info->gpmc_cs,
PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
if (ret) {
/* PFPW engine is busy, use cpu copy method */
if (info->nand.options & NAND_BUSWIDTH_16)
omap_read_buf16(mtd, (u_char *)p, len);
else
omap_read_buf8(mtd, (u_char *)p, len);
} else {
do {
r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
r_count = r_count >> 2;
ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
p += r_count;
len -= r_count << 2;
} while (len);
/* disable and stop the PFPW engine */
gpmc_prefetch_reset(info->gpmc_cs);
}
}
/**
* omap_write_buf_pref - write buffer to NAND controller
* @mtd: MTD device structure
* @buf: data buffer
* @len: number of bytes to write
*/
static void omap_write_buf_pref(struct mtd_info *mtd,
const u_char *buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
uint32_t w_count = 0;
int i = 0, ret = 0;
u16 *p = (u16 *)buf;
unsigned long tim, limit;
/* take care of subpage writes */
if (len % 2 != 0) {
writeb(*buf, info->nand.IO_ADDR_W);
p = (u16 *)(buf + 1);
len--;
}
/* configure and start prefetch transfer */
ret = gpmc_prefetch_enable(info->gpmc_cs,
PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
if (ret) {
/* PFPW engine is busy, use cpu copy method */
if (info->nand.options & NAND_BUSWIDTH_16)
omap_write_buf16(mtd, (u_char *)p, len);
else
omap_write_buf8(mtd, (u_char *)p, len);
} else {
while (len) {
w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
w_count = w_count >> 1;
for (i = 0; (i < w_count) && len; i++, len -= 2)
iowrite16(*p++, info->nand.IO_ADDR_W);
}
/* wait for data to flushed-out before reset the prefetch */
tim = 0;
limit = (loops_per_jiffy *
msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
cpu_relax();
/* disable and stop the PFPW engine */
gpmc_prefetch_reset(info->gpmc_cs);
}
}
/*
* omap_nand_dma_cb: callback on the completion of dma transfer
* @lch: logical channel
* @ch_satuts: channel status
* @data: pointer to completion data structure
*/
static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
{
complete((struct completion *) data);
}
/*
* omap_nand_dma_transfer: configer and start dma transfer
* @mtd: MTD device structure
* @addr: virtual address in RAM of source/destination
* @len: number of data bytes to be transferred
* @is_write: flag for read/write operation
*/
static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
unsigned int len, int is_write)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
DMA_FROM_DEVICE;
dma_addr_t dma_addr;
int ret;
unsigned long tim, limit;
/* The fifo depth is 64 bytes max.
* But configure the FIFO-threahold to 32 to get a sync at each frame
* and frame length is 32 bytes.
*/
int buf_len = len >> 6;
if (addr >= high_memory) {
struct page *p1;
if (((size_t)addr & PAGE_MASK) !=
((size_t)(addr + len - 1) & PAGE_MASK))
goto out_copy;
p1 = vmalloc_to_page(addr);
if (!p1)
goto out_copy;
addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
}
dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
dev_err(&info->pdev->dev,
"Couldn't DMA map a %d byte buffer\n", len);
goto out_copy;
}
if (is_write) {
omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
info->phys_base, 0, 0);
omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
dma_addr, 0, 0);
omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
0x10, buf_len, OMAP_DMA_SYNC_FRAME,
OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
} else {
omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
info->phys_base, 0, 0);
omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
dma_addr, 0, 0);
omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
0x10, buf_len, OMAP_DMA_SYNC_FRAME,
OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
}
/* configure and start prefetch transfer */
ret = gpmc_prefetch_enable(info->gpmc_cs,
PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
if (ret)
/* PFPW engine is busy, use cpu copy method */
goto out_copy;
init_completion(&info->comp);
omap_start_dma(info->dma_ch);
/* setup and start DMA using dma_addr */
wait_for_completion(&info->comp);
tim = 0;
limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
cpu_relax();
/* disable and stop the PFPW engine */
gpmc_prefetch_reset(info->gpmc_cs);
dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
return 0;
out_copy:
if (info->nand.options & NAND_BUSWIDTH_16)
is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
: omap_write_buf16(mtd, (u_char *) addr, len);
else
is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
: omap_write_buf8(mtd, (u_char *) addr, len);
return 0;
}
/**
* omap_read_buf_dma_pref - read data from NAND controller into buffer
* @mtd: MTD device structure
* @buf: buffer to store date
* @len: number of bytes to read
*/
static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
{
if (len <= mtd->oobsize)
omap_read_buf_pref(mtd, buf, len);
else
/* start transfer in DMA mode */
omap_nand_dma_transfer(mtd, buf, len, 0x0);
}
/**
* omap_write_buf_dma_pref - write buffer to NAND controller
* @mtd: MTD device structure
* @buf: data buffer
* @len: number of bytes to write
*/
static void omap_write_buf_dma_pref(struct mtd_info *mtd,
const u_char *buf, int len)
{
if (len <= mtd->oobsize)
omap_write_buf_pref(mtd, buf, len);
else
/* start transfer in DMA mode */
omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
}
/*
* omap_nand_irq - GMPC irq handler
* @this_irq: gpmc irq number
* @dev: omap_nand_info structure pointer is passed here
*/
static irqreturn_t omap_nand_irq(int this_irq, void *dev)
{
struct omap_nand_info *info = (struct omap_nand_info *) dev;
u32 bytes;
u32 irq_stat;
irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
if (irq_stat & 0x2)
goto done;
if (info->buf_len && (info->buf_len < bytes))
bytes = info->buf_len;
else if (!info->buf_len)
bytes = 0;
iowrite32_rep(info->nand.IO_ADDR_W,
(u32 *)info->buf, bytes >> 2);
info->buf = info->buf + bytes;
info->buf_len -= bytes;
} else {
ioread32_rep(info->nand.IO_ADDR_R,
(u32 *)info->buf, bytes >> 2);
info->buf = info->buf + bytes;
if (irq_stat & 0x2)
goto done;
}
gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
return IRQ_HANDLED;
done:
complete(&info->comp);
/* disable irq */
gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
/* clear status */
gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
return IRQ_HANDLED;
}
/*
* omap_read_buf_irq_pref - read data from NAND controller into buffer
* @mtd: MTD device structure
* @buf: buffer to store date
* @len: number of bytes to read
*/
static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
int ret = 0;
if (len <= mtd->oobsize) {
omap_read_buf_pref(mtd, buf, len);
return;
}
info->iomode = OMAP_NAND_IO_READ;
info->buf = buf;
init_completion(&info->comp);
/* configure and start prefetch transfer */
ret = gpmc_prefetch_enable(info->gpmc_cs,
PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
if (ret)
/* PFPW engine is busy, use cpu copy method */
goto out_copy;
info->buf_len = len;
/* enable irq */
gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
(GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
/* waiting for read to complete */
wait_for_completion(&info->comp);
/* disable and stop the PFPW engine */
gpmc_prefetch_reset(info->gpmc_cs);
return;
out_copy:
if (info->nand.options & NAND_BUSWIDTH_16)
omap_read_buf16(mtd, buf, len);
else
omap_read_buf8(mtd, buf, len);
}
/*
* omap_write_buf_irq_pref - write buffer to NAND controller
* @mtd: MTD device structure
* @buf: data buffer
* @len: number of bytes to write
*/
static void omap_write_buf_irq_pref(struct mtd_info *mtd,
const u_char *buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
struct omap_nand_info, mtd);
int ret = 0;
unsigned long tim, limit;
if (len <= mtd->oobsize) {
omap_write_buf_pref(mtd, buf, len);
return;
}
info->iomode = OMAP_NAND_IO_WRITE;
info->buf = (u_char *) buf;
init_completion(&info->comp);
/* configure and start prefetch transfer : size=24 */
ret = gpmc_prefetch_enable(info->gpmc_cs,
(PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
if (ret)
/* PFPW engine is busy, use cpu copy method */
goto out_copy;
info->buf_len = len;
/* enable irq */
gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
(GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
/* waiting for write to complete */
wait_for_completion(&info->comp);
/* wait for data to flushed-out before reset the prefetch */
tim = 0;
limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
cpu_relax();
/* disable and stop the PFPW engine */
gpmc_prefetch_reset(info->gpmc_cs);
return;
out_copy:
if (info->nand.options & NAND_BUSWIDTH_16)
omap_write_buf16(mtd, buf, len);
else
omap_write_buf8(mtd, buf, len);
}
/**
* omap_verify_buf - Verify chip data against buffer
* @mtd: MTD device structure
* @buf: buffer containing the data to compare
* @len: number of bytes to compare
*/
static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
u16 *p = (u16 *) buf;
len >>= 1;
while (len--) {
if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
return -EFAULT;
}
return 0;
}
/**
* gen_true_ecc - This function will generate true ECC value
* @ecc_buf: buffer to store ecc code
*
* This generated true ECC value can be used when correcting
* data read from NAND flash memory core
*/
static void gen_true_ecc(u8 *ecc_buf)
{
u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
P1e(tmp) | P2048o(tmp) | P2048e(tmp));
}
/**
* omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
* @ecc_data1: ecc code from nand spare area
* @ecc_data2: ecc code from hardware register obtained from hardware ecc
* @page_data: page data
*
* This function compares two ECC's and indicates if there is an error.
* If the error can be corrected it will be corrected to the buffer.
* If there is no error, %0 is returned. If there is an error but it
* was corrected, %1 is returned. Otherwise, %-1 is returned.
*/
static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
u8 *ecc_data2, /* read from register */
u8 *page_data)
{
uint i;
u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
u8 ecc_bit[24];
u8 ecc_sum = 0;
u8 find_bit = 0;
uint find_byte = 0;
int isEccFF;
isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
gen_true_ecc(ecc_data1);
gen_true_ecc(ecc_data2);
for (i = 0; i <= 2; i++) {
*(ecc_data1 + i) = ~(*(ecc_data1 + i));
*(ecc_data2 + i) = ~(*(ecc_data2 + i));
}
for (i = 0; i < 8; i++) {
tmp0_bit[i] = *ecc_data1 % 2;
*ecc_data1 = *ecc_data1 / 2;
}
for (i = 0; i < 8; i++) {
tmp1_bit[i] = *(ecc_data1 + 1) % 2;
*(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
}
for (i = 0; i < 8; i++) {
tmp2_bit[i] = *(ecc_data1 + 2) % 2;
*(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
}
for (i = 0; i < 8; i++) {
comp0_bit[i] = *ecc_data2 % 2;
*ecc_data2 = *ecc_data2 / 2;
}
for (i = 0; i < 8; i++) {
comp1_bit[i] = *(ecc_data2 + 1) % 2;
*(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
}
for (i = 0; i < 8; i++) {
comp2_bit[i] = *(ecc_data2 + 2) % 2;
*(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
}
for (i = 0; i < 6; i++)
ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
for (i = 0; i < 8; i++)
ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
for (i = 0; i < 8; i++)
ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
for (i = 0; i < 24; i++)
ecc_sum += ecc_bit[i];
switch (ecc_sum) {
case 0:
/* Not reached because this function is not called if
* ECC values are equal
*/
return 0;
case 1:
/* Uncorrectable error */
pr_debug("ECC UNCORRECTED_ERROR 1\n");
return -1;
case 11:
/* UN-Correctable error */
pr_debug("ECC UNCORRECTED_ERROR B\n");
return -1;
case 12:
/* Correctable error */
find_byte = (ecc_bit[23] << 8) +
(ecc_bit[21] << 7) +
(ecc_bit[19] << 6) +
(ecc_bit[17] << 5) +
(ecc_bit[15] << 4) +
(ecc_bit[13] << 3) +
(ecc_bit[11] << 2) +
(ecc_bit[9] << 1) +
ecc_bit[7];
find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
pr_debug("Correcting single bit ECC error at offset: "
"%d, bit: %d\n", find_byte, find_bit);
page_data[find_byte] ^= (1 << find_bit);
return 1;
default:
if (isEccFF) {
if (ecc_data2[0] == 0 &&
ecc_data2[1] == 0 &&
ecc_data2[2] == 0)
return 0;
}
pr_debug("UNCORRECTED_ERROR default\n");
return -1;
}
}
/**
* omap_correct_data - Compares the ECC read with HW generated ECC
* @mtd: MTD device structure
* @dat: page data
* @read_ecc: ecc read from nand flash
* @calc_ecc: ecc read from HW ECC registers
*
* Compares the ecc read from nand spare area with ECC registers values
* and if ECC's mismatched, it will call 'omap_compare_ecc' for error
* detection and correction. If there are no errors, %0 is returned. If
* there were errors and all of the errors were corrected, the number of
* corrected errors is returned. If uncorrectable errors exist, %-1 is
* returned.
*/
static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
int blockCnt = 0, i = 0, ret = 0;
int stat = 0;
/* Ex NAND_ECC_HW12_2048 */
if ((info->nand.ecc.mode == NAND_ECC_HW) &&
(info->nand.ecc.size == 2048))
blockCnt = 4;
else
blockCnt = 1;
for (i = 0; i < blockCnt; i++) {
if (memcmp(read_ecc, calc_ecc, 3) != 0) {
ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
if (ret < 0)
return ret;
/* keep track of the number of corrected errors */
stat += ret;
}
read_ecc += 3;
calc_ecc += 3;
dat += 512;
}
return stat;
}
/**
* omap_calcuate_ecc - Generate non-inverted ECC bytes.
* @mtd: MTD device structure
* @dat: The pointer to data on which ecc is computed
* @ecc_code: The ecc_code buffer
*
* Using noninverted ECC can be considered ugly since writing a blank
* page ie. padding will clear the ECC bytes. This is no problem as long
* nobody is trying to write data on the seemingly unused page. Reading
* an erased page will produce an ECC mismatch between generated and read
* ECC bytes that has to be dealt with separately.
*/
static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
}
/**
* omap_enable_hwecc - This function enables the hardware ecc functionality
* @mtd: MTD device structure
* @mode: Read/Write mode
*/
static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
struct nand_chip *chip = mtd->priv;
unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
}
/**
* omap_wait - wait until the command is done
* @mtd: MTD device structure
* @chip: NAND Chip structure
*
* Wait function is called during Program and erase operations and
* the way it is called from MTD layer, we should wait till the NAND
* chip is ready after the programming/erase operation has completed.
*
* Erase can take up to 400ms and program up to 20ms according to
* general NAND and SmartMedia specs
*/
static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
struct nand_chip *this = mtd->priv;
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
unsigned long timeo = jiffies;
int status = NAND_STATUS_FAIL, state = this->state;
if (state == FL_ERASING)
timeo += (HZ * 400) / 1000;
else
timeo += (HZ * 20) / 1000;
gpmc_nand_write(info->gpmc_cs,
GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
while (time_before(jiffies, timeo)) {
status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
if (status & NAND_STATUS_READY)
break;
cond_resched();
}
return status;
}
/**
* omap_dev_ready - calls the platform specific dev_ready function
* @mtd: MTD device structure
*/
static int omap_dev_ready(struct mtd_info *mtd)
{
unsigned int val = 0;
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
if ((val & 0x100) == 0x100) {
/* Clear IRQ Interrupt */
val |= 0x100;
val &= ~(0x0);
gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
} else {
unsigned int cnt = 0;
while (cnt++ < 0x1FF) {
if ((val & 0x100) == 0x100)
return 0;
val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
}
}
return 1;
}
static int __devinit omap_nand_probe(struct platform_device *pdev)
{
struct omap_nand_info *info;
struct omap_nand_platform_data *pdata;
int err;
int i, offset;
pdata = pdev->dev.platform_data;
if (pdata == NULL) {
dev_err(&pdev->dev, "platform data missing\n");
return -ENODEV;
}
info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
if (!info)
return -ENOMEM;
platform_set_drvdata(pdev, info);
spin_lock_init(&info->controller.lock);
init_waitqueue_head(&info->controller.wq);
info->pdev = pdev;
info->gpmc_cs = pdata->cs;
info->phys_base = pdata->phys_base;
info->mtd.priv = &info->nand;
info->mtd.name = dev_name(&pdev->dev);
info->mtd.owner = THIS_MODULE;
info->nand.options = pdata->devsize;
info->nand.options |= NAND_SKIP_BBTSCAN;
/* NAND write protect off */
gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
pdev->dev.driver->name)) {
err = -EBUSY;
goto out_free_info;
}
info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
if (!info->nand.IO_ADDR_R) {
err = -ENOMEM;
goto out_release_mem_region;
}
info->nand.controller = &info->controller;
info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
info->nand.cmd_ctrl = omap_hwcontrol;
/*
* If RDY/BSY line is connected to OMAP then use the omap ready
* funcrtion and the generic nand_wait function which reads the status
* register after monitoring the RDY/BSY line.Otherwise use a standard
* chip delay which is slightly more than tR (AC Timing) of the NAND
* device and read status register until you get a failure or success
*/
if (pdata->dev_ready) {
info->nand.dev_ready = omap_dev_ready;
info->nand.chip_delay = 0;
} else {
info->nand.waitfunc = omap_wait;
info->nand.chip_delay = 50;
}
switch (pdata->xfer_type) {
case NAND_OMAP_PREFETCH_POLLED:
info->nand.read_buf = omap_read_buf_pref;
info->nand.write_buf = omap_write_buf_pref;
break;
case NAND_OMAP_POLLED:
if (info->nand.options & NAND_BUSWIDTH_16) {
info->nand.read_buf = omap_read_buf16;
info->nand.write_buf = omap_write_buf16;
} else {
info->nand.read_buf = omap_read_buf8;
info->nand.write_buf = omap_write_buf8;
}
break;
case NAND_OMAP_PREFETCH_DMA:
err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
omap_nand_dma_cb, &info->comp, &info->dma_ch);
if (err < 0) {
info->dma_ch = -1;
dev_err(&pdev->dev, "DMA request failed!\n");
goto out_release_mem_region;
} else {
omap_set_dma_dest_burst_mode(info->dma_ch,
OMAP_DMA_DATA_BURST_16);
omap_set_dma_src_burst_mode(info->dma_ch,
OMAP_DMA_DATA_BURST_16);
info->nand.read_buf = omap_read_buf_dma_pref;
info->nand.write_buf = omap_write_buf_dma_pref;
}
break;
case NAND_OMAP_PREFETCH_IRQ:
err = request_irq(pdata->gpmc_irq,
omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
if (err) {
dev_err(&pdev->dev, "requesting irq(%d) error:%d",
pdata->gpmc_irq, err);
goto out_release_mem_region;
} else {
info->gpmc_irq = pdata->gpmc_irq;
info->nand.read_buf = omap_read_buf_irq_pref;
info->nand.write_buf = omap_write_buf_irq_pref;
}
break;
default:
dev_err(&pdev->dev,
"xfer_type(%d) not supported!\n", pdata->xfer_type);
err = -EINVAL;
goto out_release_mem_region;
}
info->nand.verify_buf = omap_verify_buf;
/* selsect the ecc type */
if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
info->nand.ecc.mode = NAND_ECC_SOFT;
else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
(pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
info->nand.ecc.bytes = 3;
info->nand.ecc.size = 512;
info->nand.ecc.strength = 1;
info->nand.ecc.calculate = omap_calculate_ecc;
info->nand.ecc.hwctl = omap_enable_hwecc;
info->nand.ecc.correct = omap_correct_data;
info->nand.ecc.mode = NAND_ECC_HW;
}
/* DIP switches on some boards change between 8 and 16 bit
* bus widths for flash. Try the other width if the first try fails.
*/
if (nand_scan_ident(&info->mtd, 1, NULL)) {
info->nand.options ^= NAND_BUSWIDTH_16;
if (nand_scan_ident(&info->mtd, 1, NULL)) {
err = -ENXIO;
goto out_release_mem_region;
}
}
/* rom code layout */
if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
if (info->nand.options & NAND_BUSWIDTH_16)
offset = 2;
else {
offset = 1;
info->nand.badblock_pattern = &bb_descrip_flashbased;
}
omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
for (i = 0; i < omap_oobinfo.eccbytes; i++)
omap_oobinfo.eccpos[i] = i+offset;
omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
omap_oobinfo.oobfree->length = info->mtd.oobsize -
(offset + omap_oobinfo.eccbytes);
info->nand.ecc.layout = &omap_oobinfo;
}
/* second phase scan */
if (nand_scan_tail(&info->mtd)) {
err = -ENXIO;
goto out_release_mem_region;
}
mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
pdata->nr_parts);
platform_set_drvdata(pdev, &info->mtd);
return 0;
out_release_mem_region:
release_mem_region(info->phys_base, NAND_IO_SIZE);
out_free_info:
kfree(info);
return err;
}
static int omap_nand_remove(struct platform_device *pdev)
{
struct mtd_info *mtd = platform_get_drvdata(pdev);
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
platform_set_drvdata(pdev, NULL);
if (info->dma_ch != -1)
omap_free_dma(info->dma_ch);
if (info->gpmc_irq)
free_irq(info->gpmc_irq, info);
/* Release NAND device, its internal structures and partitions */
nand_release(&info->mtd);
iounmap(info->nand.IO_ADDR_R);
kfree(&info->mtd);
return 0;
}
static struct platform_driver omap_nand_driver = {
.probe = omap_nand_probe,
.remove = omap_nand_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
},
};
module_platform_driver(omap_nand_driver);
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
| gpl-2.0 |
lolhi/ef52-kernel | drivers/misc/pm8xxx-nfc.c | 3505 | 7236 | /* Copyright (c) 2010,2011 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* Qualcomm PMIC8XXX NFC driver
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/mfd/pm8xxx/core.h>
#include <linux/mfd/pm8xxx/nfc.h>
/* PM8XXX NFC */
#define SSBI_REG_NFC_CTRL 0x14D
#define SSBI_REG_NFC_TEST 0x14E
/* NFC_CTRL */
#define PM8XXX_NFC_SUPPORT_EN 0x80
#define PM8XXX_NFC_LDO_EN 0x40
#define PM8XXX_NFC_EN 0x20
#define PM8XXX_NFC_EXT_VDDLDO_EN 0x10
#define PM8XXX_NFC_VPH_PWR_EN 0x08
#define PM8XXX_NFC_RESERVED 0x04
#define PM8XXX_NFC_VDDLDO_LEVEL 0x03
/* NFC_TEST */
#define PM8XXX_NFC_VDDLDO_MON_EN 0x80
#define PM8XXX_NFC_ATEST_EN 0x40
#define PM8XXX_NFC_DTEST1_EN 0x20
#define PM8XXX_NFC_RESERVED2 0x18
#define PM8XXX_NFC_VDDLDO_OK_S 0x04
#define PM8XXX_NFC_MBG_EN_S 0x02
#define PM8XXX_NFC_EXT_EN_S 0x01
struct pm8xxx_nfc_device {
struct device *dev;
struct mutex nfc_mutex;
#if defined(CONFIG_DEBUG_FS)
struct dentry *dent;
#endif
};
static struct pm8xxx_nfc_device *nfc_dev;
/* APIs */
/*
* pm8xxx_nfc_request - request a handle to access NFC device
*/
struct pm8xxx_nfc_device *pm8xxx_nfc_request(void)
{
return nfc_dev;
}
EXPORT_SYMBOL(pm8xxx_nfc_request);
/*
* pm8xxx_nfc_config - configure NFC signals
*
* @nfcdev: the NFC device
* @mask: signal mask to configure
* @flags: control flags
*/
int pm8xxx_nfc_config(struct pm8xxx_nfc_device *nfcdev, u32 mask, u32 flags)
{
u8 nfc_ctrl, nfc_test, m, f;
int rc;
if (nfcdev == NULL || IS_ERR(nfcdev) || !mask)
return -EINVAL;
mutex_lock(&nfcdev->nfc_mutex);
if (!(mask & PM_NFC_CTRL_REQ))
goto config_test;
rc = pm8xxx_readb(nfcdev->dev->parent, SSBI_REG_NFC_CTRL, &nfc_ctrl);
if (rc) {
pr_err("%s: FAIL pm8xxx_readb(): rc=%d (nfc_ctrl=0x%x)\n",
__func__, rc, nfc_ctrl);
goto config_done;
}
m = mask & 0x00ff;
f = flags & 0x00ff;
nfc_ctrl &= ~m;
nfc_ctrl |= m & f;
rc = pm8xxx_writeb(nfcdev->dev->parent, SSBI_REG_NFC_CTRL, nfc_ctrl);
if (rc) {
pr_err("%s: FAIL pm8xxx_writeb(): rc=%d (nfc_ctrl=0x%x)\n",
__func__, rc, nfc_ctrl);
goto config_done;
}
config_test:
if (!(mask & PM_NFC_TEST_REQ))
goto config_done;
rc = pm8xxx_readb(nfcdev->dev->parent, SSBI_REG_NFC_TEST, &nfc_test);
if (rc) {
pr_err("%s: FAIL pm8xxx_readb(): rc=%d (nfc_test=0x%x)\n",
__func__, rc, nfc_test);
goto config_done;
}
m = (mask >> 8) & 0x00ff;
f = (flags >> 8) & 0x00ff;
nfc_test &= ~m;
nfc_test |= m & f;
rc = pm8xxx_writeb(nfcdev->dev->parent, SSBI_REG_NFC_TEST, nfc_test);
if (rc) {
pr_err("%s: FAIL pm8xxx_writeb(): rc=%d (nfc_test=0x%x)\n",
__func__, rc, nfc_test);
goto config_done;
}
config_done:
mutex_unlock(&nfcdev->nfc_mutex);
return 0;
}
EXPORT_SYMBOL(pm8xxx_nfc_config);
/*
* pm8xxx_nfc_get_status - get NFC status
*
* @nfcdev: the NFC device
* @mask: of status mask to read
* @status: pointer to the status variable
*/
int pm8xxx_nfc_get_status(struct pm8xxx_nfc_device *nfcdev,
u32 mask, u32 *status)
{
u8 nfc_ctrl, nfc_test;
u32 st;
int rc;
if (nfcdev == NULL || IS_ERR(nfcdev) || status == NULL)
return -EINVAL;
st = 0;
mutex_lock(&nfcdev->nfc_mutex);
if (!(mask & PM_NFC_CTRL_REQ))
goto read_test;
rc = pm8xxx_readb(nfcdev->dev->parent, SSBI_REG_NFC_CTRL, &nfc_ctrl);
if (rc) {
pr_err("%s: FAIL pm8xxx_readb(): rc=%d (nfc_ctrl=0x%x)\n",
__func__, rc, nfc_ctrl);
goto get_status_done;
}
read_test:
if (!(mask & (PM_NFC_TEST_REQ | PM_NFC_TEST_STATUS)))
goto get_status_done;
rc = pm8xxx_readb(nfcdev->dev->parent, SSBI_REG_NFC_TEST, &nfc_test);
if (rc)
pr_err("%s: FAIL pm8xxx_readb(): rc=%d (nfc_test=0x%x)\n",
__func__, rc, nfc_test);
get_status_done:
st = nfc_ctrl;
st |= nfc_test << 8;
*status = st;
mutex_unlock(&nfcdev->nfc_mutex);
return 0;
}
EXPORT_SYMBOL(pm8xxx_nfc_get_status);
/*
* pm8xxx_nfc_free - free the NFC device
*/
void pm8xxx_nfc_free(struct pm8xxx_nfc_device *nfcdev)
{
/* Disable all signals */
pm8xxx_nfc_config(nfcdev, PM_NFC_CTRL_REQ, 0);
}
EXPORT_SYMBOL(pm8xxx_nfc_free);
#if defined(CONFIG_DEBUG_FS)
static int pm8xxx_nfc_debug_set(void *data, u64 val)
{
struct pm8xxx_nfc_device *nfcdev;
u32 mask, control;
int rc;
nfcdev = (struct pm8xxx_nfc_device *)data;
control = (u32)val & 0xffff;
mask = ((u32)val >> 16) & 0xffff;
rc = pm8xxx_nfc_config(nfcdev, mask, control);
if (rc)
pr_err("%s: ERR pm8xxx_nfc_config: rc=%d, "
"[mask, control]=[0x%x, 0x%x]\n",
__func__, rc, mask, control);
return 0;
}
static int pm8xxx_nfc_debug_get(void *data, u64 *val)
{
struct pm8xxx_nfc_device *nfcdev;
u32 status;
int rc;
nfcdev = (struct pm8xxx_nfc_device *)data;
rc = pm8xxx_nfc_get_status(nfcdev, (u32)-1, &status);
if (rc)
pr_err("%s: ERR pm8xxx_nfc_get_status: rc=%d, status=0x%x\n",
__func__, rc, status);
if (val)
*val = (u64)status;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(pm8xxx_nfc_fops, pm8xxx_nfc_debug_get,
pm8xxx_nfc_debug_set, "%llu\n");
static int pm8xxx_nfc_debug_init(struct pm8xxx_nfc_device *nfcdev)
{
struct dentry *dent;
dent = debugfs_create_file("pm8xxx-nfc", 0644, NULL,
(void *)nfcdev, &pm8xxx_nfc_fops);
if (dent == NULL || IS_ERR(dent))
pr_err("%s: ERR debugfs_create_file: dent=0x%x\n",
__func__, (unsigned)dent);
nfcdev->dent = dent;
return 0;
}
#endif
static int __devinit pm8xxx_nfc_probe(struct platform_device *pdev)
{
struct pm8xxx_nfc_device *nfcdev;
nfcdev = kzalloc(sizeof *nfcdev, GFP_KERNEL);
if (nfcdev == NULL) {
pr_err("%s: kzalloc() failed.\n", __func__);
return -ENOMEM;
}
mutex_init(&nfcdev->nfc_mutex);
nfcdev->dev = &pdev->dev;
nfc_dev = nfcdev;
platform_set_drvdata(pdev, nfcdev);
#if defined(CONFIG_DEBUG_FS)
pm8xxx_nfc_debug_init(nfc_dev);
#endif
pr_notice("%s: OK\n", __func__);
return 0;
}
static int __devexit pm8xxx_nfc_remove(struct platform_device *pdev)
{
struct pm8xxx_nfc_device *nfcdev = platform_get_drvdata(pdev);
#if defined(CONFIG_DEBUG_FS)
debugfs_remove(nfcdev->dent);
#endif
platform_set_drvdata(pdev, NULL);
kfree(nfcdev);
return 0;
}
static struct platform_driver pm8xxx_nfc_driver = {
.probe = pm8xxx_nfc_probe,
.remove = __devexit_p(pm8xxx_nfc_remove),
.driver = {
.name = PM8XXX_NFC_DEV_NAME,
.owner = THIS_MODULE,
},
};
static int __init pm8xxx_nfc_init(void)
{
return platform_driver_register(&pm8xxx_nfc_driver);
}
static void __exit pm8xxx_nfc_exit(void)
{
platform_driver_unregister(&pm8xxx_nfc_driver);
}
module_init(pm8xxx_nfc_init);
module_exit(pm8xxx_nfc_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PM8XXX NFC driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:" PM8XXX_NFC_DEV_NAME);
| gpl-2.0 |
zaclimon/android_kernel_samsung_kylepro | drivers/usb/gadget/uvc_queue.c | 4785 | 15282 | /*
* uvc_queue.c -- USB Video Class driver - Buffers management
*
* Copyright (C) 2005-2010
* Laurent Pinchart (laurent.pinchart@ideasonboard.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/usb.h>
#include <linux/videodev2.h>
#include <linux/vmalloc.h>
#include <linux/wait.h>
#include <linux/atomic.h>
#include "uvc.h"
/* ------------------------------------------------------------------------
* Video buffers queue management.
*
* Video queues is initialized by uvc_queue_init(). The function performs
* basic initialization of the uvc_video_queue struct and never fails.
*
* Video buffer allocation and freeing are performed by uvc_alloc_buffers and
* uvc_free_buffers respectively. The former acquires the video queue lock,
* while the later must be called with the lock held (so that allocation can
* free previously allocated buffers). Trying to free buffers that are mapped
* to user space will return -EBUSY.
*
* Video buffers are managed using two queues. However, unlike most USB video
* drivers that use an in queue and an out queue, we use a main queue to hold
* all queued buffers (both 'empty' and 'done' buffers), and an irq queue to
* hold empty buffers. This design (copied from video-buf) minimizes locking
* in interrupt, as only one queue is shared between interrupt and user
* contexts.
*
* Use cases
* ---------
*
* Unless stated otherwise, all operations that modify the irq buffers queue
* are protected by the irq spinlock.
*
* 1. The user queues the buffers, starts streaming and dequeues a buffer.
*
* The buffers are added to the main and irq queues. Both operations are
* protected by the queue lock, and the later is protected by the irq
* spinlock as well.
*
* The completion handler fetches a buffer from the irq queue and fills it
* with video data. If no buffer is available (irq queue empty), the handler
* returns immediately.
*
* When the buffer is full, the completion handler removes it from the irq
* queue, marks it as ready (UVC_BUF_STATE_DONE) and wakes its wait queue.
* At that point, any process waiting on the buffer will be woken up. If a
* process tries to dequeue a buffer after it has been marked ready, the
* dequeing will succeed immediately.
*
* 2. Buffers are queued, user is waiting on a buffer and the device gets
* disconnected.
*
* When the device is disconnected, the kernel calls the completion handler
* with an appropriate status code. The handler marks all buffers in the
* irq queue as being erroneous (UVC_BUF_STATE_ERROR) and wakes them up so
* that any process waiting on a buffer gets woken up.
*
* Waking up up the first buffer on the irq list is not enough, as the
* process waiting on the buffer might restart the dequeue operation
* immediately.
*
*/
static void
uvc_queue_init(struct uvc_video_queue *queue, enum v4l2_buf_type type)
{
mutex_init(&queue->mutex);
spin_lock_init(&queue->irqlock);
INIT_LIST_HEAD(&queue->mainqueue);
INIT_LIST_HEAD(&queue->irqqueue);
queue->type = type;
}
/*
* Free the video buffers.
*
* This function must be called with the queue lock held.
*/
static int uvc_free_buffers(struct uvc_video_queue *queue)
{
unsigned int i;
for (i = 0; i < queue->count; ++i) {
if (queue->buffer[i].vma_use_count != 0)
return -EBUSY;
}
if (queue->count) {
vfree(queue->mem);
queue->count = 0;
}
return 0;
}
/*
* Allocate the video buffers.
*
* Pages are reserved to make sure they will not be swapped, as they will be
* filled in the URB completion handler.
*
* Buffers will be individually mapped, so they must all be page aligned.
*/
static int
uvc_alloc_buffers(struct uvc_video_queue *queue, unsigned int nbuffers,
unsigned int buflength)
{
unsigned int bufsize = PAGE_ALIGN(buflength);
unsigned int i;
void *mem = NULL;
int ret;
if (nbuffers > UVC_MAX_VIDEO_BUFFERS)
nbuffers = UVC_MAX_VIDEO_BUFFERS;
mutex_lock(&queue->mutex);
if ((ret = uvc_free_buffers(queue)) < 0)
goto done;
/* Bail out if no buffers should be allocated. */
if (nbuffers == 0)
goto done;
/* Decrement the number of buffers until allocation succeeds. */
for (; nbuffers > 0; --nbuffers) {
mem = vmalloc_32(nbuffers * bufsize);
if (mem != NULL)
break;
}
if (mem == NULL) {
ret = -ENOMEM;
goto done;
}
for (i = 0; i < nbuffers; ++i) {
memset(&queue->buffer[i], 0, sizeof queue->buffer[i]);
queue->buffer[i].buf.index = i;
queue->buffer[i].buf.m.offset = i * bufsize;
queue->buffer[i].buf.length = buflength;
queue->buffer[i].buf.type = queue->type;
queue->buffer[i].buf.sequence = 0;
queue->buffer[i].buf.field = V4L2_FIELD_NONE;
queue->buffer[i].buf.memory = V4L2_MEMORY_MMAP;
queue->buffer[i].buf.flags = 0;
init_waitqueue_head(&queue->buffer[i].wait);
}
queue->mem = mem;
queue->count = nbuffers;
queue->buf_size = bufsize;
ret = nbuffers;
done:
mutex_unlock(&queue->mutex);
return ret;
}
static void __uvc_query_buffer(struct uvc_buffer *buf,
struct v4l2_buffer *v4l2_buf)
{
memcpy(v4l2_buf, &buf->buf, sizeof *v4l2_buf);
if (buf->vma_use_count)
v4l2_buf->flags |= V4L2_BUF_FLAG_MAPPED;
switch (buf->state) {
case UVC_BUF_STATE_ERROR:
case UVC_BUF_STATE_DONE:
v4l2_buf->flags |= V4L2_BUF_FLAG_DONE;
break;
case UVC_BUF_STATE_QUEUED:
case UVC_BUF_STATE_ACTIVE:
v4l2_buf->flags |= V4L2_BUF_FLAG_QUEUED;
break;
case UVC_BUF_STATE_IDLE:
default:
break;
}
}
static int
uvc_query_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf)
{
int ret = 0;
mutex_lock(&queue->mutex);
if (v4l2_buf->index >= queue->count) {
ret = -EINVAL;
goto done;
}
__uvc_query_buffer(&queue->buffer[v4l2_buf->index], v4l2_buf);
done:
mutex_unlock(&queue->mutex);
return ret;
}
/*
* Queue a video buffer. Attempting to queue a buffer that has already been
* queued will return -EINVAL.
*/
static int
uvc_queue_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf)
{
struct uvc_buffer *buf;
unsigned long flags;
int ret = 0;
uvc_trace(UVC_TRACE_CAPTURE, "Queuing buffer %u.\n", v4l2_buf->index);
if (v4l2_buf->type != queue->type ||
v4l2_buf->memory != V4L2_MEMORY_MMAP) {
uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer type (%u) "
"and/or memory (%u).\n", v4l2_buf->type,
v4l2_buf->memory);
return -EINVAL;
}
mutex_lock(&queue->mutex);
if (v4l2_buf->index >= queue->count) {
uvc_trace(UVC_TRACE_CAPTURE, "[E] Out of range index.\n");
ret = -EINVAL;
goto done;
}
buf = &queue->buffer[v4l2_buf->index];
if (buf->state != UVC_BUF_STATE_IDLE) {
uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer state "
"(%u).\n", buf->state);
ret = -EINVAL;
goto done;
}
if (v4l2_buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT &&
v4l2_buf->bytesused > buf->buf.length) {
uvc_trace(UVC_TRACE_CAPTURE, "[E] Bytes used out of bounds.\n");
ret = -EINVAL;
goto done;
}
if (v4l2_buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
buf->buf.bytesused = 0;
else
buf->buf.bytesused = v4l2_buf->bytesused;
spin_lock_irqsave(&queue->irqlock, flags);
if (queue->flags & UVC_QUEUE_DISCONNECTED) {
spin_unlock_irqrestore(&queue->irqlock, flags);
ret = -ENODEV;
goto done;
}
buf->state = UVC_BUF_STATE_QUEUED;
ret = (queue->flags & UVC_QUEUE_PAUSED) != 0;
queue->flags &= ~UVC_QUEUE_PAUSED;
list_add_tail(&buf->stream, &queue->mainqueue);
list_add_tail(&buf->queue, &queue->irqqueue);
spin_unlock_irqrestore(&queue->irqlock, flags);
done:
mutex_unlock(&queue->mutex);
return ret;
}
static int uvc_queue_waiton(struct uvc_buffer *buf, int nonblocking)
{
if (nonblocking) {
return (buf->state != UVC_BUF_STATE_QUEUED &&
buf->state != UVC_BUF_STATE_ACTIVE)
? 0 : -EAGAIN;
}
return wait_event_interruptible(buf->wait,
buf->state != UVC_BUF_STATE_QUEUED &&
buf->state != UVC_BUF_STATE_ACTIVE);
}
/*
* Dequeue a video buffer. If nonblocking is false, block until a buffer is
* available.
*/
static int
uvc_dequeue_buffer(struct uvc_video_queue *queue, struct v4l2_buffer *v4l2_buf,
int nonblocking)
{
struct uvc_buffer *buf;
int ret = 0;
if (v4l2_buf->type != queue->type ||
v4l2_buf->memory != V4L2_MEMORY_MMAP) {
uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer type (%u) "
"and/or memory (%u).\n", v4l2_buf->type,
v4l2_buf->memory);
return -EINVAL;
}
mutex_lock(&queue->mutex);
if (list_empty(&queue->mainqueue)) {
uvc_trace(UVC_TRACE_CAPTURE, "[E] Empty buffer queue.\n");
ret = -EINVAL;
goto done;
}
buf = list_first_entry(&queue->mainqueue, struct uvc_buffer, stream);
if ((ret = uvc_queue_waiton(buf, nonblocking)) < 0)
goto done;
uvc_trace(UVC_TRACE_CAPTURE, "Dequeuing buffer %u (%u, %u bytes).\n",
buf->buf.index, buf->state, buf->buf.bytesused);
switch (buf->state) {
case UVC_BUF_STATE_ERROR:
uvc_trace(UVC_TRACE_CAPTURE, "[W] Corrupted data "
"(transmission error).\n");
ret = -EIO;
case UVC_BUF_STATE_DONE:
buf->state = UVC_BUF_STATE_IDLE;
break;
case UVC_BUF_STATE_IDLE:
case UVC_BUF_STATE_QUEUED:
case UVC_BUF_STATE_ACTIVE:
default:
uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer state %u "
"(driver bug?).\n", buf->state);
ret = -EINVAL;
goto done;
}
list_del(&buf->stream);
__uvc_query_buffer(buf, v4l2_buf);
done:
mutex_unlock(&queue->mutex);
return ret;
}
/*
* Poll the video queue.
*
* This function implements video queue polling and is intended to be used by
* the device poll handler.
*/
static unsigned int
uvc_queue_poll(struct uvc_video_queue *queue, struct file *file,
poll_table *wait)
{
struct uvc_buffer *buf;
unsigned int mask = 0;
mutex_lock(&queue->mutex);
if (list_empty(&queue->mainqueue))
goto done;
buf = list_first_entry(&queue->mainqueue, struct uvc_buffer, stream);
poll_wait(file, &buf->wait, wait);
if (buf->state == UVC_BUF_STATE_DONE ||
buf->state == UVC_BUF_STATE_ERROR)
mask |= POLLOUT | POLLWRNORM;
done:
mutex_unlock(&queue->mutex);
return mask;
}
/*
* VMA operations.
*/
static void uvc_vm_open(struct vm_area_struct *vma)
{
struct uvc_buffer *buffer = vma->vm_private_data;
buffer->vma_use_count++;
}
static void uvc_vm_close(struct vm_area_struct *vma)
{
struct uvc_buffer *buffer = vma->vm_private_data;
buffer->vma_use_count--;
}
static struct vm_operations_struct uvc_vm_ops = {
.open = uvc_vm_open,
.close = uvc_vm_close,
};
/*
* Memory-map a buffer.
*
* This function implements video buffer memory mapping and is intended to be
* used by the device mmap handler.
*/
static int
uvc_queue_mmap(struct uvc_video_queue *queue, struct vm_area_struct *vma)
{
struct uvc_buffer *uninitialized_var(buffer);
struct page *page;
unsigned long addr, start, size;
unsigned int i;
int ret = 0;
start = vma->vm_start;
size = vma->vm_end - vma->vm_start;
mutex_lock(&queue->mutex);
for (i = 0; i < queue->count; ++i) {
buffer = &queue->buffer[i];
if ((buffer->buf.m.offset >> PAGE_SHIFT) == vma->vm_pgoff)
break;
}
if (i == queue->count || size != queue->buf_size) {
ret = -EINVAL;
goto done;
}
/*
* VM_IO marks the area as being an mmaped region for I/O to a
* device. It also prevents the region from being core dumped.
*/
vma->vm_flags |= VM_IO;
addr = (unsigned long)queue->mem + buffer->buf.m.offset;
while (size > 0) {
page = vmalloc_to_page((void *)addr);
if ((ret = vm_insert_page(vma, start, page)) < 0)
goto done;
start += PAGE_SIZE;
addr += PAGE_SIZE;
size -= PAGE_SIZE;
}
vma->vm_ops = &uvc_vm_ops;
vma->vm_private_data = buffer;
uvc_vm_open(vma);
done:
mutex_unlock(&queue->mutex);
return ret;
}
/*
* Cancel the video buffers queue.
*
* Cancelling the queue marks all buffers on the irq queue as erroneous,
* wakes them up and removes them from the queue.
*
* If the disconnect parameter is set, further calls to uvc_queue_buffer will
* fail with -ENODEV.
*
* This function acquires the irq spinlock and can be called from interrupt
* context.
*/
static void uvc_queue_cancel(struct uvc_video_queue *queue, int disconnect)
{
struct uvc_buffer *buf;
unsigned long flags;
spin_lock_irqsave(&queue->irqlock, flags);
while (!list_empty(&queue->irqqueue)) {
buf = list_first_entry(&queue->irqqueue, struct uvc_buffer,
queue);
list_del(&buf->queue);
buf->state = UVC_BUF_STATE_ERROR;
wake_up(&buf->wait);
}
/* This must be protected by the irqlock spinlock to avoid race
* conditions between uvc_queue_buffer and the disconnection event that
* could result in an interruptible wait in uvc_dequeue_buffer. Do not
* blindly replace this logic by checking for the UVC_DEV_DISCONNECTED
* state outside the queue code.
*/
if (disconnect)
queue->flags |= UVC_QUEUE_DISCONNECTED;
spin_unlock_irqrestore(&queue->irqlock, flags);
}
/*
* Enable or disable the video buffers queue.
*
* The queue must be enabled before starting video acquisition and must be
* disabled after stopping it. This ensures that the video buffers queue
* state can be properly initialized before buffers are accessed from the
* interrupt handler.
*
* Enabling the video queue initializes parameters (such as sequence number,
* sync pattern, ...). If the queue is already enabled, return -EBUSY.
*
* Disabling the video queue cancels the queue and removes all buffers from
* the main queue.
*
* This function can't be called from interrupt context. Use
* uvc_queue_cancel() instead.
*/
static int uvc_queue_enable(struct uvc_video_queue *queue, int enable)
{
unsigned int i;
int ret = 0;
mutex_lock(&queue->mutex);
if (enable) {
if (uvc_queue_streaming(queue)) {
ret = -EBUSY;
goto done;
}
queue->sequence = 0;
queue->flags |= UVC_QUEUE_STREAMING;
queue->buf_used = 0;
} else {
uvc_queue_cancel(queue, 0);
INIT_LIST_HEAD(&queue->mainqueue);
for (i = 0; i < queue->count; ++i)
queue->buffer[i].state = UVC_BUF_STATE_IDLE;
queue->flags &= ~UVC_QUEUE_STREAMING;
}
done:
mutex_unlock(&queue->mutex);
return ret;
}
/* called with queue->irqlock held.. */
static struct uvc_buffer *
uvc_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *buf)
{
struct uvc_buffer *nextbuf;
if ((queue->flags & UVC_QUEUE_DROP_INCOMPLETE) &&
buf->buf.length != buf->buf.bytesused) {
buf->state = UVC_BUF_STATE_QUEUED;
buf->buf.bytesused = 0;
return buf;
}
list_del(&buf->queue);
if (!list_empty(&queue->irqqueue))
nextbuf = list_first_entry(&queue->irqqueue, struct uvc_buffer,
queue);
else
nextbuf = NULL;
buf->buf.sequence = queue->sequence++;
do_gettimeofday(&buf->buf.timestamp);
wake_up(&buf->wait);
return nextbuf;
}
static struct uvc_buffer *uvc_queue_head(struct uvc_video_queue *queue)
{
struct uvc_buffer *buf = NULL;
if (!list_empty(&queue->irqqueue))
buf = list_first_entry(&queue->irqqueue, struct uvc_buffer,
queue);
else
queue->flags |= UVC_QUEUE_PAUSED;
return buf;
}
| gpl-2.0 |
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