repo_name string | path string | copies string | size string | content string | license string |
|---|---|---|---|---|---|
andr00ib/kernel_v30c | drivers/message/fusion/mptspi.c | 8017 | 43777 | /*
* linux/drivers/message/fusion/mptspi.c
* For use with LSI PCI chip/adapter(s)
* running LSI Fusion MPT (Message Passing Technology) firmware.
*
* Copyright (c) 1999-2008 LSI Corporation
* (mailto:DL-MPTFusionLinux@lsi.com)
*
*/
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; version 2 of the License.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
NO WARRANTY
THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
solely responsible for determining the appropriateness of using and
distributing the Program and assumes all risks associated with its
exercise of rights under this Agreement, including but not limited to
the risks and costs of program errors, damage to or loss of data,
programs or equipment, and unavailability or interruption of operations.
DISCLAIMER OF LIABILITY
NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/kdev_t.h>
#include <linux/blkdev.h>
#include <linux/delay.h> /* for mdelay */
#include <linux/interrupt.h> /* needed for in_interrupt() proto */
#include <linux/reboot.h> /* notifier code */
#include <linux/workqueue.h>
#include <linux/raid_class.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_tcq.h>
#include <scsi/scsi_transport.h>
#include <scsi/scsi_transport_spi.h>
#include <scsi/scsi_dbg.h>
#include "mptbase.h"
#include "mptscsih.h"
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
#define my_NAME "Fusion MPT SPI Host driver"
#define my_VERSION MPT_LINUX_VERSION_COMMON
#define MYNAM "mptspi"
MODULE_AUTHOR(MODULEAUTHOR);
MODULE_DESCRIPTION(my_NAME);
MODULE_LICENSE("GPL");
MODULE_VERSION(my_VERSION);
/* Command line args */
static int mpt_saf_te = MPTSCSIH_SAF_TE;
module_param(mpt_saf_te, int, 0);
MODULE_PARM_DESC(mpt_saf_te, " Force enabling SEP Processor: enable=1 (default=MPTSCSIH_SAF_TE=0)");
static void mptspi_write_offset(struct scsi_target *, int);
static void mptspi_write_width(struct scsi_target *, int);
static int mptspi_write_spi_device_pg1(struct scsi_target *,
struct _CONFIG_PAGE_SCSI_DEVICE_1 *);
static struct scsi_transport_template *mptspi_transport_template = NULL;
static u8 mptspiDoneCtx = MPT_MAX_PROTOCOL_DRIVERS;
static u8 mptspiTaskCtx = MPT_MAX_PROTOCOL_DRIVERS;
static u8 mptspiInternalCtx = MPT_MAX_PROTOCOL_DRIVERS; /* Used only for internal commands */
/**
* mptspi_setTargetNegoParms - Update the target negotiation parameters
* @hd: Pointer to a SCSI Host Structure
* @target: per target private data
* @sdev: SCSI device
*
* Update the target negotiation parameters based on the the Inquiry
* data, adapter capabilities, and NVRAM settings.
**/
static void
mptspi_setTargetNegoParms(MPT_SCSI_HOST *hd, VirtTarget *target,
struct scsi_device *sdev)
{
MPT_ADAPTER *ioc = hd->ioc;
SpiCfgData *pspi_data = &ioc->spi_data;
int id = (int) target->id;
int nvram;
u8 width = MPT_NARROW;
u8 factor = MPT_ASYNC;
u8 offset = 0;
u8 nfactor;
u8 noQas = 1;
target->negoFlags = pspi_data->noQas;
if (sdev->scsi_level < SCSI_2) {
width = 0;
factor = MPT_ULTRA2;
offset = pspi_data->maxSyncOffset;
target->tflags &= ~MPT_TARGET_FLAGS_Q_YES;
} else {
if (scsi_device_wide(sdev))
width = 1;
if (scsi_device_sync(sdev)) {
factor = pspi_data->minSyncFactor;
if (!scsi_device_dt(sdev))
factor = MPT_ULTRA2;
else {
if (!scsi_device_ius(sdev) &&
!scsi_device_qas(sdev))
factor = MPT_ULTRA160;
else {
factor = MPT_ULTRA320;
if (scsi_device_qas(sdev)) {
ddvprintk(ioc,
printk(MYIOC_s_DEBUG_FMT "Enabling QAS due to "
"byte56=%02x on id=%d!\n", ioc->name,
scsi_device_qas(sdev), id));
noQas = 0;
}
if (sdev->type == TYPE_TAPE &&
scsi_device_ius(sdev))
target->negoFlags |= MPT_TAPE_NEGO_IDP;
}
}
offset = pspi_data->maxSyncOffset;
/* If RAID, never disable QAS
* else if non RAID, do not disable
* QAS if bit 1 is set
* bit 1 QAS support, non-raid only
* bit 0 IU support
*/
if (target->raidVolume == 1)
noQas = 0;
} else {
factor = MPT_ASYNC;
offset = 0;
}
}
if (!sdev->tagged_supported)
target->tflags &= ~MPT_TARGET_FLAGS_Q_YES;
/* Update tflags based on NVRAM settings. (SCSI only)
*/
if (pspi_data->nvram && (pspi_data->nvram[id] != MPT_HOST_NVRAM_INVALID)) {
nvram = pspi_data->nvram[id];
nfactor = (nvram & MPT_NVRAM_SYNC_MASK) >> 8;
if (width)
width = nvram & MPT_NVRAM_WIDE_DISABLE ? 0 : 1;
if (offset > 0) {
/* Ensure factor is set to the
* maximum of: adapter, nvram, inquiry
*/
if (nfactor) {
if (nfactor < pspi_data->minSyncFactor )
nfactor = pspi_data->minSyncFactor;
factor = max(factor, nfactor);
if (factor == MPT_ASYNC)
offset = 0;
} else {
offset = 0;
factor = MPT_ASYNC;
}
} else {
factor = MPT_ASYNC;
}
}
/* Make sure data is consistent
*/
if ((!width) && (factor < MPT_ULTRA2))
factor = MPT_ULTRA2;
/* Save the data to the target structure.
*/
target->minSyncFactor = factor;
target->maxOffset = offset;
target->maxWidth = width;
spi_min_period(scsi_target(sdev)) = factor;
spi_max_offset(scsi_target(sdev)) = offset;
spi_max_width(scsi_target(sdev)) = width;
target->tflags |= MPT_TARGET_FLAGS_VALID_NEGO;
/* Disable unused features.
*/
if (!width)
target->negoFlags |= MPT_TARGET_NO_NEGO_WIDE;
if (!offset)
target->negoFlags |= MPT_TARGET_NO_NEGO_SYNC;
if ( factor > MPT_ULTRA320 )
noQas = 0;
if (noQas && (pspi_data->noQas == 0)) {
pspi_data->noQas |= MPT_TARGET_NO_NEGO_QAS;
target->negoFlags |= MPT_TARGET_NO_NEGO_QAS;
/* Disable QAS in a mixed configuration case
*/
ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
"Disabling QAS due to noQas=%02x on id=%d!\n", ioc->name, noQas, id));
}
}
/**
* mptspi_writeIOCPage4 - write IOC Page 4
* @hd: Pointer to a SCSI Host Structure
* @channel: channel number
* @id: write IOC Page4 for this ID & Bus
*
* Return: -EAGAIN if unable to obtain a Message Frame
* or 0 if success.
*
* Remark: We do not wait for a return, write pages sequentially.
**/
static int
mptspi_writeIOCPage4(MPT_SCSI_HOST *hd, u8 channel , u8 id)
{
MPT_ADAPTER *ioc = hd->ioc;
Config_t *pReq;
IOCPage4_t *IOCPage4Ptr;
MPT_FRAME_HDR *mf;
dma_addr_t dataDma;
u16 req_idx;
u32 frameOffset;
u32 flagsLength;
int ii;
/* Get a MF for this command.
*/
if ((mf = mpt_get_msg_frame(ioc->DoneCtx, ioc)) == NULL) {
dfailprintk(ioc, printk(MYIOC_s_WARN_FMT
"writeIOCPage4 : no msg frames!\n",ioc->name));
return -EAGAIN;
}
/* Set the request and the data pointers.
* Place data at end of MF.
*/
pReq = (Config_t *)mf;
req_idx = le16_to_cpu(mf->u.frame.hwhdr.msgctxu.fld.req_idx);
frameOffset = ioc->req_sz - sizeof(IOCPage4_t);
/* Complete the request frame (same for all requests).
*/
pReq->Action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
pReq->Reserved = 0;
pReq->ChainOffset = 0;
pReq->Function = MPI_FUNCTION_CONFIG;
pReq->ExtPageLength = 0;
pReq->ExtPageType = 0;
pReq->MsgFlags = 0;
for (ii=0; ii < 8; ii++) {
pReq->Reserved2[ii] = 0;
}
IOCPage4Ptr = ioc->spi_data.pIocPg4;
dataDma = ioc->spi_data.IocPg4_dma;
ii = IOCPage4Ptr->ActiveSEP++;
IOCPage4Ptr->SEP[ii].SEPTargetID = id;
IOCPage4Ptr->SEP[ii].SEPBus = channel;
pReq->Header = IOCPage4Ptr->Header;
pReq->PageAddress = cpu_to_le32(id | (channel << 8 ));
/* Add a SGE to the config request.
*/
flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE |
(IOCPage4Ptr->Header.PageLength + ii) * 4;
ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, dataDma);
ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
"writeIOCPage4: MaxSEP=%d ActiveSEP=%d id=%d bus=%d\n",
ioc->name, IOCPage4Ptr->MaxSEP, IOCPage4Ptr->ActiveSEP, id, channel));
mpt_put_msg_frame(ioc->DoneCtx, ioc, mf);
return 0;
}
/**
* mptspi_initTarget - Target, LUN alloc/free functionality.
* @hd: Pointer to MPT_SCSI_HOST structure
* @vtarget: per target private data
* @sdev: SCSI device
*
* NOTE: It's only SAFE to call this routine if data points to
* sane & valid STANDARD INQUIRY data!
*
* Allocate and initialize memory for this target.
* Save inquiry data.
*
**/
static void
mptspi_initTarget(MPT_SCSI_HOST *hd, VirtTarget *vtarget,
struct scsi_device *sdev)
{
/* Is LUN supported? If so, upper 2 bits will be 0
* in first byte of inquiry data.
*/
if (sdev->inq_periph_qual != 0)
return;
if (vtarget == NULL)
return;
vtarget->type = sdev->type;
if ((sdev->type == TYPE_PROCESSOR) && (hd->ioc->spi_data.Saf_Te)) {
/* Treat all Processors as SAF-TE if
* command line option is set */
vtarget->tflags |= MPT_TARGET_FLAGS_SAF_TE_ISSUED;
mptspi_writeIOCPage4(hd, vtarget->channel, vtarget->id);
}else if ((sdev->type == TYPE_PROCESSOR) &&
!(vtarget->tflags & MPT_TARGET_FLAGS_SAF_TE_ISSUED )) {
if (sdev->inquiry_len > 49 ) {
if (sdev->inquiry[44] == 'S' &&
sdev->inquiry[45] == 'A' &&
sdev->inquiry[46] == 'F' &&
sdev->inquiry[47] == '-' &&
sdev->inquiry[48] == 'T' &&
sdev->inquiry[49] == 'E' ) {
vtarget->tflags |= MPT_TARGET_FLAGS_SAF_TE_ISSUED;
mptspi_writeIOCPage4(hd, vtarget->channel, vtarget->id);
}
}
}
mptspi_setTargetNegoParms(hd, vtarget, sdev);
}
/**
* mptspi_is_raid - Determines whether target is belonging to volume
* @hd: Pointer to a SCSI HOST structure
* @id: target device id
*
* Return:
* non-zero = true
* zero = false
*
*/
static int
mptspi_is_raid(struct _MPT_SCSI_HOST *hd, u32 id)
{
int i, rc = 0;
MPT_ADAPTER *ioc = hd->ioc;
if (!ioc->raid_data.pIocPg2)
goto out;
if (!ioc->raid_data.pIocPg2->NumActiveVolumes)
goto out;
for (i=0; i < ioc->raid_data.pIocPg2->NumActiveVolumes; i++) {
if (ioc->raid_data.pIocPg2->RaidVolume[i].VolumeID == id) {
rc = 1;
goto out;
}
}
out:
return rc;
}
static int mptspi_target_alloc(struct scsi_target *starget)
{
struct Scsi_Host *shost = dev_to_shost(&starget->dev);
struct _MPT_SCSI_HOST *hd = shost_priv(shost);
VirtTarget *vtarget;
MPT_ADAPTER *ioc;
if (hd == NULL)
return -ENODEV;
ioc = hd->ioc;
vtarget = kzalloc(sizeof(VirtTarget), GFP_KERNEL);
if (!vtarget)
return -ENOMEM;
vtarget->ioc_id = ioc->id;
vtarget->tflags = MPT_TARGET_FLAGS_Q_YES;
vtarget->id = (u8)starget->id;
vtarget->channel = (u8)starget->channel;
vtarget->starget = starget;
starget->hostdata = vtarget;
if (starget->channel == 1) {
if (mptscsih_is_phys_disk(ioc, 0, starget->id) == 0)
return 0;
vtarget->tflags |= MPT_TARGET_FLAGS_RAID_COMPONENT;
/* The real channel for this device is zero */
vtarget->channel = 0;
/* The actual physdisknum (for RAID passthrough) */
vtarget->id = mptscsih_raid_id_to_num(ioc, 0,
starget->id);
}
if (starget->channel == 0 &&
mptspi_is_raid(hd, starget->id)) {
vtarget->raidVolume = 1;
ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
"RAID Volume @ channel=%d id=%d\n", ioc->name, starget->channel,
starget->id));
}
if (ioc->spi_data.nvram &&
ioc->spi_data.nvram[starget->id] != MPT_HOST_NVRAM_INVALID) {
u32 nvram = ioc->spi_data.nvram[starget->id];
spi_min_period(starget) = (nvram & MPT_NVRAM_SYNC_MASK) >> MPT_NVRAM_SYNC_SHIFT;
spi_max_width(starget) = nvram & MPT_NVRAM_WIDE_DISABLE ? 0 : 1;
} else {
spi_min_period(starget) = ioc->spi_data.minSyncFactor;
spi_max_width(starget) = ioc->spi_data.maxBusWidth;
}
spi_max_offset(starget) = ioc->spi_data.maxSyncOffset;
spi_offset(starget) = 0;
spi_period(starget) = 0xFF;
mptspi_write_width(starget, 0);
return 0;
}
static void
mptspi_target_destroy(struct scsi_target *starget)
{
if (starget->hostdata)
kfree(starget->hostdata);
starget->hostdata = NULL;
}
/**
* mptspi_print_write_nego - negotiation parameters debug info that is being sent
* @hd: Pointer to a SCSI HOST structure
* @starget: SCSI target
* @ii: negotiation parameters
*
*/
static void
mptspi_print_write_nego(struct _MPT_SCSI_HOST *hd, struct scsi_target *starget, u32 ii)
{
ddvprintk(hd->ioc, printk(MYIOC_s_DEBUG_FMT "id=%d Requested = 0x%08x"
" ( %s factor = 0x%02x @ offset = 0x%02x %s%s%s%s%s%s%s%s)\n",
hd->ioc->name, starget->id, ii,
ii & MPI_SCSIDEVPAGE0_NP_WIDE ? "Wide ": "",
((ii >> 8) & 0xFF), ((ii >> 16) & 0xFF),
ii & MPI_SCSIDEVPAGE0_NP_IU ? "IU ": "",
ii & MPI_SCSIDEVPAGE0_NP_DT ? "DT ": "",
ii & MPI_SCSIDEVPAGE0_NP_QAS ? "QAS ": "",
ii & MPI_SCSIDEVPAGE0_NP_HOLD_MCS ? "HOLDMCS ": "",
ii & MPI_SCSIDEVPAGE0_NP_WR_FLOW ? "WRFLOW ": "",
ii & MPI_SCSIDEVPAGE0_NP_RD_STRM ? "RDSTRM ": "",
ii & MPI_SCSIDEVPAGE0_NP_RTI ? "RTI ": "",
ii & MPI_SCSIDEVPAGE0_NP_PCOMP_EN ? "PCOMP ": ""));
}
/**
* mptspi_print_read_nego - negotiation parameters debug info that is being read
* @hd: Pointer to a SCSI HOST structure
* @starget: SCSI target
* @ii: negotiation parameters
*
*/
static void
mptspi_print_read_nego(struct _MPT_SCSI_HOST *hd, struct scsi_target *starget, u32 ii)
{
ddvprintk(hd->ioc, printk(MYIOC_s_DEBUG_FMT "id=%d Read = 0x%08x"
" ( %s factor = 0x%02x @ offset = 0x%02x %s%s%s%s%s%s%s%s)\n",
hd->ioc->name, starget->id, ii,
ii & MPI_SCSIDEVPAGE0_NP_WIDE ? "Wide ": "",
((ii >> 8) & 0xFF), ((ii >> 16) & 0xFF),
ii & MPI_SCSIDEVPAGE0_NP_IU ? "IU ": "",
ii & MPI_SCSIDEVPAGE0_NP_DT ? "DT ": "",
ii & MPI_SCSIDEVPAGE0_NP_QAS ? "QAS ": "",
ii & MPI_SCSIDEVPAGE0_NP_HOLD_MCS ? "HOLDMCS ": "",
ii & MPI_SCSIDEVPAGE0_NP_WR_FLOW ? "WRFLOW ": "",
ii & MPI_SCSIDEVPAGE0_NP_RD_STRM ? "RDSTRM ": "",
ii & MPI_SCSIDEVPAGE0_NP_RTI ? "RTI ": "",
ii & MPI_SCSIDEVPAGE0_NP_PCOMP_EN ? "PCOMP ": ""));
}
static int mptspi_read_spi_device_pg0(struct scsi_target *starget,
struct _CONFIG_PAGE_SCSI_DEVICE_0 *pass_pg0)
{
struct Scsi_Host *shost = dev_to_shost(&starget->dev);
struct _MPT_SCSI_HOST *hd = shost_priv(shost);
struct _MPT_ADAPTER *ioc = hd->ioc;
struct _CONFIG_PAGE_SCSI_DEVICE_0 *spi_dev_pg0;
dma_addr_t spi_dev_pg0_dma;
int size;
struct _x_config_parms cfg;
struct _CONFIG_PAGE_HEADER hdr;
int err = -EBUSY;
/* No SPI parameters for RAID devices */
if (starget->channel == 0 &&
mptspi_is_raid(hd, starget->id))
return -1;
size = ioc->spi_data.sdp0length * 4;
/*
if (ioc->spi_data.sdp0length & 1)
size += size + 4;
size += 2048;
*/
spi_dev_pg0 = dma_alloc_coherent(&ioc->pcidev->dev, size, &spi_dev_pg0_dma, GFP_KERNEL);
if (spi_dev_pg0 == NULL) {
starget_printk(KERN_ERR, starget, MYIOC_s_FMT
"dma_alloc_coherent for parameters failed\n", ioc->name);
return -EINVAL;
}
memset(&hdr, 0, sizeof(hdr));
hdr.PageVersion = ioc->spi_data.sdp0version;
hdr.PageLength = ioc->spi_data.sdp0length;
hdr.PageNumber = 0;
hdr.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
memset(&cfg, 0, sizeof(cfg));
cfg.cfghdr.hdr = &hdr;
cfg.physAddr = spi_dev_pg0_dma;
cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
cfg.dir = 0;
cfg.pageAddr = starget->id;
cfg.timeout = 60;
if (mpt_config(ioc, &cfg)) {
starget_printk(KERN_ERR, starget, MYIOC_s_FMT "mpt_config failed\n", ioc->name);
goto out_free;
}
err = 0;
memcpy(pass_pg0, spi_dev_pg0, size);
mptspi_print_read_nego(hd, starget, le32_to_cpu(spi_dev_pg0->NegotiatedParameters));
out_free:
dma_free_coherent(&ioc->pcidev->dev, size, spi_dev_pg0, spi_dev_pg0_dma);
return err;
}
static u32 mptspi_getRP(struct scsi_target *starget)
{
u32 nego = 0;
nego |= spi_iu(starget) ? MPI_SCSIDEVPAGE1_RP_IU : 0;
nego |= spi_dt(starget) ? MPI_SCSIDEVPAGE1_RP_DT : 0;
nego |= spi_qas(starget) ? MPI_SCSIDEVPAGE1_RP_QAS : 0;
nego |= spi_hold_mcs(starget) ? MPI_SCSIDEVPAGE1_RP_HOLD_MCS : 0;
nego |= spi_wr_flow(starget) ? MPI_SCSIDEVPAGE1_RP_WR_FLOW : 0;
nego |= spi_rd_strm(starget) ? MPI_SCSIDEVPAGE1_RP_RD_STRM : 0;
nego |= spi_rti(starget) ? MPI_SCSIDEVPAGE1_RP_RTI : 0;
nego |= spi_pcomp_en(starget) ? MPI_SCSIDEVPAGE1_RP_PCOMP_EN : 0;
nego |= (spi_period(starget) << MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD) & MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK;
nego |= (spi_offset(starget) << MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET) & MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK;
nego |= spi_width(starget) ? MPI_SCSIDEVPAGE1_RP_WIDE : 0;
return nego;
}
static void mptspi_read_parameters(struct scsi_target *starget)
{
int nego;
struct _CONFIG_PAGE_SCSI_DEVICE_0 spi_dev_pg0;
mptspi_read_spi_device_pg0(starget, &spi_dev_pg0);
nego = le32_to_cpu(spi_dev_pg0.NegotiatedParameters);
spi_iu(starget) = (nego & MPI_SCSIDEVPAGE0_NP_IU) ? 1 : 0;
spi_dt(starget) = (nego & MPI_SCSIDEVPAGE0_NP_DT) ? 1 : 0;
spi_qas(starget) = (nego & MPI_SCSIDEVPAGE0_NP_QAS) ? 1 : 0;
spi_wr_flow(starget) = (nego & MPI_SCSIDEVPAGE0_NP_WR_FLOW) ? 1 : 0;
spi_rd_strm(starget) = (nego & MPI_SCSIDEVPAGE0_NP_RD_STRM) ? 1 : 0;
spi_rti(starget) = (nego & MPI_SCSIDEVPAGE0_NP_RTI) ? 1 : 0;
spi_pcomp_en(starget) = (nego & MPI_SCSIDEVPAGE0_NP_PCOMP_EN) ? 1 : 0;
spi_hold_mcs(starget) = (nego & MPI_SCSIDEVPAGE0_NP_HOLD_MCS) ? 1 : 0;
spi_period(starget) = (nego & MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK) >> MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD;
spi_offset(starget) = (nego & MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK) >> MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET;
spi_width(starget) = (nego & MPI_SCSIDEVPAGE0_NP_WIDE) ? 1 : 0;
}
int
mptscsih_quiesce_raid(MPT_SCSI_HOST *hd, int quiesce, u8 channel, u8 id)
{
MPT_ADAPTER *ioc = hd->ioc;
MpiRaidActionRequest_t *pReq;
MPT_FRAME_HDR *mf;
int ret;
unsigned long timeleft;
mutex_lock(&ioc->internal_cmds.mutex);
/* Get and Populate a free Frame
*/
if ((mf = mpt_get_msg_frame(ioc->InternalCtx, ioc)) == NULL) {
dfailprintk(hd->ioc, printk(MYIOC_s_WARN_FMT
"%s: no msg frames!\n", ioc->name, __func__));
ret = -EAGAIN;
goto out;
}
pReq = (MpiRaidActionRequest_t *)mf;
if (quiesce)
pReq->Action = MPI_RAID_ACTION_QUIESCE_PHYS_IO;
else
pReq->Action = MPI_RAID_ACTION_ENABLE_PHYS_IO;
pReq->Reserved1 = 0;
pReq->ChainOffset = 0;
pReq->Function = MPI_FUNCTION_RAID_ACTION;
pReq->VolumeID = id;
pReq->VolumeBus = channel;
pReq->PhysDiskNum = 0;
pReq->MsgFlags = 0;
pReq->Reserved2 = 0;
pReq->ActionDataWord = 0; /* Reserved for this action */
ioc->add_sge((char *)&pReq->ActionDataSGE,
MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1);
ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RAID Volume action=%x channel=%d id=%d\n",
ioc->name, pReq->Action, channel, id));
INITIALIZE_MGMT_STATUS(ioc->internal_cmds.status)
mpt_put_msg_frame(ioc->InternalCtx, ioc, mf);
timeleft = wait_for_completion_timeout(&ioc->internal_cmds.done, 10*HZ);
if (!(ioc->internal_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
ret = -ETIME;
dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT "%s: TIMED OUT!\n",
ioc->name, __func__));
if (ioc->internal_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
goto out;
if (!timeleft) {
printk(MYIOC_s_WARN_FMT "Issuing Reset from %s!!\n",
ioc->name, __func__);
mpt_HardResetHandler(ioc, CAN_SLEEP);
mpt_free_msg_frame(ioc, mf);
}
goto out;
}
ret = ioc->internal_cmds.completion_code;
out:
CLEAR_MGMT_STATUS(ioc->internal_cmds.status)
mutex_unlock(&ioc->internal_cmds.mutex);
return ret;
}
static void mptspi_dv_device(struct _MPT_SCSI_HOST *hd,
struct scsi_device *sdev)
{
VirtTarget *vtarget = scsi_target(sdev)->hostdata;
MPT_ADAPTER *ioc = hd->ioc;
/* no DV on RAID devices */
if (sdev->channel == 0 &&
mptspi_is_raid(hd, sdev->id))
return;
/* If this is a piece of a RAID, then quiesce first */
if (sdev->channel == 1 &&
mptscsih_quiesce_raid(hd, 1, vtarget->channel, vtarget->id) < 0) {
starget_printk(KERN_ERR, scsi_target(sdev), MYIOC_s_FMT
"Integrated RAID quiesce failed\n", ioc->name);
return;
}
hd->spi_pending |= (1 << sdev->id);
spi_dv_device(sdev);
hd->spi_pending &= ~(1 << sdev->id);
if (sdev->channel == 1 &&
mptscsih_quiesce_raid(hd, 0, vtarget->channel, vtarget->id) < 0)
starget_printk(KERN_ERR, scsi_target(sdev), MYIOC_s_FMT
"Integrated RAID resume failed\n", ioc->name);
mptspi_read_parameters(sdev->sdev_target);
spi_display_xfer_agreement(sdev->sdev_target);
mptspi_read_parameters(sdev->sdev_target);
}
static int mptspi_slave_alloc(struct scsi_device *sdev)
{
MPT_SCSI_HOST *hd = shost_priv(sdev->host);
VirtTarget *vtarget;
VirtDevice *vdevice;
struct scsi_target *starget;
MPT_ADAPTER *ioc = hd->ioc;
if (sdev->channel == 1 &&
mptscsih_is_phys_disk(ioc, 0, sdev->id) == 0)
return -ENXIO;
vdevice = kzalloc(sizeof(VirtDevice), GFP_KERNEL);
if (!vdevice) {
printk(MYIOC_s_ERR_FMT "slave_alloc kmalloc(%zd) FAILED!\n",
ioc->name, sizeof(VirtDevice));
return -ENOMEM;
}
vdevice->lun = sdev->lun;
sdev->hostdata = vdevice;
starget = scsi_target(sdev);
vtarget = starget->hostdata;
vdevice->vtarget = vtarget;
vtarget->num_luns++;
if (sdev->channel == 1)
sdev->no_uld_attach = 1;
return 0;
}
static int mptspi_slave_configure(struct scsi_device *sdev)
{
struct _MPT_SCSI_HOST *hd = shost_priv(sdev->host);
VirtTarget *vtarget = scsi_target(sdev)->hostdata;
int ret;
mptspi_initTarget(hd, vtarget, sdev);
ret = mptscsih_slave_configure(sdev);
if (ret)
return ret;
ddvprintk(hd->ioc, printk(MYIOC_s_DEBUG_FMT "id=%d min_period=0x%02x"
" max_offset=0x%02x max_width=%d\n", hd->ioc->name,
sdev->id, spi_min_period(scsi_target(sdev)),
spi_max_offset(scsi_target(sdev)),
spi_max_width(scsi_target(sdev))));
if ((sdev->channel == 1 ||
!(mptspi_is_raid(hd, sdev->id))) &&
!spi_initial_dv(sdev->sdev_target))
mptspi_dv_device(hd, sdev);
return 0;
}
static int
mptspi_qcmd_lck(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
{
struct _MPT_SCSI_HOST *hd = shost_priv(SCpnt->device->host);
VirtDevice *vdevice = SCpnt->device->hostdata;
MPT_ADAPTER *ioc = hd->ioc;
if (!vdevice || !vdevice->vtarget) {
SCpnt->result = DID_NO_CONNECT << 16;
done(SCpnt);
return 0;
}
if (SCpnt->device->channel == 1 &&
mptscsih_is_phys_disk(ioc, 0, SCpnt->device->id) == 0) {
SCpnt->result = DID_NO_CONNECT << 16;
done(SCpnt);
return 0;
}
if (spi_dv_pending(scsi_target(SCpnt->device)))
ddvprintk(ioc, scsi_print_command(SCpnt));
return mptscsih_qcmd(SCpnt,done);
}
static DEF_SCSI_QCMD(mptspi_qcmd)
static void mptspi_slave_destroy(struct scsi_device *sdev)
{
struct scsi_target *starget = scsi_target(sdev);
VirtTarget *vtarget = starget->hostdata;
VirtDevice *vdevice = sdev->hostdata;
/* Will this be the last lun on a non-raid device? */
if (vtarget->num_luns == 1 && vdevice->configured_lun) {
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
/* Async Narrow */
pg1.RequestedParameters = 0;
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
mptscsih_slave_destroy(sdev);
}
static struct scsi_host_template mptspi_driver_template = {
.module = THIS_MODULE,
.proc_name = "mptspi",
.proc_info = mptscsih_proc_info,
.name = "MPT SPI Host",
.info = mptscsih_info,
.queuecommand = mptspi_qcmd,
.target_alloc = mptspi_target_alloc,
.slave_alloc = mptspi_slave_alloc,
.slave_configure = mptspi_slave_configure,
.target_destroy = mptspi_target_destroy,
.slave_destroy = mptspi_slave_destroy,
.change_queue_depth = mptscsih_change_queue_depth,
.eh_abort_handler = mptscsih_abort,
.eh_device_reset_handler = mptscsih_dev_reset,
.eh_bus_reset_handler = mptscsih_bus_reset,
.eh_host_reset_handler = mptscsih_host_reset,
.bios_param = mptscsih_bios_param,
.can_queue = MPT_SCSI_CAN_QUEUE,
.this_id = -1,
.sg_tablesize = MPT_SCSI_SG_DEPTH,
.max_sectors = 8192,
.cmd_per_lun = 7,
.use_clustering = ENABLE_CLUSTERING,
.shost_attrs = mptscsih_host_attrs,
};
static int mptspi_write_spi_device_pg1(struct scsi_target *starget,
struct _CONFIG_PAGE_SCSI_DEVICE_1 *pass_pg1)
{
struct Scsi_Host *shost = dev_to_shost(&starget->dev);
struct _MPT_SCSI_HOST *hd = shost_priv(shost);
struct _MPT_ADAPTER *ioc = hd->ioc;
struct _CONFIG_PAGE_SCSI_DEVICE_1 *pg1;
dma_addr_t pg1_dma;
int size;
struct _x_config_parms cfg;
struct _CONFIG_PAGE_HEADER hdr;
int err = -EBUSY;
u32 nego_parms;
u32 period;
struct scsi_device *sdev;
int i;
/* don't allow updating nego parameters on RAID devices */
if (starget->channel == 0 &&
mptspi_is_raid(hd, starget->id))
return -1;
size = ioc->spi_data.sdp1length * 4;
pg1 = dma_alloc_coherent(&ioc->pcidev->dev, size, &pg1_dma, GFP_KERNEL);
if (pg1 == NULL) {
starget_printk(KERN_ERR, starget, MYIOC_s_FMT
"dma_alloc_coherent for parameters failed\n", ioc->name);
return -EINVAL;
}
memset(&hdr, 0, sizeof(hdr));
hdr.PageVersion = ioc->spi_data.sdp1version;
hdr.PageLength = ioc->spi_data.sdp1length;
hdr.PageNumber = 1;
hdr.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
memset(&cfg, 0, sizeof(cfg));
cfg.cfghdr.hdr = &hdr;
cfg.physAddr = pg1_dma;
cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
cfg.dir = 1;
cfg.pageAddr = starget->id;
memcpy(pg1, pass_pg1, size);
pg1->Header.PageVersion = hdr.PageVersion;
pg1->Header.PageLength = hdr.PageLength;
pg1->Header.PageNumber = hdr.PageNumber;
pg1->Header.PageType = hdr.PageType;
nego_parms = le32_to_cpu(pg1->RequestedParameters);
period = (nego_parms & MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK) >>
MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD;
if (period == 8) {
/* Turn on inline data padding for TAPE when running U320 */
for (i = 0 ; i < 16; i++) {
sdev = scsi_device_lookup_by_target(starget, i);
if (sdev && sdev->type == TYPE_TAPE) {
sdev_printk(KERN_DEBUG, sdev, MYIOC_s_FMT
"IDP:ON\n", ioc->name);
nego_parms |= MPI_SCSIDEVPAGE1_RP_IDP;
pg1->RequestedParameters =
cpu_to_le32(nego_parms);
break;
}
}
}
mptspi_print_write_nego(hd, starget, le32_to_cpu(pg1->RequestedParameters));
if (mpt_config(ioc, &cfg)) {
starget_printk(KERN_ERR, starget, MYIOC_s_FMT
"mpt_config failed\n", ioc->name);
goto out_free;
}
err = 0;
out_free:
dma_free_coherent(&ioc->pcidev->dev, size, pg1, pg1_dma);
return err;
}
static void mptspi_write_offset(struct scsi_target *starget, int offset)
{
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
u32 nego;
if (offset < 0)
offset = 0;
if (offset > 255)
offset = 255;
if (spi_offset(starget) == -1)
mptspi_read_parameters(starget);
spi_offset(starget) = offset;
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
static void mptspi_write_period(struct scsi_target *starget, int period)
{
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
u32 nego;
if (period < 8)
period = 8;
if (period > 255)
period = 255;
if (spi_period(starget) == -1)
mptspi_read_parameters(starget);
if (period == 8) {
spi_iu(starget) = 1;
spi_dt(starget) = 1;
} else if (period == 9) {
spi_dt(starget) = 1;
}
spi_period(starget) = period;
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
static void mptspi_write_dt(struct scsi_target *starget, int dt)
{
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
u32 nego;
if (spi_period(starget) == -1)
mptspi_read_parameters(starget);
if (!dt && spi_period(starget) < 10)
spi_period(starget) = 10;
spi_dt(starget) = dt;
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
static void mptspi_write_iu(struct scsi_target *starget, int iu)
{
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
u32 nego;
if (spi_period(starget) == -1)
mptspi_read_parameters(starget);
if (!iu && spi_period(starget) < 9)
spi_period(starget) = 9;
spi_iu(starget) = iu;
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
#define MPTSPI_SIMPLE_TRANSPORT_PARM(parm) \
static void mptspi_write_##parm(struct scsi_target *starget, int parm)\
{ \
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1; \
u32 nego; \
\
spi_##parm(starget) = parm; \
\
nego = mptspi_getRP(starget); \
\
pg1.RequestedParameters = cpu_to_le32(nego); \
pg1.Reserved = 0; \
pg1.Configuration = 0; \
\
mptspi_write_spi_device_pg1(starget, &pg1); \
}
MPTSPI_SIMPLE_TRANSPORT_PARM(rd_strm)
MPTSPI_SIMPLE_TRANSPORT_PARM(wr_flow)
MPTSPI_SIMPLE_TRANSPORT_PARM(rti)
MPTSPI_SIMPLE_TRANSPORT_PARM(hold_mcs)
MPTSPI_SIMPLE_TRANSPORT_PARM(pcomp_en)
static void mptspi_write_qas(struct scsi_target *starget, int qas)
{
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
struct Scsi_Host *shost = dev_to_shost(&starget->dev);
struct _MPT_SCSI_HOST *hd = shost_priv(shost);
VirtTarget *vtarget = starget->hostdata;
u32 nego;
if ((vtarget->negoFlags & MPT_TARGET_NO_NEGO_QAS) ||
hd->ioc->spi_data.noQas)
spi_qas(starget) = 0;
else
spi_qas(starget) = qas;
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
static void mptspi_write_width(struct scsi_target *starget, int width)
{
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
u32 nego;
if (!width) {
spi_dt(starget) = 0;
if (spi_period(starget) < 10)
spi_period(starget) = 10;
}
spi_width(starget) = width;
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
struct work_queue_wrapper {
struct work_struct work;
struct _MPT_SCSI_HOST *hd;
int disk;
};
static void mpt_work_wrapper(struct work_struct *work)
{
struct work_queue_wrapper *wqw =
container_of(work, struct work_queue_wrapper, work);
struct _MPT_SCSI_HOST *hd = wqw->hd;
MPT_ADAPTER *ioc = hd->ioc;
struct Scsi_Host *shost = ioc->sh;
struct scsi_device *sdev;
int disk = wqw->disk;
struct _CONFIG_PAGE_IOC_3 *pg3;
kfree(wqw);
mpt_findImVolumes(ioc);
pg3 = ioc->raid_data.pIocPg3;
if (!pg3)
return;
shost_for_each_device(sdev,shost) {
struct scsi_target *starget = scsi_target(sdev);
VirtTarget *vtarget = starget->hostdata;
/* only want to search RAID components */
if (sdev->channel != 1)
continue;
/* The id is the raid PhysDiskNum, even if
* starget->id is the actual target address */
if(vtarget->id != disk)
continue;
starget_printk(KERN_INFO, vtarget->starget, MYIOC_s_FMT
"Integrated RAID requests DV of new device\n", ioc->name);
mptspi_dv_device(hd, sdev);
}
shost_printk(KERN_INFO, shost, MYIOC_s_FMT
"Integrated RAID detects new device %d\n", ioc->name, disk);
scsi_scan_target(&ioc->sh->shost_gendev, 1, disk, 0, 1);
}
static void mpt_dv_raid(struct _MPT_SCSI_HOST *hd, int disk)
{
struct work_queue_wrapper *wqw = kmalloc(sizeof(*wqw), GFP_ATOMIC);
MPT_ADAPTER *ioc = hd->ioc;
if (!wqw) {
shost_printk(KERN_ERR, ioc->sh, MYIOC_s_FMT
"Failed to act on RAID event for physical disk %d\n",
ioc->name, disk);
return;
}
INIT_WORK(&wqw->work, mpt_work_wrapper);
wqw->hd = hd;
wqw->disk = disk;
schedule_work(&wqw->work);
}
static int
mptspi_event_process(MPT_ADAPTER *ioc, EventNotificationReply_t *pEvReply)
{
u8 event = le32_to_cpu(pEvReply->Event) & 0xFF;
struct _MPT_SCSI_HOST *hd = shost_priv(ioc->sh);
if (ioc->bus_type != SPI)
return 0;
if (hd && event == MPI_EVENT_INTEGRATED_RAID) {
int reason
= (le32_to_cpu(pEvReply->Data[0]) & 0x00FF0000) >> 16;
if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
int disk = (le32_to_cpu(pEvReply->Data[0]) & 0xFF000000) >> 24;
mpt_dv_raid(hd, disk);
}
}
return mptscsih_event_process(ioc, pEvReply);
}
static int
mptspi_deny_binding(struct scsi_target *starget)
{
struct _MPT_SCSI_HOST *hd =
(struct _MPT_SCSI_HOST *)dev_to_shost(starget->dev.parent)->hostdata;
return ((mptspi_is_raid(hd, starget->id)) &&
starget->channel == 0) ? 1 : 0;
}
static struct spi_function_template mptspi_transport_functions = {
.get_offset = mptspi_read_parameters,
.set_offset = mptspi_write_offset,
.show_offset = 1,
.get_period = mptspi_read_parameters,
.set_period = mptspi_write_period,
.show_period = 1,
.get_width = mptspi_read_parameters,
.set_width = mptspi_write_width,
.show_width = 1,
.get_iu = mptspi_read_parameters,
.set_iu = mptspi_write_iu,
.show_iu = 1,
.get_dt = mptspi_read_parameters,
.set_dt = mptspi_write_dt,
.show_dt = 1,
.get_qas = mptspi_read_parameters,
.set_qas = mptspi_write_qas,
.show_qas = 1,
.get_wr_flow = mptspi_read_parameters,
.set_wr_flow = mptspi_write_wr_flow,
.show_wr_flow = 1,
.get_rd_strm = mptspi_read_parameters,
.set_rd_strm = mptspi_write_rd_strm,
.show_rd_strm = 1,
.get_rti = mptspi_read_parameters,
.set_rti = mptspi_write_rti,
.show_rti = 1,
.get_pcomp_en = mptspi_read_parameters,
.set_pcomp_en = mptspi_write_pcomp_en,
.show_pcomp_en = 1,
.get_hold_mcs = mptspi_read_parameters,
.set_hold_mcs = mptspi_write_hold_mcs,
.show_hold_mcs = 1,
.deny_binding = mptspi_deny_binding,
};
/****************************************************************************
* Supported hardware
*/
static struct pci_device_id mptspi_pci_table[] = {
{ PCI_VENDOR_ID_LSI_LOGIC, MPI_MANUFACTPAGE_DEVID_53C1030,
PCI_ANY_ID, PCI_ANY_ID },
{ PCI_VENDOR_ID_ATTO, MPI_MANUFACTPAGE_DEVID_53C1030,
PCI_ANY_ID, PCI_ANY_ID },
{ PCI_VENDOR_ID_LSI_LOGIC, MPI_MANUFACTPAGE_DEVID_53C1035,
PCI_ANY_ID, PCI_ANY_ID },
{0} /* Terminating entry */
};
MODULE_DEVICE_TABLE(pci, mptspi_pci_table);
/*
* renegotiate for a given target
*/
static void
mptspi_dv_renegotiate_work(struct work_struct *work)
{
struct work_queue_wrapper *wqw =
container_of(work, struct work_queue_wrapper, work);
struct _MPT_SCSI_HOST *hd = wqw->hd;
struct scsi_device *sdev;
struct scsi_target *starget;
struct _CONFIG_PAGE_SCSI_DEVICE_1 pg1;
u32 nego;
MPT_ADAPTER *ioc = hd->ioc;
kfree(wqw);
if (hd->spi_pending) {
shost_for_each_device(sdev, ioc->sh) {
if (hd->spi_pending & (1 << sdev->id))
continue;
starget = scsi_target(sdev);
nego = mptspi_getRP(starget);
pg1.RequestedParameters = cpu_to_le32(nego);
pg1.Reserved = 0;
pg1.Configuration = 0;
mptspi_write_spi_device_pg1(starget, &pg1);
}
} else {
shost_for_each_device(sdev, ioc->sh)
mptspi_dv_device(hd, sdev);
}
}
static void
mptspi_dv_renegotiate(struct _MPT_SCSI_HOST *hd)
{
struct work_queue_wrapper *wqw = kmalloc(sizeof(*wqw), GFP_ATOMIC);
if (!wqw)
return;
INIT_WORK(&wqw->work, mptspi_dv_renegotiate_work);
wqw->hd = hd;
schedule_work(&wqw->work);
}
/*
* spi module reset handler
*/
static int
mptspi_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
{
int rc;
rc = mptscsih_ioc_reset(ioc, reset_phase);
if ((ioc->bus_type != SPI) || (!rc))
return rc;
/* only try to do a renegotiation if we're properly set up
* if we get an ioc fault on bringup, ioc->sh will be NULL */
if (reset_phase == MPT_IOC_POST_RESET &&
ioc->sh) {
struct _MPT_SCSI_HOST *hd = shost_priv(ioc->sh);
mptspi_dv_renegotiate(hd);
}
return rc;
}
#ifdef CONFIG_PM
/*
* spi module resume handler
*/
static int
mptspi_resume(struct pci_dev *pdev)
{
MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
struct _MPT_SCSI_HOST *hd = shost_priv(ioc->sh);
int rc;
rc = mptscsih_resume(pdev);
mptspi_dv_renegotiate(hd);
return rc;
}
#endif
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/*
* mptspi_probe - Installs scsi devices per bus.
* @pdev: Pointer to pci_dev structure
*
* Returns 0 for success, non-zero for failure.
*
*/
static int
mptspi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct Scsi_Host *sh;
MPT_SCSI_HOST *hd;
MPT_ADAPTER *ioc;
unsigned long flags;
int ii;
int numSGE = 0;
int scale;
int ioc_cap;
int error=0;
int r;
if ((r = mpt_attach(pdev,id)) != 0)
return r;
ioc = pci_get_drvdata(pdev);
ioc->DoneCtx = mptspiDoneCtx;
ioc->TaskCtx = mptspiTaskCtx;
ioc->InternalCtx = mptspiInternalCtx;
/* Added sanity check on readiness of the MPT adapter.
*/
if (ioc->last_state != MPI_IOC_STATE_OPERATIONAL) {
printk(MYIOC_s_WARN_FMT
"Skipping because it's not operational!\n",
ioc->name);
error = -ENODEV;
goto out_mptspi_probe;
}
if (!ioc->active) {
printk(MYIOC_s_WARN_FMT "Skipping because it's disabled!\n",
ioc->name);
error = -ENODEV;
goto out_mptspi_probe;
}
/* Sanity check - ensure at least 1 port is INITIATOR capable
*/
ioc_cap = 0;
for (ii=0; ii < ioc->facts.NumberOfPorts; ii++) {
if (ioc->pfacts[ii].ProtocolFlags &
MPI_PORTFACTS_PROTOCOL_INITIATOR)
ioc_cap ++;
}
if (!ioc_cap) {
printk(MYIOC_s_WARN_FMT
"Skipping ioc=%p because SCSI Initiator mode is NOT enabled!\n",
ioc->name, ioc);
return 0;
}
sh = scsi_host_alloc(&mptspi_driver_template, sizeof(MPT_SCSI_HOST));
if (!sh) {
printk(MYIOC_s_WARN_FMT
"Unable to register controller with SCSI subsystem\n",
ioc->name);
error = -1;
goto out_mptspi_probe;
}
spin_lock_irqsave(&ioc->FreeQlock, flags);
/* Attach the SCSI Host to the IOC structure
*/
ioc->sh = sh;
sh->io_port = 0;
sh->n_io_port = 0;
sh->irq = 0;
/* set 16 byte cdb's */
sh->max_cmd_len = 16;
/* Yikes! This is important!
* Otherwise, by default, linux
* only scans target IDs 0-7!
* pfactsN->MaxDevices unreliable
* (not supported in early
* versions of the FW).
* max_id = 1 + actual max id,
* max_lun = 1 + actual last lun,
* see hosts.h :o(
*/
sh->max_id = ioc->devices_per_bus;
sh->max_lun = MPT_LAST_LUN + 1;
/*
* If RAID Firmware Detected, setup virtual channel
*/
if (ioc->ir_firmware)
sh->max_channel = 1;
else
sh->max_channel = 0;
sh->this_id = ioc->pfacts[0].PortSCSIID;
/* Required entry.
*/
sh->unique_id = ioc->id;
/* Verify that we won't exceed the maximum
* number of chain buffers
* We can optimize: ZZ = req_sz/sizeof(SGE)
* For 32bit SGE's:
* numSGE = 1 + (ZZ-1)*(maxChain -1) + ZZ
* + (req_sz - 64)/sizeof(SGE)
* A slightly different algorithm is required for
* 64bit SGEs.
*/
scale = ioc->req_sz/ioc->SGE_size;
if (ioc->sg_addr_size == sizeof(u64)) {
numSGE = (scale - 1) *
(ioc->facts.MaxChainDepth-1) + scale +
(ioc->req_sz - 60) / ioc->SGE_size;
} else {
numSGE = 1 + (scale - 1) *
(ioc->facts.MaxChainDepth-1) + scale +
(ioc->req_sz - 64) / ioc->SGE_size;
}
if (numSGE < sh->sg_tablesize) {
/* Reset this value */
dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
"Resetting sg_tablesize to %d from %d\n",
ioc->name, numSGE, sh->sg_tablesize));
sh->sg_tablesize = numSGE;
}
spin_unlock_irqrestore(&ioc->FreeQlock, flags);
hd = shost_priv(sh);
hd->ioc = ioc;
/* SCSI needs scsi_cmnd lookup table!
* (with size equal to req_depth*PtrSz!)
*/
ioc->ScsiLookup = kcalloc(ioc->req_depth, sizeof(void *), GFP_ATOMIC);
if (!ioc->ScsiLookup) {
error = -ENOMEM;
goto out_mptspi_probe;
}
spin_lock_init(&ioc->scsi_lookup_lock);
dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ScsiLookup @ %p\n",
ioc->name, ioc->ScsiLookup));
ioc->spi_data.Saf_Te = mpt_saf_te;
ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
"saf_te %x\n",
ioc->name,
mpt_saf_te));
ioc->spi_data.noQas = 0;
hd->last_queue_full = 0;
hd->spi_pending = 0;
/* Some versions of the firmware don't support page 0; without
* that we can't get the parameters */
if (ioc->spi_data.sdp0length != 0)
sh->transportt = mptspi_transport_template;
error = scsi_add_host (sh, &ioc->pcidev->dev);
if(error) {
dprintk(ioc, printk(MYIOC_s_ERR_FMT
"scsi_add_host failed\n", ioc->name));
goto out_mptspi_probe;
}
/*
* issue internal bus reset
*/
if (ioc->spi_data.bus_reset)
mptscsih_IssueTaskMgmt(hd,
MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS,
0, 0, 0, 0, 5);
scsi_scan_host(sh);
return 0;
out_mptspi_probe:
mptscsih_remove(pdev);
return error;
}
static struct pci_driver mptspi_driver = {
.name = "mptspi",
.id_table = mptspi_pci_table,
.probe = mptspi_probe,
.remove = __devexit_p(mptscsih_remove),
.shutdown = mptscsih_shutdown,
#ifdef CONFIG_PM
.suspend = mptscsih_suspend,
.resume = mptspi_resume,
#endif
};
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/**
* mptspi_init - Register MPT adapter(s) as SCSI host(s) with SCSI mid-layer.
*
* Returns 0 for success, non-zero for failure.
*/
static int __init
mptspi_init(void)
{
int error;
show_mptmod_ver(my_NAME, my_VERSION);
mptspi_transport_template = spi_attach_transport(&mptspi_transport_functions);
if (!mptspi_transport_template)
return -ENODEV;
mptspiDoneCtx = mpt_register(mptscsih_io_done, MPTSPI_DRIVER,
"mptscsih_io_done");
mptspiTaskCtx = mpt_register(mptscsih_taskmgmt_complete, MPTSPI_DRIVER,
"mptscsih_taskmgmt_complete");
mptspiInternalCtx = mpt_register(mptscsih_scandv_complete,
MPTSPI_DRIVER, "mptscsih_scandv_complete");
mpt_event_register(mptspiDoneCtx, mptspi_event_process);
mpt_reset_register(mptspiDoneCtx, mptspi_ioc_reset);
error = pci_register_driver(&mptspi_driver);
if (error)
spi_release_transport(mptspi_transport_template);
return error;
}
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/**
* mptspi_exit - Unregisters MPT adapter(s)
*/
static void __exit
mptspi_exit(void)
{
pci_unregister_driver(&mptspi_driver);
mpt_reset_deregister(mptspiDoneCtx);
mpt_event_deregister(mptspiDoneCtx);
mpt_deregister(mptspiInternalCtx);
mpt_deregister(mptspiTaskCtx);
mpt_deregister(mptspiDoneCtx);
spi_release_transport(mptspi_transport_template);
}
module_init(mptspi_init);
module_exit(mptspi_exit);
| gpl-2.0 |
xNombre/android_kernel_samsung_golden | drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c | 8273 | 70692 | /**
@verbatim
Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
ADDI-DATA GmbH
Dieselstrasse 3
D-77833 Ottersweier
Tel: +19(0)7223/9493-0
Fax: +49(0)7223/9493-92
http://www.addi-data.com
info@addi-data.com
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
You should also find the complete GPL in the COPYING file accompanying this source code.
@endverbatim
*/
/*
+-----------------------------------------------------------------------+
| (C) ADDI-DATA GmbH Dieselstraße 3 D-77833 Ottersweier |
+-----------------------------------------------------------------------+
| Tel : +49 (0) 7223/9493-0 | email : info@addi-data.com |
| Fax : +49 (0) 7223/9493-92 | Internet : http://www.addi-data.com |
+-----------------------------------------------------------------------+
| Project : API APCI1710 | Compiler : gcc |
| Module name : TOR.C | Version : 2.96 |
+-------------------------------+---------------------------------------+
| Project manager: Eric Stolz | Date : 02/12/2002 |
+-----------------------------------------------------------------------+
| Description : APCI-1710 tor counter module |
| |
| |
+-----------------------------------------------------------------------+
| UPDATES |
+-----------------------------------------------------------------------+
| Date | Author | Description of updates |
+----------+-----------+------------------------------------------------+
| 27/01/99 | S. Weber | 40 MHz implementation |
+-----------------------------------------------------------------------+
| 28/04/00 | S. Weber | Simple,double and quadruple mode implementation|
| | | Extern clock implementation |
+-----------------------------------------------------------------------+
| 08/05/00 | Guinot C | - 0400/0228 All Function in RING 0 |
| | | available |
+-----------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Included files |
+----------------------------------------------------------------------------+
*/
#include "APCI1710_Tor.h"
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_InitTorCounter |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned char_ b_PCIInputClock, |
| unsigned char_ b_TimingUnit, |
| ULONG_ ul_TimingInterval, |
| PULONG_ pul_RealTimingInterval) |
+----------------------------------------------------------------------------+
| Task : Configure the selected tor counter (b_TorCounter) |
| from selected module (b_ModulNbr). |
| The ul_TimingInterval and ul_TimingUnit determine the |
| timing base for the measurement. |
| The pul_RealTimingInterval return the real timing |
| value. You must calling this function be for you call |
| any other function witch access of the tor counter. |
| |
+----------------------------------------------------------------------------+
| Input Parameters : |
|
CR_AREF unsigned char_ b_ModulNbr : Module number to configure |
| (0 to 3) |
| data[0] unsigned char_ b_TorCounter : Tor counter selection |
| (0 or 1). |
| data[1] unsigned char_ b_PCIInputClock : Selection from PCI bus clock|
| - APCI1710_30MHZ : |
| The PC have a PCI bus |
| clock from 30 MHz |
| - APCI1710_33MHZ : |
| The PC have a PCI bus |
| clock from 33 MHz |
| - APCI1710_40MHZ |
| The APCI-1710 have a |
| integrated 40Mhz |
| quartz. |
| - APCI1710_GATE_INPUT |
| Used the gate input for |
| the base clock. If you |
| have selected this option,|
| than it is not possibl to |
| used the gate input for |
| enabled the acquisition |
| data[2] unsigned char_ b_TimingUnit : Base timing unit (0 to 4) |
| 0 : ns |
| 1 : µs |
| 2 : ms |
| 3 : s |
| 4 : mn |
| data[3] ULONG_ ul_TimingInterval : Base timing value. |
+----------------------------------------------------------------------------+
| Output Parameters : PULONG_ pul_RealTimingInterval : Real base timing |
| data[0] value. |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: The selected PCI input clock is wrong |
| -6: Timing unit selection is wrong |
| -7: Base timing selection is wrong |
| -8: You can not used the 40MHz clock selection wich |
| this board |
| -9: You can not used the 40MHz clock selection wich |
| this TOR version |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnConfigInitTorCounter(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int ul_TimerValue = 0;
unsigned int dw_Command;
double d_RealTimingInterval = 0;
unsigned char b_ModulNbr;
unsigned char b_TorCounter;
unsigned char b_PCIInputClock;
unsigned char b_TimingUnit;
unsigned int ul_TimingInterval;
unsigned int ul_RealTimingInterval = 0;
i_ReturnValue = insn->n;
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
b_TorCounter = (unsigned char) data[0];
b_PCIInputClock = (unsigned char) data[1];
b_TimingUnit = (unsigned char) data[2];
ul_TimingInterval = (unsigned int) data[3];
printk("INPUT clock %d\n", b_PCIInputClock);
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
/**************************/
/* Test the PCI bus clock */
/**************************/
if ((b_PCIInputClock == APCI1710_30MHZ) ||
(b_PCIInputClock == APCI1710_33MHZ) ||
(b_PCIInputClock == APCI1710_40MHZ) ||
(b_PCIInputClock ==
APCI1710_GATE_INPUT)) {
/************************/
/* Test the timing unit */
/************************/
if ((b_TimingUnit <= 4)
|| (b_PCIInputClock ==
APCI1710_GATE_INPUT)) {
/**********************************/
/* Test the base timing selection */
/**********************************/
if (((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 0) && (ul_TimingInterval >= 133) && (ul_TimingInterval <= 0xFFFFFFFFUL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 1) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 571230650UL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 2) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 571230UL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 3) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 571UL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 4) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 9UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 0) && (ul_TimingInterval >= 121) && (ul_TimingInterval <= 0xFFFFFFFFUL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 1) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 519691043UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 2) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 519691UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 3) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 520UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 4) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 8UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 0) && (ul_TimingInterval >= 100) && (ul_TimingInterval <= 0xFFFFFFFFUL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 1) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 429496729UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 2) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 429496UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 3) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 429UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 4) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 7UL)) || ((b_PCIInputClock == APCI1710_GATE_INPUT) && (ul_TimingInterval >= 2))) {
/**************************/
/* Test the board version */
/**************************/
if (((b_PCIInputClock == APCI1710_40MHZ) && (devpriv->s_BoardInfos.b_BoardVersion > 0)) || (b_PCIInputClock != APCI1710_40MHZ)) {
/************************/
/* Test the TOR version */
/************************/
if (((b_PCIInputClock == APCI1710_40MHZ) && ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) >= 0x3131)) || ((b_PCIInputClock == APCI1710_GATE_INPUT) && ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) >= 0x3132)) || (b_PCIInputClock == APCI1710_30MHZ) || (b_PCIInputClock == APCI1710_33MHZ)) {
/*********************************/
/* Test if not extern clock used */
/*********************************/
if (b_PCIInputClock != APCI1710_GATE_INPUT) {
fpu_begin
();
/****************************************/
/* Calculate the timer 0 division fator */
/****************************************/
switch (b_TimingUnit) {
/******/
/* ns */
/******/
case 0:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(ul_TimingInterval
*
(0.00025 * b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (0.00025 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(0.00025 * (double)b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(0.00025
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (0.00025 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/******/
/* æs */
/******/
case 1:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(ul_TimingInterval
*
(0.25 * b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (0.25 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(0.25 * (double)b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(
(double)
0.25
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (0.25 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/******/
/* ms */
/******/
case 2:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
ul_TimingInterval
*
(250.0
*
b_PCIInputClock);
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (250.0 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(250.0 * (double)b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(250.0
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (250.0 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/*****/
/* s */
/*****/
case 3:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(ul_TimingInterval
*
(250000.0
*
b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (250000.0 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (250000.0 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/******/
/* mn */
/******/
case 4:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(
(ul_TimingInterval
*
60)
*
(250000.0
*
b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)(ul_TimingInterval * 60.0) * (250000.0 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock))
/
60;
d_RealTimingInterval
=
(
(double)
ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock))
/
60.0;
if ((double)(((double)ul_TimerValue / (250000.0 * (double)b_PCIInputClock)) / 60.0) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
}
fpu_end();
} /* if (b_PCIInputClock != APCI1710_GATE_INPUT) */
else {
/*************************************************************/
/* 2 Clock used for the overflow and the reload from counter */
/*************************************************************/
ul_TimerValue
=
ul_TimingInterval
-
2;
} /* if (b_PCIInputClock != APCI1710_GATE_INPUT) */
/****************************/
/* Save the PCI input clock */
/****************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
b_PCIInputClock
=
b_PCIInputClock;
/************************/
/* Save the timing unit */
/************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_TimingUnit
=
b_TimingUnit;
/************************/
/* Save the base timing */
/************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
d_TimingInterval
=
d_RealTimingInterval;
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
ul_RealTimingInterval
=
ul_RealTimingInterval;
/*******************/
/* Get the command */
/*******************/
dw_Command
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
4
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
dw_Command
=
(dw_Command
>>
4)
&
0xF;
/******************/
/* Test if 40 MHz */
/******************/
if (b_PCIInputClock == APCI1710_40MHZ) {
/****************************/
/* Set the 40 MHz selection */
/****************************/
dw_Command
=
dw_Command
|
0x10;
}
/*****************************/
/* Test if extern clock used */
/*****************************/
if (b_PCIInputClock == APCI1710_GATE_INPUT) {
/****************************/
/* Set the 40 MHz selection */
/****************************/
dw_Command
=
dw_Command
|
0x20;
}
/*************************/
/* Write the new command */
/*************************/
outl(dw_Command, devpriv->s_BoardInfos.ui_Address + 4 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/*******************/
/* Disable the tor */
/*******************/
outl(0, devpriv->s_BoardInfos.ui_Address + 8 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/*************************/
/* Set the timer 1 value */
/*************************/
outl(ul_TimerValue, devpriv->s_BoardInfos.ui_Address + 0 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/*********************/
/* Tor counter init. */
/*********************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_TorCounterInit
=
1;
} else {
/***********************************************/
/* TOR version error for 40MHz clock selection */
/***********************************************/
DPRINTK("TOR version error for 40MHz clock selection\n");
i_ReturnValue
=
-9;
}
} else {
/**************************************************************/
/* You can not used the 40MHz clock selection wich this board */
/**************************************************************/
DPRINTK("You can not used the 40MHz clock selection wich this board\n");
i_ReturnValue =
-8;
}
} else {
/**********************************/
/* Base timing selection is wrong */
/**********************************/
DPRINTK("Base timing selection is wrong\n");
i_ReturnValue = -7;
}
} /* if ((b_TimingUnit >= 0) && (b_TimingUnit <= 4)) */
else {
/**********************************/
/* Timing unit selection is wrong */
/**********************************/
DPRINTK("Timing unit selection is wrong\n");
i_ReturnValue = -6;
} /* if ((b_TimingUnit >= 0) && (b_TimingUnit <= 4)) */
} /* if ((b_PCIInputClock == APCI1710_30MHZ) || (b_PCIInputClock == APCI1710_33MHZ)) */
else {
/*****************************************/
/* The selected PCI input clock is wrong */
/*****************************************/
DPRINTK("The selected PCI input clock is wrong\n");
i_ReturnValue = -5;
} /* if ((b_PCIInputClock == APCI1710_30MHZ) || (b_PCIInputClock == APCI1710_33MHZ)) */
} /* if (b_TorCounterMode >= 0 && b_TorCounterMode <= 7) */
else {
/**********************************/
/* Tor Counter selection is wrong */
/**********************************/
DPRINTK("Tor Counter selection is wrong\n");
i_ReturnValue = -4;
} /* if (b_TorCounterMode >= 0 && b_TorCounterMode <= 7) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
data[0] = (unsigned int) ul_RealTimingInterval;
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_EnableTorCounter |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned char_ b_InputMode, |
| unsigned char_ b_ExternGate, |
| unsigned char_ b_CycleMode, |
| unsigned char_ b_InterruptEnable) |
+----------------------------------------------------------------------------+
| Task : Enable the tor counter (b_TorCounter) from selected |
| module (b_ModulNbr). You must calling the |
| "i_APCI1710_InitTorCounter" function be for you call |
| this function. |
| If you enable the tor counter interrupt, the |
| tor counter generate a interrupt after the timing cycle|
| See function "i_APCI1710_SetBoardIntRoutineX" and the |
| Interrupt mask description chapter from this manual. |
| The b_CycleMode parameter determine if you will |
| measured a single or more cycle. |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1). |
| unsigned char_ b_InputMode : Input signal level selection |
| 0 : Tor count each low level |
| 1 : Tor count each high level|
| unsigned char_ b_ExternGate : Extern gate action selection |
| 0 : Extern gate signal not |
| used |
| 1 : Extern gate signal used. |
| If you selected the |
| single mode, each high |
| level signal start the |
| counter. |
| If you selected the |
| continuous mode, the |
| first high level signal |
| start the tor counter |
| |
| APCI1710_TOR_QUADRUPLE _MODE : |
| In the quadruple mode, the edge|
| analysis circuit generates a |
| counting pulse from each edge |
| of 2 signals which are phase |
| shifted in relation to each |
| other. |
| The gate input is used for the |
| signal B |
| |
| APCI1710_TOR_DOUBLE_MODE: |
| Functions in the same way as |
| the quadruple mode, except that|
| only two of the four edges are |
| analysed per period. |
| The gate input is used for the |
| signal B |
| |
| APCI1710_TOR_SIMPLE_MODE: |
| Functions in the same way as |
| the quadruple mode, except that|
| only one of the four edges is |
| analysed per period. |
| The gate input is used for the |
| signal B |
| |
| unsigned char_ b_CycleMode : Selected the tor counter |
| acquisition mode |
| unsigned char_ b_InterruptEnable : Enable or disable the |
| tor counter interrupt. |
| APCI1710_ENABLE: |
| Enable the tor counter |
| interrupt |
| APCI1710_DISABLE: |
| Disable the tor counter |
| interrupt |
+----------------------------------------------------------------------------+
| Output Parameters : - |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
| -6: Tor input signal selection is wrong |
| -7: Extern gate signal mode is wrong |
| -8: Tor counter acquisition mode cycle is wrong |
| -9: Interrupt parameter is wrong |
| -10:Interrupt function not initialised. |
| See function "i_APCI1710_SetBoardIntRoutineX" |
+----------------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_DisableTorCounter |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter) |
+----------------------------------------------------------------------------+
| Task : Disable the tor counter (b_TorCounter) from selected |
| module (b_ModulNbr). If you disable the tor counter |
| after a start cycle occur and you restart the tor |
| counter witch the " i_APCI1710_EnableTorCounter" |
| function, the status register is cleared |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1). |
+----------------------------------------------------------------------------+
| Output Parameters : - |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
| -6: Tor counter not enabled see function |
| "i_APCI1710_EnableTorCounter" |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnWriteEnableDisableTorCounter(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_Status;
unsigned int dw_DummyRead;
unsigned int dw_ConfigReg;
unsigned char b_ModulNbr, b_Action;
unsigned char b_TorCounter;
unsigned char b_InputMode;
unsigned char b_ExternGate;
unsigned char b_CycleMode;
unsigned char b_InterruptEnable;
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
b_Action = (unsigned char) data[0]; /* enable or disable */
b_TorCounter = (unsigned char) data[1];
b_InputMode = (unsigned char) data[2];
b_ExternGate = (unsigned char) data[3];
b_CycleMode = (unsigned char) data[4];
b_InterruptEnable = (unsigned char) data[5];
i_ReturnValue = insn->n;
devpriv->tsk_Current = current; /* Save the current process task structure */
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
switch (b_Action) /* Enable or Disable */
{
case APCI1710_ENABLE:
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status =
inl(devpriv->s_BoardInfos.
ui_Address + 8 +
(16 * b_TorCounter) +
(64 * b_ModulNbr));
if (dw_Status & 0x10) {
/******************************/
/* Test the input signal mode */
/******************************/
if (b_InputMode == 0 ||
b_InputMode == 1 ||
b_InputMode ==
APCI1710_TOR_SIMPLE_MODE
|| b_InputMode ==
APCI1710_TOR_DOUBLE_MODE
|| b_InputMode ==
APCI1710_TOR_QUADRUPLE_MODE)
{
/************************************/
/* Test the extern gate signal mode */
/************************************/
if (b_ExternGate == 0
|| b_ExternGate
== 1
|| b_InputMode >
1) {
/*********************************/
/* Test the cycle mode parameter */
/*********************************/
if ((b_CycleMode == APCI1710_SINGLE) || (b_CycleMode == APCI1710_CONTINUOUS)) {
/***************************/
/* Test the interrupt flag */
/***************************/
if ((b_InterruptEnable == APCI1710_ENABLE) || (b_InterruptEnable == APCI1710_DISABLE)) {
/***************************/
/* Save the interrupt mode */
/***************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_InterruptEnable
=
b_InterruptEnable;
/*******************/
/* Get the command */
/*******************/
dw_ConfigReg
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
4
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
dw_ConfigReg
=
(dw_ConfigReg
>>
4)
&
0x30;
/********************************/
/* Test if not direct mode used */
/********************************/
if (b_InputMode > 1) {
/*******************************/
/* Extern gate can not be used */
/*******************************/
b_ExternGate
=
0;
/*******************************************/
/* Enable the extern gate for the Signal B */
/*******************************************/
dw_ConfigReg
=
dw_ConfigReg
|
0x40;
/***********************/
/* Test if simple mode */
/***********************/
if (b_InputMode == APCI1710_TOR_SIMPLE_MODE) {
/**************************/
/* Enable the sinple mode */
/**************************/
dw_ConfigReg
=
dw_ConfigReg
|
0x780;
} /* if (b_InputMode == APCI1710_TOR_SIMPLE_MODE) */
/***********************/
/* Test if double mode */
/***********************/
if (b_InputMode == APCI1710_TOR_DOUBLE_MODE) {
/**************************/
/* Enable the double mode */
/**************************/
dw_ConfigReg
=
dw_ConfigReg
|
0x180;
} /* if (b_InputMode == APCI1710_TOR_DOUBLE_MODE) */
b_InputMode
=
0;
} /* if (b_InputMode > 1) */
/*******************/
/* Set the command */
/*******************/
dw_ConfigReg
=
dw_ConfigReg
|
b_CycleMode
|
(b_InterruptEnable
*
2)
|
(b_InputMode
*
4)
|
(b_ExternGate
*
8);
/*****************************/
/* Clear the status register */
/*****************************/
dw_DummyRead
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
0
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
/***************************************/
/* Clear the interrupt status register */
/***************************************/
dw_DummyRead
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
12
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
/********************/
/* Set the commando */
/********************/
outl(dw_ConfigReg, devpriv->s_BoardInfos.ui_Address + 4 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/****************/
/* Set the gate */
/****************/
outl(1, devpriv->s_BoardInfos.ui_Address + 8 + (16 * b_TorCounter) + (64 * b_ModulNbr));
} /* if ((b_InterruptEnable == APCI1710_ENABLE) || (b_InterruptEnable == APCI1710_DISABLE)) */
else {
/********************************/
/* Interrupt parameter is wrong */
/********************************/
DPRINTK("Interrupt parameter is wrong\n");
i_ReturnValue
=
-9;
} /* if ((b_InterruptEnable == APCI1710_ENABLE) || (b_InterruptEnable == APCI1710_DISABLE)) */
} /* if ((b_CycleMode == APCI1710_SINGLE) || (b_CycleMode == APCI1710_CONTINUOUS)) */
else {
/***********************************************/
/* Tor counter acquisition mode cycle is wrong */
/***********************************************/
DPRINTK("Tor counter acquisition mode cycle is wrong\n");
i_ReturnValue
=
-8;
} /* if ((b_CycleMode == APCI1710_SINGLE) || (b_CycleMode == APCI1710_CONTINUOUS)) */
} /* if (b_ExternGate >= 0 && b_ExternGate <= 1) */
else {
/***********************************/
/* Extern gate input mode is wrong */
/***********************************/
DPRINTK("Extern gate input mode is wrong\n");
i_ReturnValue =
-7;
} /* if (b_ExternGate >= 0 && b_ExternGate <= 1) */
} /* if (b_InputMode >= 0 && b_InputMode <= 1) */
else {
/***************************************/
/* Tor input signal selection is wrong */
/***************************************/
DPRINTK("Tor input signal selection is wrong\n");
i_ReturnValue = -6;
}
} else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
}
break;
case APCI1710_DISABLE:
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 8 +
(16 * b_TorCounter) +
(64 * b_ModulNbr));
/*******************************/
/* Test if counter initialised */
/*******************************/
if (dw_Status & 0x10) {
/***************************/
/* Test if counter enabled */
/***************************/
if (dw_Status & 0x1) {
/****************************/
/* Clear the interrupt mode */
/****************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_InterruptEnable
=
APCI1710_DISABLE;
/******************/
/* Clear the gate */
/******************/
outl(0, devpriv->
s_BoardInfos.
ui_Address + 8 +
(16 * b_TorCounter) + (64 * b_ModulNbr));
} /* if (dw_Status & 0x1) */
else {
/***************************/
/* Tor counter not enabled */
/***************************/
DPRINTK("Tor counter not enabled \n");
i_ReturnValue = -6;
} /* if (dw_Status & 0x1) */
} /* if (dw_Status & 0x10) */
else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
} /* // if (dw_Status & 0x10) */
} /* switch */
} /* if (b_TorCounter <= 1) */
else {
/**********************************/
/* Tor counter selection is wrong */
/**********************************/
DPRINTK("Tor counter selection is wrong\n");
i_ReturnValue = -4;
} /* if (b_TorCounter <= 1) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module \n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error \n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_GetTorCounterInitialisation |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned char *_ pb_TimingUnit, |
| PULONG_ pul_TimingInterval, |
| unsigned char *_ pb_InputMode, |
| unsigned char *_ pb_ExternGate, |
| unsigned char *_ pb_CycleMode, |
| unsigned char *_ pb_Enable, |
| unsigned char *_ pb_InterruptEnable)|
+----------------------------------------------------------------------------+
| Task : Enable the tor counter (b_TorCounter) from selected |
| module (b_ModulNbr). You must calling the |
| "i_APCI1710_InitTorCounter" function be for you call |
| this function. |
| If you enable the tor counter interrupt, the |
| tor counter generate a interrupt after the timing cycle|
| See function "i_APCI1710_SetBoardIntRoutineX" and the |
| Interrupt mask description chapter from this manual. |
| The b_CycleMode parameter determine if you will |
| measured a single or more cycle. |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1)
b_ModulNbr = CR_AREF(insn->chanspec);
b_TorCounter = CR_CHAN(insn->chanspec);
. |
+----------------------------------------------------------------------------+
| Output Parameters : unsigned char *_ pb_TimingUnit : Base timing unit (0 to 4) |
| 0 : ns |
| 1 : µs |
| 2 : ms |
| 3 : s |
| 4 : mn |
| PULONG_ pul_TimingInterval : Base timing value. |
| unsigned char *_ pb_InputMode : Input signal level |
| selection |
| 0 : Tor count each low level |
| 1 : Tor count each high level|
| unsigned char *_ pb_ExternGate : Extern gate action |
| selection |
| 0 : Extern gate signal not |
| used |
| 1 : Extern gate signal used|
| unsigned char *_ pb_CycleMode : Tor counter acquisition |
| mode |
| unsigned char *_ pb_Enable : Indicate if the tor counter|
| is enabled or no |
| 0 : Tor counter disabled |
| 1 : Tor counter enabled |
| unsigned char *_ pb_InterruptEnable : Enable or disable the |
| tor counter interrupt. |
| APCI1710_ENABLE: |
| Enable the tor counter |
| interrupt |
| APCI1710_DISABLE: |
| Disable the tor counter |
| interrupt
pb_TimingUnit = (unsigned char *) &data[0];
pul_TimingInterval = (unsigned int *) &data[1];
pb_InputMode = (unsigned char *) &data[2];
pb_ExternGate = (unsigned char *) &data[3];
pb_CycleMode = (unsigned char *) &data[4];
pb_Enable = (unsigned char *) &data[5];
pb_InterruptEnable = (unsigned char *) &data[6];
|
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnReadGetTorCounterInitialisation(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_Status;
unsigned char b_ModulNbr;
unsigned char b_TorCounter;
unsigned char *pb_TimingUnit;
unsigned int *pul_TimingInterval;
unsigned char *pb_InputMode;
unsigned char *pb_ExternGate;
unsigned char *pb_CycleMode;
unsigned char *pb_Enable;
unsigned char *pb_InterruptEnable;
i_ReturnValue = insn->n;
b_ModulNbr = CR_AREF(insn->chanspec);
b_TorCounter = CR_CHAN(insn->chanspec);
pb_TimingUnit = (unsigned char *) &data[0];
pul_TimingInterval = (unsigned int *) &data[1];
pb_InputMode = (unsigned char *) &data[2];
pb_ExternGate = (unsigned char *) &data[3];
pb_CycleMode = (unsigned char *) &data[4];
pb_Enable = (unsigned char *) &data[5];
pb_InterruptEnable = (unsigned char *) &data[6];
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 8 + (16 * b_TorCounter) +
(64 * b_ModulNbr));
if (dw_Status & 0x10) {
*pb_Enable = dw_Status & 1;
/********************/
/* Get the commando */
/********************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 4 +
(16 * b_TorCounter) +
(64 * b_ModulNbr));
*pb_CycleMode =
(unsigned char) ((dw_Status >> 4) & 1);
*pb_InterruptEnable =
(unsigned char) ((dw_Status >> 5) & 1);
/******************************************************/
/* Test if extern gate used for clock or for signal B */
/******************************************************/
if (dw_Status & 0x600) {
/*****************************************/
/* Test if extern gate used for signal B */
/*****************************************/
if (dw_Status & 0x400) {
/***********************/
/* Test if simple mode */
/***********************/
if ((dw_Status & 0x7800)
== 0x7800) {
*pb_InputMode =
APCI1710_TOR_SIMPLE_MODE;
}
/***********************/
/* Test if double mode */
/***********************/
if ((dw_Status & 0x7800)
== 0x1800) {
*pb_InputMode =
APCI1710_TOR_DOUBLE_MODE;
}
/**************************/
/* Test if quadruple mode */
/**************************/
if ((dw_Status & 0x7800)
== 0x0000) {
*pb_InputMode =
APCI1710_TOR_QUADRUPLE_MODE;
}
} /* if (dw_Status & 0x400) */
else {
*pb_InputMode = 1;
} /* // if (dw_Status & 0x400) */
/************************/
/* Extern gate not used */
/************************/
*pb_ExternGate = 0;
} /* if (dw_Status & 0x600) */
else {
*pb_InputMode =
(unsigned char) ((dw_Status >> 6)
& 1);
*pb_ExternGate =
(unsigned char) ((dw_Status >> 7)
& 1);
} /* if (dw_Status & 0x600) */
*pb_TimingUnit =
devpriv->
s_ModuleInfo[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo[b_TorCounter].
b_TimingUnit;
*pul_TimingInterval =
devpriv->
s_ModuleInfo[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo[b_TorCounter].
ul_RealTimingInterval;
} else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
}
} /* if (b_TorCounter <= 1) */
else {
/**********************************/
/* Tor counter selection is wrong */
/**********************************/
DPRINTK("Tor counter selection is wrong \n");
i_ReturnValue = -4;
} /* if (b_TorCounter <= 1) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_ReadTorCounterValue |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned int_ ui_TimeOut, |
| unsigned char *_ pb_TorCounterStatus, |
| PULONG_ pul_TorCounterValue) |
+----------------------------------------------------------------------------+
| Task case APCI1710_TOR_GETPROGRESSSTATUS: Return the tor counter
(b_TorCounter) status (pb_TorCounterStatus) from selected tor counter |
| module (b_ModulNbr).
case APCI1710_TOR_GETCOUNTERVALUE :
Return the tor counter (b_TorCounter) status |
| (pb_TorCounterStatus) and the timing value |
| (pul_TorCounterValue) after a conting cycle stop |
| from selected tor counter module (b_ModulNbr). |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1).
b_ModulNbr = CR_AREF(insn->chanspec);
b_ReadType = (unsigned char) data[0];
b_TorCounter = (unsigned char) data[1];
ui_TimeOut = (unsigned int) data[2]; |
+----------------------------------------------------------------------------+
| Output Parameters : unsigned char *_ pb_TorCounterStatus : Return the tor counter |
| status. |
| 0 : Conting cycle not started|
| Software gate not set. |
| 1 : Conting cycle started. |
| Software gate set. |
| 2 : Conting cycle stopped. |
| The conting cycle is |
| terminate. |
| 3 : A overflow occur. You |
| must change the base |
| timing witch the |
| function |
| "i_APCI1710_InitTorCounter"|
| 4 : Timeeout occur |
| unsigned int * pul_TorCounterValue : Tor counter value.
pb_TorCounterStatus=(unsigned char *) &data[0];
pul_TorCounterValue=(unsigned int *) &data[1]; |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
| -6: Tor counter not enabled see function |
| "i_APCI1710_EnableTorCounter" |
| -7: Timeout parameter is wrong (0 to 65535) |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnBitsGetTorCounterProgressStatusAndValue(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_Status;
unsigned int dw_TimeOut = 0;
unsigned char b_ModulNbr;
unsigned char b_TorCounter;
unsigned char b_ReadType;
unsigned int ui_TimeOut;
unsigned char *pb_TorCounterStatus;
unsigned int *pul_TorCounterValue;
i_ReturnValue = insn->n;
b_ModulNbr = CR_AREF(insn->chanspec);
b_ReadType = (unsigned char) data[0];
b_TorCounter = (unsigned char) data[1];
ui_TimeOut = (unsigned int) data[2];
pb_TorCounterStatus = (unsigned char *) &data[0];
pul_TorCounterValue = (unsigned int *) &data[1];
/**************************/
/* Test the module number */
/**************************/
if (b_ReadType == APCI1710_TOR_READINTERRUPT) {
data[0] = devpriv->s_InterruptParameters.
s_FIFOInterruptParameters[devpriv->
s_InterruptParameters.ui_Read].b_OldModuleMask;
data[1] = devpriv->s_InterruptParameters.
s_FIFOInterruptParameters[devpriv->
s_InterruptParameters.ui_Read].ul_OldInterruptMask;
data[2] = devpriv->s_InterruptParameters.
s_FIFOInterruptParameters[devpriv->
s_InterruptParameters.ui_Read].ul_OldCounterLatchValue;
/**************************/
/* Increment the read FIFO */
/***************************/
devpriv->
s_InterruptParameters.
ui_Read = (devpriv->
s_InterruptParameters.
ui_Read + 1) % APCI1710_SAVE_INTERRUPT;
return insn->n;
}
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 8 + (16 * b_TorCounter) +
(64 * b_ModulNbr));
/*******************************/
/* Test if counter initialised */
/*******************************/
if (dw_Status & 0x10) {
/***************************/
/* Test if counter enabled */
/***************************/
if (dw_Status & 0x1) {
switch (b_ReadType) {
case APCI1710_TOR_GETPROGRESSSTATUS:
/*******************/
/* Read the status */
/*******************/
dw_Status =
inl(devpriv->
s_BoardInfos.
ui_Address + 4 +
(16 * b_TorCounter) + (64 * b_ModulNbr));
dw_Status =
dw_Status & 0xF;
/*****************/
/* Test if start */
/*****************/
if (dw_Status & 1) {
if (dw_Status &
2) {
if (dw_Status & 4) {
/************************/
/* Tor counter overflow */
/************************/
*pb_TorCounterStatus
=
3;
} else {
/***********************/
/* Tor counter started */
/***********************/
*pb_TorCounterStatus
=
2;
}
} else {
/***********************/
/* Tor counter started */
/***********************/
*pb_TorCounterStatus
=
1;
}
} else {
/***************************/
/* Tor counter not started */
/***************************/
*pb_TorCounterStatus
= 0;
}
break;
case APCI1710_TOR_GETCOUNTERVALUE:
/*****************************/
/* Test the timout parameter */
/*****************************/
if ((ui_TimeOut >= 0)
&& (ui_TimeOut
<=
65535UL))
{
for (;;) {
/*******************/
/* Read the status */
/*******************/
dw_Status
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
4
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
/********************/
/* Test if overflow */
/********************/
if ((dw_Status & 4) == 4) {
/******************/
/* Overflow occur */
/******************/
*pb_TorCounterStatus
=
3;
/******************/
/* Read the value */
/******************/
*pul_TorCounterValue
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
0
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
break;
} /* if ((dw_Status & 4) == 4) */
else {
/*******************************/
/* Test if measurement stopped */
/*******************************/
if ((dw_Status & 2) == 2) {
/***********************/
/* A stop signal occur */
/***********************/
*pb_TorCounterStatus
=
2;
/******************/
/* Read the value */
/******************/
*pul_TorCounterValue
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
0
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
break;
} /* if ((dw_Status & 2) == 2) */
else {
/*******************************/
/* Test if measurement started */
/*******************************/
if ((dw_Status & 1) == 1) {
/************************/
/* A start signal occur */
/************************/
*pb_TorCounterStatus
=
1;
} /* if ((dw_Status & 1) == 1) */
else {
/***************************/
/* Measurement not started */
/***************************/
*pb_TorCounterStatus
=
0;
} /* if ((dw_Status & 1) == 1) */
} /* if ((dw_Status & 2) == 2) */
} /* if ((dw_Status & 8) == 8) */
if (dw_TimeOut == ui_TimeOut) {
/*****************/
/* Timeout occur */
/*****************/
break;
} else {
/*************************/
/* Increment the timeout */
/*************************/
dw_TimeOut
=
dw_TimeOut
+
1;
mdelay(1000);
}
} /* for (;;) */
/*************************/
/* Test if timeout occur */
/*************************/
if ((*pb_TorCounterStatus != 3) && (dw_TimeOut == ui_TimeOut) && (ui_TimeOut != 0)) {
/*****************/
/* Timeout occur */
/*****************/
*pb_TorCounterStatus
=
4;
}
} else {
/******************************/
/* Timeout parameter is wrong */
/******************************/
DPRINTK("Timeout parameter is wrong\n");
i_ReturnValue =
-7;
}
break;
default:
printk("Inputs wrong\n");
} /* switch end */
} /* if (dw_Status & 0x1) */
else {
/***************************/
/* Tor counter not enabled */
/***************************/
DPRINTK("Tor counter not enabled\n");
i_ReturnValue = -6;
} /* if (dw_Status & 0x1) */
} else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
}
} /* if (b_TorCounter <= 1) */
else {
/**********************************/
/* Tor counter selection is wrong */
/**********************************/
DPRINTK("Tor counter selection is wrong\n");
i_ReturnValue = -4;
} /* if (b_TorCounter <= 1) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
| gpl-2.0 |
jsnmarek/kernel_samsung_jf | drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c | 8273 | 70692 | /**
@verbatim
Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
ADDI-DATA GmbH
Dieselstrasse 3
D-77833 Ottersweier
Tel: +19(0)7223/9493-0
Fax: +49(0)7223/9493-92
http://www.addi-data.com
info@addi-data.com
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
You should also find the complete GPL in the COPYING file accompanying this source code.
@endverbatim
*/
/*
+-----------------------------------------------------------------------+
| (C) ADDI-DATA GmbH Dieselstraße 3 D-77833 Ottersweier |
+-----------------------------------------------------------------------+
| Tel : +49 (0) 7223/9493-0 | email : info@addi-data.com |
| Fax : +49 (0) 7223/9493-92 | Internet : http://www.addi-data.com |
+-----------------------------------------------------------------------+
| Project : API APCI1710 | Compiler : gcc |
| Module name : TOR.C | Version : 2.96 |
+-------------------------------+---------------------------------------+
| Project manager: Eric Stolz | Date : 02/12/2002 |
+-----------------------------------------------------------------------+
| Description : APCI-1710 tor counter module |
| |
| |
+-----------------------------------------------------------------------+
| UPDATES |
+-----------------------------------------------------------------------+
| Date | Author | Description of updates |
+----------+-----------+------------------------------------------------+
| 27/01/99 | S. Weber | 40 MHz implementation |
+-----------------------------------------------------------------------+
| 28/04/00 | S. Weber | Simple,double and quadruple mode implementation|
| | | Extern clock implementation |
+-----------------------------------------------------------------------+
| 08/05/00 | Guinot C | - 0400/0228 All Function in RING 0 |
| | | available |
+-----------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Included files |
+----------------------------------------------------------------------------+
*/
#include "APCI1710_Tor.h"
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_InitTorCounter |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned char_ b_PCIInputClock, |
| unsigned char_ b_TimingUnit, |
| ULONG_ ul_TimingInterval, |
| PULONG_ pul_RealTimingInterval) |
+----------------------------------------------------------------------------+
| Task : Configure the selected tor counter (b_TorCounter) |
| from selected module (b_ModulNbr). |
| The ul_TimingInterval and ul_TimingUnit determine the |
| timing base for the measurement. |
| The pul_RealTimingInterval return the real timing |
| value. You must calling this function be for you call |
| any other function witch access of the tor counter. |
| |
+----------------------------------------------------------------------------+
| Input Parameters : |
|
CR_AREF unsigned char_ b_ModulNbr : Module number to configure |
| (0 to 3) |
| data[0] unsigned char_ b_TorCounter : Tor counter selection |
| (0 or 1). |
| data[1] unsigned char_ b_PCIInputClock : Selection from PCI bus clock|
| - APCI1710_30MHZ : |
| The PC have a PCI bus |
| clock from 30 MHz |
| - APCI1710_33MHZ : |
| The PC have a PCI bus |
| clock from 33 MHz |
| - APCI1710_40MHZ |
| The APCI-1710 have a |
| integrated 40Mhz |
| quartz. |
| - APCI1710_GATE_INPUT |
| Used the gate input for |
| the base clock. If you |
| have selected this option,|
| than it is not possibl to |
| used the gate input for |
| enabled the acquisition |
| data[2] unsigned char_ b_TimingUnit : Base timing unit (0 to 4) |
| 0 : ns |
| 1 : µs |
| 2 : ms |
| 3 : s |
| 4 : mn |
| data[3] ULONG_ ul_TimingInterval : Base timing value. |
+----------------------------------------------------------------------------+
| Output Parameters : PULONG_ pul_RealTimingInterval : Real base timing |
| data[0] value. |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: The selected PCI input clock is wrong |
| -6: Timing unit selection is wrong |
| -7: Base timing selection is wrong |
| -8: You can not used the 40MHz clock selection wich |
| this board |
| -9: You can not used the 40MHz clock selection wich |
| this TOR version |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnConfigInitTorCounter(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int ul_TimerValue = 0;
unsigned int dw_Command;
double d_RealTimingInterval = 0;
unsigned char b_ModulNbr;
unsigned char b_TorCounter;
unsigned char b_PCIInputClock;
unsigned char b_TimingUnit;
unsigned int ul_TimingInterval;
unsigned int ul_RealTimingInterval = 0;
i_ReturnValue = insn->n;
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
b_TorCounter = (unsigned char) data[0];
b_PCIInputClock = (unsigned char) data[1];
b_TimingUnit = (unsigned char) data[2];
ul_TimingInterval = (unsigned int) data[3];
printk("INPUT clock %d\n", b_PCIInputClock);
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
/**************************/
/* Test the PCI bus clock */
/**************************/
if ((b_PCIInputClock == APCI1710_30MHZ) ||
(b_PCIInputClock == APCI1710_33MHZ) ||
(b_PCIInputClock == APCI1710_40MHZ) ||
(b_PCIInputClock ==
APCI1710_GATE_INPUT)) {
/************************/
/* Test the timing unit */
/************************/
if ((b_TimingUnit <= 4)
|| (b_PCIInputClock ==
APCI1710_GATE_INPUT)) {
/**********************************/
/* Test the base timing selection */
/**********************************/
if (((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 0) && (ul_TimingInterval >= 133) && (ul_TimingInterval <= 0xFFFFFFFFUL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 1) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 571230650UL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 2) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 571230UL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 3) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 571UL)) || ((b_PCIInputClock == APCI1710_30MHZ) && (b_TimingUnit == 4) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 9UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 0) && (ul_TimingInterval >= 121) && (ul_TimingInterval <= 0xFFFFFFFFUL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 1) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 519691043UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 2) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 519691UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 3) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 520UL)) || ((b_PCIInputClock == APCI1710_33MHZ) && (b_TimingUnit == 4) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 8UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 0) && (ul_TimingInterval >= 100) && (ul_TimingInterval <= 0xFFFFFFFFUL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 1) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 429496729UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 2) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 429496UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 3) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 429UL)) || ((b_PCIInputClock == APCI1710_40MHZ) && (b_TimingUnit == 4) && (ul_TimingInterval >= 1) && (ul_TimingInterval <= 7UL)) || ((b_PCIInputClock == APCI1710_GATE_INPUT) && (ul_TimingInterval >= 2))) {
/**************************/
/* Test the board version */
/**************************/
if (((b_PCIInputClock == APCI1710_40MHZ) && (devpriv->s_BoardInfos.b_BoardVersion > 0)) || (b_PCIInputClock != APCI1710_40MHZ)) {
/************************/
/* Test the TOR version */
/************************/
if (((b_PCIInputClock == APCI1710_40MHZ) && ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) >= 0x3131)) || ((b_PCIInputClock == APCI1710_GATE_INPUT) && ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF) >= 0x3132)) || (b_PCIInputClock == APCI1710_30MHZ) || (b_PCIInputClock == APCI1710_33MHZ)) {
/*********************************/
/* Test if not extern clock used */
/*********************************/
if (b_PCIInputClock != APCI1710_GATE_INPUT) {
fpu_begin
();
/****************************************/
/* Calculate the timer 0 division fator */
/****************************************/
switch (b_TimingUnit) {
/******/
/* ns */
/******/
case 0:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(ul_TimingInterval
*
(0.00025 * b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (0.00025 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(0.00025 * (double)b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(0.00025
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (0.00025 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/******/
/* æs */
/******/
case 1:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(ul_TimingInterval
*
(0.25 * b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (0.25 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(0.25 * (double)b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(
(double)
0.25
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (0.25 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/******/
/* ms */
/******/
case 2:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
ul_TimingInterval
*
(250.0
*
b_PCIInputClock);
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (250.0 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(250.0 * (double)b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(250.0
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (250.0 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/*****/
/* s */
/*****/
case 3:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(ul_TimingInterval
*
(250000.0
*
b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)ul_TimingInterval * (250000.0 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock));
d_RealTimingInterval
=
(double)
ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock);
if ((double)((double)ul_TimerValue / (250000.0 * (double)b_PCIInputClock)) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
/******/
/* mn */
/******/
case 4:
/******************/
/* Timer 0 factor */
/******************/
ul_TimerValue
=
(unsigned int)
(
(ul_TimingInterval
*
60)
*
(250000.0
*
b_PCIInputClock));
/*******************/
/* Round the value */
/*******************/
if ((double)((double)(ul_TimingInterval * 60.0) * (250000.0 * (double)b_PCIInputClock)) >= ((double)((double)ul_TimerValue + 0.5))) {
ul_TimerValue
=
ul_TimerValue
+
1;
}
/*****************************/
/* Calculate the real timing */
/*****************************/
ul_RealTimingInterval
=
(unsigned int)
(ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock))
/
60;
d_RealTimingInterval
=
(
(double)
ul_TimerValue
/
(250000.0
*
(double)
b_PCIInputClock))
/
60.0;
if ((double)(((double)ul_TimerValue / (250000.0 * (double)b_PCIInputClock)) / 60.0) >= (double)((double)ul_RealTimingInterval + 0.5)) {
ul_RealTimingInterval
=
ul_RealTimingInterval
+
1;
}
ul_TimingInterval
=
ul_TimingInterval
-
1;
ul_TimerValue
=
ul_TimerValue
-
2;
if (b_PCIInputClock != APCI1710_40MHZ) {
ul_TimerValue
=
(unsigned int)
(
(double)
(ul_TimerValue)
*
1.007752288);
}
break;
}
fpu_end();
} /* if (b_PCIInputClock != APCI1710_GATE_INPUT) */
else {
/*************************************************************/
/* 2 Clock used for the overflow and the reload from counter */
/*************************************************************/
ul_TimerValue
=
ul_TimingInterval
-
2;
} /* if (b_PCIInputClock != APCI1710_GATE_INPUT) */
/****************************/
/* Save the PCI input clock */
/****************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
b_PCIInputClock
=
b_PCIInputClock;
/************************/
/* Save the timing unit */
/************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_TimingUnit
=
b_TimingUnit;
/************************/
/* Save the base timing */
/************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
d_TimingInterval
=
d_RealTimingInterval;
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
ul_RealTimingInterval
=
ul_RealTimingInterval;
/*******************/
/* Get the command */
/*******************/
dw_Command
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
4
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
dw_Command
=
(dw_Command
>>
4)
&
0xF;
/******************/
/* Test if 40 MHz */
/******************/
if (b_PCIInputClock == APCI1710_40MHZ) {
/****************************/
/* Set the 40 MHz selection */
/****************************/
dw_Command
=
dw_Command
|
0x10;
}
/*****************************/
/* Test if extern clock used */
/*****************************/
if (b_PCIInputClock == APCI1710_GATE_INPUT) {
/****************************/
/* Set the 40 MHz selection */
/****************************/
dw_Command
=
dw_Command
|
0x20;
}
/*************************/
/* Write the new command */
/*************************/
outl(dw_Command, devpriv->s_BoardInfos.ui_Address + 4 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/*******************/
/* Disable the tor */
/*******************/
outl(0, devpriv->s_BoardInfos.ui_Address + 8 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/*************************/
/* Set the timer 1 value */
/*************************/
outl(ul_TimerValue, devpriv->s_BoardInfos.ui_Address + 0 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/*********************/
/* Tor counter init. */
/*********************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_TorCounterInit
=
1;
} else {
/***********************************************/
/* TOR version error for 40MHz clock selection */
/***********************************************/
DPRINTK("TOR version error for 40MHz clock selection\n");
i_ReturnValue
=
-9;
}
} else {
/**************************************************************/
/* You can not used the 40MHz clock selection wich this board */
/**************************************************************/
DPRINTK("You can not used the 40MHz clock selection wich this board\n");
i_ReturnValue =
-8;
}
} else {
/**********************************/
/* Base timing selection is wrong */
/**********************************/
DPRINTK("Base timing selection is wrong\n");
i_ReturnValue = -7;
}
} /* if ((b_TimingUnit >= 0) && (b_TimingUnit <= 4)) */
else {
/**********************************/
/* Timing unit selection is wrong */
/**********************************/
DPRINTK("Timing unit selection is wrong\n");
i_ReturnValue = -6;
} /* if ((b_TimingUnit >= 0) && (b_TimingUnit <= 4)) */
} /* if ((b_PCIInputClock == APCI1710_30MHZ) || (b_PCIInputClock == APCI1710_33MHZ)) */
else {
/*****************************************/
/* The selected PCI input clock is wrong */
/*****************************************/
DPRINTK("The selected PCI input clock is wrong\n");
i_ReturnValue = -5;
} /* if ((b_PCIInputClock == APCI1710_30MHZ) || (b_PCIInputClock == APCI1710_33MHZ)) */
} /* if (b_TorCounterMode >= 0 && b_TorCounterMode <= 7) */
else {
/**********************************/
/* Tor Counter selection is wrong */
/**********************************/
DPRINTK("Tor Counter selection is wrong\n");
i_ReturnValue = -4;
} /* if (b_TorCounterMode >= 0 && b_TorCounterMode <= 7) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
data[0] = (unsigned int) ul_RealTimingInterval;
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_EnableTorCounter |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned char_ b_InputMode, |
| unsigned char_ b_ExternGate, |
| unsigned char_ b_CycleMode, |
| unsigned char_ b_InterruptEnable) |
+----------------------------------------------------------------------------+
| Task : Enable the tor counter (b_TorCounter) from selected |
| module (b_ModulNbr). You must calling the |
| "i_APCI1710_InitTorCounter" function be for you call |
| this function. |
| If you enable the tor counter interrupt, the |
| tor counter generate a interrupt after the timing cycle|
| See function "i_APCI1710_SetBoardIntRoutineX" and the |
| Interrupt mask description chapter from this manual. |
| The b_CycleMode parameter determine if you will |
| measured a single or more cycle. |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1). |
| unsigned char_ b_InputMode : Input signal level selection |
| 0 : Tor count each low level |
| 1 : Tor count each high level|
| unsigned char_ b_ExternGate : Extern gate action selection |
| 0 : Extern gate signal not |
| used |
| 1 : Extern gate signal used. |
| If you selected the |
| single mode, each high |
| level signal start the |
| counter. |
| If you selected the |
| continuous mode, the |
| first high level signal |
| start the tor counter |
| |
| APCI1710_TOR_QUADRUPLE _MODE : |
| In the quadruple mode, the edge|
| analysis circuit generates a |
| counting pulse from each edge |
| of 2 signals which are phase |
| shifted in relation to each |
| other. |
| The gate input is used for the |
| signal B |
| |
| APCI1710_TOR_DOUBLE_MODE: |
| Functions in the same way as |
| the quadruple mode, except that|
| only two of the four edges are |
| analysed per period. |
| The gate input is used for the |
| signal B |
| |
| APCI1710_TOR_SIMPLE_MODE: |
| Functions in the same way as |
| the quadruple mode, except that|
| only one of the four edges is |
| analysed per period. |
| The gate input is used for the |
| signal B |
| |
| unsigned char_ b_CycleMode : Selected the tor counter |
| acquisition mode |
| unsigned char_ b_InterruptEnable : Enable or disable the |
| tor counter interrupt. |
| APCI1710_ENABLE: |
| Enable the tor counter |
| interrupt |
| APCI1710_DISABLE: |
| Disable the tor counter |
| interrupt |
+----------------------------------------------------------------------------+
| Output Parameters : - |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
| -6: Tor input signal selection is wrong |
| -7: Extern gate signal mode is wrong |
| -8: Tor counter acquisition mode cycle is wrong |
| -9: Interrupt parameter is wrong |
| -10:Interrupt function not initialised. |
| See function "i_APCI1710_SetBoardIntRoutineX" |
+----------------------------------------------------------------------------+
*/
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_DisableTorCounter |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter) |
+----------------------------------------------------------------------------+
| Task : Disable the tor counter (b_TorCounter) from selected |
| module (b_ModulNbr). If you disable the tor counter |
| after a start cycle occur and you restart the tor |
| counter witch the " i_APCI1710_EnableTorCounter" |
| function, the status register is cleared |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1). |
+----------------------------------------------------------------------------+
| Output Parameters : - |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
| -6: Tor counter not enabled see function |
| "i_APCI1710_EnableTorCounter" |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnWriteEnableDisableTorCounter(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_Status;
unsigned int dw_DummyRead;
unsigned int dw_ConfigReg;
unsigned char b_ModulNbr, b_Action;
unsigned char b_TorCounter;
unsigned char b_InputMode;
unsigned char b_ExternGate;
unsigned char b_CycleMode;
unsigned char b_InterruptEnable;
b_ModulNbr = (unsigned char) CR_AREF(insn->chanspec);
b_Action = (unsigned char) data[0]; /* enable or disable */
b_TorCounter = (unsigned char) data[1];
b_InputMode = (unsigned char) data[2];
b_ExternGate = (unsigned char) data[3];
b_CycleMode = (unsigned char) data[4];
b_InterruptEnable = (unsigned char) data[5];
i_ReturnValue = insn->n;
devpriv->tsk_Current = current; /* Save the current process task structure */
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
switch (b_Action) /* Enable or Disable */
{
case APCI1710_ENABLE:
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status =
inl(devpriv->s_BoardInfos.
ui_Address + 8 +
(16 * b_TorCounter) +
(64 * b_ModulNbr));
if (dw_Status & 0x10) {
/******************************/
/* Test the input signal mode */
/******************************/
if (b_InputMode == 0 ||
b_InputMode == 1 ||
b_InputMode ==
APCI1710_TOR_SIMPLE_MODE
|| b_InputMode ==
APCI1710_TOR_DOUBLE_MODE
|| b_InputMode ==
APCI1710_TOR_QUADRUPLE_MODE)
{
/************************************/
/* Test the extern gate signal mode */
/************************************/
if (b_ExternGate == 0
|| b_ExternGate
== 1
|| b_InputMode >
1) {
/*********************************/
/* Test the cycle mode parameter */
/*********************************/
if ((b_CycleMode == APCI1710_SINGLE) || (b_CycleMode == APCI1710_CONTINUOUS)) {
/***************************/
/* Test the interrupt flag */
/***************************/
if ((b_InterruptEnable == APCI1710_ENABLE) || (b_InterruptEnable == APCI1710_DISABLE)) {
/***************************/
/* Save the interrupt mode */
/***************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_InterruptEnable
=
b_InterruptEnable;
/*******************/
/* Get the command */
/*******************/
dw_ConfigReg
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
4
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
dw_ConfigReg
=
(dw_ConfigReg
>>
4)
&
0x30;
/********************************/
/* Test if not direct mode used */
/********************************/
if (b_InputMode > 1) {
/*******************************/
/* Extern gate can not be used */
/*******************************/
b_ExternGate
=
0;
/*******************************************/
/* Enable the extern gate for the Signal B */
/*******************************************/
dw_ConfigReg
=
dw_ConfigReg
|
0x40;
/***********************/
/* Test if simple mode */
/***********************/
if (b_InputMode == APCI1710_TOR_SIMPLE_MODE) {
/**************************/
/* Enable the sinple mode */
/**************************/
dw_ConfigReg
=
dw_ConfigReg
|
0x780;
} /* if (b_InputMode == APCI1710_TOR_SIMPLE_MODE) */
/***********************/
/* Test if double mode */
/***********************/
if (b_InputMode == APCI1710_TOR_DOUBLE_MODE) {
/**************************/
/* Enable the double mode */
/**************************/
dw_ConfigReg
=
dw_ConfigReg
|
0x180;
} /* if (b_InputMode == APCI1710_TOR_DOUBLE_MODE) */
b_InputMode
=
0;
} /* if (b_InputMode > 1) */
/*******************/
/* Set the command */
/*******************/
dw_ConfigReg
=
dw_ConfigReg
|
b_CycleMode
|
(b_InterruptEnable
*
2)
|
(b_InputMode
*
4)
|
(b_ExternGate
*
8);
/*****************************/
/* Clear the status register */
/*****************************/
dw_DummyRead
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
0
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
/***************************************/
/* Clear the interrupt status register */
/***************************************/
dw_DummyRead
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
12
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
/********************/
/* Set the commando */
/********************/
outl(dw_ConfigReg, devpriv->s_BoardInfos.ui_Address + 4 + (16 * b_TorCounter) + (64 * b_ModulNbr));
/****************/
/* Set the gate */
/****************/
outl(1, devpriv->s_BoardInfos.ui_Address + 8 + (16 * b_TorCounter) + (64 * b_ModulNbr));
} /* if ((b_InterruptEnable == APCI1710_ENABLE) || (b_InterruptEnable == APCI1710_DISABLE)) */
else {
/********************************/
/* Interrupt parameter is wrong */
/********************************/
DPRINTK("Interrupt parameter is wrong\n");
i_ReturnValue
=
-9;
} /* if ((b_InterruptEnable == APCI1710_ENABLE) || (b_InterruptEnable == APCI1710_DISABLE)) */
} /* if ((b_CycleMode == APCI1710_SINGLE) || (b_CycleMode == APCI1710_CONTINUOUS)) */
else {
/***********************************************/
/* Tor counter acquisition mode cycle is wrong */
/***********************************************/
DPRINTK("Tor counter acquisition mode cycle is wrong\n");
i_ReturnValue
=
-8;
} /* if ((b_CycleMode == APCI1710_SINGLE) || (b_CycleMode == APCI1710_CONTINUOUS)) */
} /* if (b_ExternGate >= 0 && b_ExternGate <= 1) */
else {
/***********************************/
/* Extern gate input mode is wrong */
/***********************************/
DPRINTK("Extern gate input mode is wrong\n");
i_ReturnValue =
-7;
} /* if (b_ExternGate >= 0 && b_ExternGate <= 1) */
} /* if (b_InputMode >= 0 && b_InputMode <= 1) */
else {
/***************************************/
/* Tor input signal selection is wrong */
/***************************************/
DPRINTK("Tor input signal selection is wrong\n");
i_ReturnValue = -6;
}
} else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
}
break;
case APCI1710_DISABLE:
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 8 +
(16 * b_TorCounter) +
(64 * b_ModulNbr));
/*******************************/
/* Test if counter initialised */
/*******************************/
if (dw_Status & 0x10) {
/***************************/
/* Test if counter enabled */
/***************************/
if (dw_Status & 0x1) {
/****************************/
/* Clear the interrupt mode */
/****************************/
devpriv->
s_ModuleInfo
[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo
[b_TorCounter].
b_InterruptEnable
=
APCI1710_DISABLE;
/******************/
/* Clear the gate */
/******************/
outl(0, devpriv->
s_BoardInfos.
ui_Address + 8 +
(16 * b_TorCounter) + (64 * b_ModulNbr));
} /* if (dw_Status & 0x1) */
else {
/***************************/
/* Tor counter not enabled */
/***************************/
DPRINTK("Tor counter not enabled \n");
i_ReturnValue = -6;
} /* if (dw_Status & 0x1) */
} /* if (dw_Status & 0x10) */
else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
} /* // if (dw_Status & 0x10) */
} /* switch */
} /* if (b_TorCounter <= 1) */
else {
/**********************************/
/* Tor counter selection is wrong */
/**********************************/
DPRINTK("Tor counter selection is wrong\n");
i_ReturnValue = -4;
} /* if (b_TorCounter <= 1) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module \n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error \n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_GetTorCounterInitialisation |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned char *_ pb_TimingUnit, |
| PULONG_ pul_TimingInterval, |
| unsigned char *_ pb_InputMode, |
| unsigned char *_ pb_ExternGate, |
| unsigned char *_ pb_CycleMode, |
| unsigned char *_ pb_Enable, |
| unsigned char *_ pb_InterruptEnable)|
+----------------------------------------------------------------------------+
| Task : Enable the tor counter (b_TorCounter) from selected |
| module (b_ModulNbr). You must calling the |
| "i_APCI1710_InitTorCounter" function be for you call |
| this function. |
| If you enable the tor counter interrupt, the |
| tor counter generate a interrupt after the timing cycle|
| See function "i_APCI1710_SetBoardIntRoutineX" and the |
| Interrupt mask description chapter from this manual. |
| The b_CycleMode parameter determine if you will |
| measured a single or more cycle. |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1)
b_ModulNbr = CR_AREF(insn->chanspec);
b_TorCounter = CR_CHAN(insn->chanspec);
. |
+----------------------------------------------------------------------------+
| Output Parameters : unsigned char *_ pb_TimingUnit : Base timing unit (0 to 4) |
| 0 : ns |
| 1 : µs |
| 2 : ms |
| 3 : s |
| 4 : mn |
| PULONG_ pul_TimingInterval : Base timing value. |
| unsigned char *_ pb_InputMode : Input signal level |
| selection |
| 0 : Tor count each low level |
| 1 : Tor count each high level|
| unsigned char *_ pb_ExternGate : Extern gate action |
| selection |
| 0 : Extern gate signal not |
| used |
| 1 : Extern gate signal used|
| unsigned char *_ pb_CycleMode : Tor counter acquisition |
| mode |
| unsigned char *_ pb_Enable : Indicate if the tor counter|
| is enabled or no |
| 0 : Tor counter disabled |
| 1 : Tor counter enabled |
| unsigned char *_ pb_InterruptEnable : Enable or disable the |
| tor counter interrupt. |
| APCI1710_ENABLE: |
| Enable the tor counter |
| interrupt |
| APCI1710_DISABLE: |
| Disable the tor counter |
| interrupt
pb_TimingUnit = (unsigned char *) &data[0];
pul_TimingInterval = (unsigned int *) &data[1];
pb_InputMode = (unsigned char *) &data[2];
pb_ExternGate = (unsigned char *) &data[3];
pb_CycleMode = (unsigned char *) &data[4];
pb_Enable = (unsigned char *) &data[5];
pb_InterruptEnable = (unsigned char *) &data[6];
|
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnReadGetTorCounterInitialisation(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_Status;
unsigned char b_ModulNbr;
unsigned char b_TorCounter;
unsigned char *pb_TimingUnit;
unsigned int *pul_TimingInterval;
unsigned char *pb_InputMode;
unsigned char *pb_ExternGate;
unsigned char *pb_CycleMode;
unsigned char *pb_Enable;
unsigned char *pb_InterruptEnable;
i_ReturnValue = insn->n;
b_ModulNbr = CR_AREF(insn->chanspec);
b_TorCounter = CR_CHAN(insn->chanspec);
pb_TimingUnit = (unsigned char *) &data[0];
pul_TimingInterval = (unsigned int *) &data[1];
pb_InputMode = (unsigned char *) &data[2];
pb_ExternGate = (unsigned char *) &data[3];
pb_CycleMode = (unsigned char *) &data[4];
pb_Enable = (unsigned char *) &data[5];
pb_InterruptEnable = (unsigned char *) &data[6];
/**************************/
/* Test the module number */
/**************************/
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 8 + (16 * b_TorCounter) +
(64 * b_ModulNbr));
if (dw_Status & 0x10) {
*pb_Enable = dw_Status & 1;
/********************/
/* Get the commando */
/********************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 4 +
(16 * b_TorCounter) +
(64 * b_ModulNbr));
*pb_CycleMode =
(unsigned char) ((dw_Status >> 4) & 1);
*pb_InterruptEnable =
(unsigned char) ((dw_Status >> 5) & 1);
/******************************************************/
/* Test if extern gate used for clock or for signal B */
/******************************************************/
if (dw_Status & 0x600) {
/*****************************************/
/* Test if extern gate used for signal B */
/*****************************************/
if (dw_Status & 0x400) {
/***********************/
/* Test if simple mode */
/***********************/
if ((dw_Status & 0x7800)
== 0x7800) {
*pb_InputMode =
APCI1710_TOR_SIMPLE_MODE;
}
/***********************/
/* Test if double mode */
/***********************/
if ((dw_Status & 0x7800)
== 0x1800) {
*pb_InputMode =
APCI1710_TOR_DOUBLE_MODE;
}
/**************************/
/* Test if quadruple mode */
/**************************/
if ((dw_Status & 0x7800)
== 0x0000) {
*pb_InputMode =
APCI1710_TOR_QUADRUPLE_MODE;
}
} /* if (dw_Status & 0x400) */
else {
*pb_InputMode = 1;
} /* // if (dw_Status & 0x400) */
/************************/
/* Extern gate not used */
/************************/
*pb_ExternGate = 0;
} /* if (dw_Status & 0x600) */
else {
*pb_InputMode =
(unsigned char) ((dw_Status >> 6)
& 1);
*pb_ExternGate =
(unsigned char) ((dw_Status >> 7)
& 1);
} /* if (dw_Status & 0x600) */
*pb_TimingUnit =
devpriv->
s_ModuleInfo[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo[b_TorCounter].
b_TimingUnit;
*pul_TimingInterval =
devpriv->
s_ModuleInfo[b_ModulNbr].
s_TorCounterModuleInfo.
s_TorCounterInfo[b_TorCounter].
ul_RealTimingInterval;
} else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
}
} /* if (b_TorCounter <= 1) */
else {
/**********************************/
/* Tor counter selection is wrong */
/**********************************/
DPRINTK("Tor counter selection is wrong \n");
i_ReturnValue = -4;
} /* if (b_TorCounter <= 1) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
/*
+----------------------------------------------------------------------------+
| Function Name : _INT_ i_APCI1710_ReadTorCounterValue |
| (unsigned char_ b_BoardHandle, |
| unsigned char_ b_ModulNbr, |
| unsigned char_ b_TorCounter, |
| unsigned int_ ui_TimeOut, |
| unsigned char *_ pb_TorCounterStatus, |
| PULONG_ pul_TorCounterValue) |
+----------------------------------------------------------------------------+
| Task case APCI1710_TOR_GETPROGRESSSTATUS: Return the tor counter
(b_TorCounter) status (pb_TorCounterStatus) from selected tor counter |
| module (b_ModulNbr).
case APCI1710_TOR_GETCOUNTERVALUE :
Return the tor counter (b_TorCounter) status |
| (pb_TorCounterStatus) and the timing value |
| (pul_TorCounterValue) after a conting cycle stop |
| from selected tor counter module (b_ModulNbr). |
+----------------------------------------------------------------------------+
| Input Parameters : unsigned char_ b_BoardHandle : Handle of board APCI-1710 |
| unsigned char_ b_ModulNbr : Selected module number (0 to 3) |
| unsigned char_ b_TorCounter : Tor counter selection (0 or 1).
b_ModulNbr = CR_AREF(insn->chanspec);
b_ReadType = (unsigned char) data[0];
b_TorCounter = (unsigned char) data[1];
ui_TimeOut = (unsigned int) data[2]; |
+----------------------------------------------------------------------------+
| Output Parameters : unsigned char *_ pb_TorCounterStatus : Return the tor counter |
| status. |
| 0 : Conting cycle not started|
| Software gate not set. |
| 1 : Conting cycle started. |
| Software gate set. |
| 2 : Conting cycle stopped. |
| The conting cycle is |
| terminate. |
| 3 : A overflow occur. You |
| must change the base |
| timing witch the |
| function |
| "i_APCI1710_InitTorCounter"|
| 4 : Timeeout occur |
| unsigned int * pul_TorCounterValue : Tor counter value.
pb_TorCounterStatus=(unsigned char *) &data[0];
pul_TorCounterValue=(unsigned int *) &data[1]; |
+----------------------------------------------------------------------------+
| Return Value : 0: No error |
| -1: The handle parameter of the board is wrong |
| -2: Module selection wrong |
| -3: The module is not a tor counter module |
| -4: Tor counter selection is wrong |
| -5: Tor counter not initialised see function |
| "i_APCI1710_InitTorCounter" |
| -6: Tor counter not enabled see function |
| "i_APCI1710_EnableTorCounter" |
| -7: Timeout parameter is wrong (0 to 65535) |
+----------------------------------------------------------------------------+
*/
int i_APCI1710_InsnBitsGetTorCounterProgressStatusAndValue(struct comedi_device *dev,
struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data)
{
int i_ReturnValue = 0;
unsigned int dw_Status;
unsigned int dw_TimeOut = 0;
unsigned char b_ModulNbr;
unsigned char b_TorCounter;
unsigned char b_ReadType;
unsigned int ui_TimeOut;
unsigned char *pb_TorCounterStatus;
unsigned int *pul_TorCounterValue;
i_ReturnValue = insn->n;
b_ModulNbr = CR_AREF(insn->chanspec);
b_ReadType = (unsigned char) data[0];
b_TorCounter = (unsigned char) data[1];
ui_TimeOut = (unsigned int) data[2];
pb_TorCounterStatus = (unsigned char *) &data[0];
pul_TorCounterValue = (unsigned int *) &data[1];
/**************************/
/* Test the module number */
/**************************/
if (b_ReadType == APCI1710_TOR_READINTERRUPT) {
data[0] = devpriv->s_InterruptParameters.
s_FIFOInterruptParameters[devpriv->
s_InterruptParameters.ui_Read].b_OldModuleMask;
data[1] = devpriv->s_InterruptParameters.
s_FIFOInterruptParameters[devpriv->
s_InterruptParameters.ui_Read].ul_OldInterruptMask;
data[2] = devpriv->s_InterruptParameters.
s_FIFOInterruptParameters[devpriv->
s_InterruptParameters.ui_Read].ul_OldCounterLatchValue;
/**************************/
/* Increment the read FIFO */
/***************************/
devpriv->
s_InterruptParameters.
ui_Read = (devpriv->
s_InterruptParameters.
ui_Read + 1) % APCI1710_SAVE_INTERRUPT;
return insn->n;
}
if (b_ModulNbr < 4) {
/***********************/
/* Test if tor counter */
/***********************/
if ((devpriv->s_BoardInfos.
dw_MolduleConfiguration[b_ModulNbr] &
0xFFFF0000UL) == APCI1710_TOR_COUNTER) {
/**********************************/
/* Test the tor counter selection */
/**********************************/
if (b_TorCounter <= 1) {
/***********************************/
/* Test if tor counter initialised */
/***********************************/
dw_Status = inl(devpriv->s_BoardInfos.
ui_Address + 8 + (16 * b_TorCounter) +
(64 * b_ModulNbr));
/*******************************/
/* Test if counter initialised */
/*******************************/
if (dw_Status & 0x10) {
/***************************/
/* Test if counter enabled */
/***************************/
if (dw_Status & 0x1) {
switch (b_ReadType) {
case APCI1710_TOR_GETPROGRESSSTATUS:
/*******************/
/* Read the status */
/*******************/
dw_Status =
inl(devpriv->
s_BoardInfos.
ui_Address + 4 +
(16 * b_TorCounter) + (64 * b_ModulNbr));
dw_Status =
dw_Status & 0xF;
/*****************/
/* Test if start */
/*****************/
if (dw_Status & 1) {
if (dw_Status &
2) {
if (dw_Status & 4) {
/************************/
/* Tor counter overflow */
/************************/
*pb_TorCounterStatus
=
3;
} else {
/***********************/
/* Tor counter started */
/***********************/
*pb_TorCounterStatus
=
2;
}
} else {
/***********************/
/* Tor counter started */
/***********************/
*pb_TorCounterStatus
=
1;
}
} else {
/***************************/
/* Tor counter not started */
/***************************/
*pb_TorCounterStatus
= 0;
}
break;
case APCI1710_TOR_GETCOUNTERVALUE:
/*****************************/
/* Test the timout parameter */
/*****************************/
if ((ui_TimeOut >= 0)
&& (ui_TimeOut
<=
65535UL))
{
for (;;) {
/*******************/
/* Read the status */
/*******************/
dw_Status
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
4
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
/********************/
/* Test if overflow */
/********************/
if ((dw_Status & 4) == 4) {
/******************/
/* Overflow occur */
/******************/
*pb_TorCounterStatus
=
3;
/******************/
/* Read the value */
/******************/
*pul_TorCounterValue
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
0
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
break;
} /* if ((dw_Status & 4) == 4) */
else {
/*******************************/
/* Test if measurement stopped */
/*******************************/
if ((dw_Status & 2) == 2) {
/***********************/
/* A stop signal occur */
/***********************/
*pb_TorCounterStatus
=
2;
/******************/
/* Read the value */
/******************/
*pul_TorCounterValue
=
inl
(devpriv->
s_BoardInfos.
ui_Address
+
0
+
(16 * b_TorCounter) + (64 * b_ModulNbr));
break;
} /* if ((dw_Status & 2) == 2) */
else {
/*******************************/
/* Test if measurement started */
/*******************************/
if ((dw_Status & 1) == 1) {
/************************/
/* A start signal occur */
/************************/
*pb_TorCounterStatus
=
1;
} /* if ((dw_Status & 1) == 1) */
else {
/***************************/
/* Measurement not started */
/***************************/
*pb_TorCounterStatus
=
0;
} /* if ((dw_Status & 1) == 1) */
} /* if ((dw_Status & 2) == 2) */
} /* if ((dw_Status & 8) == 8) */
if (dw_TimeOut == ui_TimeOut) {
/*****************/
/* Timeout occur */
/*****************/
break;
} else {
/*************************/
/* Increment the timeout */
/*************************/
dw_TimeOut
=
dw_TimeOut
+
1;
mdelay(1000);
}
} /* for (;;) */
/*************************/
/* Test if timeout occur */
/*************************/
if ((*pb_TorCounterStatus != 3) && (dw_TimeOut == ui_TimeOut) && (ui_TimeOut != 0)) {
/*****************/
/* Timeout occur */
/*****************/
*pb_TorCounterStatus
=
4;
}
} else {
/******************************/
/* Timeout parameter is wrong */
/******************************/
DPRINTK("Timeout parameter is wrong\n");
i_ReturnValue =
-7;
}
break;
default:
printk("Inputs wrong\n");
} /* switch end */
} /* if (dw_Status & 0x1) */
else {
/***************************/
/* Tor counter not enabled */
/***************************/
DPRINTK("Tor counter not enabled\n");
i_ReturnValue = -6;
} /* if (dw_Status & 0x1) */
} else {
/*******************************/
/* Tor counter not initialised */
/*******************************/
DPRINTK("Tor counter not initialised\n");
i_ReturnValue = -5;
}
} /* if (b_TorCounter <= 1) */
else {
/**********************************/
/* Tor counter selection is wrong */
/**********************************/
DPRINTK("Tor counter selection is wrong\n");
i_ReturnValue = -4;
} /* if (b_TorCounter <= 1) */
} else {
/******************************************/
/* The module is not a tor counter module */
/******************************************/
DPRINTK("The module is not a tor counter module\n");
i_ReturnValue = -3;
}
} else {
/***********************/
/* Module number error */
/***********************/
DPRINTK("Module number error\n");
i_ReturnValue = -2;
}
return i_ReturnValue;
}
| gpl-2.0 |
qtekfun/htcDesire820Kernel | kernel/drivers/isdn/hisax/l3dss1.c | 9553 | 78840 | /* $Id: l3dss1.c,v 2.32.2.3 2004/01/13 14:31:25 keil Exp $
*
* EURO/DSS1 D-channel protocol
*
* German 1TR6 D-channel protocol
*
* Author Karsten Keil
* based on the teles driver from Jan den Ouden
* Copyright by Karsten Keil <keil@isdn4linux.de>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
* For changes and modifications please read
* Documentation/isdn/HiSax.cert
*
* Thanks to Jan den Ouden
* Fritz Elfert
*
*/
#include "hisax.h"
#include "isdnl3.h"
#include "l3dss1.h"
#include <linux/ctype.h>
#include <linux/slab.h>
extern char *HiSax_getrev(const char *revision);
static const char *dss1_revision = "$Revision: 2.32.2.3 $";
#define EXT_BEARER_CAPS 1
#define MsgHead(ptr, cref, mty) \
*ptr++ = 0x8; \
if (cref == -1) { \
*ptr++ = 0x0; \
} else { \
*ptr++ = 0x1; \
*ptr++ = cref^0x80; \
} \
*ptr++ = mty
/**********************************************/
/* get a new invoke id for remote operations. */
/* Only a return value != 0 is valid */
/**********************************************/
static unsigned char new_invoke_id(struct PStack *p)
{
unsigned char retval;
int i;
i = 32; /* maximum search depth */
retval = p->prot.dss1.last_invoke_id + 1; /* try new id */
while ((i) && (p->prot.dss1.invoke_used[retval >> 3] == 0xFF)) {
p->prot.dss1.last_invoke_id = (retval & 0xF8) + 8;
i--;
}
if (i) {
while (p->prot.dss1.invoke_used[retval >> 3] & (1 << (retval & 7)))
retval++;
} else
retval = 0;
p->prot.dss1.last_invoke_id = retval;
p->prot.dss1.invoke_used[retval >> 3] |= (1 << (retval & 7));
return (retval);
} /* new_invoke_id */
/*************************/
/* free a used invoke id */
/*************************/
static void free_invoke_id(struct PStack *p, unsigned char id)
{
if (!id) return; /* 0 = invalid value */
p->prot.dss1.invoke_used[id >> 3] &= ~(1 << (id & 7));
} /* free_invoke_id */
/**********************************************************/
/* create a new l3 process and fill in dss1 specific data */
/**********************************************************/
static struct l3_process
*dss1_new_l3_process(struct PStack *st, int cr)
{ struct l3_process *proc;
if (!(proc = new_l3_process(st, cr)))
return (NULL);
proc->prot.dss1.invoke_id = 0;
proc->prot.dss1.remote_operation = 0;
proc->prot.dss1.uus1_data[0] = '\0';
return (proc);
} /* dss1_new_l3_process */
/************************************************/
/* free a l3 process and all dss1 specific data */
/************************************************/
static void
dss1_release_l3_process(struct l3_process *p)
{
free_invoke_id(p->st, p->prot.dss1.invoke_id);
release_l3_process(p);
} /* dss1_release_l3_process */
/********************************************************/
/* search a process with invoke id id and dummy callref */
/********************************************************/
static struct l3_process *
l3dss1_search_dummy_proc(struct PStack *st, int id)
{ struct l3_process *pc = st->l3.proc; /* start of processes */
if (!id) return (NULL);
while (pc)
{ if ((pc->callref == -1) && (pc->prot.dss1.invoke_id == id))
return (pc);
pc = pc->next;
}
return (NULL);
} /* l3dss1_search_dummy_proc */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a return result is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_return_result(struct PStack *st, int id, u_char *p, u_char nlen)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
struct l3_process *pc = NULL;
if ((pc = l3dss1_search_dummy_proc(st, id)))
{ L3DelTimer(&pc->timer); /* remove timer */
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_RES;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = 0;
ic.parm.dss1_io.datalen = nlen;
ic.parm.dss1_io.data = p;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
}
else
l3_debug(st, "dummy return result id=0x%x result len=%d", id, nlen);
} /* l3dss1_dummy_return_result */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a return error is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_error_return(struct PStack *st, int id, ulong error)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
struct l3_process *pc = NULL;
if ((pc = l3dss1_search_dummy_proc(st, id)))
{ L3DelTimer(&pc->timer); /* remove timer */
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_ERR;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = error;
ic.parm.dss1_io.datalen = 0;
ic.parm.dss1_io.data = NULL;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
}
else
l3_debug(st, "dummy return error id=0x%x error=0x%lx", id, error);
} /* l3dss1_error_return */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a invoke is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_invoke(struct PStack *st, int cr, int id,
int ident, u_char *p, u_char nlen)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
l3_debug(st, "dummy invoke %s id=0x%x ident=0x%x datalen=%d",
(cr == -1) ? "local" : "broadcast", id, ident, nlen);
if (cr >= -1) return; /* ignore local data */
cs = st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_BRD;
ic.parm.dss1_io.hl_id = id;
ic.parm.dss1_io.ll_id = 0;
ic.parm.dss1_io.proc = ident;
ic.parm.dss1_io.timeout = 0;
ic.parm.dss1_io.datalen = nlen;
ic.parm.dss1_io.data = p;
cs->iif.statcallb(&ic);
} /* l3dss1_dummy_invoke */
static void
l3dss1_parse_facility(struct PStack *st, struct l3_process *pc,
int cr, u_char *p)
{
int qd_len = 0;
unsigned char nlen = 0, ilen, cp_tag;
int ident, id;
ulong err_ret;
if (pc)
st = pc->st; /* valid Stack */
else
if ((!st) || (cr >= 0)) return; /* neither pc nor st specified */
p++;
qd_len = *p++;
if (qd_len == 0) {
l3_debug(st, "qd_len == 0");
return;
}
if ((*p & 0x1F) != 0x11) { /* Service discriminator, supplementary service */
l3_debug(st, "supplementary service != 0x11");
return;
}
while (qd_len > 0 && !(*p & 0x80)) { /* extension ? */
p++;
qd_len--;
}
if (qd_len < 2) {
l3_debug(st, "qd_len < 2");
return;
}
p++;
qd_len--;
if ((*p & 0xE0) != 0xA0) { /* class and form */
l3_debug(st, "class and form != 0xA0");
return;
}
cp_tag = *p & 0x1F; /* remember tag value */
p++;
qd_len--;
if (qd_len < 1)
{ l3_debug(st, "qd_len < 1");
return;
}
if (*p & 0x80)
{ /* length format indefinite or limited */
nlen = *p++ & 0x7F; /* number of len bytes or indefinite */
if ((qd_len-- < ((!nlen) ? 3 : (1 + nlen))) ||
(nlen > 1))
{ l3_debug(st, "length format error or not implemented");
return;
}
if (nlen == 1)
{ nlen = *p++; /* complete length */
qd_len--;
}
else
{ qd_len -= 2; /* trailing null bytes */
if ((*(p + qd_len)) || (*(p + qd_len + 1)))
{ l3_debug(st, "length format indefinite error");
return;
}
nlen = qd_len;
}
}
else
{ nlen = *p++;
qd_len--;
}
if (qd_len < nlen)
{ l3_debug(st, "qd_len < nlen");
return;
}
qd_len -= nlen;
if (nlen < 2)
{ l3_debug(st, "nlen < 2");
return;
}
if (*p != 0x02)
{ /* invoke identifier tag */
l3_debug(st, "invoke identifier tag !=0x02");
return;
}
p++;
nlen--;
if (*p & 0x80)
{ /* length format */
l3_debug(st, "invoke id length format 2");
return;
}
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0)
{ l3_debug(st, "ilen > nlen || ilen == 0");
return;
}
nlen -= ilen;
id = 0;
while (ilen > 0)
{ id = (id << 8) | (*p++ & 0xFF); /* invoke identifier */
ilen--;
}
switch (cp_tag) { /* component tag */
case 1: /* invoke */
if (nlen < 2) {
l3_debug(st, "nlen < 2 22");
return;
}
if (*p != 0x02) { /* operation value */
l3_debug(st, "operation value !=0x02");
return;
}
p++;
nlen--;
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0) {
l3_debug(st, "ilen > nlen || ilen == 0 22");
return;
}
nlen -= ilen;
ident = 0;
while (ilen > 0) {
ident = (ident << 8) | (*p++ & 0xFF);
ilen--;
}
if (!pc)
{ l3dss1_dummy_invoke(st, cr, id, ident, p, nlen);
return;
}
#ifdef CONFIG_DE_AOC
{
#define FOO1(s, a, b) \
while (nlen > 1) { \
int ilen = p[1]; \
if (nlen < ilen + 2) { \
l3_debug(st, "FOO1 nlen < ilen+2"); \
return; \
} \
nlen -= ilen + 2; \
if ((*p & 0xFF) == (a)) { \
int nlen = ilen; \
p += 2; \
b; \
} else { \
p += ilen + 2; \
} \
}
switch (ident) {
case 0x22: /* during */
FOO1("1A", 0x30, FOO1("1C", 0xA1, FOO1("1D", 0x30, FOO1("1E", 0x02, ( {
ident = 0;
nlen = (nlen) ? nlen : 0; /* Make gcc happy */
while (ilen > 0) {
ident = (ident << 8) | *p++;
ilen--;
}
if (ident > pc->para.chargeinfo) {
pc->para.chargeinfo = ident;
st->l3.l3l4(st, CC_CHARGE | INDICATION, pc);
}
if (st->l3.debug & L3_DEB_CHARGE) {
if (*(p + 2) == 0) {
l3_debug(st, "charging info during %d", pc->para.chargeinfo);
}
else {
l3_debug(st, "charging info final %d", pc->para.chargeinfo);
}
}
}
)))))
break;
case 0x24: /* final */
FOO1("2A", 0x30, FOO1("2B", 0x30, FOO1("2C", 0xA1, FOO1("2D", 0x30, FOO1("2E", 0x02, ( {
ident = 0;
nlen = (nlen) ? nlen : 0; /* Make gcc happy */
while (ilen > 0) {
ident = (ident << 8) | *p++;
ilen--;
}
if (ident > pc->para.chargeinfo) {
pc->para.chargeinfo = ident;
st->l3.l3l4(st, CC_CHARGE | INDICATION, pc);
}
if (st->l3.debug & L3_DEB_CHARGE) {
l3_debug(st, "charging info final %d", pc->para.chargeinfo);
}
}
))))))
break;
default:
l3_debug(st, "invoke break invalid ident %02x", ident);
break;
}
#undef FOO1
}
#else /* not CONFIG_DE_AOC */
l3_debug(st, "invoke break");
#endif /* not CONFIG_DE_AOC */
break;
case 2: /* return result */
/* if no process available handle separately */
if (!pc)
{ if (cr == -1)
l3dss1_dummy_return_result(st, id, p, nlen);
return;
}
if ((pc->prot.dss1.invoke_id) && (pc->prot.dss1.invoke_id == id))
{ /* Diversion successful */
free_invoke_id(st, pc->prot.dss1.invoke_id);
pc->prot.dss1.remote_result = 0; /* success */
pc->prot.dss1.invoke_id = 0;
pc->redir_result = pc->prot.dss1.remote_result;
st->l3.l3l4(st, CC_REDIR | INDICATION, pc); } /* Diversion successful */
else
l3_debug(st, "return error unknown identifier");
break;
case 3: /* return error */
err_ret = 0;
if (nlen < 2)
{ l3_debug(st, "return error nlen < 2");
return;
}
if (*p != 0x02)
{ /* result tag */
l3_debug(st, "invoke error tag !=0x02");
return;
}
p++;
nlen--;
if (*p > 4)
{ /* length format */
l3_debug(st, "invoke return errlen > 4 ");
return;
}
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0)
{ l3_debug(st, "error return ilen > nlen || ilen == 0");
return;
}
nlen -= ilen;
while (ilen > 0)
{ err_ret = (err_ret << 8) | (*p++ & 0xFF); /* error value */
ilen--;
}
/* if no process available handle separately */
if (!pc)
{ if (cr == -1)
l3dss1_dummy_error_return(st, id, err_ret);
return;
}
if ((pc->prot.dss1.invoke_id) && (pc->prot.dss1.invoke_id == id))
{ /* Deflection error */
free_invoke_id(st, pc->prot.dss1.invoke_id);
pc->prot.dss1.remote_result = err_ret; /* result */
pc->prot.dss1.invoke_id = 0;
pc->redir_result = pc->prot.dss1.remote_result;
st->l3.l3l4(st, CC_REDIR | INDICATION, pc);
} /* Deflection error */
else
l3_debug(st, "return result unknown identifier");
break;
default:
l3_debug(st, "facility default break tag=0x%02x", cp_tag);
break;
}
}
static void
l3dss1_message(struct l3_process *pc, u_char mt)
{
struct sk_buff *skb;
u_char *p;
if (!(skb = l3_alloc_skb(4)))
return;
p = skb_put(skb, 4);
MsgHead(p, pc->callref, mt);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_message_cause(struct l3_process *pc, u_char mt, u_char cause)
{
struct sk_buff *skb;
u_char tmp[16];
u_char *p = tmp;
int l;
MsgHead(p, pc->callref, mt);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_status_send(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
MsgHead(p, pc->callref, MT_STATUS);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = pc->para.cause | 0x80;
*p++ = IE_CALL_STATE;
*p++ = 0x1;
*p++ = pc->state & 0x3f;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_msg_without_setup(struct l3_process *pc, u_char pr, void *arg)
{
/* This routine is called if here was no SETUP made (checks in dss1up and in
* l3dss1_setup) and a RELEASE_COMPLETE have to be sent with an error code
* MT_STATUS_ENQUIRE in the NULL state is handled too
*/
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
switch (pc->para.cause) {
case 81: /* invalid callreference */
case 88: /* incomp destination */
case 96: /* mandory IE missing */
case 100: /* invalid IE contents */
case 101: /* incompatible Callstate */
MsgHead(p, pc->callref, MT_RELEASE_COMPLETE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = pc->para.cause | 0x80;
break;
default:
printk(KERN_ERR "HiSax l3dss1_msg_without_setup wrong cause %d\n",
pc->para.cause);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
dss1_release_l3_process(pc);
}
static int ie_ALERTING[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, IE_HLC,
IE_USER_USER, -1};
static int ie_CALL_PROCEEDING[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_HLC, -1};
static int ie_CONNECT[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_DATE, IE_SIGNAL,
IE_CONNECT_PN, IE_CONNECT_SUB, IE_LLC, IE_HLC, IE_USER_USER, -1};
static int ie_CONNECT_ACKNOWLEDGE[] = {IE_CHANNEL_ID, IE_DISPLAY, IE_SIGNAL, -1};
static int ie_DISCONNECT[] = {IE_CAUSE | IE_MANDATORY, IE_FACILITY,
IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, IE_USER_USER, -1};
static int ie_INFORMATION[] = {IE_COMPLETE, IE_DISPLAY, IE_KEYPAD, IE_SIGNAL,
IE_CALLED_PN, -1};
static int ie_NOTIFY[] = {IE_BEARER, IE_NOTIFY | IE_MANDATORY, IE_DISPLAY, -1};
static int ie_PROGRESS[] = {IE_BEARER, IE_CAUSE, IE_FACILITY, IE_PROGRESS |
IE_MANDATORY, IE_DISPLAY, IE_HLC, IE_USER_USER, -1};
static int ie_RELEASE[] = {IE_CAUSE | IE_MANDATORY_1, IE_FACILITY, IE_DISPLAY,
IE_SIGNAL, IE_USER_USER, -1};
/* a RELEASE_COMPLETE with errors don't require special actions
static int ie_RELEASE_COMPLETE[] = {IE_CAUSE | IE_MANDATORY_1, IE_DISPLAY, IE_SIGNAL, IE_USER_USER, -1};
*/
static int ie_RESUME_ACKNOWLEDGE[] = {IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY,
IE_DISPLAY, -1};
static int ie_RESUME_REJECT[] = {IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
static int ie_SETUP[] = {IE_COMPLETE, IE_BEARER | IE_MANDATORY,
IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY, IE_PROGRESS,
IE_NET_FAC, IE_DISPLAY, IE_KEYPAD, IE_SIGNAL, IE_CALLING_PN,
IE_CALLING_SUB, IE_CALLED_PN, IE_CALLED_SUB, IE_REDIR_NR,
IE_LLC, IE_HLC, IE_USER_USER, -1};
static int ie_SETUP_ACKNOWLEDGE[] = {IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY,
IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, -1};
static int ie_STATUS[] = {IE_CAUSE | IE_MANDATORY, IE_CALL_STATE |
IE_MANDATORY, IE_DISPLAY, -1};
static int ie_STATUS_ENQUIRY[] = {IE_DISPLAY, -1};
static int ie_SUSPEND_ACKNOWLEDGE[] = {IE_DISPLAY, IE_FACILITY, -1};
static int ie_SUSPEND_REJECT[] = {IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
/* not used
* static int ie_CONGESTION_CONTROL[] = {IE_CONGESTION | IE_MANDATORY,
* IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
* static int ie_USER_INFORMATION[] = {IE_MORE_DATA, IE_USER_USER | IE_MANDATORY, -1};
* static int ie_RESTART[] = {IE_CHANNEL_ID, IE_DISPLAY, IE_RESTART_IND |
* IE_MANDATORY, -1};
*/
static int ie_FACILITY[] = {IE_FACILITY | IE_MANDATORY, IE_DISPLAY, -1};
static int comp_required[] = {1, 2, 3, 5, 6, 7, 9, 10, 11, 14, 15, -1};
static int l3_valid_states[] = {0, 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 15, 17, 19, 25, -1};
struct ie_len {
int ie;
int len;
};
static
struct ie_len max_ie_len[] = {
{IE_SEGMENT, 4},
{IE_BEARER, 12},
{IE_CAUSE, 32},
{IE_CALL_ID, 10},
{IE_CALL_STATE, 3},
{IE_CHANNEL_ID, 34},
{IE_FACILITY, 255},
{IE_PROGRESS, 4},
{IE_NET_FAC, 255},
{IE_NOTIFY, 3},
{IE_DISPLAY, 82},
{IE_DATE, 8},
{IE_KEYPAD, 34},
{IE_SIGNAL, 3},
{IE_INFORATE, 6},
{IE_E2E_TDELAY, 11},
{IE_TDELAY_SEL, 5},
{IE_PACK_BINPARA, 3},
{IE_PACK_WINSIZE, 4},
{IE_PACK_SIZE, 4},
{IE_CUG, 7},
{IE_REV_CHARGE, 3},
{IE_CALLING_PN, 24},
{IE_CALLING_SUB, 23},
{IE_CALLED_PN, 24},
{IE_CALLED_SUB, 23},
{IE_REDIR_NR, 255},
{IE_TRANS_SEL, 255},
{IE_RESTART_IND, 3},
{IE_LLC, 18},
{IE_HLC, 5},
{IE_USER_USER, 131},
{-1, 0},
};
static int
getmax_ie_len(u_char ie) {
int i = 0;
while (max_ie_len[i].ie != -1) {
if (max_ie_len[i].ie == ie)
return (max_ie_len[i].len);
i++;
}
return (255);
}
static int
ie_in_set(struct l3_process *pc, u_char ie, int *checklist) {
int ret = 1;
while (*checklist != -1) {
if ((*checklist & 0xff) == ie) {
if (ie & 0x80)
return (-ret);
else
return (ret);
}
ret++;
checklist++;
}
return (0);
}
static int
check_infoelements(struct l3_process *pc, struct sk_buff *skb, int *checklist)
{
int *cl = checklist;
u_char mt;
u_char *p, ie;
int l, newpos, oldpos;
int err_seq = 0, err_len = 0, err_compr = 0, err_ureg = 0;
u_char codeset = 0;
u_char old_codeset = 0;
u_char codelock = 1;
p = skb->data;
/* skip cr */
p++;
l = (*p++) & 0xf;
p += l;
mt = *p++;
oldpos = 0;
while ((p - skb->data) < skb->len) {
if ((*p & 0xf0) == 0x90) { /* shift codeset */
old_codeset = codeset;
codeset = *p & 7;
if (*p & 0x08)
codelock = 0;
else
codelock = 1;
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE shift%scodeset %d->%d",
codelock ? " locking " : " ", old_codeset, codeset);
p++;
continue;
}
if (!codeset) { /* only codeset 0 */
if ((newpos = ie_in_set(pc, *p, cl))) {
if (newpos > 0) {
if (newpos < oldpos)
err_seq++;
else
oldpos = newpos;
}
} else {
if (ie_in_set(pc, *p, comp_required))
err_compr++;
else
err_ureg++;
}
}
ie = *p++;
if (ie & 0x80) {
l = 1;
} else {
l = *p++;
p += l;
l += 2;
}
if (!codeset && (l > getmax_ie_len(ie)))
err_len++;
if (!codelock) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE shift back codeset %d->%d",
codeset, old_codeset);
codeset = old_codeset;
codelock = 1;
}
}
if (err_compr | err_ureg | err_len | err_seq) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE MT(%x) %d/%d/%d/%d",
mt, err_compr, err_ureg, err_len, err_seq);
if (err_compr)
return (ERR_IE_COMPREHENSION);
if (err_ureg)
return (ERR_IE_UNRECOGNIZED);
if (err_len)
return (ERR_IE_LENGTH);
if (err_seq)
return (ERR_IE_SEQUENCE);
}
return (0);
}
/* verify if a message type exists and contain no IE error */
static int
l3dss1_check_messagetype_validity(struct l3_process *pc, int mt, void *arg)
{
switch (mt) {
case MT_ALERTING:
case MT_CALL_PROCEEDING:
case MT_CONNECT:
case MT_CONNECT_ACKNOWLEDGE:
case MT_DISCONNECT:
case MT_INFORMATION:
case MT_FACILITY:
case MT_NOTIFY:
case MT_PROGRESS:
case MT_RELEASE:
case MT_RELEASE_COMPLETE:
case MT_SETUP:
case MT_SETUP_ACKNOWLEDGE:
case MT_RESUME_ACKNOWLEDGE:
case MT_RESUME_REJECT:
case MT_SUSPEND_ACKNOWLEDGE:
case MT_SUSPEND_REJECT:
case MT_USER_INFORMATION:
case MT_RESTART:
case MT_RESTART_ACKNOWLEDGE:
case MT_CONGESTION_CONTROL:
case MT_STATUS:
case MT_STATUS_ENQUIRY:
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "l3dss1_check_messagetype_validity mt(%x) OK", mt);
break;
case MT_RESUME: /* RESUME only in user->net */
case MT_SUSPEND: /* SUSPEND only in user->net */
default:
if (pc->debug & (L3_DEB_CHECK | L3_DEB_WARN))
l3_debug(pc->st, "l3dss1_check_messagetype_validity mt(%x) fail", mt);
pc->para.cause = 97;
l3dss1_status_send(pc, 0, NULL);
return (1);
}
return (0);
}
static void
l3dss1_std_ie_err(struct l3_process *pc, int ret) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check_infoelements ret %d", ret);
switch (ret) {
case 0:
break;
case ERR_IE_COMPREHENSION:
pc->para.cause = 96;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_UNRECOGNIZED:
pc->para.cause = 99;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_LENGTH:
pc->para.cause = 100;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_SEQUENCE:
default:
break;
}
}
static int
l3dss1_get_channel_id(struct l3_process *pc, struct sk_buff *skb) {
u_char *p;
p = skb->data;
if ((p = findie(p, skb->len, IE_CHANNEL_ID, 0))) {
p++;
if (*p != 1) { /* len for BRI = 1 */
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong chid len %d", *p);
return (-2);
}
p++;
if (*p & 0x60) { /* only base rate interface */
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong chid %x", *p);
return (-3);
}
return (*p & 0x3);
} else
return (-1);
}
static int
l3dss1_get_cause(struct l3_process *pc, struct sk_buff *skb) {
u_char l, i = 0;
u_char *p;
p = skb->data;
pc->para.cause = 31;
pc->para.loc = 0;
if ((p = findie(p, skb->len, IE_CAUSE, 0))) {
p++;
l = *p++;
if (l > 30)
return (1);
if (l) {
pc->para.loc = *p++;
l--;
} else {
return (2);
}
if (l && !(pc->para.loc & 0x80)) {
l--;
p++; /* skip recommendation */
}
if (l) {
pc->para.cause = *p++;
l--;
if (!(pc->para.cause & 0x80))
return (3);
} else
return (4);
while (l && (i < 6)) {
pc->para.diag[i++] = *p++;
l--;
}
} else
return (-1);
return (0);
}
static void
l3dss1_msg_with_uus(struct l3_process *pc, u_char cmd)
{
struct sk_buff *skb;
u_char tmp[16 + 40];
u_char *p = tmp;
int l;
MsgHead(p, pc->callref, cmd);
if (pc->prot.dss1.uus1_data[0])
{ *p++ = IE_USER_USER; /* UUS info element */
*p++ = strlen(pc->prot.dss1.uus1_data) + 1;
*p++ = 0x04; /* IA5 chars */
strcpy(p, pc->prot.dss1.uus1_data);
p += strlen(pc->prot.dss1.uus1_data);
pc->prot.dss1.uus1_data[0] = '\0';
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
} /* l3dss1_msg_with_uus */
static void
l3dss1_release_req(struct l3_process *pc, u_char pr, void *arg)
{
StopAllL3Timer(pc);
newl3state(pc, 19);
if (!pc->prot.dss1.uus1_data[0])
l3dss1_message(pc, MT_RELEASE);
else
l3dss1_msg_with_uus(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_release_cmpl(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb)) > 0) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "RELCMPL get_cause ret(%d)", ret);
} else if (ret < 0)
pc->para.cause = NO_CAUSE;
StopAllL3Timer(pc);
newl3state(pc, 0);
pc->st->l3.l3l4(pc->st, CC_RELEASE | CONFIRM, pc);
dss1_release_l3_process(pc);
}
#ifdef EXT_BEARER_CAPS
static u_char *
EncodeASyncParams(u_char *p, u_char si2)
{ // 7c 06 88 90 21 42 00 bb
p[0] = 0;
p[1] = 0x40; // Intermediate rate: 16 kbit/s jj 2000.02.19
p[2] = 0x80;
if (si2 & 32) // 7 data bits
p[2] += 16;
else // 8 data bits
p[2] += 24;
if (si2 & 16) // 2 stop bits
p[2] += 96;
else // 1 stop bit
p[2] += 32;
if (si2 & 8) // even parity
p[2] += 2;
else // no parity
p[2] += 3;
switch (si2 & 0x07) {
case 0:
p[0] = 66; // 1200 bit/s
break;
case 1:
p[0] = 88; // 1200/75 bit/s
break;
case 2:
p[0] = 87; // 75/1200 bit/s
break;
case 3:
p[0] = 67; // 2400 bit/s
break;
case 4:
p[0] = 69; // 4800 bit/s
break;
case 5:
p[0] = 72; // 9600 bit/s
break;
case 6:
p[0] = 73; // 14400 bit/s
break;
case 7:
p[0] = 75; // 19200 bit/s
break;
}
return p + 3;
}
static u_char
EncodeSyncParams(u_char si2, u_char ai)
{
switch (si2) {
case 0:
return ai + 2; // 1200 bit/s
case 1:
return ai + 24; // 1200/75 bit/s
case 2:
return ai + 23; // 75/1200 bit/s
case 3:
return ai + 3; // 2400 bit/s
case 4:
return ai + 5; // 4800 bit/s
case 5:
return ai + 8; // 9600 bit/s
case 6:
return ai + 9; // 14400 bit/s
case 7:
return ai + 11; // 19200 bit/s
case 8:
return ai + 14; // 48000 bit/s
case 9:
return ai + 15; // 56000 bit/s
case 15:
return ai + 40; // negotiate bit/s
default:
break;
}
return ai;
}
static u_char
DecodeASyncParams(u_char si2, u_char *p)
{
u_char info;
switch (p[5]) {
case 66: // 1200 bit/s
break; // si2 don't change
case 88: // 1200/75 bit/s
si2 += 1;
break;
case 87: // 75/1200 bit/s
si2 += 2;
break;
case 67: // 2400 bit/s
si2 += 3;
break;
case 69: // 4800 bit/s
si2 += 4;
break;
case 72: // 9600 bit/s
si2 += 5;
break;
case 73: // 14400 bit/s
si2 += 6;
break;
case 75: // 19200 bit/s
si2 += 7;
break;
}
info = p[7] & 0x7f;
if ((info & 16) && (!(info & 8))) // 7 data bits
si2 += 32; // else 8 data bits
if ((info & 96) == 96) // 2 stop bits
si2 += 16; // else 1 stop bit
if ((info & 2) && (!(info & 1))) // even parity
si2 += 8; // else no parity
return si2;
}
static u_char
DecodeSyncParams(u_char si2, u_char info)
{
info &= 0x7f;
switch (info) {
case 40: // bit/s negotiation failed ai := 165 not 175!
return si2 + 15;
case 15: // 56000 bit/s failed, ai := 0 not 169 !
return si2 + 9;
case 14: // 48000 bit/s
return si2 + 8;
case 11: // 19200 bit/s
return si2 + 7;
case 9: // 14400 bit/s
return si2 + 6;
case 8: // 9600 bit/s
return si2 + 5;
case 5: // 4800 bit/s
return si2 + 4;
case 3: // 2400 bit/s
return si2 + 3;
case 23: // 75/1200 bit/s
return si2 + 2;
case 24: // 1200/75 bit/s
return si2 + 1;
default: // 1200 bit/s
return si2;
}
}
static u_char
DecodeSI2(struct sk_buff *skb)
{
u_char *p; //, *pend=skb->data + skb->len;
if ((p = findie(skb->data, skb->len, 0x7c, 0))) {
switch (p[4] & 0x0f) {
case 0x01:
if (p[1] == 0x04) // sync. Bitratenadaption
return DecodeSyncParams(160, p[5]); // V.110/X.30
else if (p[1] == 0x06) // async. Bitratenadaption
return DecodeASyncParams(192, p); // V.110/X.30
break;
case 0x08: // if (p[5] == 0x02) // sync. Bitratenadaption
if (p[1] > 3)
return DecodeSyncParams(176, p[5]); // V.120
break;
}
}
return 0;
}
#endif
static void
l3dss1_setup_req(struct l3_process *pc, u_char pr,
void *arg)
{
struct sk_buff *skb;
u_char tmp[128];
u_char *p = tmp;
u_char channel = 0;
u_char send_keypad;
u_char screen = 0x80;
u_char *teln;
u_char *msn;
u_char *sub;
u_char *sp;
int l;
MsgHead(p, pc->callref, MT_SETUP);
teln = pc->para.setup.phone;
#ifndef CONFIG_HISAX_NO_KEYPAD
send_keypad = (strchr(teln, '*') || strchr(teln, '#')) ? 1 : 0;
#else
send_keypad = 0;
#endif
#ifndef CONFIG_HISAX_NO_SENDCOMPLETE
if (!send_keypad)
*p++ = 0xa1; /* complete indicator */
#endif
/*
* Set Bearer Capability, Map info from 1TR6-convention to EDSS1
*/
switch (pc->para.setup.si1) {
case 1: /* Telephony */
*p++ = IE_BEARER;
*p++ = 0x3; /* Length */
*p++ = 0x90; /* Coding Std. CCITT, 3.1 kHz audio */
*p++ = 0x90; /* Circuit-Mode 64kbps */
*p++ = 0xa3; /* A-Law Audio */
break;
case 5: /* Datatransmission 64k, BTX */
case 7: /* Datatransmission 64k */
default:
*p++ = IE_BEARER;
*p++ = 0x2; /* Length */
*p++ = 0x88; /* Coding Std. CCITT, unrestr. dig. Inform. */
*p++ = 0x90; /* Circuit-Mode 64kbps */
break;
}
if (send_keypad) {
*p++ = IE_KEYPAD;
*p++ = strlen(teln);
while (*teln)
*p++ = (*teln++) & 0x7F;
}
/*
* What about info2? Mapping to High-Layer-Compatibility?
*/
if ((*teln) && (!send_keypad)) {
/* parse number for special things */
if (!isdigit(*teln)) {
switch (0x5f & *teln) {
case 'C':
channel = 0x08;
case 'P':
channel |= 0x80;
teln++;
if (*teln == '1')
channel |= 0x01;
else
channel |= 0x02;
break;
case 'R':
screen = 0xA0;
break;
case 'D':
screen = 0x80;
break;
default:
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "Wrong MSN Code");
break;
}
teln++;
}
}
if (channel) {
*p++ = IE_CHANNEL_ID;
*p++ = 1;
*p++ = channel;
}
msn = pc->para.setup.eazmsn;
sub = NULL;
sp = msn;
while (*sp) {
if ('.' == *sp) {
sub = sp;
*sp = 0;
} else
sp++;
}
if (*msn) {
*p++ = IE_CALLING_PN;
*p++ = strlen(msn) + (screen ? 2 : 1);
/* Classify as AnyPref. */
if (screen) {
*p++ = 0x01; /* Ext = '0'B, Type = '000'B, Plan = '0001'B. */
*p++ = screen;
} else
*p++ = 0x81; /* Ext = '1'B, Type = '000'B, Plan = '0001'B. */
while (*msn)
*p++ = *msn++ & 0x7f;
}
if (sub) {
*sub++ = '.';
*p++ = IE_CALLING_SUB;
*p++ = strlen(sub) + 2;
*p++ = 0x80; /* NSAP coded */
*p++ = 0x50; /* local IDI format */
while (*sub)
*p++ = *sub++ & 0x7f;
}
sub = NULL;
sp = teln;
while (*sp) {
if ('.' == *sp) {
sub = sp;
*sp = 0;
} else
sp++;
}
if (!send_keypad) {
*p++ = IE_CALLED_PN;
*p++ = strlen(teln) + 1;
/* Classify as AnyPref. */
*p++ = 0x81; /* Ext = '1'B, Type = '000'B, Plan = '0001'B. */
while (*teln)
*p++ = *teln++ & 0x7f;
if (sub) {
*sub++ = '.';
*p++ = IE_CALLED_SUB;
*p++ = strlen(sub) + 2;
*p++ = 0x80; /* NSAP coded */
*p++ = 0x50; /* local IDI format */
while (*sub)
*p++ = *sub++ & 0x7f;
}
}
#ifdef EXT_BEARER_CAPS
if ((pc->para.setup.si2 >= 160) && (pc->para.setup.si2 <= 175)) { // sync. Bitratenadaption, V.110/X.30
*p++ = IE_LLC;
*p++ = 0x04;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x21;
*p++ = EncodeSyncParams(pc->para.setup.si2 - 160, 0x80);
} else if ((pc->para.setup.si2 >= 176) && (pc->para.setup.si2 <= 191)) { // sync. Bitratenadaption, V.120
*p++ = IE_LLC;
*p++ = 0x05;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x28;
*p++ = EncodeSyncParams(pc->para.setup.si2 - 176, 0);
*p++ = 0x82;
} else if (pc->para.setup.si2 >= 192) { // async. Bitratenadaption, V.110/X.30
*p++ = IE_LLC;
*p++ = 0x06;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x21;
p = EncodeASyncParams(p, pc->para.setup.si2 - 192);
#ifndef CONFIG_HISAX_NO_LLC
} else {
switch (pc->para.setup.si1) {
case 1: /* Telephony */
*p++ = IE_LLC;
*p++ = 0x3; /* Length */
*p++ = 0x90; /* Coding Std. CCITT, 3.1 kHz audio */
*p++ = 0x90; /* Circuit-Mode 64kbps */
*p++ = 0xa3; /* A-Law Audio */
break;
case 5: /* Datatransmission 64k, BTX */
case 7: /* Datatransmission 64k */
default:
*p++ = IE_LLC;
*p++ = 0x2; /* Length */
*p++ = 0x88; /* Coding Std. CCITT, unrestr. dig. Inform. */
*p++ = 0x90; /* Circuit-Mode 64kbps */
break;
}
#endif
}
#endif
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T303, CC_T303);
newl3state(pc, 1);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_call_proc(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else if (1 == pc->state) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer wrong chid (ret %d)", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
ret = check_infoelements(pc, skb, ie_CALL_PROCEEDING);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
newl3state(pc, 3);
L3AddTimer(&pc->timer, T310, CC_T310);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_PROCEEDING | INDICATION, pc);
}
static void
l3dss1_setup_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer wrong chid (ret %d)", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
ret = check_infoelements(pc, skb, ie_SETUP_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
newl3state(pc, 2);
L3AddTimer(&pc->timer, T304, CC_T304);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_MORE_INFO | INDICATION, pc);
}
static void
l3dss1_disconnect(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
u_char *p;
int ret;
u_char cause = 0;
StopAllL3Timer(pc);
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "DISC get_cause ret(%d)", ret);
if (ret < 0)
cause = 96;
else if (ret > 0)
cause = 100;
}
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0)))
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
ret = check_infoelements(pc, skb, ie_DISCONNECT);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if ((!cause) && (ERR_IE_UNRECOGNIZED == ret))
cause = 99;
ret = pc->state;
newl3state(pc, 12);
if (cause)
newl3state(pc, 19);
if (11 != ret)
pc->st->l3.l3l4(pc->st, CC_DISCONNECT | INDICATION, pc);
else if (!cause)
l3dss1_release_req(pc, pr, NULL);
if (cause) {
l3dss1_message_cause(pc, MT_RELEASE, cause);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
}
static void
l3dss1_connect(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_CONNECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer); /* T310 */
newl3state(pc, 10);
pc->para.chargeinfo = 0;
/* here should inserted COLP handling KKe */
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_SETUP | CONFIRM, pc);
}
static void
l3dss1_alerting(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_ALERTING);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer); /* T304 */
newl3state(pc, 4);
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_ALERTING | INDICATION, pc);
}
static void
l3dss1_setup(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
int bcfound = 0;
char tmp[80];
struct sk_buff *skb = arg;
int id;
int err = 0;
/*
* Bearer Capabilities
*/
p = skb->data;
/* only the first occurrence 'll be detected ! */
if ((p = findie(p, skb->len, 0x04, 0))) {
if ((p[1] < 2) || (p[1] > 11))
err = 1;
else {
pc->para.setup.si2 = 0;
switch (p[2] & 0x7f) {
case 0x00: /* Speech */
case 0x10: /* 3.1 Khz audio */
pc->para.setup.si1 = 1;
break;
case 0x08: /* Unrestricted digital information */
pc->para.setup.si1 = 7;
/* JIM, 05.11.97 I wanna set service indicator 2 */
#ifdef EXT_BEARER_CAPS
pc->para.setup.si2 = DecodeSI2(skb);
#endif
break;
case 0x09: /* Restricted digital information */
pc->para.setup.si1 = 2;
break;
case 0x11:
/* Unrestr. digital information with
* tones/announcements ( or 7 kHz audio
*/
pc->para.setup.si1 = 3;
break;
case 0x18: /* Video */
pc->para.setup.si1 = 4;
break;
default:
err = 2;
break;
}
switch (p[3] & 0x7f) {
case 0x40: /* packed mode */
pc->para.setup.si1 = 8;
break;
case 0x10: /* 64 kbit */
case 0x11: /* 2*64 kbit */
case 0x13: /* 384 kbit */
case 0x15: /* 1536 kbit */
case 0x17: /* 1920 kbit */
pc->para.moderate = p[3] & 0x7f;
break;
default:
err = 3;
break;
}
}
if (pc->debug & L3_DEB_SI)
l3_debug(pc->st, "SI=%d, AI=%d",
pc->para.setup.si1, pc->para.setup.si2);
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong bearer(l=%d:%x,%x)",
p[1], p[2], p[3]);
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup without bearer capabilities");
/* ETS 300-104 1.3.3 */
pc->para.cause = 96;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
/*
* Channel Identification
*/
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((pc->para.bchannel = id)) {
if ((3 == id) && (0x10 == pc->para.moderate)) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong chid %x",
id);
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
bcfound++;
} else
{ if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup without bchannel, call waiting");
bcfound++;
}
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong chid ret %d", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_SETUP);
if (ERR_IE_COMPREHENSION == err) {
pc->para.cause = 96;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
p = skb->data;
if ((p = findie(p, skb->len, 0x70, 0)))
iecpy(pc->para.setup.eazmsn, p, 1);
else
pc->para.setup.eazmsn[0] = 0;
p = skb->data;
if ((p = findie(p, skb->len, 0x71, 0))) {
/* Called party subaddress */
if ((p[1] >= 2) && (p[2] == 0x80) && (p[3] == 0x50)) {
tmp[0] = '.';
iecpy(&tmp[1], p, 2);
strcat(pc->para.setup.eazmsn, tmp);
} else if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong called subaddress");
}
p = skb->data;
if ((p = findie(p, skb->len, 0x6c, 0))) {
pc->para.setup.plan = p[2];
if (p[2] & 0x80) {
iecpy(pc->para.setup.phone, p, 1);
pc->para.setup.screen = 0;
} else {
iecpy(pc->para.setup.phone, p, 2);
pc->para.setup.screen = p[3];
}
} else {
pc->para.setup.phone[0] = 0;
pc->para.setup.plan = 0;
pc->para.setup.screen = 0;
}
p = skb->data;
if ((p = findie(p, skb->len, 0x6d, 0))) {
/* Calling party subaddress */
if ((p[1] >= 2) && (p[2] == 0x80) && (p[3] == 0x50)) {
tmp[0] = '.';
iecpy(&tmp[1], p, 2);
strcat(pc->para.setup.phone, tmp);
} else if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong calling subaddress");
}
newl3state(pc, 6);
if (err) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, err);
pc->st->l3.l3l4(pc->st, CC_SETUP | INDICATION, pc);
}
static void
l3dss1_reset(struct l3_process *pc, u_char pr, void *arg)
{
dss1_release_l3_process(pc);
}
static void
l3dss1_disconnect_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[16 + 40];
u_char *p = tmp;
int l;
u_char cause = 16;
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
StopAllL3Timer(pc);
MsgHead(p, pc->callref, MT_DISCONNECT);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
if (pc->prot.dss1.uus1_data[0])
{ *p++ = IE_USER_USER; /* UUS info element */
*p++ = strlen(pc->prot.dss1.uus1_data) + 1;
*p++ = 0x04; /* IA5 chars */
strcpy(p, pc->prot.dss1.uus1_data);
p += strlen(pc->prot.dss1.uus1_data);
pc->prot.dss1.uus1_data[0] = '\0';
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 11);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
L3AddTimer(&pc->timer, T305, CC_T305);
}
static void
l3dss1_setup_rsp(struct l3_process *pc, u_char pr,
void *arg)
{
if (!pc->para.bchannel)
{ if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "D-chan connect for waiting call");
l3dss1_disconnect_req(pc, pr, arg);
return;
}
newl3state(pc, 8);
l3dss1_message(pc, MT_CONNECT);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T313, CC_T313);
}
static void
l3dss1_connect_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_CONNECT_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
newl3state(pc, 10);
L3DelTimer(&pc->timer);
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_SETUP_COMPL | INDICATION, pc);
}
static void
l3dss1_reject_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[16];
u_char *p = tmp;
int l;
u_char cause = 21;
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
MsgHead(p, pc->callref, MT_RELEASE_COMPLETE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
static void
l3dss1_release(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
u_char *p;
int ret, cause = 0;
StopAllL3Timer(pc);
if ((ret = l3dss1_get_cause(pc, skb)) > 0) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "REL get_cause ret(%d)", ret);
} else if (ret < 0)
pc->para.cause = NO_CAUSE;
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0))) {
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
}
if ((ret < 0) && (pc->state != 11))
cause = 96;
else if (ret > 0)
cause = 100;
ret = check_infoelements(pc, skb, ie_RELEASE);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if ((ERR_IE_UNRECOGNIZED == ret) && (!cause))
cause = 99;
if (cause)
l3dss1_message_cause(pc, MT_RELEASE_COMPLETE, cause);
else
l3dss1_message(pc, MT_RELEASE_COMPLETE);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
static void
l3dss1_alert_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 7);
if (!pc->prot.dss1.uus1_data[0])
l3dss1_message(pc, MT_ALERTING);
else
l3dss1_msg_with_uus(pc, MT_ALERTING);
}
static void
l3dss1_proceed_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 9);
l3dss1_message(pc, MT_CALL_PROCEEDING);
pc->st->l3.l3l4(pc->st, CC_PROCEED_SEND | INDICATION, pc);
}
static void
l3dss1_setup_ack_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 25);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T302, CC_T302);
l3dss1_message(pc, MT_SETUP_ACKNOWLEDGE);
}
/********************************************/
/* deliver a incoming display message to HL */
/********************************************/
static void
l3dss1_deliver_display(struct l3_process *pc, int pr, u_char *infp)
{ u_char len;
isdn_ctrl ic;
struct IsdnCardState *cs;
char *p;
if (*infp++ != IE_DISPLAY) return;
if ((len = *infp++) > 80) return; /* total length <= 82 */
if (!pc->chan) return;
p = ic.parm.display;
while (len--)
*p++ = *infp++;
*p = '\0';
ic.command = ISDN_STAT_DISPLAY;
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.arg = pc->chan->chan;
cs->iif.statcallb(&ic);
} /* l3dss1_deliver_display */
static void
l3dss1_progress(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int err = 0;
u_char *p;
if ((p = findie(skb->data, skb->len, IE_PROGRESS, 0))) {
if (p[1] != 2) {
err = 1;
pc->para.cause = 100;
} else if (!(p[2] & 0x70)) {
switch (p[2]) {
case 0x80:
case 0x81:
case 0x82:
case 0x84:
case 0x85:
case 0x87:
case 0x8a:
switch (p[3]) {
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x88:
break;
default:
err = 2;
pc->para.cause = 100;
break;
}
break;
default:
err = 3;
pc->para.cause = 100;
break;
}
}
} else {
pc->para.cause = 96;
err = 4;
}
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "progress error %d", err);
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_PROGRESS);
if (err)
l3dss1_std_ie_err(pc, err);
if (ERR_IE_COMPREHENSION != err)
pc->st->l3.l3l4(pc->st, CC_PROGRESS | INDICATION, pc);
}
static void
l3dss1_notify(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int err = 0;
u_char *p;
if ((p = findie(skb->data, skb->len, IE_NOTIFY, 0))) {
if (p[1] != 1) {
err = 1;
pc->para.cause = 100;
} else {
switch (p[2]) {
case 0x80:
case 0x81:
case 0x82:
break;
default:
pc->para.cause = 100;
err = 2;
break;
}
}
} else {
pc->para.cause = 96;
err = 3;
}
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "notify error %d", err);
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_NOTIFY);
if (err)
l3dss1_std_ie_err(pc, err);
if (ERR_IE_COMPREHENSION != err)
pc->st->l3.l3l4(pc->st, CC_NOTIFY | INDICATION, pc);
}
static void
l3dss1_status_enq(struct l3_process *pc, u_char pr, void *arg)
{
int ret;
struct sk_buff *skb = arg;
ret = check_infoelements(pc, skb, ie_STATUS_ENQUIRY);
l3dss1_std_ie_err(pc, ret);
pc->para.cause = 30; /* response to STATUS_ENQUIRY */
l3dss1_status_send(pc, pr, NULL);
}
static void
l3dss1_information(struct l3_process *pc, u_char pr, void *arg)
{
int ret;
struct sk_buff *skb = arg;
u_char *p;
char tmp[32];
ret = check_infoelements(pc, skb, ie_INFORMATION);
if (ret)
l3dss1_std_ie_err(pc, ret);
if (pc->state == 25) { /* overlap receiving */
L3DelTimer(&pc->timer);
p = skb->data;
if ((p = findie(p, skb->len, 0x70, 0))) {
iecpy(tmp, p, 1);
strcat(pc->para.setup.eazmsn, tmp);
pc->st->l3.l3l4(pc->st, CC_MORE_INFO | INDICATION, pc);
}
L3AddTimer(&pc->timer, T302, CC_T302);
}
}
/******************************/
/* handle deflection requests */
/******************************/
static void l3dss1_redir_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[128];
u_char *p = tmp;
u_char *subp;
u_char len_phone = 0;
u_char len_sub = 0;
int l;
strcpy(pc->prot.dss1.uus1_data, pc->chan->setup.eazmsn); /* copy uus element if available */
if (!pc->chan->setup.phone[0])
{ pc->para.cause = -1;
l3dss1_disconnect_req(pc, pr, arg); /* disconnect immediately */
return;
} /* only uus */
if (pc->prot.dss1.invoke_id)
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
if (!(pc->prot.dss1.invoke_id = new_invoke_id(pc->st)))
return;
MsgHead(p, pc->callref, MT_FACILITY);
for (subp = pc->chan->setup.phone; (*subp) && (*subp != '.'); subp++) len_phone++; /* len of phone number */
if (*subp++ == '.') len_sub = strlen(subp) + 2; /* length including info subaddress element */
*p++ = 0x1c; /* Facility info element */
*p++ = len_phone + len_sub + 2 + 2 + 8 + 3 + 3; /* length of element */
*p++ = 0x91; /* remote operations protocol */
*p++ = 0xa1; /* invoke component */
*p++ = len_phone + len_sub + 2 + 2 + 8 + 3; /* length of data */
*p++ = 0x02; /* invoke id tag, integer */
*p++ = 0x01; /* length */
*p++ = pc->prot.dss1.invoke_id; /* invoke id */
*p++ = 0x02; /* operation value tag, integer */
*p++ = 0x01; /* length */
*p++ = 0x0D; /* Call Deflect */
*p++ = 0x30; /* sequence phone number */
*p++ = len_phone + 2 + 2 + 3 + len_sub; /* length */
*p++ = 0x30; /* Deflected to UserNumber */
*p++ = len_phone + 2 + len_sub; /* length */
*p++ = 0x80; /* NumberDigits */
*p++ = len_phone; /* length */
for (l = 0; l < len_phone; l++)
*p++ = pc->chan->setup.phone[l];
if (len_sub)
{ *p++ = 0x04; /* called party subaddress */
*p++ = len_sub - 2;
while (*subp) *p++ = *subp++;
}
*p++ = 0x01; /* screening identifier */
*p++ = 0x01;
*p++ = pc->chan->setup.screen;
l = p - tmp;
if (!(skb = l3_alloc_skb(l))) return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
} /* l3dss1_redir_req */
/********************************************/
/* handle deflection request in early state */
/********************************************/
static void l3dss1_redir_req_early(struct l3_process *pc, u_char pr, void *arg)
{
l3dss1_proceed_req(pc, pr, arg);
l3dss1_redir_req(pc, pr, arg);
} /* l3dss1_redir_req_early */
/***********************************************/
/* handle special commands for this protocol. */
/* Examples are call independent services like */
/* remote operations with dummy callref. */
/***********************************************/
static int l3dss1_cmd_global(struct PStack *st, isdn_ctrl *ic)
{ u_char id;
u_char temp[265];
u_char *p = temp;
int i, l, proc_len;
struct sk_buff *skb;
struct l3_process *pc = NULL;
switch (ic->arg)
{ case DSS1_CMD_INVOKE:
if (ic->parm.dss1_io.datalen < 0) return (-2); /* invalid parameter */
for (proc_len = 1, i = ic->parm.dss1_io.proc >> 8; i; i++)
i = i >> 8; /* add one byte */
l = ic->parm.dss1_io.datalen + proc_len + 8; /* length excluding ie header */
if (l > 255)
return (-2); /* too long */
if (!(id = new_invoke_id(st)))
return (0); /* first get a invoke id -> return if no available */
i = -1;
MsgHead(p, i, MT_FACILITY); /* build message head */
*p++ = 0x1C; /* Facility IE */
*p++ = l; /* length of ie */
*p++ = 0x91; /* remote operations */
*p++ = 0xA1; /* invoke */
*p++ = l - 3; /* length of invoke */
*p++ = 0x02; /* invoke id tag */
*p++ = 0x01; /* length is 1 */
*p++ = id; /* invoke id */
*p++ = 0x02; /* operation */
*p++ = proc_len; /* length of operation */
for (i = proc_len; i; i--)
*p++ = (ic->parm.dss1_io.proc >> (i - 1)) & 0xFF;
memcpy(p, ic->parm.dss1_io.data, ic->parm.dss1_io.datalen); /* copy data */
l = (p - temp) + ic->parm.dss1_io.datalen; /* total length */
if (ic->parm.dss1_io.timeout > 0)
if (!(pc = dss1_new_l3_process(st, -1)))
{ free_invoke_id(st, id);
return (-2);
}
pc->prot.dss1.ll_id = ic->parm.dss1_io.ll_id; /* remember id */
pc->prot.dss1.proc = ic->parm.dss1_io.proc; /* and procedure */
if (!(skb = l3_alloc_skb(l)))
{ free_invoke_id(st, id);
if (pc) dss1_release_l3_process(pc);
return (-2);
}
memcpy(skb_put(skb, l), temp, l);
if (pc)
{ pc->prot.dss1.invoke_id = id; /* remember id */
L3AddTimer(&pc->timer, ic->parm.dss1_io.timeout, CC_TDSS1_IO | REQUEST);
}
l3_msg(st, DL_DATA | REQUEST, skb);
ic->parm.dss1_io.hl_id = id; /* return id */
return (0);
case DSS1_CMD_INVOKE_ABORT:
if ((pc = l3dss1_search_dummy_proc(st, ic->parm.dss1_io.hl_id)))
{ L3DelTimer(&pc->timer); /* remove timer */
dss1_release_l3_process(pc);
return (0);
}
else
{ l3_debug(st, "l3dss1_cmd_global abort unknown id");
return (-2);
}
break;
default:
l3_debug(st, "l3dss1_cmd_global unknown cmd 0x%lx", ic->arg);
return (-1);
} /* switch ic-> arg */
return (-1);
} /* l3dss1_cmd_global */
static void
l3dss1_io_timer(struct l3_process *pc)
{ isdn_ctrl ic;
struct IsdnCardState *cs = pc->st->l1.hardware;
L3DelTimer(&pc->timer); /* remove timer */
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_ERR;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = -1;
ic.parm.dss1_io.datalen = 0;
ic.parm.dss1_io.data = NULL;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
} /* l3dss1_io_timer */
static void
l3dss1_release_ind(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
struct sk_buff *skb = arg;
int callState = 0;
p = skb->data;
if ((p = findie(p, skb->len, IE_CALL_STATE, 0))) {
p++;
if (1 == *p++)
callState = *p;
}
if (callState == 0) {
/* ETS 300-104 7.6.1, 8.6.1, 10.6.1... and 16.1
* set down layer 3 without sending any message
*/
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
} else {
pc->st->l3.l3l4(pc->st, CC_IGNORE | INDICATION, pc);
}
}
static void
l3dss1_dummy(struct l3_process *pc, u_char pr, void *arg)
{
}
static void
l3dss1_t302(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 28; /* invalid number */
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t303(struct l3_process *pc, u_char pr, void *arg)
{
if (pc->N303 > 0) {
pc->N303--;
L3DelTimer(&pc->timer);
l3dss1_setup_req(pc, pr, arg);
} else {
L3DelTimer(&pc->timer);
l3dss1_message_cause(pc, MT_RELEASE_COMPLETE, 102);
pc->st->l3.l3l4(pc->st, CC_NOSETUP_RSP, pc);
dss1_release_l3_process(pc);
}
}
static void
l3dss1_t304(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t305(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
u_char cause = 16;
L3DelTimer(&pc->timer);
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
MsgHead(p, pc->callref, MT_RELEASE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 19);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_t310(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t313(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_CONNECT_ERR, pc);
}
static void
l3dss1_t308_1(struct l3_process *pc, u_char pr, void *arg)
{
newl3state(pc, 19);
L3DelTimer(&pc->timer);
l3dss1_message(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_2);
}
static void
l3dss1_t308_2(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RELEASE_ERR, pc);
dss1_release_l3_process(pc);
}
static void
l3dss1_t318(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 102; /* Timer expiry */
pc->para.loc = 0; /* local */
pc->st->l3.l3l4(pc->st, CC_RESUME_ERR, pc);
newl3state(pc, 19);
l3dss1_message(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_t319(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 102; /* Timer expiry */
pc->para.loc = 0; /* local */
pc->st->l3.l3l4(pc->st, CC_SUSPEND_ERR, pc);
newl3state(pc, 10);
}
static void
l3dss1_restart(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
dss1_release_l3_process(pc);
}
static void
l3dss1_status(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
struct sk_buff *skb = arg;
int ret;
u_char cause = 0, callState = 0;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "STATUS get_cause ret(%d)", ret);
if (ret < 0)
cause = 96;
else if (ret > 0)
cause = 100;
}
if ((p = findie(skb->data, skb->len, IE_CALL_STATE, 0))) {
p++;
if (1 == *p++) {
callState = *p;
if (!ie_in_set(pc, *p, l3_valid_states))
cause = 100;
} else
cause = 100;
} else
cause = 96;
if (!cause) { /* no error before */
ret = check_infoelements(pc, skb, ie_STATUS);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if (ERR_IE_UNRECOGNIZED == ret)
cause = 99;
}
if (cause) {
u_char tmp;
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "STATUS error(%d/%d)", ret, cause);
tmp = pc->para.cause;
pc->para.cause = cause;
l3dss1_status_send(pc, 0, NULL);
if (cause == 99)
pc->para.cause = tmp;
else
return;
}
cause = pc->para.cause;
if (((cause & 0x7f) == 111) && (callState == 0)) {
/* ETS 300-104 7.6.1, 8.6.1, 10.6.1...
* if received MT_STATUS with cause == 111 and call
* state == 0, then we must set down layer 3
*/
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
}
static void
l3dss1_facility(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_FACILITY);
l3dss1_std_ie_err(pc, ret);
{
u_char *p;
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0)))
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
}
}
static void
l3dss1_suspend_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[32];
u_char *p = tmp;
u_char i, l;
u_char *msg = pc->chan->setup.phone;
MsgHead(p, pc->callref, MT_SUSPEND);
l = *msg++;
if (l && (l <= 10)) { /* Max length 10 octets */
*p++ = IE_CALL_ID;
*p++ = l;
for (i = 0; i < l; i++)
*p++ = *msg++;
} else if (l) {
l3_debug(pc->st, "SUS wrong CALL_ID len %d", l);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
newl3state(pc, 15);
L3AddTimer(&pc->timer, T319, CC_T319);
}
static void
l3dss1_suspend_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
L3DelTimer(&pc->timer);
newl3state(pc, 0);
pc->para.cause = NO_CAUSE;
pc->st->l3.l3l4(pc->st, CC_SUSPEND | CONFIRM, pc);
/* We don't handle suspend_ack for IE errors now */
if ((ret = check_infoelements(pc, skb, ie_SUSPEND_ACKNOWLEDGE)))
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "SUSPACK check ie(%d)", ret);
dss1_release_l3_process(pc);
}
static void
l3dss1_suspend_rej(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "SUSP_REJ get_cause ret(%d)", ret);
if (ret < 0)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_SUSPEND_REJECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_SUSPEND_ERR, pc);
newl3state(pc, 10);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
}
static void
l3dss1_resume_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[32];
u_char *p = tmp;
u_char i, l;
u_char *msg = pc->para.setup.phone;
MsgHead(p, pc->callref, MT_RESUME);
l = *msg++;
if (l && (l <= 10)) { /* Max length 10 octets */
*p++ = IE_CALL_ID;
*p++ = l;
for (i = 0; i < l; i++)
*p++ = *msg++;
} else if (l) {
l3_debug(pc->st, "RES wrong CALL_ID len %d", l);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
newl3state(pc, 17);
L3AddTimer(&pc->timer, T318, CC_T318);
}
static void
l3dss1_resume_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) > 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "resume ack with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else if (1 == pc->state) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "resume ack without chid (ret %d)", id);
pc->para.cause = 96;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_RESUME_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RESUME | CONFIRM, pc);
newl3state(pc, 10);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
}
static void
l3dss1_resume_rej(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "RES_REJ get_cause ret(%d)", ret);
if (ret < 0)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_RESUME_REJECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RESUME_ERR, pc);
newl3state(pc, 0);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
dss1_release_l3_process(pc);
}
static void
l3dss1_global_restart(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[32];
u_char *p;
u_char ri, ch = 0, chan = 0;
int l;
struct sk_buff *skb = arg;
struct l3_process *up;
newl3state(pc, 2);
L3DelTimer(&pc->timer);
p = skb->data;
if ((p = findie(p, skb->len, IE_RESTART_IND, 0))) {
ri = p[2];
l3_debug(pc->st, "Restart %x", ri);
} else {
l3_debug(pc->st, "Restart without restart IE");
ri = 0x86;
}
p = skb->data;
if ((p = findie(p, skb->len, IE_CHANNEL_ID, 0))) {
chan = p[2] & 3;
ch = p[2];
if (pc->st->l3.debug)
l3_debug(pc->st, "Restart for channel %d", chan);
}
newl3state(pc, 2);
up = pc->st->l3.proc;
while (up) {
if ((ri & 7) == 7)
up->st->lli.l4l3(up->st, CC_RESTART | REQUEST, up);
else if (up->para.bchannel == chan)
up->st->lli.l4l3(up->st, CC_RESTART | REQUEST, up);
up = up->next;
}
p = tmp;
MsgHead(p, pc->callref, MT_RESTART_ACKNOWLEDGE);
if (chan) {
*p++ = IE_CHANNEL_ID;
*p++ = 1;
*p++ = ch | 0x80;
}
*p++ = 0x79; /* RESTART Ind */
*p++ = 1;
*p++ = ri;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 0);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_dl_reset(struct l3_process *pc, u_char pr, void *arg)
{
pc->para.cause = 0x29; /* Temporary failure */
pc->para.loc = 0;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_dl_release(struct l3_process *pc, u_char pr, void *arg)
{
newl3state(pc, 0);
pc->para.cause = 0x1b; /* Destination out of order */
pc->para.loc = 0;
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
release_l3_process(pc);
}
static void
l3dss1_dl_reestablish(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T309, CC_T309);
l3_msg(pc->st, DL_ESTABLISH | REQUEST, NULL);
}
static void
l3dss1_dl_reest_status(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 0x1F; /* normal, unspecified */
l3dss1_status_send(pc, 0, NULL);
}
/* *INDENT-OFF* */
static struct stateentry downstatelist[] =
{
{SBIT(0),
CC_SETUP | REQUEST, l3dss1_setup_req},
{SBIT(0),
CC_RESUME | REQUEST, l3dss1_resume_req},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(6) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(25),
CC_DISCONNECT | REQUEST, l3dss1_disconnect_req},
{SBIT(12),
CC_RELEASE | REQUEST, l3dss1_release_req},
{ALL_STATES,
CC_RESTART | REQUEST, l3dss1_restart},
{SBIT(6) | SBIT(25),
CC_IGNORE | REQUEST, l3dss1_reset},
{SBIT(6) | SBIT(25),
CC_REJECT | REQUEST, l3dss1_reject_req},
{SBIT(6) | SBIT(25),
CC_PROCEED_SEND | REQUEST, l3dss1_proceed_req},
{SBIT(6),
CC_MORE_INFO | REQUEST, l3dss1_setup_ack_req},
{SBIT(25),
CC_MORE_INFO | REQUEST, l3dss1_dummy},
{SBIT(6) | SBIT(9) | SBIT(25),
CC_ALERTING | REQUEST, l3dss1_alert_req},
{SBIT(6) | SBIT(7) | SBIT(9) | SBIT(25),
CC_SETUP | RESPONSE, l3dss1_setup_rsp},
{SBIT(10),
CC_SUSPEND | REQUEST, l3dss1_suspend_req},
{SBIT(7) | SBIT(9) | SBIT(25),
CC_REDIR | REQUEST, l3dss1_redir_req},
{SBIT(6),
CC_REDIR | REQUEST, l3dss1_redir_req_early},
{SBIT(9) | SBIT(25),
CC_DISCONNECT | REQUEST, l3dss1_disconnect_req},
{SBIT(25),
CC_T302, l3dss1_t302},
{SBIT(1),
CC_T303, l3dss1_t303},
{SBIT(2),
CC_T304, l3dss1_t304},
{SBIT(3),
CC_T310, l3dss1_t310},
{SBIT(8),
CC_T313, l3dss1_t313},
{SBIT(11),
CC_T305, l3dss1_t305},
{SBIT(15),
CC_T319, l3dss1_t319},
{SBIT(17),
CC_T318, l3dss1_t318},
{SBIT(19),
CC_T308_1, l3dss1_t308_1},
{SBIT(19),
CC_T308_2, l3dss1_t308_2},
{SBIT(10),
CC_T309, l3dss1_dl_release},
};
static struct stateentry datastatelist[] =
{
{ALL_STATES,
MT_STATUS_ENQUIRY, l3dss1_status_enq},
{ALL_STATES,
MT_FACILITY, l3dss1_facility},
{SBIT(19),
MT_STATUS, l3dss1_release_ind},
{ALL_STATES,
MT_STATUS, l3dss1_status},
{SBIT(0),
MT_SETUP, l3dss1_setup},
{SBIT(6) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(12) |
SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_SETUP, l3dss1_dummy},
{SBIT(1) | SBIT(2),
MT_CALL_PROCEEDING, l3dss1_call_proc},
{SBIT(1),
MT_SETUP_ACKNOWLEDGE, l3dss1_setup_ack},
{SBIT(2) | SBIT(3),
MT_ALERTING, l3dss1_alerting},
{SBIT(2) | SBIT(3),
MT_PROGRESS, l3dss1_progress},
{SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) |
SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_INFORMATION, l3dss1_information},
{SBIT(10) | SBIT(11) | SBIT(15),
MT_NOTIFY, l3dss1_notify},
{SBIT(0) | SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(10) |
SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_RELEASE_COMPLETE, l3dss1_release_cmpl},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(25),
MT_RELEASE, l3dss1_release},
{SBIT(19), MT_RELEASE, l3dss1_release_ind},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(15) | SBIT(17) | SBIT(25),
MT_DISCONNECT, l3dss1_disconnect},
{SBIT(19),
MT_DISCONNECT, l3dss1_dummy},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4),
MT_CONNECT, l3dss1_connect},
{SBIT(8),
MT_CONNECT_ACKNOWLEDGE, l3dss1_connect_ack},
{SBIT(15),
MT_SUSPEND_ACKNOWLEDGE, l3dss1_suspend_ack},
{SBIT(15),
MT_SUSPEND_REJECT, l3dss1_suspend_rej},
{SBIT(17),
MT_RESUME_ACKNOWLEDGE, l3dss1_resume_ack},
{SBIT(17),
MT_RESUME_REJECT, l3dss1_resume_rej},
};
static struct stateentry globalmes_list[] =
{
{ALL_STATES,
MT_STATUS, l3dss1_status},
{SBIT(0),
MT_RESTART, l3dss1_global_restart},
/* {SBIT(1),
MT_RESTART_ACKNOWLEDGE, l3dss1_restart_ack},
*/
};
static struct stateentry manstatelist[] =
{
{SBIT(2),
DL_ESTABLISH | INDICATION, l3dss1_dl_reset},
{SBIT(10),
DL_ESTABLISH | CONFIRM, l3dss1_dl_reest_status},
{SBIT(10),
DL_RELEASE | INDICATION, l3dss1_dl_reestablish},
{ALL_STATES,
DL_RELEASE | INDICATION, l3dss1_dl_release},
};
/* *INDENT-ON* */
static void
global_handler(struct PStack *st, int mt, struct sk_buff *skb)
{
u_char tmp[16];
u_char *p = tmp;
int l;
int i;
struct l3_process *proc = st->l3.global;
proc->callref = skb->data[2]; /* cr flag */
for (i = 0; i < ARRAY_SIZE(globalmes_list); i++)
if ((mt == globalmes_list[i].primitive) &&
((1 << proc->state) & globalmes_list[i].state))
break;
if (i == ARRAY_SIZE(globalmes_list)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global state %d mt %x unhandled",
proc->state, mt);
}
MsgHead(p, proc->callref, MT_STATUS);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = 81 | 0x80; /* invalid cr */
*p++ = 0x14; /* CallState */
*p++ = 0x1;
*p++ = proc->state & 0x3f;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(proc->st, DL_DATA | REQUEST, skb);
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global %d mt %x",
proc->state, mt);
}
globalmes_list[i].rout(proc, mt, skb);
}
}
static void
dss1up(struct PStack *st, int pr, void *arg)
{
int i, mt, cr, callState;
char *ptr;
u_char *p;
struct sk_buff *skb = arg;
struct l3_process *proc;
switch (pr) {
case (DL_DATA | INDICATION):
case (DL_UNIT_DATA | INDICATION):
break;
case (DL_ESTABLISH | CONFIRM):
case (DL_ESTABLISH | INDICATION):
case (DL_RELEASE | INDICATION):
case (DL_RELEASE | CONFIRM):
l3_msg(st, pr, arg);
return;
break;
default:
printk(KERN_ERR "HiSax dss1up unknown pr=%04x\n", pr);
return;
}
if (skb->len < 3) {
l3_debug(st, "dss1up frame too short(%d)", skb->len);
dev_kfree_skb(skb);
return;
}
if (skb->data[0] != PROTO_DIS_EURO) {
if (st->l3.debug & L3_DEB_PROTERR) {
l3_debug(st, "dss1up%sunexpected discriminator %x message len %d",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
skb->data[0], skb->len);
}
dev_kfree_skb(skb);
return;
}
cr = getcallref(skb->data);
if (skb->len < ((skb->data[1] & 0x0f) + 3)) {
l3_debug(st, "dss1up frame too short(%d)", skb->len);
dev_kfree_skb(skb);
return;
}
mt = skb->data[skb->data[1] + 2];
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up cr %d", cr);
if (cr == -2) { /* wrong Callref */
if (st->l3.debug & L3_DEB_WARN)
l3_debug(st, "dss1up wrong Callref");
dev_kfree_skb(skb);
return;
} else if (cr == -1) { /* Dummy Callref */
if (mt == MT_FACILITY)
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0))) {
l3dss1_parse_facility(st, NULL,
(pr == (DL_DATA | INDICATION)) ? -1 : -2, p);
dev_kfree_skb(skb);
return;
}
if (st->l3.debug & L3_DEB_WARN)
l3_debug(st, "dss1up dummy Callref (no facility msg or ie)");
dev_kfree_skb(skb);
return;
} else if ((((skb->data[1] & 0x0f) == 1) && (0 == (cr & 0x7f))) ||
(((skb->data[1] & 0x0f) == 2) && (0 == (cr & 0x7fff)))) { /* Global CallRef */
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up Global CallRef");
global_handler(st, mt, skb);
dev_kfree_skb(skb);
return;
} else if (!(proc = getl3proc(st, cr))) {
/* No transaction process exist, that means no call with
* this callreference is active
*/
if (mt == MT_SETUP) {
/* Setup creates a new transaction process */
if (skb->data[2] & 0x80) {
/* Setup with wrong CREF flag */
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up wrong CRef flag");
dev_kfree_skb(skb);
return;
}
if (!(proc = dss1_new_l3_process(st, cr))) {
/* May be to answer with RELEASE_COMPLETE and
* CAUSE 0x2f "Resource unavailable", but this
* need a new_l3_process too ... arghh
*/
dev_kfree_skb(skb);
return;
}
} else if (mt == MT_STATUS) {
if ((ptr = findie(skb->data, skb->len, IE_CAUSE, 0)) != NULL) {
ptr++;
if (*ptr++ == 2)
ptr++;
}
callState = 0;
if ((ptr = findie(skb->data, skb->len, IE_CALL_STATE, 0)) != NULL) {
ptr++;
if (*ptr++ == 2)
ptr++;
callState = *ptr;
}
/* ETS 300-104 part 2.4.1
* if setup has not been made and a message type
* MT_STATUS is received with call state == 0,
* we must send nothing
*/
if (callState != 0) {
/* ETS 300-104 part 2.4.2
* if setup has not been made and a message type
* MT_STATUS is received with call state != 0,
* we must send MT_RELEASE_COMPLETE cause 101
*/
if ((proc = dss1_new_l3_process(st, cr))) {
proc->para.cause = 101;
l3dss1_msg_without_setup(proc, 0, NULL);
}
}
dev_kfree_skb(skb);
return;
} else if (mt == MT_RELEASE_COMPLETE) {
dev_kfree_skb(skb);
return;
} else {
/* ETS 300-104 part 2
* if setup has not been made and a message type
* (except MT_SETUP and RELEASE_COMPLETE) is received,
* we must send MT_RELEASE_COMPLETE cause 81 */
dev_kfree_skb(skb);
if ((proc = dss1_new_l3_process(st, cr))) {
proc->para.cause = 81;
l3dss1_msg_without_setup(proc, 0, NULL);
}
return;
}
}
if (l3dss1_check_messagetype_validity(proc, mt, skb)) {
dev_kfree_skb(skb);
return;
}
if ((p = findie(skb->data, skb->len, IE_DISPLAY, 0)) != NULL)
l3dss1_deliver_display(proc, pr, p); /* Display IE included */
for (i = 0; i < ARRAY_SIZE(datastatelist); i++)
if ((mt == datastatelist[i].primitive) &&
((1 << proc->state) & datastatelist[i].state))
break;
if (i == ARRAY_SIZE(datastatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %#x unhandled",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
proc->state, mt);
}
if ((MT_RELEASE_COMPLETE != mt) && (MT_RELEASE != mt)) {
proc->para.cause = 101;
l3dss1_status_send(proc, pr, skb);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %x",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
proc->state, mt);
}
datastatelist[i].rout(proc, pr, skb);
}
dev_kfree_skb(skb);
return;
}
static void
dss1down(struct PStack *st, int pr, void *arg)
{
int i, cr;
struct l3_process *proc;
struct Channel *chan;
if ((DL_ESTABLISH | REQUEST) == pr) {
l3_msg(st, pr, NULL);
return;
} else if (((CC_SETUP | REQUEST) == pr) || ((CC_RESUME | REQUEST) == pr)) {
chan = arg;
cr = newcallref();
cr |= 0x80;
if ((proc = dss1_new_l3_process(st, cr))) {
proc->chan = chan;
chan->proc = proc;
memcpy(&proc->para.setup, &chan->setup, sizeof(setup_parm));
proc->callref = cr;
}
} else {
proc = arg;
}
if (!proc) {
printk(KERN_ERR "HiSax dss1down without proc pr=%04x\n", pr);
return;
}
if (pr == (CC_TDSS1_IO | REQUEST)) {
l3dss1_io_timer(proc); /* timer expires */
return;
}
for (i = 0; i < ARRAY_SIZE(downstatelist); i++)
if ((pr == downstatelist[i].primitive) &&
((1 << proc->state) & downstatelist[i].state))
break;
if (i == ARRAY_SIZE(downstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x unhandled",
proc->state, pr);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x",
proc->state, pr);
}
downstatelist[i].rout(proc, pr, arg);
}
}
static void
dss1man(struct PStack *st, int pr, void *arg)
{
int i;
struct l3_process *proc = arg;
if (!proc) {
printk(KERN_ERR "HiSax dss1man without proc pr=%04x\n", pr);
return;
}
for (i = 0; i < ARRAY_SIZE(manstatelist); i++)
if ((pr == manstatelist[i].primitive) &&
((1 << proc->state) & manstatelist[i].state))
break;
if (i == ARRAY_SIZE(manstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x unhandled",
proc->callref & 0x7f, proc->state, pr);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x",
proc->callref & 0x7f, proc->state, pr);
}
manstatelist[i].rout(proc, pr, arg);
}
}
void
setstack_dss1(struct PStack *st)
{
char tmp[64];
int i;
st->lli.l4l3 = dss1down;
st->lli.l4l3_proto = l3dss1_cmd_global;
st->l2.l2l3 = dss1up;
st->l3.l3ml3 = dss1man;
st->l3.N303 = 1;
st->prot.dss1.last_invoke_id = 0;
st->prot.dss1.invoke_used[0] = 1; /* Bit 0 must always be set to 1 */
i = 1;
while (i < 32)
st->prot.dss1.invoke_used[i++] = 0;
if (!(st->l3.global = kmalloc(sizeof(struct l3_process), GFP_ATOMIC))) {
printk(KERN_ERR "HiSax can't get memory for dss1 global CR\n");
} else {
st->l3.global->state = 0;
st->l3.global->callref = 0;
st->l3.global->next = NULL;
st->l3.global->debug = L3_DEB_WARN;
st->l3.global->st = st;
st->l3.global->N303 = 1;
st->l3.global->prot.dss1.invoke_id = 0;
L3InitTimer(st->l3.global, &st->l3.global->timer);
}
strcpy(tmp, dss1_revision);
printk(KERN_INFO "HiSax: DSS1 Rev. %s\n", HiSax_getrev(tmp));
}
| gpl-2.0 |
Team-M8/android_kernel_htc_msm8974-staging | drivers/isdn/i4l/isdn_v110.c | 9553 | 16538 | /* $Id: isdn_v110.c,v 1.1.2.2 2004/01/12 22:37:19 keil Exp $
*
* Linux ISDN subsystem, V.110 related functions (linklevel).
*
* Copyright by Thomas Pfeiffer (pfeiffer@pds.de)
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/isdn.h>
#include "isdn_v110.h"
#undef ISDN_V110_DEBUG
char *isdn_v110_revision = "$Revision: 1.1.2.2 $";
#define V110_38400 255
#define V110_19200 15
#define V110_9600 3
/*
* The following data are precoded matrices, online and offline matrix
* for 9600, 19200 und 38400, respectively
*/
static unsigned char V110_OnMatrix_9600[] =
{0xfc, 0xfc, 0xfc, 0xfc, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff,
0xff, 0xfd, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xfd,
0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff,
0xff, 0xfd, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xfd};
static unsigned char V110_OffMatrix_9600[] =
{0xfc, 0xfc, 0xfc, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
static unsigned char V110_OnMatrix_19200[] =
{0xf0, 0xf0, 0xff, 0xf7, 0xff, 0xf7, 0xff, 0xf7, 0xff, 0xf7,
0xfd, 0xff, 0xff, 0xf7, 0xff, 0xf7, 0xff, 0xf7, 0xff, 0xf7};
static unsigned char V110_OffMatrix_19200[] =
{0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
static unsigned char V110_OnMatrix_38400[] =
{0x00, 0x7f, 0x7f, 0x7f, 0x7f, 0xfd, 0x7f, 0x7f, 0x7f, 0x7f};
static unsigned char V110_OffMatrix_38400[] =
{0x00, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff};
/*
* FlipBits reorders sequences of keylen bits in one byte.
* E.g. source order 7654321 will be converted to 45670123 when keylen = 4,
* and to 67452301 when keylen = 2. This is necessary because ordering on
* the isdn line is the other way.
*/
static inline unsigned char
FlipBits(unsigned char c, int keylen)
{
unsigned char b = c;
unsigned char bit = 128;
int i;
int j;
int hunks = (8 / keylen);
c = 0;
for (i = 0; i < hunks; i++) {
for (j = 0; j < keylen; j++) {
if (b & (bit >> j))
c |= bit >> (keylen - j - 1);
}
bit >>= keylen;
}
return c;
}
/* isdn_v110_open allocates and initializes private V.110 data
* structures and returns a pointer to these.
*/
static isdn_v110_stream *
isdn_v110_open(unsigned char key, int hdrlen, int maxsize)
{
int i;
isdn_v110_stream *v;
if ((v = kzalloc(sizeof(isdn_v110_stream), GFP_ATOMIC)) == NULL)
return NULL;
v->key = key;
v->nbits = 0;
for (i = 0; key & (1 << i); i++)
v->nbits++;
v->nbytes = 8 / v->nbits;
v->decodelen = 0;
switch (key) {
case V110_38400:
v->OnlineFrame = V110_OnMatrix_38400;
v->OfflineFrame = V110_OffMatrix_38400;
break;
case V110_19200:
v->OnlineFrame = V110_OnMatrix_19200;
v->OfflineFrame = V110_OffMatrix_19200;
break;
default:
v->OnlineFrame = V110_OnMatrix_9600;
v->OfflineFrame = V110_OffMatrix_9600;
break;
}
v->framelen = v->nbytes * 10;
v->SyncInit = 5;
v->introducer = 0;
v->dbit = 1;
v->b = 0;
v->skbres = hdrlen;
v->maxsize = maxsize - hdrlen;
if ((v->encodebuf = kmalloc(maxsize, GFP_ATOMIC)) == NULL) {
kfree(v);
return NULL;
}
return v;
}
/* isdn_v110_close frees private V.110 data structures */
void
isdn_v110_close(isdn_v110_stream *v)
{
if (v == NULL)
return;
#ifdef ISDN_V110_DEBUG
printk(KERN_DEBUG "v110 close\n");
#endif
kfree(v->encodebuf);
kfree(v);
}
/*
* ValidHeaderBytes return the number of valid bytes in v->decodebuf
*/
static int
ValidHeaderBytes(isdn_v110_stream *v)
{
int i;
for (i = 0; (i < v->decodelen) && (i < v->nbytes); i++)
if ((v->decodebuf[i] & v->key) != 0)
break;
return i;
}
/*
* SyncHeader moves the decodebuf ptr to the next valid header
*/
static void
SyncHeader(isdn_v110_stream *v)
{
unsigned char *rbuf = v->decodebuf;
int len = v->decodelen;
if (len == 0)
return;
for (rbuf++, len--; len > 0; len--, rbuf++) /* such den SyncHeader in buf ! */
if ((*rbuf & v->key) == 0) /* erstes byte gefunden ? */
break; /* jupp! */
if (len)
memcpy(v->decodebuf, rbuf, len);
v->decodelen = len;
#ifdef ISDN_V110_DEBUG
printk(KERN_DEBUG "isdn_v110: Header resync\n");
#endif
}
/* DecodeMatrix takes n (n>=1) matrices (v110 frames, 10 bytes) where
len is the number of matrix-lines. len must be a multiple of 10, i.e.
only complete matices must be given.
From these, netto data is extracted and returned in buf. The return-value
is the bytecount of the decoded data.
*/
static int
DecodeMatrix(isdn_v110_stream *v, unsigned char *m, int len, unsigned char *buf)
{
int line = 0;
int buflen = 0;
int mbit = 64;
int introducer = v->introducer;
int dbit = v->dbit;
unsigned char b = v->b;
while (line < len) { /* Are we done with all lines of the matrix? */
if ((line % 10) == 0) { /* the 0. line of the matrix is always 0 ! */
if (m[line] != 0x00) { /* not 0 ? -> error! */
#ifdef ISDN_V110_DEBUG
printk(KERN_DEBUG "isdn_v110: DecodeMatrix, V110 Bad Header\n");
/* returning now is not the right thing, though :-( */
#endif
}
line++; /* next line of matrix */
continue;
} else if ((line % 10) == 5) { /* in line 5 there's only e-bits ! */
if ((m[line] & 0x70) != 0x30) { /* 011 has to be at the beginning! */
#ifdef ISDN_V110_DEBUG
printk(KERN_DEBUG "isdn_v110: DecodeMatrix, V110 Bad 5th line\n");
/* returning now is not the right thing, though :-( */
#endif
}
line++; /* next line */
continue;
} else if (!introducer) { /* every byte starts with 10 (stopbit, startbit) */
introducer = (m[line] & mbit) ? 0 : 1; /* current bit of the matrix */
next_byte:
if (mbit > 2) { /* was it the last bit in this line ? */
mbit >>= 1; /* no -> take next */
continue;
} /* otherwise start with leftmost bit in the next line */
mbit = 64;
line++;
continue;
} else { /* otherwise we need to set a data bit */
if (m[line] & mbit) /* was that bit set in the matrix ? */
b |= dbit; /* yes -> set it in the data byte */
else
b &= dbit - 1; /* no -> clear it in the data byte */
if (dbit < 128) /* is that data byte done ? */
dbit <<= 1; /* no, got the next bit */
else { /* data byte is done */
buf[buflen++] = b; /* copy byte into the output buffer */
introducer = b = 0; /* init of the intro sequence and of the data byte */
dbit = 1; /* next we look for the 0th bit */
}
goto next_byte; /* look for next bit in the matrix */
}
}
v->introducer = introducer;
v->dbit = dbit;
v->b = b;
return buflen; /* return number of bytes in the output buffer */
}
/*
* DecodeStream receives V.110 coded data from the input stream. It recovers the
* original frames.
* The input stream doesn't need to be framed
*/
struct sk_buff *
isdn_v110_decode(isdn_v110_stream *v, struct sk_buff *skb)
{
int i;
int j;
int len;
unsigned char *v110_buf;
unsigned char *rbuf;
if (!skb) {
printk(KERN_WARNING "isdn_v110_decode called with NULL skb!\n");
return NULL;
}
rbuf = skb->data;
len = skb->len;
if (v == NULL) {
/* invalid handle, no chance to proceed */
printk(KERN_WARNING "isdn_v110_decode called with NULL stream!\n");
dev_kfree_skb(skb);
return NULL;
}
if (v->decodelen == 0) /* cache empty? */
for (; len > 0; len--, rbuf++) /* scan for SyncHeader in buf */
if ((*rbuf & v->key) == 0)
break; /* found first byte */
if (len == 0) {
dev_kfree_skb(skb);
return NULL;
}
/* copy new data to decode-buffer */
memcpy(&(v->decodebuf[v->decodelen]), rbuf, len);
v->decodelen += len;
ReSync:
if (v->decodelen < v->nbytes) { /* got a new header ? */
dev_kfree_skb(skb);
return NULL; /* no, try later */
}
if (ValidHeaderBytes(v) != v->nbytes) { /* is that a valid header? */
SyncHeader(v); /* no -> look for header */
goto ReSync;
}
len = (v->decodelen - (v->decodelen % (10 * v->nbytes))) / v->nbytes;
if ((v110_buf = kmalloc(len, GFP_ATOMIC)) == NULL) {
printk(KERN_WARNING "isdn_v110_decode: Couldn't allocate v110_buf\n");
dev_kfree_skb(skb);
return NULL;
}
for (i = 0; i < len; i++) {
v110_buf[i] = 0;
for (j = 0; j < v->nbytes; j++)
v110_buf[i] |= (v->decodebuf[(i * v->nbytes) + j] & v->key) << (8 - ((j + 1) * v->nbits));
v110_buf[i] = FlipBits(v110_buf[i], v->nbits);
}
v->decodelen = (v->decodelen % (10 * v->nbytes));
memcpy(v->decodebuf, &(v->decodebuf[len * v->nbytes]), v->decodelen);
skb_trim(skb, DecodeMatrix(v, v110_buf, len, skb->data));
kfree(v110_buf);
if (skb->len)
return skb;
else {
kfree_skb(skb);
return NULL;
}
}
/* EncodeMatrix takes input data in buf, len is the bytecount.
Data is encoded into v110 frames in m. Return value is the number of
matrix-lines generated.
*/
static int
EncodeMatrix(unsigned char *buf, int len, unsigned char *m, int mlen)
{
int line = 0;
int i = 0;
int mbit = 128;
int dbit = 1;
int introducer = 3;
int ibit[] = {0, 1, 1};
while ((i < len) && (line < mlen)) { /* while we still have input data */
switch (line % 10) { /* in which line of the matrix are we? */
case 0:
m[line++] = 0x00; /* line 0 is always 0 */
mbit = 128; /* go on with the 7th bit */
break;
case 5:
m[line++] = 0xbf; /* line 5 is always 10111111 */
mbit = 128; /* go on with the 7th bit */
break;
}
if (line >= mlen) {
printk(KERN_WARNING "isdn_v110 (EncodeMatrix): buffer full!\n");
return line;
}
next_bit:
switch (mbit) { /* leftmost or rightmost bit ? */
case 1:
line++; /* rightmost -> go to next line */
if (line >= mlen) {
printk(KERN_WARNING "isdn_v110 (EncodeMatrix): buffer full!\n");
return line;
}
case 128:
m[line] = 128; /* leftmost -> set byte to 1000000 */
mbit = 64; /* current bit in the matrix line */
continue;
}
if (introducer) { /* set 110 sequence ? */
introducer--; /* set on digit less */
m[line] |= ibit[introducer] ? mbit : 0; /* set corresponding bit */
mbit >>= 1; /* bit of matrix line >> 1 */
goto next_bit; /* and go on there */
} /* else push data bits into the matrix! */
m[line] |= (buf[i] & dbit) ? mbit : 0; /* set data bit in matrix */
if (dbit == 128) { /* was it the last one? */
dbit = 1; /* then go on with first bit of */
i++; /* next byte in input buffer */
if (i < len) /* input buffer done ? */
introducer = 3; /* no, write introducer 110 */
else { /* input buffer done ! */
m[line] |= (mbit - 1) & 0xfe; /* set remaining bits in line to 1 */
break;
}
} else /* not the last data bit */
dbit <<= 1; /* then go to next data bit */
mbit >>= 1; /* go to next bit of matrix */
goto next_bit;
}
/* if necessary, generate remaining lines of the matrix... */
if ((line) && ((line + 10) < mlen))
switch (++line % 10) {
case 1:
m[line++] = 0xfe;
case 2:
m[line++] = 0xfe;
case 3:
m[line++] = 0xfe;
case 4:
m[line++] = 0xfe;
case 5:
m[line++] = 0xbf;
case 6:
m[line++] = 0xfe;
case 7:
m[line++] = 0xfe;
case 8:
m[line++] = 0xfe;
case 9:
m[line++] = 0xfe;
}
return line; /* that's how many lines we have */
}
/*
* Build a sync frame.
*/
static struct sk_buff *
isdn_v110_sync(isdn_v110_stream *v)
{
struct sk_buff *skb;
if (v == NULL) {
/* invalid handle, no chance to proceed */
printk(KERN_WARNING "isdn_v110_sync called with NULL stream!\n");
return NULL;
}
if ((skb = dev_alloc_skb(v->framelen + v->skbres))) {
skb_reserve(skb, v->skbres);
memcpy(skb_put(skb, v->framelen), v->OfflineFrame, v->framelen);
}
return skb;
}
/*
* Build an idle frame.
*/
static struct sk_buff *
isdn_v110_idle(isdn_v110_stream *v)
{
struct sk_buff *skb;
if (v == NULL) {
/* invalid handle, no chance to proceed */
printk(KERN_WARNING "isdn_v110_sync called with NULL stream!\n");
return NULL;
}
if ((skb = dev_alloc_skb(v->framelen + v->skbres))) {
skb_reserve(skb, v->skbres);
memcpy(skb_put(skb, v->framelen), v->OnlineFrame, v->framelen);
}
return skb;
}
struct sk_buff *
isdn_v110_encode(isdn_v110_stream *v, struct sk_buff *skb)
{
int i;
int j;
int rlen;
int mlen;
int olen;
int size;
int sval1;
int sval2;
int nframes;
unsigned char *v110buf;
unsigned char *rbuf;
struct sk_buff *nskb;
if (v == NULL) {
/* invalid handle, no chance to proceed */
printk(KERN_WARNING "isdn_v110_encode called with NULL stream!\n");
return NULL;
}
if (!skb) {
/* invalid skb, no chance to proceed */
printk(KERN_WARNING "isdn_v110_encode called with NULL skb!\n");
return NULL;
}
rlen = skb->len;
nframes = (rlen + 3) / 4;
v110buf = v->encodebuf;
if ((nframes * 40) > v->maxsize) {
size = v->maxsize;
rlen = v->maxsize / 40;
} else
size = nframes * 40;
if (!(nskb = dev_alloc_skb(size + v->skbres + sizeof(int)))) {
printk(KERN_WARNING "isdn_v110_encode: Couldn't alloc skb\n");
return NULL;
}
skb_reserve(nskb, v->skbres + sizeof(int));
if (skb->len == 0) {
memcpy(skb_put(nskb, v->framelen), v->OnlineFrame, v->framelen);
*((int *)skb_push(nskb, sizeof(int))) = 0;
return nskb;
}
mlen = EncodeMatrix(skb->data, rlen, v110buf, size);
/* now distribute 2 or 4 bits each to the output stream! */
rbuf = skb_put(nskb, size);
olen = 0;
sval1 = 8 - v->nbits;
sval2 = v->key << sval1;
for (i = 0; i < mlen; i++) {
v110buf[i] = FlipBits(v110buf[i], v->nbits);
for (j = 0; j < v->nbytes; j++) {
if (size--)
*rbuf++ = ~v->key | (((v110buf[i] << (j * v->nbits)) & sval2) >> sval1);
else {
printk(KERN_WARNING "isdn_v110_encode: buffers full!\n");
goto buffer_full;
}
olen++;
}
}
buffer_full:
skb_trim(nskb, olen);
*((int *)skb_push(nskb, sizeof(int))) = rlen;
return nskb;
}
int
isdn_v110_stat_callback(int idx, isdn_ctrl *c)
{
isdn_v110_stream *v = NULL;
int i;
int ret = 0;
if (idx < 0)
return 0;
switch (c->command) {
case ISDN_STAT_BSENT:
/* Keep the send-queue of the driver filled
* with frames:
* If number of outstanding frames < 3,
* send down an Idle-Frame (or an Sync-Frame, if
* v->SyncInit != 0).
*/
if (!(v = dev->v110[idx]))
return 0;
atomic_inc(&dev->v110use[idx]);
for (i = 0; i * v->framelen < c->parm.length; i++) {
if (v->skbidle > 0) {
v->skbidle--;
ret = 1;
} else {
if (v->skbuser > 0)
v->skbuser--;
ret = 0;
}
}
for (i = v->skbuser + v->skbidle; i < 2; i++) {
struct sk_buff *skb;
if (v->SyncInit > 0)
skb = isdn_v110_sync(v);
else
skb = isdn_v110_idle(v);
if (skb) {
if (dev->drv[c->driver]->interface->writebuf_skb(c->driver, c->arg, 1, skb) <= 0) {
dev_kfree_skb(skb);
break;
} else {
if (v->SyncInit)
v->SyncInit--;
v->skbidle++;
}
} else
break;
}
atomic_dec(&dev->v110use[idx]);
return ret;
case ISDN_STAT_DHUP:
case ISDN_STAT_BHUP:
while (1) {
atomic_inc(&dev->v110use[idx]);
if (atomic_dec_and_test(&dev->v110use[idx])) {
isdn_v110_close(dev->v110[idx]);
dev->v110[idx] = NULL;
break;
}
mdelay(1);
}
break;
case ISDN_STAT_BCONN:
if (dev->v110emu[idx] && (dev->v110[idx] == NULL)) {
int hdrlen = dev->drv[c->driver]->interface->hl_hdrlen;
int maxsize = dev->drv[c->driver]->interface->maxbufsize;
atomic_inc(&dev->v110use[idx]);
switch (dev->v110emu[idx]) {
case ISDN_PROTO_L2_V11096:
dev->v110[idx] = isdn_v110_open(V110_9600, hdrlen, maxsize);
break;
case ISDN_PROTO_L2_V11019:
dev->v110[idx] = isdn_v110_open(V110_19200, hdrlen, maxsize);
break;
case ISDN_PROTO_L2_V11038:
dev->v110[idx] = isdn_v110_open(V110_38400, hdrlen, maxsize);
break;
default:;
}
if ((v = dev->v110[idx])) {
while (v->SyncInit) {
struct sk_buff *skb = isdn_v110_sync(v);
if (dev->drv[c->driver]->interface->writebuf_skb(c->driver, c->arg, 1, skb) <= 0) {
dev_kfree_skb(skb);
/* Unable to send, try later */
break;
}
v->SyncInit--;
v->skbidle++;
}
} else
printk(KERN_WARNING "isdn_v110: Couldn't open stream for chan %d\n", idx);
atomic_dec(&dev->v110use[idx]);
}
break;
default:
return 0;
}
return 0;
}
| gpl-2.0 |
ronasimi/LGF180-Optimus-G-_Android_KK_v30a_Kernel | drivers/isdn/hisax/l3dss1.c | 9553 | 78840 | /* $Id: l3dss1.c,v 2.32.2.3 2004/01/13 14:31:25 keil Exp $
*
* EURO/DSS1 D-channel protocol
*
* German 1TR6 D-channel protocol
*
* Author Karsten Keil
* based on the teles driver from Jan den Ouden
* Copyright by Karsten Keil <keil@isdn4linux.de>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
* For changes and modifications please read
* Documentation/isdn/HiSax.cert
*
* Thanks to Jan den Ouden
* Fritz Elfert
*
*/
#include "hisax.h"
#include "isdnl3.h"
#include "l3dss1.h"
#include <linux/ctype.h>
#include <linux/slab.h>
extern char *HiSax_getrev(const char *revision);
static const char *dss1_revision = "$Revision: 2.32.2.3 $";
#define EXT_BEARER_CAPS 1
#define MsgHead(ptr, cref, mty) \
*ptr++ = 0x8; \
if (cref == -1) { \
*ptr++ = 0x0; \
} else { \
*ptr++ = 0x1; \
*ptr++ = cref^0x80; \
} \
*ptr++ = mty
/**********************************************/
/* get a new invoke id for remote operations. */
/* Only a return value != 0 is valid */
/**********************************************/
static unsigned char new_invoke_id(struct PStack *p)
{
unsigned char retval;
int i;
i = 32; /* maximum search depth */
retval = p->prot.dss1.last_invoke_id + 1; /* try new id */
while ((i) && (p->prot.dss1.invoke_used[retval >> 3] == 0xFF)) {
p->prot.dss1.last_invoke_id = (retval & 0xF8) + 8;
i--;
}
if (i) {
while (p->prot.dss1.invoke_used[retval >> 3] & (1 << (retval & 7)))
retval++;
} else
retval = 0;
p->prot.dss1.last_invoke_id = retval;
p->prot.dss1.invoke_used[retval >> 3] |= (1 << (retval & 7));
return (retval);
} /* new_invoke_id */
/*************************/
/* free a used invoke id */
/*************************/
static void free_invoke_id(struct PStack *p, unsigned char id)
{
if (!id) return; /* 0 = invalid value */
p->prot.dss1.invoke_used[id >> 3] &= ~(1 << (id & 7));
} /* free_invoke_id */
/**********************************************************/
/* create a new l3 process and fill in dss1 specific data */
/**********************************************************/
static struct l3_process
*dss1_new_l3_process(struct PStack *st, int cr)
{ struct l3_process *proc;
if (!(proc = new_l3_process(st, cr)))
return (NULL);
proc->prot.dss1.invoke_id = 0;
proc->prot.dss1.remote_operation = 0;
proc->prot.dss1.uus1_data[0] = '\0';
return (proc);
} /* dss1_new_l3_process */
/************************************************/
/* free a l3 process and all dss1 specific data */
/************************************************/
static void
dss1_release_l3_process(struct l3_process *p)
{
free_invoke_id(p->st, p->prot.dss1.invoke_id);
release_l3_process(p);
} /* dss1_release_l3_process */
/********************************************************/
/* search a process with invoke id id and dummy callref */
/********************************************************/
static struct l3_process *
l3dss1_search_dummy_proc(struct PStack *st, int id)
{ struct l3_process *pc = st->l3.proc; /* start of processes */
if (!id) return (NULL);
while (pc)
{ if ((pc->callref == -1) && (pc->prot.dss1.invoke_id == id))
return (pc);
pc = pc->next;
}
return (NULL);
} /* l3dss1_search_dummy_proc */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a return result is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_return_result(struct PStack *st, int id, u_char *p, u_char nlen)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
struct l3_process *pc = NULL;
if ((pc = l3dss1_search_dummy_proc(st, id)))
{ L3DelTimer(&pc->timer); /* remove timer */
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_RES;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = 0;
ic.parm.dss1_io.datalen = nlen;
ic.parm.dss1_io.data = p;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
}
else
l3_debug(st, "dummy return result id=0x%x result len=%d", id, nlen);
} /* l3dss1_dummy_return_result */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a return error is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_error_return(struct PStack *st, int id, ulong error)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
struct l3_process *pc = NULL;
if ((pc = l3dss1_search_dummy_proc(st, id)))
{ L3DelTimer(&pc->timer); /* remove timer */
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_ERR;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = error;
ic.parm.dss1_io.datalen = 0;
ic.parm.dss1_io.data = NULL;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
}
else
l3_debug(st, "dummy return error id=0x%x error=0x%lx", id, error);
} /* l3dss1_error_return */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a invoke is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_invoke(struct PStack *st, int cr, int id,
int ident, u_char *p, u_char nlen)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
l3_debug(st, "dummy invoke %s id=0x%x ident=0x%x datalen=%d",
(cr == -1) ? "local" : "broadcast", id, ident, nlen);
if (cr >= -1) return; /* ignore local data */
cs = st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_BRD;
ic.parm.dss1_io.hl_id = id;
ic.parm.dss1_io.ll_id = 0;
ic.parm.dss1_io.proc = ident;
ic.parm.dss1_io.timeout = 0;
ic.parm.dss1_io.datalen = nlen;
ic.parm.dss1_io.data = p;
cs->iif.statcallb(&ic);
} /* l3dss1_dummy_invoke */
static void
l3dss1_parse_facility(struct PStack *st, struct l3_process *pc,
int cr, u_char *p)
{
int qd_len = 0;
unsigned char nlen = 0, ilen, cp_tag;
int ident, id;
ulong err_ret;
if (pc)
st = pc->st; /* valid Stack */
else
if ((!st) || (cr >= 0)) return; /* neither pc nor st specified */
p++;
qd_len = *p++;
if (qd_len == 0) {
l3_debug(st, "qd_len == 0");
return;
}
if ((*p & 0x1F) != 0x11) { /* Service discriminator, supplementary service */
l3_debug(st, "supplementary service != 0x11");
return;
}
while (qd_len > 0 && !(*p & 0x80)) { /* extension ? */
p++;
qd_len--;
}
if (qd_len < 2) {
l3_debug(st, "qd_len < 2");
return;
}
p++;
qd_len--;
if ((*p & 0xE0) != 0xA0) { /* class and form */
l3_debug(st, "class and form != 0xA0");
return;
}
cp_tag = *p & 0x1F; /* remember tag value */
p++;
qd_len--;
if (qd_len < 1)
{ l3_debug(st, "qd_len < 1");
return;
}
if (*p & 0x80)
{ /* length format indefinite or limited */
nlen = *p++ & 0x7F; /* number of len bytes or indefinite */
if ((qd_len-- < ((!nlen) ? 3 : (1 + nlen))) ||
(nlen > 1))
{ l3_debug(st, "length format error or not implemented");
return;
}
if (nlen == 1)
{ nlen = *p++; /* complete length */
qd_len--;
}
else
{ qd_len -= 2; /* trailing null bytes */
if ((*(p + qd_len)) || (*(p + qd_len + 1)))
{ l3_debug(st, "length format indefinite error");
return;
}
nlen = qd_len;
}
}
else
{ nlen = *p++;
qd_len--;
}
if (qd_len < nlen)
{ l3_debug(st, "qd_len < nlen");
return;
}
qd_len -= nlen;
if (nlen < 2)
{ l3_debug(st, "nlen < 2");
return;
}
if (*p != 0x02)
{ /* invoke identifier tag */
l3_debug(st, "invoke identifier tag !=0x02");
return;
}
p++;
nlen--;
if (*p & 0x80)
{ /* length format */
l3_debug(st, "invoke id length format 2");
return;
}
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0)
{ l3_debug(st, "ilen > nlen || ilen == 0");
return;
}
nlen -= ilen;
id = 0;
while (ilen > 0)
{ id = (id << 8) | (*p++ & 0xFF); /* invoke identifier */
ilen--;
}
switch (cp_tag) { /* component tag */
case 1: /* invoke */
if (nlen < 2) {
l3_debug(st, "nlen < 2 22");
return;
}
if (*p != 0x02) { /* operation value */
l3_debug(st, "operation value !=0x02");
return;
}
p++;
nlen--;
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0) {
l3_debug(st, "ilen > nlen || ilen == 0 22");
return;
}
nlen -= ilen;
ident = 0;
while (ilen > 0) {
ident = (ident << 8) | (*p++ & 0xFF);
ilen--;
}
if (!pc)
{ l3dss1_dummy_invoke(st, cr, id, ident, p, nlen);
return;
}
#ifdef CONFIG_DE_AOC
{
#define FOO1(s, a, b) \
while (nlen > 1) { \
int ilen = p[1]; \
if (nlen < ilen + 2) { \
l3_debug(st, "FOO1 nlen < ilen+2"); \
return; \
} \
nlen -= ilen + 2; \
if ((*p & 0xFF) == (a)) { \
int nlen = ilen; \
p += 2; \
b; \
} else { \
p += ilen + 2; \
} \
}
switch (ident) {
case 0x22: /* during */
FOO1("1A", 0x30, FOO1("1C", 0xA1, FOO1("1D", 0x30, FOO1("1E", 0x02, ( {
ident = 0;
nlen = (nlen) ? nlen : 0; /* Make gcc happy */
while (ilen > 0) {
ident = (ident << 8) | *p++;
ilen--;
}
if (ident > pc->para.chargeinfo) {
pc->para.chargeinfo = ident;
st->l3.l3l4(st, CC_CHARGE | INDICATION, pc);
}
if (st->l3.debug & L3_DEB_CHARGE) {
if (*(p + 2) == 0) {
l3_debug(st, "charging info during %d", pc->para.chargeinfo);
}
else {
l3_debug(st, "charging info final %d", pc->para.chargeinfo);
}
}
}
)))))
break;
case 0x24: /* final */
FOO1("2A", 0x30, FOO1("2B", 0x30, FOO1("2C", 0xA1, FOO1("2D", 0x30, FOO1("2E", 0x02, ( {
ident = 0;
nlen = (nlen) ? nlen : 0; /* Make gcc happy */
while (ilen > 0) {
ident = (ident << 8) | *p++;
ilen--;
}
if (ident > pc->para.chargeinfo) {
pc->para.chargeinfo = ident;
st->l3.l3l4(st, CC_CHARGE | INDICATION, pc);
}
if (st->l3.debug & L3_DEB_CHARGE) {
l3_debug(st, "charging info final %d", pc->para.chargeinfo);
}
}
))))))
break;
default:
l3_debug(st, "invoke break invalid ident %02x", ident);
break;
}
#undef FOO1
}
#else /* not CONFIG_DE_AOC */
l3_debug(st, "invoke break");
#endif /* not CONFIG_DE_AOC */
break;
case 2: /* return result */
/* if no process available handle separately */
if (!pc)
{ if (cr == -1)
l3dss1_dummy_return_result(st, id, p, nlen);
return;
}
if ((pc->prot.dss1.invoke_id) && (pc->prot.dss1.invoke_id == id))
{ /* Diversion successful */
free_invoke_id(st, pc->prot.dss1.invoke_id);
pc->prot.dss1.remote_result = 0; /* success */
pc->prot.dss1.invoke_id = 0;
pc->redir_result = pc->prot.dss1.remote_result;
st->l3.l3l4(st, CC_REDIR | INDICATION, pc); } /* Diversion successful */
else
l3_debug(st, "return error unknown identifier");
break;
case 3: /* return error */
err_ret = 0;
if (nlen < 2)
{ l3_debug(st, "return error nlen < 2");
return;
}
if (*p != 0x02)
{ /* result tag */
l3_debug(st, "invoke error tag !=0x02");
return;
}
p++;
nlen--;
if (*p > 4)
{ /* length format */
l3_debug(st, "invoke return errlen > 4 ");
return;
}
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0)
{ l3_debug(st, "error return ilen > nlen || ilen == 0");
return;
}
nlen -= ilen;
while (ilen > 0)
{ err_ret = (err_ret << 8) | (*p++ & 0xFF); /* error value */
ilen--;
}
/* if no process available handle separately */
if (!pc)
{ if (cr == -1)
l3dss1_dummy_error_return(st, id, err_ret);
return;
}
if ((pc->prot.dss1.invoke_id) && (pc->prot.dss1.invoke_id == id))
{ /* Deflection error */
free_invoke_id(st, pc->prot.dss1.invoke_id);
pc->prot.dss1.remote_result = err_ret; /* result */
pc->prot.dss1.invoke_id = 0;
pc->redir_result = pc->prot.dss1.remote_result;
st->l3.l3l4(st, CC_REDIR | INDICATION, pc);
} /* Deflection error */
else
l3_debug(st, "return result unknown identifier");
break;
default:
l3_debug(st, "facility default break tag=0x%02x", cp_tag);
break;
}
}
static void
l3dss1_message(struct l3_process *pc, u_char mt)
{
struct sk_buff *skb;
u_char *p;
if (!(skb = l3_alloc_skb(4)))
return;
p = skb_put(skb, 4);
MsgHead(p, pc->callref, mt);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_message_cause(struct l3_process *pc, u_char mt, u_char cause)
{
struct sk_buff *skb;
u_char tmp[16];
u_char *p = tmp;
int l;
MsgHead(p, pc->callref, mt);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_status_send(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
MsgHead(p, pc->callref, MT_STATUS);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = pc->para.cause | 0x80;
*p++ = IE_CALL_STATE;
*p++ = 0x1;
*p++ = pc->state & 0x3f;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_msg_without_setup(struct l3_process *pc, u_char pr, void *arg)
{
/* This routine is called if here was no SETUP made (checks in dss1up and in
* l3dss1_setup) and a RELEASE_COMPLETE have to be sent with an error code
* MT_STATUS_ENQUIRE in the NULL state is handled too
*/
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
switch (pc->para.cause) {
case 81: /* invalid callreference */
case 88: /* incomp destination */
case 96: /* mandory IE missing */
case 100: /* invalid IE contents */
case 101: /* incompatible Callstate */
MsgHead(p, pc->callref, MT_RELEASE_COMPLETE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = pc->para.cause | 0x80;
break;
default:
printk(KERN_ERR "HiSax l3dss1_msg_without_setup wrong cause %d\n",
pc->para.cause);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
dss1_release_l3_process(pc);
}
static int ie_ALERTING[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, IE_HLC,
IE_USER_USER, -1};
static int ie_CALL_PROCEEDING[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_HLC, -1};
static int ie_CONNECT[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_DATE, IE_SIGNAL,
IE_CONNECT_PN, IE_CONNECT_SUB, IE_LLC, IE_HLC, IE_USER_USER, -1};
static int ie_CONNECT_ACKNOWLEDGE[] = {IE_CHANNEL_ID, IE_DISPLAY, IE_SIGNAL, -1};
static int ie_DISCONNECT[] = {IE_CAUSE | IE_MANDATORY, IE_FACILITY,
IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, IE_USER_USER, -1};
static int ie_INFORMATION[] = {IE_COMPLETE, IE_DISPLAY, IE_KEYPAD, IE_SIGNAL,
IE_CALLED_PN, -1};
static int ie_NOTIFY[] = {IE_BEARER, IE_NOTIFY | IE_MANDATORY, IE_DISPLAY, -1};
static int ie_PROGRESS[] = {IE_BEARER, IE_CAUSE, IE_FACILITY, IE_PROGRESS |
IE_MANDATORY, IE_DISPLAY, IE_HLC, IE_USER_USER, -1};
static int ie_RELEASE[] = {IE_CAUSE | IE_MANDATORY_1, IE_FACILITY, IE_DISPLAY,
IE_SIGNAL, IE_USER_USER, -1};
/* a RELEASE_COMPLETE with errors don't require special actions
static int ie_RELEASE_COMPLETE[] = {IE_CAUSE | IE_MANDATORY_1, IE_DISPLAY, IE_SIGNAL, IE_USER_USER, -1};
*/
static int ie_RESUME_ACKNOWLEDGE[] = {IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY,
IE_DISPLAY, -1};
static int ie_RESUME_REJECT[] = {IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
static int ie_SETUP[] = {IE_COMPLETE, IE_BEARER | IE_MANDATORY,
IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY, IE_PROGRESS,
IE_NET_FAC, IE_DISPLAY, IE_KEYPAD, IE_SIGNAL, IE_CALLING_PN,
IE_CALLING_SUB, IE_CALLED_PN, IE_CALLED_SUB, IE_REDIR_NR,
IE_LLC, IE_HLC, IE_USER_USER, -1};
static int ie_SETUP_ACKNOWLEDGE[] = {IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY,
IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, -1};
static int ie_STATUS[] = {IE_CAUSE | IE_MANDATORY, IE_CALL_STATE |
IE_MANDATORY, IE_DISPLAY, -1};
static int ie_STATUS_ENQUIRY[] = {IE_DISPLAY, -1};
static int ie_SUSPEND_ACKNOWLEDGE[] = {IE_DISPLAY, IE_FACILITY, -1};
static int ie_SUSPEND_REJECT[] = {IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
/* not used
* static int ie_CONGESTION_CONTROL[] = {IE_CONGESTION | IE_MANDATORY,
* IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
* static int ie_USER_INFORMATION[] = {IE_MORE_DATA, IE_USER_USER | IE_MANDATORY, -1};
* static int ie_RESTART[] = {IE_CHANNEL_ID, IE_DISPLAY, IE_RESTART_IND |
* IE_MANDATORY, -1};
*/
static int ie_FACILITY[] = {IE_FACILITY | IE_MANDATORY, IE_DISPLAY, -1};
static int comp_required[] = {1, 2, 3, 5, 6, 7, 9, 10, 11, 14, 15, -1};
static int l3_valid_states[] = {0, 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 15, 17, 19, 25, -1};
struct ie_len {
int ie;
int len;
};
static
struct ie_len max_ie_len[] = {
{IE_SEGMENT, 4},
{IE_BEARER, 12},
{IE_CAUSE, 32},
{IE_CALL_ID, 10},
{IE_CALL_STATE, 3},
{IE_CHANNEL_ID, 34},
{IE_FACILITY, 255},
{IE_PROGRESS, 4},
{IE_NET_FAC, 255},
{IE_NOTIFY, 3},
{IE_DISPLAY, 82},
{IE_DATE, 8},
{IE_KEYPAD, 34},
{IE_SIGNAL, 3},
{IE_INFORATE, 6},
{IE_E2E_TDELAY, 11},
{IE_TDELAY_SEL, 5},
{IE_PACK_BINPARA, 3},
{IE_PACK_WINSIZE, 4},
{IE_PACK_SIZE, 4},
{IE_CUG, 7},
{IE_REV_CHARGE, 3},
{IE_CALLING_PN, 24},
{IE_CALLING_SUB, 23},
{IE_CALLED_PN, 24},
{IE_CALLED_SUB, 23},
{IE_REDIR_NR, 255},
{IE_TRANS_SEL, 255},
{IE_RESTART_IND, 3},
{IE_LLC, 18},
{IE_HLC, 5},
{IE_USER_USER, 131},
{-1, 0},
};
static int
getmax_ie_len(u_char ie) {
int i = 0;
while (max_ie_len[i].ie != -1) {
if (max_ie_len[i].ie == ie)
return (max_ie_len[i].len);
i++;
}
return (255);
}
static int
ie_in_set(struct l3_process *pc, u_char ie, int *checklist) {
int ret = 1;
while (*checklist != -1) {
if ((*checklist & 0xff) == ie) {
if (ie & 0x80)
return (-ret);
else
return (ret);
}
ret++;
checklist++;
}
return (0);
}
static int
check_infoelements(struct l3_process *pc, struct sk_buff *skb, int *checklist)
{
int *cl = checklist;
u_char mt;
u_char *p, ie;
int l, newpos, oldpos;
int err_seq = 0, err_len = 0, err_compr = 0, err_ureg = 0;
u_char codeset = 0;
u_char old_codeset = 0;
u_char codelock = 1;
p = skb->data;
/* skip cr */
p++;
l = (*p++) & 0xf;
p += l;
mt = *p++;
oldpos = 0;
while ((p - skb->data) < skb->len) {
if ((*p & 0xf0) == 0x90) { /* shift codeset */
old_codeset = codeset;
codeset = *p & 7;
if (*p & 0x08)
codelock = 0;
else
codelock = 1;
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE shift%scodeset %d->%d",
codelock ? " locking " : " ", old_codeset, codeset);
p++;
continue;
}
if (!codeset) { /* only codeset 0 */
if ((newpos = ie_in_set(pc, *p, cl))) {
if (newpos > 0) {
if (newpos < oldpos)
err_seq++;
else
oldpos = newpos;
}
} else {
if (ie_in_set(pc, *p, comp_required))
err_compr++;
else
err_ureg++;
}
}
ie = *p++;
if (ie & 0x80) {
l = 1;
} else {
l = *p++;
p += l;
l += 2;
}
if (!codeset && (l > getmax_ie_len(ie)))
err_len++;
if (!codelock) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE shift back codeset %d->%d",
codeset, old_codeset);
codeset = old_codeset;
codelock = 1;
}
}
if (err_compr | err_ureg | err_len | err_seq) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE MT(%x) %d/%d/%d/%d",
mt, err_compr, err_ureg, err_len, err_seq);
if (err_compr)
return (ERR_IE_COMPREHENSION);
if (err_ureg)
return (ERR_IE_UNRECOGNIZED);
if (err_len)
return (ERR_IE_LENGTH);
if (err_seq)
return (ERR_IE_SEQUENCE);
}
return (0);
}
/* verify if a message type exists and contain no IE error */
static int
l3dss1_check_messagetype_validity(struct l3_process *pc, int mt, void *arg)
{
switch (mt) {
case MT_ALERTING:
case MT_CALL_PROCEEDING:
case MT_CONNECT:
case MT_CONNECT_ACKNOWLEDGE:
case MT_DISCONNECT:
case MT_INFORMATION:
case MT_FACILITY:
case MT_NOTIFY:
case MT_PROGRESS:
case MT_RELEASE:
case MT_RELEASE_COMPLETE:
case MT_SETUP:
case MT_SETUP_ACKNOWLEDGE:
case MT_RESUME_ACKNOWLEDGE:
case MT_RESUME_REJECT:
case MT_SUSPEND_ACKNOWLEDGE:
case MT_SUSPEND_REJECT:
case MT_USER_INFORMATION:
case MT_RESTART:
case MT_RESTART_ACKNOWLEDGE:
case MT_CONGESTION_CONTROL:
case MT_STATUS:
case MT_STATUS_ENQUIRY:
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "l3dss1_check_messagetype_validity mt(%x) OK", mt);
break;
case MT_RESUME: /* RESUME only in user->net */
case MT_SUSPEND: /* SUSPEND only in user->net */
default:
if (pc->debug & (L3_DEB_CHECK | L3_DEB_WARN))
l3_debug(pc->st, "l3dss1_check_messagetype_validity mt(%x) fail", mt);
pc->para.cause = 97;
l3dss1_status_send(pc, 0, NULL);
return (1);
}
return (0);
}
static void
l3dss1_std_ie_err(struct l3_process *pc, int ret) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check_infoelements ret %d", ret);
switch (ret) {
case 0:
break;
case ERR_IE_COMPREHENSION:
pc->para.cause = 96;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_UNRECOGNIZED:
pc->para.cause = 99;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_LENGTH:
pc->para.cause = 100;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_SEQUENCE:
default:
break;
}
}
static int
l3dss1_get_channel_id(struct l3_process *pc, struct sk_buff *skb) {
u_char *p;
p = skb->data;
if ((p = findie(p, skb->len, IE_CHANNEL_ID, 0))) {
p++;
if (*p != 1) { /* len for BRI = 1 */
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong chid len %d", *p);
return (-2);
}
p++;
if (*p & 0x60) { /* only base rate interface */
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong chid %x", *p);
return (-3);
}
return (*p & 0x3);
} else
return (-1);
}
static int
l3dss1_get_cause(struct l3_process *pc, struct sk_buff *skb) {
u_char l, i = 0;
u_char *p;
p = skb->data;
pc->para.cause = 31;
pc->para.loc = 0;
if ((p = findie(p, skb->len, IE_CAUSE, 0))) {
p++;
l = *p++;
if (l > 30)
return (1);
if (l) {
pc->para.loc = *p++;
l--;
} else {
return (2);
}
if (l && !(pc->para.loc & 0x80)) {
l--;
p++; /* skip recommendation */
}
if (l) {
pc->para.cause = *p++;
l--;
if (!(pc->para.cause & 0x80))
return (3);
} else
return (4);
while (l && (i < 6)) {
pc->para.diag[i++] = *p++;
l--;
}
} else
return (-1);
return (0);
}
static void
l3dss1_msg_with_uus(struct l3_process *pc, u_char cmd)
{
struct sk_buff *skb;
u_char tmp[16 + 40];
u_char *p = tmp;
int l;
MsgHead(p, pc->callref, cmd);
if (pc->prot.dss1.uus1_data[0])
{ *p++ = IE_USER_USER; /* UUS info element */
*p++ = strlen(pc->prot.dss1.uus1_data) + 1;
*p++ = 0x04; /* IA5 chars */
strcpy(p, pc->prot.dss1.uus1_data);
p += strlen(pc->prot.dss1.uus1_data);
pc->prot.dss1.uus1_data[0] = '\0';
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
} /* l3dss1_msg_with_uus */
static void
l3dss1_release_req(struct l3_process *pc, u_char pr, void *arg)
{
StopAllL3Timer(pc);
newl3state(pc, 19);
if (!pc->prot.dss1.uus1_data[0])
l3dss1_message(pc, MT_RELEASE);
else
l3dss1_msg_with_uus(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_release_cmpl(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb)) > 0) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "RELCMPL get_cause ret(%d)", ret);
} else if (ret < 0)
pc->para.cause = NO_CAUSE;
StopAllL3Timer(pc);
newl3state(pc, 0);
pc->st->l3.l3l4(pc->st, CC_RELEASE | CONFIRM, pc);
dss1_release_l3_process(pc);
}
#ifdef EXT_BEARER_CAPS
static u_char *
EncodeASyncParams(u_char *p, u_char si2)
{ // 7c 06 88 90 21 42 00 bb
p[0] = 0;
p[1] = 0x40; // Intermediate rate: 16 kbit/s jj 2000.02.19
p[2] = 0x80;
if (si2 & 32) // 7 data bits
p[2] += 16;
else // 8 data bits
p[2] += 24;
if (si2 & 16) // 2 stop bits
p[2] += 96;
else // 1 stop bit
p[2] += 32;
if (si2 & 8) // even parity
p[2] += 2;
else // no parity
p[2] += 3;
switch (si2 & 0x07) {
case 0:
p[0] = 66; // 1200 bit/s
break;
case 1:
p[0] = 88; // 1200/75 bit/s
break;
case 2:
p[0] = 87; // 75/1200 bit/s
break;
case 3:
p[0] = 67; // 2400 bit/s
break;
case 4:
p[0] = 69; // 4800 bit/s
break;
case 5:
p[0] = 72; // 9600 bit/s
break;
case 6:
p[0] = 73; // 14400 bit/s
break;
case 7:
p[0] = 75; // 19200 bit/s
break;
}
return p + 3;
}
static u_char
EncodeSyncParams(u_char si2, u_char ai)
{
switch (si2) {
case 0:
return ai + 2; // 1200 bit/s
case 1:
return ai + 24; // 1200/75 bit/s
case 2:
return ai + 23; // 75/1200 bit/s
case 3:
return ai + 3; // 2400 bit/s
case 4:
return ai + 5; // 4800 bit/s
case 5:
return ai + 8; // 9600 bit/s
case 6:
return ai + 9; // 14400 bit/s
case 7:
return ai + 11; // 19200 bit/s
case 8:
return ai + 14; // 48000 bit/s
case 9:
return ai + 15; // 56000 bit/s
case 15:
return ai + 40; // negotiate bit/s
default:
break;
}
return ai;
}
static u_char
DecodeASyncParams(u_char si2, u_char *p)
{
u_char info;
switch (p[5]) {
case 66: // 1200 bit/s
break; // si2 don't change
case 88: // 1200/75 bit/s
si2 += 1;
break;
case 87: // 75/1200 bit/s
si2 += 2;
break;
case 67: // 2400 bit/s
si2 += 3;
break;
case 69: // 4800 bit/s
si2 += 4;
break;
case 72: // 9600 bit/s
si2 += 5;
break;
case 73: // 14400 bit/s
si2 += 6;
break;
case 75: // 19200 bit/s
si2 += 7;
break;
}
info = p[7] & 0x7f;
if ((info & 16) && (!(info & 8))) // 7 data bits
si2 += 32; // else 8 data bits
if ((info & 96) == 96) // 2 stop bits
si2 += 16; // else 1 stop bit
if ((info & 2) && (!(info & 1))) // even parity
si2 += 8; // else no parity
return si2;
}
static u_char
DecodeSyncParams(u_char si2, u_char info)
{
info &= 0x7f;
switch (info) {
case 40: // bit/s negotiation failed ai := 165 not 175!
return si2 + 15;
case 15: // 56000 bit/s failed, ai := 0 not 169 !
return si2 + 9;
case 14: // 48000 bit/s
return si2 + 8;
case 11: // 19200 bit/s
return si2 + 7;
case 9: // 14400 bit/s
return si2 + 6;
case 8: // 9600 bit/s
return si2 + 5;
case 5: // 4800 bit/s
return si2 + 4;
case 3: // 2400 bit/s
return si2 + 3;
case 23: // 75/1200 bit/s
return si2 + 2;
case 24: // 1200/75 bit/s
return si2 + 1;
default: // 1200 bit/s
return si2;
}
}
static u_char
DecodeSI2(struct sk_buff *skb)
{
u_char *p; //, *pend=skb->data + skb->len;
if ((p = findie(skb->data, skb->len, 0x7c, 0))) {
switch (p[4] & 0x0f) {
case 0x01:
if (p[1] == 0x04) // sync. Bitratenadaption
return DecodeSyncParams(160, p[5]); // V.110/X.30
else if (p[1] == 0x06) // async. Bitratenadaption
return DecodeASyncParams(192, p); // V.110/X.30
break;
case 0x08: // if (p[5] == 0x02) // sync. Bitratenadaption
if (p[1] > 3)
return DecodeSyncParams(176, p[5]); // V.120
break;
}
}
return 0;
}
#endif
static void
l3dss1_setup_req(struct l3_process *pc, u_char pr,
void *arg)
{
struct sk_buff *skb;
u_char tmp[128];
u_char *p = tmp;
u_char channel = 0;
u_char send_keypad;
u_char screen = 0x80;
u_char *teln;
u_char *msn;
u_char *sub;
u_char *sp;
int l;
MsgHead(p, pc->callref, MT_SETUP);
teln = pc->para.setup.phone;
#ifndef CONFIG_HISAX_NO_KEYPAD
send_keypad = (strchr(teln, '*') || strchr(teln, '#')) ? 1 : 0;
#else
send_keypad = 0;
#endif
#ifndef CONFIG_HISAX_NO_SENDCOMPLETE
if (!send_keypad)
*p++ = 0xa1; /* complete indicator */
#endif
/*
* Set Bearer Capability, Map info from 1TR6-convention to EDSS1
*/
switch (pc->para.setup.si1) {
case 1: /* Telephony */
*p++ = IE_BEARER;
*p++ = 0x3; /* Length */
*p++ = 0x90; /* Coding Std. CCITT, 3.1 kHz audio */
*p++ = 0x90; /* Circuit-Mode 64kbps */
*p++ = 0xa3; /* A-Law Audio */
break;
case 5: /* Datatransmission 64k, BTX */
case 7: /* Datatransmission 64k */
default:
*p++ = IE_BEARER;
*p++ = 0x2; /* Length */
*p++ = 0x88; /* Coding Std. CCITT, unrestr. dig. Inform. */
*p++ = 0x90; /* Circuit-Mode 64kbps */
break;
}
if (send_keypad) {
*p++ = IE_KEYPAD;
*p++ = strlen(teln);
while (*teln)
*p++ = (*teln++) & 0x7F;
}
/*
* What about info2? Mapping to High-Layer-Compatibility?
*/
if ((*teln) && (!send_keypad)) {
/* parse number for special things */
if (!isdigit(*teln)) {
switch (0x5f & *teln) {
case 'C':
channel = 0x08;
case 'P':
channel |= 0x80;
teln++;
if (*teln == '1')
channel |= 0x01;
else
channel |= 0x02;
break;
case 'R':
screen = 0xA0;
break;
case 'D':
screen = 0x80;
break;
default:
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "Wrong MSN Code");
break;
}
teln++;
}
}
if (channel) {
*p++ = IE_CHANNEL_ID;
*p++ = 1;
*p++ = channel;
}
msn = pc->para.setup.eazmsn;
sub = NULL;
sp = msn;
while (*sp) {
if ('.' == *sp) {
sub = sp;
*sp = 0;
} else
sp++;
}
if (*msn) {
*p++ = IE_CALLING_PN;
*p++ = strlen(msn) + (screen ? 2 : 1);
/* Classify as AnyPref. */
if (screen) {
*p++ = 0x01; /* Ext = '0'B, Type = '000'B, Plan = '0001'B. */
*p++ = screen;
} else
*p++ = 0x81; /* Ext = '1'B, Type = '000'B, Plan = '0001'B. */
while (*msn)
*p++ = *msn++ & 0x7f;
}
if (sub) {
*sub++ = '.';
*p++ = IE_CALLING_SUB;
*p++ = strlen(sub) + 2;
*p++ = 0x80; /* NSAP coded */
*p++ = 0x50; /* local IDI format */
while (*sub)
*p++ = *sub++ & 0x7f;
}
sub = NULL;
sp = teln;
while (*sp) {
if ('.' == *sp) {
sub = sp;
*sp = 0;
} else
sp++;
}
if (!send_keypad) {
*p++ = IE_CALLED_PN;
*p++ = strlen(teln) + 1;
/* Classify as AnyPref. */
*p++ = 0x81; /* Ext = '1'B, Type = '000'B, Plan = '0001'B. */
while (*teln)
*p++ = *teln++ & 0x7f;
if (sub) {
*sub++ = '.';
*p++ = IE_CALLED_SUB;
*p++ = strlen(sub) + 2;
*p++ = 0x80; /* NSAP coded */
*p++ = 0x50; /* local IDI format */
while (*sub)
*p++ = *sub++ & 0x7f;
}
}
#ifdef EXT_BEARER_CAPS
if ((pc->para.setup.si2 >= 160) && (pc->para.setup.si2 <= 175)) { // sync. Bitratenadaption, V.110/X.30
*p++ = IE_LLC;
*p++ = 0x04;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x21;
*p++ = EncodeSyncParams(pc->para.setup.si2 - 160, 0x80);
} else if ((pc->para.setup.si2 >= 176) && (pc->para.setup.si2 <= 191)) { // sync. Bitratenadaption, V.120
*p++ = IE_LLC;
*p++ = 0x05;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x28;
*p++ = EncodeSyncParams(pc->para.setup.si2 - 176, 0);
*p++ = 0x82;
} else if (pc->para.setup.si2 >= 192) { // async. Bitratenadaption, V.110/X.30
*p++ = IE_LLC;
*p++ = 0x06;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x21;
p = EncodeASyncParams(p, pc->para.setup.si2 - 192);
#ifndef CONFIG_HISAX_NO_LLC
} else {
switch (pc->para.setup.si1) {
case 1: /* Telephony */
*p++ = IE_LLC;
*p++ = 0x3; /* Length */
*p++ = 0x90; /* Coding Std. CCITT, 3.1 kHz audio */
*p++ = 0x90; /* Circuit-Mode 64kbps */
*p++ = 0xa3; /* A-Law Audio */
break;
case 5: /* Datatransmission 64k, BTX */
case 7: /* Datatransmission 64k */
default:
*p++ = IE_LLC;
*p++ = 0x2; /* Length */
*p++ = 0x88; /* Coding Std. CCITT, unrestr. dig. Inform. */
*p++ = 0x90; /* Circuit-Mode 64kbps */
break;
}
#endif
}
#endif
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T303, CC_T303);
newl3state(pc, 1);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_call_proc(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else if (1 == pc->state) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer wrong chid (ret %d)", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
ret = check_infoelements(pc, skb, ie_CALL_PROCEEDING);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
newl3state(pc, 3);
L3AddTimer(&pc->timer, T310, CC_T310);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_PROCEEDING | INDICATION, pc);
}
static void
l3dss1_setup_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer wrong chid (ret %d)", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
ret = check_infoelements(pc, skb, ie_SETUP_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
newl3state(pc, 2);
L3AddTimer(&pc->timer, T304, CC_T304);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_MORE_INFO | INDICATION, pc);
}
static void
l3dss1_disconnect(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
u_char *p;
int ret;
u_char cause = 0;
StopAllL3Timer(pc);
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "DISC get_cause ret(%d)", ret);
if (ret < 0)
cause = 96;
else if (ret > 0)
cause = 100;
}
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0)))
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
ret = check_infoelements(pc, skb, ie_DISCONNECT);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if ((!cause) && (ERR_IE_UNRECOGNIZED == ret))
cause = 99;
ret = pc->state;
newl3state(pc, 12);
if (cause)
newl3state(pc, 19);
if (11 != ret)
pc->st->l3.l3l4(pc->st, CC_DISCONNECT | INDICATION, pc);
else if (!cause)
l3dss1_release_req(pc, pr, NULL);
if (cause) {
l3dss1_message_cause(pc, MT_RELEASE, cause);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
}
static void
l3dss1_connect(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_CONNECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer); /* T310 */
newl3state(pc, 10);
pc->para.chargeinfo = 0;
/* here should inserted COLP handling KKe */
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_SETUP | CONFIRM, pc);
}
static void
l3dss1_alerting(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_ALERTING);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer); /* T304 */
newl3state(pc, 4);
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_ALERTING | INDICATION, pc);
}
static void
l3dss1_setup(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
int bcfound = 0;
char tmp[80];
struct sk_buff *skb = arg;
int id;
int err = 0;
/*
* Bearer Capabilities
*/
p = skb->data;
/* only the first occurrence 'll be detected ! */
if ((p = findie(p, skb->len, 0x04, 0))) {
if ((p[1] < 2) || (p[1] > 11))
err = 1;
else {
pc->para.setup.si2 = 0;
switch (p[2] & 0x7f) {
case 0x00: /* Speech */
case 0x10: /* 3.1 Khz audio */
pc->para.setup.si1 = 1;
break;
case 0x08: /* Unrestricted digital information */
pc->para.setup.si1 = 7;
/* JIM, 05.11.97 I wanna set service indicator 2 */
#ifdef EXT_BEARER_CAPS
pc->para.setup.si2 = DecodeSI2(skb);
#endif
break;
case 0x09: /* Restricted digital information */
pc->para.setup.si1 = 2;
break;
case 0x11:
/* Unrestr. digital information with
* tones/announcements ( or 7 kHz audio
*/
pc->para.setup.si1 = 3;
break;
case 0x18: /* Video */
pc->para.setup.si1 = 4;
break;
default:
err = 2;
break;
}
switch (p[3] & 0x7f) {
case 0x40: /* packed mode */
pc->para.setup.si1 = 8;
break;
case 0x10: /* 64 kbit */
case 0x11: /* 2*64 kbit */
case 0x13: /* 384 kbit */
case 0x15: /* 1536 kbit */
case 0x17: /* 1920 kbit */
pc->para.moderate = p[3] & 0x7f;
break;
default:
err = 3;
break;
}
}
if (pc->debug & L3_DEB_SI)
l3_debug(pc->st, "SI=%d, AI=%d",
pc->para.setup.si1, pc->para.setup.si2);
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong bearer(l=%d:%x,%x)",
p[1], p[2], p[3]);
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup without bearer capabilities");
/* ETS 300-104 1.3.3 */
pc->para.cause = 96;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
/*
* Channel Identification
*/
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((pc->para.bchannel = id)) {
if ((3 == id) && (0x10 == pc->para.moderate)) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong chid %x",
id);
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
bcfound++;
} else
{ if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup without bchannel, call waiting");
bcfound++;
}
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong chid ret %d", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_SETUP);
if (ERR_IE_COMPREHENSION == err) {
pc->para.cause = 96;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
p = skb->data;
if ((p = findie(p, skb->len, 0x70, 0)))
iecpy(pc->para.setup.eazmsn, p, 1);
else
pc->para.setup.eazmsn[0] = 0;
p = skb->data;
if ((p = findie(p, skb->len, 0x71, 0))) {
/* Called party subaddress */
if ((p[1] >= 2) && (p[2] == 0x80) && (p[3] == 0x50)) {
tmp[0] = '.';
iecpy(&tmp[1], p, 2);
strcat(pc->para.setup.eazmsn, tmp);
} else if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong called subaddress");
}
p = skb->data;
if ((p = findie(p, skb->len, 0x6c, 0))) {
pc->para.setup.plan = p[2];
if (p[2] & 0x80) {
iecpy(pc->para.setup.phone, p, 1);
pc->para.setup.screen = 0;
} else {
iecpy(pc->para.setup.phone, p, 2);
pc->para.setup.screen = p[3];
}
} else {
pc->para.setup.phone[0] = 0;
pc->para.setup.plan = 0;
pc->para.setup.screen = 0;
}
p = skb->data;
if ((p = findie(p, skb->len, 0x6d, 0))) {
/* Calling party subaddress */
if ((p[1] >= 2) && (p[2] == 0x80) && (p[3] == 0x50)) {
tmp[0] = '.';
iecpy(&tmp[1], p, 2);
strcat(pc->para.setup.phone, tmp);
} else if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong calling subaddress");
}
newl3state(pc, 6);
if (err) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, err);
pc->st->l3.l3l4(pc->st, CC_SETUP | INDICATION, pc);
}
static void
l3dss1_reset(struct l3_process *pc, u_char pr, void *arg)
{
dss1_release_l3_process(pc);
}
static void
l3dss1_disconnect_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[16 + 40];
u_char *p = tmp;
int l;
u_char cause = 16;
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
StopAllL3Timer(pc);
MsgHead(p, pc->callref, MT_DISCONNECT);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
if (pc->prot.dss1.uus1_data[0])
{ *p++ = IE_USER_USER; /* UUS info element */
*p++ = strlen(pc->prot.dss1.uus1_data) + 1;
*p++ = 0x04; /* IA5 chars */
strcpy(p, pc->prot.dss1.uus1_data);
p += strlen(pc->prot.dss1.uus1_data);
pc->prot.dss1.uus1_data[0] = '\0';
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 11);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
L3AddTimer(&pc->timer, T305, CC_T305);
}
static void
l3dss1_setup_rsp(struct l3_process *pc, u_char pr,
void *arg)
{
if (!pc->para.bchannel)
{ if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "D-chan connect for waiting call");
l3dss1_disconnect_req(pc, pr, arg);
return;
}
newl3state(pc, 8);
l3dss1_message(pc, MT_CONNECT);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T313, CC_T313);
}
static void
l3dss1_connect_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_CONNECT_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
newl3state(pc, 10);
L3DelTimer(&pc->timer);
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_SETUP_COMPL | INDICATION, pc);
}
static void
l3dss1_reject_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[16];
u_char *p = tmp;
int l;
u_char cause = 21;
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
MsgHead(p, pc->callref, MT_RELEASE_COMPLETE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
static void
l3dss1_release(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
u_char *p;
int ret, cause = 0;
StopAllL3Timer(pc);
if ((ret = l3dss1_get_cause(pc, skb)) > 0) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "REL get_cause ret(%d)", ret);
} else if (ret < 0)
pc->para.cause = NO_CAUSE;
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0))) {
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
}
if ((ret < 0) && (pc->state != 11))
cause = 96;
else if (ret > 0)
cause = 100;
ret = check_infoelements(pc, skb, ie_RELEASE);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if ((ERR_IE_UNRECOGNIZED == ret) && (!cause))
cause = 99;
if (cause)
l3dss1_message_cause(pc, MT_RELEASE_COMPLETE, cause);
else
l3dss1_message(pc, MT_RELEASE_COMPLETE);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
static void
l3dss1_alert_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 7);
if (!pc->prot.dss1.uus1_data[0])
l3dss1_message(pc, MT_ALERTING);
else
l3dss1_msg_with_uus(pc, MT_ALERTING);
}
static void
l3dss1_proceed_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 9);
l3dss1_message(pc, MT_CALL_PROCEEDING);
pc->st->l3.l3l4(pc->st, CC_PROCEED_SEND | INDICATION, pc);
}
static void
l3dss1_setup_ack_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 25);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T302, CC_T302);
l3dss1_message(pc, MT_SETUP_ACKNOWLEDGE);
}
/********************************************/
/* deliver a incoming display message to HL */
/********************************************/
static void
l3dss1_deliver_display(struct l3_process *pc, int pr, u_char *infp)
{ u_char len;
isdn_ctrl ic;
struct IsdnCardState *cs;
char *p;
if (*infp++ != IE_DISPLAY) return;
if ((len = *infp++) > 80) return; /* total length <= 82 */
if (!pc->chan) return;
p = ic.parm.display;
while (len--)
*p++ = *infp++;
*p = '\0';
ic.command = ISDN_STAT_DISPLAY;
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.arg = pc->chan->chan;
cs->iif.statcallb(&ic);
} /* l3dss1_deliver_display */
static void
l3dss1_progress(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int err = 0;
u_char *p;
if ((p = findie(skb->data, skb->len, IE_PROGRESS, 0))) {
if (p[1] != 2) {
err = 1;
pc->para.cause = 100;
} else if (!(p[2] & 0x70)) {
switch (p[2]) {
case 0x80:
case 0x81:
case 0x82:
case 0x84:
case 0x85:
case 0x87:
case 0x8a:
switch (p[3]) {
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x88:
break;
default:
err = 2;
pc->para.cause = 100;
break;
}
break;
default:
err = 3;
pc->para.cause = 100;
break;
}
}
} else {
pc->para.cause = 96;
err = 4;
}
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "progress error %d", err);
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_PROGRESS);
if (err)
l3dss1_std_ie_err(pc, err);
if (ERR_IE_COMPREHENSION != err)
pc->st->l3.l3l4(pc->st, CC_PROGRESS | INDICATION, pc);
}
static void
l3dss1_notify(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int err = 0;
u_char *p;
if ((p = findie(skb->data, skb->len, IE_NOTIFY, 0))) {
if (p[1] != 1) {
err = 1;
pc->para.cause = 100;
} else {
switch (p[2]) {
case 0x80:
case 0x81:
case 0x82:
break;
default:
pc->para.cause = 100;
err = 2;
break;
}
}
} else {
pc->para.cause = 96;
err = 3;
}
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "notify error %d", err);
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_NOTIFY);
if (err)
l3dss1_std_ie_err(pc, err);
if (ERR_IE_COMPREHENSION != err)
pc->st->l3.l3l4(pc->st, CC_NOTIFY | INDICATION, pc);
}
static void
l3dss1_status_enq(struct l3_process *pc, u_char pr, void *arg)
{
int ret;
struct sk_buff *skb = arg;
ret = check_infoelements(pc, skb, ie_STATUS_ENQUIRY);
l3dss1_std_ie_err(pc, ret);
pc->para.cause = 30; /* response to STATUS_ENQUIRY */
l3dss1_status_send(pc, pr, NULL);
}
static void
l3dss1_information(struct l3_process *pc, u_char pr, void *arg)
{
int ret;
struct sk_buff *skb = arg;
u_char *p;
char tmp[32];
ret = check_infoelements(pc, skb, ie_INFORMATION);
if (ret)
l3dss1_std_ie_err(pc, ret);
if (pc->state == 25) { /* overlap receiving */
L3DelTimer(&pc->timer);
p = skb->data;
if ((p = findie(p, skb->len, 0x70, 0))) {
iecpy(tmp, p, 1);
strcat(pc->para.setup.eazmsn, tmp);
pc->st->l3.l3l4(pc->st, CC_MORE_INFO | INDICATION, pc);
}
L3AddTimer(&pc->timer, T302, CC_T302);
}
}
/******************************/
/* handle deflection requests */
/******************************/
static void l3dss1_redir_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[128];
u_char *p = tmp;
u_char *subp;
u_char len_phone = 0;
u_char len_sub = 0;
int l;
strcpy(pc->prot.dss1.uus1_data, pc->chan->setup.eazmsn); /* copy uus element if available */
if (!pc->chan->setup.phone[0])
{ pc->para.cause = -1;
l3dss1_disconnect_req(pc, pr, arg); /* disconnect immediately */
return;
} /* only uus */
if (pc->prot.dss1.invoke_id)
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
if (!(pc->prot.dss1.invoke_id = new_invoke_id(pc->st)))
return;
MsgHead(p, pc->callref, MT_FACILITY);
for (subp = pc->chan->setup.phone; (*subp) && (*subp != '.'); subp++) len_phone++; /* len of phone number */
if (*subp++ == '.') len_sub = strlen(subp) + 2; /* length including info subaddress element */
*p++ = 0x1c; /* Facility info element */
*p++ = len_phone + len_sub + 2 + 2 + 8 + 3 + 3; /* length of element */
*p++ = 0x91; /* remote operations protocol */
*p++ = 0xa1; /* invoke component */
*p++ = len_phone + len_sub + 2 + 2 + 8 + 3; /* length of data */
*p++ = 0x02; /* invoke id tag, integer */
*p++ = 0x01; /* length */
*p++ = pc->prot.dss1.invoke_id; /* invoke id */
*p++ = 0x02; /* operation value tag, integer */
*p++ = 0x01; /* length */
*p++ = 0x0D; /* Call Deflect */
*p++ = 0x30; /* sequence phone number */
*p++ = len_phone + 2 + 2 + 3 + len_sub; /* length */
*p++ = 0x30; /* Deflected to UserNumber */
*p++ = len_phone + 2 + len_sub; /* length */
*p++ = 0x80; /* NumberDigits */
*p++ = len_phone; /* length */
for (l = 0; l < len_phone; l++)
*p++ = pc->chan->setup.phone[l];
if (len_sub)
{ *p++ = 0x04; /* called party subaddress */
*p++ = len_sub - 2;
while (*subp) *p++ = *subp++;
}
*p++ = 0x01; /* screening identifier */
*p++ = 0x01;
*p++ = pc->chan->setup.screen;
l = p - tmp;
if (!(skb = l3_alloc_skb(l))) return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
} /* l3dss1_redir_req */
/********************************************/
/* handle deflection request in early state */
/********************************************/
static void l3dss1_redir_req_early(struct l3_process *pc, u_char pr, void *arg)
{
l3dss1_proceed_req(pc, pr, arg);
l3dss1_redir_req(pc, pr, arg);
} /* l3dss1_redir_req_early */
/***********************************************/
/* handle special commands for this protocol. */
/* Examples are call independent services like */
/* remote operations with dummy callref. */
/***********************************************/
static int l3dss1_cmd_global(struct PStack *st, isdn_ctrl *ic)
{ u_char id;
u_char temp[265];
u_char *p = temp;
int i, l, proc_len;
struct sk_buff *skb;
struct l3_process *pc = NULL;
switch (ic->arg)
{ case DSS1_CMD_INVOKE:
if (ic->parm.dss1_io.datalen < 0) return (-2); /* invalid parameter */
for (proc_len = 1, i = ic->parm.dss1_io.proc >> 8; i; i++)
i = i >> 8; /* add one byte */
l = ic->parm.dss1_io.datalen + proc_len + 8; /* length excluding ie header */
if (l > 255)
return (-2); /* too long */
if (!(id = new_invoke_id(st)))
return (0); /* first get a invoke id -> return if no available */
i = -1;
MsgHead(p, i, MT_FACILITY); /* build message head */
*p++ = 0x1C; /* Facility IE */
*p++ = l; /* length of ie */
*p++ = 0x91; /* remote operations */
*p++ = 0xA1; /* invoke */
*p++ = l - 3; /* length of invoke */
*p++ = 0x02; /* invoke id tag */
*p++ = 0x01; /* length is 1 */
*p++ = id; /* invoke id */
*p++ = 0x02; /* operation */
*p++ = proc_len; /* length of operation */
for (i = proc_len; i; i--)
*p++ = (ic->parm.dss1_io.proc >> (i - 1)) & 0xFF;
memcpy(p, ic->parm.dss1_io.data, ic->parm.dss1_io.datalen); /* copy data */
l = (p - temp) + ic->parm.dss1_io.datalen; /* total length */
if (ic->parm.dss1_io.timeout > 0)
if (!(pc = dss1_new_l3_process(st, -1)))
{ free_invoke_id(st, id);
return (-2);
}
pc->prot.dss1.ll_id = ic->parm.dss1_io.ll_id; /* remember id */
pc->prot.dss1.proc = ic->parm.dss1_io.proc; /* and procedure */
if (!(skb = l3_alloc_skb(l)))
{ free_invoke_id(st, id);
if (pc) dss1_release_l3_process(pc);
return (-2);
}
memcpy(skb_put(skb, l), temp, l);
if (pc)
{ pc->prot.dss1.invoke_id = id; /* remember id */
L3AddTimer(&pc->timer, ic->parm.dss1_io.timeout, CC_TDSS1_IO | REQUEST);
}
l3_msg(st, DL_DATA | REQUEST, skb);
ic->parm.dss1_io.hl_id = id; /* return id */
return (0);
case DSS1_CMD_INVOKE_ABORT:
if ((pc = l3dss1_search_dummy_proc(st, ic->parm.dss1_io.hl_id)))
{ L3DelTimer(&pc->timer); /* remove timer */
dss1_release_l3_process(pc);
return (0);
}
else
{ l3_debug(st, "l3dss1_cmd_global abort unknown id");
return (-2);
}
break;
default:
l3_debug(st, "l3dss1_cmd_global unknown cmd 0x%lx", ic->arg);
return (-1);
} /* switch ic-> arg */
return (-1);
} /* l3dss1_cmd_global */
static void
l3dss1_io_timer(struct l3_process *pc)
{ isdn_ctrl ic;
struct IsdnCardState *cs = pc->st->l1.hardware;
L3DelTimer(&pc->timer); /* remove timer */
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_ERR;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = -1;
ic.parm.dss1_io.datalen = 0;
ic.parm.dss1_io.data = NULL;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
} /* l3dss1_io_timer */
static void
l3dss1_release_ind(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
struct sk_buff *skb = arg;
int callState = 0;
p = skb->data;
if ((p = findie(p, skb->len, IE_CALL_STATE, 0))) {
p++;
if (1 == *p++)
callState = *p;
}
if (callState == 0) {
/* ETS 300-104 7.6.1, 8.6.1, 10.6.1... and 16.1
* set down layer 3 without sending any message
*/
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
} else {
pc->st->l3.l3l4(pc->st, CC_IGNORE | INDICATION, pc);
}
}
static void
l3dss1_dummy(struct l3_process *pc, u_char pr, void *arg)
{
}
static void
l3dss1_t302(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 28; /* invalid number */
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t303(struct l3_process *pc, u_char pr, void *arg)
{
if (pc->N303 > 0) {
pc->N303--;
L3DelTimer(&pc->timer);
l3dss1_setup_req(pc, pr, arg);
} else {
L3DelTimer(&pc->timer);
l3dss1_message_cause(pc, MT_RELEASE_COMPLETE, 102);
pc->st->l3.l3l4(pc->st, CC_NOSETUP_RSP, pc);
dss1_release_l3_process(pc);
}
}
static void
l3dss1_t304(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t305(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
u_char cause = 16;
L3DelTimer(&pc->timer);
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
MsgHead(p, pc->callref, MT_RELEASE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 19);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_t310(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t313(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_CONNECT_ERR, pc);
}
static void
l3dss1_t308_1(struct l3_process *pc, u_char pr, void *arg)
{
newl3state(pc, 19);
L3DelTimer(&pc->timer);
l3dss1_message(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_2);
}
static void
l3dss1_t308_2(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RELEASE_ERR, pc);
dss1_release_l3_process(pc);
}
static void
l3dss1_t318(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 102; /* Timer expiry */
pc->para.loc = 0; /* local */
pc->st->l3.l3l4(pc->st, CC_RESUME_ERR, pc);
newl3state(pc, 19);
l3dss1_message(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_t319(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 102; /* Timer expiry */
pc->para.loc = 0; /* local */
pc->st->l3.l3l4(pc->st, CC_SUSPEND_ERR, pc);
newl3state(pc, 10);
}
static void
l3dss1_restart(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
dss1_release_l3_process(pc);
}
static void
l3dss1_status(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
struct sk_buff *skb = arg;
int ret;
u_char cause = 0, callState = 0;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "STATUS get_cause ret(%d)", ret);
if (ret < 0)
cause = 96;
else if (ret > 0)
cause = 100;
}
if ((p = findie(skb->data, skb->len, IE_CALL_STATE, 0))) {
p++;
if (1 == *p++) {
callState = *p;
if (!ie_in_set(pc, *p, l3_valid_states))
cause = 100;
} else
cause = 100;
} else
cause = 96;
if (!cause) { /* no error before */
ret = check_infoelements(pc, skb, ie_STATUS);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if (ERR_IE_UNRECOGNIZED == ret)
cause = 99;
}
if (cause) {
u_char tmp;
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "STATUS error(%d/%d)", ret, cause);
tmp = pc->para.cause;
pc->para.cause = cause;
l3dss1_status_send(pc, 0, NULL);
if (cause == 99)
pc->para.cause = tmp;
else
return;
}
cause = pc->para.cause;
if (((cause & 0x7f) == 111) && (callState == 0)) {
/* ETS 300-104 7.6.1, 8.6.1, 10.6.1...
* if received MT_STATUS with cause == 111 and call
* state == 0, then we must set down layer 3
*/
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
}
static void
l3dss1_facility(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_FACILITY);
l3dss1_std_ie_err(pc, ret);
{
u_char *p;
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0)))
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
}
}
static void
l3dss1_suspend_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[32];
u_char *p = tmp;
u_char i, l;
u_char *msg = pc->chan->setup.phone;
MsgHead(p, pc->callref, MT_SUSPEND);
l = *msg++;
if (l && (l <= 10)) { /* Max length 10 octets */
*p++ = IE_CALL_ID;
*p++ = l;
for (i = 0; i < l; i++)
*p++ = *msg++;
} else if (l) {
l3_debug(pc->st, "SUS wrong CALL_ID len %d", l);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
newl3state(pc, 15);
L3AddTimer(&pc->timer, T319, CC_T319);
}
static void
l3dss1_suspend_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
L3DelTimer(&pc->timer);
newl3state(pc, 0);
pc->para.cause = NO_CAUSE;
pc->st->l3.l3l4(pc->st, CC_SUSPEND | CONFIRM, pc);
/* We don't handle suspend_ack for IE errors now */
if ((ret = check_infoelements(pc, skb, ie_SUSPEND_ACKNOWLEDGE)))
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "SUSPACK check ie(%d)", ret);
dss1_release_l3_process(pc);
}
static void
l3dss1_suspend_rej(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "SUSP_REJ get_cause ret(%d)", ret);
if (ret < 0)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_SUSPEND_REJECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_SUSPEND_ERR, pc);
newl3state(pc, 10);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
}
static void
l3dss1_resume_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[32];
u_char *p = tmp;
u_char i, l;
u_char *msg = pc->para.setup.phone;
MsgHead(p, pc->callref, MT_RESUME);
l = *msg++;
if (l && (l <= 10)) { /* Max length 10 octets */
*p++ = IE_CALL_ID;
*p++ = l;
for (i = 0; i < l; i++)
*p++ = *msg++;
} else if (l) {
l3_debug(pc->st, "RES wrong CALL_ID len %d", l);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
newl3state(pc, 17);
L3AddTimer(&pc->timer, T318, CC_T318);
}
static void
l3dss1_resume_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) > 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "resume ack with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else if (1 == pc->state) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "resume ack without chid (ret %d)", id);
pc->para.cause = 96;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_RESUME_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RESUME | CONFIRM, pc);
newl3state(pc, 10);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
}
static void
l3dss1_resume_rej(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "RES_REJ get_cause ret(%d)", ret);
if (ret < 0)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_RESUME_REJECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RESUME_ERR, pc);
newl3state(pc, 0);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
dss1_release_l3_process(pc);
}
static void
l3dss1_global_restart(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[32];
u_char *p;
u_char ri, ch = 0, chan = 0;
int l;
struct sk_buff *skb = arg;
struct l3_process *up;
newl3state(pc, 2);
L3DelTimer(&pc->timer);
p = skb->data;
if ((p = findie(p, skb->len, IE_RESTART_IND, 0))) {
ri = p[2];
l3_debug(pc->st, "Restart %x", ri);
} else {
l3_debug(pc->st, "Restart without restart IE");
ri = 0x86;
}
p = skb->data;
if ((p = findie(p, skb->len, IE_CHANNEL_ID, 0))) {
chan = p[2] & 3;
ch = p[2];
if (pc->st->l3.debug)
l3_debug(pc->st, "Restart for channel %d", chan);
}
newl3state(pc, 2);
up = pc->st->l3.proc;
while (up) {
if ((ri & 7) == 7)
up->st->lli.l4l3(up->st, CC_RESTART | REQUEST, up);
else if (up->para.bchannel == chan)
up->st->lli.l4l3(up->st, CC_RESTART | REQUEST, up);
up = up->next;
}
p = tmp;
MsgHead(p, pc->callref, MT_RESTART_ACKNOWLEDGE);
if (chan) {
*p++ = IE_CHANNEL_ID;
*p++ = 1;
*p++ = ch | 0x80;
}
*p++ = 0x79; /* RESTART Ind */
*p++ = 1;
*p++ = ri;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 0);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_dl_reset(struct l3_process *pc, u_char pr, void *arg)
{
pc->para.cause = 0x29; /* Temporary failure */
pc->para.loc = 0;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_dl_release(struct l3_process *pc, u_char pr, void *arg)
{
newl3state(pc, 0);
pc->para.cause = 0x1b; /* Destination out of order */
pc->para.loc = 0;
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
release_l3_process(pc);
}
static void
l3dss1_dl_reestablish(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T309, CC_T309);
l3_msg(pc->st, DL_ESTABLISH | REQUEST, NULL);
}
static void
l3dss1_dl_reest_status(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 0x1F; /* normal, unspecified */
l3dss1_status_send(pc, 0, NULL);
}
/* *INDENT-OFF* */
static struct stateentry downstatelist[] =
{
{SBIT(0),
CC_SETUP | REQUEST, l3dss1_setup_req},
{SBIT(0),
CC_RESUME | REQUEST, l3dss1_resume_req},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(6) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(25),
CC_DISCONNECT | REQUEST, l3dss1_disconnect_req},
{SBIT(12),
CC_RELEASE | REQUEST, l3dss1_release_req},
{ALL_STATES,
CC_RESTART | REQUEST, l3dss1_restart},
{SBIT(6) | SBIT(25),
CC_IGNORE | REQUEST, l3dss1_reset},
{SBIT(6) | SBIT(25),
CC_REJECT | REQUEST, l3dss1_reject_req},
{SBIT(6) | SBIT(25),
CC_PROCEED_SEND | REQUEST, l3dss1_proceed_req},
{SBIT(6),
CC_MORE_INFO | REQUEST, l3dss1_setup_ack_req},
{SBIT(25),
CC_MORE_INFO | REQUEST, l3dss1_dummy},
{SBIT(6) | SBIT(9) | SBIT(25),
CC_ALERTING | REQUEST, l3dss1_alert_req},
{SBIT(6) | SBIT(7) | SBIT(9) | SBIT(25),
CC_SETUP | RESPONSE, l3dss1_setup_rsp},
{SBIT(10),
CC_SUSPEND | REQUEST, l3dss1_suspend_req},
{SBIT(7) | SBIT(9) | SBIT(25),
CC_REDIR | REQUEST, l3dss1_redir_req},
{SBIT(6),
CC_REDIR | REQUEST, l3dss1_redir_req_early},
{SBIT(9) | SBIT(25),
CC_DISCONNECT | REQUEST, l3dss1_disconnect_req},
{SBIT(25),
CC_T302, l3dss1_t302},
{SBIT(1),
CC_T303, l3dss1_t303},
{SBIT(2),
CC_T304, l3dss1_t304},
{SBIT(3),
CC_T310, l3dss1_t310},
{SBIT(8),
CC_T313, l3dss1_t313},
{SBIT(11),
CC_T305, l3dss1_t305},
{SBIT(15),
CC_T319, l3dss1_t319},
{SBIT(17),
CC_T318, l3dss1_t318},
{SBIT(19),
CC_T308_1, l3dss1_t308_1},
{SBIT(19),
CC_T308_2, l3dss1_t308_2},
{SBIT(10),
CC_T309, l3dss1_dl_release},
};
static struct stateentry datastatelist[] =
{
{ALL_STATES,
MT_STATUS_ENQUIRY, l3dss1_status_enq},
{ALL_STATES,
MT_FACILITY, l3dss1_facility},
{SBIT(19),
MT_STATUS, l3dss1_release_ind},
{ALL_STATES,
MT_STATUS, l3dss1_status},
{SBIT(0),
MT_SETUP, l3dss1_setup},
{SBIT(6) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(12) |
SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_SETUP, l3dss1_dummy},
{SBIT(1) | SBIT(2),
MT_CALL_PROCEEDING, l3dss1_call_proc},
{SBIT(1),
MT_SETUP_ACKNOWLEDGE, l3dss1_setup_ack},
{SBIT(2) | SBIT(3),
MT_ALERTING, l3dss1_alerting},
{SBIT(2) | SBIT(3),
MT_PROGRESS, l3dss1_progress},
{SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) |
SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_INFORMATION, l3dss1_information},
{SBIT(10) | SBIT(11) | SBIT(15),
MT_NOTIFY, l3dss1_notify},
{SBIT(0) | SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(10) |
SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_RELEASE_COMPLETE, l3dss1_release_cmpl},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(25),
MT_RELEASE, l3dss1_release},
{SBIT(19), MT_RELEASE, l3dss1_release_ind},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(15) | SBIT(17) | SBIT(25),
MT_DISCONNECT, l3dss1_disconnect},
{SBIT(19),
MT_DISCONNECT, l3dss1_dummy},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4),
MT_CONNECT, l3dss1_connect},
{SBIT(8),
MT_CONNECT_ACKNOWLEDGE, l3dss1_connect_ack},
{SBIT(15),
MT_SUSPEND_ACKNOWLEDGE, l3dss1_suspend_ack},
{SBIT(15),
MT_SUSPEND_REJECT, l3dss1_suspend_rej},
{SBIT(17),
MT_RESUME_ACKNOWLEDGE, l3dss1_resume_ack},
{SBIT(17),
MT_RESUME_REJECT, l3dss1_resume_rej},
};
static struct stateentry globalmes_list[] =
{
{ALL_STATES,
MT_STATUS, l3dss1_status},
{SBIT(0),
MT_RESTART, l3dss1_global_restart},
/* {SBIT(1),
MT_RESTART_ACKNOWLEDGE, l3dss1_restart_ack},
*/
};
static struct stateentry manstatelist[] =
{
{SBIT(2),
DL_ESTABLISH | INDICATION, l3dss1_dl_reset},
{SBIT(10),
DL_ESTABLISH | CONFIRM, l3dss1_dl_reest_status},
{SBIT(10),
DL_RELEASE | INDICATION, l3dss1_dl_reestablish},
{ALL_STATES,
DL_RELEASE | INDICATION, l3dss1_dl_release},
};
/* *INDENT-ON* */
static void
global_handler(struct PStack *st, int mt, struct sk_buff *skb)
{
u_char tmp[16];
u_char *p = tmp;
int l;
int i;
struct l3_process *proc = st->l3.global;
proc->callref = skb->data[2]; /* cr flag */
for (i = 0; i < ARRAY_SIZE(globalmes_list); i++)
if ((mt == globalmes_list[i].primitive) &&
((1 << proc->state) & globalmes_list[i].state))
break;
if (i == ARRAY_SIZE(globalmes_list)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global state %d mt %x unhandled",
proc->state, mt);
}
MsgHead(p, proc->callref, MT_STATUS);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = 81 | 0x80; /* invalid cr */
*p++ = 0x14; /* CallState */
*p++ = 0x1;
*p++ = proc->state & 0x3f;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(proc->st, DL_DATA | REQUEST, skb);
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global %d mt %x",
proc->state, mt);
}
globalmes_list[i].rout(proc, mt, skb);
}
}
static void
dss1up(struct PStack *st, int pr, void *arg)
{
int i, mt, cr, callState;
char *ptr;
u_char *p;
struct sk_buff *skb = arg;
struct l3_process *proc;
switch (pr) {
case (DL_DATA | INDICATION):
case (DL_UNIT_DATA | INDICATION):
break;
case (DL_ESTABLISH | CONFIRM):
case (DL_ESTABLISH | INDICATION):
case (DL_RELEASE | INDICATION):
case (DL_RELEASE | CONFIRM):
l3_msg(st, pr, arg);
return;
break;
default:
printk(KERN_ERR "HiSax dss1up unknown pr=%04x\n", pr);
return;
}
if (skb->len < 3) {
l3_debug(st, "dss1up frame too short(%d)", skb->len);
dev_kfree_skb(skb);
return;
}
if (skb->data[0] != PROTO_DIS_EURO) {
if (st->l3.debug & L3_DEB_PROTERR) {
l3_debug(st, "dss1up%sunexpected discriminator %x message len %d",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
skb->data[0], skb->len);
}
dev_kfree_skb(skb);
return;
}
cr = getcallref(skb->data);
if (skb->len < ((skb->data[1] & 0x0f) + 3)) {
l3_debug(st, "dss1up frame too short(%d)", skb->len);
dev_kfree_skb(skb);
return;
}
mt = skb->data[skb->data[1] + 2];
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up cr %d", cr);
if (cr == -2) { /* wrong Callref */
if (st->l3.debug & L3_DEB_WARN)
l3_debug(st, "dss1up wrong Callref");
dev_kfree_skb(skb);
return;
} else if (cr == -1) { /* Dummy Callref */
if (mt == MT_FACILITY)
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0))) {
l3dss1_parse_facility(st, NULL,
(pr == (DL_DATA | INDICATION)) ? -1 : -2, p);
dev_kfree_skb(skb);
return;
}
if (st->l3.debug & L3_DEB_WARN)
l3_debug(st, "dss1up dummy Callref (no facility msg or ie)");
dev_kfree_skb(skb);
return;
} else if ((((skb->data[1] & 0x0f) == 1) && (0 == (cr & 0x7f))) ||
(((skb->data[1] & 0x0f) == 2) && (0 == (cr & 0x7fff)))) { /* Global CallRef */
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up Global CallRef");
global_handler(st, mt, skb);
dev_kfree_skb(skb);
return;
} else if (!(proc = getl3proc(st, cr))) {
/* No transaction process exist, that means no call with
* this callreference is active
*/
if (mt == MT_SETUP) {
/* Setup creates a new transaction process */
if (skb->data[2] & 0x80) {
/* Setup with wrong CREF flag */
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up wrong CRef flag");
dev_kfree_skb(skb);
return;
}
if (!(proc = dss1_new_l3_process(st, cr))) {
/* May be to answer with RELEASE_COMPLETE and
* CAUSE 0x2f "Resource unavailable", but this
* need a new_l3_process too ... arghh
*/
dev_kfree_skb(skb);
return;
}
} else if (mt == MT_STATUS) {
if ((ptr = findie(skb->data, skb->len, IE_CAUSE, 0)) != NULL) {
ptr++;
if (*ptr++ == 2)
ptr++;
}
callState = 0;
if ((ptr = findie(skb->data, skb->len, IE_CALL_STATE, 0)) != NULL) {
ptr++;
if (*ptr++ == 2)
ptr++;
callState = *ptr;
}
/* ETS 300-104 part 2.4.1
* if setup has not been made and a message type
* MT_STATUS is received with call state == 0,
* we must send nothing
*/
if (callState != 0) {
/* ETS 300-104 part 2.4.2
* if setup has not been made and a message type
* MT_STATUS is received with call state != 0,
* we must send MT_RELEASE_COMPLETE cause 101
*/
if ((proc = dss1_new_l3_process(st, cr))) {
proc->para.cause = 101;
l3dss1_msg_without_setup(proc, 0, NULL);
}
}
dev_kfree_skb(skb);
return;
} else if (mt == MT_RELEASE_COMPLETE) {
dev_kfree_skb(skb);
return;
} else {
/* ETS 300-104 part 2
* if setup has not been made and a message type
* (except MT_SETUP and RELEASE_COMPLETE) is received,
* we must send MT_RELEASE_COMPLETE cause 81 */
dev_kfree_skb(skb);
if ((proc = dss1_new_l3_process(st, cr))) {
proc->para.cause = 81;
l3dss1_msg_without_setup(proc, 0, NULL);
}
return;
}
}
if (l3dss1_check_messagetype_validity(proc, mt, skb)) {
dev_kfree_skb(skb);
return;
}
if ((p = findie(skb->data, skb->len, IE_DISPLAY, 0)) != NULL)
l3dss1_deliver_display(proc, pr, p); /* Display IE included */
for (i = 0; i < ARRAY_SIZE(datastatelist); i++)
if ((mt == datastatelist[i].primitive) &&
((1 << proc->state) & datastatelist[i].state))
break;
if (i == ARRAY_SIZE(datastatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %#x unhandled",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
proc->state, mt);
}
if ((MT_RELEASE_COMPLETE != mt) && (MT_RELEASE != mt)) {
proc->para.cause = 101;
l3dss1_status_send(proc, pr, skb);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %x",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
proc->state, mt);
}
datastatelist[i].rout(proc, pr, skb);
}
dev_kfree_skb(skb);
return;
}
static void
dss1down(struct PStack *st, int pr, void *arg)
{
int i, cr;
struct l3_process *proc;
struct Channel *chan;
if ((DL_ESTABLISH | REQUEST) == pr) {
l3_msg(st, pr, NULL);
return;
} else if (((CC_SETUP | REQUEST) == pr) || ((CC_RESUME | REQUEST) == pr)) {
chan = arg;
cr = newcallref();
cr |= 0x80;
if ((proc = dss1_new_l3_process(st, cr))) {
proc->chan = chan;
chan->proc = proc;
memcpy(&proc->para.setup, &chan->setup, sizeof(setup_parm));
proc->callref = cr;
}
} else {
proc = arg;
}
if (!proc) {
printk(KERN_ERR "HiSax dss1down without proc pr=%04x\n", pr);
return;
}
if (pr == (CC_TDSS1_IO | REQUEST)) {
l3dss1_io_timer(proc); /* timer expires */
return;
}
for (i = 0; i < ARRAY_SIZE(downstatelist); i++)
if ((pr == downstatelist[i].primitive) &&
((1 << proc->state) & downstatelist[i].state))
break;
if (i == ARRAY_SIZE(downstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x unhandled",
proc->state, pr);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x",
proc->state, pr);
}
downstatelist[i].rout(proc, pr, arg);
}
}
static void
dss1man(struct PStack *st, int pr, void *arg)
{
int i;
struct l3_process *proc = arg;
if (!proc) {
printk(KERN_ERR "HiSax dss1man without proc pr=%04x\n", pr);
return;
}
for (i = 0; i < ARRAY_SIZE(manstatelist); i++)
if ((pr == manstatelist[i].primitive) &&
((1 << proc->state) & manstatelist[i].state))
break;
if (i == ARRAY_SIZE(manstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x unhandled",
proc->callref & 0x7f, proc->state, pr);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x",
proc->callref & 0x7f, proc->state, pr);
}
manstatelist[i].rout(proc, pr, arg);
}
}
void
setstack_dss1(struct PStack *st)
{
char tmp[64];
int i;
st->lli.l4l3 = dss1down;
st->lli.l4l3_proto = l3dss1_cmd_global;
st->l2.l2l3 = dss1up;
st->l3.l3ml3 = dss1man;
st->l3.N303 = 1;
st->prot.dss1.last_invoke_id = 0;
st->prot.dss1.invoke_used[0] = 1; /* Bit 0 must always be set to 1 */
i = 1;
while (i < 32)
st->prot.dss1.invoke_used[i++] = 0;
if (!(st->l3.global = kmalloc(sizeof(struct l3_process), GFP_ATOMIC))) {
printk(KERN_ERR "HiSax can't get memory for dss1 global CR\n");
} else {
st->l3.global->state = 0;
st->l3.global->callref = 0;
st->l3.global->next = NULL;
st->l3.global->debug = L3_DEB_WARN;
st->l3.global->st = st;
st->l3.global->N303 = 1;
st->l3.global->prot.dss1.invoke_id = 0;
L3InitTimer(st->l3.global, &st->l3.global->timer);
}
strcpy(tmp, dss1_revision);
printk(KERN_INFO "HiSax: DSS1 Rev. %s\n", HiSax_getrev(tmp));
}
| gpl-2.0 |
Freack-v/android_kernel_eagle | drivers/isdn/hisax/l3dss1.c | 9553 | 78840 | /* $Id: l3dss1.c,v 2.32.2.3 2004/01/13 14:31:25 keil Exp $
*
* EURO/DSS1 D-channel protocol
*
* German 1TR6 D-channel protocol
*
* Author Karsten Keil
* based on the teles driver from Jan den Ouden
* Copyright by Karsten Keil <keil@isdn4linux.de>
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
* For changes and modifications please read
* Documentation/isdn/HiSax.cert
*
* Thanks to Jan den Ouden
* Fritz Elfert
*
*/
#include "hisax.h"
#include "isdnl3.h"
#include "l3dss1.h"
#include <linux/ctype.h>
#include <linux/slab.h>
extern char *HiSax_getrev(const char *revision);
static const char *dss1_revision = "$Revision: 2.32.2.3 $";
#define EXT_BEARER_CAPS 1
#define MsgHead(ptr, cref, mty) \
*ptr++ = 0x8; \
if (cref == -1) { \
*ptr++ = 0x0; \
} else { \
*ptr++ = 0x1; \
*ptr++ = cref^0x80; \
} \
*ptr++ = mty
/**********************************************/
/* get a new invoke id for remote operations. */
/* Only a return value != 0 is valid */
/**********************************************/
static unsigned char new_invoke_id(struct PStack *p)
{
unsigned char retval;
int i;
i = 32; /* maximum search depth */
retval = p->prot.dss1.last_invoke_id + 1; /* try new id */
while ((i) && (p->prot.dss1.invoke_used[retval >> 3] == 0xFF)) {
p->prot.dss1.last_invoke_id = (retval & 0xF8) + 8;
i--;
}
if (i) {
while (p->prot.dss1.invoke_used[retval >> 3] & (1 << (retval & 7)))
retval++;
} else
retval = 0;
p->prot.dss1.last_invoke_id = retval;
p->prot.dss1.invoke_used[retval >> 3] |= (1 << (retval & 7));
return (retval);
} /* new_invoke_id */
/*************************/
/* free a used invoke id */
/*************************/
static void free_invoke_id(struct PStack *p, unsigned char id)
{
if (!id) return; /* 0 = invalid value */
p->prot.dss1.invoke_used[id >> 3] &= ~(1 << (id & 7));
} /* free_invoke_id */
/**********************************************************/
/* create a new l3 process and fill in dss1 specific data */
/**********************************************************/
static struct l3_process
*dss1_new_l3_process(struct PStack *st, int cr)
{ struct l3_process *proc;
if (!(proc = new_l3_process(st, cr)))
return (NULL);
proc->prot.dss1.invoke_id = 0;
proc->prot.dss1.remote_operation = 0;
proc->prot.dss1.uus1_data[0] = '\0';
return (proc);
} /* dss1_new_l3_process */
/************************************************/
/* free a l3 process and all dss1 specific data */
/************************************************/
static void
dss1_release_l3_process(struct l3_process *p)
{
free_invoke_id(p->st, p->prot.dss1.invoke_id);
release_l3_process(p);
} /* dss1_release_l3_process */
/********************************************************/
/* search a process with invoke id id and dummy callref */
/********************************************************/
static struct l3_process *
l3dss1_search_dummy_proc(struct PStack *st, int id)
{ struct l3_process *pc = st->l3.proc; /* start of processes */
if (!id) return (NULL);
while (pc)
{ if ((pc->callref == -1) && (pc->prot.dss1.invoke_id == id))
return (pc);
pc = pc->next;
}
return (NULL);
} /* l3dss1_search_dummy_proc */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a return result is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_return_result(struct PStack *st, int id, u_char *p, u_char nlen)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
struct l3_process *pc = NULL;
if ((pc = l3dss1_search_dummy_proc(st, id)))
{ L3DelTimer(&pc->timer); /* remove timer */
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_RES;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = 0;
ic.parm.dss1_io.datalen = nlen;
ic.parm.dss1_io.data = p;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
}
else
l3_debug(st, "dummy return result id=0x%x result len=%d", id, nlen);
} /* l3dss1_dummy_return_result */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a return error is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_error_return(struct PStack *st, int id, ulong error)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
struct l3_process *pc = NULL;
if ((pc = l3dss1_search_dummy_proc(st, id)))
{ L3DelTimer(&pc->timer); /* remove timer */
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_ERR;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = error;
ic.parm.dss1_io.datalen = 0;
ic.parm.dss1_io.data = NULL;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
}
else
l3_debug(st, "dummy return error id=0x%x error=0x%lx", id, error);
} /* l3dss1_error_return */
/*******************************************************************/
/* called when a facility message with a dummy callref is received */
/* and a invoke is delivered. id specifies the invoke id. */
/*******************************************************************/
static void
l3dss1_dummy_invoke(struct PStack *st, int cr, int id,
int ident, u_char *p, u_char nlen)
{ isdn_ctrl ic;
struct IsdnCardState *cs;
l3_debug(st, "dummy invoke %s id=0x%x ident=0x%x datalen=%d",
(cr == -1) ? "local" : "broadcast", id, ident, nlen);
if (cr >= -1) return; /* ignore local data */
cs = st->l1.hardware;
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_BRD;
ic.parm.dss1_io.hl_id = id;
ic.parm.dss1_io.ll_id = 0;
ic.parm.dss1_io.proc = ident;
ic.parm.dss1_io.timeout = 0;
ic.parm.dss1_io.datalen = nlen;
ic.parm.dss1_io.data = p;
cs->iif.statcallb(&ic);
} /* l3dss1_dummy_invoke */
static void
l3dss1_parse_facility(struct PStack *st, struct l3_process *pc,
int cr, u_char *p)
{
int qd_len = 0;
unsigned char nlen = 0, ilen, cp_tag;
int ident, id;
ulong err_ret;
if (pc)
st = pc->st; /* valid Stack */
else
if ((!st) || (cr >= 0)) return; /* neither pc nor st specified */
p++;
qd_len = *p++;
if (qd_len == 0) {
l3_debug(st, "qd_len == 0");
return;
}
if ((*p & 0x1F) != 0x11) { /* Service discriminator, supplementary service */
l3_debug(st, "supplementary service != 0x11");
return;
}
while (qd_len > 0 && !(*p & 0x80)) { /* extension ? */
p++;
qd_len--;
}
if (qd_len < 2) {
l3_debug(st, "qd_len < 2");
return;
}
p++;
qd_len--;
if ((*p & 0xE0) != 0xA0) { /* class and form */
l3_debug(st, "class and form != 0xA0");
return;
}
cp_tag = *p & 0x1F; /* remember tag value */
p++;
qd_len--;
if (qd_len < 1)
{ l3_debug(st, "qd_len < 1");
return;
}
if (*p & 0x80)
{ /* length format indefinite or limited */
nlen = *p++ & 0x7F; /* number of len bytes or indefinite */
if ((qd_len-- < ((!nlen) ? 3 : (1 + nlen))) ||
(nlen > 1))
{ l3_debug(st, "length format error or not implemented");
return;
}
if (nlen == 1)
{ nlen = *p++; /* complete length */
qd_len--;
}
else
{ qd_len -= 2; /* trailing null bytes */
if ((*(p + qd_len)) || (*(p + qd_len + 1)))
{ l3_debug(st, "length format indefinite error");
return;
}
nlen = qd_len;
}
}
else
{ nlen = *p++;
qd_len--;
}
if (qd_len < nlen)
{ l3_debug(st, "qd_len < nlen");
return;
}
qd_len -= nlen;
if (nlen < 2)
{ l3_debug(st, "nlen < 2");
return;
}
if (*p != 0x02)
{ /* invoke identifier tag */
l3_debug(st, "invoke identifier tag !=0x02");
return;
}
p++;
nlen--;
if (*p & 0x80)
{ /* length format */
l3_debug(st, "invoke id length format 2");
return;
}
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0)
{ l3_debug(st, "ilen > nlen || ilen == 0");
return;
}
nlen -= ilen;
id = 0;
while (ilen > 0)
{ id = (id << 8) | (*p++ & 0xFF); /* invoke identifier */
ilen--;
}
switch (cp_tag) { /* component tag */
case 1: /* invoke */
if (nlen < 2) {
l3_debug(st, "nlen < 2 22");
return;
}
if (*p != 0x02) { /* operation value */
l3_debug(st, "operation value !=0x02");
return;
}
p++;
nlen--;
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0) {
l3_debug(st, "ilen > nlen || ilen == 0 22");
return;
}
nlen -= ilen;
ident = 0;
while (ilen > 0) {
ident = (ident << 8) | (*p++ & 0xFF);
ilen--;
}
if (!pc)
{ l3dss1_dummy_invoke(st, cr, id, ident, p, nlen);
return;
}
#ifdef CONFIG_DE_AOC
{
#define FOO1(s, a, b) \
while (nlen > 1) { \
int ilen = p[1]; \
if (nlen < ilen + 2) { \
l3_debug(st, "FOO1 nlen < ilen+2"); \
return; \
} \
nlen -= ilen + 2; \
if ((*p & 0xFF) == (a)) { \
int nlen = ilen; \
p += 2; \
b; \
} else { \
p += ilen + 2; \
} \
}
switch (ident) {
case 0x22: /* during */
FOO1("1A", 0x30, FOO1("1C", 0xA1, FOO1("1D", 0x30, FOO1("1E", 0x02, ( {
ident = 0;
nlen = (nlen) ? nlen : 0; /* Make gcc happy */
while (ilen > 0) {
ident = (ident << 8) | *p++;
ilen--;
}
if (ident > pc->para.chargeinfo) {
pc->para.chargeinfo = ident;
st->l3.l3l4(st, CC_CHARGE | INDICATION, pc);
}
if (st->l3.debug & L3_DEB_CHARGE) {
if (*(p + 2) == 0) {
l3_debug(st, "charging info during %d", pc->para.chargeinfo);
}
else {
l3_debug(st, "charging info final %d", pc->para.chargeinfo);
}
}
}
)))))
break;
case 0x24: /* final */
FOO1("2A", 0x30, FOO1("2B", 0x30, FOO1("2C", 0xA1, FOO1("2D", 0x30, FOO1("2E", 0x02, ( {
ident = 0;
nlen = (nlen) ? nlen : 0; /* Make gcc happy */
while (ilen > 0) {
ident = (ident << 8) | *p++;
ilen--;
}
if (ident > pc->para.chargeinfo) {
pc->para.chargeinfo = ident;
st->l3.l3l4(st, CC_CHARGE | INDICATION, pc);
}
if (st->l3.debug & L3_DEB_CHARGE) {
l3_debug(st, "charging info final %d", pc->para.chargeinfo);
}
}
))))))
break;
default:
l3_debug(st, "invoke break invalid ident %02x", ident);
break;
}
#undef FOO1
}
#else /* not CONFIG_DE_AOC */
l3_debug(st, "invoke break");
#endif /* not CONFIG_DE_AOC */
break;
case 2: /* return result */
/* if no process available handle separately */
if (!pc)
{ if (cr == -1)
l3dss1_dummy_return_result(st, id, p, nlen);
return;
}
if ((pc->prot.dss1.invoke_id) && (pc->prot.dss1.invoke_id == id))
{ /* Diversion successful */
free_invoke_id(st, pc->prot.dss1.invoke_id);
pc->prot.dss1.remote_result = 0; /* success */
pc->prot.dss1.invoke_id = 0;
pc->redir_result = pc->prot.dss1.remote_result;
st->l3.l3l4(st, CC_REDIR | INDICATION, pc); } /* Diversion successful */
else
l3_debug(st, "return error unknown identifier");
break;
case 3: /* return error */
err_ret = 0;
if (nlen < 2)
{ l3_debug(st, "return error nlen < 2");
return;
}
if (*p != 0x02)
{ /* result tag */
l3_debug(st, "invoke error tag !=0x02");
return;
}
p++;
nlen--;
if (*p > 4)
{ /* length format */
l3_debug(st, "invoke return errlen > 4 ");
return;
}
ilen = *p++;
nlen--;
if (ilen > nlen || ilen == 0)
{ l3_debug(st, "error return ilen > nlen || ilen == 0");
return;
}
nlen -= ilen;
while (ilen > 0)
{ err_ret = (err_ret << 8) | (*p++ & 0xFF); /* error value */
ilen--;
}
/* if no process available handle separately */
if (!pc)
{ if (cr == -1)
l3dss1_dummy_error_return(st, id, err_ret);
return;
}
if ((pc->prot.dss1.invoke_id) && (pc->prot.dss1.invoke_id == id))
{ /* Deflection error */
free_invoke_id(st, pc->prot.dss1.invoke_id);
pc->prot.dss1.remote_result = err_ret; /* result */
pc->prot.dss1.invoke_id = 0;
pc->redir_result = pc->prot.dss1.remote_result;
st->l3.l3l4(st, CC_REDIR | INDICATION, pc);
} /* Deflection error */
else
l3_debug(st, "return result unknown identifier");
break;
default:
l3_debug(st, "facility default break tag=0x%02x", cp_tag);
break;
}
}
static void
l3dss1_message(struct l3_process *pc, u_char mt)
{
struct sk_buff *skb;
u_char *p;
if (!(skb = l3_alloc_skb(4)))
return;
p = skb_put(skb, 4);
MsgHead(p, pc->callref, mt);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_message_cause(struct l3_process *pc, u_char mt, u_char cause)
{
struct sk_buff *skb;
u_char tmp[16];
u_char *p = tmp;
int l;
MsgHead(p, pc->callref, mt);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_status_send(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
MsgHead(p, pc->callref, MT_STATUS);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = pc->para.cause | 0x80;
*p++ = IE_CALL_STATE;
*p++ = 0x1;
*p++ = pc->state & 0x3f;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_msg_without_setup(struct l3_process *pc, u_char pr, void *arg)
{
/* This routine is called if here was no SETUP made (checks in dss1up and in
* l3dss1_setup) and a RELEASE_COMPLETE have to be sent with an error code
* MT_STATUS_ENQUIRE in the NULL state is handled too
*/
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
switch (pc->para.cause) {
case 81: /* invalid callreference */
case 88: /* incomp destination */
case 96: /* mandory IE missing */
case 100: /* invalid IE contents */
case 101: /* incompatible Callstate */
MsgHead(p, pc->callref, MT_RELEASE_COMPLETE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = pc->para.cause | 0x80;
break;
default:
printk(KERN_ERR "HiSax l3dss1_msg_without_setup wrong cause %d\n",
pc->para.cause);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
dss1_release_l3_process(pc);
}
static int ie_ALERTING[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, IE_HLC,
IE_USER_USER, -1};
static int ie_CALL_PROCEEDING[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_HLC, -1};
static int ie_CONNECT[] = {IE_BEARER, IE_CHANNEL_ID | IE_MANDATORY_1,
IE_FACILITY, IE_PROGRESS, IE_DISPLAY, IE_DATE, IE_SIGNAL,
IE_CONNECT_PN, IE_CONNECT_SUB, IE_LLC, IE_HLC, IE_USER_USER, -1};
static int ie_CONNECT_ACKNOWLEDGE[] = {IE_CHANNEL_ID, IE_DISPLAY, IE_SIGNAL, -1};
static int ie_DISCONNECT[] = {IE_CAUSE | IE_MANDATORY, IE_FACILITY,
IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, IE_USER_USER, -1};
static int ie_INFORMATION[] = {IE_COMPLETE, IE_DISPLAY, IE_KEYPAD, IE_SIGNAL,
IE_CALLED_PN, -1};
static int ie_NOTIFY[] = {IE_BEARER, IE_NOTIFY | IE_MANDATORY, IE_DISPLAY, -1};
static int ie_PROGRESS[] = {IE_BEARER, IE_CAUSE, IE_FACILITY, IE_PROGRESS |
IE_MANDATORY, IE_DISPLAY, IE_HLC, IE_USER_USER, -1};
static int ie_RELEASE[] = {IE_CAUSE | IE_MANDATORY_1, IE_FACILITY, IE_DISPLAY,
IE_SIGNAL, IE_USER_USER, -1};
/* a RELEASE_COMPLETE with errors don't require special actions
static int ie_RELEASE_COMPLETE[] = {IE_CAUSE | IE_MANDATORY_1, IE_DISPLAY, IE_SIGNAL, IE_USER_USER, -1};
*/
static int ie_RESUME_ACKNOWLEDGE[] = {IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY,
IE_DISPLAY, -1};
static int ie_RESUME_REJECT[] = {IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
static int ie_SETUP[] = {IE_COMPLETE, IE_BEARER | IE_MANDATORY,
IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY, IE_PROGRESS,
IE_NET_FAC, IE_DISPLAY, IE_KEYPAD, IE_SIGNAL, IE_CALLING_PN,
IE_CALLING_SUB, IE_CALLED_PN, IE_CALLED_SUB, IE_REDIR_NR,
IE_LLC, IE_HLC, IE_USER_USER, -1};
static int ie_SETUP_ACKNOWLEDGE[] = {IE_CHANNEL_ID | IE_MANDATORY, IE_FACILITY,
IE_PROGRESS, IE_DISPLAY, IE_SIGNAL, -1};
static int ie_STATUS[] = {IE_CAUSE | IE_MANDATORY, IE_CALL_STATE |
IE_MANDATORY, IE_DISPLAY, -1};
static int ie_STATUS_ENQUIRY[] = {IE_DISPLAY, -1};
static int ie_SUSPEND_ACKNOWLEDGE[] = {IE_DISPLAY, IE_FACILITY, -1};
static int ie_SUSPEND_REJECT[] = {IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
/* not used
* static int ie_CONGESTION_CONTROL[] = {IE_CONGESTION | IE_MANDATORY,
* IE_CAUSE | IE_MANDATORY, IE_DISPLAY, -1};
* static int ie_USER_INFORMATION[] = {IE_MORE_DATA, IE_USER_USER | IE_MANDATORY, -1};
* static int ie_RESTART[] = {IE_CHANNEL_ID, IE_DISPLAY, IE_RESTART_IND |
* IE_MANDATORY, -1};
*/
static int ie_FACILITY[] = {IE_FACILITY | IE_MANDATORY, IE_DISPLAY, -1};
static int comp_required[] = {1, 2, 3, 5, 6, 7, 9, 10, 11, 14, 15, -1};
static int l3_valid_states[] = {0, 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 15, 17, 19, 25, -1};
struct ie_len {
int ie;
int len;
};
static
struct ie_len max_ie_len[] = {
{IE_SEGMENT, 4},
{IE_BEARER, 12},
{IE_CAUSE, 32},
{IE_CALL_ID, 10},
{IE_CALL_STATE, 3},
{IE_CHANNEL_ID, 34},
{IE_FACILITY, 255},
{IE_PROGRESS, 4},
{IE_NET_FAC, 255},
{IE_NOTIFY, 3},
{IE_DISPLAY, 82},
{IE_DATE, 8},
{IE_KEYPAD, 34},
{IE_SIGNAL, 3},
{IE_INFORATE, 6},
{IE_E2E_TDELAY, 11},
{IE_TDELAY_SEL, 5},
{IE_PACK_BINPARA, 3},
{IE_PACK_WINSIZE, 4},
{IE_PACK_SIZE, 4},
{IE_CUG, 7},
{IE_REV_CHARGE, 3},
{IE_CALLING_PN, 24},
{IE_CALLING_SUB, 23},
{IE_CALLED_PN, 24},
{IE_CALLED_SUB, 23},
{IE_REDIR_NR, 255},
{IE_TRANS_SEL, 255},
{IE_RESTART_IND, 3},
{IE_LLC, 18},
{IE_HLC, 5},
{IE_USER_USER, 131},
{-1, 0},
};
static int
getmax_ie_len(u_char ie) {
int i = 0;
while (max_ie_len[i].ie != -1) {
if (max_ie_len[i].ie == ie)
return (max_ie_len[i].len);
i++;
}
return (255);
}
static int
ie_in_set(struct l3_process *pc, u_char ie, int *checklist) {
int ret = 1;
while (*checklist != -1) {
if ((*checklist & 0xff) == ie) {
if (ie & 0x80)
return (-ret);
else
return (ret);
}
ret++;
checklist++;
}
return (0);
}
static int
check_infoelements(struct l3_process *pc, struct sk_buff *skb, int *checklist)
{
int *cl = checklist;
u_char mt;
u_char *p, ie;
int l, newpos, oldpos;
int err_seq = 0, err_len = 0, err_compr = 0, err_ureg = 0;
u_char codeset = 0;
u_char old_codeset = 0;
u_char codelock = 1;
p = skb->data;
/* skip cr */
p++;
l = (*p++) & 0xf;
p += l;
mt = *p++;
oldpos = 0;
while ((p - skb->data) < skb->len) {
if ((*p & 0xf0) == 0x90) { /* shift codeset */
old_codeset = codeset;
codeset = *p & 7;
if (*p & 0x08)
codelock = 0;
else
codelock = 1;
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE shift%scodeset %d->%d",
codelock ? " locking " : " ", old_codeset, codeset);
p++;
continue;
}
if (!codeset) { /* only codeset 0 */
if ((newpos = ie_in_set(pc, *p, cl))) {
if (newpos > 0) {
if (newpos < oldpos)
err_seq++;
else
oldpos = newpos;
}
} else {
if (ie_in_set(pc, *p, comp_required))
err_compr++;
else
err_ureg++;
}
}
ie = *p++;
if (ie & 0x80) {
l = 1;
} else {
l = *p++;
p += l;
l += 2;
}
if (!codeset && (l > getmax_ie_len(ie)))
err_len++;
if (!codelock) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE shift back codeset %d->%d",
codeset, old_codeset);
codeset = old_codeset;
codelock = 1;
}
}
if (err_compr | err_ureg | err_len | err_seq) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check IE MT(%x) %d/%d/%d/%d",
mt, err_compr, err_ureg, err_len, err_seq);
if (err_compr)
return (ERR_IE_COMPREHENSION);
if (err_ureg)
return (ERR_IE_UNRECOGNIZED);
if (err_len)
return (ERR_IE_LENGTH);
if (err_seq)
return (ERR_IE_SEQUENCE);
}
return (0);
}
/* verify if a message type exists and contain no IE error */
static int
l3dss1_check_messagetype_validity(struct l3_process *pc, int mt, void *arg)
{
switch (mt) {
case MT_ALERTING:
case MT_CALL_PROCEEDING:
case MT_CONNECT:
case MT_CONNECT_ACKNOWLEDGE:
case MT_DISCONNECT:
case MT_INFORMATION:
case MT_FACILITY:
case MT_NOTIFY:
case MT_PROGRESS:
case MT_RELEASE:
case MT_RELEASE_COMPLETE:
case MT_SETUP:
case MT_SETUP_ACKNOWLEDGE:
case MT_RESUME_ACKNOWLEDGE:
case MT_RESUME_REJECT:
case MT_SUSPEND_ACKNOWLEDGE:
case MT_SUSPEND_REJECT:
case MT_USER_INFORMATION:
case MT_RESTART:
case MT_RESTART_ACKNOWLEDGE:
case MT_CONGESTION_CONTROL:
case MT_STATUS:
case MT_STATUS_ENQUIRY:
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "l3dss1_check_messagetype_validity mt(%x) OK", mt);
break;
case MT_RESUME: /* RESUME only in user->net */
case MT_SUSPEND: /* SUSPEND only in user->net */
default:
if (pc->debug & (L3_DEB_CHECK | L3_DEB_WARN))
l3_debug(pc->st, "l3dss1_check_messagetype_validity mt(%x) fail", mt);
pc->para.cause = 97;
l3dss1_status_send(pc, 0, NULL);
return (1);
}
return (0);
}
static void
l3dss1_std_ie_err(struct l3_process *pc, int ret) {
if (pc->debug & L3_DEB_CHECK)
l3_debug(pc->st, "check_infoelements ret %d", ret);
switch (ret) {
case 0:
break;
case ERR_IE_COMPREHENSION:
pc->para.cause = 96;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_UNRECOGNIZED:
pc->para.cause = 99;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_LENGTH:
pc->para.cause = 100;
l3dss1_status_send(pc, 0, NULL);
break;
case ERR_IE_SEQUENCE:
default:
break;
}
}
static int
l3dss1_get_channel_id(struct l3_process *pc, struct sk_buff *skb) {
u_char *p;
p = skb->data;
if ((p = findie(p, skb->len, IE_CHANNEL_ID, 0))) {
p++;
if (*p != 1) { /* len for BRI = 1 */
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong chid len %d", *p);
return (-2);
}
p++;
if (*p & 0x60) { /* only base rate interface */
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong chid %x", *p);
return (-3);
}
return (*p & 0x3);
} else
return (-1);
}
static int
l3dss1_get_cause(struct l3_process *pc, struct sk_buff *skb) {
u_char l, i = 0;
u_char *p;
p = skb->data;
pc->para.cause = 31;
pc->para.loc = 0;
if ((p = findie(p, skb->len, IE_CAUSE, 0))) {
p++;
l = *p++;
if (l > 30)
return (1);
if (l) {
pc->para.loc = *p++;
l--;
} else {
return (2);
}
if (l && !(pc->para.loc & 0x80)) {
l--;
p++; /* skip recommendation */
}
if (l) {
pc->para.cause = *p++;
l--;
if (!(pc->para.cause & 0x80))
return (3);
} else
return (4);
while (l && (i < 6)) {
pc->para.diag[i++] = *p++;
l--;
}
} else
return (-1);
return (0);
}
static void
l3dss1_msg_with_uus(struct l3_process *pc, u_char cmd)
{
struct sk_buff *skb;
u_char tmp[16 + 40];
u_char *p = tmp;
int l;
MsgHead(p, pc->callref, cmd);
if (pc->prot.dss1.uus1_data[0])
{ *p++ = IE_USER_USER; /* UUS info element */
*p++ = strlen(pc->prot.dss1.uus1_data) + 1;
*p++ = 0x04; /* IA5 chars */
strcpy(p, pc->prot.dss1.uus1_data);
p += strlen(pc->prot.dss1.uus1_data);
pc->prot.dss1.uus1_data[0] = '\0';
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
} /* l3dss1_msg_with_uus */
static void
l3dss1_release_req(struct l3_process *pc, u_char pr, void *arg)
{
StopAllL3Timer(pc);
newl3state(pc, 19);
if (!pc->prot.dss1.uus1_data[0])
l3dss1_message(pc, MT_RELEASE);
else
l3dss1_msg_with_uus(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_release_cmpl(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb)) > 0) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "RELCMPL get_cause ret(%d)", ret);
} else if (ret < 0)
pc->para.cause = NO_CAUSE;
StopAllL3Timer(pc);
newl3state(pc, 0);
pc->st->l3.l3l4(pc->st, CC_RELEASE | CONFIRM, pc);
dss1_release_l3_process(pc);
}
#ifdef EXT_BEARER_CAPS
static u_char *
EncodeASyncParams(u_char *p, u_char si2)
{ // 7c 06 88 90 21 42 00 bb
p[0] = 0;
p[1] = 0x40; // Intermediate rate: 16 kbit/s jj 2000.02.19
p[2] = 0x80;
if (si2 & 32) // 7 data bits
p[2] += 16;
else // 8 data bits
p[2] += 24;
if (si2 & 16) // 2 stop bits
p[2] += 96;
else // 1 stop bit
p[2] += 32;
if (si2 & 8) // even parity
p[2] += 2;
else // no parity
p[2] += 3;
switch (si2 & 0x07) {
case 0:
p[0] = 66; // 1200 bit/s
break;
case 1:
p[0] = 88; // 1200/75 bit/s
break;
case 2:
p[0] = 87; // 75/1200 bit/s
break;
case 3:
p[0] = 67; // 2400 bit/s
break;
case 4:
p[0] = 69; // 4800 bit/s
break;
case 5:
p[0] = 72; // 9600 bit/s
break;
case 6:
p[0] = 73; // 14400 bit/s
break;
case 7:
p[0] = 75; // 19200 bit/s
break;
}
return p + 3;
}
static u_char
EncodeSyncParams(u_char si2, u_char ai)
{
switch (si2) {
case 0:
return ai + 2; // 1200 bit/s
case 1:
return ai + 24; // 1200/75 bit/s
case 2:
return ai + 23; // 75/1200 bit/s
case 3:
return ai + 3; // 2400 bit/s
case 4:
return ai + 5; // 4800 bit/s
case 5:
return ai + 8; // 9600 bit/s
case 6:
return ai + 9; // 14400 bit/s
case 7:
return ai + 11; // 19200 bit/s
case 8:
return ai + 14; // 48000 bit/s
case 9:
return ai + 15; // 56000 bit/s
case 15:
return ai + 40; // negotiate bit/s
default:
break;
}
return ai;
}
static u_char
DecodeASyncParams(u_char si2, u_char *p)
{
u_char info;
switch (p[5]) {
case 66: // 1200 bit/s
break; // si2 don't change
case 88: // 1200/75 bit/s
si2 += 1;
break;
case 87: // 75/1200 bit/s
si2 += 2;
break;
case 67: // 2400 bit/s
si2 += 3;
break;
case 69: // 4800 bit/s
si2 += 4;
break;
case 72: // 9600 bit/s
si2 += 5;
break;
case 73: // 14400 bit/s
si2 += 6;
break;
case 75: // 19200 bit/s
si2 += 7;
break;
}
info = p[7] & 0x7f;
if ((info & 16) && (!(info & 8))) // 7 data bits
si2 += 32; // else 8 data bits
if ((info & 96) == 96) // 2 stop bits
si2 += 16; // else 1 stop bit
if ((info & 2) && (!(info & 1))) // even parity
si2 += 8; // else no parity
return si2;
}
static u_char
DecodeSyncParams(u_char si2, u_char info)
{
info &= 0x7f;
switch (info) {
case 40: // bit/s negotiation failed ai := 165 not 175!
return si2 + 15;
case 15: // 56000 bit/s failed, ai := 0 not 169 !
return si2 + 9;
case 14: // 48000 bit/s
return si2 + 8;
case 11: // 19200 bit/s
return si2 + 7;
case 9: // 14400 bit/s
return si2 + 6;
case 8: // 9600 bit/s
return si2 + 5;
case 5: // 4800 bit/s
return si2 + 4;
case 3: // 2400 bit/s
return si2 + 3;
case 23: // 75/1200 bit/s
return si2 + 2;
case 24: // 1200/75 bit/s
return si2 + 1;
default: // 1200 bit/s
return si2;
}
}
static u_char
DecodeSI2(struct sk_buff *skb)
{
u_char *p; //, *pend=skb->data + skb->len;
if ((p = findie(skb->data, skb->len, 0x7c, 0))) {
switch (p[4] & 0x0f) {
case 0x01:
if (p[1] == 0x04) // sync. Bitratenadaption
return DecodeSyncParams(160, p[5]); // V.110/X.30
else if (p[1] == 0x06) // async. Bitratenadaption
return DecodeASyncParams(192, p); // V.110/X.30
break;
case 0x08: // if (p[5] == 0x02) // sync. Bitratenadaption
if (p[1] > 3)
return DecodeSyncParams(176, p[5]); // V.120
break;
}
}
return 0;
}
#endif
static void
l3dss1_setup_req(struct l3_process *pc, u_char pr,
void *arg)
{
struct sk_buff *skb;
u_char tmp[128];
u_char *p = tmp;
u_char channel = 0;
u_char send_keypad;
u_char screen = 0x80;
u_char *teln;
u_char *msn;
u_char *sub;
u_char *sp;
int l;
MsgHead(p, pc->callref, MT_SETUP);
teln = pc->para.setup.phone;
#ifndef CONFIG_HISAX_NO_KEYPAD
send_keypad = (strchr(teln, '*') || strchr(teln, '#')) ? 1 : 0;
#else
send_keypad = 0;
#endif
#ifndef CONFIG_HISAX_NO_SENDCOMPLETE
if (!send_keypad)
*p++ = 0xa1; /* complete indicator */
#endif
/*
* Set Bearer Capability, Map info from 1TR6-convention to EDSS1
*/
switch (pc->para.setup.si1) {
case 1: /* Telephony */
*p++ = IE_BEARER;
*p++ = 0x3; /* Length */
*p++ = 0x90; /* Coding Std. CCITT, 3.1 kHz audio */
*p++ = 0x90; /* Circuit-Mode 64kbps */
*p++ = 0xa3; /* A-Law Audio */
break;
case 5: /* Datatransmission 64k, BTX */
case 7: /* Datatransmission 64k */
default:
*p++ = IE_BEARER;
*p++ = 0x2; /* Length */
*p++ = 0x88; /* Coding Std. CCITT, unrestr. dig. Inform. */
*p++ = 0x90; /* Circuit-Mode 64kbps */
break;
}
if (send_keypad) {
*p++ = IE_KEYPAD;
*p++ = strlen(teln);
while (*teln)
*p++ = (*teln++) & 0x7F;
}
/*
* What about info2? Mapping to High-Layer-Compatibility?
*/
if ((*teln) && (!send_keypad)) {
/* parse number for special things */
if (!isdigit(*teln)) {
switch (0x5f & *teln) {
case 'C':
channel = 0x08;
case 'P':
channel |= 0x80;
teln++;
if (*teln == '1')
channel |= 0x01;
else
channel |= 0x02;
break;
case 'R':
screen = 0xA0;
break;
case 'D':
screen = 0x80;
break;
default:
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "Wrong MSN Code");
break;
}
teln++;
}
}
if (channel) {
*p++ = IE_CHANNEL_ID;
*p++ = 1;
*p++ = channel;
}
msn = pc->para.setup.eazmsn;
sub = NULL;
sp = msn;
while (*sp) {
if ('.' == *sp) {
sub = sp;
*sp = 0;
} else
sp++;
}
if (*msn) {
*p++ = IE_CALLING_PN;
*p++ = strlen(msn) + (screen ? 2 : 1);
/* Classify as AnyPref. */
if (screen) {
*p++ = 0x01; /* Ext = '0'B, Type = '000'B, Plan = '0001'B. */
*p++ = screen;
} else
*p++ = 0x81; /* Ext = '1'B, Type = '000'B, Plan = '0001'B. */
while (*msn)
*p++ = *msn++ & 0x7f;
}
if (sub) {
*sub++ = '.';
*p++ = IE_CALLING_SUB;
*p++ = strlen(sub) + 2;
*p++ = 0x80; /* NSAP coded */
*p++ = 0x50; /* local IDI format */
while (*sub)
*p++ = *sub++ & 0x7f;
}
sub = NULL;
sp = teln;
while (*sp) {
if ('.' == *sp) {
sub = sp;
*sp = 0;
} else
sp++;
}
if (!send_keypad) {
*p++ = IE_CALLED_PN;
*p++ = strlen(teln) + 1;
/* Classify as AnyPref. */
*p++ = 0x81; /* Ext = '1'B, Type = '000'B, Plan = '0001'B. */
while (*teln)
*p++ = *teln++ & 0x7f;
if (sub) {
*sub++ = '.';
*p++ = IE_CALLED_SUB;
*p++ = strlen(sub) + 2;
*p++ = 0x80; /* NSAP coded */
*p++ = 0x50; /* local IDI format */
while (*sub)
*p++ = *sub++ & 0x7f;
}
}
#ifdef EXT_BEARER_CAPS
if ((pc->para.setup.si2 >= 160) && (pc->para.setup.si2 <= 175)) { // sync. Bitratenadaption, V.110/X.30
*p++ = IE_LLC;
*p++ = 0x04;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x21;
*p++ = EncodeSyncParams(pc->para.setup.si2 - 160, 0x80);
} else if ((pc->para.setup.si2 >= 176) && (pc->para.setup.si2 <= 191)) { // sync. Bitratenadaption, V.120
*p++ = IE_LLC;
*p++ = 0x05;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x28;
*p++ = EncodeSyncParams(pc->para.setup.si2 - 176, 0);
*p++ = 0x82;
} else if (pc->para.setup.si2 >= 192) { // async. Bitratenadaption, V.110/X.30
*p++ = IE_LLC;
*p++ = 0x06;
*p++ = 0x88;
*p++ = 0x90;
*p++ = 0x21;
p = EncodeASyncParams(p, pc->para.setup.si2 - 192);
#ifndef CONFIG_HISAX_NO_LLC
} else {
switch (pc->para.setup.si1) {
case 1: /* Telephony */
*p++ = IE_LLC;
*p++ = 0x3; /* Length */
*p++ = 0x90; /* Coding Std. CCITT, 3.1 kHz audio */
*p++ = 0x90; /* Circuit-Mode 64kbps */
*p++ = 0xa3; /* A-Law Audio */
break;
case 5: /* Datatransmission 64k, BTX */
case 7: /* Datatransmission 64k */
default:
*p++ = IE_LLC;
*p++ = 0x2; /* Length */
*p++ = 0x88; /* Coding Std. CCITT, unrestr. dig. Inform. */
*p++ = 0x90; /* Circuit-Mode 64kbps */
break;
}
#endif
}
#endif
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T303, CC_T303);
newl3state(pc, 1);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_call_proc(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else if (1 == pc->state) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer wrong chid (ret %d)", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
ret = check_infoelements(pc, skb, ie_CALL_PROCEEDING);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
newl3state(pc, 3);
L3AddTimer(&pc->timer, T310, CC_T310);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_PROCEEDING | INDICATION, pc);
}
static void
l3dss1_setup_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup answer wrong chid (ret %d)", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
ret = check_infoelements(pc, skb, ie_SETUP_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
newl3state(pc, 2);
L3AddTimer(&pc->timer, T304, CC_T304);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_MORE_INFO | INDICATION, pc);
}
static void
l3dss1_disconnect(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
u_char *p;
int ret;
u_char cause = 0;
StopAllL3Timer(pc);
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "DISC get_cause ret(%d)", ret);
if (ret < 0)
cause = 96;
else if (ret > 0)
cause = 100;
}
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0)))
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
ret = check_infoelements(pc, skb, ie_DISCONNECT);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if ((!cause) && (ERR_IE_UNRECOGNIZED == ret))
cause = 99;
ret = pc->state;
newl3state(pc, 12);
if (cause)
newl3state(pc, 19);
if (11 != ret)
pc->st->l3.l3l4(pc->st, CC_DISCONNECT | INDICATION, pc);
else if (!cause)
l3dss1_release_req(pc, pr, NULL);
if (cause) {
l3dss1_message_cause(pc, MT_RELEASE, cause);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
}
static void
l3dss1_connect(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_CONNECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer); /* T310 */
newl3state(pc, 10);
pc->para.chargeinfo = 0;
/* here should inserted COLP handling KKe */
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_SETUP | CONFIRM, pc);
}
static void
l3dss1_alerting(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_ALERTING);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer); /* T304 */
newl3state(pc, 4);
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_ALERTING | INDICATION, pc);
}
static void
l3dss1_setup(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
int bcfound = 0;
char tmp[80];
struct sk_buff *skb = arg;
int id;
int err = 0;
/*
* Bearer Capabilities
*/
p = skb->data;
/* only the first occurrence 'll be detected ! */
if ((p = findie(p, skb->len, 0x04, 0))) {
if ((p[1] < 2) || (p[1] > 11))
err = 1;
else {
pc->para.setup.si2 = 0;
switch (p[2] & 0x7f) {
case 0x00: /* Speech */
case 0x10: /* 3.1 Khz audio */
pc->para.setup.si1 = 1;
break;
case 0x08: /* Unrestricted digital information */
pc->para.setup.si1 = 7;
/* JIM, 05.11.97 I wanna set service indicator 2 */
#ifdef EXT_BEARER_CAPS
pc->para.setup.si2 = DecodeSI2(skb);
#endif
break;
case 0x09: /* Restricted digital information */
pc->para.setup.si1 = 2;
break;
case 0x11:
/* Unrestr. digital information with
* tones/announcements ( or 7 kHz audio
*/
pc->para.setup.si1 = 3;
break;
case 0x18: /* Video */
pc->para.setup.si1 = 4;
break;
default:
err = 2;
break;
}
switch (p[3] & 0x7f) {
case 0x40: /* packed mode */
pc->para.setup.si1 = 8;
break;
case 0x10: /* 64 kbit */
case 0x11: /* 2*64 kbit */
case 0x13: /* 384 kbit */
case 0x15: /* 1536 kbit */
case 0x17: /* 1920 kbit */
pc->para.moderate = p[3] & 0x7f;
break;
default:
err = 3;
break;
}
}
if (pc->debug & L3_DEB_SI)
l3_debug(pc->st, "SI=%d, AI=%d",
pc->para.setup.si1, pc->para.setup.si2);
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong bearer(l=%d:%x,%x)",
p[1], p[2], p[3]);
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup without bearer capabilities");
/* ETS 300-104 1.3.3 */
pc->para.cause = 96;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
/*
* Channel Identification
*/
if ((id = l3dss1_get_channel_id(pc, skb)) >= 0) {
if ((pc->para.bchannel = id)) {
if ((3 == id) && (0x10 == pc->para.moderate)) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong chid %x",
id);
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
bcfound++;
} else
{ if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup without bchannel, call waiting");
bcfound++;
}
} else {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "setup with wrong chid ret %d", id);
if (id == -1)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_SETUP);
if (ERR_IE_COMPREHENSION == err) {
pc->para.cause = 96;
l3dss1_msg_without_setup(pc, pr, NULL);
return;
}
p = skb->data;
if ((p = findie(p, skb->len, 0x70, 0)))
iecpy(pc->para.setup.eazmsn, p, 1);
else
pc->para.setup.eazmsn[0] = 0;
p = skb->data;
if ((p = findie(p, skb->len, 0x71, 0))) {
/* Called party subaddress */
if ((p[1] >= 2) && (p[2] == 0x80) && (p[3] == 0x50)) {
tmp[0] = '.';
iecpy(&tmp[1], p, 2);
strcat(pc->para.setup.eazmsn, tmp);
} else if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong called subaddress");
}
p = skb->data;
if ((p = findie(p, skb->len, 0x6c, 0))) {
pc->para.setup.plan = p[2];
if (p[2] & 0x80) {
iecpy(pc->para.setup.phone, p, 1);
pc->para.setup.screen = 0;
} else {
iecpy(pc->para.setup.phone, p, 2);
pc->para.setup.screen = p[3];
}
} else {
pc->para.setup.phone[0] = 0;
pc->para.setup.plan = 0;
pc->para.setup.screen = 0;
}
p = skb->data;
if ((p = findie(p, skb->len, 0x6d, 0))) {
/* Calling party subaddress */
if ((p[1] >= 2) && (p[2] == 0x80) && (p[3] == 0x50)) {
tmp[0] = '.';
iecpy(&tmp[1], p, 2);
strcat(pc->para.setup.phone, tmp);
} else if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "wrong calling subaddress");
}
newl3state(pc, 6);
if (err) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, err);
pc->st->l3.l3l4(pc->st, CC_SETUP | INDICATION, pc);
}
static void
l3dss1_reset(struct l3_process *pc, u_char pr, void *arg)
{
dss1_release_l3_process(pc);
}
static void
l3dss1_disconnect_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[16 + 40];
u_char *p = tmp;
int l;
u_char cause = 16;
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
StopAllL3Timer(pc);
MsgHead(p, pc->callref, MT_DISCONNECT);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
if (pc->prot.dss1.uus1_data[0])
{ *p++ = IE_USER_USER; /* UUS info element */
*p++ = strlen(pc->prot.dss1.uus1_data) + 1;
*p++ = 0x04; /* IA5 chars */
strcpy(p, pc->prot.dss1.uus1_data);
p += strlen(pc->prot.dss1.uus1_data);
pc->prot.dss1.uus1_data[0] = '\0';
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 11);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
L3AddTimer(&pc->timer, T305, CC_T305);
}
static void
l3dss1_setup_rsp(struct l3_process *pc, u_char pr,
void *arg)
{
if (!pc->para.bchannel)
{ if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "D-chan connect for waiting call");
l3dss1_disconnect_req(pc, pr, arg);
return;
}
newl3state(pc, 8);
l3dss1_message(pc, MT_CONNECT);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T313, CC_T313);
}
static void
l3dss1_connect_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_CONNECT_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
newl3state(pc, 10);
L3DelTimer(&pc->timer);
if (ret)
l3dss1_std_ie_err(pc, ret);
pc->st->l3.l3l4(pc->st, CC_SETUP_COMPL | INDICATION, pc);
}
static void
l3dss1_reject_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[16];
u_char *p = tmp;
int l;
u_char cause = 21;
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
MsgHead(p, pc->callref, MT_RELEASE_COMPLETE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
static void
l3dss1_release(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
u_char *p;
int ret, cause = 0;
StopAllL3Timer(pc);
if ((ret = l3dss1_get_cause(pc, skb)) > 0) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "REL get_cause ret(%d)", ret);
} else if (ret < 0)
pc->para.cause = NO_CAUSE;
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0))) {
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
}
if ((ret < 0) && (pc->state != 11))
cause = 96;
else if (ret > 0)
cause = 100;
ret = check_infoelements(pc, skb, ie_RELEASE);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if ((ERR_IE_UNRECOGNIZED == ret) && (!cause))
cause = 99;
if (cause)
l3dss1_message_cause(pc, MT_RELEASE_COMPLETE, cause);
else
l3dss1_message(pc, MT_RELEASE_COMPLETE);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
static void
l3dss1_alert_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 7);
if (!pc->prot.dss1.uus1_data[0])
l3dss1_message(pc, MT_ALERTING);
else
l3dss1_msg_with_uus(pc, MT_ALERTING);
}
static void
l3dss1_proceed_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 9);
l3dss1_message(pc, MT_CALL_PROCEEDING);
pc->st->l3.l3l4(pc->st, CC_PROCEED_SEND | INDICATION, pc);
}
static void
l3dss1_setup_ack_req(struct l3_process *pc, u_char pr,
void *arg)
{
newl3state(pc, 25);
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T302, CC_T302);
l3dss1_message(pc, MT_SETUP_ACKNOWLEDGE);
}
/********************************************/
/* deliver a incoming display message to HL */
/********************************************/
static void
l3dss1_deliver_display(struct l3_process *pc, int pr, u_char *infp)
{ u_char len;
isdn_ctrl ic;
struct IsdnCardState *cs;
char *p;
if (*infp++ != IE_DISPLAY) return;
if ((len = *infp++) > 80) return; /* total length <= 82 */
if (!pc->chan) return;
p = ic.parm.display;
while (len--)
*p++ = *infp++;
*p = '\0';
ic.command = ISDN_STAT_DISPLAY;
cs = pc->st->l1.hardware;
ic.driver = cs->myid;
ic.arg = pc->chan->chan;
cs->iif.statcallb(&ic);
} /* l3dss1_deliver_display */
static void
l3dss1_progress(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int err = 0;
u_char *p;
if ((p = findie(skb->data, skb->len, IE_PROGRESS, 0))) {
if (p[1] != 2) {
err = 1;
pc->para.cause = 100;
} else if (!(p[2] & 0x70)) {
switch (p[2]) {
case 0x80:
case 0x81:
case 0x82:
case 0x84:
case 0x85:
case 0x87:
case 0x8a:
switch (p[3]) {
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x88:
break;
default:
err = 2;
pc->para.cause = 100;
break;
}
break;
default:
err = 3;
pc->para.cause = 100;
break;
}
}
} else {
pc->para.cause = 96;
err = 4;
}
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "progress error %d", err);
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_PROGRESS);
if (err)
l3dss1_std_ie_err(pc, err);
if (ERR_IE_COMPREHENSION != err)
pc->st->l3.l3l4(pc->st, CC_PROGRESS | INDICATION, pc);
}
static void
l3dss1_notify(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int err = 0;
u_char *p;
if ((p = findie(skb->data, skb->len, IE_NOTIFY, 0))) {
if (p[1] != 1) {
err = 1;
pc->para.cause = 100;
} else {
switch (p[2]) {
case 0x80:
case 0x81:
case 0x82:
break;
default:
pc->para.cause = 100;
err = 2;
break;
}
}
} else {
pc->para.cause = 96;
err = 3;
}
if (err) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "notify error %d", err);
l3dss1_status_send(pc, pr, NULL);
return;
}
/* Now we are on none mandatory IEs */
err = check_infoelements(pc, skb, ie_NOTIFY);
if (err)
l3dss1_std_ie_err(pc, err);
if (ERR_IE_COMPREHENSION != err)
pc->st->l3.l3l4(pc->st, CC_NOTIFY | INDICATION, pc);
}
static void
l3dss1_status_enq(struct l3_process *pc, u_char pr, void *arg)
{
int ret;
struct sk_buff *skb = arg;
ret = check_infoelements(pc, skb, ie_STATUS_ENQUIRY);
l3dss1_std_ie_err(pc, ret);
pc->para.cause = 30; /* response to STATUS_ENQUIRY */
l3dss1_status_send(pc, pr, NULL);
}
static void
l3dss1_information(struct l3_process *pc, u_char pr, void *arg)
{
int ret;
struct sk_buff *skb = arg;
u_char *p;
char tmp[32];
ret = check_infoelements(pc, skb, ie_INFORMATION);
if (ret)
l3dss1_std_ie_err(pc, ret);
if (pc->state == 25) { /* overlap receiving */
L3DelTimer(&pc->timer);
p = skb->data;
if ((p = findie(p, skb->len, 0x70, 0))) {
iecpy(tmp, p, 1);
strcat(pc->para.setup.eazmsn, tmp);
pc->st->l3.l3l4(pc->st, CC_MORE_INFO | INDICATION, pc);
}
L3AddTimer(&pc->timer, T302, CC_T302);
}
}
/******************************/
/* handle deflection requests */
/******************************/
static void l3dss1_redir_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[128];
u_char *p = tmp;
u_char *subp;
u_char len_phone = 0;
u_char len_sub = 0;
int l;
strcpy(pc->prot.dss1.uus1_data, pc->chan->setup.eazmsn); /* copy uus element if available */
if (!pc->chan->setup.phone[0])
{ pc->para.cause = -1;
l3dss1_disconnect_req(pc, pr, arg); /* disconnect immediately */
return;
} /* only uus */
if (pc->prot.dss1.invoke_id)
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
if (!(pc->prot.dss1.invoke_id = new_invoke_id(pc->st)))
return;
MsgHead(p, pc->callref, MT_FACILITY);
for (subp = pc->chan->setup.phone; (*subp) && (*subp != '.'); subp++) len_phone++; /* len of phone number */
if (*subp++ == '.') len_sub = strlen(subp) + 2; /* length including info subaddress element */
*p++ = 0x1c; /* Facility info element */
*p++ = len_phone + len_sub + 2 + 2 + 8 + 3 + 3; /* length of element */
*p++ = 0x91; /* remote operations protocol */
*p++ = 0xa1; /* invoke component */
*p++ = len_phone + len_sub + 2 + 2 + 8 + 3; /* length of data */
*p++ = 0x02; /* invoke id tag, integer */
*p++ = 0x01; /* length */
*p++ = pc->prot.dss1.invoke_id; /* invoke id */
*p++ = 0x02; /* operation value tag, integer */
*p++ = 0x01; /* length */
*p++ = 0x0D; /* Call Deflect */
*p++ = 0x30; /* sequence phone number */
*p++ = len_phone + 2 + 2 + 3 + len_sub; /* length */
*p++ = 0x30; /* Deflected to UserNumber */
*p++ = len_phone + 2 + len_sub; /* length */
*p++ = 0x80; /* NumberDigits */
*p++ = len_phone; /* length */
for (l = 0; l < len_phone; l++)
*p++ = pc->chan->setup.phone[l];
if (len_sub)
{ *p++ = 0x04; /* called party subaddress */
*p++ = len_sub - 2;
while (*subp) *p++ = *subp++;
}
*p++ = 0x01; /* screening identifier */
*p++ = 0x01;
*p++ = pc->chan->setup.screen;
l = p - tmp;
if (!(skb = l3_alloc_skb(l))) return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
} /* l3dss1_redir_req */
/********************************************/
/* handle deflection request in early state */
/********************************************/
static void l3dss1_redir_req_early(struct l3_process *pc, u_char pr, void *arg)
{
l3dss1_proceed_req(pc, pr, arg);
l3dss1_redir_req(pc, pr, arg);
} /* l3dss1_redir_req_early */
/***********************************************/
/* handle special commands for this protocol. */
/* Examples are call independent services like */
/* remote operations with dummy callref. */
/***********************************************/
static int l3dss1_cmd_global(struct PStack *st, isdn_ctrl *ic)
{ u_char id;
u_char temp[265];
u_char *p = temp;
int i, l, proc_len;
struct sk_buff *skb;
struct l3_process *pc = NULL;
switch (ic->arg)
{ case DSS1_CMD_INVOKE:
if (ic->parm.dss1_io.datalen < 0) return (-2); /* invalid parameter */
for (proc_len = 1, i = ic->parm.dss1_io.proc >> 8; i; i++)
i = i >> 8; /* add one byte */
l = ic->parm.dss1_io.datalen + proc_len + 8; /* length excluding ie header */
if (l > 255)
return (-2); /* too long */
if (!(id = new_invoke_id(st)))
return (0); /* first get a invoke id -> return if no available */
i = -1;
MsgHead(p, i, MT_FACILITY); /* build message head */
*p++ = 0x1C; /* Facility IE */
*p++ = l; /* length of ie */
*p++ = 0x91; /* remote operations */
*p++ = 0xA1; /* invoke */
*p++ = l - 3; /* length of invoke */
*p++ = 0x02; /* invoke id tag */
*p++ = 0x01; /* length is 1 */
*p++ = id; /* invoke id */
*p++ = 0x02; /* operation */
*p++ = proc_len; /* length of operation */
for (i = proc_len; i; i--)
*p++ = (ic->parm.dss1_io.proc >> (i - 1)) & 0xFF;
memcpy(p, ic->parm.dss1_io.data, ic->parm.dss1_io.datalen); /* copy data */
l = (p - temp) + ic->parm.dss1_io.datalen; /* total length */
if (ic->parm.dss1_io.timeout > 0)
if (!(pc = dss1_new_l3_process(st, -1)))
{ free_invoke_id(st, id);
return (-2);
}
pc->prot.dss1.ll_id = ic->parm.dss1_io.ll_id; /* remember id */
pc->prot.dss1.proc = ic->parm.dss1_io.proc; /* and procedure */
if (!(skb = l3_alloc_skb(l)))
{ free_invoke_id(st, id);
if (pc) dss1_release_l3_process(pc);
return (-2);
}
memcpy(skb_put(skb, l), temp, l);
if (pc)
{ pc->prot.dss1.invoke_id = id; /* remember id */
L3AddTimer(&pc->timer, ic->parm.dss1_io.timeout, CC_TDSS1_IO | REQUEST);
}
l3_msg(st, DL_DATA | REQUEST, skb);
ic->parm.dss1_io.hl_id = id; /* return id */
return (0);
case DSS1_CMD_INVOKE_ABORT:
if ((pc = l3dss1_search_dummy_proc(st, ic->parm.dss1_io.hl_id)))
{ L3DelTimer(&pc->timer); /* remove timer */
dss1_release_l3_process(pc);
return (0);
}
else
{ l3_debug(st, "l3dss1_cmd_global abort unknown id");
return (-2);
}
break;
default:
l3_debug(st, "l3dss1_cmd_global unknown cmd 0x%lx", ic->arg);
return (-1);
} /* switch ic-> arg */
return (-1);
} /* l3dss1_cmd_global */
static void
l3dss1_io_timer(struct l3_process *pc)
{ isdn_ctrl ic;
struct IsdnCardState *cs = pc->st->l1.hardware;
L3DelTimer(&pc->timer); /* remove timer */
ic.driver = cs->myid;
ic.command = ISDN_STAT_PROT;
ic.arg = DSS1_STAT_INVOKE_ERR;
ic.parm.dss1_io.hl_id = pc->prot.dss1.invoke_id;
ic.parm.dss1_io.ll_id = pc->prot.dss1.ll_id;
ic.parm.dss1_io.proc = pc->prot.dss1.proc;
ic.parm.dss1_io.timeout = -1;
ic.parm.dss1_io.datalen = 0;
ic.parm.dss1_io.data = NULL;
free_invoke_id(pc->st, pc->prot.dss1.invoke_id);
pc->prot.dss1.invoke_id = 0; /* reset id */
cs->iif.statcallb(&ic);
dss1_release_l3_process(pc);
} /* l3dss1_io_timer */
static void
l3dss1_release_ind(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
struct sk_buff *skb = arg;
int callState = 0;
p = skb->data;
if ((p = findie(p, skb->len, IE_CALL_STATE, 0))) {
p++;
if (1 == *p++)
callState = *p;
}
if (callState == 0) {
/* ETS 300-104 7.6.1, 8.6.1, 10.6.1... and 16.1
* set down layer 3 without sending any message
*/
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
} else {
pc->st->l3.l3l4(pc->st, CC_IGNORE | INDICATION, pc);
}
}
static void
l3dss1_dummy(struct l3_process *pc, u_char pr, void *arg)
{
}
static void
l3dss1_t302(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 28; /* invalid number */
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t303(struct l3_process *pc, u_char pr, void *arg)
{
if (pc->N303 > 0) {
pc->N303--;
L3DelTimer(&pc->timer);
l3dss1_setup_req(pc, pr, arg);
} else {
L3DelTimer(&pc->timer);
l3dss1_message_cause(pc, MT_RELEASE_COMPLETE, 102);
pc->st->l3.l3l4(pc->st, CC_NOSETUP_RSP, pc);
dss1_release_l3_process(pc);
}
}
static void
l3dss1_t304(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t305(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[16];
u_char *p = tmp;
int l;
struct sk_buff *skb;
u_char cause = 16;
L3DelTimer(&pc->timer);
if (pc->para.cause != NO_CAUSE)
cause = pc->para.cause;
MsgHead(p, pc->callref, MT_RELEASE);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = cause | 0x80;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 19);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_t310(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_t313(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.loc = 0;
pc->para.cause = 102;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_CONNECT_ERR, pc);
}
static void
l3dss1_t308_1(struct l3_process *pc, u_char pr, void *arg)
{
newl3state(pc, 19);
L3DelTimer(&pc->timer);
l3dss1_message(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_2);
}
static void
l3dss1_t308_2(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RELEASE_ERR, pc);
dss1_release_l3_process(pc);
}
static void
l3dss1_t318(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 102; /* Timer expiry */
pc->para.loc = 0; /* local */
pc->st->l3.l3l4(pc->st, CC_RESUME_ERR, pc);
newl3state(pc, 19);
l3dss1_message(pc, MT_RELEASE);
L3AddTimer(&pc->timer, T308, CC_T308_1);
}
static void
l3dss1_t319(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 102; /* Timer expiry */
pc->para.loc = 0; /* local */
pc->st->l3.l3l4(pc->st, CC_SUSPEND_ERR, pc);
newl3state(pc, 10);
}
static void
l3dss1_restart(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
dss1_release_l3_process(pc);
}
static void
l3dss1_status(struct l3_process *pc, u_char pr, void *arg)
{
u_char *p;
struct sk_buff *skb = arg;
int ret;
u_char cause = 0, callState = 0;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "STATUS get_cause ret(%d)", ret);
if (ret < 0)
cause = 96;
else if (ret > 0)
cause = 100;
}
if ((p = findie(skb->data, skb->len, IE_CALL_STATE, 0))) {
p++;
if (1 == *p++) {
callState = *p;
if (!ie_in_set(pc, *p, l3_valid_states))
cause = 100;
} else
cause = 100;
} else
cause = 96;
if (!cause) { /* no error before */
ret = check_infoelements(pc, skb, ie_STATUS);
if (ERR_IE_COMPREHENSION == ret)
cause = 96;
else if (ERR_IE_UNRECOGNIZED == ret)
cause = 99;
}
if (cause) {
u_char tmp;
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "STATUS error(%d/%d)", ret, cause);
tmp = pc->para.cause;
pc->para.cause = cause;
l3dss1_status_send(pc, 0, NULL);
if (cause == 99)
pc->para.cause = tmp;
else
return;
}
cause = pc->para.cause;
if (((cause & 0x7f) == 111) && (callState == 0)) {
/* ETS 300-104 7.6.1, 8.6.1, 10.6.1...
* if received MT_STATUS with cause == 111 and call
* state == 0, then we must set down layer 3
*/
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
newl3state(pc, 0);
dss1_release_l3_process(pc);
}
}
static void
l3dss1_facility(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
ret = check_infoelements(pc, skb, ie_FACILITY);
l3dss1_std_ie_err(pc, ret);
{
u_char *p;
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0)))
l3dss1_parse_facility(pc->st, pc, pc->callref, p);
}
}
static void
l3dss1_suspend_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[32];
u_char *p = tmp;
u_char i, l;
u_char *msg = pc->chan->setup.phone;
MsgHead(p, pc->callref, MT_SUSPEND);
l = *msg++;
if (l && (l <= 10)) { /* Max length 10 octets */
*p++ = IE_CALL_ID;
*p++ = l;
for (i = 0; i < l; i++)
*p++ = *msg++;
} else if (l) {
l3_debug(pc->st, "SUS wrong CALL_ID len %d", l);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
newl3state(pc, 15);
L3AddTimer(&pc->timer, T319, CC_T319);
}
static void
l3dss1_suspend_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
L3DelTimer(&pc->timer);
newl3state(pc, 0);
pc->para.cause = NO_CAUSE;
pc->st->l3.l3l4(pc->st, CC_SUSPEND | CONFIRM, pc);
/* We don't handle suspend_ack for IE errors now */
if ((ret = check_infoelements(pc, skb, ie_SUSPEND_ACKNOWLEDGE)))
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "SUSPACK check ie(%d)", ret);
dss1_release_l3_process(pc);
}
static void
l3dss1_suspend_rej(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "SUSP_REJ get_cause ret(%d)", ret);
if (ret < 0)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_SUSPEND_REJECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_SUSPEND_ERR, pc);
newl3state(pc, 10);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
}
static void
l3dss1_resume_req(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb;
u_char tmp[32];
u_char *p = tmp;
u_char i, l;
u_char *msg = pc->para.setup.phone;
MsgHead(p, pc->callref, MT_RESUME);
l = *msg++;
if (l && (l <= 10)) { /* Max length 10 octets */
*p++ = IE_CALL_ID;
*p++ = l;
for (i = 0; i < l; i++)
*p++ = *msg++;
} else if (l) {
l3_debug(pc->st, "RES wrong CALL_ID len %d", l);
return;
}
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
newl3state(pc, 17);
L3AddTimer(&pc->timer, T318, CC_T318);
}
static void
l3dss1_resume_ack(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int id, ret;
if ((id = l3dss1_get_channel_id(pc, skb)) > 0) {
if ((0 == id) || ((3 == id) && (0x10 == pc->para.moderate))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "resume ack with wrong chid %x", id);
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
pc->para.bchannel = id;
} else if (1 == pc->state) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "resume ack without chid (ret %d)", id);
pc->para.cause = 96;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_RESUME_ACKNOWLEDGE);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RESUME | CONFIRM, pc);
newl3state(pc, 10);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
}
static void
l3dss1_resume_rej(struct l3_process *pc, u_char pr, void *arg)
{
struct sk_buff *skb = arg;
int ret;
if ((ret = l3dss1_get_cause(pc, skb))) {
if (pc->debug & L3_DEB_WARN)
l3_debug(pc->st, "RES_REJ get_cause ret(%d)", ret);
if (ret < 0)
pc->para.cause = 96;
else
pc->para.cause = 100;
l3dss1_status_send(pc, pr, NULL);
return;
}
ret = check_infoelements(pc, skb, ie_RESUME_REJECT);
if (ERR_IE_COMPREHENSION == ret) {
l3dss1_std_ie_err(pc, ret);
return;
}
L3DelTimer(&pc->timer);
pc->st->l3.l3l4(pc->st, CC_RESUME_ERR, pc);
newl3state(pc, 0);
if (ret) /* STATUS for none mandatory IE errors after actions are taken */
l3dss1_std_ie_err(pc, ret);
dss1_release_l3_process(pc);
}
static void
l3dss1_global_restart(struct l3_process *pc, u_char pr, void *arg)
{
u_char tmp[32];
u_char *p;
u_char ri, ch = 0, chan = 0;
int l;
struct sk_buff *skb = arg;
struct l3_process *up;
newl3state(pc, 2);
L3DelTimer(&pc->timer);
p = skb->data;
if ((p = findie(p, skb->len, IE_RESTART_IND, 0))) {
ri = p[2];
l3_debug(pc->st, "Restart %x", ri);
} else {
l3_debug(pc->st, "Restart without restart IE");
ri = 0x86;
}
p = skb->data;
if ((p = findie(p, skb->len, IE_CHANNEL_ID, 0))) {
chan = p[2] & 3;
ch = p[2];
if (pc->st->l3.debug)
l3_debug(pc->st, "Restart for channel %d", chan);
}
newl3state(pc, 2);
up = pc->st->l3.proc;
while (up) {
if ((ri & 7) == 7)
up->st->lli.l4l3(up->st, CC_RESTART | REQUEST, up);
else if (up->para.bchannel == chan)
up->st->lli.l4l3(up->st, CC_RESTART | REQUEST, up);
up = up->next;
}
p = tmp;
MsgHead(p, pc->callref, MT_RESTART_ACKNOWLEDGE);
if (chan) {
*p++ = IE_CHANNEL_ID;
*p++ = 1;
*p++ = ch | 0x80;
}
*p++ = 0x79; /* RESTART Ind */
*p++ = 1;
*p++ = ri;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
newl3state(pc, 0);
l3_msg(pc->st, DL_DATA | REQUEST, skb);
}
static void
l3dss1_dl_reset(struct l3_process *pc, u_char pr, void *arg)
{
pc->para.cause = 0x29; /* Temporary failure */
pc->para.loc = 0;
l3dss1_disconnect_req(pc, pr, NULL);
pc->st->l3.l3l4(pc->st, CC_SETUP_ERR, pc);
}
static void
l3dss1_dl_release(struct l3_process *pc, u_char pr, void *arg)
{
newl3state(pc, 0);
pc->para.cause = 0x1b; /* Destination out of order */
pc->para.loc = 0;
pc->st->l3.l3l4(pc->st, CC_RELEASE | INDICATION, pc);
release_l3_process(pc);
}
static void
l3dss1_dl_reestablish(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
L3AddTimer(&pc->timer, T309, CC_T309);
l3_msg(pc->st, DL_ESTABLISH | REQUEST, NULL);
}
static void
l3dss1_dl_reest_status(struct l3_process *pc, u_char pr, void *arg)
{
L3DelTimer(&pc->timer);
pc->para.cause = 0x1F; /* normal, unspecified */
l3dss1_status_send(pc, 0, NULL);
}
/* *INDENT-OFF* */
static struct stateentry downstatelist[] =
{
{SBIT(0),
CC_SETUP | REQUEST, l3dss1_setup_req},
{SBIT(0),
CC_RESUME | REQUEST, l3dss1_resume_req},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(6) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(25),
CC_DISCONNECT | REQUEST, l3dss1_disconnect_req},
{SBIT(12),
CC_RELEASE | REQUEST, l3dss1_release_req},
{ALL_STATES,
CC_RESTART | REQUEST, l3dss1_restart},
{SBIT(6) | SBIT(25),
CC_IGNORE | REQUEST, l3dss1_reset},
{SBIT(6) | SBIT(25),
CC_REJECT | REQUEST, l3dss1_reject_req},
{SBIT(6) | SBIT(25),
CC_PROCEED_SEND | REQUEST, l3dss1_proceed_req},
{SBIT(6),
CC_MORE_INFO | REQUEST, l3dss1_setup_ack_req},
{SBIT(25),
CC_MORE_INFO | REQUEST, l3dss1_dummy},
{SBIT(6) | SBIT(9) | SBIT(25),
CC_ALERTING | REQUEST, l3dss1_alert_req},
{SBIT(6) | SBIT(7) | SBIT(9) | SBIT(25),
CC_SETUP | RESPONSE, l3dss1_setup_rsp},
{SBIT(10),
CC_SUSPEND | REQUEST, l3dss1_suspend_req},
{SBIT(7) | SBIT(9) | SBIT(25),
CC_REDIR | REQUEST, l3dss1_redir_req},
{SBIT(6),
CC_REDIR | REQUEST, l3dss1_redir_req_early},
{SBIT(9) | SBIT(25),
CC_DISCONNECT | REQUEST, l3dss1_disconnect_req},
{SBIT(25),
CC_T302, l3dss1_t302},
{SBIT(1),
CC_T303, l3dss1_t303},
{SBIT(2),
CC_T304, l3dss1_t304},
{SBIT(3),
CC_T310, l3dss1_t310},
{SBIT(8),
CC_T313, l3dss1_t313},
{SBIT(11),
CC_T305, l3dss1_t305},
{SBIT(15),
CC_T319, l3dss1_t319},
{SBIT(17),
CC_T318, l3dss1_t318},
{SBIT(19),
CC_T308_1, l3dss1_t308_1},
{SBIT(19),
CC_T308_2, l3dss1_t308_2},
{SBIT(10),
CC_T309, l3dss1_dl_release},
};
static struct stateentry datastatelist[] =
{
{ALL_STATES,
MT_STATUS_ENQUIRY, l3dss1_status_enq},
{ALL_STATES,
MT_FACILITY, l3dss1_facility},
{SBIT(19),
MT_STATUS, l3dss1_release_ind},
{ALL_STATES,
MT_STATUS, l3dss1_status},
{SBIT(0),
MT_SETUP, l3dss1_setup},
{SBIT(6) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(12) |
SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_SETUP, l3dss1_dummy},
{SBIT(1) | SBIT(2),
MT_CALL_PROCEEDING, l3dss1_call_proc},
{SBIT(1),
MT_SETUP_ACKNOWLEDGE, l3dss1_setup_ack},
{SBIT(2) | SBIT(3),
MT_ALERTING, l3dss1_alerting},
{SBIT(2) | SBIT(3),
MT_PROGRESS, l3dss1_progress},
{SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) |
SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_INFORMATION, l3dss1_information},
{SBIT(10) | SBIT(11) | SBIT(15),
MT_NOTIFY, l3dss1_notify},
{SBIT(0) | SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(10) |
SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(19) | SBIT(25),
MT_RELEASE_COMPLETE, l3dss1_release_cmpl},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(12) | SBIT(15) | SBIT(17) | SBIT(25),
MT_RELEASE, l3dss1_release},
{SBIT(19), MT_RELEASE, l3dss1_release_ind},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4) | SBIT(7) | SBIT(8) | SBIT(9) | SBIT(10) | SBIT(11) | SBIT(15) | SBIT(17) | SBIT(25),
MT_DISCONNECT, l3dss1_disconnect},
{SBIT(19),
MT_DISCONNECT, l3dss1_dummy},
{SBIT(1) | SBIT(2) | SBIT(3) | SBIT(4),
MT_CONNECT, l3dss1_connect},
{SBIT(8),
MT_CONNECT_ACKNOWLEDGE, l3dss1_connect_ack},
{SBIT(15),
MT_SUSPEND_ACKNOWLEDGE, l3dss1_suspend_ack},
{SBIT(15),
MT_SUSPEND_REJECT, l3dss1_suspend_rej},
{SBIT(17),
MT_RESUME_ACKNOWLEDGE, l3dss1_resume_ack},
{SBIT(17),
MT_RESUME_REJECT, l3dss1_resume_rej},
};
static struct stateentry globalmes_list[] =
{
{ALL_STATES,
MT_STATUS, l3dss1_status},
{SBIT(0),
MT_RESTART, l3dss1_global_restart},
/* {SBIT(1),
MT_RESTART_ACKNOWLEDGE, l3dss1_restart_ack},
*/
};
static struct stateentry manstatelist[] =
{
{SBIT(2),
DL_ESTABLISH | INDICATION, l3dss1_dl_reset},
{SBIT(10),
DL_ESTABLISH | CONFIRM, l3dss1_dl_reest_status},
{SBIT(10),
DL_RELEASE | INDICATION, l3dss1_dl_reestablish},
{ALL_STATES,
DL_RELEASE | INDICATION, l3dss1_dl_release},
};
/* *INDENT-ON* */
static void
global_handler(struct PStack *st, int mt, struct sk_buff *skb)
{
u_char tmp[16];
u_char *p = tmp;
int l;
int i;
struct l3_process *proc = st->l3.global;
proc->callref = skb->data[2]; /* cr flag */
for (i = 0; i < ARRAY_SIZE(globalmes_list); i++)
if ((mt == globalmes_list[i].primitive) &&
((1 << proc->state) & globalmes_list[i].state))
break;
if (i == ARRAY_SIZE(globalmes_list)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global state %d mt %x unhandled",
proc->state, mt);
}
MsgHead(p, proc->callref, MT_STATUS);
*p++ = IE_CAUSE;
*p++ = 0x2;
*p++ = 0x80;
*p++ = 81 | 0x80; /* invalid cr */
*p++ = 0x14; /* CallState */
*p++ = 0x1;
*p++ = proc->state & 0x3f;
l = p - tmp;
if (!(skb = l3_alloc_skb(l)))
return;
memcpy(skb_put(skb, l), tmp, l);
l3_msg(proc->st, DL_DATA | REQUEST, skb);
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1 global %d mt %x",
proc->state, mt);
}
globalmes_list[i].rout(proc, mt, skb);
}
}
static void
dss1up(struct PStack *st, int pr, void *arg)
{
int i, mt, cr, callState;
char *ptr;
u_char *p;
struct sk_buff *skb = arg;
struct l3_process *proc;
switch (pr) {
case (DL_DATA | INDICATION):
case (DL_UNIT_DATA | INDICATION):
break;
case (DL_ESTABLISH | CONFIRM):
case (DL_ESTABLISH | INDICATION):
case (DL_RELEASE | INDICATION):
case (DL_RELEASE | CONFIRM):
l3_msg(st, pr, arg);
return;
break;
default:
printk(KERN_ERR "HiSax dss1up unknown pr=%04x\n", pr);
return;
}
if (skb->len < 3) {
l3_debug(st, "dss1up frame too short(%d)", skb->len);
dev_kfree_skb(skb);
return;
}
if (skb->data[0] != PROTO_DIS_EURO) {
if (st->l3.debug & L3_DEB_PROTERR) {
l3_debug(st, "dss1up%sunexpected discriminator %x message len %d",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
skb->data[0], skb->len);
}
dev_kfree_skb(skb);
return;
}
cr = getcallref(skb->data);
if (skb->len < ((skb->data[1] & 0x0f) + 3)) {
l3_debug(st, "dss1up frame too short(%d)", skb->len);
dev_kfree_skb(skb);
return;
}
mt = skb->data[skb->data[1] + 2];
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up cr %d", cr);
if (cr == -2) { /* wrong Callref */
if (st->l3.debug & L3_DEB_WARN)
l3_debug(st, "dss1up wrong Callref");
dev_kfree_skb(skb);
return;
} else if (cr == -1) { /* Dummy Callref */
if (mt == MT_FACILITY)
if ((p = findie(skb->data, skb->len, IE_FACILITY, 0))) {
l3dss1_parse_facility(st, NULL,
(pr == (DL_DATA | INDICATION)) ? -1 : -2, p);
dev_kfree_skb(skb);
return;
}
if (st->l3.debug & L3_DEB_WARN)
l3_debug(st, "dss1up dummy Callref (no facility msg or ie)");
dev_kfree_skb(skb);
return;
} else if ((((skb->data[1] & 0x0f) == 1) && (0 == (cr & 0x7f))) ||
(((skb->data[1] & 0x0f) == 2) && (0 == (cr & 0x7fff)))) { /* Global CallRef */
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up Global CallRef");
global_handler(st, mt, skb);
dev_kfree_skb(skb);
return;
} else if (!(proc = getl3proc(st, cr))) {
/* No transaction process exist, that means no call with
* this callreference is active
*/
if (mt == MT_SETUP) {
/* Setup creates a new transaction process */
if (skb->data[2] & 0x80) {
/* Setup with wrong CREF flag */
if (st->l3.debug & L3_DEB_STATE)
l3_debug(st, "dss1up wrong CRef flag");
dev_kfree_skb(skb);
return;
}
if (!(proc = dss1_new_l3_process(st, cr))) {
/* May be to answer with RELEASE_COMPLETE and
* CAUSE 0x2f "Resource unavailable", but this
* need a new_l3_process too ... arghh
*/
dev_kfree_skb(skb);
return;
}
} else if (mt == MT_STATUS) {
if ((ptr = findie(skb->data, skb->len, IE_CAUSE, 0)) != NULL) {
ptr++;
if (*ptr++ == 2)
ptr++;
}
callState = 0;
if ((ptr = findie(skb->data, skb->len, IE_CALL_STATE, 0)) != NULL) {
ptr++;
if (*ptr++ == 2)
ptr++;
callState = *ptr;
}
/* ETS 300-104 part 2.4.1
* if setup has not been made and a message type
* MT_STATUS is received with call state == 0,
* we must send nothing
*/
if (callState != 0) {
/* ETS 300-104 part 2.4.2
* if setup has not been made and a message type
* MT_STATUS is received with call state != 0,
* we must send MT_RELEASE_COMPLETE cause 101
*/
if ((proc = dss1_new_l3_process(st, cr))) {
proc->para.cause = 101;
l3dss1_msg_without_setup(proc, 0, NULL);
}
}
dev_kfree_skb(skb);
return;
} else if (mt == MT_RELEASE_COMPLETE) {
dev_kfree_skb(skb);
return;
} else {
/* ETS 300-104 part 2
* if setup has not been made and a message type
* (except MT_SETUP and RELEASE_COMPLETE) is received,
* we must send MT_RELEASE_COMPLETE cause 81 */
dev_kfree_skb(skb);
if ((proc = dss1_new_l3_process(st, cr))) {
proc->para.cause = 81;
l3dss1_msg_without_setup(proc, 0, NULL);
}
return;
}
}
if (l3dss1_check_messagetype_validity(proc, mt, skb)) {
dev_kfree_skb(skb);
return;
}
if ((p = findie(skb->data, skb->len, IE_DISPLAY, 0)) != NULL)
l3dss1_deliver_display(proc, pr, p); /* Display IE included */
for (i = 0; i < ARRAY_SIZE(datastatelist); i++)
if ((mt == datastatelist[i].primitive) &&
((1 << proc->state) & datastatelist[i].state))
break;
if (i == ARRAY_SIZE(datastatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %#x unhandled",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
proc->state, mt);
}
if ((MT_RELEASE_COMPLETE != mt) && (MT_RELEASE != mt)) {
proc->para.cause = 101;
l3dss1_status_send(proc, pr, skb);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1up%sstate %d mt %x",
(pr == (DL_DATA | INDICATION)) ? " " : "(broadcast) ",
proc->state, mt);
}
datastatelist[i].rout(proc, pr, skb);
}
dev_kfree_skb(skb);
return;
}
static void
dss1down(struct PStack *st, int pr, void *arg)
{
int i, cr;
struct l3_process *proc;
struct Channel *chan;
if ((DL_ESTABLISH | REQUEST) == pr) {
l3_msg(st, pr, NULL);
return;
} else if (((CC_SETUP | REQUEST) == pr) || ((CC_RESUME | REQUEST) == pr)) {
chan = arg;
cr = newcallref();
cr |= 0x80;
if ((proc = dss1_new_l3_process(st, cr))) {
proc->chan = chan;
chan->proc = proc;
memcpy(&proc->para.setup, &chan->setup, sizeof(setup_parm));
proc->callref = cr;
}
} else {
proc = arg;
}
if (!proc) {
printk(KERN_ERR "HiSax dss1down without proc pr=%04x\n", pr);
return;
}
if (pr == (CC_TDSS1_IO | REQUEST)) {
l3dss1_io_timer(proc); /* timer expires */
return;
}
for (i = 0; i < ARRAY_SIZE(downstatelist); i++)
if ((pr == downstatelist[i].primitive) &&
((1 << proc->state) & downstatelist[i].state))
break;
if (i == ARRAY_SIZE(downstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x unhandled",
proc->state, pr);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "dss1down state %d prim %#x",
proc->state, pr);
}
downstatelist[i].rout(proc, pr, arg);
}
}
static void
dss1man(struct PStack *st, int pr, void *arg)
{
int i;
struct l3_process *proc = arg;
if (!proc) {
printk(KERN_ERR "HiSax dss1man without proc pr=%04x\n", pr);
return;
}
for (i = 0; i < ARRAY_SIZE(manstatelist); i++)
if ((pr == manstatelist[i].primitive) &&
((1 << proc->state) & manstatelist[i].state))
break;
if (i == ARRAY_SIZE(manstatelist)) {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x unhandled",
proc->callref & 0x7f, proc->state, pr);
}
} else {
if (st->l3.debug & L3_DEB_STATE) {
l3_debug(st, "cr %d dss1man state %d prim %#x",
proc->callref & 0x7f, proc->state, pr);
}
manstatelist[i].rout(proc, pr, arg);
}
}
void
setstack_dss1(struct PStack *st)
{
char tmp[64];
int i;
st->lli.l4l3 = dss1down;
st->lli.l4l3_proto = l3dss1_cmd_global;
st->l2.l2l3 = dss1up;
st->l3.l3ml3 = dss1man;
st->l3.N303 = 1;
st->prot.dss1.last_invoke_id = 0;
st->prot.dss1.invoke_used[0] = 1; /* Bit 0 must always be set to 1 */
i = 1;
while (i < 32)
st->prot.dss1.invoke_used[i++] = 0;
if (!(st->l3.global = kmalloc(sizeof(struct l3_process), GFP_ATOMIC))) {
printk(KERN_ERR "HiSax can't get memory for dss1 global CR\n");
} else {
st->l3.global->state = 0;
st->l3.global->callref = 0;
st->l3.global->next = NULL;
st->l3.global->debug = L3_DEB_WARN;
st->l3.global->st = st;
st->l3.global->N303 = 1;
st->l3.global->prot.dss1.invoke_id = 0;
L3InitTimer(st->l3.global, &st->l3.global->timer);
}
strcpy(tmp, dss1_revision);
printk(KERN_INFO "HiSax: DSS1 Rev. %s\n", HiSax_getrev(tmp));
}
| gpl-2.0 |
resin-io/linux | sound/usb/mixer_quirks.c | 82 | 43945 | /*
* USB Audio Driver for ALSA
*
* Quirks and vendor-specific extensions for mixer interfaces
*
* Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
*
* Many codes borrowed from audio.c by
* Alan Cox (alan@lxorguk.ukuu.org.uk)
* Thomas Sailer (sailer@ife.ee.ethz.ch)
*
* Audio Advantage Micro II support added by:
* Przemek Rudy (prudy1@o2.pl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/usb.h>
#include <linux/usb/audio.h>
#include <sound/asoundef.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/hwdep.h>
#include <sound/info.h>
#include "usbaudio.h"
#include "mixer.h"
#include "mixer_quirks.h"
#include "helper.h"
extern struct snd_kcontrol_new *snd_usb_feature_unit_ctl;
struct std_mono_table {
unsigned int unitid, control, cmask;
int val_type;
const char *name;
snd_kcontrol_tlv_rw_t *tlv_callback;
};
/* private_free callback */
static void usb_mixer_elem_free(struct snd_kcontrol *kctl)
{
kfree(kctl->private_data);
kctl->private_data = NULL;
}
/* This function allows for the creation of standard UAC controls.
* See the quirks for M-Audio FTUs or Ebox-44.
* If you don't want to set a TLV callback pass NULL.
*
* Since there doesn't seem to be a devices that needs a multichannel
* version, we keep it mono for simplicity.
*/
static int snd_create_std_mono_ctl_offset(struct usb_mixer_interface *mixer,
unsigned int unitid,
unsigned int control,
unsigned int cmask,
int val_type,
unsigned int idx_off,
const char *name,
snd_kcontrol_tlv_rw_t *tlv_callback)
{
int err;
struct usb_mixer_elem_info *cval;
struct snd_kcontrol *kctl;
cval = kzalloc(sizeof(*cval), GFP_KERNEL);
if (!cval)
return -ENOMEM;
cval->id = unitid;
cval->mixer = mixer;
cval->val_type = val_type;
cval->channels = 1;
cval->control = control;
cval->cmask = cmask;
cval->idx_off = idx_off;
/* get_min_max() is called only for integer volumes later,
* so provide a short-cut for booleans */
cval->min = 0;
cval->max = 1;
cval->res = 0;
cval->dBmin = 0;
cval->dBmax = 0;
/* Create control */
kctl = snd_ctl_new1(snd_usb_feature_unit_ctl, cval);
if (!kctl) {
kfree(cval);
return -ENOMEM;
}
/* Set name */
snprintf(kctl->id.name, sizeof(kctl->id.name), name);
kctl->private_free = usb_mixer_elem_free;
/* set TLV */
if (tlv_callback) {
kctl->tlv.c = tlv_callback;
kctl->vd[0].access |=
SNDRV_CTL_ELEM_ACCESS_TLV_READ |
SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
}
/* Add control to mixer */
err = snd_usb_mixer_add_control(mixer, kctl);
if (err < 0)
return err;
return 0;
}
static int snd_create_std_mono_ctl(struct usb_mixer_interface *mixer,
unsigned int unitid,
unsigned int control,
unsigned int cmask,
int val_type,
const char *name,
snd_kcontrol_tlv_rw_t *tlv_callback)
{
return snd_create_std_mono_ctl_offset(mixer, unitid, control, cmask,
val_type, 0 /* Offset */, name, tlv_callback);
}
/*
* Create a set of standard UAC controls from a table
*/
static int snd_create_std_mono_table(struct usb_mixer_interface *mixer,
struct std_mono_table *t)
{
int err;
while (t->name != NULL) {
err = snd_create_std_mono_ctl(mixer, t->unitid, t->control,
t->cmask, t->val_type, t->name, t->tlv_callback);
if (err < 0)
return err;
t++;
}
return 0;
}
/*
* Sound Blaster remote control configuration
*
* format of remote control data:
* Extigy: xx 00
* Audigy 2 NX: 06 80 xx 00 00 00
* Live! 24-bit: 06 80 xx yy 22 83
*/
static const struct rc_config {
u32 usb_id;
u8 offset;
u8 length;
u8 packet_length;
u8 min_packet_length; /* minimum accepted length of the URB result */
u8 mute_mixer_id;
u32 mute_code;
} rc_configs[] = {
{ USB_ID(0x041e, 0x3000), 0, 1, 2, 1, 18, 0x0013 }, /* Extigy */
{ USB_ID(0x041e, 0x3020), 2, 1, 6, 6, 18, 0x0013 }, /* Audigy 2 NX */
{ USB_ID(0x041e, 0x3040), 2, 2, 6, 6, 2, 0x6e91 }, /* Live! 24-bit */
{ USB_ID(0x041e, 0x3042), 0, 1, 1, 1, 1, 0x000d }, /* Usb X-Fi S51 */
{ USB_ID(0x041e, 0x30df), 0, 1, 1, 1, 1, 0x000d }, /* Usb X-Fi S51 Pro */
{ USB_ID(0x041e, 0x3048), 2, 2, 6, 6, 2, 0x6e91 }, /* Toshiba SB0500 */
};
static void snd_usb_soundblaster_remote_complete(struct urb *urb)
{
struct usb_mixer_interface *mixer = urb->context;
const struct rc_config *rc = mixer->rc_cfg;
u32 code;
if (urb->status < 0 || urb->actual_length < rc->min_packet_length)
return;
code = mixer->rc_buffer[rc->offset];
if (rc->length == 2)
code |= mixer->rc_buffer[rc->offset + 1] << 8;
/* the Mute button actually changes the mixer control */
if (code == rc->mute_code)
snd_usb_mixer_notify_id(mixer, rc->mute_mixer_id);
mixer->rc_code = code;
wmb();
wake_up(&mixer->rc_waitq);
}
static long snd_usb_sbrc_hwdep_read(struct snd_hwdep *hw, char __user *buf,
long count, loff_t *offset)
{
struct usb_mixer_interface *mixer = hw->private_data;
int err;
u32 rc_code;
if (count != 1 && count != 4)
return -EINVAL;
err = wait_event_interruptible(mixer->rc_waitq,
(rc_code = xchg(&mixer->rc_code, 0)) != 0);
if (err == 0) {
if (count == 1)
err = put_user(rc_code, buf);
else
err = put_user(rc_code, (u32 __user *)buf);
}
return err < 0 ? err : count;
}
static unsigned int snd_usb_sbrc_hwdep_poll(struct snd_hwdep *hw, struct file *file,
poll_table *wait)
{
struct usb_mixer_interface *mixer = hw->private_data;
poll_wait(file, &mixer->rc_waitq, wait);
return mixer->rc_code ? POLLIN | POLLRDNORM : 0;
}
static int snd_usb_soundblaster_remote_init(struct usb_mixer_interface *mixer)
{
struct snd_hwdep *hwdep;
int err, len, i;
for (i = 0; i < ARRAY_SIZE(rc_configs); ++i)
if (rc_configs[i].usb_id == mixer->chip->usb_id)
break;
if (i >= ARRAY_SIZE(rc_configs))
return 0;
mixer->rc_cfg = &rc_configs[i];
len = mixer->rc_cfg->packet_length;
init_waitqueue_head(&mixer->rc_waitq);
err = snd_hwdep_new(mixer->chip->card, "SB remote control", 0, &hwdep);
if (err < 0)
return err;
snprintf(hwdep->name, sizeof(hwdep->name),
"%s remote control", mixer->chip->card->shortname);
hwdep->iface = SNDRV_HWDEP_IFACE_SB_RC;
hwdep->private_data = mixer;
hwdep->ops.read = snd_usb_sbrc_hwdep_read;
hwdep->ops.poll = snd_usb_sbrc_hwdep_poll;
hwdep->exclusive = 1;
mixer->rc_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!mixer->rc_urb)
return -ENOMEM;
mixer->rc_setup_packet = kmalloc(sizeof(*mixer->rc_setup_packet), GFP_KERNEL);
if (!mixer->rc_setup_packet) {
usb_free_urb(mixer->rc_urb);
mixer->rc_urb = NULL;
return -ENOMEM;
}
mixer->rc_setup_packet->bRequestType =
USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
mixer->rc_setup_packet->bRequest = UAC_GET_MEM;
mixer->rc_setup_packet->wValue = cpu_to_le16(0);
mixer->rc_setup_packet->wIndex = cpu_to_le16(0);
mixer->rc_setup_packet->wLength = cpu_to_le16(len);
usb_fill_control_urb(mixer->rc_urb, mixer->chip->dev,
usb_rcvctrlpipe(mixer->chip->dev, 0),
(u8*)mixer->rc_setup_packet, mixer->rc_buffer, len,
snd_usb_soundblaster_remote_complete, mixer);
return 0;
}
#define snd_audigy2nx_led_info snd_ctl_boolean_mono_info
static int snd_audigy2nx_led_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
int index = kcontrol->private_value;
ucontrol->value.integer.value[0] = mixer->audigy2nx_leds[index];
return 0;
}
static int snd_audigy2nx_led_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
int index = kcontrol->private_value;
int value = ucontrol->value.integer.value[0];
int err, changed;
if (value > 1)
return -EINVAL;
changed = value != mixer->audigy2nx_leds[index];
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown) {
err = -ENODEV;
goto out;
}
if (mixer->chip->usb_id == USB_ID(0x041e, 0x3042))
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0), 0x24,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
!value, 0, NULL, 0);
/* USB X-Fi S51 Pro */
if (mixer->chip->usb_id == USB_ID(0x041e, 0x30df))
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0), 0x24,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
!value, 0, NULL, 0);
else
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0), 0x24,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
value, index + 2, NULL, 0);
out:
up_read(&mixer->chip->shutdown_rwsem);
if (err < 0)
return err;
mixer->audigy2nx_leds[index] = value;
return changed;
}
static struct snd_kcontrol_new snd_audigy2nx_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "CMSS LED Switch",
.info = snd_audigy2nx_led_info,
.get = snd_audigy2nx_led_get,
.put = snd_audigy2nx_led_put,
.private_value = 0,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Power LED Switch",
.info = snd_audigy2nx_led_info,
.get = snd_audigy2nx_led_get,
.put = snd_audigy2nx_led_put,
.private_value = 1,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Dolby Digital LED Switch",
.info = snd_audigy2nx_led_info,
.get = snd_audigy2nx_led_get,
.put = snd_audigy2nx_led_put,
.private_value = 2,
},
};
static int snd_audigy2nx_controls_create(struct usb_mixer_interface *mixer)
{
int i, err;
for (i = 0; i < ARRAY_SIZE(snd_audigy2nx_controls); ++i) {
/* USB X-Fi S51 doesn't have a CMSS LED */
if ((mixer->chip->usb_id == USB_ID(0x041e, 0x3042)) && i == 0)
continue;
/* USB X-Fi S51 Pro doesn't have one either */
if ((mixer->chip->usb_id == USB_ID(0x041e, 0x30df)) && i == 0)
continue;
if (i > 1 && /* Live24ext has 2 LEDs only */
(mixer->chip->usb_id == USB_ID(0x041e, 0x3040) ||
mixer->chip->usb_id == USB_ID(0x041e, 0x3042) ||
mixer->chip->usb_id == USB_ID(0x041e, 0x30df) ||
mixer->chip->usb_id == USB_ID(0x041e, 0x3048)))
break;
err = snd_ctl_add(mixer->chip->card,
snd_ctl_new1(&snd_audigy2nx_controls[i], mixer));
if (err < 0)
return err;
}
mixer->audigy2nx_leds[1] = 1; /* Power LED is on by default */
return 0;
}
static void snd_audigy2nx_proc_read(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
static const struct sb_jack {
int unitid;
const char *name;
} jacks_audigy2nx[] = {
{4, "dig in "},
{7, "line in"},
{19, "spk out"},
{20, "hph out"},
{-1, NULL}
}, jacks_live24ext[] = {
{4, "line in"}, /* &1=Line, &2=Mic*/
{3, "hph out"}, /* headphones */
{0, "RC "}, /* last command, 6 bytes see rc_config above */
{-1, NULL}
};
const struct sb_jack *jacks;
struct usb_mixer_interface *mixer = entry->private_data;
int i, err;
u8 buf[3];
snd_iprintf(buffer, "%s jacks\n\n", mixer->chip->card->shortname);
if (mixer->chip->usb_id == USB_ID(0x041e, 0x3020))
jacks = jacks_audigy2nx;
else if (mixer->chip->usb_id == USB_ID(0x041e, 0x3040) ||
mixer->chip->usb_id == USB_ID(0x041e, 0x3048))
jacks = jacks_live24ext;
else
return;
for (i = 0; jacks[i].name; ++i) {
snd_iprintf(buffer, "%s: ", jacks[i].name);
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
err = 0;
else
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_rcvctrlpipe(mixer->chip->dev, 0),
UAC_GET_MEM, USB_DIR_IN | USB_TYPE_CLASS |
USB_RECIP_INTERFACE, 0,
jacks[i].unitid << 8, buf, 3);
up_read(&mixer->chip->shutdown_rwsem);
if (err == 3 && (buf[0] == 3 || buf[0] == 6))
snd_iprintf(buffer, "%02x %02x\n", buf[1], buf[2]);
else
snd_iprintf(buffer, "?\n");
}
}
/* EMU0204 */
static int snd_emu0204_ch_switch_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static const char *texts[2] = {"1/2",
"3/4"
};
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 2;
if (uinfo->value.enumerated.item > 1)
uinfo->value.enumerated.item = 1;
strcpy(uinfo->value.enumerated.name,
texts[uinfo->value.enumerated.item]);
return 0;
}
static int snd_emu0204_ch_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.enumerated.item[0] = kcontrol->private_value;
return 0;
}
static int snd_emu0204_ch_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
unsigned int value = ucontrol->value.enumerated.item[0];
int err, changed;
unsigned char buf[2];
if (value > 1)
return -EINVAL;
buf[0] = 0x01;
buf[1] = value ? 0x02 : 0x01;
changed = value != kcontrol->private_value;
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown) {
err = -ENODEV;
goto out;
}
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0), UAC_SET_CUR,
USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_OUT,
0x0400, 0x0e00, buf, 2);
out:
up_read(&mixer->chip->shutdown_rwsem);
if (err < 0)
return err;
kcontrol->private_value = value;
return changed;
}
static struct snd_kcontrol_new snd_emu0204_controls[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Front Jack Channels",
.info = snd_emu0204_ch_switch_info,
.get = snd_emu0204_ch_switch_get,
.put = snd_emu0204_ch_switch_put,
.private_value = 0,
},
};
static int snd_emu0204_controls_create(struct usb_mixer_interface *mixer)
{
int i, err;
for (i = 0; i < ARRAY_SIZE(snd_emu0204_controls); ++i) {
err = snd_ctl_add(mixer->chip->card,
snd_ctl_new1(&snd_emu0204_controls[i], mixer));
if (err < 0)
return err;
}
return 0;
}
/* ASUS Xonar U1 / U3 controls */
static int snd_xonar_u1_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
ucontrol->value.integer.value[0] = !!(mixer->xonar_u1_status & 0x02);
return 0;
}
static int snd_xonar_u1_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
u8 old_status, new_status;
int err, changed;
old_status = mixer->xonar_u1_status;
if (ucontrol->value.integer.value[0])
new_status = old_status | 0x02;
else
new_status = old_status & ~0x02;
changed = new_status != old_status;
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
err = -ENODEV;
else
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0), 0x08,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
50, 0, &new_status, 1);
up_read(&mixer->chip->shutdown_rwsem);
if (err < 0)
return err;
mixer->xonar_u1_status = new_status;
return changed;
}
static struct snd_kcontrol_new snd_xonar_u1_output_switch = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Digital Playback Switch",
.info = snd_ctl_boolean_mono_info,
.get = snd_xonar_u1_switch_get,
.put = snd_xonar_u1_switch_put,
};
static int snd_xonar_u1_controls_create(struct usb_mixer_interface *mixer)
{
int err;
err = snd_ctl_add(mixer->chip->card,
snd_ctl_new1(&snd_xonar_u1_output_switch, mixer));
if (err < 0)
return err;
mixer->xonar_u1_status = 0x05;
return 0;
}
/* Native Instruments device quirks */
#define _MAKE_NI_CONTROL(bRequest,wIndex) ((bRequest) << 16 | (wIndex))
static int snd_nativeinstruments_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
struct usb_device *dev = mixer->chip->dev;
u8 bRequest = (kcontrol->private_value >> 16) & 0xff;
u16 wIndex = kcontrol->private_value & 0xffff;
u8 tmp;
int ret;
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
ret = -ENODEV;
else
ret = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), bRequest,
USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
0, wIndex,
&tmp, sizeof(tmp));
up_read(&mixer->chip->shutdown_rwsem);
if (ret < 0) {
dev_err(&dev->dev,
"unable to issue vendor read request (ret = %d)", ret);
return ret;
}
ucontrol->value.integer.value[0] = tmp;
return 0;
}
static int snd_nativeinstruments_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
struct usb_device *dev = mixer->chip->dev;
u8 bRequest = (kcontrol->private_value >> 16) & 0xff;
u16 wIndex = kcontrol->private_value & 0xffff;
u16 wValue = ucontrol->value.integer.value[0];
int ret;
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
ret = -ENODEV;
else
ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), bRequest,
USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
wValue, wIndex,
NULL, 0, 1000);
up_read(&mixer->chip->shutdown_rwsem);
if (ret < 0) {
dev_err(&dev->dev,
"unable to issue vendor write request (ret = %d)", ret);
return ret;
}
return 0;
}
static struct snd_kcontrol_new snd_nativeinstruments_ta6_mixers[] = {
{
.name = "Direct Thru Channel A",
.private_value = _MAKE_NI_CONTROL(0x01, 0x03),
},
{
.name = "Direct Thru Channel B",
.private_value = _MAKE_NI_CONTROL(0x01, 0x05),
},
{
.name = "Phono Input Channel A",
.private_value = _MAKE_NI_CONTROL(0x02, 0x03),
},
{
.name = "Phono Input Channel B",
.private_value = _MAKE_NI_CONTROL(0x02, 0x05),
},
};
static struct snd_kcontrol_new snd_nativeinstruments_ta10_mixers[] = {
{
.name = "Direct Thru Channel A",
.private_value = _MAKE_NI_CONTROL(0x01, 0x03),
},
{
.name = "Direct Thru Channel B",
.private_value = _MAKE_NI_CONTROL(0x01, 0x05),
},
{
.name = "Direct Thru Channel C",
.private_value = _MAKE_NI_CONTROL(0x01, 0x07),
},
{
.name = "Direct Thru Channel D",
.private_value = _MAKE_NI_CONTROL(0x01, 0x09),
},
{
.name = "Phono Input Channel A",
.private_value = _MAKE_NI_CONTROL(0x02, 0x03),
},
{
.name = "Phono Input Channel B",
.private_value = _MAKE_NI_CONTROL(0x02, 0x05),
},
{
.name = "Phono Input Channel C",
.private_value = _MAKE_NI_CONTROL(0x02, 0x07),
},
{
.name = "Phono Input Channel D",
.private_value = _MAKE_NI_CONTROL(0x02, 0x09),
},
};
static int snd_nativeinstruments_create_mixer(struct usb_mixer_interface *mixer,
const struct snd_kcontrol_new *kc,
unsigned int count)
{
int i, err = 0;
struct snd_kcontrol_new template = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.get = snd_nativeinstruments_control_get,
.put = snd_nativeinstruments_control_put,
.info = snd_ctl_boolean_mono_info,
};
for (i = 0; i < count; i++) {
struct snd_kcontrol *c;
template.name = kc[i].name;
template.private_value = kc[i].private_value;
c = snd_ctl_new1(&template, mixer);
err = snd_ctl_add(mixer->chip->card, c);
if (err < 0)
break;
}
return err;
}
/* M-Audio FastTrack Ultra quirks */
/* FTU Effect switch (also used by C400/C600) */
struct snd_ftu_eff_switch_priv_val {
struct usb_mixer_interface *mixer;
int cached_value;
int is_cached;
int bUnitID;
int validx;
};
static int snd_ftu_eff_switch_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static const char *texts[8] = {"Room 1",
"Room 2",
"Room 3",
"Hall 1",
"Hall 2",
"Plate",
"Delay",
"Echo"
};
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 8;
if (uinfo->value.enumerated.item > 7)
uinfo->value.enumerated.item = 7;
strcpy(uinfo->value.enumerated.name,
texts[uinfo->value.enumerated.item]);
return 0;
}
static int snd_ftu_eff_switch_get(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_usb_audio *chip;
struct usb_mixer_interface *mixer;
struct snd_ftu_eff_switch_priv_val *pval;
int err;
unsigned char value[2];
int id, validx;
const int val_len = 2;
value[0] = 0x00;
value[1] = 0x00;
pval = (struct snd_ftu_eff_switch_priv_val *)
kctl->private_value;
if (pval->is_cached) {
ucontrol->value.enumerated.item[0] = pval->cached_value;
return 0;
}
mixer = (struct usb_mixer_interface *) pval->mixer;
if (snd_BUG_ON(!mixer))
return -EINVAL;
chip = (struct snd_usb_audio *) mixer->chip;
if (snd_BUG_ON(!chip))
return -EINVAL;
id = pval->bUnitID;
validx = pval->validx;
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
err = -ENODEV;
else
err = snd_usb_ctl_msg(chip->dev,
usb_rcvctrlpipe(chip->dev, 0), UAC_GET_CUR,
USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_IN,
validx << 8, snd_usb_ctrl_intf(chip) | (id << 8),
value, val_len);
up_read(&mixer->chip->shutdown_rwsem);
if (err < 0)
return err;
ucontrol->value.enumerated.item[0] = value[0];
pval->cached_value = value[0];
pval->is_cached = 1;
return 0;
}
static int snd_ftu_eff_switch_put(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_usb_audio *chip;
struct snd_ftu_eff_switch_priv_val *pval;
struct usb_mixer_interface *mixer;
int changed, cur_val, err, new_val;
unsigned char value[2];
int id, validx;
const int val_len = 2;
changed = 0;
pval = (struct snd_ftu_eff_switch_priv_val *)
kctl->private_value;
cur_val = pval->cached_value;
new_val = ucontrol->value.enumerated.item[0];
mixer = (struct usb_mixer_interface *) pval->mixer;
if (snd_BUG_ON(!mixer))
return -EINVAL;
chip = (struct snd_usb_audio *) mixer->chip;
if (snd_BUG_ON(!chip))
return -EINVAL;
id = pval->bUnitID;
validx = pval->validx;
if (!pval->is_cached) {
/* Read current value */
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
err = -ENODEV;
else
err = snd_usb_ctl_msg(chip->dev,
usb_rcvctrlpipe(chip->dev, 0), UAC_GET_CUR,
USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_IN,
validx << 8, snd_usb_ctrl_intf(chip) | (id << 8),
value, val_len);
up_read(&mixer->chip->shutdown_rwsem);
if (err < 0)
return err;
cur_val = value[0];
pval->cached_value = cur_val;
pval->is_cached = 1;
}
/* update value if needed */
if (cur_val != new_val) {
value[0] = new_val;
value[1] = 0;
down_read(&mixer->chip->shutdown_rwsem);
if (mixer->chip->shutdown)
err = -ENODEV;
else
err = snd_usb_ctl_msg(chip->dev,
usb_sndctrlpipe(chip->dev, 0), UAC_SET_CUR,
USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_OUT,
validx << 8, snd_usb_ctrl_intf(chip) | (id << 8),
value, val_len);
up_read(&mixer->chip->shutdown_rwsem);
if (err < 0)
return err;
pval->cached_value = new_val;
pval->is_cached = 1;
changed = 1;
}
return changed;
}
static void kctl_private_value_free(struct snd_kcontrol *kctl)
{
kfree((void *)kctl->private_value);
}
static int snd_ftu_create_effect_switch(struct usb_mixer_interface *mixer,
int validx, int bUnitID)
{
static struct snd_kcontrol_new template = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Effect Program Switch",
.index = 0,
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = snd_ftu_eff_switch_info,
.get = snd_ftu_eff_switch_get,
.put = snd_ftu_eff_switch_put
};
int err;
struct snd_kcontrol *kctl;
struct snd_ftu_eff_switch_priv_val *pval;
pval = kzalloc(sizeof(*pval), GFP_KERNEL);
if (!pval)
return -ENOMEM;
pval->cached_value = 0;
pval->is_cached = 0;
pval->mixer = mixer;
pval->bUnitID = bUnitID;
pval->validx = validx;
template.private_value = (unsigned long) pval;
kctl = snd_ctl_new1(&template, mixer->chip);
if (!kctl) {
kfree(pval);
return -ENOMEM;
}
kctl->private_free = kctl_private_value_free;
err = snd_ctl_add(mixer->chip->card, kctl);
if (err < 0)
return err;
return 0;
}
/* Create volume controls for FTU devices*/
static int snd_ftu_create_volume_ctls(struct usb_mixer_interface *mixer)
{
char name[64];
unsigned int control, cmask;
int in, out, err;
const unsigned int id = 5;
const int val_type = USB_MIXER_S16;
for (out = 0; out < 8; out++) {
control = out + 1;
for (in = 0; in < 8; in++) {
cmask = 1 << in;
snprintf(name, sizeof(name),
"AIn%d - Out%d Capture Volume",
in + 1, out + 1);
err = snd_create_std_mono_ctl(mixer, id, control,
cmask, val_type, name,
&snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
for (in = 8; in < 16; in++) {
cmask = 1 << in;
snprintf(name, sizeof(name),
"DIn%d - Out%d Playback Volume",
in - 7, out + 1);
err = snd_create_std_mono_ctl(mixer, id, control,
cmask, val_type, name,
&snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
}
return 0;
}
/* This control needs a volume quirk, see mixer.c */
static int snd_ftu_create_effect_volume_ctl(struct usb_mixer_interface *mixer)
{
static const char name[] = "Effect Volume";
const unsigned int id = 6;
const int val_type = USB_MIXER_U8;
const unsigned int control = 2;
const unsigned int cmask = 0;
return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type,
name, snd_usb_mixer_vol_tlv);
}
/* This control needs a volume quirk, see mixer.c */
static int snd_ftu_create_effect_duration_ctl(struct usb_mixer_interface *mixer)
{
static const char name[] = "Effect Duration";
const unsigned int id = 6;
const int val_type = USB_MIXER_S16;
const unsigned int control = 3;
const unsigned int cmask = 0;
return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type,
name, snd_usb_mixer_vol_tlv);
}
/* This control needs a volume quirk, see mixer.c */
static int snd_ftu_create_effect_feedback_ctl(struct usb_mixer_interface *mixer)
{
static const char name[] = "Effect Feedback Volume";
const unsigned int id = 6;
const int val_type = USB_MIXER_U8;
const unsigned int control = 4;
const unsigned int cmask = 0;
return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type,
name, NULL);
}
static int snd_ftu_create_effect_return_ctls(struct usb_mixer_interface *mixer)
{
unsigned int cmask;
int err, ch;
char name[48];
const unsigned int id = 7;
const int val_type = USB_MIXER_S16;
const unsigned int control = 7;
for (ch = 0; ch < 4; ++ch) {
cmask = 1 << ch;
snprintf(name, sizeof(name),
"Effect Return %d Volume", ch + 1);
err = snd_create_std_mono_ctl(mixer, id, control,
cmask, val_type, name,
snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
return 0;
}
static int snd_ftu_create_effect_send_ctls(struct usb_mixer_interface *mixer)
{
unsigned int cmask;
int err, ch;
char name[48];
const unsigned int id = 5;
const int val_type = USB_MIXER_S16;
const unsigned int control = 9;
for (ch = 0; ch < 8; ++ch) {
cmask = 1 << ch;
snprintf(name, sizeof(name),
"Effect Send AIn%d Volume", ch + 1);
err = snd_create_std_mono_ctl(mixer, id, control, cmask,
val_type, name,
snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
for (ch = 8; ch < 16; ++ch) {
cmask = 1 << ch;
snprintf(name, sizeof(name),
"Effect Send DIn%d Volume", ch - 7);
err = snd_create_std_mono_ctl(mixer, id, control, cmask,
val_type, name,
snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
return 0;
}
static int snd_ftu_create_mixer(struct usb_mixer_interface *mixer)
{
int err;
err = snd_ftu_create_volume_ctls(mixer);
if (err < 0)
return err;
err = snd_ftu_create_effect_switch(mixer, 1, 6);
if (err < 0)
return err;
err = snd_ftu_create_effect_volume_ctl(mixer);
if (err < 0)
return err;
err = snd_ftu_create_effect_duration_ctl(mixer);
if (err < 0)
return err;
err = snd_ftu_create_effect_feedback_ctl(mixer);
if (err < 0)
return err;
err = snd_ftu_create_effect_return_ctls(mixer);
if (err < 0)
return err;
err = snd_ftu_create_effect_send_ctls(mixer);
if (err < 0)
return err;
return 0;
}
void snd_emuusb_set_samplerate(struct snd_usb_audio *chip,
unsigned char samplerate_id)
{
struct usb_mixer_interface *mixer;
struct usb_mixer_elem_info *cval;
int unitid = 12; /* SamleRate ExtensionUnit ID */
list_for_each_entry(mixer, &chip->mixer_list, list) {
cval = mixer->id_elems[unitid];
if (cval) {
snd_usb_mixer_set_ctl_value(cval, UAC_SET_CUR,
cval->control << 8,
samplerate_id);
snd_usb_mixer_notify_id(mixer, unitid);
}
break;
}
}
/* M-Audio Fast Track C400/C600 */
/* C400/C600 volume controls, this control needs a volume quirk, see mixer.c */
static int snd_c400_create_vol_ctls(struct usb_mixer_interface *mixer)
{
char name[64];
unsigned int cmask, offset;
int out, chan, err;
int num_outs = 0;
int num_ins = 0;
const unsigned int id = 0x40;
const int val_type = USB_MIXER_S16;
const int control = 1;
switch (mixer->chip->usb_id) {
case USB_ID(0x0763, 0x2030):
num_outs = 6;
num_ins = 4;
break;
case USB_ID(0x0763, 0x2031):
num_outs = 8;
num_ins = 6;
break;
}
for (chan = 0; chan < num_outs + num_ins; chan++) {
for (out = 0; out < num_outs; out++) {
if (chan < num_outs) {
snprintf(name, sizeof(name),
"PCM%d-Out%d Playback Volume",
chan + 1, out + 1);
} else {
snprintf(name, sizeof(name),
"In%d-Out%d Playback Volume",
chan - num_outs + 1, out + 1);
}
cmask = (out == 0) ? 0 : 1 << (out - 1);
offset = chan * num_outs;
err = snd_create_std_mono_ctl_offset(mixer, id, control,
cmask, val_type, offset, name,
&snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
}
return 0;
}
/* This control needs a volume quirk, see mixer.c */
static int snd_c400_create_effect_volume_ctl(struct usb_mixer_interface *mixer)
{
static const char name[] = "Effect Volume";
const unsigned int id = 0x43;
const int val_type = USB_MIXER_U8;
const unsigned int control = 3;
const unsigned int cmask = 0;
return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type,
name, snd_usb_mixer_vol_tlv);
}
/* This control needs a volume quirk, see mixer.c */
static int snd_c400_create_effect_duration_ctl(struct usb_mixer_interface *mixer)
{
static const char name[] = "Effect Duration";
const unsigned int id = 0x43;
const int val_type = USB_MIXER_S16;
const unsigned int control = 4;
const unsigned int cmask = 0;
return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type,
name, snd_usb_mixer_vol_tlv);
}
/* This control needs a volume quirk, see mixer.c */
static int snd_c400_create_effect_feedback_ctl(struct usb_mixer_interface *mixer)
{
static const char name[] = "Effect Feedback Volume";
const unsigned int id = 0x43;
const int val_type = USB_MIXER_U8;
const unsigned int control = 5;
const unsigned int cmask = 0;
return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type,
name, NULL);
}
static int snd_c400_create_effect_vol_ctls(struct usb_mixer_interface *mixer)
{
char name[64];
unsigned int cmask;
int chan, err;
int num_outs = 0;
int num_ins = 0;
const unsigned int id = 0x42;
const int val_type = USB_MIXER_S16;
const int control = 1;
switch (mixer->chip->usb_id) {
case USB_ID(0x0763, 0x2030):
num_outs = 6;
num_ins = 4;
break;
case USB_ID(0x0763, 0x2031):
num_outs = 8;
num_ins = 6;
break;
}
for (chan = 0; chan < num_outs + num_ins; chan++) {
if (chan < num_outs) {
snprintf(name, sizeof(name),
"Effect Send DOut%d",
chan + 1);
} else {
snprintf(name, sizeof(name),
"Effect Send AIn%d",
chan - num_outs + 1);
}
cmask = (chan == 0) ? 0 : 1 << (chan - 1);
err = snd_create_std_mono_ctl(mixer, id, control,
cmask, val_type, name,
&snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
return 0;
}
static int snd_c400_create_effect_ret_vol_ctls(struct usb_mixer_interface *mixer)
{
char name[64];
unsigned int cmask;
int chan, err;
int num_outs = 0;
int offset = 0;
const unsigned int id = 0x40;
const int val_type = USB_MIXER_S16;
const int control = 1;
switch (mixer->chip->usb_id) {
case USB_ID(0x0763, 0x2030):
num_outs = 6;
offset = 0x3c;
/* { 0x3c, 0x43, 0x3e, 0x45, 0x40, 0x47 } */
break;
case USB_ID(0x0763, 0x2031):
num_outs = 8;
offset = 0x70;
/* { 0x70, 0x79, 0x72, 0x7b, 0x74, 0x7d, 0x76, 0x7f } */
break;
}
for (chan = 0; chan < num_outs; chan++) {
snprintf(name, sizeof(name),
"Effect Return %d",
chan + 1);
cmask = (chan == 0) ? 0 :
1 << (chan + (chan % 2) * num_outs - 1);
err = snd_create_std_mono_ctl_offset(mixer, id, control,
cmask, val_type, offset, name,
&snd_usb_mixer_vol_tlv);
if (err < 0)
return err;
}
return 0;
}
static int snd_c400_create_mixer(struct usb_mixer_interface *mixer)
{
int err;
err = snd_c400_create_vol_ctls(mixer);
if (err < 0)
return err;
err = snd_c400_create_effect_vol_ctls(mixer);
if (err < 0)
return err;
err = snd_c400_create_effect_ret_vol_ctls(mixer);
if (err < 0)
return err;
err = snd_ftu_create_effect_switch(mixer, 2, 0x43);
if (err < 0)
return err;
err = snd_c400_create_effect_volume_ctl(mixer);
if (err < 0)
return err;
err = snd_c400_create_effect_duration_ctl(mixer);
if (err < 0)
return err;
err = snd_c400_create_effect_feedback_ctl(mixer);
if (err < 0)
return err;
return 0;
}
/*
* The mixer units for Ebox-44 are corrupt, and even where they
* are valid they presents mono controls as L and R channels of
* stereo. So we provide a good mixer here.
*/
static struct std_mono_table ebox44_table[] = {
{
.unitid = 4,
.control = 1,
.cmask = 0x0,
.val_type = USB_MIXER_INV_BOOLEAN,
.name = "Headphone Playback Switch"
},
{
.unitid = 4,
.control = 2,
.cmask = 0x1,
.val_type = USB_MIXER_S16,
.name = "Headphone A Mix Playback Volume"
},
{
.unitid = 4,
.control = 2,
.cmask = 0x2,
.val_type = USB_MIXER_S16,
.name = "Headphone B Mix Playback Volume"
},
{
.unitid = 7,
.control = 1,
.cmask = 0x0,
.val_type = USB_MIXER_INV_BOOLEAN,
.name = "Output Playback Switch"
},
{
.unitid = 7,
.control = 2,
.cmask = 0x1,
.val_type = USB_MIXER_S16,
.name = "Output A Playback Volume"
},
{
.unitid = 7,
.control = 2,
.cmask = 0x2,
.val_type = USB_MIXER_S16,
.name = "Output B Playback Volume"
},
{
.unitid = 10,
.control = 1,
.cmask = 0x0,
.val_type = USB_MIXER_INV_BOOLEAN,
.name = "Input Capture Switch"
},
{
.unitid = 10,
.control = 2,
.cmask = 0x1,
.val_type = USB_MIXER_S16,
.name = "Input A Capture Volume"
},
{
.unitid = 10,
.control = 2,
.cmask = 0x2,
.val_type = USB_MIXER_S16,
.name = "Input B Capture Volume"
},
{}
};
/* Audio Advantage Micro II findings:
*
* Mapping spdif AES bits to vendor register.bit:
* AES0: [0 0 0 0 2.3 2.2 2.1 2.0] - default 0x00
* AES1: [3.3 3.2.3.1.3.0 2.7 2.6 2.5 2.4] - default: 0x01
* AES2: [0 0 0 0 0 0 0 0]
* AES3: [0 0 0 0 0 0 x 0] - 'x' bit is set basing on standard usb request
* (UAC_EP_CS_ATTR_SAMPLE_RATE) for Audio Devices
*
* power on values:
* r2: 0x10
* r3: 0x20 (b7 is zeroed just before playback (except IEC61937) and set
* just after it to 0xa0, presumably it disables/mutes some analog
* parts when there is no audio.)
* r9: 0x28
*
* Optical transmitter on/off:
* vendor register.bit: 9.1
* 0 - on (0x28 register value)
* 1 - off (0x2a register value)
*
*/
static int snd_microii_spdif_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int snd_microii_spdif_default_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
int err;
struct usb_interface *iface;
struct usb_host_interface *alts;
unsigned int ep;
unsigned char data[3];
int rate;
ucontrol->value.iec958.status[0] = kcontrol->private_value & 0xff;
ucontrol->value.iec958.status[1] = (kcontrol->private_value >> 8) & 0xff;
ucontrol->value.iec958.status[2] = 0x00;
/* use known values for that card: interface#1 altsetting#1 */
iface = usb_ifnum_to_if(mixer->chip->dev, 1);
alts = &iface->altsetting[1];
ep = get_endpoint(alts, 0)->bEndpointAddress;
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_rcvctrlpipe(mixer->chip->dev, 0),
UAC_GET_CUR,
USB_TYPE_CLASS | USB_RECIP_ENDPOINT | USB_DIR_IN,
UAC_EP_CS_ATTR_SAMPLE_RATE << 8,
ep,
data,
sizeof(data));
if (err < 0)
goto end;
rate = data[0] | (data[1] << 8) | (data[2] << 16);
ucontrol->value.iec958.status[3] = (rate == 48000) ?
IEC958_AES3_CON_FS_48000 : IEC958_AES3_CON_FS_44100;
err = 0;
end:
return err;
}
static int snd_microii_spdif_default_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
int err;
u8 reg;
unsigned long priv_backup = kcontrol->private_value;
reg = ((ucontrol->value.iec958.status[1] & 0x0f) << 4) |
(ucontrol->value.iec958.status[0] & 0x0f);
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0),
UAC_SET_CUR,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
reg,
2,
NULL,
0);
if (err < 0)
goto end;
kcontrol->private_value &= 0xfffff0f0;
kcontrol->private_value |= (ucontrol->value.iec958.status[1] & 0x0f) << 8;
kcontrol->private_value |= (ucontrol->value.iec958.status[0] & 0x0f);
reg = (ucontrol->value.iec958.status[0] & IEC958_AES0_NONAUDIO) ?
0xa0 : 0x20;
reg |= (ucontrol->value.iec958.status[1] >> 4) & 0x0f;
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0),
UAC_SET_CUR,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
reg,
3,
NULL,
0);
if (err < 0)
goto end;
kcontrol->private_value &= 0xffff0fff;
kcontrol->private_value |= (ucontrol->value.iec958.status[1] & 0xf0) << 8;
/* The frequency bits in AES3 cannot be set via register access. */
/* Silently ignore any bits from the request that cannot be set. */
err = (priv_backup != kcontrol->private_value);
end:
return err;
}
static int snd_microii_spdif_mask_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.iec958.status[0] = 0x0f;
ucontrol->value.iec958.status[1] = 0xff;
ucontrol->value.iec958.status[2] = 0x00;
ucontrol->value.iec958.status[3] = 0x00;
return 0;
}
static int snd_microii_spdif_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = !(kcontrol->private_value & 0x02);
return 0;
}
static int snd_microii_spdif_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct usb_mixer_interface *mixer = snd_kcontrol_chip(kcontrol);
int err;
u8 reg = ucontrol->value.integer.value[0] ? 0x28 : 0x2a;
err = snd_usb_ctl_msg(mixer->chip->dev,
usb_sndctrlpipe(mixer->chip->dev, 0),
UAC_SET_CUR,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
reg,
9,
NULL,
0);
if (!err) {
err = (reg != (kcontrol->private_value & 0x0ff));
if (err)
kcontrol->private_value = reg;
}
return err;
}
static struct snd_kcontrol_new snd_microii_mixer_spdif[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.info = snd_microii_spdif_info,
.get = snd_microii_spdif_default_get,
.put = snd_microii_spdif_default_put,
.private_value = 0x00000100UL,/* reset value */
},
{
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
.info = snd_microii_spdif_info,
.get = snd_microii_spdif_mask_get,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH),
.info = snd_ctl_boolean_mono_info,
.get = snd_microii_spdif_switch_get,
.put = snd_microii_spdif_switch_put,
.private_value = 0x00000028UL,/* reset value */
}
};
static int snd_microii_controls_create(struct usb_mixer_interface *mixer)
{
int err, i;
for (i = 0; i < ARRAY_SIZE(snd_microii_mixer_spdif); ++i) {
err = snd_ctl_add(mixer->chip->card,
snd_ctl_new1(&snd_microii_mixer_spdif[i], mixer));
if (err < 0)
return err;
}
return 0;
}
int snd_usb_mixer_apply_create_quirk(struct usb_mixer_interface *mixer)
{
int err = 0;
struct snd_info_entry *entry;
if ((err = snd_usb_soundblaster_remote_init(mixer)) < 0)
return err;
switch (mixer->chip->usb_id) {
case USB_ID(0x041e, 0x3020):
case USB_ID(0x041e, 0x3040):
case USB_ID(0x041e, 0x3042):
case USB_ID(0x041e, 0x30df):
case USB_ID(0x041e, 0x3048):
err = snd_audigy2nx_controls_create(mixer);
if (err < 0)
break;
if (!snd_card_proc_new(mixer->chip->card, "audigy2nx", &entry))
snd_info_set_text_ops(entry, mixer,
snd_audigy2nx_proc_read);
break;
/* EMU0204 */
case USB_ID(0x041e, 0x3f19):
err = snd_emu0204_controls_create(mixer);
if (err < 0)
break;
break;
case USB_ID(0x0763, 0x2030): /* M-Audio Fast Track C400 */
case USB_ID(0x0763, 0x2031): /* M-Audio Fast Track C400 */
err = snd_c400_create_mixer(mixer);
break;
case USB_ID(0x0763, 0x2080): /* M-Audio Fast Track Ultra */
case USB_ID(0x0763, 0x2081): /* M-Audio Fast Track Ultra 8R */
err = snd_ftu_create_mixer(mixer);
break;
case USB_ID(0x0b05, 0x1739): /* ASUS Xonar U1 */
case USB_ID(0x0b05, 0x1743): /* ASUS Xonar U1 (2) */
case USB_ID(0x0b05, 0x17a0): /* ASUS Xonar U3 */
err = snd_xonar_u1_controls_create(mixer);
break;
case USB_ID(0x0d8c, 0x0103): /* Audio Advantage Micro II */
err = snd_microii_controls_create(mixer);
break;
case USB_ID(0x17cc, 0x1011): /* Traktor Audio 6 */
err = snd_nativeinstruments_create_mixer(mixer,
snd_nativeinstruments_ta6_mixers,
ARRAY_SIZE(snd_nativeinstruments_ta6_mixers));
break;
case USB_ID(0x17cc, 0x1021): /* Traktor Audio 10 */
err = snd_nativeinstruments_create_mixer(mixer,
snd_nativeinstruments_ta10_mixers,
ARRAY_SIZE(snd_nativeinstruments_ta10_mixers));
break;
case USB_ID(0x200c, 0x1018): /* Electrix Ebox-44 */
/* detection is disabled in mixer_maps.c */
err = snd_create_std_mono_table(mixer, ebox44_table);
break;
}
return err;
}
void snd_usb_mixer_rc_memory_change(struct usb_mixer_interface *mixer,
int unitid)
{
if (!mixer->rc_cfg)
return;
/* unit ids specific to Extigy/Audigy 2 NX: */
switch (unitid) {
case 0: /* remote control */
mixer->rc_urb->dev = mixer->chip->dev;
usb_submit_urb(mixer->rc_urb, GFP_ATOMIC);
break;
case 4: /* digital in jack */
case 7: /* line in jacks */
case 19: /* speaker out jacks */
case 20: /* headphones out jack */
break;
/* live24ext: 4 = line-in jack */
case 3: /* hp-out jack (may actuate Mute) */
if (mixer->chip->usb_id == USB_ID(0x041e, 0x3040) ||
mixer->chip->usb_id == USB_ID(0x041e, 0x3048))
snd_usb_mixer_notify_id(mixer, mixer->rc_cfg->mute_mixer_id);
break;
default:
usb_audio_dbg(mixer->chip, "memory change in unknown unit %d\n", unitid);
break;
}
}
| gpl-2.0 |
sensarliar/zfcs_uboot | arch/powerpc/cpu/mpc8xx/cpu.c | 82 | 16148 | /*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* m8xx.c
*
* CPU specific code
*
* written or collected and sometimes rewritten by
* Magnus Damm <damm@bitsmart.com>
*
* minor modifications by
* Wolfgang Denk <wd@denx.de>
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <netdev.h>
#include <asm/cache.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
static char *cpu_warning = "\n " \
"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
!defined(CONFIG_MPC862))
static int check_CPU (long clock, uint pvr, uint immr)
{
char *id_str =
# if defined(CONFIG_MPC855)
"PC855";
# elif defined(CONFIG_MPC860P)
"PC860P";
# else
NULL;
# endif
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
char pre = 'X';
char *mid = "xx";
char *suf;
/* the highest 16 bits should be 0x0050 for a 860 */
if ((pvr >> 16) != 0x0050)
return -1;
k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
m = 0;
suf = "";
/*
* Some boards use sockets so different CPUs can be used.
* We have to check chip version in run time.
*/
switch (k) {
case 0x00020001: pre = 'P'; break;
case 0x00030001: break;
case 0x00120003: suf = "A"; break;
case 0x00130003: suf = "A3"; break;
case 0x00200004: suf = "B"; break;
case 0x00300004: suf = "C"; break;
case 0x00310004: suf = "C1"; m = 1; break;
case 0x00200064: mid = "SR"; suf = "B"; break;
case 0x00300065: mid = "SR"; suf = "C"; break;
case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
case 0x05010000: suf = "D3"; m = 1; break;
case 0x05020000: suf = "D4"; m = 1; break;
/* this value is not documented anywhere */
case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
case 0x08010004: /* Rev. A.0 */
suf = "A";
/* fall through */
case 0x08000003: /* Rev. 0.3 */
pre = 'M'; m = 1;
if (id_str == NULL)
id_str =
# if defined(CONFIG_MPC852T)
"PC852T";
# elif defined(CONFIG_MPC859T)
"PC859T";
# elif defined(CONFIG_MPC859DSL)
"PC859DSL";
# elif defined(CONFIG_MPC866T)
"PC866T";
# else
"PC866x"; /* Unknown chip from MPC866 family */
# endif
break;
case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
if (id_str == NULL)
id_str = "PC885"; /* 870/875/880/885 */
break;
default: suf = NULL; break;
}
if (id_str == NULL)
id_str = "PC86x"; /* Unknown 86x chip */
if (suf)
printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
else
printf ("unknown M%s (0x%08x)", id_str, k);
#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
strmhz (buf, clock),
CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
);
#else
printf (" at %s MHz: ", strmhz (buf, clock));
#endif
printf ("%u kB I-Cache %u kB D-Cache",
checkicache () >> 10,
checkdcache () >> 10
);
/* do we have a FEC (860T/P or 852/859/866/885)? */
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
printf (" FEC present");
}
if (!m) {
puts (cpu_warning);
}
putc ('\n');
#ifdef DEBUG
if(clock != measure_gclk()) {
printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
}
#endif
return 0;
}
#elif defined(CONFIG_MPC862)
static int check_CPU (long clock, uint pvr, uint immr)
{
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
char pre = 'X';
char *mid = "xx";
char *suf;
/* the highest 16 bits should be 0x0050 for a 8xx */
if ((pvr >> 16) != 0x0050)
return -1;
k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
m = 0;
switch (k) {
/* this value is not documented anywhere */
case 0x06000000: mid = "P"; suf = "0"; break;
case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
default: suf = NULL; break;
}
#ifndef CONFIG_MPC857
if (suf)
printf ("%cPC862%sZPnn%s", pre, mid, suf);
else
printf ("unknown MPC862 (0x%08x)", k);
#else
if (suf)
printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
else
printf ("unknown MPC857 (0x%08x)", k);
#endif
printf (" at %s MHz:", strmhz (buf, clock));
printf (" %u kB I-Cache", checkicache () >> 10);
printf (" %u kB D-Cache", checkdcache () >> 10);
/* lets check and see if we're running on a 862T (or P?) */
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
printf (" FEC present");
}
if (!m) {
puts (cpu_warning);
}
putc ('\n');
return 0;
}
#elif defined(CONFIG_MPC823)
static int check_CPU (long clock, uint pvr, uint immr)
{
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
char *suf;
/* the highest 16 bits should be 0x0050 for a 8xx */
if ((pvr >> 16) != 0x0050)
return -1;
k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
m = 0;
switch (k) {
/* MPC823 */
case 0x20000000: suf = "0"; break;
case 0x20010000: suf = "0.1"; break;
case 0x20020000: suf = "Z2/3"; break;
case 0x20020001: suf = "Z3"; break;
case 0x21000000: suf = "A"; break;
case 0x21010000: suf = "B"; m = 1; break;
case 0x21010001: suf = "B2"; m = 1; break;
/* MPC823E */
case 0x24010000: suf = NULL;
puts ("PPC823EZTnnB2");
m = 1;
break;
default:
suf = NULL;
printf ("unknown MPC823 (0x%08x)", k);
break;
}
if (suf)
printf ("PPC823ZTnn%s", suf);
printf (" at %s MHz:", strmhz (buf, clock));
printf (" %u kB I-Cache", checkicache () >> 10);
printf (" %u kB D-Cache", checkdcache () >> 10);
/* lets check and see if we're running on a 860T (or P?) */
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
puts (" FEC present");
}
if (!m) {
puts (cpu_warning);
}
putc ('\n');
return 0;
}
#elif defined(CONFIG_MPC850)
static int check_CPU (long clock, uint pvr, uint immr)
{
volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
uint k, m;
char buf[32];
/* the highest 16 bits should be 0x0050 for a 8xx */
if ((pvr >> 16) != 0x0050)
return -1;
k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
m = 0;
switch (k) {
case 0x20020001:
printf ("XPC850xxZT");
break;
case 0x21000065:
printf ("XPC850xxZTA");
break;
case 0x21010067:
printf ("XPC850xxZTB");
m = 1;
break;
case 0x21020068:
printf ("XPC850xxZTC");
m = 1;
break;
default:
printf ("unknown MPC850 (0x%08x)", k);
}
printf (" at %s MHz:", strmhz (buf, clock));
printf (" %u kB I-Cache", checkicache () >> 10);
printf (" %u kB D-Cache", checkdcache () >> 10);
/* lets check and see if we're running on a 850T (or P?) */
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
printf (" FEC present");
}
if (!m) {
puts (cpu_warning);
}
putc ('\n');
return 0;
}
#else
#error CPU undefined
#endif
/* ------------------------------------------------------------------------- */
int checkcpu (void)
{
ulong clock = gd->cpu_clk;
uint immr = get_immr (0); /* Return full IMMR contents */
uint pvr = get_pvr ();
puts ("CPU: ");
/* 850 has PARTNUM 20 */
/* 801 has PARTNUM 10 */
return check_CPU (clock, pvr, immr);
}
/* ------------------------------------------------------------------------- */
/* L1 i-cache */
/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
int checkicache (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;
#ifdef CONFIG_IP86x
u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
#endif
u32 m;
u32 lines = -1;
wr_ic_cst (IDC_UNALL);
wr_ic_cst (IDC_INVALL);
wr_ic_cst (IDC_DISABLE);
__asm__ volatile ("isync");
while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
wr_ic_adr (k);
wr_ic_cst (IDC_LDLCK);
__asm__ volatile ("isync");
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
wr_ic_cst (IDC_UNALL);
wr_ic_cst (IDC_INVALL);
if (cacheon)
wr_ic_cst (IDC_ENABLE);
else
wr_ic_cst (IDC_DISABLE);
__asm__ volatile ("isync");
return lines << 4;
};
/* ------------------------------------------------------------------------- */
/* L1 d-cache */
/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
/* call with cache disabled */
int checkdcache (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;
#ifdef CONFIG_IP86x
u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
#endif
u32 m;
u32 lines = -1;
wr_dc_cst (IDC_UNALL);
wr_dc_cst (IDC_INVALL);
wr_dc_cst (IDC_DISABLE);
while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
wr_dc_adr (k);
wr_dc_cst (IDC_LDLCK);
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
wr_dc_cst (IDC_UNALL);
wr_dc_cst (IDC_INVALL);
if (cacheon)
wr_dc_cst (IDC_ENABLE);
else
wr_dc_cst (IDC_DISABLE);
return lines << 4;
};
/* ------------------------------------------------------------------------- */
void upmconfig (uint upm, uint * table, uint size)
{
uint i;
uint addr = 0;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
for (i = 0; i < size; i++) {
memctl->memc_mdr = table[i]; /* (16-15) */
memctl->memc_mcr = addr | upm; /* (16-16) */
addr++;
}
}
/* ------------------------------------------------------------------------- */
#ifndef CONFIG_LWMON
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
/* Interrupts and MMU off */
__asm__ volatile ("mtspr 81, 0");
__asm__ volatile ("mfmsr %0":"=r" (msr));
msr &= ~0x1030;
__asm__ volatile ("mtmsr %0"::"r" (msr));
/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
#ifdef CONFIG_SYS_RESET_ADDRESS
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
* - sizeof (ulong) is usually a valid address. Better pick an address
* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
}
#else /* CONFIG_LWMON */
/*
* On the LWMON board, the MCLR reset input of the PIC's on the board
* uses a 47K/1n RC combination which has a 47us time constant. The
* low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
* and thus too short to reset the external hardware. So we use the
* watchdog to reset the board.
*/
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* prevent triggering the watchdog */
disable_interrupts ();
/* make sure the watchdog is running */
reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
/* wait for watchdog reset */
while (1) {};
/* NOTREACHED */
return 1;
}
#endif /* CONFIG_LWMON */
/* ------------------------------------------------------------------------- */
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*
* See sections 14.2 and 14.6 of the User's Manual
*/
unsigned long get_tbclk (void)
{
uint immr = get_immr (0); /* Return full IMMR contents */
volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
ulong oscclk, factor, pll;
if (immap->im_clkrst.car_sccr & SCCR_TBS) {
return (gd->cpu_clk / 16);
}
pll = immap->im_clkrst.car_plprcr;
#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
/*
* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
* factor is calculated as follows:
*
* MFN
* MFI + -------
* MFD + 1
* factor = -----------------
* (PDF + 1) * 2^S
*
* For older chips, it's just MF field of PLPRCR plus one.
*/
if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
} else {
factor = PLPRCR_val(MF)+1;
}
oscclk = gd->cpu_clk / factor;
if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
return (oscclk / 4);
}
return (oscclk / 16);
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
void reset_8xx_watchdog (volatile immap_t * immr)
{
# if defined(CONFIG_LWMON)
/*
* The LWMON board uses a MAX6301 Watchdog
* with the trigger pin connected to port PA.7
*
* (The old board version used a MAX706TESA Watchdog, which
* had to be handled exactly the same.)
*/
# define WATCHDOG_BIT 0x0100
immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
/*
* The KUP4 boards uses a TPS3705 Watchdog
* with the trigger pin connected to port PA.5
*/
# define WATCHDOG_BIT 0x0400
immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
# else
/*
* All other boards use the MPC8xx Internal Watchdog
*/
immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
# endif /* CONFIG_LWMON */
}
#endif /* CONFIG_WATCHDOG */
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis)
{
#if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
scc_initialize(bis);
#endif
#if defined(FEC_ENET)
fec_initialize(bis);
#endif
return 0;
}
| gpl-2.0 |
matanb10/linux | drivers/net/ethernet/lantiq_etop.c | 82 | 18485 | /*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*
* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <linux/in.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/phy.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/ethtool.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <asm/checksum.h>
#include <lantiq_soc.h>
#include <xway_dma.h>
#include <lantiq_platform.h>
#define LTQ_ETOP_MDIO 0x11804
#define MDIO_REQUEST 0x80000000
#define MDIO_READ 0x40000000
#define MDIO_ADDR_MASK 0x1f
#define MDIO_ADDR_OFFSET 0x15
#define MDIO_REG_MASK 0x1f
#define MDIO_REG_OFFSET 0x10
#define MDIO_VAL_MASK 0xffff
#define PPE32_CGEN 0x800
#define LQ_PPE32_ENET_MAC_CFG 0x1840
#define LTQ_ETOP_ENETS0 0x11850
#define LTQ_ETOP_MAC_DA0 0x1186C
#define LTQ_ETOP_MAC_DA1 0x11870
#define LTQ_ETOP_CFG 0x16020
#define LTQ_ETOP_IGPLEN 0x16080
#define MAX_DMA_CHAN 0x8
#define MAX_DMA_CRC_LEN 0x4
#define MAX_DMA_DATA_LEN 0x600
#define ETOP_FTCU BIT(28)
#define ETOP_MII_MASK 0xf
#define ETOP_MII_NORMAL 0xd
#define ETOP_MII_REVERSE 0xe
#define ETOP_PLEN_UNDER 0x40
#define ETOP_CGEN 0x800
/* use 2 static channels for TX/RX */
#define LTQ_ETOP_TX_CHANNEL 1
#define LTQ_ETOP_RX_CHANNEL 6
#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
#define ltq_etop_w32_mask(x, y, z) \
ltq_w32_mask(x, y, ltq_etop_membase + (z))
#define DRV_VERSION "1.0"
static void __iomem *ltq_etop_membase;
struct ltq_etop_chan {
int idx;
int tx_free;
struct net_device *netdev;
struct napi_struct napi;
struct ltq_dma_channel dma;
struct sk_buff *skb[LTQ_DESC_NUM];
};
struct ltq_etop_priv {
struct net_device *netdev;
struct platform_device *pdev;
struct ltq_eth_data *pldata;
struct resource *res;
struct mii_bus *mii_bus;
struct ltq_etop_chan ch[MAX_DMA_CHAN];
int tx_free[MAX_DMA_CHAN >> 1];
spinlock_t lock;
};
static int
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
{
ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
if (!ch->skb[ch->dma.desc])
return -ENOMEM;
ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
DMA_FROM_DEVICE);
ch->dma.desc_base[ch->dma.desc].addr =
CPHYSADDR(ch->skb[ch->dma.desc]->data);
ch->dma.desc_base[ch->dma.desc].ctl =
LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
MAX_DMA_DATA_LEN;
skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
return 0;
}
static void
ltq_etop_hw_receive(struct ltq_etop_chan *ch)
{
struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
struct sk_buff *skb = ch->skb[ch->dma.desc];
int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
if (ltq_etop_alloc_skb(ch)) {
netdev_err(ch->netdev,
"failed to allocate new rx buffer, stopping DMA\n");
ltq_dma_close(&ch->dma);
}
ch->dma.desc++;
ch->dma.desc %= LTQ_DESC_NUM;
spin_unlock_irqrestore(&priv->lock, flags);
skb_put(skb, len);
skb->protocol = eth_type_trans(skb, ch->netdev);
netif_receive_skb(skb);
}
static int
ltq_etop_poll_rx(struct napi_struct *napi, int budget)
{
struct ltq_etop_chan *ch = container_of(napi,
struct ltq_etop_chan, napi);
int rx = 0;
int complete = 0;
while ((rx < budget) && !complete) {
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
ltq_etop_hw_receive(ch);
rx++;
} else {
complete = 1;
}
}
if (complete || !rx) {
napi_complete(&ch->napi);
ltq_dma_ack_irq(&ch->dma);
}
return rx;
}
static int
ltq_etop_poll_tx(struct napi_struct *napi, int budget)
{
struct ltq_etop_chan *ch =
container_of(napi, struct ltq_etop_chan, napi);
struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
struct netdev_queue *txq =
netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
while ((ch->dma.desc_base[ch->tx_free].ctl &
(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
dev_kfree_skb_any(ch->skb[ch->tx_free]);
ch->skb[ch->tx_free] = NULL;
memset(&ch->dma.desc_base[ch->tx_free], 0,
sizeof(struct ltq_dma_desc));
ch->tx_free++;
ch->tx_free %= LTQ_DESC_NUM;
}
spin_unlock_irqrestore(&priv->lock, flags);
if (netif_tx_queue_stopped(txq))
netif_tx_start_queue(txq);
napi_complete(&ch->napi);
ltq_dma_ack_irq(&ch->dma);
return 1;
}
static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
struct ltq_etop_priv *priv = _priv;
int ch = irq - LTQ_DMA_CH0_INT;
napi_schedule(&priv->ch[ch].napi);
return IRQ_HANDLED;
}
static void
ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
ltq_dma_free(&ch->dma);
if (ch->dma.irq)
free_irq(ch->dma.irq, priv);
if (IS_RX(ch->idx)) {
int desc;
for (desc = 0; desc < LTQ_DESC_NUM; desc++)
dev_kfree_skb_any(ch->skb[ch->dma.desc]);
}
}
static void
ltq_etop_hw_exit(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
int i;
ltq_pmu_disable(PMU_PPE);
for (i = 0; i < MAX_DMA_CHAN; i++)
if (IS_TX(i) || IS_RX(i))
ltq_etop_free_channel(dev, &priv->ch[i]);
}
static int
ltq_etop_hw_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
int i;
ltq_pmu_enable(PMU_PPE);
switch (priv->pldata->mii_mode) {
case PHY_INTERFACE_MODE_RMII:
ltq_etop_w32_mask(ETOP_MII_MASK,
ETOP_MII_REVERSE, LTQ_ETOP_CFG);
break;
case PHY_INTERFACE_MODE_MII:
ltq_etop_w32_mask(ETOP_MII_MASK,
ETOP_MII_NORMAL, LTQ_ETOP_CFG);
break;
default:
netdev_err(dev, "unknown mii mode %d\n",
priv->pldata->mii_mode);
return -ENOTSUPP;
}
/* enable crc generation */
ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
ltq_dma_init_port(DMA_PORT_ETOP);
for (i = 0; i < MAX_DMA_CHAN; i++) {
int irq = LTQ_DMA_CH0_INT + i;
struct ltq_etop_chan *ch = &priv->ch[i];
ch->idx = ch->dma.nr = i;
if (IS_TX(i)) {
ltq_dma_alloc_tx(&ch->dma);
request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
} else if (IS_RX(i)) {
ltq_dma_alloc_rx(&ch->dma);
for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
ch->dma.desc++)
if (ltq_etop_alloc_skb(ch))
return -ENOMEM;
ch->dma.desc = 0;
request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
}
ch->dma.irq = irq;
}
return 0;
}
static void
ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
strlcpy(info->version, DRV_VERSION, sizeof(info->version));
}
static int
ltq_etop_nway_reset(struct net_device *dev)
{
return phy_start_aneg(dev->phydev);
}
static const struct ethtool_ops ltq_etop_ethtool_ops = {
.get_drvinfo = ltq_etop_get_drvinfo,
.nway_reset = ltq_etop_nway_reset,
.get_link_ksettings = phy_ethtool_get_link_ksettings,
.set_link_ksettings = phy_ethtool_set_link_ksettings,
};
static int
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
u32 val = MDIO_REQUEST |
((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
phy_data;
while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
;
ltq_etop_w32(val, LTQ_ETOP_MDIO);
return 0;
}
static int
ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
{
u32 val = MDIO_REQUEST | MDIO_READ |
((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
;
ltq_etop_w32(val, LTQ_ETOP_MDIO);
while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
;
val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
return val;
}
static void
ltq_etop_mdio_link(struct net_device *dev)
{
/* nothing to do */
}
static int
ltq_etop_mdio_probe(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
struct phy_device *phydev;
phydev = phy_find_first(priv->mii_bus);
if (!phydev) {
netdev_err(dev, "no PHY found\n");
return -ENODEV;
}
phydev = phy_connect(dev, phydev_name(phydev),
<q_etop_mdio_link, priv->pldata->mii_mode);
if (IS_ERR(phydev)) {
netdev_err(dev, "Could not attach to PHY\n");
return PTR_ERR(phydev);
}
phydev->supported &= (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
| SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_MII
| SUPPORTED_TP);
phydev->advertising = phydev->supported;
phy_attached_info(phydev);
return 0;
}
static int
ltq_etop_mdio_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
int err;
priv->mii_bus = mdiobus_alloc();
if (!priv->mii_bus) {
netdev_err(dev, "failed to allocate mii bus\n");
err = -ENOMEM;
goto err_out;
}
priv->mii_bus->priv = dev;
priv->mii_bus->read = ltq_etop_mdio_rd;
priv->mii_bus->write = ltq_etop_mdio_wr;
priv->mii_bus->name = "ltq_mii";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
priv->pdev->name, priv->pdev->id);
if (mdiobus_register(priv->mii_bus)) {
err = -ENXIO;
goto err_out_free_mdiobus;
}
if (ltq_etop_mdio_probe(dev)) {
err = -ENXIO;
goto err_out_unregister_bus;
}
return 0;
err_out_unregister_bus:
mdiobus_unregister(priv->mii_bus);
err_out_free_mdiobus:
mdiobus_free(priv->mii_bus);
err_out:
return err;
}
static void
ltq_etop_mdio_cleanup(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
phy_disconnect(dev->phydev);
mdiobus_unregister(priv->mii_bus);
mdiobus_free(priv->mii_bus);
}
static int
ltq_etop_open(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
int i;
for (i = 0; i < MAX_DMA_CHAN; i++) {
struct ltq_etop_chan *ch = &priv->ch[i];
if (!IS_TX(i) && (!IS_RX(i)))
continue;
ltq_dma_open(&ch->dma);
napi_enable(&ch->napi);
}
phy_start(dev->phydev);
netif_tx_start_all_queues(dev);
return 0;
}
static int
ltq_etop_stop(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
int i;
netif_tx_stop_all_queues(dev);
phy_stop(dev->phydev);
for (i = 0; i < MAX_DMA_CHAN; i++) {
struct ltq_etop_chan *ch = &priv->ch[i];
if (!IS_RX(i) && !IS_TX(i))
continue;
napi_disable(&ch->napi);
ltq_dma_close(&ch->dma);
}
return 0;
}
static int
ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
{
int queue = skb_get_queue_mapping(skb);
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
struct ltq_etop_priv *priv = netdev_priv(dev);
struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
int len;
unsigned long flags;
u32 byte_offset;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
dev_kfree_skb_any(skb);
netdev_err(dev, "tx ring full\n");
netif_tx_stop_queue(txq);
return NETDEV_TX_BUSY;
}
/* dma needs to start on a 16 byte aligned address */
byte_offset = CPHYSADDR(skb->data) % 16;
ch->skb[ch->dma.desc] = skb;
netif_trans_update(dev);
spin_lock_irqsave(&priv->lock, flags);
desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
DMA_TO_DEVICE)) - byte_offset;
wmb();
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
ch->dma.desc++;
ch->dma.desc %= LTQ_DESC_NUM;
spin_unlock_irqrestore(&priv->lock, flags);
if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
netif_tx_stop_queue(txq);
return NETDEV_TX_OK;
}
static int
ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
{
int ret = eth_change_mtu(dev, new_mtu);
if (!ret) {
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
LTQ_ETOP_IGPLEN);
spin_unlock_irqrestore(&priv->lock, flags);
}
return ret;
}
static int
ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
/* TODO: mii-toll reports "No MII transceiver present!." ?!*/
return phy_mii_ioctl(dev->phydev, rq, cmd);
}
static int
ltq_etop_set_mac_address(struct net_device *dev, void *p)
{
int ret = eth_mac_addr(dev, p);
if (!ret) {
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned long flags;
/* store the mac for the unicast filter */
spin_lock_irqsave(&priv->lock, flags);
ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
LTQ_ETOP_MAC_DA1);
spin_unlock_irqrestore(&priv->lock, flags);
}
return ret;
}
static void
ltq_etop_set_multicast_list(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned long flags;
/* ensure that the unicast filter is not enabled in promiscious mode */
spin_lock_irqsave(&priv->lock, flags);
if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
else
ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
spin_unlock_irqrestore(&priv->lock, flags);
}
static u16
ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb,
void *accel_priv, select_queue_fallback_t fallback)
{
/* we are currently only using the first queue */
return 0;
}
static int
ltq_etop_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
struct sockaddr mac;
int err;
bool random_mac = false;
dev->watchdog_timeo = 10 * HZ;
err = ltq_etop_hw_init(dev);
if (err)
goto err_hw;
ltq_etop_change_mtu(dev, 1500);
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
if (!is_valid_ether_addr(mac.sa_data)) {
pr_warn("etop: invalid MAC, using random\n");
eth_random_addr(mac.sa_data);
random_mac = true;
}
err = ltq_etop_set_mac_address(dev, &mac);
if (err)
goto err_netdev;
/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
if (random_mac)
dev->addr_assign_type = NET_ADDR_RANDOM;
ltq_etop_set_multicast_list(dev);
err = ltq_etop_mdio_init(dev);
if (err)
goto err_netdev;
return 0;
err_netdev:
unregister_netdev(dev);
free_netdev(dev);
err_hw:
ltq_etop_hw_exit(dev);
return err;
}
static void
ltq_etop_tx_timeout(struct net_device *dev)
{
int err;
ltq_etop_hw_exit(dev);
err = ltq_etop_hw_init(dev);
if (err)
goto err_hw;
netif_trans_update(dev);
netif_wake_queue(dev);
return;
err_hw:
ltq_etop_hw_exit(dev);
netdev_err(dev, "failed to restart etop after TX timeout\n");
}
static const struct net_device_ops ltq_eth_netdev_ops = {
.ndo_open = ltq_etop_open,
.ndo_stop = ltq_etop_stop,
.ndo_start_xmit = ltq_etop_tx,
.ndo_change_mtu = ltq_etop_change_mtu,
.ndo_do_ioctl = ltq_etop_ioctl,
.ndo_set_mac_address = ltq_etop_set_mac_address,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_rx_mode = ltq_etop_set_multicast_list,
.ndo_select_queue = ltq_etop_select_queue,
.ndo_init = ltq_etop_init,
.ndo_tx_timeout = ltq_etop_tx_timeout,
};
static int __init
ltq_etop_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct ltq_etop_priv *priv;
struct resource *res;
int err;
int i;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get etop resource\n");
err = -ENOENT;
goto err_out;
}
res = devm_request_mem_region(&pdev->dev, res->start,
resource_size(res), dev_name(&pdev->dev));
if (!res) {
dev_err(&pdev->dev, "failed to request etop resource\n");
err = -EBUSY;
goto err_out;
}
ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
res->start, resource_size(res));
if (!ltq_etop_membase) {
dev_err(&pdev->dev, "failed to remap etop engine %d\n",
pdev->id);
err = -ENOMEM;
goto err_out;
}
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
if (!dev) {
err = -ENOMEM;
goto err_out;
}
strcpy(dev->name, "eth%d");
dev->netdev_ops = <q_eth_netdev_ops;
dev->ethtool_ops = <q_etop_ethtool_ops;
priv = netdev_priv(dev);
priv->res = res;
priv->pdev = pdev;
priv->pldata = dev_get_platdata(&pdev->dev);
priv->netdev = dev;
spin_lock_init(&priv->lock);
for (i = 0; i < MAX_DMA_CHAN; i++) {
if (IS_TX(i))
netif_napi_add(dev, &priv->ch[i].napi,
ltq_etop_poll_tx, 8);
else if (IS_RX(i))
netif_napi_add(dev, &priv->ch[i].napi,
ltq_etop_poll_rx, 32);
priv->ch[i].netdev = dev;
}
err = register_netdev(dev);
if (err)
goto err_free;
platform_set_drvdata(pdev, dev);
return 0;
err_free:
free_netdev(dev);
err_out:
return err;
}
static int
ltq_etop_remove(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
if (dev) {
netif_tx_stop_all_queues(dev);
ltq_etop_hw_exit(dev);
ltq_etop_mdio_cleanup(dev);
unregister_netdev(dev);
}
return 0;
}
static struct platform_driver ltq_mii_driver = {
.remove = ltq_etop_remove,
.driver = {
.name = "ltq_etop",
},
};
int __init
init_ltq_etop(void)
{
int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
if (ret)
pr_err("ltq_etop: Error registering platform driver!");
return ret;
}
static void __exit
exit_ltq_etop(void)
{
platform_driver_unregister(<q_mii_driver);
}
module_init(init_ltq_etop);
module_exit(exit_ltq_etop);
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("Lantiq SoC ETOP");
MODULE_LICENSE("GPL");
| gpl-2.0 |
ztemt/U9180_kernel | arch/arm/kernel/arch_timer.c | 82 | 14522 | /*
* linux/arch/arm/kernel/arch_timer.c
*
* Copyright (C) 2011 ARM Ltd.
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timex.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/cpu.h>
#include <linux/jiffies.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <asm/cputype.h>
#include <asm/delay.h>
#include <asm/localtimer.h>
#include <asm/arch_timer.h>
#include <asm/sched_clock.h>
#include <asm/hardware/gic.h>
#include <asm/system_info.h>
static unsigned long arch_timer_rate;
static int arch_timer_spi;
static int arch_timer_ppi;
static int arch_timer_ppi2;
static struct clock_event_device __percpu **arch_timer_evt;
static void __iomem *timer_base;
static struct delay_timer arch_delay_timer;
/*
* Architected system timer support.
*/
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
#define ARCH_TIMER_REG_CTRL 0
#define ARCH_TIMER_REG_FREQ 1
#define ARCH_TIMER_REG_TVAL 2
/* Iomapped Register Offsets */
#define QTIMER_CNTP_LOW_REG 0x000
#define QTIMER_CNTP_HIGH_REG 0x004
#define QTIMER_CNTV_LOW_REG 0x008
#define QTIMER_CNTV_HIGH_REG 0x00C
#define QTIMER_CTRL_REG 0x02C
#define QTIMER_FREQ_REG 0x010
#define QTIMER_CNTP_TVAL_REG 0x028
#define QTIMER_CNTV_TVAL_REG 0x038
static inline void timer_reg_write_mem(int reg, u32 val)
{
switch (reg) {
case ARCH_TIMER_REG_CTRL:
__raw_writel(val, timer_base + QTIMER_CTRL_REG);
break;
case ARCH_TIMER_REG_TVAL:
__raw_writel(val, timer_base + QTIMER_CNTP_TVAL_REG);
break;
}
}
static inline void timer_reg_write_cp15(int reg, u32 val)
{
switch (reg) {
case ARCH_TIMER_REG_CTRL:
asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
break;
}
isb();
}
static inline void arch_timer_reg_write(int cp15, int reg, u32 val)
{
if (cp15)
timer_reg_write_cp15(reg, val);
else
timer_reg_write_mem(reg, val);
}
static inline u32 timer_reg_read_mem(int reg)
{
u32 val;
switch (reg) {
case ARCH_TIMER_REG_CTRL:
val = __raw_readl(timer_base + QTIMER_CTRL_REG);
break;
case ARCH_TIMER_REG_FREQ:
val = __raw_readl(timer_base + QTIMER_FREQ_REG);
break;
case ARCH_TIMER_REG_TVAL:
val = __raw_readl(timer_base + QTIMER_CNTP_TVAL_REG);
break;
default:
BUG();
}
return val;
}
static inline u32 timer_reg_read_cp15(int reg)
{
u32 val;
switch (reg) {
case ARCH_TIMER_REG_CTRL:
asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
break;
case ARCH_TIMER_REG_FREQ:
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
break;
default:
BUG();
}
return val;
}
static inline u32 arch_timer_reg_read(int cp15, int reg)
{
if (cp15)
return timer_reg_read_cp15(reg);
else
return timer_reg_read_mem(reg);
}
static inline irqreturn_t arch_timer_handler(int cp15,
struct clock_event_device *evt)
{
unsigned long ctrl;
ctrl = arch_timer_reg_read(cp15, ARCH_TIMER_REG_CTRL);
if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
ctrl |= ARCH_TIMER_CTRL_IT_MASK;
arch_timer_reg_write(cp15, ARCH_TIMER_REG_CTRL, ctrl);
evt->event_handler(evt);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static irqreturn_t arch_timer_handler_cp15(int irq, void *dev_id)
{
struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
return arch_timer_handler(1, evt);
}
static irqreturn_t arch_timer_handler_mem(int irq, void *dev_id)
{
return arch_timer_handler(0, dev_id);
}
static inline void arch_timer_set_mode(int cp15, enum clock_event_mode mode,
struct clock_event_device *clk)
{
unsigned long ctrl;
switch (mode) {
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
ctrl = arch_timer_reg_read(cp15, ARCH_TIMER_REG_CTRL);
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
arch_timer_reg_write(cp15, ARCH_TIMER_REG_CTRL, ctrl);
break;
case CLOCK_EVT_MODE_ONESHOT:
ctrl = arch_timer_reg_read(cp15, ARCH_TIMER_REG_CTRL);
ctrl |= ARCH_TIMER_CTRL_ENABLE;
arch_timer_reg_write(cp15, ARCH_TIMER_REG_CTRL, ctrl);
default:
break;
}
}
static void arch_timer_set_mode_cp15(enum clock_event_mode mode,
struct clock_event_device *clk)
{
arch_timer_set_mode(1, mode, clk);
}
static void arch_timer_set_mode_mem(enum clock_event_mode mode,
struct clock_event_device *clk)
{
arch_timer_set_mode(0, mode, clk);
}
static int arch_timer_set_next_event(int cp15, unsigned long evt,
struct clock_event_device *unused)
{
unsigned long ctrl;
ctrl = arch_timer_reg_read(cp15, ARCH_TIMER_REG_CTRL);
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
arch_timer_reg_write(cp15, ARCH_TIMER_REG_CTRL, ctrl);
arch_timer_reg_write(cp15, ARCH_TIMER_REG_TVAL, evt);
return 0;
}
static int arch_timer_set_next_event_cp15(unsigned long evt,
struct clock_event_device *unused)
{
return arch_timer_set_next_event(1, evt, unused);
}
static int arch_timer_set_next_event_mem(unsigned long evt,
struct clock_event_device *unused)
{
return arch_timer_set_next_event(0, evt, unused);
}
static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
{
/* setup clock event only once for CPU 0 */
if (!smp_processor_id() && clk->irq == arch_timer_ppi)
return 0;
clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
clk->name = "arch_sys_timer";
clk->rating = 450;
clk->set_mode = arch_timer_set_mode_cp15;
clk->set_next_event = arch_timer_set_next_event_cp15;
clk->irq = arch_timer_ppi;
/* Be safe... */
clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
clockevents_config_and_register(clk, arch_timer_rate,
0xf, 0x7fffffff);
*__this_cpu_ptr(arch_timer_evt) = clk;
enable_percpu_irq(clk->irq, 0);
if (arch_timer_ppi2)
enable_percpu_irq(arch_timer_ppi2, 0);
return 0;
}
/* Is the optional system timer available? */
static int local_timer_is_architected(void)
{
return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
}
static int arch_timer_available(void)
{
unsigned long freq;
if (arch_timer_rate == 0) {
arch_timer_reg_write(1, ARCH_TIMER_REG_CTRL, 0);
freq = arch_timer_reg_read(1, ARCH_TIMER_REG_FREQ);
/* Check the timer frequency. */
if (freq == 0) {
pr_warn("Architected timer frequency not available\n");
return -EINVAL;
}
arch_timer_rate = freq;
pr_info("Architected local timer running at %lu.%02luMHz.\n",
freq / 1000000, (freq / 10000) % 100);
}
return 0;
}
static inline cycle_t notrace counter_get_cntpct_mem(void)
{
u32 cvall, cvalh, thigh;
do {
cvalh = __raw_readl(timer_base + QTIMER_CNTP_HIGH_REG);
cvall = __raw_readl(timer_base + QTIMER_CNTP_LOW_REG);
thigh = __raw_readl(timer_base + QTIMER_CNTP_HIGH_REG);
} while (cvalh != thigh);
return ((cycle_t) cvalh << 32) | cvall;
}
static inline cycle_t notrace counter_get_cntpct_cp15(void)
{
u32 cvall, cvalh;
asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
return ((cycle_t) cvalh << 32) | cvall;
}
static inline cycle_t notrace counter_get_cntvct_mem(void)
{
u32 cvall, cvalh, thigh;
do {
cvalh = __raw_readl(timer_base + QTIMER_CNTV_HIGH_REG);
cvall = __raw_readl(timer_base + QTIMER_CNTV_LOW_REG);
thigh = __raw_readl(timer_base + QTIMER_CNTV_HIGH_REG);
} while (cvalh != thigh);
return ((cycle_t) cvalh << 32) | cvall;
}
static inline cycle_t notrace counter_get_cntvct_cp15(void)
{
u32 cvall, cvalh;
asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
return ((cycle_t) cvalh << 32) | cvall;
}
static cycle_t (*get_cntpct_func)(void) = counter_get_cntpct_cp15;
static cycle_t (*get_cntvct_func)(void) = counter_get_cntvct_cp15;
cycle_t arch_counter_get_cntpct(void)
{
return get_cntpct_func();
}
EXPORT_SYMBOL(arch_counter_get_cntpct);
static cycle_t arch_counter_read(struct clocksource *cs)
{
return arch_counter_get_cntpct();
}
static unsigned long arch_timer_read_current_timer(void)
{
return arch_counter_get_cntpct();
}
static struct clocksource clocksource_counter = {
.name = "arch_sys_counter",
.rating = 400,
.read = arch_counter_read,
.mask = CLOCKSOURCE_MASK(56),
.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
};
static u32 arch_counter_get_cntvct32(void)
{
cycle_t cntvct;
cntvct = get_cntvct_func();
/*
* The sched_clock infrastructure only knows about counters
* with at most 32bits. Forget about the upper 24 bits for the
* time being...
*/
return (u32)(cntvct & (u32)~0);
}
static u32 notrace arch_timer_update_sched_clock(void)
{
return arch_counter_get_cntvct32();
}
static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
{
pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
clk->irq, smp_processor_id());
disable_percpu_irq(clk->irq);
if (arch_timer_ppi2)
disable_percpu_irq(arch_timer_ppi2);
clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
}
static struct local_timer_ops arch_timer_ops __cpuinitdata = {
.setup = arch_timer_setup,
.stop = arch_timer_stop,
};
static struct clock_event_device arch_timer_global_evt;
static void __init arch_timer_counter_init(void)
{
clocksource_register_hz(&clocksource_counter, arch_timer_rate);
setup_sched_clock(arch_timer_update_sched_clock, 32, arch_timer_rate);
/* Use the architected timer for the delay loop. */
arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
arch_delay_timer.freq = arch_timer_rate;
register_current_timer_delay(&arch_delay_timer);
}
static int __init arch_timer_common_register(void)
{
int err;
if (!local_timer_is_architected())
return -ENXIO;
err = arch_timer_available();
if (err)
return err;
arch_timer_evt = alloc_percpu(struct clock_event_device *);
if (!arch_timer_evt)
return -ENOMEM;
err = request_percpu_irq(arch_timer_ppi, arch_timer_handler_cp15,
"arch_timer", arch_timer_evt);
if (err) {
pr_err("arch_timer: can't register interrupt %d (%d)\n",
arch_timer_ppi, err);
goto out_free;
}
if (arch_timer_ppi2) {
err = request_percpu_irq(arch_timer_ppi2,
arch_timer_handler_cp15,
"arch_timer", arch_timer_evt);
if (err) {
pr_err("arch_timer: can't register interrupt %d (%d)\n",
arch_timer_ppi2, err);
arch_timer_ppi2 = 0;
goto out_free_irq;
}
}
err = local_timer_register(&arch_timer_ops);
if (err) {
/*
* We couldn't register as a local timer (could be
* because we're on a UP platform, or because some
* other local timer is already present...). Try as a
* global timer instead.
*/
arch_timer_global_evt.cpumask = cpumask_of(0);
err = arch_timer_setup(&arch_timer_global_evt);
}
if (err)
goto out_free_irq;
return 0;
out_free_irq:
free_percpu_irq(arch_timer_ppi, arch_timer_evt);
if (arch_timer_ppi2)
free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
out_free:
free_percpu(arch_timer_evt);
return err;
}
static int __init arch_timer_mem_register(void)
{
int err;
struct clock_event_device *clk;
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
clk->features = CLOCK_EVT_FEAT_ONESHOT;
clk->name = "arch_mem_timer";
clk->rating = 400;
clk->set_mode = arch_timer_set_mode_mem;
clk->set_next_event = arch_timer_set_next_event_mem;
clk->irq = arch_timer_spi;
clk->cpumask = cpu_all_mask;
clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
clockevents_config_and_register(clk, arch_timer_rate,
0xf, 0x7fffffff);
err = request_irq(arch_timer_spi, arch_timer_handler_mem, 0,
"arch_timer", clk);
return err;
}
int __init arch_timer_register(struct arch_timer *at)
{
if (at->res[0].start <= 0 || !(at->res[0].flags & IORESOURCE_IRQ))
return -EINVAL;
arch_timer_ppi = at->res[0].start;
if (at->res[1].start > 0 && (at->res[1].flags & IORESOURCE_IRQ))
arch_timer_ppi2 = at->res[1].start;
if (at->res[2].start > 0 && at->res[2].end > 0 &&
(at->res[2].flags & IORESOURCE_MEM))
timer_base = ioremap(at->res[2].start,
resource_size(&at->res[2]));
if (!timer_base) {
pr_err("arch_timer: cant map timer base\n");
return -ENOMEM;
}
return arch_timer_common_register();
}
#ifdef CONFIG_OF
static const struct of_device_id arch_timer_of_match[] __initconst = {
{ .compatible = "arm,armv7-timer", },
{},
};
static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
{ .compatible = "arm,armv7-timer-mem", },
{},
};
int __init arch_timer_of_register(void)
{
struct device_node *np, *frame;
u32 freq;
int ret;
int has_cp15 = false, has_mem = false;
np = of_find_matching_node(NULL, arch_timer_of_match);
if (np) {
has_cp15 = true;
/*
* Try to determine the frequency from the device tree
*/
if (!of_property_read_u32(np, "clock-frequency", &freq))
arch_timer_rate = freq;
ret = irq_of_parse_and_map(np, 0);
if (ret <= 0) {
pr_err("arch_timer: interrupt not specified in timer node\n");
return -ENODEV;
}
arch_timer_ppi = ret;
ret = irq_of_parse_and_map(np, 1);
if (ret > 0)
arch_timer_ppi2 = ret;
ret = arch_timer_common_register();
if (ret)
return ret;
}
np = of_find_matching_node(NULL, arch_timer_mem_of_match);
if (np) {
has_mem = true;
if (!has_cp15) {
get_cntpct_func = counter_get_cntpct_mem;
get_cntvct_func = counter_get_cntvct_mem;
}
/*
* Try to determine the frequency from the device tree
*/
if (!of_property_read_u32(np, "clock-frequency", &freq))
arch_timer_rate = freq;
frame = of_get_next_child(np, NULL);
if (!frame) {
pr_err("arch_timer: no child frame\n");
return -EINVAL;
}
timer_base = of_iomap(frame, 0);
if (!timer_base) {
pr_err("arch_timer: cant map timer base\n");
return -ENOMEM;
}
arch_timer_spi = irq_of_parse_and_map(frame, 0);
if (!arch_timer_spi) {
pr_err("arch_timer: no physical timer irq\n");
return -EINVAL;
}
ret = arch_timer_mem_register();
if (ret)
return ret;
}
if (!has_cp15 && !has_mem) {
pr_err("arch_timer: can't find DT node\n");
return -ENODEV;
}
arch_timer_counter_init();
return 0;
}
#endif
| gpl-2.0 |
ISTweak/android_kernel_sharp_c01 | arch/arm/mach-clps711x/p720t.c | 1618 | 3079 | /*
* linux/arch/arm/mach-clps711x/p720t.c
*
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/syspld.h>
#include "common.h"
/*
* Map the P720T system PLD. It occupies two address spaces:
* SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
* We map both here.
*/
static struct map_desc p720t_io_desc[] __initdata = {
{
.virtual = SYSPLD_VIRT_BASE,
.pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
.length = SZ_1M,
.type = MT_DEVICE
}, {
.virtual = 0xfe400000,
.pfn = __phys_to_pfn(0x10400000),
.length = SZ_1M,
.type = MT_DEVICE
}
};
static void __init
fixup_p720t(struct machine_desc *desc, struct tag *tag,
char **cmdline, struct meminfo *mi)
{
/*
* Our bootloader doesn't setup any tags (yet).
*/
if (tag->hdr.tag != ATAG_CORE) {
tag->hdr.tag = ATAG_CORE;
tag->hdr.size = tag_size(tag_core);
tag->u.core.flags = 0;
tag->u.core.pagesize = PAGE_SIZE;
tag->u.core.rootdev = 0x0100;
tag = tag_next(tag);
tag->hdr.tag = ATAG_MEM;
tag->hdr.size = tag_size(tag_mem32);
tag->u.mem.size = 4096;
tag->u.mem.start = PHYS_OFFSET;
tag = tag_next(tag);
tag->hdr.tag = ATAG_NONE;
tag->hdr.size = 0;
}
}
static void __init p720t_map_io(void)
{
clps711x_map_io();
iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
}
MACHINE_START(P720T, "ARM-Prospector720T")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.phys_io = 0x80000000,
.io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
.boot_params = 0xc0000100,
.fixup = fixup_p720t,
.map_io = p720t_map_io,
.init_irq = clps711x_init_irq,
.timer = &clps711x_timer,
MACHINE_END
static int p720t_hw_init(void)
{
/*
* Power down as much as possible in case we don't
* have the drivers loaded.
*/
PLD_LCDEN = 0;
PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
PLD_KBD = 0;
PLD_IO = 0;
PLD_IRDA = 0;
PLD_CODEC = 0;
PLD_TCH = 0;
PLD_SPI = 0;
#ifndef CONFIG_DEBUG_LL
PLD_COM2 = 0;
PLD_COM1 = 0;
#endif
return 0;
}
__initcall(p720t_hw_init);
| gpl-2.0 |
InfinitiveOS-Devices/android_kernel_huawei_msm8916 | drivers/ssb/driver_gpio.c | 2386 | 5300 | /*
* Sonics Silicon Backplane
* GPIO driver
*
* Copyright 2011, Broadcom Corporation
* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include <linux/gpio.h>
#include <linux/export.h>
#include <linux/ssb/ssb.h>
#include "ssb_private.h"
static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
{
return container_of(chip, struct ssb_bus, gpio);
}
static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
}
static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
int value)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
}
static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
return 0;
}
static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
return 0;
}
static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
/* clear pulldown */
ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
/* Set pullup */
ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
return 0;
}
static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
/* clear pullup */
ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
}
static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
if (bus->bustype == SSB_BUSTYPE_SSB)
return ssb_mips_irq(bus->chipco.dev) + 2;
else
return -EINVAL;
}
static int ssb_gpio_chipco_init(struct ssb_bus *bus)
{
struct gpio_chip *chip = &bus->gpio;
chip->label = "ssb_chipco_gpio";
chip->owner = THIS_MODULE;
chip->request = ssb_gpio_chipco_request;
chip->free = ssb_gpio_chipco_free;
chip->get = ssb_gpio_chipco_get_value;
chip->set = ssb_gpio_chipco_set_value;
chip->direction_input = ssb_gpio_chipco_direction_input;
chip->direction_output = ssb_gpio_chipco_direction_output;
chip->to_irq = ssb_gpio_chipco_to_irq;
chip->ngpio = 16;
/* There is just one SoC in one device and its GPIO addresses should be
* deterministic to address them more easily. The other buses could get
* a random base number. */
if (bus->bustype == SSB_BUSTYPE_SSB)
chip->base = 0;
else
chip->base = -1;
return gpiochip_add(chip);
}
#ifdef CONFIG_SSB_DRIVER_EXTIF
static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
}
static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
int value)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
}
static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
return 0;
}
static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
return 0;
}
static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
{
struct ssb_bus *bus = ssb_gpio_get_bus(chip);
if (bus->bustype == SSB_BUSTYPE_SSB)
return ssb_mips_irq(bus->extif.dev) + 2;
else
return -EINVAL;
}
static int ssb_gpio_extif_init(struct ssb_bus *bus)
{
struct gpio_chip *chip = &bus->gpio;
chip->label = "ssb_extif_gpio";
chip->owner = THIS_MODULE;
chip->get = ssb_gpio_extif_get_value;
chip->set = ssb_gpio_extif_set_value;
chip->direction_input = ssb_gpio_extif_direction_input;
chip->direction_output = ssb_gpio_extif_direction_output;
chip->to_irq = ssb_gpio_extif_to_irq;
chip->ngpio = 5;
/* There is just one SoC in one device and its GPIO addresses should be
* deterministic to address them more easily. The other buses could get
* a random base number. */
if (bus->bustype == SSB_BUSTYPE_SSB)
chip->base = 0;
else
chip->base = -1;
return gpiochip_add(chip);
}
#else
static int ssb_gpio_extif_init(struct ssb_bus *bus)
{
return -ENOTSUPP;
}
#endif
int ssb_gpio_init(struct ssb_bus *bus)
{
if (ssb_chipco_available(&bus->chipco))
return ssb_gpio_chipco_init(bus);
else if (ssb_extif_available(&bus->extif))
return ssb_gpio_extif_init(bus);
else
SSB_WARN_ON(1);
return -1;
}
int ssb_gpio_unregister(struct ssb_bus *bus)
{
if (ssb_chipco_available(&bus->chipco) ||
ssb_extif_available(&bus->extif)) {
return gpiochip_remove(&bus->gpio);
} else {
SSB_WARN_ON(1);
}
return -1;
}
| gpl-2.0 |
knone1/pinaslang-zenfone5-kernel | drivers/gpu/drm/radeon/radeon_state.c | 2386 | 95158 | /* radeon_state.c -- State support for Radeon -*- linux-c -*- */
/*
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Kevin E. Martin <martin@valinux.com>
*
* ------------------------ This file is DEPRECATED! -------------------------
*/
#include <drm/drmP.h>
#include <drm/drm_buffer.h>
#include <drm/radeon_drm.h>
#include "radeon_drv.h"
/* ================================================================
* Helper functions for client state checking and fixup
*/
static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
dev_priv,
struct drm_file * file_priv,
u32 *offset)
{
u64 off = *offset;
u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
struct drm_radeon_driver_file_fields *radeon_priv;
/* Hrm ... the story of the offset ... So this function converts
* the various ideas of what userland clients might have for an
* offset in the card address space into an offset into the card
* address space :) So with a sane client, it should just keep
* the value intact and just do some boundary checking. However,
* not all clients are sane. Some older clients pass us 0 based
* offsets relative to the start of the framebuffer and some may
* assume the AGP aperture it appended to the framebuffer, so we
* try to detect those cases and fix them up.
*
* Note: It might be a good idea here to make sure the offset lands
* in some "allowed" area to protect things like the PCIE GART...
*/
/* First, the best case, the offset already lands in either the
* framebuffer or the GART mapped space
*/
if (radeon_check_offset(dev_priv, off))
return 0;
/* Ok, that didn't happen... now check if we have a zero based
* offset that fits in the framebuffer + gart space, apply the
* magic offset we get from SETPARAM or calculated from fb_location
*/
if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
radeon_priv = file_priv->driver_priv;
off += radeon_priv->radeon_fb_delta;
}
/* Finally, assume we aimed at a GART offset if beyond the fb */
if (off > fb_end)
off = off - fb_end - 1 + dev_priv->gart_vm_start;
/* Now recheck and fail if out of bounds */
if (radeon_check_offset(dev_priv, off)) {
DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
*offset = off;
return 0;
}
return -EINVAL;
}
static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
dev_priv,
struct drm_file *file_priv,
int id, struct drm_buffer *buf)
{
u32 *data;
switch (id) {
case RADEON_EMIT_PP_MISC:
data = drm_buffer_pointer_to_dword(buf,
(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4);
if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
DRM_ERROR("Invalid depth buffer offset\n");
return -EINVAL;
}
dev_priv->have_z_offset = 1;
break;
case RADEON_EMIT_PP_CNTL:
data = drm_buffer_pointer_to_dword(buf,
(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4);
if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
DRM_ERROR("Invalid colour buffer offset\n");
return -EINVAL;
}
break;
case R200_EMIT_PP_TXOFFSET_0:
case R200_EMIT_PP_TXOFFSET_1:
case R200_EMIT_PP_TXOFFSET_2:
case R200_EMIT_PP_TXOFFSET_3:
case R200_EMIT_PP_TXOFFSET_4:
case R200_EMIT_PP_TXOFFSET_5:
data = drm_buffer_pointer_to_dword(buf, 0);
if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
DRM_ERROR("Invalid R200 texture offset\n");
return -EINVAL;
}
break;
case RADEON_EMIT_PP_TXFILTER_0:
case RADEON_EMIT_PP_TXFILTER_1:
case RADEON_EMIT_PP_TXFILTER_2:
data = drm_buffer_pointer_to_dword(buf,
(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4);
if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
DRM_ERROR("Invalid R100 texture offset\n");
return -EINVAL;
}
break;
case R200_EMIT_PP_CUBIC_OFFSETS_0:
case R200_EMIT_PP_CUBIC_OFFSETS_1:
case R200_EMIT_PP_CUBIC_OFFSETS_2:
case R200_EMIT_PP_CUBIC_OFFSETS_3:
case R200_EMIT_PP_CUBIC_OFFSETS_4:
case R200_EMIT_PP_CUBIC_OFFSETS_5:{
int i;
for (i = 0; i < 5; i++) {
data = drm_buffer_pointer_to_dword(buf, i);
if (radeon_check_and_fixup_offset(dev_priv,
file_priv,
data)) {
DRM_ERROR
("Invalid R200 cubic texture offset\n");
return -EINVAL;
}
}
break;
}
case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
int i;
for (i = 0; i < 5; i++) {
data = drm_buffer_pointer_to_dword(buf, i);
if (radeon_check_and_fixup_offset(dev_priv,
file_priv,
data)) {
DRM_ERROR
("Invalid R100 cubic texture offset\n");
return -EINVAL;
}
}
}
break;
case R200_EMIT_VAP_CTL:{
RING_LOCALS;
BEGIN_RING(2);
OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
ADVANCE_RING();
}
break;
case RADEON_EMIT_RB3D_COLORPITCH:
case RADEON_EMIT_RE_LINE_PATTERN:
case RADEON_EMIT_SE_LINE_WIDTH:
case RADEON_EMIT_PP_LUM_MATRIX:
case RADEON_EMIT_PP_ROT_MATRIX_0:
case RADEON_EMIT_RB3D_STENCILREFMASK:
case RADEON_EMIT_SE_VPORT_XSCALE:
case RADEON_EMIT_SE_CNTL:
case RADEON_EMIT_SE_CNTL_STATUS:
case RADEON_EMIT_RE_MISC:
case RADEON_EMIT_PP_BORDER_COLOR_0:
case RADEON_EMIT_PP_BORDER_COLOR_1:
case RADEON_EMIT_PP_BORDER_COLOR_2:
case RADEON_EMIT_SE_ZBIAS_FACTOR:
case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
case R200_EMIT_PP_TXCBLEND_0:
case R200_EMIT_PP_TXCBLEND_1:
case R200_EMIT_PP_TXCBLEND_2:
case R200_EMIT_PP_TXCBLEND_3:
case R200_EMIT_PP_TXCBLEND_4:
case R200_EMIT_PP_TXCBLEND_5:
case R200_EMIT_PP_TXCBLEND_6:
case R200_EMIT_PP_TXCBLEND_7:
case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
case R200_EMIT_TFACTOR_0:
case R200_EMIT_VTX_FMT_0:
case R200_EMIT_MATRIX_SELECT_0:
case R200_EMIT_TEX_PROC_CTL_2:
case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
case R200_EMIT_PP_TXFILTER_0:
case R200_EMIT_PP_TXFILTER_1:
case R200_EMIT_PP_TXFILTER_2:
case R200_EMIT_PP_TXFILTER_3:
case R200_EMIT_PP_TXFILTER_4:
case R200_EMIT_PP_TXFILTER_5:
case R200_EMIT_VTE_CNTL:
case R200_EMIT_OUTPUT_VTX_COMP_SEL:
case R200_EMIT_PP_TAM_DEBUG3:
case R200_EMIT_PP_CNTL_X:
case R200_EMIT_RB3D_DEPTHXY_OFFSET:
case R200_EMIT_RE_AUX_SCISSOR_CNTL:
case R200_EMIT_RE_SCISSOR_TL_0:
case R200_EMIT_RE_SCISSOR_TL_1:
case R200_EMIT_RE_SCISSOR_TL_2:
case R200_EMIT_SE_VAP_CNTL_STATUS:
case R200_EMIT_SE_VTX_STATE_CNTL:
case R200_EMIT_RE_POINTSIZE:
case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
case R200_EMIT_PP_CUBIC_FACES_0:
case R200_EMIT_PP_CUBIC_FACES_1:
case R200_EMIT_PP_CUBIC_FACES_2:
case R200_EMIT_PP_CUBIC_FACES_3:
case R200_EMIT_PP_CUBIC_FACES_4:
case R200_EMIT_PP_CUBIC_FACES_5:
case RADEON_EMIT_PP_TEX_SIZE_0:
case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
case R200_EMIT_TCL_POINT_SPRITE_CNTL:
case RADEON_EMIT_PP_CUBIC_FACES_0:
case RADEON_EMIT_PP_CUBIC_FACES_1:
case RADEON_EMIT_PP_CUBIC_FACES_2:
case R200_EMIT_PP_TRI_PERF_CNTL:
case R200_EMIT_PP_AFS_0:
case R200_EMIT_PP_AFS_1:
case R200_EMIT_ATF_TFACTOR:
case R200_EMIT_PP_TXCTLALL_0:
case R200_EMIT_PP_TXCTLALL_1:
case R200_EMIT_PP_TXCTLALL_2:
case R200_EMIT_PP_TXCTLALL_3:
case R200_EMIT_PP_TXCTLALL_4:
case R200_EMIT_PP_TXCTLALL_5:
case R200_EMIT_VAP_PVS_CNTL:
/* These packets don't contain memory offsets */
break;
default:
DRM_ERROR("Unknown state packet ID %d\n", id);
return -EINVAL;
}
return 0;
}
static int radeon_check_and_fixup_packet3(drm_radeon_private_t *
dev_priv,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *
cmdbuf,
unsigned int *cmdsz)
{
u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
u32 offset, narrays;
int count, i, k;
count = ((*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16);
*cmdsz = 2 + count;
if ((*cmd & 0xc0000000) != RADEON_CP_PACKET3) {
DRM_ERROR("Not a type 3 packet\n");
return -EINVAL;
}
if (4 * *cmdsz > drm_buffer_unprocessed(cmdbuf->buffer)) {
DRM_ERROR("Packet size larger than size of data provided\n");
return -EINVAL;
}
switch (*cmd & 0xff00) {
/* XXX Are there old drivers needing other packets? */
case RADEON_3D_DRAW_IMMD:
case RADEON_3D_DRAW_VBUF:
case RADEON_3D_DRAW_INDX:
case RADEON_WAIT_FOR_IDLE:
case RADEON_CP_NOP:
case RADEON_3D_CLEAR_ZMASK:
/* case RADEON_CP_NEXT_CHAR:
case RADEON_CP_PLY_NEXTSCAN:
case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
/* these packets are safe */
break;
case RADEON_CP_3D_DRAW_IMMD_2:
case RADEON_CP_3D_DRAW_VBUF_2:
case RADEON_CP_3D_DRAW_INDX_2:
case RADEON_3D_CLEAR_HIZ:
/* safe but r200 only */
if (dev_priv->microcode_version != UCODE_R200) {
DRM_ERROR("Invalid 3d packet for r100-class chip\n");
return -EINVAL;
}
break;
case RADEON_3D_LOAD_VBPNTR:
if (count > 18) { /* 12 arrays max */
DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
count);
return -EINVAL;
}
/* carefully check packet contents */
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
narrays = *cmd & ~0xc000;
k = 0;
i = 2;
while ((k < narrays) && (i < (count + 2))) {
i++; /* skip attribute field */
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
if (radeon_check_and_fixup_offset(dev_priv, file_priv,
cmd)) {
DRM_ERROR
("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
k, i);
return -EINVAL;
}
k++;
i++;
if (k == narrays)
break;
/* have one more to process, they come in pairs */
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
if (radeon_check_and_fixup_offset(dev_priv,
file_priv, cmd))
{
DRM_ERROR
("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
k, i);
return -EINVAL;
}
k++;
i++;
}
/* do the counts match what we expect ? */
if ((k != narrays) || (i != (count + 2))) {
DRM_ERROR
("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
k, i, narrays, count + 1);
return -EINVAL;
}
break;
case RADEON_3D_RNDR_GEN_INDX_PRIM:
if (dev_priv->microcode_version != UCODE_R100) {
DRM_ERROR("Invalid 3d packet for r200-class chip\n");
return -EINVAL;
}
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
DRM_ERROR("Invalid rndr_gen_indx offset\n");
return -EINVAL;
}
break;
case RADEON_CP_INDX_BUFFER:
if (dev_priv->microcode_version != UCODE_R200) {
DRM_ERROR("Invalid 3d packet for r100-class chip\n");
return -EINVAL;
}
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
if ((*cmd & 0x8000ffff) != 0x80000810) {
DRM_ERROR("Invalid indx_buffer reg address %08X\n", *cmd);
return -EINVAL;
}
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
DRM_ERROR("Invalid indx_buffer offset is %08X\n", *cmd);
return -EINVAL;
}
break;
case RADEON_CNTL_HOSTDATA_BLT:
case RADEON_CNTL_PAINT_MULTI:
case RADEON_CNTL_BITBLT_MULTI:
/* MSB of opcode: next DWORD GUI_CNTL */
cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
if (*cmd & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
| RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
offset = *cmd2 << 10;
if (radeon_check_and_fixup_offset
(dev_priv, file_priv, &offset)) {
DRM_ERROR("Invalid first packet offset\n");
return -EINVAL;
}
*cmd2 = (*cmd2 & 0xffc00000) | offset >> 10;
}
if ((*cmd & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
(*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
offset = *cmd3 << 10;
if (radeon_check_and_fixup_offset
(dev_priv, file_priv, &offset)) {
DRM_ERROR("Invalid second packet offset\n");
return -EINVAL;
}
*cmd3 = (*cmd3 & 0xffc00000) | offset >> 10;
}
break;
default:
DRM_ERROR("Invalid packet type %x\n", *cmd & 0xff00);
return -EINVAL;
}
return 0;
}
/* ================================================================
* CP hardware state programming functions
*/
static void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
struct drm_clip_rect * box)
{
RING_LOCALS;
DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
box->x1, box->y1, box->x2, box->y2);
BEGIN_RING(4);
OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
OUT_RING((box->y1 << 16) | box->x1);
OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
ADVANCE_RING();
}
/* Emit 1.1 state
*/
static int radeon_emit_state(drm_radeon_private_t * dev_priv,
struct drm_file *file_priv,
drm_radeon_context_regs_t * ctx,
drm_radeon_texture_regs_t * tex,
unsigned int dirty)
{
RING_LOCALS;
DRM_DEBUG("dirty=0x%08x\n", dirty);
if (dirty & RADEON_UPLOAD_CONTEXT) {
if (radeon_check_and_fixup_offset(dev_priv, file_priv,
&ctx->rb3d_depthoffset)) {
DRM_ERROR("Invalid depth buffer offset\n");
return -EINVAL;
}
if (radeon_check_and_fixup_offset(dev_priv, file_priv,
&ctx->rb3d_coloroffset)) {
DRM_ERROR("Invalid depth buffer offset\n");
return -EINVAL;
}
BEGIN_RING(14);
OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
OUT_RING(ctx->pp_misc);
OUT_RING(ctx->pp_fog_color);
OUT_RING(ctx->re_solid_color);
OUT_RING(ctx->rb3d_blendcntl);
OUT_RING(ctx->rb3d_depthoffset);
OUT_RING(ctx->rb3d_depthpitch);
OUT_RING(ctx->rb3d_zstencilcntl);
OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
OUT_RING(ctx->pp_cntl);
OUT_RING(ctx->rb3d_cntl);
OUT_RING(ctx->rb3d_coloroffset);
OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
OUT_RING(ctx->rb3d_colorpitch);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_VERTFMT) {
BEGIN_RING(2);
OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
OUT_RING(ctx->se_coord_fmt);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_LINE) {
BEGIN_RING(5);
OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
OUT_RING(ctx->re_line_pattern);
OUT_RING(ctx->re_line_state);
OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
OUT_RING(ctx->se_line_width);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_BUMPMAP) {
BEGIN_RING(5);
OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
OUT_RING(ctx->pp_lum_matrix);
OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
OUT_RING(ctx->pp_rot_matrix_0);
OUT_RING(ctx->pp_rot_matrix_1);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_MASKS) {
BEGIN_RING(4);
OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
OUT_RING(ctx->rb3d_stencilrefmask);
OUT_RING(ctx->rb3d_ropcntl);
OUT_RING(ctx->rb3d_planemask);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_VIEWPORT) {
BEGIN_RING(7);
OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
OUT_RING(ctx->se_vport_xscale);
OUT_RING(ctx->se_vport_xoffset);
OUT_RING(ctx->se_vport_yscale);
OUT_RING(ctx->se_vport_yoffset);
OUT_RING(ctx->se_vport_zscale);
OUT_RING(ctx->se_vport_zoffset);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_SETUP) {
BEGIN_RING(4);
OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
OUT_RING(ctx->se_cntl);
OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
OUT_RING(ctx->se_cntl_status);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_MISC) {
BEGIN_RING(2);
OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
OUT_RING(ctx->re_misc);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_TEX0) {
if (radeon_check_and_fixup_offset(dev_priv, file_priv,
&tex[0].pp_txoffset)) {
DRM_ERROR("Invalid texture offset for unit 0\n");
return -EINVAL;
}
BEGIN_RING(9);
OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
OUT_RING(tex[0].pp_txfilter);
OUT_RING(tex[0].pp_txformat);
OUT_RING(tex[0].pp_txoffset);
OUT_RING(tex[0].pp_txcblend);
OUT_RING(tex[0].pp_txablend);
OUT_RING(tex[0].pp_tfactor);
OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
OUT_RING(tex[0].pp_border_color);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_TEX1) {
if (radeon_check_and_fixup_offset(dev_priv, file_priv,
&tex[1].pp_txoffset)) {
DRM_ERROR("Invalid texture offset for unit 1\n");
return -EINVAL;
}
BEGIN_RING(9);
OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
OUT_RING(tex[1].pp_txfilter);
OUT_RING(tex[1].pp_txformat);
OUT_RING(tex[1].pp_txoffset);
OUT_RING(tex[1].pp_txcblend);
OUT_RING(tex[1].pp_txablend);
OUT_RING(tex[1].pp_tfactor);
OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
OUT_RING(tex[1].pp_border_color);
ADVANCE_RING();
}
if (dirty & RADEON_UPLOAD_TEX2) {
if (radeon_check_and_fixup_offset(dev_priv, file_priv,
&tex[2].pp_txoffset)) {
DRM_ERROR("Invalid texture offset for unit 2\n");
return -EINVAL;
}
BEGIN_RING(9);
OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
OUT_RING(tex[2].pp_txfilter);
OUT_RING(tex[2].pp_txformat);
OUT_RING(tex[2].pp_txoffset);
OUT_RING(tex[2].pp_txcblend);
OUT_RING(tex[2].pp_txablend);
OUT_RING(tex[2].pp_tfactor);
OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
OUT_RING(tex[2].pp_border_color);
ADVANCE_RING();
}
return 0;
}
/* Emit 1.2 state
*/
static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
struct drm_file *file_priv,
drm_radeon_state_t * state)
{
RING_LOCALS;
if (state->dirty & RADEON_UPLOAD_ZBIAS) {
BEGIN_RING(3);
OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
OUT_RING(state->context2.se_zbias_factor);
OUT_RING(state->context2.se_zbias_constant);
ADVANCE_RING();
}
return radeon_emit_state(dev_priv, file_priv, &state->context,
state->tex, state->dirty);
}
/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
* 1.3 cmdbuffers allow all previous state to be updated as well as
* the tcl scalar and vector areas.
*/
static struct {
int start;
int len;
const char *name;
} packet[RADEON_MAX_STATE_PACKETS] = {
{RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
{RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
{RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
{RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
{RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
{RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
{RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
{RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
{RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
{RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
{RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
{RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
{RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
{RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
{RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
{RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
{RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
{RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
{RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
{RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
{RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
{R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
{R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
{R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
{R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
{R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
{R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
{R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
{R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
{R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
{R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
{R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
{R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
{R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
{R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
{R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
{R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
{R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
{R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
{R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
{R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
{R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
{R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
{R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
{R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
{R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
{R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
{R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
{R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
{R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
"R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
{R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
{R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
{R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
{R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
{R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
{R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
{R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
{R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
{R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
{R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
{R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
"R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
{R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
{R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
{R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
{R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
{R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
{R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
{R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
{R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
{R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
{R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
{R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
{R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
{RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
{RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
{RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
{R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
{R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
{RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
{RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
{RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
{RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
{RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
{RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
{R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
{R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
{R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
{R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
{R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
{R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
{R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
{R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
{R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
{R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
{R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
};
/* ================================================================
* Performance monitoring functions
*/
static void radeon_clear_box(drm_radeon_private_t * dev_priv,
struct drm_radeon_master_private *master_priv,
int x, int y, int w, int h, int r, int g, int b)
{
u32 color;
RING_LOCALS;
x += master_priv->sarea_priv->boxes[0].x1;
y += master_priv->sarea_priv->boxes[0].y1;
switch (dev_priv->color_fmt) {
case RADEON_COLOR_FORMAT_RGB565:
color = (((r & 0xf8) << 8) |
((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
break;
case RADEON_COLOR_FORMAT_ARGB8888:
default:
color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
break;
}
BEGIN_RING(4);
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
OUT_RING(0xffffffff);
ADVANCE_RING();
BEGIN_RING(6);
OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
if (master_priv->sarea_priv->pfCurrentPage == 1) {
OUT_RING(dev_priv->front_pitch_offset);
} else {
OUT_RING(dev_priv->back_pitch_offset);
}
OUT_RING(color);
OUT_RING((x << 16) | y);
OUT_RING((w << 16) | h);
ADVANCE_RING();
}
static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_private *master_priv)
{
/* Collapse various things into a wait flag -- trying to
* guess if userspase slept -- better just to have them tell us.
*/
if (dev_priv->stats.last_frame_reads > 1 ||
dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
}
if (dev_priv->stats.freelist_loops) {
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
}
/* Purple box for page flipping
*/
if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255);
/* Red box if we have to wait for idle at any point
*/
if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0);
/* Blue box: lost context?
*/
/* Yellow box for texture swaps
*/
if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0);
/* Green box if hardware never idles (as far as we can tell)
*/
if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0);
/* Draw bars indicating number of buffers allocated
* (not a great measure, easily confused)
*/
if (dev_priv->stats.requested_bufs) {
if (dev_priv->stats.requested_bufs > 100)
dev_priv->stats.requested_bufs = 100;
radeon_clear_box(dev_priv, master_priv, 4, 16,
dev_priv->stats.requested_bufs, 4,
196, 128, 128);
}
memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
}
/* ================================================================
* CP command dispatch functions
*/
static void radeon_cp_dispatch_clear(struct drm_device * dev,
struct drm_master *master,
drm_radeon_clear_t * clear,
drm_radeon_clear_rect_t * depth_boxes)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
int nbox = sarea_priv->nbox;
struct drm_clip_rect *pbox = sarea_priv->boxes;
unsigned int flags = clear->flags;
u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
int i;
RING_LOCALS;
DRM_DEBUG("flags = 0x%x\n", flags);
dev_priv->stats.clears++;
if (sarea_priv->pfCurrentPage == 1) {
unsigned int tmp = flags;
flags &= ~(RADEON_FRONT | RADEON_BACK);
if (tmp & RADEON_FRONT)
flags |= RADEON_BACK;
if (tmp & RADEON_BACK)
flags |= RADEON_FRONT;
}
if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
if (!dev_priv->have_z_offset) {
printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
}
}
if (flags & (RADEON_FRONT | RADEON_BACK)) {
BEGIN_RING(4);
/* Ensure the 3D stream is idle before doing a
* 2D fill to clear the front or back buffer.
*/
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
OUT_RING(clear->color_mask);
ADVANCE_RING();
/* Make sure we restore the 3D state next time.
*/
sarea_priv->ctx_owner = 0;
for (i = 0; i < nbox; i++) {
int x = pbox[i].x1;
int y = pbox[i].y1;
int w = pbox[i].x2 - x;
int h = pbox[i].y2 - y;
DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n",
x, y, w, h, flags);
if (flags & RADEON_FRONT) {
BEGIN_RING(6);
OUT_RING(CP_PACKET3
(RADEON_CNTL_PAINT_MULTI, 4));
OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->
color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS);
OUT_RING(dev_priv->front_pitch_offset);
OUT_RING(clear->clear_color);
OUT_RING((x << 16) | y);
OUT_RING((w << 16) | h);
ADVANCE_RING();
}
if (flags & RADEON_BACK) {
BEGIN_RING(6);
OUT_RING(CP_PACKET3
(RADEON_CNTL_PAINT_MULTI, 4));
OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
(dev_priv->
color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_P |
RADEON_GMC_CLR_CMP_CNTL_DIS);
OUT_RING(dev_priv->back_pitch_offset);
OUT_RING(clear->clear_color);
OUT_RING((x << 16) | y);
OUT_RING((w << 16) | h);
ADVANCE_RING();
}
}
}
/* hyper z clear */
/* no docs available, based on reverse engineering by Stephane Marchesin */
if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
&& (flags & RADEON_CLEAR_FASTZ)) {
int i;
int depthpixperline =
dev_priv->depth_fmt ==
RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
2) : (dev_priv->
depth_pitch / 4);
u32 clearmask;
u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
((clear->depth_mask & 0xff) << 24);
/* Make sure we restore the 3D state next time.
* we haven't touched any "normal" state - still need this?
*/
sarea_priv->ctx_owner = 0;
if ((dev_priv->flags & RADEON_HAS_HIERZ)
&& (flags & RADEON_USE_HIERZ)) {
/* FIXME : reverse engineer that for Rx00 cards */
/* FIXME : the mask supposedly contains low-res z values. So can't set
just to the max (0xff? or actually 0x3fff?), need to take z clear
value into account? */
/* pattern seems to work for r100, though get slight
rendering errors with glxgears. If hierz is not enabled for r100,
only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
other ones are ignored, and the same clear mask can be used. That's
very different behaviour than R200 which needs different clear mask
and different number of tiles to clear if hierz is enabled or not !?!
*/
clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
} else {
/* clear mask : chooses the clearing pattern.
rv250: could be used to clear only parts of macrotiles
(but that would get really complicated...)?
bit 0 and 1 (either or both of them ?!?!) are used to
not clear tile (or maybe one of the bits indicates if the tile is
compressed or not), bit 2 and 3 to not clear tile 1,...,.
Pattern is as follows:
| 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
bits -------------------------------------------------
| 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
rv100: clearmask covers 2x8 4x1 tiles, but one clear still
covers 256 pixels ?!?
*/
clearmask = 0x0;
}
BEGIN_RING(8);
RADEON_WAIT_UNTIL_2D_IDLE();
OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
tempRB3D_DEPTHCLEARVALUE);
/* what offset is this exactly ? */
OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
/* need ctlstat, otherwise get some strange black flickering */
OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
RADEON_RB3D_ZC_FLUSH_ALL);
ADVANCE_RING();
for (i = 0; i < nbox; i++) {
int tileoffset, nrtilesx, nrtilesy, j;
/* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
if ((dev_priv->flags & RADEON_HAS_HIERZ)
&& !(dev_priv->microcode_version == UCODE_R200)) {
/* FIXME : figure this out for r200 (when hierz is enabled). Or
maybe r200 actually doesn't need to put the low-res z value into
the tile cache like r100, but just needs to clear the hi-level z-buffer?
Works for R100, both with hierz and without.
R100 seems to operate on 2x1 8x8 tiles, but...
odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
problematic with resolutions which are not 64 pix aligned? */
tileoffset =
((pbox[i].y1 >> 3) * depthpixperline +
pbox[i].x1) >> 6;
nrtilesx =
((pbox[i].x2 & ~63) -
(pbox[i].x1 & ~63)) >> 4;
nrtilesy =
(pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
for (j = 0; j <= nrtilesy; j++) {
BEGIN_RING(4);
OUT_RING(CP_PACKET3
(RADEON_3D_CLEAR_ZMASK, 2));
/* first tile */
OUT_RING(tileoffset * 8);
/* the number of tiles to clear */
OUT_RING(nrtilesx + 4);
/* clear mask : chooses the clearing pattern. */
OUT_RING(clearmask);
ADVANCE_RING();
tileoffset += depthpixperline >> 6;
}
} else if (dev_priv->microcode_version == UCODE_R200) {
/* works for rv250. */
/* find first macro tile (8x2 4x4 z-pixels on rv250) */
tileoffset =
((pbox[i].y1 >> 3) * depthpixperline +
pbox[i].x1) >> 5;
nrtilesx =
(pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
nrtilesy =
(pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
for (j = 0; j <= nrtilesy; j++) {
BEGIN_RING(4);
OUT_RING(CP_PACKET3
(RADEON_3D_CLEAR_ZMASK, 2));
/* first tile */
/* judging by the first tile offset needed, could possibly
directly address/clear 4x4 tiles instead of 8x2 * 4x4
macro tiles, though would still need clear mask for
right/bottom if truly 4x4 granularity is desired ? */
OUT_RING(tileoffset * 16);
/* the number of tiles to clear */
OUT_RING(nrtilesx + 1);
/* clear mask : chooses the clearing pattern. */
OUT_RING(clearmask);
ADVANCE_RING();
tileoffset += depthpixperline >> 5;
}
} else { /* rv 100 */
/* rv100 might not need 64 pix alignment, who knows */
/* offsets are, hmm, weird */
tileoffset =
((pbox[i].y1 >> 4) * depthpixperline +
pbox[i].x1) >> 6;
nrtilesx =
((pbox[i].x2 & ~63) -
(pbox[i].x1 & ~63)) >> 4;
nrtilesy =
(pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
for (j = 0; j <= nrtilesy; j++) {
BEGIN_RING(4);
OUT_RING(CP_PACKET3
(RADEON_3D_CLEAR_ZMASK, 2));
OUT_RING(tileoffset * 128);
/* the number of tiles to clear */
OUT_RING(nrtilesx + 4);
/* clear mask : chooses the clearing pattern. */
OUT_RING(clearmask);
ADVANCE_RING();
tileoffset += depthpixperline >> 6;
}
}
}
/* TODO don't always clear all hi-level z tiles */
if ((dev_priv->flags & RADEON_HAS_HIERZ)
&& (dev_priv->microcode_version == UCODE_R200)
&& (flags & RADEON_USE_HIERZ))
/* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
/* FIXME : the mask supposedly contains low-res z values. So can't set
just to the max (0xff? or actually 0x3fff?), need to take z clear
value into account? */
{
BEGIN_RING(4);
OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
OUT_RING(0x0); /* First tile */
OUT_RING(0x3cc0);
OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
ADVANCE_RING();
}
}
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
*/
else if ((dev_priv->microcode_version == UCODE_R200) &&
(flags & (RADEON_DEPTH | RADEON_STENCIL))) {
int tempPP_CNTL;
int tempRE_CNTL;
int tempRB3D_CNTL;
int tempRB3D_ZSTENCILCNTL;
int tempRB3D_STENCILREFMASK;
int tempRB3D_PLANEMASK;
int tempSE_CNTL;
int tempSE_VTE_CNTL;
int tempSE_VTX_FMT_0;
int tempSE_VTX_FMT_1;
int tempSE_VAP_CNTL;
int tempRE_AUX_SCISSOR_CNTL;
tempPP_CNTL = 0;
tempRE_CNTL = 0;
tempRB3D_CNTL = depth_clear->rb3d_cntl;
tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
tempRB3D_STENCILREFMASK = 0x0;
tempSE_CNTL = depth_clear->se_cntl;
/* Disable TCL */
tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
(0x9 <<
SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
tempRB3D_PLANEMASK = 0x0;
tempRE_AUX_SCISSOR_CNTL = 0x0;
tempSE_VTE_CNTL =
SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
/* Vertex format (X, Y, Z, W) */
tempSE_VTX_FMT_0 =
SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
tempSE_VTX_FMT_1 = 0x0;
/*
* Depth buffer specific enables
*/
if (flags & RADEON_DEPTH) {
/* Enable depth buffer */
tempRB3D_CNTL |= RADEON_Z_ENABLE;
} else {
/* Disable depth buffer */
tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
}
/*
* Stencil buffer specific enables
*/
if (flags & RADEON_STENCIL) {
tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
tempRB3D_STENCILREFMASK = clear->depth_mask;
} else {
tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
tempRB3D_STENCILREFMASK = 0x00000000;
}
if (flags & RADEON_USE_COMP_ZBUF) {
tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
RADEON_Z_DECOMPRESSION_ENABLE;
}
if (flags & RADEON_USE_HIERZ) {
tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
}
BEGIN_RING(26);
RADEON_WAIT_UNTIL_2D_IDLE();
OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
tempRB3D_STENCILREFMASK);
OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
ADVANCE_RING();
/* Make sure we restore the 3D state next time.
*/
sarea_priv->ctx_owner = 0;
for (i = 0; i < nbox; i++) {
/* Funny that this should be required --
* sets top-left?
*/
radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
BEGIN_RING(14);
OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
RADEON_PRIM_WALK_RING |
(3 << RADEON_NUM_VERTICES_SHIFT)));
OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
OUT_RING(0x3f800000);
OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
OUT_RING(0x3f800000);
OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
OUT_RING(0x3f800000);
ADVANCE_RING();
}
} else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
rb3d_cntl = depth_clear->rb3d_cntl;
if (flags & RADEON_DEPTH) {
rb3d_cntl |= RADEON_Z_ENABLE;
} else {
rb3d_cntl &= ~RADEON_Z_ENABLE;
}
if (flags & RADEON_STENCIL) {
rb3d_cntl |= RADEON_STENCIL_ENABLE;
rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
} else {
rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
rb3d_stencilrefmask = 0x00000000;
}
if (flags & RADEON_USE_COMP_ZBUF) {
tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
RADEON_Z_DECOMPRESSION_ENABLE;
}
if (flags & RADEON_USE_HIERZ) {
tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
}
BEGIN_RING(13);
RADEON_WAIT_UNTIL_2D_IDLE();
OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
OUT_RING(0x00000000);
OUT_RING(rb3d_cntl);
OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
ADVANCE_RING();
/* Make sure we restore the 3D state next time.
*/
sarea_priv->ctx_owner = 0;
for (i = 0; i < nbox; i++) {
/* Funny that this should be required --
* sets top-left?
*/
radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
BEGIN_RING(15);
OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
OUT_RING(RADEON_VTX_Z_PRESENT |
RADEON_VTX_PKCOLOR_PRESENT);
OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
RADEON_PRIM_WALK_RING |
RADEON_MAOS_ENABLE |
RADEON_VTX_FMT_RADEON_MODE |
(3 << RADEON_NUM_VERTICES_SHIFT)));
OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
OUT_RING(0x0);
OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
OUT_RING(0x0);
OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
OUT_RING(0x0);
ADVANCE_RING();
}
}
/* Increment the clear counter. The client-side 3D driver must
* wait on this value before performing the clear ioctl. We
* need this because the card's so damned fast...
*/
sarea_priv->last_clear++;
BEGIN_RING(4);
RADEON_CLEAR_AGE(sarea_priv->last_clear);
RADEON_WAIT_UNTIL_IDLE();
ADVANCE_RING();
}
static void radeon_cp_dispatch_swap(struct drm_device *dev, struct drm_master *master)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
int nbox = sarea_priv->nbox;
struct drm_clip_rect *pbox = sarea_priv->boxes;
int i;
RING_LOCALS;
DRM_DEBUG("\n");
/* Do some trivial performance monitoring...
*/
if (dev_priv->do_boxes)
radeon_cp_performance_boxes(dev_priv, master_priv);
/* Wait for the 3D stream to idle before dispatching the bitblt.
* This will prevent data corruption between the two streams.
*/
BEGIN_RING(2);
RADEON_WAIT_UNTIL_3D_IDLE();
ADVANCE_RING();
for (i = 0; i < nbox; i++) {
int x = pbox[i].x1;
int y = pbox[i].y1;
int w = pbox[i].x2 - x;
int h = pbox[i].y2 - y;
DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
BEGIN_RING(9);
OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_NONE |
(dev_priv->color_fmt << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_S |
RADEON_DP_SRC_SOURCE_MEMORY |
RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
/* Make this work even if front & back are flipped:
*/
OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
if (sarea_priv->pfCurrentPage == 0) {
OUT_RING(dev_priv->back_pitch_offset);
OUT_RING(dev_priv->front_pitch_offset);
} else {
OUT_RING(dev_priv->front_pitch_offset);
OUT_RING(dev_priv->back_pitch_offset);
}
OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
OUT_RING((x << 16) | y);
OUT_RING((x << 16) | y);
OUT_RING((w << 16) | h);
ADVANCE_RING();
}
/* Increment the frame counter. The client-side 3D driver must
* throttle the framerate by waiting for this value before
* performing the swapbuffer ioctl.
*/
sarea_priv->last_frame++;
BEGIN_RING(4);
RADEON_FRAME_AGE(sarea_priv->last_frame);
RADEON_WAIT_UNTIL_2D_IDLE();
ADVANCE_RING();
}
void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
struct drm_sarea *sarea = (struct drm_sarea *)master_priv->sarea->handle;
int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
? dev_priv->front_offset : dev_priv->back_offset;
RING_LOCALS;
DRM_DEBUG("pfCurrentPage=%d\n",
master_priv->sarea_priv->pfCurrentPage);
/* Do some trivial performance monitoring...
*/
if (dev_priv->do_boxes) {
dev_priv->stats.boxes |= RADEON_BOX_FLIP;
radeon_cp_performance_boxes(dev_priv, master_priv);
}
/* Update the frame offsets for both CRTCs
*/
BEGIN_RING(6);
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING_REG(RADEON_CRTC_OFFSET,
((sarea->frame.y * dev_priv->front_pitch +
sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
+ offset);
OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
+ offset);
ADVANCE_RING();
/* Increment the frame counter. The client-side 3D driver must
* throttle the framerate by waiting for this value before
* performing the swapbuffer ioctl.
*/
master_priv->sarea_priv->last_frame++;
master_priv->sarea_priv->pfCurrentPage =
1 - master_priv->sarea_priv->pfCurrentPage;
BEGIN_RING(2);
RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
ADVANCE_RING();
}
static int bad_prim_vertex_nr(int primitive, int nr)
{
switch (primitive & RADEON_PRIM_TYPE_MASK) {
case RADEON_PRIM_TYPE_NONE:
case RADEON_PRIM_TYPE_POINT:
return nr < 1;
case RADEON_PRIM_TYPE_LINE:
return (nr & 1) || nr == 0;
case RADEON_PRIM_TYPE_LINE_STRIP:
return nr < 2;
case RADEON_PRIM_TYPE_TRI_LIST:
case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
case RADEON_PRIM_TYPE_RECT_LIST:
return nr % 3 || nr == 0;
case RADEON_PRIM_TYPE_TRI_FAN:
case RADEON_PRIM_TYPE_TRI_STRIP:
return nr < 3;
default:
return 1;
}
}
typedef struct {
unsigned int start;
unsigned int finish;
unsigned int prim;
unsigned int numverts;
unsigned int offset;
unsigned int vc_format;
} drm_radeon_tcl_prim_t;
static void radeon_cp_dispatch_vertex(struct drm_device * dev,
struct drm_file *file_priv,
struct drm_buf * buf,
drm_radeon_tcl_prim_t * prim)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts;
int nbox = sarea_priv->nbox;
int i = 0;
RING_LOCALS;
DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
prim->prim,
prim->vc_format, prim->start, prim->finish, prim->numverts);
if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
DRM_ERROR("bad prim %x numverts %d\n",
prim->prim, prim->numverts);
return;
}
do {
/* Emit the next cliprect */
if (i < nbox) {
radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
}
/* Emit the vertex buffer rendering commands */
BEGIN_RING(5);
OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
OUT_RING(offset);
OUT_RING(numverts);
OUT_RING(prim->vc_format);
OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
RADEON_COLOR_ORDER_RGBA |
RADEON_VTX_FMT_RADEON_MODE |
(numverts << RADEON_NUM_VERTICES_SHIFT));
ADVANCE_RING();
i++;
} while (i < nbox);
}
void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
RING_LOCALS;
buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
/* Emit the vertex buffer age */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
BEGIN_RING(3);
R600_DISPATCH_AGE(buf_priv->age);
ADVANCE_RING();
} else {
BEGIN_RING(2);
RADEON_DISPATCH_AGE(buf_priv->age);
ADVANCE_RING();
}
buf->pending = 1;
buf->used = 0;
}
static void radeon_cp_dispatch_indirect(struct drm_device * dev,
struct drm_buf * buf, int start, int end)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
if (start != end) {
int offset = (dev_priv->gart_buffers_offset
+ buf->offset + start);
int dwords = (end - start + 3) / sizeof(u32);
/* Indirect buffer data must be an even number of
* dwords, so if we've been given an odd number we must
* pad the data with a Type-2 CP packet.
*/
if (dwords & 1) {
u32 *data = (u32 *)
((char *)dev->agp_buffer_map->handle
+ buf->offset + start);
data[dwords++] = RADEON_CP_PACKET2;
}
/* Fire off the indirect buffer */
BEGIN_RING(3);
OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
OUT_RING(offset);
OUT_RING(dwords);
ADVANCE_RING();
}
}
static void radeon_cp_dispatch_indices(struct drm_device *dev,
struct drm_master *master,
struct drm_buf * elt_buf,
drm_radeon_tcl_prim_t * prim)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
int offset = dev_priv->gart_buffers_offset + prim->offset;
u32 *data;
int dwords;
int i = 0;
int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
int count = (prim->finish - start) / sizeof(u16);
int nbox = sarea_priv->nbox;
DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
prim->prim,
prim->vc_format,
prim->start, prim->finish, prim->offset, prim->numverts);
if (bad_prim_vertex_nr(prim->prim, count)) {
DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
return;
}
if (start >= prim->finish || (prim->start & 0x7)) {
DRM_ERROR("buffer prim %d\n", prim->prim);
return;
}
dwords = (prim->finish - prim->start + 3) / sizeof(u32);
data = (u32 *) ((char *)dev->agp_buffer_map->handle +
elt_buf->offset + prim->start);
data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
data[1] = offset;
data[2] = prim->numverts;
data[3] = prim->vc_format;
data[4] = (prim->prim |
RADEON_PRIM_WALK_IND |
RADEON_COLOR_ORDER_RGBA |
RADEON_VTX_FMT_RADEON_MODE |
(count << RADEON_NUM_VERTICES_SHIFT));
do {
if (i < nbox)
radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
radeon_cp_dispatch_indirect(dev, elt_buf,
prim->start, prim->finish);
i++;
} while (i < nbox);
}
#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
static int radeon_cp_dispatch_texture(struct drm_device * dev,
struct drm_file *file_priv,
drm_radeon_texture_t * tex,
drm_radeon_tex_image_t * image)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_buf *buf;
u32 format;
u32 *buffer;
const u8 __user *data;
int size, dwords, tex_width, blit_width, spitch;
u32 height;
int i;
u32 texpitch, microtile;
u32 offset, byte_offset;
RING_LOCALS;
if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
DRM_ERROR("Invalid destination offset\n");
return -EINVAL;
}
dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
/* Flush the pixel cache. This ensures no pixel data gets mixed
* up with the texture data from the host data blit, otherwise
* part of the texture image may be corrupted.
*/
BEGIN_RING(4);
RADEON_FLUSH_CACHE();
RADEON_WAIT_UNTIL_IDLE();
ADVANCE_RING();
/* The compiler won't optimize away a division by a variable,
* even if the only legal values are powers of two. Thus, we'll
* use a shift instead.
*/
switch (tex->format) {
case RADEON_TXFORMAT_ARGB8888:
case RADEON_TXFORMAT_RGBA8888:
format = RADEON_COLOR_FORMAT_ARGB8888;
tex_width = tex->width * 4;
blit_width = image->width * 4;
break;
case RADEON_TXFORMAT_AI88:
case RADEON_TXFORMAT_ARGB1555:
case RADEON_TXFORMAT_RGB565:
case RADEON_TXFORMAT_ARGB4444:
case RADEON_TXFORMAT_VYUY422:
case RADEON_TXFORMAT_YVYU422:
format = RADEON_COLOR_FORMAT_RGB565;
tex_width = tex->width * 2;
blit_width = image->width * 2;
break;
case RADEON_TXFORMAT_I8:
case RADEON_TXFORMAT_RGB332:
format = RADEON_COLOR_FORMAT_CI8;
tex_width = tex->width * 1;
blit_width = image->width * 1;
break;
default:
DRM_ERROR("invalid texture format %d\n", tex->format);
return -EINVAL;
}
spitch = blit_width >> 6;
if (spitch == 0 && image->height > 1)
return -EINVAL;
texpitch = tex->pitch;
if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
microtile = 1;
if (tex_width < 64) {
texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
/* we got tiled coordinates, untile them */
image->x *= 2;
}
} else
microtile = 0;
/* this might fail for zero-sized uploads - are those illegal? */
if (!radeon_check_offset(dev_priv, tex->offset + image->height *
blit_width - 1)) {
DRM_ERROR("Invalid final destination offset\n");
return -EINVAL;
}
DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
do {
DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
tex->offset >> 10, tex->pitch, tex->format,
image->x, image->y, image->width, image->height);
/* Make a copy of some parameters in case we have to
* update them for a multi-pass texture blit.
*/
height = image->height;
data = (const u8 __user *)image->data;
size = height * blit_width;
if (size > RADEON_MAX_TEXTURE_SIZE) {
height = RADEON_MAX_TEXTURE_SIZE / blit_width;
size = height * blit_width;
} else if (size < 4 && size > 0) {
size = 4;
} else if (size == 0) {
return 0;
}
buf = radeon_freelist_get(dev);
if (0 && !buf) {
radeon_do_cp_idle(dev_priv);
buf = radeon_freelist_get(dev);
}
if (!buf) {
DRM_DEBUG("EAGAIN\n");
if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
return -EFAULT;
return -EAGAIN;
}
/* Dispatch the indirect buffer.
*/
buffer =
(u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
dwords = size / 4;
#define RADEON_COPY_MT(_buf, _data, _width) \
do { \
if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
return -EFAULT; \
} \
} while(0)
if (microtile) {
/* texture micro tiling in use, minimum texture width is thus 16 bytes.
however, we cannot use blitter directly for texture width < 64 bytes,
since minimum tex pitch is 64 bytes and we need this to match
the texture width, otherwise the blitter will tile it wrong.
Thus, tiling manually in this case. Additionally, need to special
case tex height = 1, since our actual image will have height 2
and we need to ensure we don't read beyond the texture size
from user space. */
if (tex->height == 1) {
if (tex_width >= 64 || tex_width <= 16) {
RADEON_COPY_MT(buffer, data,
(int)(tex_width * sizeof(u32)));
} else if (tex_width == 32) {
RADEON_COPY_MT(buffer, data, 16);
RADEON_COPY_MT(buffer + 8,
data + 16, 16);
}
} else if (tex_width >= 64 || tex_width == 16) {
RADEON_COPY_MT(buffer, data,
(int)(dwords * sizeof(u32)));
} else if (tex_width < 16) {
for (i = 0; i < tex->height; i++) {
RADEON_COPY_MT(buffer, data, tex_width);
buffer += 4;
data += tex_width;
}
} else if (tex_width == 32) {
/* TODO: make sure this works when not fitting in one buffer
(i.e. 32bytes x 2048...) */
for (i = 0; i < tex->height; i += 2) {
RADEON_COPY_MT(buffer, data, 16);
data += 16;
RADEON_COPY_MT(buffer + 8, data, 16);
data += 16;
RADEON_COPY_MT(buffer + 4, data, 16);
data += 16;
RADEON_COPY_MT(buffer + 12, data, 16);
data += 16;
buffer += 16;
}
}
} else {
if (tex_width >= 32) {
/* Texture image width is larger than the minimum, so we
* can upload it directly.
*/
RADEON_COPY_MT(buffer, data,
(int)(dwords * sizeof(u32)));
} else {
/* Texture image width is less than the minimum, so we
* need to pad out each image scanline to the minimum
* width.
*/
for (i = 0; i < tex->height; i++) {
RADEON_COPY_MT(buffer, data, tex_width);
buffer += 8;
data += tex_width;
}
}
}
#undef RADEON_COPY_MT
byte_offset = (image->y & ~2047) * blit_width;
buf->file_priv = file_priv;
buf->used = size;
offset = dev_priv->gart_buffers_offset + buf->offset;
BEGIN_RING(9);
OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_NONE |
(format << 8) |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_ROP3_S |
RADEON_DP_SRC_SOURCE_MEMORY |
RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
OUT_RING((spitch << 22) | (offset >> 10));
OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
OUT_RING(0);
OUT_RING((image->x << 16) | (image->y % 2048));
OUT_RING((image->width << 16) | height);
RADEON_WAIT_UNTIL_2D_IDLE();
ADVANCE_RING();
COMMIT_RING();
radeon_cp_discard_buffer(dev, file_priv->master, buf);
/* Update the input parameters for next time */
image->y += height;
image->height -= height;
image->data = (const u8 __user *)image->data + size;
} while (image->height > 0);
/* Flush the pixel cache after the blit completes. This ensures
* the texture data is written out to memory before rendering
* continues.
*/
BEGIN_RING(4);
RADEON_FLUSH_CACHE();
RADEON_WAIT_UNTIL_2D_IDLE();
ADVANCE_RING();
COMMIT_RING();
return 0;
}
static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
int i;
RING_LOCALS;
DRM_DEBUG("\n");
BEGIN_RING(35);
OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
OUT_RING(0x00000000);
OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
for (i = 0; i < 32; i++) {
OUT_RING(stipple[i]);
}
ADVANCE_RING();
}
static void radeon_apply_surface_regs(int surf_index,
drm_radeon_private_t *dev_priv)
{
if (!dev_priv->mmio)
return;
radeon_do_cp_idle(dev_priv);
RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
dev_priv->surfaces[surf_index].flags);
RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
dev_priv->surfaces[surf_index].lower);
RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
dev_priv->surfaces[surf_index].upper);
}
/* Allocates a virtual surface
* doesn't always allocate a real surface, will stretch an existing
* surface when possible.
*
* Note that refcount can be at most 2, since during a free refcount=3
* might mean we have to allocate a new surface which might not always
* be available.
* For example : we allocate three contiguous surfaces ABC. If B is
* freed, we suddenly need two surfaces to store A and C, which might
* not always be available.
*/
static int alloc_surface(drm_radeon_surface_alloc_t *new,
drm_radeon_private_t *dev_priv,
struct drm_file *file_priv)
{
struct radeon_virt_surface *s;
int i;
int virt_surface_index;
uint32_t new_upper, new_lower;
new_lower = new->address;
new_upper = new_lower + new->size - 1;
/* sanity check */
if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
RADEON_SURF_ADDRESS_FIXED_MASK)
|| ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
return -1;
/* make sure there is no overlap with existing surfaces */
for (i = 0; i < RADEON_MAX_SURFACES; i++) {
if ((dev_priv->surfaces[i].refcount != 0) &&
(((new_lower >= dev_priv->surfaces[i].lower) &&
(new_lower < dev_priv->surfaces[i].upper)) ||
((new_lower < dev_priv->surfaces[i].lower) &&
(new_upper > dev_priv->surfaces[i].lower)))) {
return -1;
}
}
/* find a virtual surface */
for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
if (dev_priv->virt_surfaces[i].file_priv == NULL)
break;
if (i == 2 * RADEON_MAX_SURFACES) {
return -1;
}
virt_surface_index = i;
/* try to reuse an existing surface */
for (i = 0; i < RADEON_MAX_SURFACES; i++) {
/* extend before */
if ((dev_priv->surfaces[i].refcount == 1) &&
(new->flags == dev_priv->surfaces[i].flags) &&
(new_upper + 1 == dev_priv->surfaces[i].lower)) {
s = &(dev_priv->virt_surfaces[virt_surface_index]);
s->surface_index = i;
s->lower = new_lower;
s->upper = new_upper;
s->flags = new->flags;
s->file_priv = file_priv;
dev_priv->surfaces[i].refcount++;
dev_priv->surfaces[i].lower = s->lower;
radeon_apply_surface_regs(s->surface_index, dev_priv);
return virt_surface_index;
}
/* extend after */
if ((dev_priv->surfaces[i].refcount == 1) &&
(new->flags == dev_priv->surfaces[i].flags) &&
(new_lower == dev_priv->surfaces[i].upper + 1)) {
s = &(dev_priv->virt_surfaces[virt_surface_index]);
s->surface_index = i;
s->lower = new_lower;
s->upper = new_upper;
s->flags = new->flags;
s->file_priv = file_priv;
dev_priv->surfaces[i].refcount++;
dev_priv->surfaces[i].upper = s->upper;
radeon_apply_surface_regs(s->surface_index, dev_priv);
return virt_surface_index;
}
}
/* okay, we need a new one */
for (i = 0; i < RADEON_MAX_SURFACES; i++) {
if (dev_priv->surfaces[i].refcount == 0) {
s = &(dev_priv->virt_surfaces[virt_surface_index]);
s->surface_index = i;
s->lower = new_lower;
s->upper = new_upper;
s->flags = new->flags;
s->file_priv = file_priv;
dev_priv->surfaces[i].refcount = 1;
dev_priv->surfaces[i].lower = s->lower;
dev_priv->surfaces[i].upper = s->upper;
dev_priv->surfaces[i].flags = s->flags;
radeon_apply_surface_regs(s->surface_index, dev_priv);
return virt_surface_index;
}
}
/* we didn't find anything */
return -1;
}
static int free_surface(struct drm_file *file_priv,
drm_radeon_private_t * dev_priv,
int lower)
{
struct radeon_virt_surface *s;
int i;
/* find the virtual surface */
for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
s = &(dev_priv->virt_surfaces[i]);
if (s->file_priv) {
if ((lower == s->lower) && (file_priv == s->file_priv))
{
if (dev_priv->surfaces[s->surface_index].
lower == s->lower)
dev_priv->surfaces[s->surface_index].
lower = s->upper;
if (dev_priv->surfaces[s->surface_index].
upper == s->upper)
dev_priv->surfaces[s->surface_index].
upper = s->lower;
dev_priv->surfaces[s->surface_index].refcount--;
if (dev_priv->surfaces[s->surface_index].
refcount == 0)
dev_priv->surfaces[s->surface_index].
flags = 0;
s->file_priv = NULL;
radeon_apply_surface_regs(s->surface_index,
dev_priv);
return 0;
}
}
}
return 1;
}
static void radeon_surfaces_release(struct drm_file *file_priv,
drm_radeon_private_t * dev_priv)
{
int i;
for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
if (dev_priv->virt_surfaces[i].file_priv == file_priv)
free_surface(file_priv, dev_priv,
dev_priv->virt_surfaces[i].lower);
}
}
/* ================================================================
* IOCTL functions
*/
static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_surface_alloc_t *alloc = data;
if (alloc_surface(alloc, dev_priv, file_priv) == -1)
return -EINVAL;
else
return 0;
}
static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_surface_free_t *memfree = data;
if (free_surface(file_priv, dev_priv, memfree->address))
return -EINVAL;
else
return 0;
}
static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
drm_radeon_clear_t *clear = data;
drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
DRM_DEBUG("\n");
LOCK_TEST_WITH_RETURN(dev, file_priv);
RING_SPACE_TEST_WITH_RETURN(dev_priv);
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
sarea_priv->nbox * sizeof(depth_boxes[0])))
return -EFAULT;
radeon_cp_dispatch_clear(dev, file_priv->master, clear, depth_boxes);
COMMIT_RING();
return 0;
}
/* Not sure why this isn't set all the time:
*/
static int radeon_do_init_pageflip(struct drm_device *dev, struct drm_master *master)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = master->driver_priv;
RING_LOCALS;
DRM_DEBUG("\n");
BEGIN_RING(6);
RADEON_WAIT_UNTIL_3D_IDLE();
OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
RADEON_CRTC_OFFSET_FLIP_CNTL);
OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
RADEON_CRTC_OFFSET_FLIP_CNTL);
ADVANCE_RING();
dev_priv->page_flipping = 1;
if (master_priv->sarea_priv->pfCurrentPage != 1)
master_priv->sarea_priv->pfCurrentPage = 0;
return 0;
}
/* Swapping and flipping are different operations, need different ioctls.
* They can & should be intermixed to support multiple 3d windows.
*/
static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
LOCK_TEST_WITH_RETURN(dev, file_priv);
RING_SPACE_TEST_WITH_RETURN(dev_priv);
if (!dev_priv->page_flipping)
radeon_do_init_pageflip(dev, file_priv->master);
radeon_cp_dispatch_flip(dev, file_priv->master);
COMMIT_RING();
return 0;
}
static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
DRM_DEBUG("\n");
LOCK_TEST_WITH_RETURN(dev, file_priv);
RING_SPACE_TEST_WITH_RETURN(dev_priv);
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
r600_cp_dispatch_swap(dev, file_priv);
else
radeon_cp_dispatch_swap(dev, file_priv->master);
sarea_priv->ctx_owner = 0;
COMMIT_RING();
return 0;
}
static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_sarea_t *sarea_priv;
struct drm_device_dma *dma = dev->dma;
struct drm_buf *buf;
drm_radeon_vertex_t *vertex = data;
drm_radeon_tcl_prim_t prim;
LOCK_TEST_WITH_RETURN(dev, file_priv);
sarea_priv = master_priv->sarea_priv;
DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
DRM_ERROR("buffer index %d (of %d max)\n",
vertex->idx, dma->buf_count - 1);
return -EINVAL;
}
if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
DRM_ERROR("buffer prim %d\n", vertex->prim);
return -EINVAL;
}
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
buf = dma->buflist[vertex->idx];
if (buf->file_priv != file_priv) {
DRM_ERROR("process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->file_priv);
return -EINVAL;
}
if (buf->pending) {
DRM_ERROR("sending pending buffer %d\n", vertex->idx);
return -EINVAL;
}
/* Build up a prim_t record:
*/
if (vertex->count) {
buf->used = vertex->count; /* not used? */
if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
if (radeon_emit_state(dev_priv, file_priv,
&sarea_priv->context_state,
sarea_priv->tex_state,
sarea_priv->dirty)) {
DRM_ERROR("radeon_emit_state failed\n");
return -EINVAL;
}
sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
RADEON_UPLOAD_TEX1IMAGES |
RADEON_UPLOAD_TEX2IMAGES |
RADEON_REQUIRE_QUIESCENCE);
}
prim.start = 0;
prim.finish = vertex->count; /* unused */
prim.prim = vertex->prim;
prim.numverts = vertex->count;
prim.vc_format = sarea_priv->vc_format;
radeon_cp_dispatch_vertex(dev, file_priv, buf, &prim);
}
if (vertex->discard) {
radeon_cp_discard_buffer(dev, file_priv->master, buf);
}
COMMIT_RING();
return 0;
}
static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_sarea_t *sarea_priv;
struct drm_device_dma *dma = dev->dma;
struct drm_buf *buf;
drm_radeon_indices_t *elts = data;
drm_radeon_tcl_prim_t prim;
int count;
LOCK_TEST_WITH_RETURN(dev, file_priv);
sarea_priv = master_priv->sarea_priv;
DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
DRM_CURRENTPID, elts->idx, elts->start, elts->end,
elts->discard);
if (elts->idx < 0 || elts->idx >= dma->buf_count) {
DRM_ERROR("buffer index %d (of %d max)\n",
elts->idx, dma->buf_count - 1);
return -EINVAL;
}
if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
DRM_ERROR("buffer prim %d\n", elts->prim);
return -EINVAL;
}
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
buf = dma->buflist[elts->idx];
if (buf->file_priv != file_priv) {
DRM_ERROR("process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->file_priv);
return -EINVAL;
}
if (buf->pending) {
DRM_ERROR("sending pending buffer %d\n", elts->idx);
return -EINVAL;
}
count = (elts->end - elts->start) / sizeof(u16);
elts->start -= RADEON_INDEX_PRIM_OFFSET;
if (elts->start & 0x7) {
DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
return -EINVAL;
}
if (elts->start < buf->used) {
DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
return -EINVAL;
}
buf->used = elts->end;
if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
if (radeon_emit_state(dev_priv, file_priv,
&sarea_priv->context_state,
sarea_priv->tex_state,
sarea_priv->dirty)) {
DRM_ERROR("radeon_emit_state failed\n");
return -EINVAL;
}
sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
RADEON_UPLOAD_TEX1IMAGES |
RADEON_UPLOAD_TEX2IMAGES |
RADEON_REQUIRE_QUIESCENCE);
}
/* Build up a prim_t record:
*/
prim.start = elts->start;
prim.finish = elts->end;
prim.prim = elts->prim;
prim.offset = 0; /* offset from start of dma buffers */
prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
prim.vc_format = sarea_priv->vc_format;
radeon_cp_dispatch_indices(dev, file_priv->master, buf, &prim);
if (elts->discard) {
radeon_cp_discard_buffer(dev, file_priv->master, buf);
}
COMMIT_RING();
return 0;
}
static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_texture_t *tex = data;
drm_radeon_tex_image_t image;
int ret;
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (tex->image == NULL) {
DRM_ERROR("null texture image!\n");
return -EINVAL;
}
if (DRM_COPY_FROM_USER(&image,
(drm_radeon_tex_image_t __user *) tex->image,
sizeof(image)))
return -EFAULT;
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
else
ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
return ret;
}
static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_stipple_t *stipple = data;
u32 mask[32];
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
return -EFAULT;
RING_SPACE_TEST_WITH_RETURN(dev_priv);
radeon_cp_dispatch_stipple(dev, mask);
COMMIT_RING();
return 0;
}
static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_device_dma *dma = dev->dma;
struct drm_buf *buf;
drm_radeon_indirect_t *indirect = data;
RING_LOCALS;
LOCK_TEST_WITH_RETURN(dev, file_priv);
DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
indirect->idx, indirect->start, indirect->end,
indirect->discard);
if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
DRM_ERROR("buffer index %d (of %d max)\n",
indirect->idx, dma->buf_count - 1);
return -EINVAL;
}
buf = dma->buflist[indirect->idx];
if (buf->file_priv != file_priv) {
DRM_ERROR("process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->file_priv);
return -EINVAL;
}
if (buf->pending) {
DRM_ERROR("sending pending buffer %d\n", indirect->idx);
return -EINVAL;
}
if (indirect->start < buf->used) {
DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
indirect->start, buf->used);
return -EINVAL;
}
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
buf->used = indirect->end;
/* Dispatch the indirect buffer full of commands from the
* X server. This is insecure and is thus only available to
* privileged clients.
*/
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
else {
/* Wait for the 3D stream to idle before the indirect buffer
* containing 2D acceleration commands is processed.
*/
BEGIN_RING(2);
RADEON_WAIT_UNTIL_3D_IDLE();
ADVANCE_RING();
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
}
if (indirect->discard) {
radeon_cp_discard_buffer(dev, file_priv->master, buf);
}
COMMIT_RING();
return 0;
}
static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_sarea_t *sarea_priv;
struct drm_device_dma *dma = dev->dma;
struct drm_buf *buf;
drm_radeon_vertex2_t *vertex = data;
int i;
unsigned char laststate;
LOCK_TEST_WITH_RETURN(dev, file_priv);
sarea_priv = master_priv->sarea_priv;
DRM_DEBUG("pid=%d index=%d discard=%d\n",
DRM_CURRENTPID, vertex->idx, vertex->discard);
if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
DRM_ERROR("buffer index %d (of %d max)\n",
vertex->idx, dma->buf_count - 1);
return -EINVAL;
}
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
buf = dma->buflist[vertex->idx];
if (buf->file_priv != file_priv) {
DRM_ERROR("process %d using buffer owned by %p\n",
DRM_CURRENTPID, buf->file_priv);
return -EINVAL;
}
if (buf->pending) {
DRM_ERROR("sending pending buffer %d\n", vertex->idx);
return -EINVAL;
}
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
return -EINVAL;
for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
drm_radeon_prim_t prim;
drm_radeon_tcl_prim_t tclprim;
if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim)))
return -EFAULT;
if (prim.stateidx != laststate) {
drm_radeon_state_t state;
if (DRM_COPY_FROM_USER(&state,
&vertex->state[prim.stateidx],
sizeof(state)))
return -EFAULT;
if (radeon_emit_state2(dev_priv, file_priv, &state)) {
DRM_ERROR("radeon_emit_state2 failed\n");
return -EINVAL;
}
laststate = prim.stateidx;
}
tclprim.start = prim.start;
tclprim.finish = prim.finish;
tclprim.prim = prim.prim;
tclprim.vc_format = prim.vc_format;
if (prim.prim & RADEON_PRIM_WALK_IND) {
tclprim.offset = prim.numverts * 64;
tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
radeon_cp_dispatch_indices(dev, file_priv->master, buf, &tclprim);
} else {
tclprim.numverts = prim.numverts;
tclprim.offset = 0; /* not used */
radeon_cp_dispatch_vertex(dev, file_priv, buf, &tclprim);
}
if (sarea_priv->nbox == 1)
sarea_priv->nbox = 0;
}
if (vertex->discard) {
radeon_cp_discard_buffer(dev, file_priv->master, buf);
}
COMMIT_RING();
return 0;
}
static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
struct drm_file *file_priv,
drm_radeon_cmd_header_t header,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
int id = (int)header.packet.packet_id;
int sz, reg;
RING_LOCALS;
if (id >= RADEON_MAX_STATE_PACKETS)
return -EINVAL;
sz = packet[id].len;
reg = packet[id].start;
if (sz * sizeof(u32) > drm_buffer_unprocessed(cmdbuf->buffer)) {
DRM_ERROR("Packet size provided larger than data provided\n");
return -EINVAL;
}
if (radeon_check_and_fixup_packets(dev_priv, file_priv, id,
cmdbuf->buffer)) {
DRM_ERROR("Packet verification failed\n");
return -EINVAL;
}
BEGIN_RING(sz + 1);
OUT_RING(CP_PACKET0(reg, (sz - 1)));
OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
ADVANCE_RING();
return 0;
}
static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
int sz = header.scalars.count;
int start = header.scalars.offset;
int stride = header.scalars.stride;
RING_LOCALS;
BEGIN_RING(3 + sz);
OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
ADVANCE_RING();
return 0;
}
/* God this is ugly
*/
static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
int sz = header.scalars.count;
int start = ((unsigned int)header.scalars.offset) + 0x100;
int stride = header.scalars.stride;
RING_LOCALS;
BEGIN_RING(3 + sz);
OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
ADVANCE_RING();
return 0;
}
static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
int sz = header.vectors.count;
int start = header.vectors.offset;
int stride = header.vectors.stride;
RING_LOCALS;
BEGIN_RING(5 + sz);
OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
ADVANCE_RING();
return 0;
}
static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
drm_radeon_cmd_header_t header,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
int sz = header.veclinear.count * 4;
int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
RING_LOCALS;
if (!sz)
return 0;
if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
return -EINVAL;
BEGIN_RING(5 + sz);
OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
ADVANCE_RING();
return 0;
}
static int radeon_emit_packet3(struct drm_device * dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
unsigned int cmdsz;
int ret;
RING_LOCALS;
DRM_DEBUG("\n");
if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
cmdbuf, &cmdsz))) {
DRM_ERROR("Packet verification failed\n");
return ret;
}
BEGIN_RING(cmdsz);
OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
ADVANCE_RING();
return 0;
}
static int radeon_emit_packet3_cliprect(struct drm_device *dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf,
int orig_nbox)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_clip_rect box;
unsigned int cmdsz;
int ret;
struct drm_clip_rect __user *boxes = cmdbuf->boxes;
int i = 0;
RING_LOCALS;
DRM_DEBUG("\n");
if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
cmdbuf, &cmdsz))) {
DRM_ERROR("Packet verification failed\n");
return ret;
}
if (!orig_nbox)
goto out;
do {
if (i < cmdbuf->nbox) {
if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
return -EFAULT;
/* FIXME The second and subsequent times round
* this loop, send a WAIT_UNTIL_3D_IDLE before
* calling emit_clip_rect(). This fixes a
* lockup on fast machines when sending
* several cliprects with a cmdbuf, as when
* waving a 2D window over a 3D
* window. Something in the commands from user
* space seems to hang the card when they're
* sent several times in a row. That would be
* the correct place to fix it but this works
* around it until I can figure that out - Tim
* Smith */
if (i) {
BEGIN_RING(2);
RADEON_WAIT_UNTIL_3D_IDLE();
ADVANCE_RING();
}
radeon_emit_clip_rect(dev_priv, &box);
}
BEGIN_RING(cmdsz);
OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
ADVANCE_RING();
} while (++i < cmdbuf->nbox);
if (cmdbuf->nbox == 1)
cmdbuf->nbox = 0;
return 0;
out:
drm_buffer_advance(cmdbuf->buffer, cmdsz * 4);
return 0;
}
static int radeon_emit_wait(struct drm_device * dev, int flags)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG("%x\n", flags);
switch (flags) {
case RADEON_WAIT_2D:
BEGIN_RING(2);
RADEON_WAIT_UNTIL_2D_IDLE();
ADVANCE_RING();
break;
case RADEON_WAIT_3D:
BEGIN_RING(2);
RADEON_WAIT_UNTIL_3D_IDLE();
ADVANCE_RING();
break;
case RADEON_WAIT_2D | RADEON_WAIT_3D:
BEGIN_RING(2);
RADEON_WAIT_UNTIL_IDLE();
ADVANCE_RING();
break;
default:
return -EINVAL;
}
return 0;
}
static int radeon_cp_cmdbuf(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_device_dma *dma = dev->dma;
struct drm_buf *buf = NULL;
drm_radeon_cmd_header_t stack_header;
int idx;
drm_radeon_kcmd_buffer_t *cmdbuf = data;
int orig_nbox;
LOCK_TEST_WITH_RETURN(dev, file_priv);
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
return -EINVAL;
}
/* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
* races between checking values and using those values in other code,
* and simply to avoid a lot of function calls to copy in data.
*/
if (cmdbuf->bufsz != 0) {
int rv;
void __user *buffer = cmdbuf->buffer;
rv = drm_buffer_alloc(&cmdbuf->buffer, cmdbuf->bufsz);
if (rv)
return rv;
rv = drm_buffer_copy_from_user(cmdbuf->buffer, buffer,
cmdbuf->bufsz);
if (rv) {
drm_buffer_free(cmdbuf->buffer);
return rv;
}
} else
goto done;
orig_nbox = cmdbuf->nbox;
if (dev_priv->microcode_version == UCODE_R300) {
int temp;
temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
drm_buffer_free(cmdbuf->buffer);
return temp;
}
/* microcode_version != r300 */
while (drm_buffer_unprocessed(cmdbuf->buffer) >= sizeof(stack_header)) {
drm_radeon_cmd_header_t *header;
header = drm_buffer_read_object(cmdbuf->buffer,
sizeof(stack_header), &stack_header);
switch (header->header.cmd_type) {
case RADEON_CMD_PACKET:
DRM_DEBUG("RADEON_CMD_PACKET\n");
if (radeon_emit_packets
(dev_priv, file_priv, *header, cmdbuf)) {
DRM_ERROR("radeon_emit_packets failed\n");
goto err;
}
break;
case RADEON_CMD_SCALARS:
DRM_DEBUG("RADEON_CMD_SCALARS\n");
if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) {
DRM_ERROR("radeon_emit_scalars failed\n");
goto err;
}
break;
case RADEON_CMD_VECTORS:
DRM_DEBUG("RADEON_CMD_VECTORS\n");
if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) {
DRM_ERROR("radeon_emit_vectors failed\n");
goto err;
}
break;
case RADEON_CMD_DMA_DISCARD:
DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
idx = header->dma.buf_idx;
if (idx < 0 || idx >= dma->buf_count) {
DRM_ERROR("buffer index %d (of %d max)\n",
idx, dma->buf_count - 1);
goto err;
}
buf = dma->buflist[idx];
if (buf->file_priv != file_priv || buf->pending) {
DRM_ERROR("bad buffer %p %p %d\n",
buf->file_priv, file_priv,
buf->pending);
goto err;
}
radeon_cp_discard_buffer(dev, file_priv->master, buf);
break;
case RADEON_CMD_PACKET3:
DRM_DEBUG("RADEON_CMD_PACKET3\n");
if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
DRM_ERROR("radeon_emit_packet3 failed\n");
goto err;
}
break;
case RADEON_CMD_PACKET3_CLIP:
DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
if (radeon_emit_packet3_cliprect
(dev, file_priv, cmdbuf, orig_nbox)) {
DRM_ERROR("radeon_emit_packet3_clip failed\n");
goto err;
}
break;
case RADEON_CMD_SCALARS2:
DRM_DEBUG("RADEON_CMD_SCALARS2\n");
if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) {
DRM_ERROR("radeon_emit_scalars2 failed\n");
goto err;
}
break;
case RADEON_CMD_WAIT:
DRM_DEBUG("RADEON_CMD_WAIT\n");
if (radeon_emit_wait(dev, header->wait.flags)) {
DRM_ERROR("radeon_emit_wait failed\n");
goto err;
}
break;
case RADEON_CMD_VECLINEAR:
DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) {
DRM_ERROR("radeon_emit_veclinear failed\n");
goto err;
}
break;
default:
DRM_ERROR("bad cmd_type %d at byte %d\n",
header->header.cmd_type,
cmdbuf->buffer->iterator);
goto err;
}
}
drm_buffer_free(cmdbuf->buffer);
done:
DRM_DEBUG("DONE\n");
COMMIT_RING();
return 0;
err:
drm_buffer_free(cmdbuf->buffer);
return -EINVAL;
}
static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_getparam_t *param = data;
int value;
DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
switch (param->param) {
case RADEON_PARAM_GART_BUFFER_OFFSET:
value = dev_priv->gart_buffers_offset;
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
value = GET_SCRATCH(dev_priv, 0);
break;
case RADEON_PARAM_LAST_DISPATCH:
value = GET_SCRATCH(dev_priv, 1);
break;
case RADEON_PARAM_LAST_CLEAR:
dev_priv->stats.last_clear_reads++;
value = GET_SCRATCH(dev_priv, 2);
break;
case RADEON_PARAM_IRQ_NR:
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
value = 0;
else
value = drm_dev_to_irq(dev);
break;
case RADEON_PARAM_GART_BASE:
value = dev_priv->gart_vm_start;
break;
case RADEON_PARAM_REGISTER_HANDLE:
value = dev_priv->mmio->offset;
break;
case RADEON_PARAM_STATUS_HANDLE:
value = dev_priv->ring_rptr_offset;
break;
#if BITS_PER_LONG == 32
/*
* This ioctl() doesn't work on 64-bit platforms because hw_lock is a
* pointer which can't fit into an int-sized variable. According to
* Michel Dänzer, the ioctl() is only used on embedded platforms, so
* not supporting it shouldn't be a problem. If the same functionality
* is needed on 64-bit platforms, a new ioctl() would have to be added,
* so backwards-compatibility for the embedded platforms can be
* maintained. --davidm 4-Feb-2004.
*/
case RADEON_PARAM_SAREA_HANDLE:
/* The lock is the first dword in the sarea. */
/* no users of this parameter */
break;
#endif
case RADEON_PARAM_GART_TEX_HANDLE:
value = dev_priv->gart_textures_offset;
break;
case RADEON_PARAM_SCRATCH_OFFSET:
if (!dev_priv->writeback_works)
return -EINVAL;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
value = R600_SCRATCH_REG_OFFSET;
else
value = RADEON_SCRATCH_REG_OFFSET;
break;
case RADEON_PARAM_CARD_TYPE:
if (dev_priv->flags & RADEON_IS_PCIE)
value = RADEON_CARD_PCIE;
else if (dev_priv->flags & RADEON_IS_AGP)
value = RADEON_CARD_AGP;
else
value = RADEON_CARD_PCI;
break;
case RADEON_PARAM_VBLANK_CRTC:
value = radeon_vblank_crtc_get(dev);
break;
case RADEON_PARAM_FB_LOCATION:
value = radeon_read_fb_location(dev_priv);
break;
case RADEON_PARAM_NUM_GB_PIPES:
value = dev_priv->num_gb_pipes;
break;
case RADEON_PARAM_NUM_Z_PIPES:
value = dev_priv->num_z_pipes;
break;
default:
DRM_DEBUG("Invalid parameter %d\n", param->param);
return -EINVAL;
}
if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
DRM_ERROR("copy_to_user\n");
return -EFAULT;
}
return 0;
}
static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
drm_radeon_setparam_t *sp = data;
struct drm_radeon_driver_file_fields *radeon_priv;
switch (sp->param) {
case RADEON_SETPARAM_FB_LOCATION:
radeon_priv = file_priv->driver_priv;
radeon_priv->radeon_fb_delta = dev_priv->fb_location -
sp->value;
break;
case RADEON_SETPARAM_SWITCH_TILING:
if (sp->value == 0) {
DRM_DEBUG("color tiling disabled\n");
dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
if (master_priv->sarea_priv)
master_priv->sarea_priv->tiling_enabled = 0;
} else if (sp->value == 1) {
DRM_DEBUG("color tiling enabled\n");
dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
if (master_priv->sarea_priv)
master_priv->sarea_priv->tiling_enabled = 1;
}
break;
case RADEON_SETPARAM_PCIGART_LOCATION:
dev_priv->pcigart_offset = sp->value;
dev_priv->pcigart_offset_set = 1;
break;
case RADEON_SETPARAM_NEW_MEMMAP:
dev_priv->new_memmap = sp->value;
break;
case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
dev_priv->gart_info.table_size = sp->value;
if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
break;
case RADEON_SETPARAM_VBLANK_CRTC:
return radeon_vblank_crtc_set(dev, sp->value);
break;
default:
DRM_DEBUG("Invalid parameter %d\n", sp->param);
return -EINVAL;
}
return 0;
}
/* When a client dies:
* - Check for and clean up flipped page state
* - Free any alloced GART memory.
* - Free any alloced radeon surfaces.
*
* DRM infrastructure takes care of reclaiming dma buffers.
*/
void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
{
if (dev->dev_private) {
drm_radeon_private_t *dev_priv = dev->dev_private;
dev_priv->page_flipping = 0;
radeon_mem_release(file_priv, dev_priv->gart_heap);
radeon_mem_release(file_priv, dev_priv->fb_heap);
radeon_surfaces_release(file_priv, dev_priv);
}
}
void radeon_driver_lastclose(struct drm_device *dev)
{
radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
radeon_do_release(dev);
}
int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
struct drm_radeon_driver_file_fields *radeon_priv;
DRM_DEBUG("\n");
radeon_priv = kmalloc(sizeof(*radeon_priv), GFP_KERNEL);
if (!radeon_priv)
return -ENOMEM;
file_priv->driver_priv = radeon_priv;
if (dev_priv)
radeon_priv->radeon_fb_delta = dev_priv->fb_location;
else
radeon_priv->radeon_fb_delta = 0;
return 0;
}
void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_radeon_driver_file_fields *radeon_priv =
file_priv->driver_priv;
kfree(radeon_priv);
}
struct drm_ioctl_desc radeon_ioctls[] = {
DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
};
int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
| gpl-2.0 |
syhost/kernel_ef39s_ics_new | drivers/of/of_net.c | 2642 | 1732 | /*
* OF helpers for network devices.
*
* This file is released under the GPLv2
*
* Initially copied out of arch/powerpc/kernel/prom_parse.c
*/
#include <linux/etherdevice.h>
#include <linux/kernel.h>
#include <linux/of_net.h>
/**
* Search the device tree for the best MAC address to use. 'mac-address' is
* checked first, because that is supposed to contain to "most recent" MAC
* address. If that isn't set, then 'local-mac-address' is checked next,
* because that is the default address. If that isn't set, then the obsolete
* 'address' is checked, just in case we're using an old device tree.
*
* Note that the 'address' property is supposed to contain a virtual address of
* the register set, but some DTS files have redefined that property to be the
* MAC address.
*
* All-zero MAC addresses are rejected, because those could be properties that
* exist in the device tree, but were not set by U-Boot. For example, the
* DTS could define 'mac-address' and 'local-mac-address', with zero MAC
* addresses. Some older U-Boots only initialized 'local-mac-address'. In
* this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
* but is all zeros.
*/
const void *of_get_mac_address(struct device_node *np)
{
struct property *pp;
pp = of_find_property(np, "mac-address", NULL);
if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
return pp->value;
pp = of_find_property(np, "local-mac-address", NULL);
if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
return pp->value;
pp = of_find_property(np, "address", NULL);
if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
return pp->value;
return NULL;
}
EXPORT_SYMBOL(of_get_mac_address);
| gpl-2.0 |
RealVNC/Android-kernel-mako-NCM | net/core/datagram.c | 2642 | 18836 | /*
* SUCS NET3:
*
* Generic datagram handling routines. These are generic for all
* protocols. Possibly a generic IP version on top of these would
* make sense. Not tonight however 8-).
* This is used because UDP, RAW, PACKET, DDP, IPX, AX.25 and
* NetROM layer all have identical poll code and mostly
* identical recvmsg() code. So we share it here. The poll was
* shared before but buried in udp.c so I moved it.
*
* Authors: Alan Cox <alan@lxorguk.ukuu.org.uk>. (datagram_poll() from old
* udp.c code)
*
* Fixes:
* Alan Cox : NULL return from skb_peek_copy()
* understood
* Alan Cox : Rewrote skb_read_datagram to avoid the
* skb_peek_copy stuff.
* Alan Cox : Added support for SOCK_SEQPACKET.
* IPX can no longer use the SO_TYPE hack
* but AX.25 now works right, and SPX is
* feasible.
* Alan Cox : Fixed write poll of non IP protocol
* crash.
* Florian La Roche: Changed for my new skbuff handling.
* Darryl Miles : Fixed non-blocking SOCK_SEQPACKET.
* Linus Torvalds : BSD semantic fixes.
* Alan Cox : Datagram iovec handling
* Darryl Miles : Fixed non-blocking SOCK_STREAM.
* Alan Cox : POSIXisms
* Pete Wyckoff : Unconnected accept() fix.
*
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/uaccess.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/inet.h>
#include <linux/netdevice.h>
#include <linux/rtnetlink.h>
#include <linux/poll.h>
#include <linux/highmem.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <net/protocol.h>
#include <linux/skbuff.h>
#include <net/checksum.h>
#include <net/sock.h>
#include <net/tcp_states.h>
#include <trace/events/skb.h>
/*
* Is a socket 'connection oriented' ?
*/
static inline int connection_based(struct sock *sk)
{
return sk->sk_type == SOCK_SEQPACKET || sk->sk_type == SOCK_STREAM;
}
static int receiver_wake_function(wait_queue_t *wait, unsigned mode, int sync,
void *key)
{
unsigned long bits = (unsigned long)key;
/*
* Avoid a wakeup if event not interesting for us
*/
if (bits && !(bits & (POLLIN | POLLERR)))
return 0;
return autoremove_wake_function(wait, mode, sync, key);
}
/*
* Wait for a packet..
*/
static int wait_for_packet(struct sock *sk, int *err, long *timeo_p)
{
int error;
DEFINE_WAIT_FUNC(wait, receiver_wake_function);
prepare_to_wait_exclusive(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
/* Socket errors? */
error = sock_error(sk);
if (error)
goto out_err;
if (!skb_queue_empty(&sk->sk_receive_queue))
goto out;
/* Socket shut down? */
if (sk->sk_shutdown & RCV_SHUTDOWN)
goto out_noerr;
/* Sequenced packets can come disconnected.
* If so we report the problem
*/
error = -ENOTCONN;
if (connection_based(sk) &&
!(sk->sk_state == TCP_ESTABLISHED || sk->sk_state == TCP_LISTEN))
goto out_err;
/* handle signals */
if (signal_pending(current))
goto interrupted;
error = 0;
*timeo_p = schedule_timeout(*timeo_p);
out:
finish_wait(sk_sleep(sk), &wait);
return error;
interrupted:
error = sock_intr_errno(*timeo_p);
out_err:
*err = error;
goto out;
out_noerr:
*err = 0;
error = 1;
goto out;
}
/**
* __skb_recv_datagram - Receive a datagram skbuff
* @sk: socket
* @flags: MSG_ flags
* @off: an offset in bytes to peek skb from. Returns an offset
* within an skb where data actually starts
* @peeked: returns non-zero if this packet has been seen before
* @err: error code returned
*
* Get a datagram skbuff, understands the peeking, nonblocking wakeups
* and possible races. This replaces identical code in packet, raw and
* udp, as well as the IPX AX.25 and Appletalk. It also finally fixes
* the long standing peek and read race for datagram sockets. If you
* alter this routine remember it must be re-entrant.
*
* This function will lock the socket if a skb is returned, so the caller
* needs to unlock the socket in that case (usually by calling
* skb_free_datagram)
*
* * It does not lock socket since today. This function is
* * free of race conditions. This measure should/can improve
* * significantly datagram socket latencies at high loads,
* * when data copying to user space takes lots of time.
* * (BTW I've just killed the last cli() in IP/IPv6/core/netlink/packet
* * 8) Great win.)
* * --ANK (980729)
*
* The order of the tests when we find no data waiting are specified
* quite explicitly by POSIX 1003.1g, don't change them without having
* the standard around please.
*/
struct sk_buff *__skb_recv_datagram(struct sock *sk, unsigned flags,
int *peeked, int *off, int *err)
{
struct sk_buff *skb;
long timeo;
/*
* Caller is allowed not to check sk->sk_err before skb_recv_datagram()
*/
int error = sock_error(sk);
if (error)
goto no_packet;
timeo = sock_rcvtimeo(sk, flags & MSG_DONTWAIT);
do {
/* Again only user level code calls this function, so nothing
* interrupt level will suddenly eat the receive_queue.
*
* Look at current nfs client by the way...
* However, this function was correct in any case. 8)
*/
unsigned long cpu_flags;
struct sk_buff_head *queue = &sk->sk_receive_queue;
spin_lock_irqsave(&queue->lock, cpu_flags);
skb_queue_walk(queue, skb) {
*peeked = skb->peeked;
if (flags & MSG_PEEK) {
if (*off >= skb->len) {
*off -= skb->len;
continue;
}
skb->peeked = 1;
atomic_inc(&skb->users);
} else
__skb_unlink(skb, queue);
spin_unlock_irqrestore(&queue->lock, cpu_flags);
return skb;
}
spin_unlock_irqrestore(&queue->lock, cpu_flags);
/* User doesn't want to wait */
error = -EAGAIN;
if (!timeo)
goto no_packet;
} while (!wait_for_packet(sk, err, &timeo));
return NULL;
no_packet:
*err = error;
return NULL;
}
EXPORT_SYMBOL(__skb_recv_datagram);
struct sk_buff *skb_recv_datagram(struct sock *sk, unsigned flags,
int noblock, int *err)
{
int peeked, off = 0;
return __skb_recv_datagram(sk, flags | (noblock ? MSG_DONTWAIT : 0),
&peeked, &off, err);
}
EXPORT_SYMBOL(skb_recv_datagram);
void skb_free_datagram(struct sock *sk, struct sk_buff *skb)
{
consume_skb(skb);
sk_mem_reclaim_partial(sk);
}
EXPORT_SYMBOL(skb_free_datagram);
void skb_free_datagram_locked(struct sock *sk, struct sk_buff *skb)
{
bool slow;
if (likely(atomic_read(&skb->users) == 1))
smp_rmb();
else if (likely(!atomic_dec_and_test(&skb->users)))
return;
slow = lock_sock_fast(sk);
skb_orphan(skb);
sk_mem_reclaim_partial(sk);
unlock_sock_fast(sk, slow);
/* skb is now orphaned, can be freed outside of locked section */
trace_kfree_skb(skb, skb_free_datagram_locked);
__kfree_skb(skb);
}
EXPORT_SYMBOL(skb_free_datagram_locked);
/**
* skb_kill_datagram - Free a datagram skbuff forcibly
* @sk: socket
* @skb: datagram skbuff
* @flags: MSG_ flags
*
* This function frees a datagram skbuff that was received by
* skb_recv_datagram. The flags argument must match the one
* used for skb_recv_datagram.
*
* If the MSG_PEEK flag is set, and the packet is still on the
* receive queue of the socket, it will be taken off the queue
* before it is freed.
*
* This function currently only disables BH when acquiring the
* sk_receive_queue lock. Therefore it must not be used in a
* context where that lock is acquired in an IRQ context.
*
* It returns 0 if the packet was removed by us.
*/
int skb_kill_datagram(struct sock *sk, struct sk_buff *skb, unsigned int flags)
{
int err = 0;
if (flags & MSG_PEEK) {
err = -ENOENT;
spin_lock_bh(&sk->sk_receive_queue.lock);
if (skb == skb_peek(&sk->sk_receive_queue)) {
__skb_unlink(skb, &sk->sk_receive_queue);
atomic_dec(&skb->users);
err = 0;
}
spin_unlock_bh(&sk->sk_receive_queue.lock);
}
kfree_skb(skb);
atomic_inc(&sk->sk_drops);
sk_mem_reclaim_partial(sk);
return err;
}
EXPORT_SYMBOL(skb_kill_datagram);
/**
* skb_copy_datagram_iovec - Copy a datagram to an iovec.
* @skb: buffer to copy
* @offset: offset in the buffer to start copying from
* @to: io vector to copy to
* @len: amount of data to copy from buffer to iovec
*
* Note: the iovec is modified during the copy.
*/
int skb_copy_datagram_iovec(const struct sk_buff *skb, int offset,
struct iovec *to, int len)
{
int start = skb_headlen(skb);
int i, copy = start - offset;
struct sk_buff *frag_iter;
trace_skb_copy_datagram_iovec(skb, len);
/* Copy header. */
if (copy > 0) {
if (copy > len)
copy = len;
if (memcpy_toiovec(to, skb->data + offset, copy))
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
}
/* Copy paged appendix. Hmm... why does this look so complicated? */
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
int end;
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
WARN_ON(start > offset + len);
end = start + skb_frag_size(frag);
if ((copy = end - offset) > 0) {
int err;
u8 *vaddr;
struct page *page = skb_frag_page(frag);
if (copy > len)
copy = len;
vaddr = kmap(page);
err = memcpy_toiovec(to, vaddr + frag->page_offset +
offset - start, copy);
kunmap(page);
if (err)
goto fault;
if (!(len -= copy))
return 0;
offset += copy;
}
start = end;
}
skb_walk_frags(skb, frag_iter) {
int end;
WARN_ON(start > offset + len);
end = start + frag_iter->len;
if ((copy = end - offset) > 0) {
if (copy > len)
copy = len;
if (skb_copy_datagram_iovec(frag_iter,
offset - start,
to, copy))
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
}
start = end;
}
if (!len)
return 0;
fault:
return -EFAULT;
}
EXPORT_SYMBOL(skb_copy_datagram_iovec);
/**
* skb_copy_datagram_const_iovec - Copy a datagram to an iovec.
* @skb: buffer to copy
* @offset: offset in the buffer to start copying from
* @to: io vector to copy to
* @to_offset: offset in the io vector to start copying to
* @len: amount of data to copy from buffer to iovec
*
* Returns 0 or -EFAULT.
* Note: the iovec is not modified during the copy.
*/
int skb_copy_datagram_const_iovec(const struct sk_buff *skb, int offset,
const struct iovec *to, int to_offset,
int len)
{
int start = skb_headlen(skb);
int i, copy = start - offset;
struct sk_buff *frag_iter;
/* Copy header. */
if (copy > 0) {
if (copy > len)
copy = len;
if (memcpy_toiovecend(to, skb->data + offset, to_offset, copy))
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
to_offset += copy;
}
/* Copy paged appendix. Hmm... why does this look so complicated? */
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
int end;
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
WARN_ON(start > offset + len);
end = start + skb_frag_size(frag);
if ((copy = end - offset) > 0) {
int err;
u8 *vaddr;
struct page *page = skb_frag_page(frag);
if (copy > len)
copy = len;
vaddr = kmap(page);
err = memcpy_toiovecend(to, vaddr + frag->page_offset +
offset - start, to_offset, copy);
kunmap(page);
if (err)
goto fault;
if (!(len -= copy))
return 0;
offset += copy;
to_offset += copy;
}
start = end;
}
skb_walk_frags(skb, frag_iter) {
int end;
WARN_ON(start > offset + len);
end = start + frag_iter->len;
if ((copy = end - offset) > 0) {
if (copy > len)
copy = len;
if (skb_copy_datagram_const_iovec(frag_iter,
offset - start,
to, to_offset,
copy))
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
to_offset += copy;
}
start = end;
}
if (!len)
return 0;
fault:
return -EFAULT;
}
EXPORT_SYMBOL(skb_copy_datagram_const_iovec);
/**
* skb_copy_datagram_from_iovec - Copy a datagram from an iovec.
* @skb: buffer to copy
* @offset: offset in the buffer to start copying to
* @from: io vector to copy to
* @from_offset: offset in the io vector to start copying from
* @len: amount of data to copy to buffer from iovec
*
* Returns 0 or -EFAULT.
* Note: the iovec is not modified during the copy.
*/
int skb_copy_datagram_from_iovec(struct sk_buff *skb, int offset,
const struct iovec *from, int from_offset,
int len)
{
int start = skb_headlen(skb);
int i, copy = start - offset;
struct sk_buff *frag_iter;
/* Copy header. */
if (copy > 0) {
if (copy > len)
copy = len;
if (memcpy_fromiovecend(skb->data + offset, from, from_offset,
copy))
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
from_offset += copy;
}
/* Copy paged appendix. Hmm... why does this look so complicated? */
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
int end;
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
WARN_ON(start > offset + len);
end = start + skb_frag_size(frag);
if ((copy = end - offset) > 0) {
int err;
u8 *vaddr;
struct page *page = skb_frag_page(frag);
if (copy > len)
copy = len;
vaddr = kmap(page);
err = memcpy_fromiovecend(vaddr + frag->page_offset +
offset - start,
from, from_offset, copy);
kunmap(page);
if (err)
goto fault;
if (!(len -= copy))
return 0;
offset += copy;
from_offset += copy;
}
start = end;
}
skb_walk_frags(skb, frag_iter) {
int end;
WARN_ON(start > offset + len);
end = start + frag_iter->len;
if ((copy = end - offset) > 0) {
if (copy > len)
copy = len;
if (skb_copy_datagram_from_iovec(frag_iter,
offset - start,
from,
from_offset,
copy))
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
from_offset += copy;
}
start = end;
}
if (!len)
return 0;
fault:
return -EFAULT;
}
EXPORT_SYMBOL(skb_copy_datagram_from_iovec);
static int skb_copy_and_csum_datagram(const struct sk_buff *skb, int offset,
u8 __user *to, int len,
__wsum *csump)
{
int start = skb_headlen(skb);
int i, copy = start - offset;
struct sk_buff *frag_iter;
int pos = 0;
/* Copy header. */
if (copy > 0) {
int err = 0;
if (copy > len)
copy = len;
*csump = csum_and_copy_to_user(skb->data + offset, to, copy,
*csump, &err);
if (err)
goto fault;
if ((len -= copy) == 0)
return 0;
offset += copy;
to += copy;
pos = copy;
}
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
int end;
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
WARN_ON(start > offset + len);
end = start + skb_frag_size(frag);
if ((copy = end - offset) > 0) {
__wsum csum2;
int err = 0;
u8 *vaddr;
struct page *page = skb_frag_page(frag);
if (copy > len)
copy = len;
vaddr = kmap(page);
csum2 = csum_and_copy_to_user(vaddr +
frag->page_offset +
offset - start,
to, copy, 0, &err);
kunmap(page);
if (err)
goto fault;
*csump = csum_block_add(*csump, csum2, pos);
if (!(len -= copy))
return 0;
offset += copy;
to += copy;
pos += copy;
}
start = end;
}
skb_walk_frags(skb, frag_iter) {
int end;
WARN_ON(start > offset + len);
end = start + frag_iter->len;
if ((copy = end - offset) > 0) {
__wsum csum2 = 0;
if (copy > len)
copy = len;
if (skb_copy_and_csum_datagram(frag_iter,
offset - start,
to, copy,
&csum2))
goto fault;
*csump = csum_block_add(*csump, csum2, pos);
if ((len -= copy) == 0)
return 0;
offset += copy;
to += copy;
pos += copy;
}
start = end;
}
if (!len)
return 0;
fault:
return -EFAULT;
}
__sum16 __skb_checksum_complete_head(struct sk_buff *skb, int len)
{
__sum16 sum;
sum = csum_fold(skb_checksum(skb, 0, len, skb->csum));
if (likely(!sum)) {
if (unlikely(skb->ip_summed == CHECKSUM_COMPLETE))
netdev_rx_csum_fault(skb->dev);
skb->ip_summed = CHECKSUM_UNNECESSARY;
}
return sum;
}
EXPORT_SYMBOL(__skb_checksum_complete_head);
__sum16 __skb_checksum_complete(struct sk_buff *skb)
{
return __skb_checksum_complete_head(skb, skb->len);
}
EXPORT_SYMBOL(__skb_checksum_complete);
/**
* skb_copy_and_csum_datagram_iovec - Copy and checkum skb to user iovec.
* @skb: skbuff
* @hlen: hardware length
* @iov: io vector
*
* Caller _must_ check that skb will fit to this iovec.
*
* Returns: 0 - success.
* -EINVAL - checksum failure.
* -EFAULT - fault during copy. Beware, in this case iovec
* can be modified!
*/
int skb_copy_and_csum_datagram_iovec(struct sk_buff *skb,
int hlen, struct iovec *iov)
{
__wsum csum;
int chunk = skb->len - hlen;
if (!chunk)
return 0;
/* Skip filled elements.
* Pretty silly, look at memcpy_toiovec, though 8)
*/
while (!iov->iov_len)
iov++;
if (iov->iov_len < chunk) {
if (__skb_checksum_complete(skb))
goto csum_error;
if (skb_copy_datagram_iovec(skb, hlen, iov, chunk))
goto fault;
} else {
csum = csum_partial(skb->data, hlen, skb->csum);
if (skb_copy_and_csum_datagram(skb, hlen, iov->iov_base,
chunk, &csum))
goto fault;
if (csum_fold(csum))
goto csum_error;
if (unlikely(skb->ip_summed == CHECKSUM_COMPLETE))
netdev_rx_csum_fault(skb->dev);
iov->iov_len -= chunk;
iov->iov_base += chunk;
}
return 0;
csum_error:
return -EINVAL;
fault:
return -EFAULT;
}
EXPORT_SYMBOL(skb_copy_and_csum_datagram_iovec);
/**
* datagram_poll - generic datagram poll
* @file: file struct
* @sock: socket
* @wait: poll table
*
* Datagram poll: Again totally generic. This also handles
* sequenced packet sockets providing the socket receive queue
* is only ever holding data ready to receive.
*
* Note: when you _don't_ use this routine for this protocol,
* and you use a different write policy from sock_writeable()
* then please supply your own write_space callback.
*/
unsigned int datagram_poll(struct file *file, struct socket *sock,
poll_table *wait)
{
struct sock *sk = sock->sk;
unsigned int mask;
sock_poll_wait(file, sk_sleep(sk), wait);
mask = 0;
/* exceptional events? */
if (sk->sk_err || !skb_queue_empty(&sk->sk_error_queue))
mask |= POLLERR;
if (sk->sk_shutdown & RCV_SHUTDOWN)
mask |= POLLRDHUP | POLLIN | POLLRDNORM;
if (sk->sk_shutdown == SHUTDOWN_MASK)
mask |= POLLHUP;
/* readable? */
if (!skb_queue_empty(&sk->sk_receive_queue))
mask |= POLLIN | POLLRDNORM;
/* Connection-based need to check for termination and startup */
if (connection_based(sk)) {
if (sk->sk_state == TCP_CLOSE)
mask |= POLLHUP;
/* connection hasn't started yet? */
if (sk->sk_state == TCP_SYN_SENT)
return mask;
}
/* writable? */
if (sock_writeable(sk))
mask |= POLLOUT | POLLWRNORM | POLLWRBAND;
else
set_bit(SOCK_ASYNC_NOSPACE, &sk->sk_socket->flags);
return mask;
}
EXPORT_SYMBOL(datagram_poll);
| gpl-2.0 |
mastero9017/Crystal | arch/x86/kvm/cpuid.c | 4690 | 17598 | /*
* Kernel-based Virtual Machine driver for Linux
* cpuid support routines
*
* derived from arch/x86/kvm/x86.c
*
* Copyright 2011 Red Hat, Inc. and/or its affiliates.
* Copyright IBM Corporation, 2008
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
*/
#include <linux/kvm_host.h>
#include <linux/module.h>
#include <linux/vmalloc.h>
#include <linux/uaccess.h>
#include <asm/user.h>
#include <asm/xsave.h>
#include "cpuid.h"
#include "lapic.h"
#include "mmu.h"
#include "trace.h"
void kvm_update_cpuid(struct kvm_vcpu *vcpu)
{
struct kvm_cpuid_entry2 *best;
struct kvm_lapic *apic = vcpu->arch.apic;
best = kvm_find_cpuid_entry(vcpu, 1, 0);
if (!best)
return;
/* Update OSXSAVE bit */
if (cpu_has_xsave && best->function == 0x1) {
best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
best->ecx |= bit(X86_FEATURE_OSXSAVE);
}
if (apic) {
if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
apic->lapic_timer.timer_mode_mask = 3 << 17;
else
apic->lapic_timer.timer_mode_mask = 1 << 17;
}
kvm_pmu_cpuid_update(vcpu);
}
static int is_efer_nx(void)
{
unsigned long long efer = 0;
rdmsrl_safe(MSR_EFER, &efer);
return efer & EFER_NX;
}
static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
{
int i;
struct kvm_cpuid_entry2 *e, *entry;
entry = NULL;
for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
e = &vcpu->arch.cpuid_entries[i];
if (e->function == 0x80000001) {
entry = e;
break;
}
}
if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
entry->edx &= ~(1 << 20);
printk(KERN_INFO "kvm: guest NX capability removed\n");
}
}
/* when an old userspace process fills a new kernel module */
int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
struct kvm_cpuid *cpuid,
struct kvm_cpuid_entry __user *entries)
{
int r, i;
struct kvm_cpuid_entry *cpuid_entries;
r = -E2BIG;
if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
goto out;
r = -ENOMEM;
cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
if (!cpuid_entries)
goto out;
r = -EFAULT;
if (copy_from_user(cpuid_entries, entries,
cpuid->nent * sizeof(struct kvm_cpuid_entry)))
goto out_free;
for (i = 0; i < cpuid->nent; i++) {
vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
vcpu->arch.cpuid_entries[i].index = 0;
vcpu->arch.cpuid_entries[i].flags = 0;
vcpu->arch.cpuid_entries[i].padding[0] = 0;
vcpu->arch.cpuid_entries[i].padding[1] = 0;
vcpu->arch.cpuid_entries[i].padding[2] = 0;
}
vcpu->arch.cpuid_nent = cpuid->nent;
cpuid_fix_nx_cap(vcpu);
r = 0;
kvm_apic_set_version(vcpu);
kvm_x86_ops->cpuid_update(vcpu);
kvm_update_cpuid(vcpu);
out_free:
vfree(cpuid_entries);
out:
return r;
}
int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
struct kvm_cpuid2 *cpuid,
struct kvm_cpuid_entry2 __user *entries)
{
int r;
r = -E2BIG;
if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
goto out;
r = -EFAULT;
if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
goto out;
vcpu->arch.cpuid_nent = cpuid->nent;
kvm_apic_set_version(vcpu);
kvm_x86_ops->cpuid_update(vcpu);
kvm_update_cpuid(vcpu);
return 0;
out:
return r;
}
int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
struct kvm_cpuid2 *cpuid,
struct kvm_cpuid_entry2 __user *entries)
{
int r;
r = -E2BIG;
if (cpuid->nent < vcpu->arch.cpuid_nent)
goto out;
r = -EFAULT;
if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
goto out;
return 0;
out:
cpuid->nent = vcpu->arch.cpuid_nent;
return r;
}
static void cpuid_mask(u32 *word, int wordnum)
{
*word &= boot_cpu_data.x86_capability[wordnum];
}
static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
u32 index)
{
entry->function = function;
entry->index = index;
cpuid_count(entry->function, entry->index,
&entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
entry->flags = 0;
}
static bool supported_xcr0_bit(unsigned bit)
{
u64 mask = ((u64)1 << bit);
return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
}
#define F(x) bit(X86_FEATURE_##x)
static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
u32 index, int *nent, int maxnent)
{
int r;
unsigned f_nx = is_efer_nx() ? F(NX) : 0;
#ifdef CONFIG_X86_64
unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
? F(GBPAGES) : 0;
unsigned f_lm = F(LM);
#else
unsigned f_gbpages = 0;
unsigned f_lm = 0;
#endif
unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
/* cpuid 1.edx */
const u32 kvm_supported_word0_x86_features =
F(FPU) | F(VME) | F(DE) | F(PSE) |
F(TSC) | F(MSR) | F(PAE) | F(MCE) |
F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
0 /* Reserved, DS, ACPI */ | F(MMX) |
F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
0 /* HTT, TM, Reserved, PBE */;
/* cpuid 0x80000001.edx */
const u32 kvm_supported_word1_x86_features =
F(FPU) | F(VME) | F(DE) | F(PSE) |
F(TSC) | F(MSR) | F(PAE) | F(MCE) |
F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
F(PAT) | F(PSE36) | 0 /* Reserved */ |
f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
/* cpuid 1.ecx */
const u32 kvm_supported_word4_x86_features =
F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
0 /* DS-CPL, VMX, SMX, EST */ |
0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
0 /* Reserved, DCA */ | F(XMM4_1) |
F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
F(F16C) | F(RDRAND);
/* cpuid 0x80000001.ecx */
const u32 kvm_supported_word6_x86_features =
F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
/* cpuid 0xC0000001.edx */
const u32 kvm_supported_word5_x86_features =
F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
F(PMM) | F(PMM_EN);
/* cpuid 7.0.ebx */
const u32 kvm_supported_word9_x86_features =
F(FSGSBASE) | F(BMI1) | F(AVX2) | F(SMEP) | F(BMI2) | F(ERMS);
/* all calls to cpuid_count() should be made on the same cpu */
get_cpu();
r = -E2BIG;
if (*nent >= maxnent)
goto out;
do_cpuid_1_ent(entry, function, index);
++*nent;
switch (function) {
case 0:
entry->eax = min(entry->eax, (u32)0xd);
break;
case 1:
entry->edx &= kvm_supported_word0_x86_features;
cpuid_mask(&entry->edx, 0);
entry->ecx &= kvm_supported_word4_x86_features;
cpuid_mask(&entry->ecx, 4);
/* we support x2apic emulation even if host does not support
* it since we emulate x2apic in software */
entry->ecx |= F(X2APIC);
break;
/* function 2 entries are STATEFUL. That is, repeated cpuid commands
* may return different values. This forces us to get_cpu() before
* issuing the first command, and also to emulate this annoying behavior
* in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
case 2: {
int t, times = entry->eax & 0xff;
entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
for (t = 1; t < times; ++t) {
if (*nent >= maxnent)
goto out;
do_cpuid_1_ent(&entry[t], function, 0);
entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
++*nent;
}
break;
}
/* function 4 has additional index. */
case 4: {
int i, cache_type;
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
/* read more entries until cache_type is zero */
for (i = 1; ; ++i) {
if (*nent >= maxnent)
goto out;
cache_type = entry[i - 1].eax & 0x1f;
if (!cache_type)
break;
do_cpuid_1_ent(&entry[i], function, i);
entry[i].flags |=
KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
++*nent;
}
break;
}
case 7: {
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
/* Mask ebx against host capbability word 9 */
if (index == 0) {
entry->ebx &= kvm_supported_word9_x86_features;
cpuid_mask(&entry->ebx, 9);
} else
entry->ebx = 0;
entry->eax = 0;
entry->ecx = 0;
entry->edx = 0;
break;
}
case 9:
break;
case 0xa: { /* Architectural Performance Monitoring */
struct x86_pmu_capability cap;
union cpuid10_eax eax;
union cpuid10_edx edx;
perf_get_x86_pmu_capability(&cap);
/*
* Only support guest architectural pmu on a host
* with architectural pmu.
*/
if (!cap.version)
memset(&cap, 0, sizeof(cap));
eax.split.version_id = min(cap.version, 2);
eax.split.num_counters = cap.num_counters_gp;
eax.split.bit_width = cap.bit_width_gp;
eax.split.mask_length = cap.events_mask_len;
edx.split.num_counters_fixed = cap.num_counters_fixed;
edx.split.bit_width_fixed = cap.bit_width_fixed;
edx.split.reserved = 0;
entry->eax = eax.full;
entry->ebx = cap.events_mask;
entry->ecx = 0;
entry->edx = edx.full;
break;
}
/* function 0xb has additional index. */
case 0xb: {
int i, level_type;
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
/* read more entries until level_type is zero */
for (i = 1; ; ++i) {
if (*nent >= maxnent)
goto out;
level_type = entry[i - 1].ecx & 0xff00;
if (!level_type)
break;
do_cpuid_1_ent(&entry[i], function, i);
entry[i].flags |=
KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
++*nent;
}
break;
}
case 0xd: {
int idx, i;
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
for (idx = 1, i = 1; idx < 64; ++idx) {
if (*nent >= maxnent)
goto out;
do_cpuid_1_ent(&entry[i], function, idx);
if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
continue;
entry[i].flags |=
KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
++*nent;
++i;
}
break;
}
case KVM_CPUID_SIGNATURE: {
char signature[12] = "KVMKVMKVM\0\0";
u32 *sigptr = (u32 *)signature;
entry->eax = 0;
entry->ebx = sigptr[0];
entry->ecx = sigptr[1];
entry->edx = sigptr[2];
break;
}
case KVM_CPUID_FEATURES:
entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
(1 << KVM_FEATURE_NOP_IO_DELAY) |
(1 << KVM_FEATURE_CLOCKSOURCE2) |
(1 << KVM_FEATURE_ASYNC_PF) |
(1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
if (sched_info_on())
entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
entry->ebx = 0;
entry->ecx = 0;
entry->edx = 0;
break;
case 0x80000000:
entry->eax = min(entry->eax, 0x8000001a);
break;
case 0x80000001:
entry->edx &= kvm_supported_word1_x86_features;
cpuid_mask(&entry->edx, 1);
entry->ecx &= kvm_supported_word6_x86_features;
cpuid_mask(&entry->ecx, 6);
break;
case 0x80000008: {
unsigned g_phys_as = (entry->eax >> 16) & 0xff;
unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
unsigned phys_as = entry->eax & 0xff;
if (!g_phys_as)
g_phys_as = phys_as;
entry->eax = g_phys_as | (virt_as << 8);
entry->ebx = entry->edx = 0;
break;
}
case 0x80000019:
entry->ecx = entry->edx = 0;
break;
case 0x8000001a:
break;
case 0x8000001d:
break;
/*Add support for Centaur's CPUID instruction*/
case 0xC0000000:
/*Just support up to 0xC0000004 now*/
entry->eax = min(entry->eax, 0xC0000004);
break;
case 0xC0000001:
entry->edx &= kvm_supported_word5_x86_features;
cpuid_mask(&entry->edx, 5);
break;
case 3: /* Processor serial number */
case 5: /* MONITOR/MWAIT */
case 6: /* Thermal management */
case 0x80000007: /* Advanced power management */
case 0xC0000002:
case 0xC0000003:
case 0xC0000004:
default:
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
break;
}
kvm_x86_ops->set_supported_cpuid(function, entry);
r = 0;
out:
put_cpu();
return r;
}
#undef F
struct kvm_cpuid_param {
u32 func;
u32 idx;
bool has_leaf_count;
bool (*qualifier)(struct kvm_cpuid_param *param);
};
static bool is_centaur_cpu(struct kvm_cpuid_param *param)
{
return boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR;
}
int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
struct kvm_cpuid_entry2 __user *entries)
{
struct kvm_cpuid_entry2 *cpuid_entries;
int limit, nent = 0, r = -E2BIG, i;
u32 func;
static struct kvm_cpuid_param param[] = {
{ .func = 0, .has_leaf_count = true },
{ .func = 0x80000000, .has_leaf_count = true },
{ .func = 0xC0000000, .qualifier = is_centaur_cpu, .has_leaf_count = true },
{ .func = KVM_CPUID_SIGNATURE },
{ .func = KVM_CPUID_FEATURES },
};
if (cpuid->nent < 1)
goto out;
if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
cpuid->nent = KVM_MAX_CPUID_ENTRIES;
r = -ENOMEM;
cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
if (!cpuid_entries)
goto out;
r = 0;
for (i = 0; i < ARRAY_SIZE(param); i++) {
struct kvm_cpuid_param *ent = ¶m[i];
if (ent->qualifier && !ent->qualifier(ent))
continue;
r = do_cpuid_ent(&cpuid_entries[nent], ent->func, ent->idx,
&nent, cpuid->nent);
if (r)
goto out_free;
if (!ent->has_leaf_count)
continue;
limit = cpuid_entries[nent - 1].eax;
for (func = ent->func + 1; func <= limit && nent < cpuid->nent && r == 0; ++func)
r = do_cpuid_ent(&cpuid_entries[nent], func, ent->idx,
&nent, cpuid->nent);
if (r)
goto out_free;
}
r = -EFAULT;
if (copy_to_user(entries, cpuid_entries,
nent * sizeof(struct kvm_cpuid_entry2)))
goto out_free;
cpuid->nent = nent;
r = 0;
out_free:
vfree(cpuid_entries);
out:
return r;
}
static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
{
struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
int j, nent = vcpu->arch.cpuid_nent;
e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
/* when no next entry is found, the current entry[i] is reselected */
for (j = i + 1; ; j = (j + 1) % nent) {
struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
if (ej->function == e->function) {
ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
return j;
}
}
return 0; /* silence gcc, even though control never reaches here */
}
/* find an entry with matching function, matching index (if needed), and that
* should be read next (if it's stateful) */
static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
u32 function, u32 index)
{
if (e->function != function)
return 0;
if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
return 0;
if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
!(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
return 0;
return 1;
}
struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
u32 function, u32 index)
{
int i;
struct kvm_cpuid_entry2 *best = NULL;
for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
struct kvm_cpuid_entry2 *e;
e = &vcpu->arch.cpuid_entries[i];
if (is_matching_cpuid_entry(e, function, index)) {
if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
move_to_next_stateful_cpuid_entry(vcpu, i);
best = e;
break;
}
}
return best;
}
EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
{
struct kvm_cpuid_entry2 *best;
best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
if (!best || best->eax < 0x80000008)
goto not_found;
best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
if (best)
return best->eax & 0xff;
not_found:
return 36;
}
/*
* If no match is found, check whether we exceed the vCPU's limit
* and return the content of the highest valid _standard_ leaf instead.
* This is to satisfy the CPUID specification.
*/
static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
u32 function, u32 index)
{
struct kvm_cpuid_entry2 *maxlevel;
maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
if (!maxlevel || maxlevel->eax >= function)
return NULL;
if (function & 0x80000000) {
maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
if (!maxlevel)
return NULL;
}
return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
}
void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
{
u32 function, index;
struct kvm_cpuid_entry2 *best;
function = kvm_register_read(vcpu, VCPU_REGS_RAX);
index = kvm_register_read(vcpu, VCPU_REGS_RCX);
kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
best = kvm_find_cpuid_entry(vcpu, function, index);
if (!best)
best = check_cpuid_limit(vcpu, function, index);
if (best) {
kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
}
kvm_x86_ops->skip_emulated_instruction(vcpu);
trace_kvm_cpuid(function,
kvm_register_read(vcpu, VCPU_REGS_RAX),
kvm_register_read(vcpu, VCPU_REGS_RBX),
kvm_register_read(vcpu, VCPU_REGS_RCX),
kvm_register_read(vcpu, VCPU_REGS_RDX));
}
EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
| gpl-2.0 |
zeroblade1984/Xiaomi-MSM8226 | drivers/media/video/ths7303.c | 4946 | 3475 | /*
* ths7303- THS7303 Video Amplifier driver
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed .as is. WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-chip-ident.h>
MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
MODULE_AUTHOR("Chaithrika U S");
MODULE_LICENSE("GPL");
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level 0-1");
/* following function is used to set ths7303 */
static int ths7303_setvalue(struct v4l2_subdev *sd, v4l2_std_id std)
{
int err = 0;
u8 val;
struct i2c_client *client;
client = v4l2_get_subdevdata(sd);
if (std & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
val = 0x02;
v4l2_dbg(1, debug, sd, "setting value for SDTV format\n");
} else {
val = 0x00;
v4l2_dbg(1, debug, sd, "disabling all channels\n");
}
err |= i2c_smbus_write_byte_data(client, 0x01, val);
err |= i2c_smbus_write_byte_data(client, 0x02, val);
err |= i2c_smbus_write_byte_data(client, 0x03, val);
if (err)
v4l2_err(sd, "write failed\n");
return err;
}
static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
{
return ths7303_setvalue(sd, norm);
}
static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
struct v4l2_dbg_chip_ident *chip)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_THS7303, 0);
}
static const struct v4l2_subdev_video_ops ths7303_video_ops = {
.s_std_output = ths7303_s_std_output,
};
static const struct v4l2_subdev_core_ops ths7303_core_ops = {
.g_chip_ident = ths7303_g_chip_ident,
};
static const struct v4l2_subdev_ops ths7303_ops = {
.core = &ths7303_core_ops,
.video = &ths7303_video_ops,
};
static int ths7303_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct v4l2_subdev *sd;
v4l2_std_id std_id = V4L2_STD_NTSC;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
sd = kzalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
if (sd == NULL)
return -ENOMEM;
v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
return ths7303_setvalue(sd, std_id);
}
static int ths7303_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
v4l2_device_unregister_subdev(sd);
kfree(sd);
return 0;
}
static const struct i2c_device_id ths7303_id[] = {
{"ths7303", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, ths7303_id);
static struct i2c_driver ths7303_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "ths7303",
},
.probe = ths7303_probe,
.remove = ths7303_remove,
.id_table = ths7303_id,
};
module_i2c_driver(ths7303_driver);
| gpl-2.0 |
PsychoGame/android_kernel_lge_msm8974-caf | drivers/media/video/ths7303.c | 4946 | 3475 | /*
* ths7303- THS7303 Video Amplifier driver
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed .as is. WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-chip-ident.h>
MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
MODULE_AUTHOR("Chaithrika U S");
MODULE_LICENSE("GPL");
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level 0-1");
/* following function is used to set ths7303 */
static int ths7303_setvalue(struct v4l2_subdev *sd, v4l2_std_id std)
{
int err = 0;
u8 val;
struct i2c_client *client;
client = v4l2_get_subdevdata(sd);
if (std & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
val = 0x02;
v4l2_dbg(1, debug, sd, "setting value for SDTV format\n");
} else {
val = 0x00;
v4l2_dbg(1, debug, sd, "disabling all channels\n");
}
err |= i2c_smbus_write_byte_data(client, 0x01, val);
err |= i2c_smbus_write_byte_data(client, 0x02, val);
err |= i2c_smbus_write_byte_data(client, 0x03, val);
if (err)
v4l2_err(sd, "write failed\n");
return err;
}
static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
{
return ths7303_setvalue(sd, norm);
}
static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
struct v4l2_dbg_chip_ident *chip)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_THS7303, 0);
}
static const struct v4l2_subdev_video_ops ths7303_video_ops = {
.s_std_output = ths7303_s_std_output,
};
static const struct v4l2_subdev_core_ops ths7303_core_ops = {
.g_chip_ident = ths7303_g_chip_ident,
};
static const struct v4l2_subdev_ops ths7303_ops = {
.core = &ths7303_core_ops,
.video = &ths7303_video_ops,
};
static int ths7303_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct v4l2_subdev *sd;
v4l2_std_id std_id = V4L2_STD_NTSC;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
v4l_info(client, "chip found @ 0x%x (%s)\n",
client->addr << 1, client->adapter->name);
sd = kzalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
if (sd == NULL)
return -ENOMEM;
v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
return ths7303_setvalue(sd, std_id);
}
static int ths7303_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
v4l2_device_unregister_subdev(sd);
kfree(sd);
return 0;
}
static const struct i2c_device_id ths7303_id[] = {
{"ths7303", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, ths7303_id);
static struct i2c_driver ths7303_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "ths7303",
},
.probe = ths7303_probe,
.remove = ths7303_remove,
.id_table = ths7303_id,
};
module_i2c_driver(ths7303_driver);
| gpl-2.0 |
markbencze/android_kernel_lge_hammerhead | fs/btrfs/zlib.c | 4946 | 10583 | /*
* Copyright (C) 2008 Oracle. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License v2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 021110-1307, USA.
*
* Based on jffs2 zlib code:
* Copyright © 2001-2007 Red Hat, Inc.
* Created by David Woodhouse <dwmw2@infradead.org>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/zlib.h>
#include <linux/zutil.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/pagemap.h>
#include <linux/bio.h>
#include "compression.h"
struct workspace {
z_stream inf_strm;
z_stream def_strm;
char *buf;
struct list_head list;
};
static void zlib_free_workspace(struct list_head *ws)
{
struct workspace *workspace = list_entry(ws, struct workspace, list);
vfree(workspace->def_strm.workspace);
vfree(workspace->inf_strm.workspace);
kfree(workspace->buf);
kfree(workspace);
}
static struct list_head *zlib_alloc_workspace(void)
{
struct workspace *workspace;
workspace = kzalloc(sizeof(*workspace), GFP_NOFS);
if (!workspace)
return ERR_PTR(-ENOMEM);
workspace->def_strm.workspace = vmalloc(zlib_deflate_workspacesize(
MAX_WBITS, MAX_MEM_LEVEL));
workspace->inf_strm.workspace = vmalloc(zlib_inflate_workspacesize());
workspace->buf = kmalloc(PAGE_CACHE_SIZE, GFP_NOFS);
if (!workspace->def_strm.workspace ||
!workspace->inf_strm.workspace || !workspace->buf)
goto fail;
INIT_LIST_HEAD(&workspace->list);
return &workspace->list;
fail:
zlib_free_workspace(&workspace->list);
return ERR_PTR(-ENOMEM);
}
static int zlib_compress_pages(struct list_head *ws,
struct address_space *mapping,
u64 start, unsigned long len,
struct page **pages,
unsigned long nr_dest_pages,
unsigned long *out_pages,
unsigned long *total_in,
unsigned long *total_out,
unsigned long max_out)
{
struct workspace *workspace = list_entry(ws, struct workspace, list);
int ret;
char *data_in;
char *cpage_out;
int nr_pages = 0;
struct page *in_page = NULL;
struct page *out_page = NULL;
unsigned long bytes_left;
*out_pages = 0;
*total_out = 0;
*total_in = 0;
if (Z_OK != zlib_deflateInit(&workspace->def_strm, 3)) {
printk(KERN_WARNING "deflateInit failed\n");
ret = -1;
goto out;
}
workspace->def_strm.total_in = 0;
workspace->def_strm.total_out = 0;
in_page = find_get_page(mapping, start >> PAGE_CACHE_SHIFT);
data_in = kmap(in_page);
out_page = alloc_page(GFP_NOFS | __GFP_HIGHMEM);
if (out_page == NULL) {
ret = -1;
goto out;
}
cpage_out = kmap(out_page);
pages[0] = out_page;
nr_pages = 1;
workspace->def_strm.next_in = data_in;
workspace->def_strm.next_out = cpage_out;
workspace->def_strm.avail_out = PAGE_CACHE_SIZE;
workspace->def_strm.avail_in = min(len, PAGE_CACHE_SIZE);
while (workspace->def_strm.total_in < len) {
ret = zlib_deflate(&workspace->def_strm, Z_SYNC_FLUSH);
if (ret != Z_OK) {
printk(KERN_DEBUG "btrfs deflate in loop returned %d\n",
ret);
zlib_deflateEnd(&workspace->def_strm);
ret = -1;
goto out;
}
/* we're making it bigger, give up */
if (workspace->def_strm.total_in > 8192 &&
workspace->def_strm.total_in <
workspace->def_strm.total_out) {
ret = -1;
goto out;
}
/* we need another page for writing out. Test this
* before the total_in so we will pull in a new page for
* the stream end if required
*/
if (workspace->def_strm.avail_out == 0) {
kunmap(out_page);
if (nr_pages == nr_dest_pages) {
out_page = NULL;
ret = -1;
goto out;
}
out_page = alloc_page(GFP_NOFS | __GFP_HIGHMEM);
if (out_page == NULL) {
ret = -1;
goto out;
}
cpage_out = kmap(out_page);
pages[nr_pages] = out_page;
nr_pages++;
workspace->def_strm.avail_out = PAGE_CACHE_SIZE;
workspace->def_strm.next_out = cpage_out;
}
/* we're all done */
if (workspace->def_strm.total_in >= len)
break;
/* we've read in a full page, get a new one */
if (workspace->def_strm.avail_in == 0) {
if (workspace->def_strm.total_out > max_out)
break;
bytes_left = len - workspace->def_strm.total_in;
kunmap(in_page);
page_cache_release(in_page);
start += PAGE_CACHE_SIZE;
in_page = find_get_page(mapping,
start >> PAGE_CACHE_SHIFT);
data_in = kmap(in_page);
workspace->def_strm.avail_in = min(bytes_left,
PAGE_CACHE_SIZE);
workspace->def_strm.next_in = data_in;
}
}
workspace->def_strm.avail_in = 0;
ret = zlib_deflate(&workspace->def_strm, Z_FINISH);
zlib_deflateEnd(&workspace->def_strm);
if (ret != Z_STREAM_END) {
ret = -1;
goto out;
}
if (workspace->def_strm.total_out >= workspace->def_strm.total_in) {
ret = -1;
goto out;
}
ret = 0;
*total_out = workspace->def_strm.total_out;
*total_in = workspace->def_strm.total_in;
out:
*out_pages = nr_pages;
if (out_page)
kunmap(out_page);
if (in_page) {
kunmap(in_page);
page_cache_release(in_page);
}
return ret;
}
static int zlib_decompress_biovec(struct list_head *ws, struct page **pages_in,
u64 disk_start,
struct bio_vec *bvec,
int vcnt,
size_t srclen)
{
struct workspace *workspace = list_entry(ws, struct workspace, list);
int ret = 0, ret2;
int wbits = MAX_WBITS;
char *data_in;
size_t total_out = 0;
unsigned long page_in_index = 0;
unsigned long page_out_index = 0;
unsigned long total_pages_in = (srclen + PAGE_CACHE_SIZE - 1) /
PAGE_CACHE_SIZE;
unsigned long buf_start;
unsigned long pg_offset;
data_in = kmap(pages_in[page_in_index]);
workspace->inf_strm.next_in = data_in;
workspace->inf_strm.avail_in = min_t(size_t, srclen, PAGE_CACHE_SIZE);
workspace->inf_strm.total_in = 0;
workspace->inf_strm.total_out = 0;
workspace->inf_strm.next_out = workspace->buf;
workspace->inf_strm.avail_out = PAGE_CACHE_SIZE;
pg_offset = 0;
/* If it's deflate, and it's got no preset dictionary, then
we can tell zlib to skip the adler32 check. */
if (srclen > 2 && !(data_in[1] & PRESET_DICT) &&
((data_in[0] & 0x0f) == Z_DEFLATED) &&
!(((data_in[0]<<8) + data_in[1]) % 31)) {
wbits = -((data_in[0] >> 4) + 8);
workspace->inf_strm.next_in += 2;
workspace->inf_strm.avail_in -= 2;
}
if (Z_OK != zlib_inflateInit2(&workspace->inf_strm, wbits)) {
printk(KERN_WARNING "inflateInit failed\n");
return -1;
}
while (workspace->inf_strm.total_in < srclen) {
ret = zlib_inflate(&workspace->inf_strm, Z_NO_FLUSH);
if (ret != Z_OK && ret != Z_STREAM_END)
break;
buf_start = total_out;
total_out = workspace->inf_strm.total_out;
/* we didn't make progress in this inflate call, we're done */
if (buf_start == total_out)
break;
ret2 = btrfs_decompress_buf2page(workspace->buf, buf_start,
total_out, disk_start,
bvec, vcnt,
&page_out_index, &pg_offset);
if (ret2 == 0) {
ret = 0;
goto done;
}
workspace->inf_strm.next_out = workspace->buf;
workspace->inf_strm.avail_out = PAGE_CACHE_SIZE;
if (workspace->inf_strm.avail_in == 0) {
unsigned long tmp;
kunmap(pages_in[page_in_index]);
page_in_index++;
if (page_in_index >= total_pages_in) {
data_in = NULL;
break;
}
data_in = kmap(pages_in[page_in_index]);
workspace->inf_strm.next_in = data_in;
tmp = srclen - workspace->inf_strm.total_in;
workspace->inf_strm.avail_in = min(tmp,
PAGE_CACHE_SIZE);
}
}
if (ret != Z_STREAM_END)
ret = -1;
else
ret = 0;
done:
zlib_inflateEnd(&workspace->inf_strm);
if (data_in)
kunmap(pages_in[page_in_index]);
return ret;
}
static int zlib_decompress(struct list_head *ws, unsigned char *data_in,
struct page *dest_page,
unsigned long start_byte,
size_t srclen, size_t destlen)
{
struct workspace *workspace = list_entry(ws, struct workspace, list);
int ret = 0;
int wbits = MAX_WBITS;
unsigned long bytes_left = destlen;
unsigned long total_out = 0;
char *kaddr;
workspace->inf_strm.next_in = data_in;
workspace->inf_strm.avail_in = srclen;
workspace->inf_strm.total_in = 0;
workspace->inf_strm.next_out = workspace->buf;
workspace->inf_strm.avail_out = PAGE_CACHE_SIZE;
workspace->inf_strm.total_out = 0;
/* If it's deflate, and it's got no preset dictionary, then
we can tell zlib to skip the adler32 check. */
if (srclen > 2 && !(data_in[1] & PRESET_DICT) &&
((data_in[0] & 0x0f) == Z_DEFLATED) &&
!(((data_in[0]<<8) + data_in[1]) % 31)) {
wbits = -((data_in[0] >> 4) + 8);
workspace->inf_strm.next_in += 2;
workspace->inf_strm.avail_in -= 2;
}
if (Z_OK != zlib_inflateInit2(&workspace->inf_strm, wbits)) {
printk(KERN_WARNING "inflateInit failed\n");
return -1;
}
while (bytes_left > 0) {
unsigned long buf_start;
unsigned long buf_offset;
unsigned long bytes;
unsigned long pg_offset = 0;
ret = zlib_inflate(&workspace->inf_strm, Z_NO_FLUSH);
if (ret != Z_OK && ret != Z_STREAM_END)
break;
buf_start = total_out;
total_out = workspace->inf_strm.total_out;
if (total_out == buf_start) {
ret = -1;
break;
}
if (total_out <= start_byte)
goto next;
if (total_out > start_byte && buf_start < start_byte)
buf_offset = start_byte - buf_start;
else
buf_offset = 0;
bytes = min(PAGE_CACHE_SIZE - pg_offset,
PAGE_CACHE_SIZE - buf_offset);
bytes = min(bytes, bytes_left);
kaddr = kmap_atomic(dest_page);
memcpy(kaddr + pg_offset, workspace->buf + buf_offset, bytes);
kunmap_atomic(kaddr);
pg_offset += bytes;
bytes_left -= bytes;
next:
workspace->inf_strm.next_out = workspace->buf;
workspace->inf_strm.avail_out = PAGE_CACHE_SIZE;
}
if (ret != Z_STREAM_END && bytes_left != 0)
ret = -1;
else
ret = 0;
zlib_inflateEnd(&workspace->inf_strm);
return ret;
}
struct btrfs_compress_op btrfs_zlib_compress = {
.alloc_workspace = zlib_alloc_workspace,
.free_workspace = zlib_free_workspace,
.compress_pages = zlib_compress_pages,
.decompress_biovec = zlib_decompress_biovec,
.decompress = zlib_decompress,
};
| gpl-2.0 |
MikeC84/android_kernel_motorola_shamu | drivers/ide/ide-cs.c | 5202 | 12339 | /*======================================================================
A driver for PCMCIA IDE/ATA disk cards
The contents of this file are subject to the Mozilla Public
License Version 1.1 (the "License"); you may not use this file
except in compliance with the License. You may obtain a copy of
the License at http://www.mozilla.org/MPL/
Software distributed under the License is distributed on an "AS
IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
implied. See the License for the specific language governing
rights and limitations under the License.
The initial developer of the original code is David A. Hinds
<dahinds@users.sourceforge.net>. Portions created by David A. Hinds
are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
Alternatively, the contents of this file may be used under the
terms of the GNU General Public License version 2 (the "GPL"), in
which case the provisions of the GPL are applicable instead of the
above. If you wish to allow the use of your version of this file
only under the terms of the GPL and not to allow others to use
your version of this file under the MPL, indicate your decision
by deleting the provisions above and replace them with the notice
and other provisions required by the GPL. If you do not delete
the provisions above, a recipient may use your version of this
file under either the MPL or the GPL.
======================================================================*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/ioport.h>
#include <linux/ide.h>
#include <linux/major.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/ds.h>
#include <pcmcia/cisreg.h>
#include <pcmcia/ciscode.h>
#define DRV_NAME "ide-cs"
/*====================================================================*/
/* Module parameters */
MODULE_AUTHOR("David Hinds <dahinds@users.sourceforge.net>");
MODULE_DESCRIPTION("PCMCIA ATA/IDE card driver");
MODULE_LICENSE("Dual MPL/GPL");
/*====================================================================*/
typedef struct ide_info_t {
struct pcmcia_device *p_dev;
struct ide_host *host;
int ndev;
} ide_info_t;
static void ide_release(struct pcmcia_device *);
static int ide_config(struct pcmcia_device *);
static void ide_detach(struct pcmcia_device *p_dev);
static int ide_probe(struct pcmcia_device *link)
{
ide_info_t *info;
dev_dbg(&link->dev, "ide_attach()\n");
/* Create new ide device */
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->p_dev = link;
link->priv = info;
link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO |
CONF_AUTO_SET_VPP | CONF_AUTO_CHECK_VCC;
return ide_config(link);
} /* ide_attach */
static void ide_detach(struct pcmcia_device *link)
{
ide_info_t *info = link->priv;
dev_dbg(&link->dev, "ide_detach(0x%p)\n", link);
ide_release(link);
kfree(info);
} /* ide_detach */
static const struct ide_port_ops idecs_port_ops = {
.quirkproc = ide_undecoded_slave,
};
static const struct ide_port_info idecs_port_info = {
.port_ops = &idecs_port_ops,
.host_flags = IDE_HFLAG_NO_DMA,
.irq_flags = IRQF_SHARED,
.chipset = ide_pci,
};
static struct ide_host *idecs_register(unsigned long io, unsigned long ctl,
unsigned long irq, struct pcmcia_device *handle)
{
struct ide_host *host;
ide_hwif_t *hwif;
int i, rc;
struct ide_hw hw, *hws[] = { &hw };
if (!request_region(io, 8, DRV_NAME)) {
printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
DRV_NAME, io, io + 7);
return NULL;
}
if (!request_region(ctl, 1, DRV_NAME)) {
printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
DRV_NAME, ctl);
release_region(io, 8);
return NULL;
}
memset(&hw, 0, sizeof(hw));
ide_std_init_ports(&hw, io, ctl);
hw.irq = irq;
hw.dev = &handle->dev;
rc = ide_host_add(&idecs_port_info, hws, 1, &host);
if (rc)
goto out_release;
hwif = host->ports[0];
if (hwif->present)
return host;
/* retry registration in case device is still spinning up */
for (i = 0; i < 10; i++) {
msleep(100);
ide_port_scan(hwif);
if (hwif->present)
return host;
}
return host;
out_release:
release_region(ctl, 1);
release_region(io, 8);
return NULL;
}
static int pcmcia_check_one_config(struct pcmcia_device *pdev, void *priv_data)
{
int *is_kme = priv_data;
if ((pdev->resource[0]->flags & IO_DATA_PATH_WIDTH)
!= IO_DATA_PATH_WIDTH_8) {
pdev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
pdev->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
}
pdev->resource[1]->flags &= ~IO_DATA_PATH_WIDTH;
pdev->resource[1]->flags |= IO_DATA_PATH_WIDTH_8;
if (pdev->resource[1]->end) {
pdev->resource[0]->end = 8;
pdev->resource[1]->end = (*is_kme) ? 2 : 1;
} else {
if (pdev->resource[0]->end < 16)
return -ENODEV;
}
return pcmcia_request_io(pdev);
}
static int ide_config(struct pcmcia_device *link)
{
ide_info_t *info = link->priv;
int ret = 0, is_kme = 0;
unsigned long io_base, ctl_base;
struct ide_host *host;
dev_dbg(&link->dev, "ide_config(0x%p)\n", link);
is_kme = ((link->manf_id == MANFID_KME) &&
((link->card_id == PRODID_KME_KXLC005_A) ||
(link->card_id == PRODID_KME_KXLC005_B)));
if (pcmcia_loop_config(link, pcmcia_check_one_config, &is_kme)) {
link->config_flags &= ~CONF_AUTO_CHECK_VCC;
if (pcmcia_loop_config(link, pcmcia_check_one_config, &is_kme))
goto failed; /* No suitable config found */
}
io_base = link->resource[0]->start;
if (link->resource[1]->end)
ctl_base = link->resource[1]->start;
else
ctl_base = link->resource[0]->start + 0x0e;
if (!link->irq)
goto failed;
ret = pcmcia_enable_device(link);
if (ret)
goto failed;
/* disable drive interrupts during IDE probe */
outb(0x02, ctl_base);
/* special setup for KXLC005 card */
if (is_kme)
outb(0x81, ctl_base+1);
host = idecs_register(io_base, ctl_base, link->irq, link);
if (host == NULL && resource_size(link->resource[0]) == 0x20) {
outb(0x02, ctl_base + 0x10);
host = idecs_register(io_base + 0x10, ctl_base + 0x10,
link->irq, link);
}
if (host == NULL)
goto failed;
info->ndev = 1;
info->host = host;
dev_info(&link->dev, "ide-cs: hd%c: Vpp = %d.%d\n",
'a' + host->ports[0]->index * 2,
link->vpp / 10, link->vpp % 10);
return 0;
failed:
ide_release(link);
return -ENODEV;
} /* ide_config */
static void ide_release(struct pcmcia_device *link)
{
ide_info_t *info = link->priv;
struct ide_host *host = info->host;
dev_dbg(&link->dev, "ide_release(0x%p)\n", link);
if (info->ndev) {
ide_hwif_t *hwif = host->ports[0];
unsigned long data_addr, ctl_addr;
data_addr = hwif->io_ports.data_addr;
ctl_addr = hwif->io_ports.ctl_addr;
ide_host_remove(host);
info->ndev = 0;
release_region(ctl_addr, 1);
release_region(data_addr, 8);
}
pcmcia_disable_device(link);
} /* ide_release */
static const struct pcmcia_device_id ide_ids[] = {
PCMCIA_DEVICE_FUNC_ID(4),
PCMCIA_DEVICE_MANF_CARD(0x0000, 0x0000), /* Corsair */
PCMCIA_DEVICE_MANF_CARD(0x0007, 0x0000), /* Hitachi */
PCMCIA_DEVICE_MANF_CARD(0x000a, 0x0000), /* I-O Data CFA */
PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */
PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704),
PCMCIA_DEVICE_MANF_CARD(0x0032, 0x2904),
PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401), /* SanDisk CFA */
PCMCIA_DEVICE_MANF_CARD(0x004f, 0x0000), /* Kingston */
PCMCIA_DEVICE_MANF_CARD(0x0097, 0x1620), /* TI emulated */
PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */
PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d),
PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */
PCMCIA_DEVICE_MANF_CARD(0x0319, 0x0000), /* Hitachi */
PCMCIA_DEVICE_MANF_CARD(0x2080, 0x0001),
PCMCIA_DEVICE_MANF_CARD(0x4e01, 0x0100), /* Viking CFA */
PCMCIA_DEVICE_MANF_CARD(0x4e01, 0x0200), /* Lexar, Viking CFA */
PCMCIA_DEVICE_PROD_ID123("Caravelle", "PSC-IDE ", "PSC000", 0x8c36137c, 0xd0693ab8, 0x2768a9f0),
PCMCIA_DEVICE_PROD_ID123("CDROM", "IDE", "MCD-601p", 0x1b9179ca, 0xede88951, 0x0d902f74),
PCMCIA_DEVICE_PROD_ID123("PCMCIA", "IDE CARD", "F1", 0x281f1c5d, 0x1907960c, 0xf7fde8b9),
PCMCIA_DEVICE_PROD_ID12("ARGOSY", "CD-ROM", 0x78f308dc, 0x66536591),
PCMCIA_DEVICE_PROD_ID12("ARGOSY", "PnPIDE", 0x78f308dc, 0x0c694728),
PCMCIA_DEVICE_PROD_ID12("CNF ", "CD-ROM", 0x46d7db81, 0x66536591),
PCMCIA_DEVICE_PROD_ID12("CNF CD-M", "CD-ROM", 0x7d93b852, 0x66536591),
PCMCIA_DEVICE_PROD_ID12("Creative Technology Ltd.", "PCMCIA CD-ROM Interface Card", 0xff8c8a45, 0xfe8020c4),
PCMCIA_DEVICE_PROD_ID12("Digital Equipment Corporation.", "Digital Mobile Media CD-ROM", 0x17692a66, 0xef1dcbde),
PCMCIA_DEVICE_PROD_ID12("EXP", "CD+GAME", 0x6f58c983, 0x63c13aaf),
PCMCIA_DEVICE_PROD_ID12("EXP ", "CD-ROM", 0x0a5c52fd, 0x66536591),
PCMCIA_DEVICE_PROD_ID12("EXP ", "PnPIDE", 0x0a5c52fd, 0x0c694728),
PCMCIA_DEVICE_PROD_ID12("FREECOM", "PCCARD-IDE", 0x5714cbf7, 0x48e0ab8e),
PCMCIA_DEVICE_PROD_ID12("HITACHI", "FLASH", 0xf4f43949, 0x9eb86aae),
PCMCIA_DEVICE_PROD_ID12("HITACHI", "microdrive", 0xf4f43949, 0xa6d76178),
PCMCIA_DEVICE_PROD_ID12("Hyperstone", "Model1", 0x3d5b9ef5, 0xca6ab420),
PCMCIA_DEVICE_PROD_ID12("IBM", "microdrive", 0xb569a6e5, 0xa6d76178),
PCMCIA_DEVICE_PROD_ID12("IBM", "IBM17JSSFP20", 0xb569a6e5, 0xf2508753),
PCMCIA_DEVICE_PROD_ID12("KINGSTON", "CF CARD 1GB", 0x2e6d1829, 0x55d5bffb),
PCMCIA_DEVICE_PROD_ID12("KINGSTON", "CF CARD 4GB", 0x2e6d1829, 0x531e7d10),
PCMCIA_DEVICE_PROD_ID12("KINGSTON", "CF8GB", 0x2e6d1829, 0xacbe682e),
PCMCIA_DEVICE_PROD_ID12("IO DATA", "CBIDE2 ", 0x547e66dc, 0x8671043b),
PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b),
PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
PCMCIA_DEVICE_PROD_ID12("PCMCIA", "PnPIDE", 0x281f1c5d, 0x0c694728),
PCMCIA_DEVICE_PROD_ID12("SHUTTLE TECHNOLOGY LTD.", "PCCARD-IDE/ATAPI Adapter", 0x4a3f0ba0, 0x322560e1),
PCMCIA_DEVICE_PROD_ID12("SEAGATE", "ST1", 0x87c1b330, 0xe1f30883),
PCMCIA_DEVICE_PROD_ID12("SAMSUNG", "04/05/06", 0x43d74cb4, 0x6a22777d),
PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443),
PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF133", 0x709b1bf1, 0x7558f133),
PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS8GCF133", 0x709b1bf1, 0xb2f89b47),
PCMCIA_DEVICE_PROD_ID12("WIT", "IDE16", 0x244e5994, 0x3e232852),
PCMCIA_DEVICE_PROD_ID12("WEIDA", "TWTTI", 0xcc7cf69c, 0x212bb918),
PCMCIA_DEVICE_PROD_ID1("STI Flash", 0xe4a13209),
PCMCIA_DEVICE_PROD_ID12("STI", "Flash 5.0", 0xbf2df18d, 0x8cb57a0e),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "SanDisk", "ConnectPlus", 0x7a954bd9, 0x74be00c6),
PCMCIA_DEVICE_PROD_ID2("Flash Card", 0x5a362506),
PCMCIA_DEVICE_NULL,
};
MODULE_DEVICE_TABLE(pcmcia, ide_ids);
static struct pcmcia_driver ide_cs_driver = {
.owner = THIS_MODULE,
.name = "ide-cs",
.probe = ide_probe,
.remove = ide_detach,
.id_table = ide_ids,
};
static int __init init_ide_cs(void)
{
return pcmcia_register_driver(&ide_cs_driver);
}
static void __exit exit_ide_cs(void)
{
pcmcia_unregister_driver(&ide_cs_driver);
}
late_initcall(init_ide_cs);
module_exit(exit_ide_cs);
| gpl-2.0 |
Tasssadar/android_kernel_google_msm | drivers/staging/usbip/vhci_sysfs.c | 5458 | 6114 | /*
* Copyright (C) 2003-2008 Takahiro Hirofuchi
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
* USA.
*/
#include <linux/kthread.h>
#include <linux/net.h>
#include "usbip_common.h"
#include "vhci.h"
/* TODO: refine locking ?*/
/* Sysfs entry to show port status */
static ssize_t show_status(struct device *dev, struct device_attribute *attr,
char *out)
{
char *s = out;
int i = 0;
BUG_ON(!the_controller || !out);
spin_lock(&the_controller->lock);
/*
* output example:
* prt sta spd dev socket local_busid
* 000 004 000 000 c5a7bb80 1-2.3
* 001 004 000 000 d8cee980 2-3.4
*
* IP address can be retrieved from a socket pointer address by looking
* up /proc/net/{tcp,tcp6}. Also, a userland program may remember a
* port number and its peer IP address.
*/
out += sprintf(out, "prt sta spd bus dev socket "
"local_busid\n");
for (i = 0; i < VHCI_NPORTS; i++) {
struct vhci_device *vdev = port_to_vdev(i);
spin_lock(&vdev->ud.lock);
out += sprintf(out, "%03u %03u ", i, vdev->ud.status);
if (vdev->ud.status == VDEV_ST_USED) {
out += sprintf(out, "%03u %08x ",
vdev->speed, vdev->devid);
out += sprintf(out, "%16p ", vdev->ud.tcp_socket);
out += sprintf(out, "%s", dev_name(&vdev->udev->dev));
} else {
out += sprintf(out, "000 000 000 0000000000000000 0-0");
}
out += sprintf(out, "\n");
spin_unlock(&vdev->ud.lock);
}
spin_unlock(&the_controller->lock);
return out - s;
}
static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
/* Sysfs entry to shutdown a virtual connection */
static int vhci_port_disconnect(__u32 rhport)
{
struct vhci_device *vdev;
usbip_dbg_vhci_sysfs("enter\n");
/* lock */
spin_lock(&the_controller->lock);
vdev = port_to_vdev(rhport);
spin_lock(&vdev->ud.lock);
if (vdev->ud.status == VDEV_ST_NULL) {
pr_err("not connected %d\n", vdev->ud.status);
/* unlock */
spin_unlock(&vdev->ud.lock);
spin_unlock(&the_controller->lock);
return -EINVAL;
}
/* unlock */
spin_unlock(&vdev->ud.lock);
spin_unlock(&the_controller->lock);
usbip_event_add(&vdev->ud, VDEV_EVENT_DOWN);
return 0;
}
static ssize_t store_detach(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int err;
__u32 rhport = 0;
sscanf(buf, "%u", &rhport);
/* check rhport */
if (rhport >= VHCI_NPORTS) {
dev_err(dev, "invalid port %u\n", rhport);
return -EINVAL;
}
err = vhci_port_disconnect(rhport);
if (err < 0)
return -EINVAL;
usbip_dbg_vhci_sysfs("Leave\n");
return count;
}
static DEVICE_ATTR(detach, S_IWUSR, NULL, store_detach);
/* Sysfs entry to establish a virtual connection */
static int valid_args(__u32 rhport, enum usb_device_speed speed)
{
/* check rhport */
if (rhport >= VHCI_NPORTS) {
pr_err("port %u\n", rhport);
return -EINVAL;
}
/* check speed */
switch (speed) {
case USB_SPEED_LOW:
case USB_SPEED_FULL:
case USB_SPEED_HIGH:
case USB_SPEED_WIRELESS:
break;
default:
pr_err("speed %d\n", speed);
return -EINVAL;
}
return 0;
}
/*
* To start a new USB/IP attachment, a userland program needs to setup a TCP
* connection and then write its socket descriptor with remote device
* information into this sysfs file.
*
* A remote device is virtually attached to the root-hub port of @rhport with
* @speed. @devid is embedded into a request to specify the remote device in a
* server host.
*
* write() returns 0 on success, else negative errno.
*/
static ssize_t store_attach(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct vhci_device *vdev;
struct socket *socket;
int sockfd = 0;
__u32 rhport = 0, devid = 0, speed = 0;
/*
* @rhport: port number of vhci_hcd
* @sockfd: socket descriptor of an established TCP connection
* @devid: unique device identifier in a remote host
* @speed: usb device speed in a remote host
*/
sscanf(buf, "%u %u %u %u", &rhport, &sockfd, &devid, &speed);
usbip_dbg_vhci_sysfs("rhport(%u) sockfd(%u) devid(%u) speed(%u)\n",
rhport, sockfd, devid, speed);
/* check received parameters */
if (valid_args(rhport, speed) < 0)
return -EINVAL;
/* check sockfd */
socket = sockfd_to_socket(sockfd);
if (!socket)
return -EINVAL;
/* now need lock until setting vdev status as used */
/* begin a lock */
spin_lock(&the_controller->lock);
vdev = port_to_vdev(rhport);
spin_lock(&vdev->ud.lock);
if (vdev->ud.status != VDEV_ST_NULL) {
/* end of the lock */
spin_unlock(&vdev->ud.lock);
spin_unlock(&the_controller->lock);
dev_err(dev, "port %d already used\n", rhport);
return -EINVAL;
}
dev_info(dev, "rhport(%u) sockfd(%d) devid(%u) speed(%u)\n",
rhport, sockfd, devid, speed);
vdev->devid = devid;
vdev->speed = speed;
vdev->ud.tcp_socket = socket;
vdev->ud.status = VDEV_ST_NOTASSIGNED;
spin_unlock(&vdev->ud.lock);
spin_unlock(&the_controller->lock);
/* end the lock */
vdev->ud.tcp_rx = kthread_run(vhci_rx_loop, &vdev->ud, "vhci_rx");
vdev->ud.tcp_tx = kthread_run(vhci_tx_loop, &vdev->ud, "vhci_tx");
rh_port_connect(rhport, speed);
return count;
}
static DEVICE_ATTR(attach, S_IWUSR, NULL, store_attach);
static struct attribute *dev_attrs[] = {
&dev_attr_status.attr,
&dev_attr_detach.attr,
&dev_attr_attach.attr,
&dev_attr_usbip_debug.attr,
NULL,
};
const struct attribute_group dev_attr_group = {
.attrs = dev_attrs,
};
| gpl-2.0 |
leonardoafa/android_kernel_motorola_msm8974 | arch/sh/kernel/cpu/sh2a/setup-sh7201.c | 7506 | 11678 | /*
* SH7201 setup
*
* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
* Copyright (C) 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <linux/io.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
ADC_ADI,
MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
RTC, WDT,
IIC30, IIC31, IIC32,
DMAC0_DMINT0, DMAC1_DMINT1,
DMAC2_DMINT2, DMAC3_DMINT3,
SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
DMAC7_DMINT7,
RCAN0, RCAN1,
SSI0_SSII, SSI1_SSII,
TMR0, TMR1,
/* interrupt groups */
PINT,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
INTC_IRQ(ADC_ADI, 92),
INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
INTC_IRQ(MTU20_VEF, 114),
INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
INTC_IRQ(MTU2_TCI3V, 136),
INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
INTC_IRQ(MTU2_TCI4V, 144),
INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
INTC_IRQ(MTU25_UVW, 150),
INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
INTC_IRQ(RTC, 154),
INTC_IRQ(WDT, 156),
INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
INTC_IRQ(IIC30, 161),
INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
INTC_IRQ(IIC31, 168),
INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
INTC_IRQ(IIC32, 174),
INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
INTC_IRQ(DMAC7_DMINT7, 219),
INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
INTC_IRQ(RCAN0, 230),
INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
INTC_IRQ(RCAN1, 236),
INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
INTC_IRQ(TMR0, 248),
INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
INTC_IRQ(TMR1, 254),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
PINT4, PINT5, PINT6, PINT7),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfffe9408, 0, 16, /* PINTER */
{ 0, 0, 0, 0, 0, 0, 0, 0,
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
mask_registers, prio_registers, NULL);
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xfffe8000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 180, 180, 180, 180 }
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xfffe8800,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 184, 184, 184, 184 }
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xfffe9000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 188, 188, 188, 188 }
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xfffe9800,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 192, 192, 192, 192 }
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xfffea000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 196, 196, 196, 196 }
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xfffea800,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 200, 200, 200, 200 }
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xfffeb000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 204, 204, 204, 204 }
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xfffeb800,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 208, 208, 208, 208 }
};
static struct platform_device scif7_device = {
.name = "sh-sci",
.id = 7,
.dev = {
.platform_data = &scif7_platform_data,
},
};
static struct resource rtc_resources[] = {
[0] = {
.start = 0xffff0800,
.end = 0xffff2000 + 0x58 - 1,
.flags = IORESOURCE_IO,
},
[1] = {
/* Shared Period/Carry/Alarm IRQ */
.start = 152,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
};
static struct sh_timer_config mtu2_0_platform_data = {
.channel_offset = -0x80,
.timer_bit = 0,
.clockevent_rating = 200,
};
static struct resource mtu2_0_resources[] = {
[0] = {
.start = 0xfffe4300,
.end = 0xfffe4326,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 108,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mtu2_0_device = {
.name = "sh_mtu2",
.id = 0,
.dev = {
.platform_data = &mtu2_0_platform_data,
},
.resource = mtu2_0_resources,
.num_resources = ARRAY_SIZE(mtu2_0_resources),
};
static struct sh_timer_config mtu2_1_platform_data = {
.channel_offset = -0x100,
.timer_bit = 1,
.clockevent_rating = 200,
};
static struct resource mtu2_1_resources[] = {
[0] = {
.start = 0xfffe4380,
.end = 0xfffe4390,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 116,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mtu2_1_device = {
.name = "sh_mtu2",
.id = 1,
.dev = {
.platform_data = &mtu2_1_platform_data,
},
.resource = mtu2_1_resources,
.num_resources = ARRAY_SIZE(mtu2_1_resources),
};
static struct sh_timer_config mtu2_2_platform_data = {
.channel_offset = 0x80,
.timer_bit = 2,
.clockevent_rating = 200,
};
static struct resource mtu2_2_resources[] = {
[0] = {
.start = 0xfffe4000,
.end = 0xfffe400a,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 124,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mtu2_2_device = {
.name = "sh_mtu2",
.id = 2,
.dev = {
.platform_data = &mtu2_2_platform_data,
},
.resource = mtu2_2_resources,
.num_resources = ARRAY_SIZE(mtu2_2_resources),
};
static struct platform_device *sh7201_devices[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
&scif3_device,
&scif4_device,
&scif5_device,
&scif6_device,
&scif7_device,
&rtc_device,
&mtu2_0_device,
&mtu2_1_device,
&mtu2_2_device,
};
static int __init sh7201_devices_setup(void)
{
return platform_add_devices(sh7201_devices,
ARRAY_SIZE(sh7201_devices));
}
arch_initcall(sh7201_devices_setup);
void __init plat_irq_setup(void)
{
register_intc_controller(&intc_desc);
}
static struct platform_device *sh7201_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
&scif3_device,
&scif4_device,
&scif5_device,
&scif6_device,
&scif7_device,
&mtu2_0_device,
&mtu2_1_device,
&mtu2_2_device,
};
#define STBCR3 0xfffe0408
void __init plat_early_device_setup(void)
{
/* enable MTU2 clock */
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
early_platform_add_devices(sh7201_early_devices,
ARRAY_SIZE(sh7201_early_devices));
}
| gpl-2.0 |
ausdim/SGS3-JB-U8 | arch/sh/kernel/cpu/sh3/setup-sh7710.c | 7506 | 5959 | /*
* SH3 Setup code for SH7710, SH7712
*
* Copyright (C) 2006 - 2009 Paul Mundt
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <asm/rtc.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
EDMAC0, EDMAC1, EDMAC2,
SIOF0, SIOF1,
TMU0, TMU1, TMU2,
RTC, WDT, REF,
};
static struct intc_vect vectors[] __initdata = {
/* IRQ0->5 are handled in setup-sh3.c */
INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
#ifdef CONFIG_CPU_SUBTYPE_SH7710
INTC_VECT(IPSEC, 0xbe0),
#endif
INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
INTC_VECT(EDMAC2, 0xc40),
INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2, 0x440),
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
INTC_VECT(RTC, 0x4c0),
INTC_VECT(WDT, 0x560),
INTC_VECT(REF, 0x580),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
{ 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
{ 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
NULL, prio_registers, NULL);
static struct resource rtc_resources[] = {
[0] = {
.start = 0xa413fec0,
.end = 0xa413fec0 + 0x1e,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
};
static struct sh_rtc_platform_info rtc_info = {
.capabilities = RTC_CAP_4_DIGIT_YEAR,
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
.dev = {
.platform_data = &rtc_info,
},
};
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 52, 52, 52, 52 },
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct sh_timer_config tmu0_platform_data = {
.channel_offset = 0x02,
.timer_bit = 0,
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.start = 0xa412fe94,
.end = 0xa412fe9f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 16,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device tmu0_device = {
.name = "sh_tmu",
.id = 0,
.dev = {
.platform_data = &tmu0_platform_data,
},
.resource = tmu0_resources,
.num_resources = ARRAY_SIZE(tmu0_resources),
};
static struct sh_timer_config tmu1_platform_data = {
.channel_offset = 0xe,
.timer_bit = 1,
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.start = 0xa412fea0,
.end = 0xa412feab,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 17,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device tmu1_device = {
.name = "sh_tmu",
.id = 1,
.dev = {
.platform_data = &tmu1_platform_data,
},
.resource = tmu1_resources,
.num_resources = ARRAY_SIZE(tmu1_resources),
};
static struct sh_timer_config tmu2_platform_data = {
.channel_offset = 0x1a,
.timer_bit = 2,
};
static struct resource tmu2_resources[] = {
[0] = {
.start = 0xa412feac,
.end = 0xa412feb5,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 18,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device tmu2_device = {
.name = "sh_tmu",
.id = 2,
.dev = {
.platform_data = &tmu2_platform_data,
},
.resource = tmu2_resources,
.num_resources = ARRAY_SIZE(tmu2_resources),
};
static struct platform_device *sh7710_devices[] __initdata = {
&scif0_device,
&scif1_device,
&tmu0_device,
&tmu1_device,
&tmu2_device,
&rtc_device,
};
static int __init sh7710_devices_setup(void)
{
return platform_add_devices(sh7710_devices,
ARRAY_SIZE(sh7710_devices));
}
arch_initcall(sh7710_devices_setup);
static struct platform_device *sh7710_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&tmu0_device,
&tmu1_device,
&tmu2_device,
};
void __init plat_early_device_setup(void)
{
early_platform_add_devices(sh7710_early_devices,
ARRAY_SIZE(sh7710_early_devices));
}
void __init plat_irq_setup(void)
{
register_intc_controller(&intc_desc);
plat_irq_setup_sh3();
}
| gpl-2.0 |
SlimRoms/kernel_htc_msm8974 | drivers/media/dvb/frontends/mb86a16.c | 8018 | 46822 | /*
Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
Copyright (C) Manu Abraham (abraham.manu@gmail.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "mb86a16.h"
#include "mb86a16_priv.h"
unsigned int verbose = 5;
module_param(verbose, int, 0644);
#define ABS(x) ((x) < 0 ? (-x) : (x))
struct mb86a16_state {
struct i2c_adapter *i2c_adap;
const struct mb86a16_config *config;
struct dvb_frontend frontend;
/* tuning parameters */
int frequency;
int srate;
/* Internal stuff */
int master_clk;
int deci;
int csel;
int rsel;
};
#define MB86A16_ERROR 0
#define MB86A16_NOTICE 1
#define MB86A16_INFO 2
#define MB86A16_DEBUG 3
#define dprintk(x, y, z, format, arg...) do { \
if (z) { \
if ((x > MB86A16_ERROR) && (x > y)) \
printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_NOTICE) && (x > y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_INFO) && (x > y)) \
printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_DEBUG) && (x > y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
} else { \
if (x > y) \
printk(format, ##arg); \
} \
} while (0)
#define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
#define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
{
int ret;
u8 buf[] = { reg, val };
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2
};
dprintk(verbose, MB86A16_DEBUG, 1,
"writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
state->config->demod_address, buf[0], buf[1]);
ret = i2c_transfer(state->i2c_adap, &msg, 1);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c_adap, msg, 2);
if (ret != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
reg, ret);
return -EREMOTEIO;
}
*val = b1[0];
return ret;
}
static int CNTM_set(struct mb86a16_state *state,
unsigned char timint1,
unsigned char timint2,
unsigned char cnext)
{
unsigned char val;
val = (timint1 << 4) | (timint2 << 2) | cnext;
if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int smrt_set(struct mb86a16_state *state, int rate)
{
int tmp ;
int m ;
unsigned char STOFS0, STOFS1;
m = 1 << state->deci;
tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
STOFS0 = tmp & 0x0ff;
STOFS1 = (tmp & 0xf00) >> 8;
if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
(state->csel << 1) |
state->rsel) < 0)
goto err;
if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
goto err;
if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
static int srst(struct mb86a16_state *state)
{
if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int afcex_data_set(struct mb86a16_state *state,
unsigned char AFCEX_L,
unsigned char AFCEX_H)
{
if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
goto err;
if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
static int afcofs_data_set(struct mb86a16_state *state,
unsigned char AFCEX_L,
unsigned char AFCEX_H)
{
if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
goto err;
if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int stlp_set(struct mb86a16_state *state,
unsigned char STRAS,
unsigned char STRBS)
{
if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
{
if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
goto err;
if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int initial_set(struct mb86a16_state *state)
{
if (stlp_set(state, 5, 7))
goto err;
udelay(100);
if (afcex_data_set(state, 0, 0))
goto err;
udelay(100);
if (afcofs_data_set(state, 0, 0))
goto err;
udelay(100);
if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
goto err;
if (mb86a16_write(state, 0x2f, 0x21) < 0)
goto err;
if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
goto err;
if (mb86a16_write(state, 0x54, 0xff) < 0)
goto err;
if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int S01T_set(struct mb86a16_state *state,
unsigned char s1t,
unsigned s0t)
{
if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int EN_set(struct mb86a16_state *state,
int cren,
int afcen)
{
unsigned char val;
val = 0x7a | (cren << 7) | (afcen << 2);
if (mb86a16_write(state, 0x49, val) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int AFCEXEN_set(struct mb86a16_state *state,
int afcexen,
int smrt)
{
unsigned char AFCA ;
if (smrt > 18875)
AFCA = 4;
else if (smrt > 9375)
AFCA = 3;
else if (smrt > 2250)
AFCA = 2;
else
AFCA = 1;
if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int DAGC_data_set(struct mb86a16_state *state,
unsigned char DAGCA,
unsigned char DAGCW)
{
if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static void smrt_info_get(struct mb86a16_state *state, int rate)
{
if (rate >= 37501) {
state->deci = 0; state->csel = 0; state->rsel = 0;
} else if (rate >= 30001) {
state->deci = 0; state->csel = 0; state->rsel = 1;
} else if (rate >= 26251) {
state->deci = 0; state->csel = 1; state->rsel = 0;
} else if (rate >= 22501) {
state->deci = 0; state->csel = 1; state->rsel = 1;
} else if (rate >= 18751) {
state->deci = 1; state->csel = 0; state->rsel = 0;
} else if (rate >= 15001) {
state->deci = 1; state->csel = 0; state->rsel = 1;
} else if (rate >= 13126) {
state->deci = 1; state->csel = 1; state->rsel = 0;
} else if (rate >= 11251) {
state->deci = 1; state->csel = 1; state->rsel = 1;
} else if (rate >= 9376) {
state->deci = 2; state->csel = 0; state->rsel = 0;
} else if (rate >= 7501) {
state->deci = 2; state->csel = 0; state->rsel = 1;
} else if (rate >= 6563) {
state->deci = 2; state->csel = 1; state->rsel = 0;
} else if (rate >= 5626) {
state->deci = 2; state->csel = 1; state->rsel = 1;
} else if (rate >= 4688) {
state->deci = 3; state->csel = 0; state->rsel = 0;
} else if (rate >= 3751) {
state->deci = 3; state->csel = 0; state->rsel = 1;
} else if (rate >= 3282) {
state->deci = 3; state->csel = 1; state->rsel = 0;
} else if (rate >= 2814) {
state->deci = 3; state->csel = 1; state->rsel = 1;
} else if (rate >= 2344) {
state->deci = 4; state->csel = 0; state->rsel = 0;
} else if (rate >= 1876) {
state->deci = 4; state->csel = 0; state->rsel = 1;
} else if (rate >= 1641) {
state->deci = 4; state->csel = 1; state->rsel = 0;
} else if (rate >= 1407) {
state->deci = 4; state->csel = 1; state->rsel = 1;
} else if (rate >= 1172) {
state->deci = 5; state->csel = 0; state->rsel = 0;
} else if (rate >= 939) {
state->deci = 5; state->csel = 0; state->rsel = 1;
} else if (rate >= 821) {
state->deci = 5; state->csel = 1; state->rsel = 0;
} else {
state->deci = 5; state->csel = 1; state->rsel = 1;
}
if (state->csel == 0)
state->master_clk = 92000;
else
state->master_clk = 61333;
}
static int signal_det(struct mb86a16_state *state,
int smrt,
unsigned char *SIG)
{
int ret ;
int smrtd ;
int wait_sym ;
u32 wait_t;
unsigned char S[3] ;
int i ;
if (*SIG > 45) {
if (CNTM_set(state, 2, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
wait_sym = 40000;
} else {
if (CNTM_set(state, 3, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
wait_sym = 80000;
}
for (i = 0; i < 3; i++) {
if (i == 0)
smrtd = smrt * 98 / 100;
else if (i == 1)
smrtd = smrt;
else
smrtd = smrt * 102 / 100;
smrt_info_get(state, smrtd);
smrt_set(state, smrtd);
srst(state);
wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
if (wait_t == 0)
wait_t = 1;
msleep_interruptible(10);
if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
}
if ((S[1] > S[0] * 112 / 100) &&
(S[1] > S[2] * 112 / 100)) {
ret = 1;
} else {
ret = 0;
}
*SIG = S[1];
if (CNTM_set(state, 0, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
return ret;
}
static int rf_val_set(struct mb86a16_state *state,
int f,
int smrt,
unsigned char R)
{
unsigned char C, F, B;
int M;
unsigned char rf_val[5];
int ack = -1;
if (smrt > 37750)
C = 1;
else if (smrt > 18875)
C = 2;
else if (smrt > 5500)
C = 3;
else
C = 4;
if (smrt > 30500)
F = 3;
else if (smrt > 9375)
F = 1;
else if (smrt > 4625)
F = 0;
else
F = 2;
if (f < 1060)
B = 0;
else if (f < 1175)
B = 1;
else if (f < 1305)
B = 2;
else if (f < 1435)
B = 3;
else if (f < 1570)
B = 4;
else if (f < 1715)
B = 5;
else if (f < 1845)
B = 6;
else if (f < 1980)
B = 7;
else if (f < 2080)
B = 8;
else
B = 9;
M = f * (1 << R) / 2;
rf_val[0] = 0x01 | (C << 3) | (F << 1);
rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
rf_val[2] = (M & 0x00ff0) >> 4;
rf_val[3] = ((M & 0x0000f) << 4) | B;
/* Frequency Set */
if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
ack = 0;
if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
ack = 0;
if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
ack = 0;
if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
ack = 0;
if (mb86a16_write(state, 0x25, 0x01) < 0)
ack = 0;
if (ack == 0) {
dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int afcerr_chk(struct mb86a16_state *state)
{
unsigned char AFCM_L, AFCM_H ;
int AFCM ;
int afcm, afcerr ;
if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
goto err;
if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
goto err;
AFCM = (AFCM_H << 8) + AFCM_L;
if (AFCM > 2048)
afcm = AFCM - 4096;
else
afcm = AFCM;
afcerr = afcm * state->master_clk / 8192;
return afcerr;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int dagcm_val_get(struct mb86a16_state *state)
{
int DAGCM;
unsigned char DAGCM_H, DAGCM_L;
if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
goto err;
if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
goto err;
DAGCM = (DAGCM_H << 8) + DAGCM_L;
return DAGCM;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
u8 stat, stat2;
struct mb86a16_state *state = fe->demodulator_priv;
*status = 0;
if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
goto err;
if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
goto err;
if ((stat > 25) && (stat2 > 25))
*status |= FE_HAS_SIGNAL;
if ((stat > 45) && (stat2 > 45))
*status |= FE_HAS_CARRIER;
if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
goto err;
if (stat & 0x01)
*status |= FE_HAS_SYNC;
if (stat & 0x01)
*status |= FE_HAS_VITERBI;
if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
goto err;
if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
*status |= FE_HAS_LOCK;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int sync_chk(struct mb86a16_state *state,
unsigned char *VIRM)
{
unsigned char val;
int sync;
if (mb86a16_read(state, 0x0d, &val) != 2)
goto err;
dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
sync = val & 0x01;
*VIRM = (val & 0x1c) >> 2;
return sync;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int freqerr_chk(struct mb86a16_state *state,
int fTP,
int smrt,
int unit)
{
unsigned char CRM, AFCML, AFCMH;
unsigned char temp1, temp2, temp3;
int crm, afcm, AFCM;
int crrerr, afcerr; /* kHz */
int frqerr; /* MHz */
int afcen, afcexen = 0;
int R, M, fOSC, fOSC_OFS;
if (mb86a16_read(state, 0x43, &CRM) != 2)
goto err;
if (CRM > 127)
crm = CRM - 256;
else
crm = CRM;
crrerr = smrt * crm / 256;
if (mb86a16_read(state, 0x49, &temp1) != 2)
goto err;
afcen = (temp1 & 0x04) >> 2;
if (afcen == 0) {
if (mb86a16_read(state, 0x2a, &temp1) != 2)
goto err;
afcexen = (temp1 & 0x20) >> 5;
}
if (afcen == 1) {
if (mb86a16_read(state, 0x0e, &AFCML) != 2)
goto err;
if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
goto err;
} else if (afcexen == 1) {
if (mb86a16_read(state, 0x2b, &AFCML) != 2)
goto err;
if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
goto err;
}
if ((afcen == 1) || (afcexen == 1)) {
smrt_info_get(state, smrt);
AFCM = ((AFCMH & 0x01) << 8) + AFCML;
if (AFCM > 255)
afcm = AFCM - 512;
else
afcm = AFCM;
afcerr = afcm * state->master_clk / 8192;
} else
afcerr = 0;
if (mb86a16_read(state, 0x22, &temp1) != 2)
goto err;
if (mb86a16_read(state, 0x23, &temp2) != 2)
goto err;
if (mb86a16_read(state, 0x24, &temp3) != 2)
goto err;
R = (temp1 & 0xe0) >> 5;
M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
if (R == 0)
fOSC = 2 * M;
else
fOSC = M;
fOSC_OFS = fOSC - fTP;
if (unit == 0) { /* MHz */
if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
else
frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
} else { /* kHz */
frqerr = crrerr + afcerr + fOSC_OFS * 1000;
}
return frqerr;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
{
unsigned char R;
if (smrt > 9375)
R = 0;
else
R = 1;
return R;
}
static void swp_info_get(struct mb86a16_state *state,
int fOSC_start,
int smrt,
int v, int R,
int swp_ofs,
int *fOSC,
int *afcex_freq,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
int crnt_swp_freq ;
crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
if (R == 0)
*fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
else
*fOSC = (crnt_swp_freq + 500) / 1000;
if (*fOSC >= crnt_swp_freq)
*afcex_freq = *fOSC * 1000 - crnt_swp_freq;
else
*afcex_freq = crnt_swp_freq - *fOSC * 1000;
AFCEX = *afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
{
int swp_freq ;
if ((i % 2 == 1) && (v <= vmax)) {
/* positive v (case 1) */
if ((v - 1 == vmin) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
(*(V + 30 + v - 1) > SIGMIN)) {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
} else if ((v == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v - 1)) &&
(*(V + 30 + v) > SIGMIN)) {
/* (case 2) */
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else if ((*(V + 30 + v) > 0) &&
(*(V + 30 + v - 1) > 0) &&
(*(V + 30 + v - 2) > 0) &&
(*(V + 30 + v - 3) > 0) &&
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
(*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
((*(V + 30 + v - 1) > SIGMIN) ||
(*(V + 30 + v - 2) > SIGMIN))) {
/* (case 3) */
if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
*SIG1 = *(V + 30 + v - 2);
}
} else if ((v == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v - 2) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v - 2)) &&
(*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
((*(V + 30 + v) > SIGMIN) ||
(*(V + 30 + v - 1) > SIGMIN))) {
/* (case 4) */
if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
}
} else {
swp_freq = -1 ;
}
} else if ((i % 2 == 0) && (v >= vmin)) {
/* Negative v (case 1) */
if ((*(V + 30 + v) > 0) &&
(*(V + 30 + v + 1) > 0) &&
(*(V + 30 + v + 2) > 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
(*(V + 30 + v + 1) > SIGMIN)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else if ((v + 1 == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 1) > SIGMIN)) {
/* (case 2) */
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v);
} else if ((v == vmin) &&
(*(V + 30 + v) > 0) &&
(*(V + 30 + v + 1) > 0) &&
(*(V + 30 + v + 2) > 0) &&
(*(V + 30 + v) > *(V + 30 + v + 1)) &&
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
(*(V + 30 + v) > SIGMIN)) {
/* (case 3) */
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else if ((*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 3) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
((*(V + 30 + v + 1) > SIGMIN) ||
(*(V + 30 + v + 2) > SIGMIN))) {
/* (case 4) */
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
*SIG1 = *(V + 30 + v + 2);
}
} else if ((*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 3) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
(*(V + 30 + v) > *(V + 30 + v + 3)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
((*(V + 30 + v) > SIGMIN) ||
(*(V + 30 + v + 1) > SIGMIN))) {
/* (case 5) */
if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
}
} else if ((v + 2 == vmin) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 2) > *(V + 30 + v)) &&
((*(V + 30 + v + 1) > SIGMIN) ||
(*(V + 30 + v + 2) > SIGMIN))) {
/* (case 6) */
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
*SIG1 = *(V + 30 + v + 2);
}
} else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
swp_freq = fOSC * 1000;
*SIG1 = *(V + 30 + v);
} else
swp_freq = -1;
} else
swp_freq = -1;
return swp_freq;
}
static void swp_info_get2(struct mb86a16_state *state,
int smrt,
int R,
int swp_freq,
int *afcex_freq,
int *fOSC,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
if (R == 0)
*fOSC = (swp_freq + 1000) / 2000 * 2;
else
*fOSC = (swp_freq + 500) / 1000;
if (*fOSC >= swp_freq)
*afcex_freq = *fOSC * 1000 - swp_freq;
else
*afcex_freq = swp_freq - *fOSC * 1000;
AFCEX = *afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static void afcex_info_get(struct mb86a16_state *state,
int afcex_freq,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
AFCEX = afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
{
/* SLOCK0 = 0 */
if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
{
/* Viterbi Rate, IQ Settings */
if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int FEC_srst(struct mb86a16_state *state)
{
if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
{
if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
{
if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int mb86a16_set_fe(struct mb86a16_state *state)
{
u8 agcval, cnmval;
int i, j;
int fOSC = 0;
int fOSC_start = 0;
int wait_t;
int fcp;
int swp_ofs;
int V[60];
u8 SIG1MIN;
unsigned char CREN, AFCEN, AFCEXEN;
unsigned char SIG1;
unsigned char TIMINT1, TIMINT2, TIMEXT;
unsigned char S0T, S1T;
unsigned char S2T;
/* unsigned char S2T, S3T; */
unsigned char S4T, S5T;
unsigned char AFCEX_L, AFCEX_H;
unsigned char R;
unsigned char VIRM;
unsigned char ETH, VIA;
unsigned char junk;
int loop;
int ftemp;
int v, vmax, vmin;
int vmax_his, vmin_his;
int swp_freq, prev_swp_freq[20];
int prev_freq_num;
int signal_dupl;
int afcex_freq;
int signal;
int afcerr;
int temp_freq, delta_freq;
int dagcm[4];
int smrt_d;
/* int freq_err; */
int n;
int ret = -1;
int sync;
dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
fcp = 3000;
swp_ofs = state->srate / 4;
for (i = 0; i < 60; i++)
V[i] = -1;
for (i = 0; i < 20; i++)
prev_swp_freq[i] = 0;
SIG1MIN = 25;
for (n = 0; ((n < 3) && (ret == -1)); n++) {
SEQ_set(state, 0);
iq_vt_set(state, 0);
CREN = 0;
AFCEN = 0;
AFCEXEN = 1;
TIMINT1 = 0;
TIMINT2 = 1;
TIMEXT = 2;
S1T = 0;
S0T = 0;
if (initial_set(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
return -1;
}
if (DAGC_data_set(state, 3, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1; /* (0, 0) */
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1; /* (1, smrt) = (1, symbolrate) */
}
if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
return -1; /* (0, 1, 2) */
}
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1; /* (0, 0) */
}
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
return -1;
}
R = vco_dev_get(state, state->srate);
if (R == 1)
fOSC_start = state->frequency;
else if (R == 0) {
if (state->frequency % 2 == 0) {
fOSC_start = state->frequency;
} else {
fOSC_start = state->frequency + 1;
if (fOSC_start > 2150)
fOSC_start = state->frequency - 1;
}
}
loop = 1;
ftemp = fOSC_start * 1000;
vmax = 0 ;
while (loop == 1) {
ftemp = ftemp + swp_ofs;
vmax++;
/* Upper bound */
if (ftemp > 2150000) {
loop = 0;
vmax--;
} else {
if ((ftemp == 2150000) ||
(ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
loop = 0;
}
}
loop = 1;
ftemp = fOSC_start * 1000;
vmin = 0 ;
while (loop == 1) {
ftemp = ftemp - swp_ofs;
vmin--;
/* Lower bound */
if (ftemp < 950000) {
loop = 0;
vmin++;
} else {
if ((ftemp == 950000) ||
(state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
loop = 0;
}
}
wait_t = (8000 + state->srate / 2) / state->srate;
if (wait_t == 0)
wait_t = 1;
i = 0;
j = 0;
prev_freq_num = 0;
loop = 1;
signal = 0;
vmax_his = 0;
vmin_his = 0;
v = 0;
while (loop == 1) {
swp_info_get(state, fOSC_start, state->srate,
v, R, swp_ofs, &fOSC,
&afcex_freq, &AFCEX_L, &AFCEX_H);
udelay(100);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
udelay(100);
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
msleep_interruptible(wait_t);
if (mb86a16_read(state, 0x37, &SIG1) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
V[30 + v] = SIG1 ;
swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
SIG1MIN, fOSC, afcex_freq,
swp_ofs, &SIG1); /* changed */
signal_dupl = 0;
for (j = 0; j < prev_freq_num; j++) {
if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
signal_dupl = 1;
dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
}
}
if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
prev_swp_freq[prev_freq_num] = swp_freq;
prev_freq_num++;
swp_info_get2(state, state->srate, R, swp_freq,
&afcex_freq, &fOSC,
&AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
signal = signal_det(state, state->srate, &SIG1);
if (signal == 1) {
dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
loop = 0;
} else {
dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
}
}
if (v > vmax)
vmax_his = 1 ;
if (v < vmin)
vmin_his = 1 ;
i++;
if ((i % 2 == 1) && (vmax_his == 1))
i++;
if ((i % 2 == 0) && (vmin_his == 1))
i++;
if (i % 2 == 1)
v = (i + 1) / 2;
else
v = -i / 2;
if ((vmax_his == 1) && (vmin_his == 1))
loop = 0 ;
}
if (signal == 1) {
dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
S1T = 7 ;
S0T = 1 ;
CREN = 0 ;
AFCEN = 1 ;
AFCEXEN = 0 ;
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1;
}
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
/* delay 4~200 */
wait_t = 200000 / state->master_clk + 200000 / state->srate;
msleep(wait_t);
afcerr = afcerr_chk(state);
if (afcerr == -1)
return -1;
swp_freq = fOSC * 1000 + afcerr ;
AFCEXEN = 1 ;
if (state->srate >= 1500)
smrt_d = state->srate / 3;
else
smrt_d = state->srate / 2;
smrt_info_get(state, smrt_d);
if (smrt_set(state, smrt_d) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
R = vco_dev_get(state, smrt_d);
if (DAGC_data_set(state, 2, 0) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
for (i = 0; i < 3; i++) {
temp_freq = swp_freq + (i - 1) * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[i] = dagcm_val_get(state);
}
if ((dagcm[0] > dagcm[1]) &&
(dagcm[0] > dagcm[2]) &&
(dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
temp_freq = swp_freq - 2 * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[3] = dagcm_val_get(state);
if (dagcm[3] > dagcm[1])
delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
else
delta_freq = 0;
} else if ((dagcm[2] > dagcm[1]) &&
(dagcm[2] > dagcm[0]) &&
(dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
temp_freq = swp_freq + 2 * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[3] = dagcm_val_get(state);
if (dagcm[3] > dagcm[1])
delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
else
delta_freq = 0 ;
} else {
delta_freq = 0 ;
}
dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
swp_freq += delta_freq;
dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
} else {
S1T = 0;
S0T = 3;
CREN = 1;
AFCEN = 0;
AFCEXEN = 1;
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1;
}
if (DAGC_data_set(state, 0, 0) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
R = vco_dev_get(state, state->srate);
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
wait_t = 7 + (10000 + state->srate / 2) / state->srate;
if (wait_t == 0)
wait_t = 1;
msleep_interruptible(wait_t);
if (mb86a16_read(state, 0x37, &SIG1) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
if (SIG1 > 110) {
S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
wait_t = 7 + (917504 + state->srate / 2) / state->srate;
} else if (SIG1 > 105) {
S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
} else if (SIG1 > 85) {
S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
} else if (SIG1 > 65) {
S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
} else {
S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
}
wait_t *= 2; /* FOS */
S2T_set(state, S2T);
S45T_set(state, S4T, S5T);
Vi_set(state, ETH, VIA);
srst(state);
msleep_interruptible(wait_t);
sync = sync_chk(state, &VIRM);
dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
if (VIRM) {
if (VIRM == 4) {
/* 5/6 */
if (SIG1 > 110)
wait_t = (786432 + state->srate / 2) / state->srate;
else
wait_t = (1572864 + state->srate / 2) / state->srate;
if (state->srate < 5000)
/* FIXME ! , should be a long wait ! */
msleep_interruptible(wait_t);
else
msleep_interruptible(wait_t);
if (sync_chk(state, &junk) == 0) {
iq_vt_set(state, 1);
FEC_srst(state);
}
}
/* 1/2, 2/3, 3/4, 7/8 */
if (SIG1 > 110)
wait_t = (786432 + state->srate / 2) / state->srate;
else
wait_t = (1572864 + state->srate / 2) / state->srate;
msleep_interruptible(wait_t);
SEQ_set(state, 1);
} else {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
SEQ_set(state, 1);
ret = -1;
}
}
} else {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
ret = -1;
}
sync = sync_chk(state, &junk);
if (sync) {
dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
freqerr_chk(state, state->frequency, state->srate, 1);
ret = 0;
break;
}
}
mb86a16_read(state, 0x15, &agcval);
mb86a16_read(state, 0x26, &cnmval);
dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
return ret;
}
static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct mb86a16_state *state = fe->demodulator_priv;
int i;
u8 regs;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
goto err;
regs = 0x18;
if (cmd->msg_len > 5 || cmd->msg_len < 4)
return -EINVAL;
for (i = 0; i < cmd->msg_len; i++) {
if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
goto err;
regs++;
}
i += 0x90;
msleep_interruptible(10);
if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
{
struct mb86a16_state *state = fe->demodulator_priv;
switch (burst) {
case SEC_MINI_A:
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_TBEN |
MB86A16_DCC1_TBO) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
case SEC_MINI_B:
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_TBEN) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
{
struct mb86a16_state *state = fe->demodulator_priv;
switch (tone) {
case SEC_TONE_ON:
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_CTOE) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
case SEC_TONE_OFF:
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
goto err;
break;
default:
return -EINVAL;
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mb86a16_state *state = fe->demodulator_priv;
state->frequency = p->frequency / 1000;
state->srate = p->symbol_rate / 1000;
if (!mb86a16_set_fe(state)) {
dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
return DVBFE_ALGO_SEARCH_SUCCESS;
}
dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
return DVBFE_ALGO_SEARCH_FAILED;
}
static void mb86a16_release(struct dvb_frontend *fe)
{
struct mb86a16_state *state = fe->demodulator_priv;
kfree(state);
}
static int mb86a16_init(struct dvb_frontend *fe)
{
return 0;
}
static int mb86a16_sleep(struct dvb_frontend *fe)
{
return 0;
}
static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
{
u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
u32 timer;
struct mb86a16_state *state = fe->demodulator_priv;
*ber = 0;
if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
goto err;
/* BER monitor invalid when BER_EN = 0 */
if (ber_mon & 0x04) {
/* coarse, fast calculation */
*ber = ber_tab & 0x1f;
dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
if (ber_mon & 0x01) {
/*
* BER_SEL = 1, The monitored BER is the estimated
* value with a Reed-Solomon decoder error amount at
* the deinterleaver output.
* monitored BER is expressed as a 20 bit output in total
*/
ber_rst = ber_mon >> 3;
*ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
if (ber_rst == 0)
timer = 12500000;
if (ber_rst == 1)
timer = 25000000;
if (ber_rst == 2)
timer = 50000000;
if (ber_rst == 3)
timer = 100000000;
*ber /= timer;
dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
} else {
/*
* BER_SEL = 0, The monitored BER is the estimated
* value with a Viterbi decoder error amount at the
* QPSK demodulator output.
* monitored BER is expressed as a 24 bit output in total
*/
ber_tim = ber_mon >> 1;
*ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
if (ber_tim == 0)
timer = 16;
if (ber_tim == 1)
timer = 24;
*ber /= 2 ^ timer;
dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
}
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
u8 agcm = 0;
struct mb86a16_state *state = fe->demodulator_priv;
*strength = 0;
if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
*strength = ((0xff - agcm) * 100) / 256;
dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
*strength = (0xffff - 0xff) + agcm;
return 0;
}
struct cnr {
u8 cn_reg;
u8 cn_val;
};
static const struct cnr cnr_tab[] = {
{ 35, 2 },
{ 40, 3 },
{ 50, 4 },
{ 60, 5 },
{ 70, 6 },
{ 80, 7 },
{ 92, 8 },
{ 103, 9 },
{ 115, 10 },
{ 138, 12 },
{ 162, 15 },
{ 180, 18 },
{ 185, 19 },
{ 189, 20 },
{ 195, 22 },
{ 199, 24 },
{ 201, 25 },
{ 202, 26 },
{ 203, 27 },
{ 205, 28 },
{ 208, 30 }
};
static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct mb86a16_state *state = fe->demodulator_priv;
int i = 0;
int low_tide = 2, high_tide = 30, q_level;
u8 cn;
*snr = 0;
if (mb86a16_read(state, 0x26, &cn) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
if (cn < cnr_tab[i].cn_reg) {
*snr = cnr_tab[i].cn_val;
break;
}
}
q_level = (*snr * 100) / (high_tide - low_tide);
dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
*snr = (0xffff - 0xff) + *snr;
return 0;
}
static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
u8 dist;
struct mb86a16_state *state = fe->demodulator_priv;
if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
*ucblocks = dist;
return 0;
}
static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
static struct dvb_frontend_ops mb86a16_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Fujitsu MB86A16 DVB-S",
.frequency_min = 950000,
.frequency_max = 2150000,
.frequency_stepsize = 3000,
.frequency_tolerance = 0,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 | FE_CAN_QPSK |
FE_CAN_FEC_AUTO
},
.release = mb86a16_release,
.get_frontend_algo = mb86a16_frontend_algo,
.search = mb86a16_search,
.init = mb86a16_init,
.sleep = mb86a16_sleep,
.read_status = mb86a16_read_status,
.read_ber = mb86a16_read_ber,
.read_signal_strength = mb86a16_read_signal_strength,
.read_snr = mb86a16_read_snr,
.read_ucblocks = mb86a16_read_ucblocks,
.diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
.diseqc_send_burst = mb86a16_send_diseqc_burst,
.set_tone = mb86a16_set_tone,
};
struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
struct i2c_adapter *i2c_adap)
{
u8 dev_id = 0;
struct mb86a16_state *state = NULL;
state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
if (state == NULL)
goto error;
state->config = config;
state->i2c_adap = i2c_adap;
mb86a16_read(state, 0x7f, &dev_id);
if (dev_id != 0xfe)
goto error;
memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
state->frontend.ops.set_voltage = state->config->set_voltage;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL(mb86a16_attach);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Manu Abraham");
| gpl-2.0 |
faux123/AK-OnePone | drivers/media/dvb/frontends/mb86a16.c | 8018 | 46822 | /*
Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
Copyright (C) Manu Abraham (abraham.manu@gmail.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "mb86a16.h"
#include "mb86a16_priv.h"
unsigned int verbose = 5;
module_param(verbose, int, 0644);
#define ABS(x) ((x) < 0 ? (-x) : (x))
struct mb86a16_state {
struct i2c_adapter *i2c_adap;
const struct mb86a16_config *config;
struct dvb_frontend frontend;
/* tuning parameters */
int frequency;
int srate;
/* Internal stuff */
int master_clk;
int deci;
int csel;
int rsel;
};
#define MB86A16_ERROR 0
#define MB86A16_NOTICE 1
#define MB86A16_INFO 2
#define MB86A16_DEBUG 3
#define dprintk(x, y, z, format, arg...) do { \
if (z) { \
if ((x > MB86A16_ERROR) && (x > y)) \
printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_NOTICE) && (x > y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_INFO) && (x > y)) \
printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
else if ((x > MB86A16_DEBUG) && (x > y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
} else { \
if (x > y) \
printk(format, ##arg); \
} \
} while (0)
#define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
#define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
{
int ret;
u8 buf[] = { reg, val };
struct i2c_msg msg = {
.addr = state->config->demod_address,
.flags = 0,
.buf = buf,
.len = 2
};
dprintk(verbose, MB86A16_DEBUG, 1,
"writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
state->config->demod_address, buf[0], buf[1]);
ret = i2c_transfer(state->i2c_adap, &msg, 1);
return (ret != 1) ? -EREMOTEIO : 0;
}
static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{
.addr = state->config->demod_address,
.flags = 0,
.buf = b0,
.len = 1
}, {
.addr = state->config->demod_address,
.flags = I2C_M_RD,
.buf = b1,
.len = 1
}
};
ret = i2c_transfer(state->i2c_adap, msg, 2);
if (ret != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
reg, ret);
return -EREMOTEIO;
}
*val = b1[0];
return ret;
}
static int CNTM_set(struct mb86a16_state *state,
unsigned char timint1,
unsigned char timint2,
unsigned char cnext)
{
unsigned char val;
val = (timint1 << 4) | (timint2 << 2) | cnext;
if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int smrt_set(struct mb86a16_state *state, int rate)
{
int tmp ;
int m ;
unsigned char STOFS0, STOFS1;
m = 1 << state->deci;
tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
STOFS0 = tmp & 0x0ff;
STOFS1 = (tmp & 0xf00) >> 8;
if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
(state->csel << 1) |
state->rsel) < 0)
goto err;
if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
goto err;
if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
static int srst(struct mb86a16_state *state)
{
if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int afcex_data_set(struct mb86a16_state *state,
unsigned char AFCEX_L,
unsigned char AFCEX_H)
{
if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
goto err;
if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
static int afcofs_data_set(struct mb86a16_state *state,
unsigned char AFCEX_L,
unsigned char AFCEX_H)
{
if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
goto err;
if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int stlp_set(struct mb86a16_state *state,
unsigned char STRAS,
unsigned char STRBS)
{
if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
{
if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
goto err;
if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int initial_set(struct mb86a16_state *state)
{
if (stlp_set(state, 5, 7))
goto err;
udelay(100);
if (afcex_data_set(state, 0, 0))
goto err;
udelay(100);
if (afcofs_data_set(state, 0, 0))
goto err;
udelay(100);
if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
goto err;
if (mb86a16_write(state, 0x2f, 0x21) < 0)
goto err;
if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
goto err;
if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
goto err;
if (mb86a16_write(state, 0x54, 0xff) < 0)
goto err;
if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int S01T_set(struct mb86a16_state *state,
unsigned char s1t,
unsigned s0t)
{
if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int EN_set(struct mb86a16_state *state,
int cren,
int afcen)
{
unsigned char val;
val = 0x7a | (cren << 7) | (afcen << 2);
if (mb86a16_write(state, 0x49, val) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int AFCEXEN_set(struct mb86a16_state *state,
int afcexen,
int smrt)
{
unsigned char AFCA ;
if (smrt > 18875)
AFCA = 4;
else if (smrt > 9375)
AFCA = 3;
else if (smrt > 2250)
AFCA = 2;
else
AFCA = 1;
if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int DAGC_data_set(struct mb86a16_state *state,
unsigned char DAGCA,
unsigned char DAGCW)
{
if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static void smrt_info_get(struct mb86a16_state *state, int rate)
{
if (rate >= 37501) {
state->deci = 0; state->csel = 0; state->rsel = 0;
} else if (rate >= 30001) {
state->deci = 0; state->csel = 0; state->rsel = 1;
} else if (rate >= 26251) {
state->deci = 0; state->csel = 1; state->rsel = 0;
} else if (rate >= 22501) {
state->deci = 0; state->csel = 1; state->rsel = 1;
} else if (rate >= 18751) {
state->deci = 1; state->csel = 0; state->rsel = 0;
} else if (rate >= 15001) {
state->deci = 1; state->csel = 0; state->rsel = 1;
} else if (rate >= 13126) {
state->deci = 1; state->csel = 1; state->rsel = 0;
} else if (rate >= 11251) {
state->deci = 1; state->csel = 1; state->rsel = 1;
} else if (rate >= 9376) {
state->deci = 2; state->csel = 0; state->rsel = 0;
} else if (rate >= 7501) {
state->deci = 2; state->csel = 0; state->rsel = 1;
} else if (rate >= 6563) {
state->deci = 2; state->csel = 1; state->rsel = 0;
} else if (rate >= 5626) {
state->deci = 2; state->csel = 1; state->rsel = 1;
} else if (rate >= 4688) {
state->deci = 3; state->csel = 0; state->rsel = 0;
} else if (rate >= 3751) {
state->deci = 3; state->csel = 0; state->rsel = 1;
} else if (rate >= 3282) {
state->deci = 3; state->csel = 1; state->rsel = 0;
} else if (rate >= 2814) {
state->deci = 3; state->csel = 1; state->rsel = 1;
} else if (rate >= 2344) {
state->deci = 4; state->csel = 0; state->rsel = 0;
} else if (rate >= 1876) {
state->deci = 4; state->csel = 0; state->rsel = 1;
} else if (rate >= 1641) {
state->deci = 4; state->csel = 1; state->rsel = 0;
} else if (rate >= 1407) {
state->deci = 4; state->csel = 1; state->rsel = 1;
} else if (rate >= 1172) {
state->deci = 5; state->csel = 0; state->rsel = 0;
} else if (rate >= 939) {
state->deci = 5; state->csel = 0; state->rsel = 1;
} else if (rate >= 821) {
state->deci = 5; state->csel = 1; state->rsel = 0;
} else {
state->deci = 5; state->csel = 1; state->rsel = 1;
}
if (state->csel == 0)
state->master_clk = 92000;
else
state->master_clk = 61333;
}
static int signal_det(struct mb86a16_state *state,
int smrt,
unsigned char *SIG)
{
int ret ;
int smrtd ;
int wait_sym ;
u32 wait_t;
unsigned char S[3] ;
int i ;
if (*SIG > 45) {
if (CNTM_set(state, 2, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
wait_sym = 40000;
} else {
if (CNTM_set(state, 3, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
wait_sym = 80000;
}
for (i = 0; i < 3; i++) {
if (i == 0)
smrtd = smrt * 98 / 100;
else if (i == 1)
smrtd = smrt;
else
smrtd = smrt * 102 / 100;
smrt_info_get(state, smrtd);
smrt_set(state, smrtd);
srst(state);
wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
if (wait_t == 0)
wait_t = 1;
msleep_interruptible(10);
if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
}
if ((S[1] > S[0] * 112 / 100) &&
(S[1] > S[2] * 112 / 100)) {
ret = 1;
} else {
ret = 0;
}
*SIG = S[1];
if (CNTM_set(state, 0, 1, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
return -1;
}
return ret;
}
static int rf_val_set(struct mb86a16_state *state,
int f,
int smrt,
unsigned char R)
{
unsigned char C, F, B;
int M;
unsigned char rf_val[5];
int ack = -1;
if (smrt > 37750)
C = 1;
else if (smrt > 18875)
C = 2;
else if (smrt > 5500)
C = 3;
else
C = 4;
if (smrt > 30500)
F = 3;
else if (smrt > 9375)
F = 1;
else if (smrt > 4625)
F = 0;
else
F = 2;
if (f < 1060)
B = 0;
else if (f < 1175)
B = 1;
else if (f < 1305)
B = 2;
else if (f < 1435)
B = 3;
else if (f < 1570)
B = 4;
else if (f < 1715)
B = 5;
else if (f < 1845)
B = 6;
else if (f < 1980)
B = 7;
else if (f < 2080)
B = 8;
else
B = 9;
M = f * (1 << R) / 2;
rf_val[0] = 0x01 | (C << 3) | (F << 1);
rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
rf_val[2] = (M & 0x00ff0) >> 4;
rf_val[3] = ((M & 0x0000f) << 4) | B;
/* Frequency Set */
if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
ack = 0;
if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
ack = 0;
if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
ack = 0;
if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
ack = 0;
if (mb86a16_write(state, 0x25, 0x01) < 0)
ack = 0;
if (ack == 0) {
dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int afcerr_chk(struct mb86a16_state *state)
{
unsigned char AFCM_L, AFCM_H ;
int AFCM ;
int afcm, afcerr ;
if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
goto err;
if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
goto err;
AFCM = (AFCM_H << 8) + AFCM_L;
if (AFCM > 2048)
afcm = AFCM - 4096;
else
afcm = AFCM;
afcerr = afcm * state->master_clk / 8192;
return afcerr;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int dagcm_val_get(struct mb86a16_state *state)
{
int DAGCM;
unsigned char DAGCM_H, DAGCM_L;
if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
goto err;
if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
goto err;
DAGCM = (DAGCM_H << 8) + DAGCM_L;
return DAGCM;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
u8 stat, stat2;
struct mb86a16_state *state = fe->demodulator_priv;
*status = 0;
if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
goto err;
if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
goto err;
if ((stat > 25) && (stat2 > 25))
*status |= FE_HAS_SIGNAL;
if ((stat > 45) && (stat2 > 45))
*status |= FE_HAS_CARRIER;
if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
goto err;
if (stat & 0x01)
*status |= FE_HAS_SYNC;
if (stat & 0x01)
*status |= FE_HAS_VITERBI;
if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
goto err;
if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
*status |= FE_HAS_LOCK;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int sync_chk(struct mb86a16_state *state,
unsigned char *VIRM)
{
unsigned char val;
int sync;
if (mb86a16_read(state, 0x0d, &val) != 2)
goto err;
dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
sync = val & 0x01;
*VIRM = (val & 0x1c) >> 2;
return sync;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int freqerr_chk(struct mb86a16_state *state,
int fTP,
int smrt,
int unit)
{
unsigned char CRM, AFCML, AFCMH;
unsigned char temp1, temp2, temp3;
int crm, afcm, AFCM;
int crrerr, afcerr; /* kHz */
int frqerr; /* MHz */
int afcen, afcexen = 0;
int R, M, fOSC, fOSC_OFS;
if (mb86a16_read(state, 0x43, &CRM) != 2)
goto err;
if (CRM > 127)
crm = CRM - 256;
else
crm = CRM;
crrerr = smrt * crm / 256;
if (mb86a16_read(state, 0x49, &temp1) != 2)
goto err;
afcen = (temp1 & 0x04) >> 2;
if (afcen == 0) {
if (mb86a16_read(state, 0x2a, &temp1) != 2)
goto err;
afcexen = (temp1 & 0x20) >> 5;
}
if (afcen == 1) {
if (mb86a16_read(state, 0x0e, &AFCML) != 2)
goto err;
if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
goto err;
} else if (afcexen == 1) {
if (mb86a16_read(state, 0x2b, &AFCML) != 2)
goto err;
if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
goto err;
}
if ((afcen == 1) || (afcexen == 1)) {
smrt_info_get(state, smrt);
AFCM = ((AFCMH & 0x01) << 8) + AFCML;
if (AFCM > 255)
afcm = AFCM - 512;
else
afcm = AFCM;
afcerr = afcm * state->master_clk / 8192;
} else
afcerr = 0;
if (mb86a16_read(state, 0x22, &temp1) != 2)
goto err;
if (mb86a16_read(state, 0x23, &temp2) != 2)
goto err;
if (mb86a16_read(state, 0x24, &temp3) != 2)
goto err;
R = (temp1 & 0xe0) >> 5;
M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
if (R == 0)
fOSC = 2 * M;
else
fOSC = M;
fOSC_OFS = fOSC - fTP;
if (unit == 0) { /* MHz */
if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
else
frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
} else { /* kHz */
frqerr = crrerr + afcerr + fOSC_OFS * 1000;
}
return frqerr;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
{
unsigned char R;
if (smrt > 9375)
R = 0;
else
R = 1;
return R;
}
static void swp_info_get(struct mb86a16_state *state,
int fOSC_start,
int smrt,
int v, int R,
int swp_ofs,
int *fOSC,
int *afcex_freq,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
int crnt_swp_freq ;
crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
if (R == 0)
*fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
else
*fOSC = (crnt_swp_freq + 500) / 1000;
if (*fOSC >= crnt_swp_freq)
*afcex_freq = *fOSC * 1000 - crnt_swp_freq;
else
*afcex_freq = crnt_swp_freq - *fOSC * 1000;
AFCEX = *afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
{
int swp_freq ;
if ((i % 2 == 1) && (v <= vmax)) {
/* positive v (case 1) */
if ((v - 1 == vmin) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
(*(V + 30 + v - 1) > SIGMIN)) {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
} else if ((v == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v - 1)) &&
(*(V + 30 + v) > SIGMIN)) {
/* (case 2) */
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else if ((*(V + 30 + v) > 0) &&
(*(V + 30 + v - 1) > 0) &&
(*(V + 30 + v - 2) > 0) &&
(*(V + 30 + v - 3) > 0) &&
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
(*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
((*(V + 30 + v - 1) > SIGMIN) ||
(*(V + 30 + v - 2) > SIGMIN))) {
/* (case 3) */
if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
*SIG1 = *(V + 30 + v - 2);
}
} else if ((v == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v - 1) >= 0) &&
(*(V + 30 + v - 2) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v - 2)) &&
(*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
((*(V + 30 + v) > SIGMIN) ||
(*(V + 30 + v - 1) > SIGMIN))) {
/* (case 4) */
if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else {
swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
*SIG1 = *(V + 30 + v - 1);
}
} else {
swp_freq = -1 ;
}
} else if ((i % 2 == 0) && (v >= vmin)) {
/* Negative v (case 1) */
if ((*(V + 30 + v) > 0) &&
(*(V + 30 + v + 1) > 0) &&
(*(V + 30 + v + 2) > 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
(*(V + 30 + v + 1) > SIGMIN)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else if ((v + 1 == vmax) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 1) > SIGMIN)) {
/* (case 2) */
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v);
} else if ((v == vmin) &&
(*(V + 30 + v) > 0) &&
(*(V + 30 + v + 1) > 0) &&
(*(V + 30 + v + 2) > 0) &&
(*(V + 30 + v) > *(V + 30 + v + 1)) &&
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
(*(V + 30 + v) > SIGMIN)) {
/* (case 3) */
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else if ((*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 3) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
((*(V + 30 + v + 1) > SIGMIN) ||
(*(V + 30 + v + 2) > SIGMIN))) {
/* (case 4) */
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
*SIG1 = *(V + 30 + v + 2);
}
} else if ((*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 3) >= 0) &&
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
(*(V + 30 + v) > *(V + 30 + v + 3)) &&
(*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
((*(V + 30 + v) > SIGMIN) ||
(*(V + 30 + v + 1) > SIGMIN))) {
/* (case 5) */
if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
swp_freq = fOSC * 1000 + afcex_freq;
*SIG1 = *(V + 30 + v);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
}
} else if ((v + 2 == vmin) &&
(*(V + 30 + v) >= 0) &&
(*(V + 30 + v + 1) >= 0) &&
(*(V + 30 + v + 2) >= 0) &&
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
(*(V + 30 + v + 2) > *(V + 30 + v)) &&
((*(V + 30 + v + 1) > SIGMIN) ||
(*(V + 30 + v + 2) > SIGMIN))) {
/* (case 6) */
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
*SIG1 = *(V + 30 + v + 1);
} else {
swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
*SIG1 = *(V + 30 + v + 2);
}
} else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
swp_freq = fOSC * 1000;
*SIG1 = *(V + 30 + v);
} else
swp_freq = -1;
} else
swp_freq = -1;
return swp_freq;
}
static void swp_info_get2(struct mb86a16_state *state,
int smrt,
int R,
int swp_freq,
int *afcex_freq,
int *fOSC,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
if (R == 0)
*fOSC = (swp_freq + 1000) / 2000 * 2;
else
*fOSC = (swp_freq + 500) / 1000;
if (*fOSC >= swp_freq)
*afcex_freq = *fOSC * 1000 - swp_freq;
else
*afcex_freq = swp_freq - *fOSC * 1000;
AFCEX = *afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static void afcex_info_get(struct mb86a16_state *state,
int afcex_freq,
unsigned char *AFCEX_L,
unsigned char *AFCEX_H)
{
int AFCEX ;
AFCEX = afcex_freq * 8192 / state->master_clk;
*AFCEX_L = AFCEX & 0x00ff;
*AFCEX_H = (AFCEX & 0x0f00) >> 8;
}
static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
{
/* SLOCK0 = 0 */
if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
{
/* Viterbi Rate, IQ Settings */
if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int FEC_srst(struct mb86a16_state *state)
{
if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
{
if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
{
if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
return 0;
}
static int mb86a16_set_fe(struct mb86a16_state *state)
{
u8 agcval, cnmval;
int i, j;
int fOSC = 0;
int fOSC_start = 0;
int wait_t;
int fcp;
int swp_ofs;
int V[60];
u8 SIG1MIN;
unsigned char CREN, AFCEN, AFCEXEN;
unsigned char SIG1;
unsigned char TIMINT1, TIMINT2, TIMEXT;
unsigned char S0T, S1T;
unsigned char S2T;
/* unsigned char S2T, S3T; */
unsigned char S4T, S5T;
unsigned char AFCEX_L, AFCEX_H;
unsigned char R;
unsigned char VIRM;
unsigned char ETH, VIA;
unsigned char junk;
int loop;
int ftemp;
int v, vmax, vmin;
int vmax_his, vmin_his;
int swp_freq, prev_swp_freq[20];
int prev_freq_num;
int signal_dupl;
int afcex_freq;
int signal;
int afcerr;
int temp_freq, delta_freq;
int dagcm[4];
int smrt_d;
/* int freq_err; */
int n;
int ret = -1;
int sync;
dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
fcp = 3000;
swp_ofs = state->srate / 4;
for (i = 0; i < 60; i++)
V[i] = -1;
for (i = 0; i < 20; i++)
prev_swp_freq[i] = 0;
SIG1MIN = 25;
for (n = 0; ((n < 3) && (ret == -1)); n++) {
SEQ_set(state, 0);
iq_vt_set(state, 0);
CREN = 0;
AFCEN = 0;
AFCEXEN = 1;
TIMINT1 = 0;
TIMINT2 = 1;
TIMEXT = 2;
S1T = 0;
S0T = 0;
if (initial_set(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
return -1;
}
if (DAGC_data_set(state, 3, 2) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1; /* (0, 0) */
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1; /* (1, smrt) = (1, symbolrate) */
}
if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
return -1; /* (0, 1, 2) */
}
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1; /* (0, 0) */
}
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
return -1;
}
R = vco_dev_get(state, state->srate);
if (R == 1)
fOSC_start = state->frequency;
else if (R == 0) {
if (state->frequency % 2 == 0) {
fOSC_start = state->frequency;
} else {
fOSC_start = state->frequency + 1;
if (fOSC_start > 2150)
fOSC_start = state->frequency - 1;
}
}
loop = 1;
ftemp = fOSC_start * 1000;
vmax = 0 ;
while (loop == 1) {
ftemp = ftemp + swp_ofs;
vmax++;
/* Upper bound */
if (ftemp > 2150000) {
loop = 0;
vmax--;
} else {
if ((ftemp == 2150000) ||
(ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
loop = 0;
}
}
loop = 1;
ftemp = fOSC_start * 1000;
vmin = 0 ;
while (loop == 1) {
ftemp = ftemp - swp_ofs;
vmin--;
/* Lower bound */
if (ftemp < 950000) {
loop = 0;
vmin++;
} else {
if ((ftemp == 950000) ||
(state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
loop = 0;
}
}
wait_t = (8000 + state->srate / 2) / state->srate;
if (wait_t == 0)
wait_t = 1;
i = 0;
j = 0;
prev_freq_num = 0;
loop = 1;
signal = 0;
vmax_his = 0;
vmin_his = 0;
v = 0;
while (loop == 1) {
swp_info_get(state, fOSC_start, state->srate,
v, R, swp_ofs, &fOSC,
&afcex_freq, &AFCEX_L, &AFCEX_H);
udelay(100);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
udelay(100);
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
msleep_interruptible(wait_t);
if (mb86a16_read(state, 0x37, &SIG1) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -1;
}
V[30 + v] = SIG1 ;
swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
SIG1MIN, fOSC, afcex_freq,
swp_ofs, &SIG1); /* changed */
signal_dupl = 0;
for (j = 0; j < prev_freq_num; j++) {
if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
signal_dupl = 1;
dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
}
}
if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
prev_swp_freq[prev_freq_num] = swp_freq;
prev_freq_num++;
swp_info_get2(state, state->srate, R, swp_freq,
&afcex_freq, &fOSC,
&AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
signal = signal_det(state, state->srate, &SIG1);
if (signal == 1) {
dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
loop = 0;
} else {
dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
}
}
if (v > vmax)
vmax_his = 1 ;
if (v < vmin)
vmin_his = 1 ;
i++;
if ((i % 2 == 1) && (vmax_his == 1))
i++;
if ((i % 2 == 0) && (vmin_his == 1))
i++;
if (i % 2 == 1)
v = (i + 1) / 2;
else
v = -i / 2;
if ((vmax_his == 1) && (vmin_his == 1))
loop = 0 ;
}
if (signal == 1) {
dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
S1T = 7 ;
S0T = 1 ;
CREN = 0 ;
AFCEN = 1 ;
AFCEXEN = 0 ;
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1;
}
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
/* delay 4~200 */
wait_t = 200000 / state->master_clk + 200000 / state->srate;
msleep(wait_t);
afcerr = afcerr_chk(state);
if (afcerr == -1)
return -1;
swp_freq = fOSC * 1000 + afcerr ;
AFCEXEN = 1 ;
if (state->srate >= 1500)
smrt_d = state->srate / 3;
else
smrt_d = state->srate / 2;
smrt_info_get(state, smrt_d);
if (smrt_set(state, smrt_d) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
R = vco_dev_get(state, smrt_d);
if (DAGC_data_set(state, 2, 0) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
for (i = 0; i < 3; i++) {
temp_freq = swp_freq + (i - 1) * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[i] = dagcm_val_get(state);
}
if ((dagcm[0] > dagcm[1]) &&
(dagcm[0] > dagcm[2]) &&
(dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
temp_freq = swp_freq - 2 * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[3] = dagcm_val_get(state);
if (dagcm[3] > dagcm[1])
delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
else
delta_freq = 0;
} else if ((dagcm[2] > dagcm[1]) &&
(dagcm[2] > dagcm[0]) &&
(dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
temp_freq = swp_freq + 2 * state->srate / 8;
swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
return -1;
}
wait_t = 200000 / state->master_clk + 40000 / smrt_d;
msleep(wait_t);
dagcm[3] = dagcm_val_get(state);
if (dagcm[3] > dagcm[1])
delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
else
delta_freq = 0 ;
} else {
delta_freq = 0 ;
}
dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
swp_freq += delta_freq;
dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
} else {
S1T = 0;
S0T = 3;
CREN = 1;
AFCEN = 0;
AFCEXEN = 1;
if (S01T_set(state, S1T, S0T) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
return -1;
}
if (DAGC_data_set(state, 0, 0) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
return -1;
}
R = vco_dev_get(state, state->srate);
smrt_info_get(state, state->srate);
if (smrt_set(state, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
return -1;
}
if (EN_set(state, CREN, AFCEN) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
return -1;
}
if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
return -1;
}
swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
if (rf_val_set(state, fOSC, state->srate, R) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
return -1;
}
if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
return -1;
}
if (srst(state) < 0) {
dprintk(verbose, MB86A16_ERROR, 1, "srst error");
return -1;
}
wait_t = 7 + (10000 + state->srate / 2) / state->srate;
if (wait_t == 0)
wait_t = 1;
msleep_interruptible(wait_t);
if (mb86a16_read(state, 0x37, &SIG1) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
if (SIG1 > 110) {
S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
wait_t = 7 + (917504 + state->srate / 2) / state->srate;
} else if (SIG1 > 105) {
S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
} else if (SIG1 > 85) {
S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
} else if (SIG1 > 65) {
S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
} else {
S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
}
wait_t *= 2; /* FOS */
S2T_set(state, S2T);
S45T_set(state, S4T, S5T);
Vi_set(state, ETH, VIA);
srst(state);
msleep_interruptible(wait_t);
sync = sync_chk(state, &VIRM);
dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
if (VIRM) {
if (VIRM == 4) {
/* 5/6 */
if (SIG1 > 110)
wait_t = (786432 + state->srate / 2) / state->srate;
else
wait_t = (1572864 + state->srate / 2) / state->srate;
if (state->srate < 5000)
/* FIXME ! , should be a long wait ! */
msleep_interruptible(wait_t);
else
msleep_interruptible(wait_t);
if (sync_chk(state, &junk) == 0) {
iq_vt_set(state, 1);
FEC_srst(state);
}
}
/* 1/2, 2/3, 3/4, 7/8 */
if (SIG1 > 110)
wait_t = (786432 + state->srate / 2) / state->srate;
else
wait_t = (1572864 + state->srate / 2) / state->srate;
msleep_interruptible(wait_t);
SEQ_set(state, 1);
} else {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
SEQ_set(state, 1);
ret = -1;
}
}
} else {
dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
ret = -1;
}
sync = sync_chk(state, &junk);
if (sync) {
dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
freqerr_chk(state, state->frequency, state->srate, 1);
ret = 0;
break;
}
}
mb86a16_read(state, 0x15, &agcval);
mb86a16_read(state, 0x26, &cnmval);
dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
return ret;
}
static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
struct dvb_diseqc_master_cmd *cmd)
{
struct mb86a16_state *state = fe->demodulator_priv;
int i;
u8 regs;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
goto err;
regs = 0x18;
if (cmd->msg_len > 5 || cmd->msg_len < 4)
return -EINVAL;
for (i = 0; i < cmd->msg_len; i++) {
if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
goto err;
regs++;
}
i += 0x90;
msleep_interruptible(10);
if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
{
struct mb86a16_state *state = fe->demodulator_priv;
switch (burst) {
case SEC_MINI_A:
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_TBEN |
MB86A16_DCC1_TBO) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
case SEC_MINI_B:
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_TBEN) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
{
struct mb86a16_state *state = fe->demodulator_priv;
switch (tone) {
case SEC_TONE_ON:
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
MB86A16_DCC1_CTOE) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
goto err;
break;
case SEC_TONE_OFF:
if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
goto err;
if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
goto err;
break;
default:
return -EINVAL;
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mb86a16_state *state = fe->demodulator_priv;
state->frequency = p->frequency / 1000;
state->srate = p->symbol_rate / 1000;
if (!mb86a16_set_fe(state)) {
dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
return DVBFE_ALGO_SEARCH_SUCCESS;
}
dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
return DVBFE_ALGO_SEARCH_FAILED;
}
static void mb86a16_release(struct dvb_frontend *fe)
{
struct mb86a16_state *state = fe->demodulator_priv;
kfree(state);
}
static int mb86a16_init(struct dvb_frontend *fe)
{
return 0;
}
static int mb86a16_sleep(struct dvb_frontend *fe)
{
return 0;
}
static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
{
u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
u32 timer;
struct mb86a16_state *state = fe->demodulator_priv;
*ber = 0;
if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
goto err;
if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
goto err;
/* BER monitor invalid when BER_EN = 0 */
if (ber_mon & 0x04) {
/* coarse, fast calculation */
*ber = ber_tab & 0x1f;
dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
if (ber_mon & 0x01) {
/*
* BER_SEL = 1, The monitored BER is the estimated
* value with a Reed-Solomon decoder error amount at
* the deinterleaver output.
* monitored BER is expressed as a 20 bit output in total
*/
ber_rst = ber_mon >> 3;
*ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
if (ber_rst == 0)
timer = 12500000;
if (ber_rst == 1)
timer = 25000000;
if (ber_rst == 2)
timer = 50000000;
if (ber_rst == 3)
timer = 100000000;
*ber /= timer;
dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
} else {
/*
* BER_SEL = 0, The monitored BER is the estimated
* value with a Viterbi decoder error amount at the
* QPSK demodulator output.
* monitored BER is expressed as a 24 bit output in total
*/
ber_tim = ber_mon >> 1;
*ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
if (ber_tim == 0)
timer = 16;
if (ber_tim == 1)
timer = 24;
*ber /= 2 ^ timer;
dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
}
}
return 0;
err:
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
u8 agcm = 0;
struct mb86a16_state *state = fe->demodulator_priv;
*strength = 0;
if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
*strength = ((0xff - agcm) * 100) / 256;
dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
*strength = (0xffff - 0xff) + agcm;
return 0;
}
struct cnr {
u8 cn_reg;
u8 cn_val;
};
static const struct cnr cnr_tab[] = {
{ 35, 2 },
{ 40, 3 },
{ 50, 4 },
{ 60, 5 },
{ 70, 6 },
{ 80, 7 },
{ 92, 8 },
{ 103, 9 },
{ 115, 10 },
{ 138, 12 },
{ 162, 15 },
{ 180, 18 },
{ 185, 19 },
{ 189, 20 },
{ 195, 22 },
{ 199, 24 },
{ 201, 25 },
{ 202, 26 },
{ 203, 27 },
{ 205, 28 },
{ 208, 30 }
};
static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct mb86a16_state *state = fe->demodulator_priv;
int i = 0;
int low_tide = 2, high_tide = 30, q_level;
u8 cn;
*snr = 0;
if (mb86a16_read(state, 0x26, &cn) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
if (cn < cnr_tab[i].cn_reg) {
*snr = cnr_tab[i].cn_val;
break;
}
}
q_level = (*snr * 100) / (high_tide - low_tide);
dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
*snr = (0xffff - 0xff) + *snr;
return 0;
}
static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
u8 dist;
struct mb86a16_state *state = fe->demodulator_priv;
if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
return -EREMOTEIO;
}
*ucblocks = dist;
return 0;
}
static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_CUSTOM;
}
static struct dvb_frontend_ops mb86a16_ops = {
.delsys = { SYS_DVBS },
.info = {
.name = "Fujitsu MB86A16 DVB-S",
.frequency_min = 950000,
.frequency_max = 2150000,
.frequency_stepsize = 3000,
.frequency_tolerance = 0,
.symbol_rate_min = 1000000,
.symbol_rate_max = 45000000,
.symbol_rate_tolerance = 500,
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
FE_CAN_FEC_7_8 | FE_CAN_QPSK |
FE_CAN_FEC_AUTO
},
.release = mb86a16_release,
.get_frontend_algo = mb86a16_frontend_algo,
.search = mb86a16_search,
.init = mb86a16_init,
.sleep = mb86a16_sleep,
.read_status = mb86a16_read_status,
.read_ber = mb86a16_read_ber,
.read_signal_strength = mb86a16_read_signal_strength,
.read_snr = mb86a16_read_snr,
.read_ucblocks = mb86a16_read_ucblocks,
.diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
.diseqc_send_burst = mb86a16_send_diseqc_burst,
.set_tone = mb86a16_set_tone,
};
struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
struct i2c_adapter *i2c_adap)
{
u8 dev_id = 0;
struct mb86a16_state *state = NULL;
state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
if (state == NULL)
goto error;
state->config = config;
state->i2c_adap = i2c_adap;
mb86a16_read(state, 0x7f, &dev_id);
if (dev_id != 0xfe)
goto error;
memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
state->frontend.ops.set_voltage = state->config->set_voltage;
return &state->frontend;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL(mb86a16_attach);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Manu Abraham");
| gpl-2.0 |
davidmueller13/ZenKernel_Flounder | arch/x86/um/mem_32.c | 8530 | 1162 | /*
* Copyright (C) 2011 Richard Weinberger <richrd@nod.at>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/mm.h>
#include <asm/page.h>
#include <asm/mman.h>
static struct vm_area_struct gate_vma;
static int __init gate_vma_init(void)
{
if (!FIXADDR_USER_START)
return 0;
gate_vma.vm_mm = NULL;
gate_vma.vm_start = FIXADDR_USER_START;
gate_vma.vm_end = FIXADDR_USER_END;
gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
gate_vma.vm_page_prot = __P101;
return 0;
}
__initcall(gate_vma_init);
struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
{
return FIXADDR_USER_START ? &gate_vma : NULL;
}
int in_gate_area_no_mm(unsigned long addr)
{
if (!FIXADDR_USER_START)
return 0;
if ((addr >= FIXADDR_USER_START) && (addr < FIXADDR_USER_END))
return 1;
return 0;
}
int in_gate_area(struct mm_struct *mm, unsigned long addr)
{
struct vm_area_struct *vma = get_gate_vma(mm);
if (!vma)
return 0;
return (addr >= vma->vm_start) && (addr < vma->vm_end);
}
| gpl-2.0 |
CyanHacker-Lollipop/kernel_sony_msm8974pro | tools/perf/scripts/perl/Perf-Trace-Util/Context.c | 11602 | 3691 | /*
* This file was generated automatically by ExtUtils::ParseXS version 2.18_02 from the
* contents of Context.xs. Do not edit this file, edit Context.xs instead.
*
* ANY CHANGES MADE HERE WILL BE LOST!
*
*/
#line 1 "Context.xs"
/*
* Context.xs. XS interfaces for perf script.
*
* Copyright (C) 2009 Tom Zanussi <tzanussi@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include "EXTERN.h"
#include "perl.h"
#include "XSUB.h"
#include "../../../perf.h"
#include "../../../util/trace-event.h"
#ifndef PERL_UNUSED_VAR
# define PERL_UNUSED_VAR(var) if (0) var = var
#endif
#line 42 "Context.c"
XS(XS_Perf__Trace__Context_common_pc); /* prototype to pass -Wmissing-prototypes */
XS(XS_Perf__Trace__Context_common_pc)
{
#ifdef dVAR
dVAR; dXSARGS;
#else
dXSARGS;
#endif
if (items != 1)
Perl_croak(aTHX_ "Usage: %s(%s)", "Perf::Trace::Context::common_pc", "context");
PERL_UNUSED_VAR(cv); /* -W */
{
struct scripting_context * context = INT2PTR(struct scripting_context *,SvIV(ST(0)));
int RETVAL;
dXSTARG;
RETVAL = common_pc(context);
XSprePUSH; PUSHi((IV)RETVAL);
}
XSRETURN(1);
}
XS(XS_Perf__Trace__Context_common_flags); /* prototype to pass -Wmissing-prototypes */
XS(XS_Perf__Trace__Context_common_flags)
{
#ifdef dVAR
dVAR; dXSARGS;
#else
dXSARGS;
#endif
if (items != 1)
Perl_croak(aTHX_ "Usage: %s(%s)", "Perf::Trace::Context::common_flags", "context");
PERL_UNUSED_VAR(cv); /* -W */
{
struct scripting_context * context = INT2PTR(struct scripting_context *,SvIV(ST(0)));
int RETVAL;
dXSTARG;
RETVAL = common_flags(context);
XSprePUSH; PUSHi((IV)RETVAL);
}
XSRETURN(1);
}
XS(XS_Perf__Trace__Context_common_lock_depth); /* prototype to pass -Wmissing-prototypes */
XS(XS_Perf__Trace__Context_common_lock_depth)
{
#ifdef dVAR
dVAR; dXSARGS;
#else
dXSARGS;
#endif
if (items != 1)
Perl_croak(aTHX_ "Usage: %s(%s)", "Perf::Trace::Context::common_lock_depth", "context");
PERL_UNUSED_VAR(cv); /* -W */
{
struct scripting_context * context = INT2PTR(struct scripting_context *,SvIV(ST(0)));
int RETVAL;
dXSTARG;
RETVAL = common_lock_depth(context);
XSprePUSH; PUSHi((IV)RETVAL);
}
XSRETURN(1);
}
#ifdef __cplusplus
extern "C"
#endif
XS(boot_Perf__Trace__Context); /* prototype to pass -Wmissing-prototypes */
XS(boot_Perf__Trace__Context)
{
#ifdef dVAR
dVAR; dXSARGS;
#else
dXSARGS;
#endif
const char* file = __FILE__;
PERL_UNUSED_VAR(cv); /* -W */
PERL_UNUSED_VAR(items); /* -W */
XS_VERSION_BOOTCHECK ;
newXSproto("Perf::Trace::Context::common_pc", XS_Perf__Trace__Context_common_pc, file, "$");
newXSproto("Perf::Trace::Context::common_flags", XS_Perf__Trace__Context_common_flags, file, "$");
newXSproto("Perf::Trace::Context::common_lock_depth", XS_Perf__Trace__Context_common_lock_depth, file, "$");
if (PL_unitcheckav)
call_list(PL_scopestack_ix, PL_unitcheckav);
XSRETURN_YES;
}
| gpl-2.0 |
gdachs/linux | arch/mips/pci/fixup-tb0226.c | 13650 | 2397 | /*
* fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
*
* Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/vr41xx/giu.h>
#include <asm/vr41xx/tb0226.h>
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = -1;
switch (slot) {
case 12:
vr41xx_set_irq_trigger(GD82559_1_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
irq = GD82559_1_IRQ;
break;
case 13:
vr41xx_set_irq_trigger(GD82559_2_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
irq = GD82559_2_IRQ;
break;
case 14:
switch (pin) {
case 1:
vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTA_PIN,
IRQ_LEVEL_LOW);
irq = UPD720100_INTA_IRQ;
break;
case 2:
vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTB_PIN,
IRQ_LEVEL_LOW);
irq = UPD720100_INTB_IRQ;
break;
case 3:
vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTC_PIN,
IRQ_LEVEL_LOW);
irq = UPD720100_INTC_IRQ;
break;
default:
break;
}
break;
default:
break;
}
return irq;
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
| gpl-2.0 |
tbalden/android_kernel_htc_m9pw | drivers/usb/host/whci/asl.c | 13906 | 9704 | /*
* Wireless Host Controller (WHC) asynchronous schedule management.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/dma-mapping.h>
#include <linux/uwb/umc.h>
#include <linux/usb.h>
#include "../../wusbcore/wusbhc.h"
#include "whcd.h"
static void qset_get_next_prev(struct whc *whc, struct whc_qset *qset,
struct whc_qset **next, struct whc_qset **prev)
{
struct list_head *n, *p;
BUG_ON(list_empty(&whc->async_list));
n = qset->list_node.next;
if (n == &whc->async_list)
n = n->next;
p = qset->list_node.prev;
if (p == &whc->async_list)
p = p->prev;
*next = container_of(n, struct whc_qset, list_node);
*prev = container_of(p, struct whc_qset, list_node);
}
static void asl_qset_insert_begin(struct whc *whc, struct whc_qset *qset)
{
list_move(&qset->list_node, &whc->async_list);
qset->in_sw_list = true;
}
static void asl_qset_insert(struct whc *whc, struct whc_qset *qset)
{
struct whc_qset *next, *prev;
qset_clear(whc, qset);
/* Link into ASL. */
qset_get_next_prev(whc, qset, &next, &prev);
whc_qset_set_link_ptr(&qset->qh.link, next->qset_dma);
whc_qset_set_link_ptr(&prev->qh.link, qset->qset_dma);
qset->in_hw_list = true;
}
static void asl_qset_remove(struct whc *whc, struct whc_qset *qset)
{
struct whc_qset *prev, *next;
qset_get_next_prev(whc, qset, &next, &prev);
list_move(&qset->list_node, &whc->async_removed_list);
qset->in_sw_list = false;
/*
* No more qsets in the ASL? The caller must stop the ASL as
* it's no longer valid.
*/
if (list_empty(&whc->async_list))
return;
/* Remove from ASL. */
whc_qset_set_link_ptr(&prev->qh.link, next->qset_dma);
qset->in_hw_list = false;
}
/**
* process_qset - process any recently inactivated or halted qTDs in a
* qset.
*
* After inactive qTDs are removed, new qTDs can be added if the
* urb queue still contains URBs.
*
* Returns any additional WUSBCMD bits for the ASL sync command (i.e.,
* WUSBCMD_ASYNC_QSET_RM if a halted qset was removed).
*/
static uint32_t process_qset(struct whc *whc, struct whc_qset *qset)
{
enum whc_update update = 0;
uint32_t status = 0;
while (qset->ntds) {
struct whc_qtd *td;
int t;
t = qset->td_start;
td = &qset->qtd[qset->td_start];
status = le32_to_cpu(td->status);
/*
* Nothing to do with a still active qTD.
*/
if (status & QTD_STS_ACTIVE)
break;
if (status & QTD_STS_HALTED) {
/* Ug, an error. */
process_halted_qtd(whc, qset, td);
/* A halted qTD always triggers an update
because the qset was either removed or
reactivated. */
update |= WHC_UPDATE_UPDATED;
goto done;
}
/* Mmm, a completed qTD. */
process_inactive_qtd(whc, qset, td);
}
if (!qset->remove)
update |= qset_add_qtds(whc, qset);
done:
/*
* Remove this qset from the ASL if requested, but only if has
* no qTDs.
*/
if (qset->remove && qset->ntds == 0) {
asl_qset_remove(whc, qset);
update |= WHC_UPDATE_REMOVED;
}
return update;
}
void asl_start(struct whc *whc)
{
struct whc_qset *qset;
qset = list_first_entry(&whc->async_list, struct whc_qset, list_node);
le_writeq(qset->qset_dma | QH_LINK_NTDS(8), whc->base + WUSBASYNCLISTADDR);
whc_write_wusbcmd(whc, WUSBCMD_ASYNC_EN, WUSBCMD_ASYNC_EN);
whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS,
WUSBSTS_ASYNC_SCHED, WUSBSTS_ASYNC_SCHED,
1000, "start ASL");
}
void asl_stop(struct whc *whc)
{
whc_write_wusbcmd(whc, WUSBCMD_ASYNC_EN, 0);
whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS,
WUSBSTS_ASYNC_SCHED, 0,
1000, "stop ASL");
}
/**
* asl_update - request an ASL update and wait for the hardware to be synced
* @whc: the WHCI HC
* @wusbcmd: WUSBCMD value to start the update.
*
* If the WUSB HC is inactive (i.e., the ASL is stopped) then the
* update must be skipped as the hardware may not respond to update
* requests.
*/
void asl_update(struct whc *whc, uint32_t wusbcmd)
{
struct wusbhc *wusbhc = &whc->wusbhc;
long t;
mutex_lock(&wusbhc->mutex);
if (wusbhc->active) {
whc_write_wusbcmd(whc, wusbcmd, wusbcmd);
t = wait_event_timeout(
whc->async_list_wq,
(le_readl(whc->base + WUSBCMD) & WUSBCMD_ASYNC_UPDATED) == 0,
msecs_to_jiffies(1000));
if (t == 0)
whc_hw_error(whc, "ASL update timeout");
}
mutex_unlock(&wusbhc->mutex);
}
/**
* scan_async_work - scan the ASL for qsets to process.
*
* Process each qset in the ASL in turn and then signal the WHC that
* the ASL has been updated.
*
* Then start, stop or update the asynchronous schedule as required.
*/
void scan_async_work(struct work_struct *work)
{
struct whc *whc = container_of(work, struct whc, async_work);
struct whc_qset *qset, *t;
enum whc_update update = 0;
spin_lock_irq(&whc->lock);
/*
* Transerve the software list backwards so new qsets can be
* safely inserted into the ASL without making it non-circular.
*/
list_for_each_entry_safe_reverse(qset, t, &whc->async_list, list_node) {
if (!qset->in_hw_list) {
asl_qset_insert(whc, qset);
update |= WHC_UPDATE_ADDED;
}
update |= process_qset(whc, qset);
}
spin_unlock_irq(&whc->lock);
if (update) {
uint32_t wusbcmd = WUSBCMD_ASYNC_UPDATED | WUSBCMD_ASYNC_SYNCED_DB;
if (update & WHC_UPDATE_REMOVED)
wusbcmd |= WUSBCMD_ASYNC_QSET_RM;
asl_update(whc, wusbcmd);
}
/*
* Now that the ASL is updated, complete the removal of any
* removed qsets.
*
* If the qset was to be reset, do so and reinsert it into the
* ASL if it has pending transfers.
*/
spin_lock_irq(&whc->lock);
list_for_each_entry_safe(qset, t, &whc->async_removed_list, list_node) {
qset_remove_complete(whc, qset);
if (qset->reset) {
qset_reset(whc, qset);
if (!list_empty(&qset->stds)) {
asl_qset_insert_begin(whc, qset);
queue_work(whc->workqueue, &whc->async_work);
}
}
}
spin_unlock_irq(&whc->lock);
}
/**
* asl_urb_enqueue - queue an URB onto the asynchronous list (ASL).
* @whc: the WHCI host controller
* @urb: the URB to enqueue
* @mem_flags: flags for any memory allocations
*
* The qset for the endpoint is obtained and the urb queued on to it.
*
* Work is scheduled to update the hardware's view of the ASL.
*/
int asl_urb_enqueue(struct whc *whc, struct urb *urb, gfp_t mem_flags)
{
struct whc_qset *qset;
int err;
unsigned long flags;
spin_lock_irqsave(&whc->lock, flags);
err = usb_hcd_link_urb_to_ep(&whc->wusbhc.usb_hcd, urb);
if (err < 0) {
spin_unlock_irqrestore(&whc->lock, flags);
return err;
}
qset = get_qset(whc, urb, GFP_ATOMIC);
if (qset == NULL)
err = -ENOMEM;
else
err = qset_add_urb(whc, qset, urb, GFP_ATOMIC);
if (!err) {
if (!qset->in_sw_list && !qset->remove)
asl_qset_insert_begin(whc, qset);
} else
usb_hcd_unlink_urb_from_ep(&whc->wusbhc.usb_hcd, urb);
spin_unlock_irqrestore(&whc->lock, flags);
if (!err)
queue_work(whc->workqueue, &whc->async_work);
return err;
}
/**
* asl_urb_dequeue - remove an URB (qset) from the async list.
* @whc: the WHCI host controller
* @urb: the URB to dequeue
* @status: the current status of the URB
*
* URBs that do yet have qTDs can simply be removed from the software
* queue, otherwise the qset must be removed from the ASL so the qTDs
* can be removed.
*/
int asl_urb_dequeue(struct whc *whc, struct urb *urb, int status)
{
struct whc_urb *wurb = urb->hcpriv;
struct whc_qset *qset = wurb->qset;
struct whc_std *std, *t;
bool has_qtd = false;
int ret;
unsigned long flags;
spin_lock_irqsave(&whc->lock, flags);
ret = usb_hcd_check_unlink_urb(&whc->wusbhc.usb_hcd, urb, status);
if (ret < 0)
goto out;
list_for_each_entry_safe(std, t, &qset->stds, list_node) {
if (std->urb == urb) {
if (std->qtd)
has_qtd = true;
qset_free_std(whc, std);
} else
std->qtd = NULL; /* so this std is re-added when the qset is */
}
if (has_qtd) {
asl_qset_remove(whc, qset);
wurb->status = status;
wurb->is_async = true;
queue_work(whc->workqueue, &wurb->dequeue_work);
} else
qset_remove_urb(whc, qset, urb, status);
out:
spin_unlock_irqrestore(&whc->lock, flags);
return ret;
}
/**
* asl_qset_delete - delete a qset from the ASL
*/
void asl_qset_delete(struct whc *whc, struct whc_qset *qset)
{
qset->remove = 1;
queue_work(whc->workqueue, &whc->async_work);
qset_delete(whc, qset);
}
/**
* asl_init - initialize the asynchronous schedule list
*
* A dummy qset with no qTDs is added to the ASL to simplify removing
* qsets (no need to stop the ASL when the last qset is removed).
*/
int asl_init(struct whc *whc)
{
struct whc_qset *qset;
qset = qset_alloc(whc, GFP_KERNEL);
if (qset == NULL)
return -ENOMEM;
asl_qset_insert_begin(whc, qset);
asl_qset_insert(whc, qset);
return 0;
}
/**
* asl_clean_up - free ASL resources
*
* The ASL is stopped and empty except for the dummy qset.
*/
void asl_clean_up(struct whc *whc)
{
struct whc_qset *qset;
if (!list_empty(&whc->async_list)) {
qset = list_first_entry(&whc->async_list, struct whc_qset, list_node);
list_del(&qset->list_node);
qset_free(whc, qset);
}
}
| gpl-2.0 |
cocasse/linux-h3 | drivers/staging/netlogic/xlr_net.c | 83 | 32251 | /*
* Copyright (c) 2003-2012 Broadcom Corporation
* All Rights Reserved
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the Broadcom
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/phy.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/smp.h>
#include <linux/ethtool.h>
#include <linux/module.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <asm/mipsregs.h>
/*
* fmn.h - For FMN credit configuration and registering fmn_handler.
* FMN is communication mechanism that allows processing agents within
* XLR/XLS to communicate each other.
*/
#include <asm/netlogic/xlr/fmn.h>
#include "platform_net.h"
#include "xlr_net.h"
/*
* The readl/writel implementation byteswaps on XLR/XLS, so
* we need to use __raw_ IO to read the NAE registers
* because they are in the big-endian MMIO area on the SoC.
*/
static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
{
__raw_writel(val, base + reg);
}
static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
{
return __raw_readl(base + reg);
}
static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
{
u32 tmp;
tmp = xlr_nae_rdreg(base_addr, off);
xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
}
#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
{
struct nlm_fmn_msg msg;
int ret = 0, num_try = 0, stnid;
unsigned long paddr, mflags;
paddr = virt_to_bus(addr);
msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
msg.msg1 = 0;
msg.msg2 = 0;
msg.msg3 = 0;
stnid = priv->nd->rfr_station;
do {
mflags = nlm_cop2_enable_irqsave();
ret = nlm_fmn_send(1, 0, stnid, &msg);
nlm_cop2_disable_irqrestore(mflags);
if (ret == 0)
return 0;
} while (++num_try < 10000);
netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
return ret;
}
static inline unsigned char *xlr_alloc_skb(void)
{
struct sk_buff *skb;
int buf_len = sizeof(struct sk_buff *);
unsigned char *skb_data;
/* skb->data is cache aligned */
skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
if (!skb)
return NULL;
skb_data = skb->data;
skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
memcpy(skb_data, &skb, buf_len);
return skb->data;
}
static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
struct nlm_fmn_msg *msg, void *arg)
{
struct sk_buff *skb;
void *skb_data = NULL;
struct net_device *ndev;
struct xlr_net_priv *priv;
u32 port, length;
unsigned char *addr;
struct xlr_adapter *adapter = arg;
length = (msg->msg0 >> 40) & 0x3fff;
if (length == 0) {
addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
addr = addr - MAC_SKB_BACK_PTR_SIZE;
skb = (struct sk_buff *)(*(unsigned long *)addr);
dev_kfree_skb_any((struct sk_buff *)addr);
} else {
addr = (unsigned char *)
bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
length = length - BYTE_OFFSET - MAC_CRC_LEN;
port = ((int)msg->msg0) & 0x0f;
addr = addr - MAC_SKB_BACK_PTR_SIZE;
skb = (struct sk_buff *)(*(unsigned long *)addr);
skb->dev = adapter->netdev[port];
if (!skb->dev)
return;
ndev = skb->dev;
priv = netdev_priv(ndev);
/* 16 byte IP header align */
skb_reserve(skb, BYTE_OFFSET);
skb_put(skb, length);
skb->protocol = eth_type_trans(skb, skb->dev);
skb->dev->last_rx = jiffies;
netif_rx(skb);
/* Fill rx ring */
skb_data = xlr_alloc_skb();
if (skb_data)
send_to_rfr_fifo(priv, skb_data);
}
}
static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
{
return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
}
/*
* Ethtool operation
*/
static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
struct phy_device *phydev = xlr_get_phydev(priv);
if (!phydev)
return -ENODEV;
return phy_ethtool_gset(phydev, ecmd);
}
static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
struct phy_device *phydev = xlr_get_phydev(priv);
if (!phydev)
return -ENODEV;
return phy_ethtool_sset(phydev, ecmd);
}
static const struct ethtool_ops xlr_ethtool_ops = {
.get_settings = xlr_get_settings,
.set_settings = xlr_set_settings,
};
/*
* Net operations
*/
static int xlr_net_fill_rx_ring(struct net_device *ndev)
{
void *skb_data;
struct xlr_net_priv *priv = netdev_priv(ndev);
int i;
for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
skb_data = xlr_alloc_skb();
if (!skb_data) {
netdev_err(ndev, "SKB allocation failed\n");
return -ENOMEM;
}
send_to_rfr_fifo(priv, skb_data);
}
netdev_info(ndev, "Rx ring setup done\n");
return 0;
}
static int xlr_net_open(struct net_device *ndev)
{
u32 err;
struct xlr_net_priv *priv = netdev_priv(ndev);
struct phy_device *phydev = xlr_get_phydev(priv);
/* schedule a link state check */
phy_start(phydev);
err = phy_start_aneg(phydev);
if (err) {
pr_err("Autoneg failed\n");
return err;
}
/* Setup the speed from PHY to internal reg*/
xlr_set_gmac_speed(priv);
netif_tx_start_all_queues(ndev);
return 0;
}
static int xlr_net_stop(struct net_device *ndev)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
struct phy_device *phydev = xlr_get_phydev(priv);
phy_stop(phydev);
netif_tx_stop_all_queues(ndev);
return 0;
}
static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
struct sk_buff *skb)
{
unsigned long physkb = virt_to_phys(skb);
int cpu_core = nlm_core_id();
int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
((u64)127 << 54) | /* No Free back */
(u64)skb->len << 40 | /* Length of data */
((u64)addr));
msg->msg1 = (((u64)1 << 63) |
((u64)fr_stn_id << 54) | /* Free back id */
(u64)0 << 40 | /* Set len to 0 */
((u64)physkb & 0xffffffff)); /* 32bit address */
msg->msg2 = 0;
msg->msg3 = 0;
}
static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
struct net_device *ndev)
{
struct nlm_fmn_msg msg;
struct xlr_net_priv *priv = netdev_priv(ndev);
int ret;
u32 flags;
xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
flags = nlm_cop2_enable_irqsave();
ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
nlm_cop2_disable_irqrestore(flags);
if (ret)
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
}
static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
void *accel_priv,
select_queue_fallback_t fallback)
{
return (u16)smp_processor_id();
}
static void xlr_hw_set_mac_addr(struct net_device *ndev)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
/* set mac station address */
xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
(ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
(1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
(1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
(1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
}
static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
{
int err;
err = eth_mac_addr(ndev, data);
if (err)
return err;
xlr_hw_set_mac_addr(ndev);
return 0;
}
static void xlr_set_rx_mode(struct net_device *ndev)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
u32 regval;
regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
if (ndev->flags & IFF_PROMISC) {
regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
(1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
(1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
(1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
} else {
regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
(1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
}
xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
}
static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
RX_DROP_PACKET_COUNTER);
stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
TX_DROP_FRAME_COUNTER);
stats->multicast = xlr_nae_rdreg(priv->base_addr,
RX_MULTICAST_PACKET_COUNTER);
stats->collisions = xlr_nae_rdreg(priv->base_addr,
TX_TOTAL_COLLISION_COUNTER);
stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
RX_FRAME_LENGTH_ERROR_COUNTER);
stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
RX_DROP_PACKET_COUNTER);
stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
RX_FCS_ERROR_COUNTER);
stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
RX_ALIGNMENT_ERROR_COUNTER);
stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
RX_DROP_PACKET_COUNTER);
stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
RX_CARRIER_SENSE_ERROR_COUNTER);
stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
stats->rx_frame_errors + stats->rx_fifo_errors +
stats->rx_missed_errors);
stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
TX_DROP_FRAME_COUNTER);
stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
TX_DROP_FRAME_COUNTER);
}
static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
struct rtnl_link_stats64 *stats
)
{
xlr_stats(ndev, stats);
return stats;
}
static const struct net_device_ops xlr_netdev_ops = {
.ndo_open = xlr_net_open,
.ndo_stop = xlr_net_stop,
.ndo_start_xmit = xlr_net_start_xmit,
.ndo_select_queue = xlr_net_select_queue,
.ndo_set_mac_address = xlr_net_set_mac_addr,
.ndo_set_rx_mode = xlr_set_rx_mode,
.ndo_get_stats64 = xlr_get_stats64,
};
/*
* Gmac init
*/
static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
int reg_start_1, int reg_size, int size)
{
void *spill;
u32 *base;
unsigned long phys_addr;
u32 spill_size;
base = priv->base_addr;
spill_size = size;
spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
if (!spill) {
pr_err("Unable to allocate memory for spill area!\n");
return ZERO_SIZE_PTR;
}
spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
phys_addr = virt_to_phys(spill);
dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
size, phys_addr);
xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
xlr_nae_wreg(base, reg_size, spill_size);
return spill;
}
/*
* Configure the 6 FIFO's that are used by the network accelarator to
* communicate with the rest of the XLx device. 4 of the FIFO's are for
* packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
* the NA with free descriptors.
*/
static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
{
priv->frin_spill = xlr_config_spill(priv,
R_REG_FRIN_SPILL_MEM_START_0,
R_REG_FRIN_SPILL_MEM_START_1,
R_REG_FRIN_SPILL_MEM_SIZE,
MAX_FRIN_SPILL *
sizeof(u64));
priv->frout_spill = xlr_config_spill(priv,
R_FROUT_SPILL_MEM_START_0,
R_FROUT_SPILL_MEM_START_1,
R_FROUT_SPILL_MEM_SIZE,
MAX_FROUT_SPILL *
sizeof(u64));
priv->class_0_spill = xlr_config_spill(priv,
R_CLASS0_SPILL_MEM_START_0,
R_CLASS0_SPILL_MEM_START_1,
R_CLASS0_SPILL_MEM_SIZE,
MAX_CLASS_0_SPILL *
sizeof(u64));
priv->class_1_spill = xlr_config_spill(priv,
R_CLASS1_SPILL_MEM_START_0,
R_CLASS1_SPILL_MEM_START_1,
R_CLASS1_SPILL_MEM_SIZE,
MAX_CLASS_1_SPILL *
sizeof(u64));
priv->class_2_spill = xlr_config_spill(priv,
R_CLASS2_SPILL_MEM_START_0,
R_CLASS2_SPILL_MEM_START_1,
R_CLASS2_SPILL_MEM_SIZE,
MAX_CLASS_2_SPILL *
sizeof(u64));
priv->class_3_spill = xlr_config_spill(priv,
R_CLASS3_SPILL_MEM_START_0,
R_CLASS3_SPILL_MEM_START_1,
R_CLASS3_SPILL_MEM_SIZE,
MAX_CLASS_3_SPILL *
sizeof(u64));
}
/*
* Configure PDE to Round-Robin distribution of packets to the
* available cpu
*/
static void xlr_config_pde(struct xlr_net_priv *priv)
{
int i = 0;
u64 bkt_map = 0;
/* Each core has 8 buckets(station) */
for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
bkt_map |= (0xff << (i * 8));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
((bkt_map >> 32) & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
((bkt_map >> 32) & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
((bkt_map >> 32) & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
((bkt_map >> 32) & 0xffffffff));
}
/*
* Setup the Message ring credits, bucket size and other
* common configuration
*/
static int xlr_config_common(struct xlr_net_priv *priv)
{
struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
int start_stn_id = gmac->start_stn_id;
int end_stn_id = gmac->end_stn_id;
int *bucket_size = priv->nd->bucket_size;
int i, j, err;
/* Setting non-core MsgBktSize(0x321 - 0x325) */
for (i = start_stn_id; i <= end_stn_id; i++) {
xlr_nae_wreg(priv->base_addr,
R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
bucket_size[i]);
}
/*
* Setting non-core Credit counter register
* Distributing Gmac's credit to CPU's
*/
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++)
xlr_nae_wreg(priv->base_addr,
(R_CC_CPU0_0 + (i * 8)) + j,
gmac->credit_config[(i * 8) + j]);
}
xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
err = xlr_net_fill_rx_ring(priv->ndev);
if (err)
return err;
nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
priv->adapter);
return 0;
}
static void xlr_config_translate_table(struct xlr_net_priv *priv)
{
u32 cpu_mask;
u32 val;
int bkts[32]; /* one bucket is assumed for each cpu */
int b1, b2, c1, c2, i, j, k;
int use_bkt;
use_bkt = 0;
cpu_mask = priv->nd->cpu_mask;
pr_info("Using %s-based distribution\n",
(use_bkt) ? "bucket" : "class");
j = 0;
for (i = 0; i < 32; i++) {
if ((1 << i) & cpu_mask) {
/* for each cpu, mark the 4+threadid bucket */
bkts[j] = ((i / 4) * 8) + (i % 4);
j++;
}
}
/*configure the 128 * 9 Translation table to send to available buckets*/
k = 0;
c1 = 3;
c2 = 0;
for (i = 0; i < 64; i++) {
/*
* On use_bkt set the b0, b1 are used, else
* the 4 classes are used, here implemented
* a logic to distribute the packets to the
* buckets equally or based on the class
*/
c1 = (c1 + 1) & 3;
c2 = (c1 + 1) & 3;
b1 = bkts[k];
k = (k + 1) % j;
b2 = bkts[k];
k = (k + 1) % j;
val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
(c2 << 7) | (b2 << 1) | (use_bkt << 0));
dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
i, b1, b2, c1, c2);
xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
c1 = c2;
}
}
static void xlr_config_parser(struct xlr_net_priv *priv)
{
u32 val;
/* Mark it as ETHERNET type */
xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
/* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
((0x7f << 8) | (1 << 1)));
/* configure the parser : L2 Type is configured in the bootloader */
/* extract IP: src, dest protocol */
xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
(9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
(0x0800 << 0));
xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
(9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
(16 << 4) | 4);
/* Configure to extract SRC port and Dest port for TCP and UDP pkts */
xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
xlr_config_translate_table(priv);
}
static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
{
unsigned long timeout, stoptime, checktime;
int timedout;
/* 100ms timeout*/
timeout = msecs_to_jiffies(100);
stoptime = jiffies + timeout;
timedout = 0;
xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
/* Write the data which starts the write cycle */
xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
/* poll for the read cycle to complete */
while (!timedout) {
checktime = jiffies;
if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
break;
timedout = time_after(checktime, stoptime);
}
if (timedout) {
pr_info("Phy device write err: device busy");
return -EBUSY;
}
return 0;
}
static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
{
unsigned long timeout, stoptime, checktime;
int timedout;
/* 100ms timeout*/
timeout = msecs_to_jiffies(100);
stoptime = jiffies + timeout;
timedout = 0;
/* setup the phy reg to be used */
xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
(phy_addr << 8) | (regnum << 0));
/* Issue the read command */
xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
(1 << O_MII_MGMT_COMMAND__rstat));
/* poll for the read cycle to complete */
while (!timedout) {
checktime = jiffies;
if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
break;
timedout = time_after(checktime, stoptime);
}
if (timedout) {
pr_info("Phy device read err: device busy");
return -EBUSY;
}
/* clear the read cycle */
xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
/* Read the data */
return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
}
static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
{
struct xlr_net_priv *priv = bus->priv;
int ret;
ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
phy_addr, regnum, val, ret);
return ret;
}
static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
{
struct xlr_net_priv *priv = bus->priv;
int ret;
ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
phy_addr, regnum, ret);
return ret;
}
/*
* XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
* which can be configured either SGMII or RGMII, considered SGMII
* by default, if board setup to RGMII the port_type need to set
* accordingly.Serdes and PCS layer need to configured for SGMII
*/
static void xlr_sgmii_init(struct xlr_net_priv *priv)
{
int phy;
xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
/* program GPIO values for serdes init parameters */
xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
/* enable autoneg - more magic */
phy = priv->phy_addr % 4 + 27;
xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
}
void xlr_set_gmac_speed(struct xlr_net_priv *priv)
{
struct phy_device *phydev = xlr_get_phydev(priv);
int speed;
if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
xlr_sgmii_init(priv);
if (phydev->speed != priv->phy_speed) {
speed = phydev->speed;
if (speed == SPEED_1000) {
/* Set interface to Byte mode */
xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
priv->phy_speed = speed;
} else if (speed == SPEED_100 || speed == SPEED_10) {
/* Set interface to Nibble mode */
xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
priv->phy_speed = speed;
}
/* Set SGMII speed in Interface control reg */
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
if (speed == SPEED_10)
xlr_nae_wreg(priv->base_addr,
R_INTERFACE_CONTROL,
SGMII_SPEED_10);
if (speed == SPEED_100)
xlr_nae_wreg(priv->base_addr,
R_INTERFACE_CONTROL,
SGMII_SPEED_100);
if (speed == SPEED_1000)
xlr_nae_wreg(priv->base_addr,
R_INTERFACE_CONTROL,
SGMII_SPEED_1000);
}
if (speed == SPEED_10)
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
if (speed == SPEED_100)
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
if (speed == SPEED_1000)
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
}
pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
}
static void xlr_gmac_link_adjust(struct net_device *ndev)
{
struct xlr_net_priv *priv = netdev_priv(ndev);
struct phy_device *phydev = xlr_get_phydev(priv);
u32 intreg;
intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
if (phydev->link) {
if (phydev->speed != priv->phy_speed) {
xlr_set_gmac_speed(priv);
pr_info("gmac%d : Link up\n", priv->port_id);
}
} else {
xlr_set_gmac_speed(priv);
pr_info("gmac%d : Link down\n", priv->port_id);
}
}
static int xlr_mii_probe(struct xlr_net_priv *priv)
{
struct phy_device *phydev = xlr_get_phydev(priv);
if (!phydev) {
pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
return -ENODEV;
}
/* Attach MAC to PHY */
phydev = phy_connect(priv->ndev, phydev_name(phydev),
xlr_gmac_link_adjust, priv->nd->phy_interface);
if (IS_ERR(phydev)) {
pr_err("could not attach PHY\n");
return PTR_ERR(phydev);
}
phydev->supported &= (ADVERTISED_10baseT_Full
| ADVERTISED_10baseT_Half
| ADVERTISED_100baseT_Full
| ADVERTISED_100baseT_Half
| ADVERTISED_1000baseT_Full
| ADVERTISED_Autoneg
| ADVERTISED_MII);
phydev->advertising = phydev->supported;
phy_attached_info(phydev);
return 0;
}
static int xlr_setup_mdio(struct xlr_net_priv *priv,
struct platform_device *pdev)
{
int err;
priv->mii_bus = mdiobus_alloc();
if (!priv->mii_bus) {
pr_err("mdiobus alloc failed\n");
return -ENOMEM;
}
priv->mii_bus->priv = priv;
priv->mii_bus->name = "xlr-mdio";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
priv->mii_bus->name, priv->port_id);
priv->mii_bus->read = xlr_mii_read;
priv->mii_bus->write = xlr_mii_write;
priv->mii_bus->parent = &pdev->dev;
/* Scan only the enabled address */
priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
/* setting clock divisor to 54 */
xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
err = mdiobus_register(priv->mii_bus);
if (err) {
mdiobus_free(priv->mii_bus);
pr_err("mdio bus registration failed\n");
return err;
}
pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
err = xlr_mii_probe(priv);
if (err) {
mdiobus_free(priv->mii_bus);
return err;
}
return 0;
}
static void xlr_port_enable(struct xlr_net_priv *priv)
{
u32 prid = (read_c0_prid() & 0xf000);
/* Setup MAC_CONFIG reg if (xls & rgmii) */
if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
xlr_reg_update(priv->base_addr, R_RX_CONTROL,
(1 << O_RX_CONTROL__RGMII),
(1 << O_RX_CONTROL__RGMII));
/* Rx Tx enable */
xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
((1 << O_MAC_CONFIG_1__rxen) |
(1 << O_MAC_CONFIG_1__txen) |
(1 << O_MAC_CONFIG_1__rxfc) |
(1 << O_MAC_CONFIG_1__txfc)),
((1 << O_MAC_CONFIG_1__rxen) |
(1 << O_MAC_CONFIG_1__txen) |
(1 << O_MAC_CONFIG_1__rxfc) |
(1 << O_MAC_CONFIG_1__txfc)));
/* Setup tx control reg */
xlr_reg_update(priv->base_addr, R_TX_CONTROL,
((1 << O_TX_CONTROL__TXENABLE) |
(512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
/* Setup rx control reg */
xlr_reg_update(priv->base_addr, R_RX_CONTROL,
1 << O_RX_CONTROL__RXENABLE,
1 << O_RX_CONTROL__RXENABLE);
}
static void xlr_port_disable(struct xlr_net_priv *priv)
{
/* Setup MAC_CONFIG reg */
/* Rx Tx disable*/
xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
((1 << O_MAC_CONFIG_1__rxen) |
(1 << O_MAC_CONFIG_1__txen) |
(1 << O_MAC_CONFIG_1__rxfc) |
(1 << O_MAC_CONFIG_1__txfc)), 0x0);
/* Setup tx control reg */
xlr_reg_update(priv->base_addr, R_TX_CONTROL,
((1 << O_TX_CONTROL__TXENABLE) |
(512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
/* Setup rx control reg */
xlr_reg_update(priv->base_addr, R_RX_CONTROL,
1 << O_RX_CONTROL__RXENABLE, 0);
}
/*
* Initialization of gmac
*/
static int xlr_gmac_init(struct xlr_net_priv *priv,
struct platform_device *pdev)
{
int ret;
pr_info("Initializing the gmac%d\n", priv->port_id);
xlr_port_disable(priv);
xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
(1 << O_DESC_PACK_CTRL__MAXENTRY) |
(BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
(1600 << O_DESC_PACK_CTRL__REGULARSIZE));
ret = xlr_setup_mdio(priv, pdev);
if (ret)
return ret;
xlr_port_enable(priv);
/* Enable Full-duplex/1000Mbps/CRC */
xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
/* speed 2.5Mhz */
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
/* Setup Interrupt mask reg */
xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
(1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
(1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
(1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
/* Clear all stats */
xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
return 0;
}
static int xlr_net_probe(struct platform_device *pdev)
{
struct xlr_net_priv *priv = NULL;
struct net_device *ndev;
struct resource *res;
struct xlr_adapter *adapter;
int err, port;
pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
/*
* Allocate our adapter data structure and attach it to the device.
*/
adapter = (struct xlr_adapter *)
devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
if (!adapter) {
err = -ENOMEM;
return err;
}
/*
* XLR and XLS have 1 and 2 NAE controller respectively
* Each controller has 4 gmac ports, mapping each controller
* under one parent device, 4 gmac ports under one device.
*/
for (port = 0; port < pdev->num_resources / 2; port++) {
ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
if (!ndev) {
dev_err(&pdev->dev,
"Allocation of Ethernet device failed\n");
return -ENOMEM;
}
priv = netdev_priv(ndev);
priv->pdev = pdev;
priv->ndev = ndev;
priv->port_id = (pdev->id * 4) + port;
priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, port);
priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->base_addr)) {
err = PTR_ERR(priv->base_addr);
goto err_gmac;
}
priv->adapter = adapter;
adapter->netdev[port] = ndev;
res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
if (!res) {
dev_err(&pdev->dev, "No irq resource for MAC %d\n",
priv->port_id);
err = -ENODEV;
goto err_gmac;
}
ndev->irq = res->start;
priv->phy_addr = priv->nd->phy_addr[port];
priv->tx_stnid = priv->nd->tx_stnid[port];
priv->mii_addr = priv->nd->mii_addr;
priv->serdes_addr = priv->nd->serdes_addr;
priv->pcs_addr = priv->nd->pcs_addr;
priv->gpio_addr = priv->nd->gpio_addr;
ndev->netdev_ops = &xlr_netdev_ops;
ndev->watchdog_timeo = HZ;
/* Setup Mac address and Rx mode */
eth_hw_addr_random(ndev);
xlr_hw_set_mac_addr(ndev);
xlr_set_rx_mode(ndev);
priv->num_rx_desc += MAX_NUM_DESC_SPILL;
ndev->ethtool_ops = &xlr_ethtool_ops;
SET_NETDEV_DEV(ndev, &pdev->dev);
xlr_config_fifo_spill_area(priv);
/* Configure PDE to Round-Robin pkt distribution */
xlr_config_pde(priv);
xlr_config_parser(priv);
/* Call init with respect to port */
if (strcmp(res->name, "gmac") == 0) {
err = xlr_gmac_init(priv, pdev);
if (err) {
dev_err(&pdev->dev, "gmac%d init failed\n",
priv->port_id);
goto err_gmac;
}
}
if (priv->port_id == 0 || priv->port_id == 4) {
err = xlr_config_common(priv);
if (err)
goto err_netdev;
}
err = register_netdev(ndev);
if (err) {
dev_err(&pdev->dev,
"Registering netdev failed for gmac%d\n",
priv->port_id);
goto err_netdev;
}
platform_set_drvdata(pdev, priv);
}
return 0;
err_netdev:
mdiobus_free(priv->mii_bus);
err_gmac:
free_netdev(ndev);
return err;
}
static int xlr_net_remove(struct platform_device *pdev)
{
struct xlr_net_priv *priv = platform_get_drvdata(pdev);
unregister_netdev(priv->ndev);
mdiobus_unregister(priv->mii_bus);
mdiobus_free(priv->mii_bus);
free_netdev(priv->ndev);
return 0;
}
static struct platform_driver xlr_net_driver = {
.probe = xlr_net_probe,
.remove = xlr_net_remove,
.driver = {
.name = "xlr-net",
},
};
module_platform_driver(xlr_net_driver);
MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("platform:xlr-net");
| gpl-2.0 |
Chad0989/Vigor-Incredikernel | drivers/media/dvb/ngene/ngene-i2c.c | 851 | 4557 | /*
* ngene-i2c.c: nGene PCIe bridge driver i2c functions
*
* Copyright (C) 2005-2007 Micronas
*
* Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
* Modifications for new nGene firmware,
* support for EEPROM-copying,
* support for new dual DVB-S2 card prototype
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
/* FIXME - some of these can probably be removed */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/poll.h>
#include <linux/io.h>
#include <asm/div64.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/smp_lock.h>
#include <linux/timer.h>
#include <linux/byteorder/generic.h>
#include <linux/firmware.h>
#include <linux/vmalloc.h>
#include "ngene.h"
/* Firmware command for i2c operations */
static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
{
struct ngene_command com;
com.cmd.hdr.Opcode = CMD_I2C_READ;
com.cmd.hdr.Length = outlen + 3;
com.cmd.I2CRead.Device = adr << 1;
memcpy(com.cmd.I2CRead.Data, out, outlen);
com.cmd.I2CRead.Data[outlen] = inlen;
com.cmd.I2CRead.Data[outlen + 1] = 0;
com.in_len = outlen + 3;
com.out_len = inlen + 1;
if (ngene_command(dev, &com) < 0)
return -EIO;
if ((com.cmd.raw8[0] >> 1) != adr)
return -EIO;
if (flag)
memcpy(in, com.cmd.raw8, inlen + 1);
else
memcpy(in, com.cmd.raw8 + 1, inlen);
return 0;
}
static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
u8 *out, u8 outlen)
{
struct ngene_command com;
com.cmd.hdr.Opcode = CMD_I2C_WRITE;
com.cmd.hdr.Length = outlen + 1;
com.cmd.I2CRead.Device = adr << 1;
memcpy(com.cmd.I2CRead.Data, out, outlen);
com.in_len = outlen + 1;
com.out_len = 1;
if (ngene_command(dev, &com) < 0)
return -EIO;
if (com.cmd.raw8[0] == 1)
return -EIO;
return 0;
}
static void ngene_i2c_set_bus(struct ngene *dev, int bus)
{
if (!(dev->card_info->i2c_access & 2))
return;
if (dev->i2c_current_bus == bus)
return;
switch (bus) {
case 0:
ngene_command_gpio_set(dev, 3, 0);
ngene_command_gpio_set(dev, 2, 1);
break;
case 1:
ngene_command_gpio_set(dev, 2, 0);
ngene_command_gpio_set(dev, 3, 1);
break;
}
dev->i2c_current_bus = bus;
}
static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
struct i2c_msg msg[], int num)
{
struct ngene_channel *chan =
(struct ngene_channel *)i2c_get_adapdata(adapter);
struct ngene *dev = chan->dev;
down(&dev->i2c_switch_mutex);
ngene_i2c_set_bus(dev, chan->number);
if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
if (!ngene_command_i2c_read(dev, msg[0].addr,
msg[0].buf, msg[0].len,
msg[1].buf, msg[1].len, 0))
goto done;
if (num == 1 && !(msg[0].flags & I2C_M_RD))
if (!ngene_command_i2c_write(dev, msg[0].addr,
msg[0].buf, msg[0].len))
goto done;
if (num == 1 && (msg[0].flags & I2C_M_RD))
if (!ngene_command_i2c_read(dev, msg[0].addr, NULL, 0,
msg[0].buf, msg[0].len, 0))
goto done;
up(&dev->i2c_switch_mutex);
return -EIO;
done:
up(&dev->i2c_switch_mutex);
return num;
}
static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_SMBUS_EMUL;
}
static struct i2c_algorithm ngene_i2c_algo = {
.master_xfer = ngene_i2c_master_xfer,
.functionality = ngene_i2c_functionality,
};
int ngene_i2c_init(struct ngene *dev, int dev_nr)
{
struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
adap->class = I2C_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
strcpy(adap->name, "nGene");
adap->algo = &ngene_i2c_algo;
adap->algo_data = (void *)&(dev->channel[dev_nr]);
adap->dev.parent = &dev->pci_dev->dev;
return i2c_add_adapter(adap);
}
| gpl-2.0 |
MCherifiOSS/linux | drivers/infiniband/hw/ipath/ipath_qp.c | 1619 | 26715 | /*
* Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
* Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include "ipath_verbs.h"
#include "ipath_kernel.h"
#define BITS_PER_PAGE (PAGE_SIZE*BITS_PER_BYTE)
#define BITS_PER_PAGE_MASK (BITS_PER_PAGE-1)
#define mk_qpn(qpt, map, off) (((map) - (qpt)->map) * BITS_PER_PAGE + \
(off))
#define find_next_offset(map, off) find_next_zero_bit((map)->page, \
BITS_PER_PAGE, off)
/*
* Convert the AETH credit code into the number of credits.
*/
static u32 credit_table[31] = {
0, /* 0 */
1, /* 1 */
2, /* 2 */
3, /* 3 */
4, /* 4 */
6, /* 5 */
8, /* 6 */
12, /* 7 */
16, /* 8 */
24, /* 9 */
32, /* A */
48, /* B */
64, /* C */
96, /* D */
128, /* E */
192, /* F */
256, /* 10 */
384, /* 11 */
512, /* 12 */
768, /* 13 */
1024, /* 14 */
1536, /* 15 */
2048, /* 16 */
3072, /* 17 */
4096, /* 18 */
6144, /* 19 */
8192, /* 1A */
12288, /* 1B */
16384, /* 1C */
24576, /* 1D */
32768 /* 1E */
};
static void get_map_page(struct ipath_qp_table *qpt, struct qpn_map *map)
{
unsigned long page = get_zeroed_page(GFP_KERNEL);
unsigned long flags;
/*
* Free the page if someone raced with us installing it.
*/
spin_lock_irqsave(&qpt->lock, flags);
if (map->page)
free_page(page);
else
map->page = (void *)page;
spin_unlock_irqrestore(&qpt->lock, flags);
}
static int alloc_qpn(struct ipath_qp_table *qpt, enum ib_qp_type type)
{
u32 i, offset, max_scan, qpn;
struct qpn_map *map;
u32 ret = -1;
if (type == IB_QPT_SMI)
ret = 0;
else if (type == IB_QPT_GSI)
ret = 1;
if (ret != -1) {
map = &qpt->map[0];
if (unlikely(!map->page)) {
get_map_page(qpt, map);
if (unlikely(!map->page)) {
ret = -ENOMEM;
goto bail;
}
}
if (!test_and_set_bit(ret, map->page))
atomic_dec(&map->n_free);
else
ret = -EBUSY;
goto bail;
}
qpn = qpt->last + 1;
if (qpn >= QPN_MAX)
qpn = 2;
offset = qpn & BITS_PER_PAGE_MASK;
map = &qpt->map[qpn / BITS_PER_PAGE];
max_scan = qpt->nmaps - !offset;
for (i = 0;;) {
if (unlikely(!map->page)) {
get_map_page(qpt, map);
if (unlikely(!map->page))
break;
}
if (likely(atomic_read(&map->n_free))) {
do {
if (!test_and_set_bit(offset, map->page)) {
atomic_dec(&map->n_free);
qpt->last = qpn;
ret = qpn;
goto bail;
}
offset = find_next_offset(map, offset);
qpn = mk_qpn(qpt, map, offset);
/*
* This test differs from alloc_pidmap().
* If find_next_offset() does find a zero
* bit, we don't need to check for QPN
* wrapping around past our starting QPN.
* We just need to be sure we don't loop
* forever.
*/
} while (offset < BITS_PER_PAGE && qpn < QPN_MAX);
}
/*
* In order to keep the number of pages allocated to a
* minimum, we scan the all existing pages before increasing
* the size of the bitmap table.
*/
if (++i > max_scan) {
if (qpt->nmaps == QPNMAP_ENTRIES)
break;
map = &qpt->map[qpt->nmaps++];
offset = 0;
} else if (map < &qpt->map[qpt->nmaps]) {
++map;
offset = 0;
} else {
map = &qpt->map[0];
offset = 2;
}
qpn = mk_qpn(qpt, map, offset);
}
ret = -ENOMEM;
bail:
return ret;
}
static void free_qpn(struct ipath_qp_table *qpt, u32 qpn)
{
struct qpn_map *map;
map = qpt->map + qpn / BITS_PER_PAGE;
if (map->page)
clear_bit(qpn & BITS_PER_PAGE_MASK, map->page);
atomic_inc(&map->n_free);
}
/**
* ipath_alloc_qpn - allocate a QP number
* @qpt: the QP table
* @qp: the QP
* @type: the QP type (IB_QPT_SMI and IB_QPT_GSI are special)
*
* Allocate the next available QPN and put the QP into the hash table.
* The hash table holds a reference to the QP.
*/
static int ipath_alloc_qpn(struct ipath_qp_table *qpt, struct ipath_qp *qp,
enum ib_qp_type type)
{
unsigned long flags;
int ret;
ret = alloc_qpn(qpt, type);
if (ret < 0)
goto bail;
qp->ibqp.qp_num = ret;
/* Add the QP to the hash table. */
spin_lock_irqsave(&qpt->lock, flags);
ret %= qpt->max;
qp->next = qpt->table[ret];
qpt->table[ret] = qp;
atomic_inc(&qp->refcount);
spin_unlock_irqrestore(&qpt->lock, flags);
ret = 0;
bail:
return ret;
}
/**
* ipath_free_qp - remove a QP from the QP table
* @qpt: the QP table
* @qp: the QP to remove
*
* Remove the QP from the table so it can't be found asynchronously by
* the receive interrupt routine.
*/
static void ipath_free_qp(struct ipath_qp_table *qpt, struct ipath_qp *qp)
{
struct ipath_qp *q, **qpp;
unsigned long flags;
spin_lock_irqsave(&qpt->lock, flags);
/* Remove QP from the hash table. */
qpp = &qpt->table[qp->ibqp.qp_num % qpt->max];
for (; (q = *qpp) != NULL; qpp = &q->next) {
if (q == qp) {
*qpp = qp->next;
qp->next = NULL;
atomic_dec(&qp->refcount);
break;
}
}
spin_unlock_irqrestore(&qpt->lock, flags);
}
/**
* ipath_free_all_qps - check for QPs still in use
* @qpt: the QP table to empty
*
* There should not be any QPs still in use.
* Free memory for table.
*/
unsigned ipath_free_all_qps(struct ipath_qp_table *qpt)
{
unsigned long flags;
struct ipath_qp *qp;
u32 n, qp_inuse = 0;
spin_lock_irqsave(&qpt->lock, flags);
for (n = 0; n < qpt->max; n++) {
qp = qpt->table[n];
qpt->table[n] = NULL;
for (; qp; qp = qp->next)
qp_inuse++;
}
spin_unlock_irqrestore(&qpt->lock, flags);
for (n = 0; n < ARRAY_SIZE(qpt->map); n++)
if (qpt->map[n].page)
free_page((unsigned long) qpt->map[n].page);
return qp_inuse;
}
/**
* ipath_lookup_qpn - return the QP with the given QPN
* @qpt: the QP table
* @qpn: the QP number to look up
*
* The caller is responsible for decrementing the QP reference count
* when done.
*/
struct ipath_qp *ipath_lookup_qpn(struct ipath_qp_table *qpt, u32 qpn)
{
unsigned long flags;
struct ipath_qp *qp;
spin_lock_irqsave(&qpt->lock, flags);
for (qp = qpt->table[qpn % qpt->max]; qp; qp = qp->next) {
if (qp->ibqp.qp_num == qpn) {
atomic_inc(&qp->refcount);
break;
}
}
spin_unlock_irqrestore(&qpt->lock, flags);
return qp;
}
/**
* ipath_reset_qp - initialize the QP state to the reset state
* @qp: the QP to reset
* @type: the QP type
*/
static void ipath_reset_qp(struct ipath_qp *qp, enum ib_qp_type type)
{
qp->remote_qpn = 0;
qp->qkey = 0;
qp->qp_access_flags = 0;
atomic_set(&qp->s_dma_busy, 0);
qp->s_flags &= IPATH_S_SIGNAL_REQ_WR;
qp->s_hdrwords = 0;
qp->s_wqe = NULL;
qp->s_pkt_delay = 0;
qp->s_draining = 0;
qp->s_psn = 0;
qp->r_psn = 0;
qp->r_msn = 0;
if (type == IB_QPT_RC) {
qp->s_state = IB_OPCODE_RC_SEND_LAST;
qp->r_state = IB_OPCODE_RC_SEND_LAST;
} else {
qp->s_state = IB_OPCODE_UC_SEND_LAST;
qp->r_state = IB_OPCODE_UC_SEND_LAST;
}
qp->s_ack_state = IB_OPCODE_RC_ACKNOWLEDGE;
qp->r_nak_state = 0;
qp->r_aflags = 0;
qp->r_flags = 0;
qp->s_rnr_timeout = 0;
qp->s_head = 0;
qp->s_tail = 0;
qp->s_cur = 0;
qp->s_last = 0;
qp->s_ssn = 1;
qp->s_lsn = 0;
memset(qp->s_ack_queue, 0, sizeof(qp->s_ack_queue));
qp->r_head_ack_queue = 0;
qp->s_tail_ack_queue = 0;
qp->s_num_rd_atomic = 0;
if (qp->r_rq.wq) {
qp->r_rq.wq->head = 0;
qp->r_rq.wq->tail = 0;
}
}
/**
* ipath_error_qp - put a QP into the error state
* @qp: the QP to put into the error state
* @err: the receive completion error to signal if a RWQE is active
*
* Flushes both send and receive work queues.
* Returns true if last WQE event should be generated.
* The QP s_lock should be held and interrupts disabled.
* If we are already in error state, just return.
*/
int ipath_error_qp(struct ipath_qp *qp, enum ib_wc_status err)
{
struct ipath_ibdev *dev = to_idev(qp->ibqp.device);
struct ib_wc wc;
int ret = 0;
if (qp->state == IB_QPS_ERR)
goto bail;
qp->state = IB_QPS_ERR;
spin_lock(&dev->pending_lock);
if (!list_empty(&qp->timerwait))
list_del_init(&qp->timerwait);
if (!list_empty(&qp->piowait))
list_del_init(&qp->piowait);
spin_unlock(&dev->pending_lock);
/* Schedule the sending tasklet to drain the send work queue. */
if (qp->s_last != qp->s_head)
ipath_schedule_send(qp);
memset(&wc, 0, sizeof(wc));
wc.qp = &qp->ibqp;
wc.opcode = IB_WC_RECV;
if (test_and_clear_bit(IPATH_R_WRID_VALID, &qp->r_aflags)) {
wc.wr_id = qp->r_wr_id;
wc.status = err;
ipath_cq_enter(to_icq(qp->ibqp.recv_cq), &wc, 1);
}
wc.status = IB_WC_WR_FLUSH_ERR;
if (qp->r_rq.wq) {
struct ipath_rwq *wq;
u32 head;
u32 tail;
spin_lock(&qp->r_rq.lock);
/* sanity check pointers before trusting them */
wq = qp->r_rq.wq;
head = wq->head;
if (head >= qp->r_rq.size)
head = 0;
tail = wq->tail;
if (tail >= qp->r_rq.size)
tail = 0;
while (tail != head) {
wc.wr_id = get_rwqe_ptr(&qp->r_rq, tail)->wr_id;
if (++tail >= qp->r_rq.size)
tail = 0;
ipath_cq_enter(to_icq(qp->ibqp.recv_cq), &wc, 1);
}
wq->tail = tail;
spin_unlock(&qp->r_rq.lock);
} else if (qp->ibqp.event_handler)
ret = 1;
bail:
return ret;
}
/**
* ipath_modify_qp - modify the attributes of a queue pair
* @ibqp: the queue pair who's attributes we're modifying
* @attr: the new attributes
* @attr_mask: the mask of attributes to modify
* @udata: user data for ipathverbs.so
*
* Returns 0 on success, otherwise returns an errno.
*/
int ipath_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
int attr_mask, struct ib_udata *udata)
{
struct ipath_ibdev *dev = to_idev(ibqp->device);
struct ipath_qp *qp = to_iqp(ibqp);
enum ib_qp_state cur_state, new_state;
int lastwqe = 0;
int ret;
spin_lock_irq(&qp->s_lock);
cur_state = attr_mask & IB_QP_CUR_STATE ?
attr->cur_qp_state : qp->state;
new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
attr_mask, IB_LINK_LAYER_UNSPECIFIED))
goto inval;
if (attr_mask & IB_QP_AV) {
if (attr->ah_attr.dlid == 0 ||
attr->ah_attr.dlid >= IPATH_MULTICAST_LID_BASE)
goto inval;
if ((attr->ah_attr.ah_flags & IB_AH_GRH) &&
(attr->ah_attr.grh.sgid_index > 1))
goto inval;
}
if (attr_mask & IB_QP_PKEY_INDEX)
if (attr->pkey_index >= ipath_get_npkeys(dev->dd))
goto inval;
if (attr_mask & IB_QP_MIN_RNR_TIMER)
if (attr->min_rnr_timer > 31)
goto inval;
if (attr_mask & IB_QP_PORT)
if (attr->port_num == 0 ||
attr->port_num > ibqp->device->phys_port_cnt)
goto inval;
/*
* don't allow invalid Path MTU values or greater than 2048
* unless we are configured for a 4KB MTU
*/
if ((attr_mask & IB_QP_PATH_MTU) &&
(ib_mtu_enum_to_int(attr->path_mtu) == -1 ||
(attr->path_mtu > IB_MTU_2048 && !ipath_mtu4096)))
goto inval;
if (attr_mask & IB_QP_PATH_MIG_STATE)
if (attr->path_mig_state != IB_MIG_MIGRATED &&
attr->path_mig_state != IB_MIG_REARM)
goto inval;
if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
if (attr->max_dest_rd_atomic > IPATH_MAX_RDMA_ATOMIC)
goto inval;
switch (new_state) {
case IB_QPS_RESET:
if (qp->state != IB_QPS_RESET) {
qp->state = IB_QPS_RESET;
spin_lock(&dev->pending_lock);
if (!list_empty(&qp->timerwait))
list_del_init(&qp->timerwait);
if (!list_empty(&qp->piowait))
list_del_init(&qp->piowait);
spin_unlock(&dev->pending_lock);
qp->s_flags &= ~IPATH_S_ANY_WAIT;
spin_unlock_irq(&qp->s_lock);
/* Stop the sending tasklet */
tasklet_kill(&qp->s_task);
wait_event(qp->wait_dma, !atomic_read(&qp->s_dma_busy));
spin_lock_irq(&qp->s_lock);
}
ipath_reset_qp(qp, ibqp->qp_type);
break;
case IB_QPS_SQD:
qp->s_draining = qp->s_last != qp->s_cur;
qp->state = new_state;
break;
case IB_QPS_SQE:
if (qp->ibqp.qp_type == IB_QPT_RC)
goto inval;
qp->state = new_state;
break;
case IB_QPS_ERR:
lastwqe = ipath_error_qp(qp, IB_WC_WR_FLUSH_ERR);
break;
default:
qp->state = new_state;
break;
}
if (attr_mask & IB_QP_PKEY_INDEX)
qp->s_pkey_index = attr->pkey_index;
if (attr_mask & IB_QP_DEST_QPN)
qp->remote_qpn = attr->dest_qp_num;
if (attr_mask & IB_QP_SQ_PSN) {
qp->s_psn = qp->s_next_psn = attr->sq_psn;
qp->s_last_psn = qp->s_next_psn - 1;
}
if (attr_mask & IB_QP_RQ_PSN)
qp->r_psn = attr->rq_psn;
if (attr_mask & IB_QP_ACCESS_FLAGS)
qp->qp_access_flags = attr->qp_access_flags;
if (attr_mask & IB_QP_AV) {
qp->remote_ah_attr = attr->ah_attr;
qp->s_dmult = ipath_ib_rate_to_mult(attr->ah_attr.static_rate);
}
if (attr_mask & IB_QP_PATH_MTU)
qp->path_mtu = attr->path_mtu;
if (attr_mask & IB_QP_RETRY_CNT)
qp->s_retry = qp->s_retry_cnt = attr->retry_cnt;
if (attr_mask & IB_QP_RNR_RETRY) {
qp->s_rnr_retry = attr->rnr_retry;
if (qp->s_rnr_retry > 7)
qp->s_rnr_retry = 7;
qp->s_rnr_retry_cnt = qp->s_rnr_retry;
}
if (attr_mask & IB_QP_MIN_RNR_TIMER)
qp->r_min_rnr_timer = attr->min_rnr_timer;
if (attr_mask & IB_QP_TIMEOUT)
qp->timeout = attr->timeout;
if (attr_mask & IB_QP_QKEY)
qp->qkey = attr->qkey;
if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
qp->r_max_rd_atomic = attr->max_dest_rd_atomic;
if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC)
qp->s_max_rd_atomic = attr->max_rd_atomic;
spin_unlock_irq(&qp->s_lock);
if (lastwqe) {
struct ib_event ev;
ev.device = qp->ibqp.device;
ev.element.qp = &qp->ibqp;
ev.event = IB_EVENT_QP_LAST_WQE_REACHED;
qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
}
ret = 0;
goto bail;
inval:
spin_unlock_irq(&qp->s_lock);
ret = -EINVAL;
bail:
return ret;
}
int ipath_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
int attr_mask, struct ib_qp_init_attr *init_attr)
{
struct ipath_qp *qp = to_iqp(ibqp);
attr->qp_state = qp->state;
attr->cur_qp_state = attr->qp_state;
attr->path_mtu = qp->path_mtu;
attr->path_mig_state = 0;
attr->qkey = qp->qkey;
attr->rq_psn = qp->r_psn;
attr->sq_psn = qp->s_next_psn;
attr->dest_qp_num = qp->remote_qpn;
attr->qp_access_flags = qp->qp_access_flags;
attr->cap.max_send_wr = qp->s_size - 1;
attr->cap.max_recv_wr = qp->ibqp.srq ? 0 : qp->r_rq.size - 1;
attr->cap.max_send_sge = qp->s_max_sge;
attr->cap.max_recv_sge = qp->r_rq.max_sge;
attr->cap.max_inline_data = 0;
attr->ah_attr = qp->remote_ah_attr;
memset(&attr->alt_ah_attr, 0, sizeof(attr->alt_ah_attr));
attr->pkey_index = qp->s_pkey_index;
attr->alt_pkey_index = 0;
attr->en_sqd_async_notify = 0;
attr->sq_draining = qp->s_draining;
attr->max_rd_atomic = qp->s_max_rd_atomic;
attr->max_dest_rd_atomic = qp->r_max_rd_atomic;
attr->min_rnr_timer = qp->r_min_rnr_timer;
attr->port_num = 1;
attr->timeout = qp->timeout;
attr->retry_cnt = qp->s_retry_cnt;
attr->rnr_retry = qp->s_rnr_retry_cnt;
attr->alt_port_num = 0;
attr->alt_timeout = 0;
init_attr->event_handler = qp->ibqp.event_handler;
init_attr->qp_context = qp->ibqp.qp_context;
init_attr->send_cq = qp->ibqp.send_cq;
init_attr->recv_cq = qp->ibqp.recv_cq;
init_attr->srq = qp->ibqp.srq;
init_attr->cap = attr->cap;
if (qp->s_flags & IPATH_S_SIGNAL_REQ_WR)
init_attr->sq_sig_type = IB_SIGNAL_REQ_WR;
else
init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
init_attr->qp_type = qp->ibqp.qp_type;
init_attr->port_num = 1;
return 0;
}
/**
* ipath_compute_aeth - compute the AETH (syndrome + MSN)
* @qp: the queue pair to compute the AETH for
*
* Returns the AETH.
*/
__be32 ipath_compute_aeth(struct ipath_qp *qp)
{
u32 aeth = qp->r_msn & IPATH_MSN_MASK;
if (qp->ibqp.srq) {
/*
* Shared receive queues don't generate credits.
* Set the credit field to the invalid value.
*/
aeth |= IPATH_AETH_CREDIT_INVAL << IPATH_AETH_CREDIT_SHIFT;
} else {
u32 min, max, x;
u32 credits;
struct ipath_rwq *wq = qp->r_rq.wq;
u32 head;
u32 tail;
/* sanity check pointers before trusting them */
head = wq->head;
if (head >= qp->r_rq.size)
head = 0;
tail = wq->tail;
if (tail >= qp->r_rq.size)
tail = 0;
/*
* Compute the number of credits available (RWQEs).
* XXX Not holding the r_rq.lock here so there is a small
* chance that the pair of reads are not atomic.
*/
credits = head - tail;
if ((int)credits < 0)
credits += qp->r_rq.size;
/*
* Binary search the credit table to find the code to
* use.
*/
min = 0;
max = 31;
for (;;) {
x = (min + max) / 2;
if (credit_table[x] == credits)
break;
if (credit_table[x] > credits)
max = x;
else if (min == x)
break;
else
min = x;
}
aeth |= x << IPATH_AETH_CREDIT_SHIFT;
}
return cpu_to_be32(aeth);
}
/**
* ipath_create_qp - create a queue pair for a device
* @ibpd: the protection domain who's device we create the queue pair for
* @init_attr: the attributes of the queue pair
* @udata: unused by InfiniPath
*
* Returns the queue pair on success, otherwise returns an errno.
*
* Called by the ib_create_qp() core verbs function.
*/
struct ib_qp *ipath_create_qp(struct ib_pd *ibpd,
struct ib_qp_init_attr *init_attr,
struct ib_udata *udata)
{
struct ipath_qp *qp;
int err;
struct ipath_swqe *swq = NULL;
struct ipath_ibdev *dev;
size_t sz;
size_t sg_list_sz;
struct ib_qp *ret;
if (init_attr->create_flags) {
ret = ERR_PTR(-EINVAL);
goto bail;
}
if (init_attr->cap.max_send_sge > ib_ipath_max_sges ||
init_attr->cap.max_send_wr > ib_ipath_max_qp_wrs) {
ret = ERR_PTR(-EINVAL);
goto bail;
}
/* Check receive queue parameters if no SRQ is specified. */
if (!init_attr->srq) {
if (init_attr->cap.max_recv_sge > ib_ipath_max_sges ||
init_attr->cap.max_recv_wr > ib_ipath_max_qp_wrs) {
ret = ERR_PTR(-EINVAL);
goto bail;
}
if (init_attr->cap.max_send_sge +
init_attr->cap.max_send_wr +
init_attr->cap.max_recv_sge +
init_attr->cap.max_recv_wr == 0) {
ret = ERR_PTR(-EINVAL);
goto bail;
}
}
switch (init_attr->qp_type) {
case IB_QPT_UC:
case IB_QPT_RC:
case IB_QPT_UD:
case IB_QPT_SMI:
case IB_QPT_GSI:
sz = sizeof(struct ipath_sge) *
init_attr->cap.max_send_sge +
sizeof(struct ipath_swqe);
swq = vmalloc((init_attr->cap.max_send_wr + 1) * sz);
if (swq == NULL) {
ret = ERR_PTR(-ENOMEM);
goto bail;
}
sz = sizeof(*qp);
sg_list_sz = 0;
if (init_attr->srq) {
struct ipath_srq *srq = to_isrq(init_attr->srq);
if (srq->rq.max_sge > 1)
sg_list_sz = sizeof(*qp->r_sg_list) *
(srq->rq.max_sge - 1);
} else if (init_attr->cap.max_recv_sge > 1)
sg_list_sz = sizeof(*qp->r_sg_list) *
(init_attr->cap.max_recv_sge - 1);
qp = kmalloc(sz + sg_list_sz, GFP_KERNEL);
if (!qp) {
ret = ERR_PTR(-ENOMEM);
goto bail_swq;
}
if (sg_list_sz && (init_attr->qp_type == IB_QPT_UD ||
init_attr->qp_type == IB_QPT_SMI ||
init_attr->qp_type == IB_QPT_GSI)) {
qp->r_ud_sg_list = kmalloc(sg_list_sz, GFP_KERNEL);
if (!qp->r_ud_sg_list) {
ret = ERR_PTR(-ENOMEM);
goto bail_qp;
}
} else
qp->r_ud_sg_list = NULL;
if (init_attr->srq) {
sz = 0;
qp->r_rq.size = 0;
qp->r_rq.max_sge = 0;
qp->r_rq.wq = NULL;
init_attr->cap.max_recv_wr = 0;
init_attr->cap.max_recv_sge = 0;
} else {
qp->r_rq.size = init_attr->cap.max_recv_wr + 1;
qp->r_rq.max_sge = init_attr->cap.max_recv_sge;
sz = (sizeof(struct ib_sge) * qp->r_rq.max_sge) +
sizeof(struct ipath_rwqe);
qp->r_rq.wq = vmalloc_user(sizeof(struct ipath_rwq) +
qp->r_rq.size * sz);
if (!qp->r_rq.wq) {
ret = ERR_PTR(-ENOMEM);
goto bail_sg_list;
}
}
/*
* ib_create_qp() will initialize qp->ibqp
* except for qp->ibqp.qp_num.
*/
spin_lock_init(&qp->s_lock);
spin_lock_init(&qp->r_rq.lock);
atomic_set(&qp->refcount, 0);
init_waitqueue_head(&qp->wait);
init_waitqueue_head(&qp->wait_dma);
tasklet_init(&qp->s_task, ipath_do_send, (unsigned long)qp);
INIT_LIST_HEAD(&qp->piowait);
INIT_LIST_HEAD(&qp->timerwait);
qp->state = IB_QPS_RESET;
qp->s_wq = swq;
qp->s_size = init_attr->cap.max_send_wr + 1;
qp->s_max_sge = init_attr->cap.max_send_sge;
if (init_attr->sq_sig_type == IB_SIGNAL_REQ_WR)
qp->s_flags = IPATH_S_SIGNAL_REQ_WR;
else
qp->s_flags = 0;
dev = to_idev(ibpd->device);
err = ipath_alloc_qpn(&dev->qp_table, qp,
init_attr->qp_type);
if (err) {
ret = ERR_PTR(err);
vfree(qp->r_rq.wq);
goto bail_sg_list;
}
qp->ip = NULL;
qp->s_tx = NULL;
ipath_reset_qp(qp, init_attr->qp_type);
break;
default:
/* Don't support raw QPs */
ret = ERR_PTR(-ENOSYS);
goto bail;
}
init_attr->cap.max_inline_data = 0;
/*
* Return the address of the RWQ as the offset to mmap.
* See ipath_mmap() for details.
*/
if (udata && udata->outlen >= sizeof(__u64)) {
if (!qp->r_rq.wq) {
__u64 offset = 0;
err = ib_copy_to_udata(udata, &offset,
sizeof(offset));
if (err) {
ret = ERR_PTR(err);
goto bail_ip;
}
} else {
u32 s = sizeof(struct ipath_rwq) +
qp->r_rq.size * sz;
qp->ip =
ipath_create_mmap_info(dev, s,
ibpd->uobject->context,
qp->r_rq.wq);
if (!qp->ip) {
ret = ERR_PTR(-ENOMEM);
goto bail_ip;
}
err = ib_copy_to_udata(udata, &(qp->ip->offset),
sizeof(qp->ip->offset));
if (err) {
ret = ERR_PTR(err);
goto bail_ip;
}
}
}
spin_lock(&dev->n_qps_lock);
if (dev->n_qps_allocated == ib_ipath_max_qps) {
spin_unlock(&dev->n_qps_lock);
ret = ERR_PTR(-ENOMEM);
goto bail_ip;
}
dev->n_qps_allocated++;
spin_unlock(&dev->n_qps_lock);
if (qp->ip) {
spin_lock_irq(&dev->pending_lock);
list_add(&qp->ip->pending_mmaps, &dev->pending_mmaps);
spin_unlock_irq(&dev->pending_lock);
}
ret = &qp->ibqp;
goto bail;
bail_ip:
if (qp->ip)
kref_put(&qp->ip->ref, ipath_release_mmap_info);
else
vfree(qp->r_rq.wq);
ipath_free_qp(&dev->qp_table, qp);
free_qpn(&dev->qp_table, qp->ibqp.qp_num);
bail_sg_list:
kfree(qp->r_ud_sg_list);
bail_qp:
kfree(qp);
bail_swq:
vfree(swq);
bail:
return ret;
}
/**
* ipath_destroy_qp - destroy a queue pair
* @ibqp: the queue pair to destroy
*
* Returns 0 on success.
*
* Note that this can be called while the QP is actively sending or
* receiving!
*/
int ipath_destroy_qp(struct ib_qp *ibqp)
{
struct ipath_qp *qp = to_iqp(ibqp);
struct ipath_ibdev *dev = to_idev(ibqp->device);
/* Make sure HW and driver activity is stopped. */
spin_lock_irq(&qp->s_lock);
if (qp->state != IB_QPS_RESET) {
qp->state = IB_QPS_RESET;
spin_lock(&dev->pending_lock);
if (!list_empty(&qp->timerwait))
list_del_init(&qp->timerwait);
if (!list_empty(&qp->piowait))
list_del_init(&qp->piowait);
spin_unlock(&dev->pending_lock);
qp->s_flags &= ~IPATH_S_ANY_WAIT;
spin_unlock_irq(&qp->s_lock);
/* Stop the sending tasklet */
tasklet_kill(&qp->s_task);
wait_event(qp->wait_dma, !atomic_read(&qp->s_dma_busy));
} else
spin_unlock_irq(&qp->s_lock);
ipath_free_qp(&dev->qp_table, qp);
if (qp->s_tx) {
atomic_dec(&qp->refcount);
if (qp->s_tx->txreq.flags & IPATH_SDMA_TXREQ_F_FREEBUF)
kfree(qp->s_tx->txreq.map_addr);
spin_lock_irq(&dev->pending_lock);
list_add(&qp->s_tx->txreq.list, &dev->txreq_free);
spin_unlock_irq(&dev->pending_lock);
qp->s_tx = NULL;
}
wait_event(qp->wait, !atomic_read(&qp->refcount));
/* all user's cleaned up, mark it available */
free_qpn(&dev->qp_table, qp->ibqp.qp_num);
spin_lock(&dev->n_qps_lock);
dev->n_qps_allocated--;
spin_unlock(&dev->n_qps_lock);
if (qp->ip)
kref_put(&qp->ip->ref, ipath_release_mmap_info);
else
vfree(qp->r_rq.wq);
kfree(qp->r_ud_sg_list);
vfree(qp->s_wq);
kfree(qp);
return 0;
}
/**
* ipath_init_qp_table - initialize the QP table for a device
* @idev: the device who's QP table we're initializing
* @size: the size of the QP table
*
* Returns 0 on success, otherwise returns an errno.
*/
int ipath_init_qp_table(struct ipath_ibdev *idev, int size)
{
int i;
int ret;
idev->qp_table.last = 1; /* QPN 0 and 1 are special. */
idev->qp_table.max = size;
idev->qp_table.nmaps = 1;
idev->qp_table.table = kzalloc(size * sizeof(*idev->qp_table.table),
GFP_KERNEL);
if (idev->qp_table.table == NULL) {
ret = -ENOMEM;
goto bail;
}
for (i = 0; i < ARRAY_SIZE(idev->qp_table.map); i++) {
atomic_set(&idev->qp_table.map[i].n_free, BITS_PER_PAGE);
idev->qp_table.map[i].page = NULL;
}
ret = 0;
bail:
return ret;
}
/**
* ipath_get_credit - flush the send work queue of a QP
* @qp: the qp who's send work queue to flush
* @aeth: the Acknowledge Extended Transport Header
*
* The QP s_lock should be held.
*/
void ipath_get_credit(struct ipath_qp *qp, u32 aeth)
{
u32 credit = (aeth >> IPATH_AETH_CREDIT_SHIFT) & IPATH_AETH_CREDIT_MASK;
/*
* If the credit is invalid, we can send
* as many packets as we like. Otherwise, we have to
* honor the credit field.
*/
if (credit == IPATH_AETH_CREDIT_INVAL)
qp->s_lsn = (u32) -1;
else if (qp->s_lsn != (u32) -1) {
/* Compute new LSN (i.e., MSN + credit) */
credit = (aeth + credit_table[credit]) & IPATH_MSN_MASK;
if (ipath_cmp24(credit, qp->s_lsn) > 0)
qp->s_lsn = credit;
}
/* Restart sending if it was blocked due to lack of credits. */
if ((qp->s_flags & IPATH_S_WAIT_SSN_CREDIT) &&
qp->s_cur != qp->s_head &&
(qp->s_lsn == (u32) -1 ||
ipath_cmp24(get_swqe_ptr(qp, qp->s_cur)->ssn,
qp->s_lsn + 1) <= 0))
ipath_schedule_send(qp);
}
| gpl-2.0 |
eskyuu/linux | drivers/video/backlight/lm3533_bl.c | 1875 | 8892 | /*
* lm3533-bl.c -- LM3533 Backlight driver
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <jhovold@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/backlight.h>
#include <linux/fb.h>
#include <linux/slab.h>
#include <linux/mfd/lm3533.h>
#define LM3533_HVCTRLBANK_COUNT 2
#define LM3533_BL_MAX_BRIGHTNESS 255
#define LM3533_REG_CTRLBANK_AB_BCONF 0x1a
struct lm3533_bl {
struct lm3533 *lm3533;
struct lm3533_ctrlbank cb;
struct backlight_device *bd;
int id;
};
static inline int lm3533_bl_get_ctrlbank_id(struct lm3533_bl *bl)
{
return bl->id;
}
static int lm3533_bl_update_status(struct backlight_device *bd)
{
struct lm3533_bl *bl = bl_get_data(bd);
int brightness = bd->props.brightness;
if (bd->props.power != FB_BLANK_UNBLANK)
brightness = 0;
if (bd->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
return lm3533_ctrlbank_set_brightness(&bl->cb, (u8)brightness);
}
static int lm3533_bl_get_brightness(struct backlight_device *bd)
{
struct lm3533_bl *bl = bl_get_data(bd);
u8 val;
int ret;
ret = lm3533_ctrlbank_get_brightness(&bl->cb, &val);
if (ret)
return ret;
return val;
}
static const struct backlight_ops lm3533_bl_ops = {
.get_brightness = lm3533_bl_get_brightness,
.update_status = lm3533_bl_update_status,
};
static ssize_t show_id(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
return scnprintf(buf, PAGE_SIZE, "%d\n", bl->id);
}
static ssize_t show_als_channel(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
unsigned channel = lm3533_bl_get_ctrlbank_id(bl);
return scnprintf(buf, PAGE_SIZE, "%u\n", channel);
}
static ssize_t show_als_en(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
int ctrlbank = lm3533_bl_get_ctrlbank_id(bl);
u8 val;
u8 mask;
bool enable;
int ret;
ret = lm3533_read(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, &val);
if (ret)
return ret;
mask = 1 << (2 * ctrlbank);
enable = val & mask;
return scnprintf(buf, PAGE_SIZE, "%d\n", enable);
}
static ssize_t store_als_en(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
int ctrlbank = lm3533_bl_get_ctrlbank_id(bl);
int enable;
u8 val;
u8 mask;
int ret;
if (kstrtoint(buf, 0, &enable))
return -EINVAL;
mask = 1 << (2 * ctrlbank);
if (enable)
val = mask;
else
val = 0;
ret = lm3533_update(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, val,
mask);
if (ret)
return ret;
return len;
}
static ssize_t show_linear(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
u8 val;
u8 mask;
int linear;
int ret;
ret = lm3533_read(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, &val);
if (ret)
return ret;
mask = 1 << (2 * lm3533_bl_get_ctrlbank_id(bl) + 1);
if (val & mask)
linear = 1;
else
linear = 0;
return scnprintf(buf, PAGE_SIZE, "%x\n", linear);
}
static ssize_t store_linear(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
unsigned long linear;
u8 mask;
u8 val;
int ret;
if (kstrtoul(buf, 0, &linear))
return -EINVAL;
mask = 1 << (2 * lm3533_bl_get_ctrlbank_id(bl) + 1);
if (linear)
val = mask;
else
val = 0;
ret = lm3533_update(bl->lm3533, LM3533_REG_CTRLBANK_AB_BCONF, val,
mask);
if (ret)
return ret;
return len;
}
static ssize_t show_pwm(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
u8 val;
int ret;
ret = lm3533_ctrlbank_get_pwm(&bl->cb, &val);
if (ret)
return ret;
return scnprintf(buf, PAGE_SIZE, "%u\n", val);
}
static ssize_t store_pwm(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
u8 val;
int ret;
if (kstrtou8(buf, 0, &val))
return -EINVAL;
ret = lm3533_ctrlbank_set_pwm(&bl->cb, val);
if (ret)
return ret;
return len;
}
static LM3533_ATTR_RO(als_channel);
static LM3533_ATTR_RW(als_en);
static LM3533_ATTR_RO(id);
static LM3533_ATTR_RW(linear);
static LM3533_ATTR_RW(pwm);
static struct attribute *lm3533_bl_attributes[] = {
&dev_attr_als_channel.attr,
&dev_attr_als_en.attr,
&dev_attr_id.attr,
&dev_attr_linear.attr,
&dev_attr_pwm.attr,
NULL,
};
static umode_t lm3533_bl_attr_is_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct lm3533_bl *bl = dev_get_drvdata(dev);
umode_t mode = attr->mode;
if (attr == &dev_attr_als_channel.attr ||
attr == &dev_attr_als_en.attr) {
if (!bl->lm3533->have_als)
mode = 0;
}
return mode;
};
static struct attribute_group lm3533_bl_attribute_group = {
.is_visible = lm3533_bl_attr_is_visible,
.attrs = lm3533_bl_attributes
};
static int lm3533_bl_setup(struct lm3533_bl *bl,
struct lm3533_bl_platform_data *pdata)
{
int ret;
ret = lm3533_ctrlbank_set_max_current(&bl->cb, pdata->max_current);
if (ret)
return ret;
return lm3533_ctrlbank_set_pwm(&bl->cb, pdata->pwm);
}
static int lm3533_bl_probe(struct platform_device *pdev)
{
struct lm3533 *lm3533;
struct lm3533_bl_platform_data *pdata;
struct lm3533_bl *bl;
struct backlight_device *bd;
struct backlight_properties props;
int ret;
dev_dbg(&pdev->dev, "%s\n", __func__);
lm3533 = dev_get_drvdata(pdev->dev.parent);
if (!lm3533)
return -EINVAL;
pdata = dev_get_platdata(&pdev->dev);
if (!pdata) {
dev_err(&pdev->dev, "no platform data\n");
return -EINVAL;
}
if (pdev->id < 0 || pdev->id >= LM3533_HVCTRLBANK_COUNT) {
dev_err(&pdev->dev, "illegal backlight id %d\n", pdev->id);
return -EINVAL;
}
bl = devm_kzalloc(&pdev->dev, sizeof(*bl), GFP_KERNEL);
if (!bl)
return -ENOMEM;
bl->lm3533 = lm3533;
bl->id = pdev->id;
bl->cb.lm3533 = lm3533;
bl->cb.id = lm3533_bl_get_ctrlbank_id(bl);
bl->cb.dev = NULL; /* until registered */
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = LM3533_BL_MAX_BRIGHTNESS;
props.brightness = pdata->default_brightness;
bd = devm_backlight_device_register(&pdev->dev, pdata->name,
pdev->dev.parent, bl, &lm3533_bl_ops,
&props);
if (IS_ERR(bd)) {
dev_err(&pdev->dev, "failed to register backlight device\n");
return PTR_ERR(bd);
}
bl->bd = bd;
bl->cb.dev = &bl->bd->dev;
platform_set_drvdata(pdev, bl);
ret = sysfs_create_group(&bd->dev.kobj, &lm3533_bl_attribute_group);
if (ret < 0) {
dev_err(&pdev->dev, "failed to create sysfs attributes\n");
return ret;
}
backlight_update_status(bd);
ret = lm3533_bl_setup(bl, pdata);
if (ret)
goto err_sysfs_remove;
ret = lm3533_ctrlbank_enable(&bl->cb);
if (ret)
goto err_sysfs_remove;
return 0;
err_sysfs_remove:
sysfs_remove_group(&bd->dev.kobj, &lm3533_bl_attribute_group);
return ret;
}
static int lm3533_bl_remove(struct platform_device *pdev)
{
struct lm3533_bl *bl = platform_get_drvdata(pdev);
struct backlight_device *bd = bl->bd;
dev_dbg(&bd->dev, "%s\n", __func__);
bd->props.power = FB_BLANK_POWERDOWN;
bd->props.brightness = 0;
lm3533_ctrlbank_disable(&bl->cb);
sysfs_remove_group(&bd->dev.kobj, &lm3533_bl_attribute_group);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int lm3533_bl_suspend(struct device *dev)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
return lm3533_ctrlbank_disable(&bl->cb);
}
static int lm3533_bl_resume(struct device *dev)
{
struct lm3533_bl *bl = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
return lm3533_ctrlbank_enable(&bl->cb);
}
#endif
static SIMPLE_DEV_PM_OPS(lm3533_bl_pm_ops, lm3533_bl_suspend, lm3533_bl_resume);
static void lm3533_bl_shutdown(struct platform_device *pdev)
{
struct lm3533_bl *bl = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "%s\n", __func__);
lm3533_ctrlbank_disable(&bl->cb);
}
static struct platform_driver lm3533_bl_driver = {
.driver = {
.name = "lm3533-backlight",
.pm = &lm3533_bl_pm_ops,
},
.probe = lm3533_bl_probe,
.remove = lm3533_bl_remove,
.shutdown = lm3533_bl_shutdown,
};
module_platform_driver(lm3533_bl_driver);
MODULE_AUTHOR("Johan Hovold <jhovold@gmail.com>");
MODULE_DESCRIPTION("LM3533 Backlight driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lm3533-backlight");
| gpl-2.0 |
dhruvvyas90/linux | fs/proc/interrupts.c | 2131 | 1092 | #include <linux/fs.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irqnr.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
/*
* /proc/interrupts
*/
static void *int_seq_start(struct seq_file *f, loff_t *pos)
{
return (*pos <= nr_irqs) ? pos : NULL;
}
static void *int_seq_next(struct seq_file *f, void *v, loff_t *pos)
{
(*pos)++;
if (*pos > nr_irqs)
return NULL;
return pos;
}
static void int_seq_stop(struct seq_file *f, void *v)
{
/* Nothing to do */
}
static const struct seq_operations int_seq_ops = {
.start = int_seq_start,
.next = int_seq_next,
.stop = int_seq_stop,
.show = show_interrupts
};
static int interrupts_open(struct inode *inode, struct file *filp)
{
return seq_open(filp, &int_seq_ops);
}
static const struct file_operations proc_interrupts_operations = {
.open = interrupts_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int __init proc_interrupts_init(void)
{
proc_create("interrupts", 0, NULL, &proc_interrupts_operations);
return 0;
}
fs_initcall(proc_interrupts_init);
| gpl-2.0 |
Pafcholini/emotion_kernel_note4_mm | fs/gfs2/main.c | 2387 | 5645 | /*
* Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved.
* Copyright (C) 2004-2006 Red Hat, Inc. All rights reserved.
*
* This copyrighted material is made available to anyone wishing to use,
* modify, copy, or redistribute it subject to the terms and conditions
* of the GNU General Public License version 2.
*/
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/buffer_head.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/gfs2_ondisk.h>
#include <linux/rcupdate.h>
#include <linux/rculist_bl.h>
#include <linux/atomic.h>
#include <linux/mempool.h>
#include "gfs2.h"
#include "incore.h"
#include "super.h"
#include "sys.h"
#include "util.h"
#include "glock.h"
#include "quota.h"
#include "recovery.h"
#include "dir.h"
struct workqueue_struct *gfs2_control_wq;
static struct shrinker qd_shrinker = {
.shrink = gfs2_shrink_qd_memory,
.seeks = DEFAULT_SEEKS,
};
static void gfs2_init_inode_once(void *foo)
{
struct gfs2_inode *ip = foo;
inode_init_once(&ip->i_inode);
init_rwsem(&ip->i_rw_mutex);
INIT_LIST_HEAD(&ip->i_trunc_list);
ip->i_res = NULL;
ip->i_hash_cache = NULL;
}
static void gfs2_init_glock_once(void *foo)
{
struct gfs2_glock *gl = foo;
INIT_HLIST_BL_NODE(&gl->gl_list);
spin_lock_init(&gl->gl_spin);
INIT_LIST_HEAD(&gl->gl_holders);
INIT_LIST_HEAD(&gl->gl_lru);
INIT_LIST_HEAD(&gl->gl_ail_list);
atomic_set(&gl->gl_ail_count, 0);
atomic_set(&gl->gl_revokes, 0);
}
static void gfs2_init_gl_aspace_once(void *foo)
{
struct gfs2_glock *gl = foo;
struct address_space *mapping = (struct address_space *)(gl + 1);
gfs2_init_glock_once(gl);
address_space_init_once(mapping);
}
/**
* init_gfs2_fs - Register GFS2 as a filesystem
*
* Returns: 0 on success, error code on failure
*/
static int __init init_gfs2_fs(void)
{
int error;
gfs2_str2qstr(&gfs2_qdot, ".");
gfs2_str2qstr(&gfs2_qdotdot, "..");
error = gfs2_sys_init();
if (error)
return error;
error = gfs2_glock_init();
if (error)
goto fail;
error = -ENOMEM;
gfs2_glock_cachep = kmem_cache_create("gfs2_glock",
sizeof(struct gfs2_glock),
0, 0,
gfs2_init_glock_once);
if (!gfs2_glock_cachep)
goto fail;
gfs2_glock_aspace_cachep = kmem_cache_create("gfs2_glock(aspace)",
sizeof(struct gfs2_glock) +
sizeof(struct address_space),
0, 0, gfs2_init_gl_aspace_once);
if (!gfs2_glock_aspace_cachep)
goto fail;
gfs2_inode_cachep = kmem_cache_create("gfs2_inode",
sizeof(struct gfs2_inode),
0, SLAB_RECLAIM_ACCOUNT|
SLAB_MEM_SPREAD,
gfs2_init_inode_once);
if (!gfs2_inode_cachep)
goto fail;
gfs2_bufdata_cachep = kmem_cache_create("gfs2_bufdata",
sizeof(struct gfs2_bufdata),
0, 0, NULL);
if (!gfs2_bufdata_cachep)
goto fail;
gfs2_rgrpd_cachep = kmem_cache_create("gfs2_rgrpd",
sizeof(struct gfs2_rgrpd),
0, 0, NULL);
if (!gfs2_rgrpd_cachep)
goto fail;
gfs2_quotad_cachep = kmem_cache_create("gfs2_quotad",
sizeof(struct gfs2_quota_data),
0, 0, NULL);
if (!gfs2_quotad_cachep)
goto fail;
gfs2_rsrv_cachep = kmem_cache_create("gfs2_mblk",
sizeof(struct gfs2_blkreserv),
0, 0, NULL);
if (!gfs2_rsrv_cachep)
goto fail;
register_shrinker(&qd_shrinker);
error = register_filesystem(&gfs2_fs_type);
if (error)
goto fail;
error = register_filesystem(&gfs2meta_fs_type);
if (error)
goto fail_unregister;
error = -ENOMEM;
gfs_recovery_wq = alloc_workqueue("gfs_recovery",
WQ_MEM_RECLAIM | WQ_FREEZABLE, 0);
if (!gfs_recovery_wq)
goto fail_wq;
gfs2_control_wq = alloc_workqueue("gfs2_control",
WQ_NON_REENTRANT | WQ_UNBOUND | WQ_FREEZABLE, 0);
if (!gfs2_control_wq)
goto fail_recovery;
gfs2_page_pool = mempool_create_page_pool(64, 0);
if (!gfs2_page_pool)
goto fail_control;
gfs2_register_debugfs();
printk("GFS2 installed\n");
return 0;
fail_control:
destroy_workqueue(gfs2_control_wq);
fail_recovery:
destroy_workqueue(gfs_recovery_wq);
fail_wq:
unregister_filesystem(&gfs2meta_fs_type);
fail_unregister:
unregister_filesystem(&gfs2_fs_type);
fail:
unregister_shrinker(&qd_shrinker);
gfs2_glock_exit();
if (gfs2_rsrv_cachep)
kmem_cache_destroy(gfs2_rsrv_cachep);
if (gfs2_quotad_cachep)
kmem_cache_destroy(gfs2_quotad_cachep);
if (gfs2_rgrpd_cachep)
kmem_cache_destroy(gfs2_rgrpd_cachep);
if (gfs2_bufdata_cachep)
kmem_cache_destroy(gfs2_bufdata_cachep);
if (gfs2_inode_cachep)
kmem_cache_destroy(gfs2_inode_cachep);
if (gfs2_glock_aspace_cachep)
kmem_cache_destroy(gfs2_glock_aspace_cachep);
if (gfs2_glock_cachep)
kmem_cache_destroy(gfs2_glock_cachep);
gfs2_sys_uninit();
return error;
}
/**
* exit_gfs2_fs - Unregister the file system
*
*/
static void __exit exit_gfs2_fs(void)
{
unregister_shrinker(&qd_shrinker);
gfs2_glock_exit();
gfs2_unregister_debugfs();
unregister_filesystem(&gfs2_fs_type);
unregister_filesystem(&gfs2meta_fs_type);
destroy_workqueue(gfs_recovery_wq);
destroy_workqueue(gfs2_control_wq);
rcu_barrier();
mempool_destroy(gfs2_page_pool);
kmem_cache_destroy(gfs2_rsrv_cachep);
kmem_cache_destroy(gfs2_quotad_cachep);
kmem_cache_destroy(gfs2_rgrpd_cachep);
kmem_cache_destroy(gfs2_bufdata_cachep);
kmem_cache_destroy(gfs2_inode_cachep);
kmem_cache_destroy(gfs2_glock_aspace_cachep);
kmem_cache_destroy(gfs2_glock_cachep);
gfs2_sys_uninit();
}
MODULE_DESCRIPTION("Global File System");
MODULE_AUTHOR("Red Hat, Inc.");
MODULE_LICENSE("GPL");
module_init(init_gfs2_fs);
module_exit(exit_gfs2_fs);
| gpl-2.0 |
MoKee/android_kernel_samsung_smdk4412 | drivers/scsi/bfa/bfa_fcpim.c | 2643 | 77797 | /*
* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
* All rights reserved
* www.brocade.com
*
* Linux driver for Brocade Fibre Channel Host Bus Adapter.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License (GPL) Version 2 as
* published by the Free Software Foundation
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include "bfad_drv.h"
#include "bfa_modules.h"
BFA_TRC_FILE(HAL, FCPIM);
BFA_MODULE(fcpim);
/*
* BFA ITNIM Related definitions
*/
static void bfa_itnim_update_del_itn_stats(struct bfa_itnim_s *itnim);
#define BFA_ITNIM_FROM_TAG(_fcpim, _tag) \
(((_fcpim)->itnim_arr + ((_tag) & ((_fcpim)->num_itnims - 1))))
#define bfa_fcpim_additn(__itnim) \
list_add_tail(&(__itnim)->qe, &(__itnim)->fcpim->itnim_q)
#define bfa_fcpim_delitn(__itnim) do { \
WARN_ON(!bfa_q_is_on_q(&(__itnim)->fcpim->itnim_q, __itnim)); \
bfa_itnim_update_del_itn_stats(__itnim); \
list_del(&(__itnim)->qe); \
WARN_ON(!list_empty(&(__itnim)->io_q)); \
WARN_ON(!list_empty(&(__itnim)->io_cleanup_q)); \
WARN_ON(!list_empty(&(__itnim)->pending_q)); \
} while (0)
#define bfa_itnim_online_cb(__itnim) do { \
if ((__itnim)->bfa->fcs) \
bfa_cb_itnim_online((__itnim)->ditn); \
else { \
bfa_cb_queue((__itnim)->bfa, &(__itnim)->hcb_qe, \
__bfa_cb_itnim_online, (__itnim)); \
} \
} while (0)
#define bfa_itnim_offline_cb(__itnim) do { \
if ((__itnim)->bfa->fcs) \
bfa_cb_itnim_offline((__itnim)->ditn); \
else { \
bfa_cb_queue((__itnim)->bfa, &(__itnim)->hcb_qe, \
__bfa_cb_itnim_offline, (__itnim)); \
} \
} while (0)
#define bfa_itnim_sler_cb(__itnim) do { \
if ((__itnim)->bfa->fcs) \
bfa_cb_itnim_sler((__itnim)->ditn); \
else { \
bfa_cb_queue((__itnim)->bfa, &(__itnim)->hcb_qe, \
__bfa_cb_itnim_sler, (__itnim)); \
} \
} while (0)
/*
* itnim state machine event
*/
enum bfa_itnim_event {
BFA_ITNIM_SM_CREATE = 1, /* itnim is created */
BFA_ITNIM_SM_ONLINE = 2, /* itnim is online */
BFA_ITNIM_SM_OFFLINE = 3, /* itnim is offline */
BFA_ITNIM_SM_FWRSP = 4, /* firmware response */
BFA_ITNIM_SM_DELETE = 5, /* deleting an existing itnim */
BFA_ITNIM_SM_CLEANUP = 6, /* IO cleanup completion */
BFA_ITNIM_SM_SLER = 7, /* second level error recovery */
BFA_ITNIM_SM_HWFAIL = 8, /* IOC h/w failure event */
BFA_ITNIM_SM_QRESUME = 9, /* queue space available */
};
/*
* BFA IOIM related definitions
*/
#define bfa_ioim_move_to_comp_q(__ioim) do { \
list_del(&(__ioim)->qe); \
list_add_tail(&(__ioim)->qe, &(__ioim)->fcpim->ioim_comp_q); \
} while (0)
#define bfa_ioim_cb_profile_comp(__fcpim, __ioim) do { \
if ((__fcpim)->profile_comp) \
(__fcpim)->profile_comp(__ioim); \
} while (0)
#define bfa_ioim_cb_profile_start(__fcpim, __ioim) do { \
if ((__fcpim)->profile_start) \
(__fcpim)->profile_start(__ioim); \
} while (0)
/*
* IO state machine events
*/
enum bfa_ioim_event {
BFA_IOIM_SM_START = 1, /* io start request from host */
BFA_IOIM_SM_COMP_GOOD = 2, /* io good comp, resource free */
BFA_IOIM_SM_COMP = 3, /* io comp, resource is free */
BFA_IOIM_SM_COMP_UTAG = 4, /* io comp, resource is free */
BFA_IOIM_SM_DONE = 5, /* io comp, resource not free */
BFA_IOIM_SM_FREE = 6, /* io resource is freed */
BFA_IOIM_SM_ABORT = 7, /* abort request from scsi stack */
BFA_IOIM_SM_ABORT_COMP = 8, /* abort from f/w */
BFA_IOIM_SM_ABORT_DONE = 9, /* abort completion from f/w */
BFA_IOIM_SM_QRESUME = 10, /* CQ space available to queue IO */
BFA_IOIM_SM_SGALLOCED = 11, /* SG page allocation successful */
BFA_IOIM_SM_SQRETRY = 12, /* sequence recovery retry */
BFA_IOIM_SM_HCB = 13, /* bfa callback complete */
BFA_IOIM_SM_CLEANUP = 14, /* IO cleanup from itnim */
BFA_IOIM_SM_TMSTART = 15, /* IO cleanup from tskim */
BFA_IOIM_SM_TMDONE = 16, /* IO cleanup from tskim */
BFA_IOIM_SM_HWFAIL = 17, /* IOC h/w failure event */
BFA_IOIM_SM_IOTOV = 18, /* ITN offline TOV */
};
/*
* BFA TSKIM related definitions
*/
/*
* task management completion handling
*/
#define bfa_tskim_qcomp(__tskim, __cbfn) do { \
bfa_cb_queue((__tskim)->bfa, &(__tskim)->hcb_qe, __cbfn, (__tskim));\
bfa_tskim_notify_comp(__tskim); \
} while (0)
#define bfa_tskim_notify_comp(__tskim) do { \
if ((__tskim)->notify) \
bfa_itnim_tskdone((__tskim)->itnim); \
} while (0)
enum bfa_tskim_event {
BFA_TSKIM_SM_START = 1, /* TM command start */
BFA_TSKIM_SM_DONE = 2, /* TM completion */
BFA_TSKIM_SM_QRESUME = 3, /* resume after qfull */
BFA_TSKIM_SM_HWFAIL = 5, /* IOC h/w failure event */
BFA_TSKIM_SM_HCB = 6, /* BFA callback completion */
BFA_TSKIM_SM_IOS_DONE = 7, /* IO and sub TM completions */
BFA_TSKIM_SM_CLEANUP = 8, /* TM cleanup on ITN offline */
BFA_TSKIM_SM_CLEANUP_DONE = 9, /* TM abort completion */
};
/*
* forward declaration for BFA ITNIM functions
*/
static void bfa_itnim_iocdisable_cleanup(struct bfa_itnim_s *itnim);
static bfa_boolean_t bfa_itnim_send_fwcreate(struct bfa_itnim_s *itnim);
static bfa_boolean_t bfa_itnim_send_fwdelete(struct bfa_itnim_s *itnim);
static void bfa_itnim_cleanp_comp(void *itnim_cbarg);
static void bfa_itnim_cleanup(struct bfa_itnim_s *itnim);
static void __bfa_cb_itnim_online(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_itnim_offline(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_itnim_sler(void *cbarg, bfa_boolean_t complete);
static void bfa_itnim_iotov_online(struct bfa_itnim_s *itnim);
static void bfa_itnim_iotov_cleanup(struct bfa_itnim_s *itnim);
static void bfa_itnim_iotov(void *itnim_arg);
static void bfa_itnim_iotov_start(struct bfa_itnim_s *itnim);
static void bfa_itnim_iotov_stop(struct bfa_itnim_s *itnim);
static void bfa_itnim_iotov_delete(struct bfa_itnim_s *itnim);
/*
* forward declaration of ITNIM state machine
*/
static void bfa_itnim_sm_uninit(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_created(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_fwcreate(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_delete_pending(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_online(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_sler(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_cleanup_offline(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_cleanup_delete(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_fwdelete(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_offline(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_iocdisable(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_deleting(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_fwcreate_qfull(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_fwdelete_qfull(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
static void bfa_itnim_sm_deleting_qfull(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event);
/*
* forward declaration for BFA IOIM functions
*/
static bfa_boolean_t bfa_ioim_send_ioreq(struct bfa_ioim_s *ioim);
static bfa_boolean_t bfa_ioim_sgpg_alloc(struct bfa_ioim_s *ioim);
static bfa_boolean_t bfa_ioim_send_abort(struct bfa_ioim_s *ioim);
static void bfa_ioim_notify_cleanup(struct bfa_ioim_s *ioim);
static void __bfa_cb_ioim_good_comp(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_ioim_comp(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_ioim_abort(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_ioim_failed(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_ioim_pathtov(void *cbarg, bfa_boolean_t complete);
static bfa_boolean_t bfa_ioim_is_abortable(struct bfa_ioim_s *ioim);
/*
* forward declaration of BFA IO state machine
*/
static void bfa_ioim_sm_uninit(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_sgalloc(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_active(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_abort(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_cleanup(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_qfull(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_abort_qfull(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_cleanup_qfull(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_hcb(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_hcb_free(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_resfree(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
static void bfa_ioim_sm_cmnd_retry(struct bfa_ioim_s *ioim,
enum bfa_ioim_event event);
/*
* forward declaration for BFA TSKIM functions
*/
static void __bfa_cb_tskim_done(void *cbarg, bfa_boolean_t complete);
static void __bfa_cb_tskim_failed(void *cbarg, bfa_boolean_t complete);
static bfa_boolean_t bfa_tskim_match_scope(struct bfa_tskim_s *tskim,
struct scsi_lun lun);
static void bfa_tskim_gather_ios(struct bfa_tskim_s *tskim);
static void bfa_tskim_cleanp_comp(void *tskim_cbarg);
static void bfa_tskim_cleanup_ios(struct bfa_tskim_s *tskim);
static bfa_boolean_t bfa_tskim_send(struct bfa_tskim_s *tskim);
static bfa_boolean_t bfa_tskim_send_abort(struct bfa_tskim_s *tskim);
static void bfa_tskim_iocdisable_ios(struct bfa_tskim_s *tskim);
/*
* forward declaration of BFA TSKIM state machine
*/
static void bfa_tskim_sm_uninit(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
static void bfa_tskim_sm_active(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
static void bfa_tskim_sm_cleanup(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
static void bfa_tskim_sm_iocleanup(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
static void bfa_tskim_sm_qfull(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
static void bfa_tskim_sm_cleanup_qfull(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
static void bfa_tskim_sm_hcb(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event);
/*
* BFA FCP Initiator Mode module
*/
/*
* Compute and return memory needed by FCP(im) module.
*/
static void
bfa_fcpim_meminfo(struct bfa_iocfc_cfg_s *cfg, u32 *km_len,
u32 *dm_len)
{
bfa_itnim_meminfo(cfg, km_len, dm_len);
/*
* IO memory
*/
if (cfg->fwcfg.num_ioim_reqs < BFA_IOIM_MIN)
cfg->fwcfg.num_ioim_reqs = BFA_IOIM_MIN;
else if (cfg->fwcfg.num_ioim_reqs > BFA_IOIM_MAX)
cfg->fwcfg.num_ioim_reqs = BFA_IOIM_MAX;
*km_len += cfg->fwcfg.num_ioim_reqs *
(sizeof(struct bfa_ioim_s) + sizeof(struct bfa_ioim_sp_s));
*dm_len += cfg->fwcfg.num_ioim_reqs * BFI_IOIM_SNSLEN;
/*
* task management command memory
*/
if (cfg->fwcfg.num_tskim_reqs < BFA_TSKIM_MIN)
cfg->fwcfg.num_tskim_reqs = BFA_TSKIM_MIN;
*km_len += cfg->fwcfg.num_tskim_reqs * sizeof(struct bfa_tskim_s);
}
static void
bfa_fcpim_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
struct bfa_meminfo_s *meminfo, struct bfa_pcidev_s *pcidev)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
bfa_trc(bfa, cfg->drvcfg.path_tov);
bfa_trc(bfa, cfg->fwcfg.num_rports);
bfa_trc(bfa, cfg->fwcfg.num_ioim_reqs);
bfa_trc(bfa, cfg->fwcfg.num_tskim_reqs);
fcpim->bfa = bfa;
fcpim->num_itnims = cfg->fwcfg.num_rports;
fcpim->num_ioim_reqs = cfg->fwcfg.num_ioim_reqs;
fcpim->num_tskim_reqs = cfg->fwcfg.num_tskim_reqs;
fcpim->path_tov = cfg->drvcfg.path_tov;
fcpim->delay_comp = cfg->drvcfg.delay_comp;
fcpim->profile_comp = NULL;
fcpim->profile_start = NULL;
bfa_itnim_attach(fcpim, meminfo);
bfa_tskim_attach(fcpim, meminfo);
bfa_ioim_attach(fcpim, meminfo);
}
static void
bfa_fcpim_detach(struct bfa_s *bfa)
{
}
static void
bfa_fcpim_start(struct bfa_s *bfa)
{
}
static void
bfa_fcpim_stop(struct bfa_s *bfa)
{
}
static void
bfa_fcpim_iocdisable(struct bfa_s *bfa)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfa_itnim_s *itnim;
struct list_head *qe, *qen;
list_for_each_safe(qe, qen, &fcpim->itnim_q) {
itnim = (struct bfa_itnim_s *) qe;
bfa_itnim_iocdisable(itnim);
}
}
void
bfa_fcpim_path_tov_set(struct bfa_s *bfa, u16 path_tov)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
fcpim->path_tov = path_tov * 1000;
if (fcpim->path_tov > BFA_FCPIM_PATHTOV_MAX)
fcpim->path_tov = BFA_FCPIM_PATHTOV_MAX;
}
u16
bfa_fcpim_path_tov_get(struct bfa_s *bfa)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
return fcpim->path_tov / 1000;
}
u16
bfa_fcpim_qdepth_get(struct bfa_s *bfa)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
return fcpim->q_depth;
}
/*
* BFA ITNIM module state machine functions
*/
/*
* Beginning/unallocated state - no events expected.
*/
static void
bfa_itnim_sm_uninit(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_CREATE:
bfa_sm_set_state(itnim, bfa_itnim_sm_created);
itnim->is_online = BFA_FALSE;
bfa_fcpim_additn(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Beginning state, only online event expected.
*/
static void
bfa_itnim_sm_created(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_ONLINE:
if (bfa_itnim_send_fwcreate(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate_qfull);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_fcpim_delitn(itnim);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Waiting for itnim create response from firmware.
*/
static void
bfa_itnim_sm_fwcreate(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_FWRSP:
bfa_sm_set_state(itnim, bfa_itnim_sm_online);
itnim->is_online = BFA_TRUE;
bfa_itnim_iotov_online(itnim);
bfa_itnim_online_cb(itnim);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_delete_pending);
break;
case BFA_ITNIM_SM_OFFLINE:
if (bfa_itnim_send_fwdelete(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_fwdelete);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_fwdelete_qfull);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
static void
bfa_itnim_sm_fwcreate_qfull(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_QRESUME:
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate);
bfa_itnim_send_fwcreate(itnim);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_reqq_wcancel(&itnim->reqq_wait);
bfa_fcpim_delitn(itnim);
break;
case BFA_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_itnim_sm_offline);
bfa_reqq_wcancel(&itnim->reqq_wait);
bfa_itnim_offline_cb(itnim);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
bfa_reqq_wcancel(&itnim->reqq_wait);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Waiting for itnim create response from firmware, a delete is pending.
*/
static void
bfa_itnim_sm_delete_pending(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_FWRSP:
if (bfa_itnim_send_fwdelete(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting_qfull);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_fcpim_delitn(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Online state - normal parking state.
*/
static void
bfa_itnim_sm_online(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_itnim_sm_cleanup_offline);
itnim->is_online = BFA_FALSE;
bfa_itnim_iotov_start(itnim);
bfa_itnim_cleanup(itnim);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_cleanup_delete);
itnim->is_online = BFA_FALSE;
bfa_itnim_cleanup(itnim);
break;
case BFA_ITNIM_SM_SLER:
bfa_sm_set_state(itnim, bfa_itnim_sm_sler);
itnim->is_online = BFA_FALSE;
bfa_itnim_iotov_start(itnim);
bfa_itnim_sler_cb(itnim);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
itnim->is_online = BFA_FALSE;
bfa_itnim_iotov_start(itnim);
bfa_itnim_iocdisable_cleanup(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Second level error recovery need.
*/
static void
bfa_itnim_sm_sler(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_itnim_sm_cleanup_offline);
bfa_itnim_cleanup(itnim);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_cleanup_delete);
bfa_itnim_cleanup(itnim);
bfa_itnim_iotov_delete(itnim);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
bfa_itnim_iocdisable_cleanup(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Going offline. Waiting for active IO cleanup.
*/
static void
bfa_itnim_sm_cleanup_offline(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_CLEANUP:
if (bfa_itnim_send_fwdelete(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_fwdelete);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_fwdelete_qfull);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_cleanup_delete);
bfa_itnim_iotov_delete(itnim);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
bfa_itnim_iocdisable_cleanup(itnim);
bfa_itnim_offline_cb(itnim);
break;
case BFA_ITNIM_SM_SLER:
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Deleting itnim. Waiting for active IO cleanup.
*/
static void
bfa_itnim_sm_cleanup_delete(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_CLEANUP:
if (bfa_itnim_send_fwdelete(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting_qfull);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
bfa_itnim_iocdisable_cleanup(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Rport offline. Fimrware itnim is being deleted - awaiting f/w response.
*/
static void
bfa_itnim_sm_fwdelete(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_FWRSP:
bfa_sm_set_state(itnim, bfa_itnim_sm_offline);
bfa_itnim_offline_cb(itnim);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
bfa_itnim_offline_cb(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
static void
bfa_itnim_sm_fwdelete_qfull(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_QRESUME:
bfa_sm_set_state(itnim, bfa_itnim_sm_fwdelete);
bfa_itnim_send_fwdelete(itnim);
break;
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting_qfull);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
bfa_reqq_wcancel(&itnim->reqq_wait);
bfa_itnim_offline_cb(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Offline state.
*/
static void
bfa_itnim_sm_offline(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_itnim_iotov_delete(itnim);
bfa_fcpim_delitn(itnim);
break;
case BFA_ITNIM_SM_ONLINE:
if (bfa_itnim_send_fwcreate(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate_qfull);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_iocdisable);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
static void
bfa_itnim_sm_iocdisable(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_itnim_iotov_delete(itnim);
bfa_fcpim_delitn(itnim);
break;
case BFA_ITNIM_SM_OFFLINE:
bfa_itnim_offline_cb(itnim);
break;
case BFA_ITNIM_SM_ONLINE:
if (bfa_itnim_send_fwcreate(itnim))
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate);
else
bfa_sm_set_state(itnim, bfa_itnim_sm_fwcreate_qfull);
break;
case BFA_ITNIM_SM_HWFAIL:
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Itnim is deleted, waiting for firmware response to delete.
*/
static void
bfa_itnim_sm_deleting(struct bfa_itnim_s *itnim, enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_FWRSP:
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_fcpim_delitn(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
static void
bfa_itnim_sm_deleting_qfull(struct bfa_itnim_s *itnim,
enum bfa_itnim_event event)
{
bfa_trc(itnim->bfa, itnim->rport->rport_tag);
bfa_trc(itnim->bfa, event);
switch (event) {
case BFA_ITNIM_SM_QRESUME:
bfa_sm_set_state(itnim, bfa_itnim_sm_deleting);
bfa_itnim_send_fwdelete(itnim);
break;
case BFA_ITNIM_SM_HWFAIL:
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
bfa_reqq_wcancel(&itnim->reqq_wait);
bfa_fcpim_delitn(itnim);
break;
default:
bfa_sm_fault(itnim->bfa, event);
}
}
/*
* Initiate cleanup of all IOs on an IOC failure.
*/
static void
bfa_itnim_iocdisable_cleanup(struct bfa_itnim_s *itnim)
{
struct bfa_tskim_s *tskim;
struct bfa_ioim_s *ioim;
struct list_head *qe, *qen;
list_for_each_safe(qe, qen, &itnim->tsk_q) {
tskim = (struct bfa_tskim_s *) qe;
bfa_tskim_iocdisable(tskim);
}
list_for_each_safe(qe, qen, &itnim->io_q) {
ioim = (struct bfa_ioim_s *) qe;
bfa_ioim_iocdisable(ioim);
}
/*
* For IO request in pending queue, we pretend an early timeout.
*/
list_for_each_safe(qe, qen, &itnim->pending_q) {
ioim = (struct bfa_ioim_s *) qe;
bfa_ioim_tov(ioim);
}
list_for_each_safe(qe, qen, &itnim->io_cleanup_q) {
ioim = (struct bfa_ioim_s *) qe;
bfa_ioim_iocdisable(ioim);
}
}
/*
* IO cleanup completion
*/
static void
bfa_itnim_cleanp_comp(void *itnim_cbarg)
{
struct bfa_itnim_s *itnim = itnim_cbarg;
bfa_stats(itnim, cleanup_comps);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_CLEANUP);
}
/*
* Initiate cleanup of all IOs.
*/
static void
bfa_itnim_cleanup(struct bfa_itnim_s *itnim)
{
struct bfa_ioim_s *ioim;
struct bfa_tskim_s *tskim;
struct list_head *qe, *qen;
bfa_wc_init(&itnim->wc, bfa_itnim_cleanp_comp, itnim);
list_for_each_safe(qe, qen, &itnim->io_q) {
ioim = (struct bfa_ioim_s *) qe;
/*
* Move IO to a cleanup queue from active queue so that a later
* TM will not pickup this IO.
*/
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &itnim->io_cleanup_q);
bfa_wc_up(&itnim->wc);
bfa_ioim_cleanup(ioim);
}
list_for_each_safe(qe, qen, &itnim->tsk_q) {
tskim = (struct bfa_tskim_s *) qe;
bfa_wc_up(&itnim->wc);
bfa_tskim_cleanup(tskim);
}
bfa_wc_wait(&itnim->wc);
}
static void
__bfa_cb_itnim_online(void *cbarg, bfa_boolean_t complete)
{
struct bfa_itnim_s *itnim = cbarg;
if (complete)
bfa_cb_itnim_online(itnim->ditn);
}
static void
__bfa_cb_itnim_offline(void *cbarg, bfa_boolean_t complete)
{
struct bfa_itnim_s *itnim = cbarg;
if (complete)
bfa_cb_itnim_offline(itnim->ditn);
}
static void
__bfa_cb_itnim_sler(void *cbarg, bfa_boolean_t complete)
{
struct bfa_itnim_s *itnim = cbarg;
if (complete)
bfa_cb_itnim_sler(itnim->ditn);
}
/*
* Call to resume any I/O requests waiting for room in request queue.
*/
static void
bfa_itnim_qresume(void *cbarg)
{
struct bfa_itnim_s *itnim = cbarg;
bfa_sm_send_event(itnim, BFA_ITNIM_SM_QRESUME);
}
/*
* bfa_itnim_public
*/
void
bfa_itnim_iodone(struct bfa_itnim_s *itnim)
{
bfa_wc_down(&itnim->wc);
}
void
bfa_itnim_tskdone(struct bfa_itnim_s *itnim)
{
bfa_wc_down(&itnim->wc);
}
void
bfa_itnim_meminfo(struct bfa_iocfc_cfg_s *cfg, u32 *km_len,
u32 *dm_len)
{
/*
* ITN memory
*/
*km_len += cfg->fwcfg.num_rports * sizeof(struct bfa_itnim_s);
}
void
bfa_itnim_attach(struct bfa_fcpim_mod_s *fcpim, struct bfa_meminfo_s *minfo)
{
struct bfa_s *bfa = fcpim->bfa;
struct bfa_itnim_s *itnim;
int i, j;
INIT_LIST_HEAD(&fcpim->itnim_q);
itnim = (struct bfa_itnim_s *) bfa_meminfo_kva(minfo);
fcpim->itnim_arr = itnim;
for (i = 0; i < fcpim->num_itnims; i++, itnim++) {
memset(itnim, 0, sizeof(struct bfa_itnim_s));
itnim->bfa = bfa;
itnim->fcpim = fcpim;
itnim->reqq = BFA_REQQ_QOS_LO;
itnim->rport = BFA_RPORT_FROM_TAG(bfa, i);
itnim->iotov_active = BFA_FALSE;
bfa_reqq_winit(&itnim->reqq_wait, bfa_itnim_qresume, itnim);
INIT_LIST_HEAD(&itnim->io_q);
INIT_LIST_HEAD(&itnim->io_cleanup_q);
INIT_LIST_HEAD(&itnim->pending_q);
INIT_LIST_HEAD(&itnim->tsk_q);
INIT_LIST_HEAD(&itnim->delay_comp_q);
for (j = 0; j < BFA_IOBUCKET_MAX; j++)
itnim->ioprofile.io_latency.min[j] = ~0;
bfa_sm_set_state(itnim, bfa_itnim_sm_uninit);
}
bfa_meminfo_kva(minfo) = (u8 *) itnim;
}
void
bfa_itnim_iocdisable(struct bfa_itnim_s *itnim)
{
bfa_stats(itnim, ioc_disabled);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_HWFAIL);
}
static bfa_boolean_t
bfa_itnim_send_fwcreate(struct bfa_itnim_s *itnim)
{
struct bfi_itnim_create_req_s *m;
itnim->msg_no++;
/*
* check for room in queue to send request now
*/
m = bfa_reqq_next(itnim->bfa, itnim->reqq);
if (!m) {
bfa_reqq_wait(itnim->bfa, itnim->reqq, &itnim->reqq_wait);
return BFA_FALSE;
}
bfi_h2i_set(m->mh, BFI_MC_ITNIM, BFI_ITNIM_H2I_CREATE_REQ,
bfa_lpuid(itnim->bfa));
m->fw_handle = itnim->rport->fw_handle;
m->class = FC_CLASS_3;
m->seq_rec = itnim->seq_rec;
m->msg_no = itnim->msg_no;
bfa_stats(itnim, fw_create);
/*
* queue I/O message to firmware
*/
bfa_reqq_produce(itnim->bfa, itnim->reqq);
return BFA_TRUE;
}
static bfa_boolean_t
bfa_itnim_send_fwdelete(struct bfa_itnim_s *itnim)
{
struct bfi_itnim_delete_req_s *m;
/*
* check for room in queue to send request now
*/
m = bfa_reqq_next(itnim->bfa, itnim->reqq);
if (!m) {
bfa_reqq_wait(itnim->bfa, itnim->reqq, &itnim->reqq_wait);
return BFA_FALSE;
}
bfi_h2i_set(m->mh, BFI_MC_ITNIM, BFI_ITNIM_H2I_DELETE_REQ,
bfa_lpuid(itnim->bfa));
m->fw_handle = itnim->rport->fw_handle;
bfa_stats(itnim, fw_delete);
/*
* queue I/O message to firmware
*/
bfa_reqq_produce(itnim->bfa, itnim->reqq);
return BFA_TRUE;
}
/*
* Cleanup all pending failed inflight requests.
*/
static void
bfa_itnim_delayed_comp(struct bfa_itnim_s *itnim, bfa_boolean_t iotov)
{
struct bfa_ioim_s *ioim;
struct list_head *qe, *qen;
list_for_each_safe(qe, qen, &itnim->delay_comp_q) {
ioim = (struct bfa_ioim_s *)qe;
bfa_ioim_delayed_comp(ioim, iotov);
}
}
/*
* Start all pending IO requests.
*/
static void
bfa_itnim_iotov_online(struct bfa_itnim_s *itnim)
{
struct bfa_ioim_s *ioim;
bfa_itnim_iotov_stop(itnim);
/*
* Abort all inflight IO requests in the queue
*/
bfa_itnim_delayed_comp(itnim, BFA_FALSE);
/*
* Start all pending IO requests.
*/
while (!list_empty(&itnim->pending_q)) {
bfa_q_deq(&itnim->pending_q, &ioim);
list_add_tail(&ioim->qe, &itnim->io_q);
bfa_ioim_start(ioim);
}
}
/*
* Fail all pending IO requests
*/
static void
bfa_itnim_iotov_cleanup(struct bfa_itnim_s *itnim)
{
struct bfa_ioim_s *ioim;
/*
* Fail all inflight IO requests in the queue
*/
bfa_itnim_delayed_comp(itnim, BFA_TRUE);
/*
* Fail any pending IO requests.
*/
while (!list_empty(&itnim->pending_q)) {
bfa_q_deq(&itnim->pending_q, &ioim);
list_add_tail(&ioim->qe, &ioim->fcpim->ioim_comp_q);
bfa_ioim_tov(ioim);
}
}
/*
* IO TOV timer callback. Fail any pending IO requests.
*/
static void
bfa_itnim_iotov(void *itnim_arg)
{
struct bfa_itnim_s *itnim = itnim_arg;
itnim->iotov_active = BFA_FALSE;
bfa_cb_itnim_tov_begin(itnim->ditn);
bfa_itnim_iotov_cleanup(itnim);
bfa_cb_itnim_tov(itnim->ditn);
}
/*
* Start IO TOV timer for failing back pending IO requests in offline state.
*/
static void
bfa_itnim_iotov_start(struct bfa_itnim_s *itnim)
{
if (itnim->fcpim->path_tov > 0) {
itnim->iotov_active = BFA_TRUE;
WARN_ON(!bfa_itnim_hold_io(itnim));
bfa_timer_start(itnim->bfa, &itnim->timer,
bfa_itnim_iotov, itnim, itnim->fcpim->path_tov);
}
}
/*
* Stop IO TOV timer.
*/
static void
bfa_itnim_iotov_stop(struct bfa_itnim_s *itnim)
{
if (itnim->iotov_active) {
itnim->iotov_active = BFA_FALSE;
bfa_timer_stop(&itnim->timer);
}
}
/*
* Stop IO TOV timer.
*/
static void
bfa_itnim_iotov_delete(struct bfa_itnim_s *itnim)
{
bfa_boolean_t pathtov_active = BFA_FALSE;
if (itnim->iotov_active)
pathtov_active = BFA_TRUE;
bfa_itnim_iotov_stop(itnim);
if (pathtov_active)
bfa_cb_itnim_tov_begin(itnim->ditn);
bfa_itnim_iotov_cleanup(itnim);
if (pathtov_active)
bfa_cb_itnim_tov(itnim->ditn);
}
static void
bfa_itnim_update_del_itn_stats(struct bfa_itnim_s *itnim)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(itnim->bfa);
fcpim->del_itn_stats.del_itn_iocomp_aborted +=
itnim->stats.iocomp_aborted;
fcpim->del_itn_stats.del_itn_iocomp_timedout +=
itnim->stats.iocomp_timedout;
fcpim->del_itn_stats.del_itn_iocom_sqer_needed +=
itnim->stats.iocom_sqer_needed;
fcpim->del_itn_stats.del_itn_iocom_res_free +=
itnim->stats.iocom_res_free;
fcpim->del_itn_stats.del_itn_iocom_hostabrts +=
itnim->stats.iocom_hostabrts;
fcpim->del_itn_stats.del_itn_total_ios += itnim->stats.total_ios;
fcpim->del_itn_stats.del_io_iocdowns += itnim->stats.io_iocdowns;
fcpim->del_itn_stats.del_tm_iocdowns += itnim->stats.tm_iocdowns;
}
/*
* bfa_itnim_public
*/
/*
* Itnim interrupt processing.
*/
void
bfa_itnim_isr(struct bfa_s *bfa, struct bfi_msg_s *m)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
union bfi_itnim_i2h_msg_u msg;
struct bfa_itnim_s *itnim;
bfa_trc(bfa, m->mhdr.msg_id);
msg.msg = m;
switch (m->mhdr.msg_id) {
case BFI_ITNIM_I2H_CREATE_RSP:
itnim = BFA_ITNIM_FROM_TAG(fcpim,
msg.create_rsp->bfa_handle);
WARN_ON(msg.create_rsp->status != BFA_STATUS_OK);
bfa_stats(itnim, create_comps);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_FWRSP);
break;
case BFI_ITNIM_I2H_DELETE_RSP:
itnim = BFA_ITNIM_FROM_TAG(fcpim,
msg.delete_rsp->bfa_handle);
WARN_ON(msg.delete_rsp->status != BFA_STATUS_OK);
bfa_stats(itnim, delete_comps);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_FWRSP);
break;
case BFI_ITNIM_I2H_SLER_EVENT:
itnim = BFA_ITNIM_FROM_TAG(fcpim,
msg.sler_event->bfa_handle);
bfa_stats(itnim, sler_events);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_SLER);
break;
default:
bfa_trc(bfa, m->mhdr.msg_id);
WARN_ON(1);
}
}
/*
* bfa_itnim_api
*/
struct bfa_itnim_s *
bfa_itnim_create(struct bfa_s *bfa, struct bfa_rport_s *rport, void *ditn)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfa_itnim_s *itnim;
itnim = BFA_ITNIM_FROM_TAG(fcpim, rport->rport_tag);
WARN_ON(itnim->rport != rport);
itnim->ditn = ditn;
bfa_stats(itnim, creates);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_CREATE);
return itnim;
}
void
bfa_itnim_delete(struct bfa_itnim_s *itnim)
{
bfa_stats(itnim, deletes);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_DELETE);
}
void
bfa_itnim_online(struct bfa_itnim_s *itnim, bfa_boolean_t seq_rec)
{
itnim->seq_rec = seq_rec;
bfa_stats(itnim, onlines);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_ONLINE);
}
void
bfa_itnim_offline(struct bfa_itnim_s *itnim)
{
bfa_stats(itnim, offlines);
bfa_sm_send_event(itnim, BFA_ITNIM_SM_OFFLINE);
}
/*
* Return true if itnim is considered offline for holding off IO request.
* IO is not held if itnim is being deleted.
*/
bfa_boolean_t
bfa_itnim_hold_io(struct bfa_itnim_s *itnim)
{
return itnim->fcpim->path_tov && itnim->iotov_active &&
(bfa_sm_cmp_state(itnim, bfa_itnim_sm_fwcreate) ||
bfa_sm_cmp_state(itnim, bfa_itnim_sm_sler) ||
bfa_sm_cmp_state(itnim, bfa_itnim_sm_cleanup_offline) ||
bfa_sm_cmp_state(itnim, bfa_itnim_sm_fwdelete) ||
bfa_sm_cmp_state(itnim, bfa_itnim_sm_offline) ||
bfa_sm_cmp_state(itnim, bfa_itnim_sm_iocdisable));
}
void
bfa_itnim_clear_stats(struct bfa_itnim_s *itnim)
{
int j;
memset(&itnim->stats, 0, sizeof(itnim->stats));
memset(&itnim->ioprofile, 0, sizeof(itnim->ioprofile));
for (j = 0; j < BFA_IOBUCKET_MAX; j++)
itnim->ioprofile.io_latency.min[j] = ~0;
}
/*
* BFA IO module state machine functions
*/
/*
* IO is not started (unallocated).
*/
static void
bfa_ioim_sm_uninit(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
switch (event) {
case BFA_IOIM_SM_START:
if (!bfa_itnim_is_online(ioim->itnim)) {
if (!bfa_itnim_hold_io(ioim->itnim)) {
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
list_del(&ioim->qe);
list_add_tail(&ioim->qe,
&ioim->fcpim->ioim_comp_q);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe,
__bfa_cb_ioim_pathtov, ioim);
} else {
list_del(&ioim->qe);
list_add_tail(&ioim->qe,
&ioim->itnim->pending_q);
}
break;
}
if (ioim->nsges > BFI_SGE_INLINE) {
if (!bfa_ioim_sgpg_alloc(ioim)) {
bfa_sm_set_state(ioim, bfa_ioim_sm_sgalloc);
return;
}
}
if (!bfa_ioim_send_ioreq(ioim)) {
bfa_sm_set_state(ioim, bfa_ioim_sm_qfull);
break;
}
bfa_sm_set_state(ioim, bfa_ioim_sm_active);
break;
case BFA_IOIM_SM_IOTOV:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe,
__bfa_cb_ioim_pathtov, ioim);
break;
case BFA_IOIM_SM_ABORT:
/*
* IO in pending queue can get abort requests. Complete abort
* requests immediately.
*/
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
WARN_ON(!bfa_q_is_on_q(&ioim->itnim->pending_q, ioim));
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe,
__bfa_cb_ioim_abort, ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is waiting for SG pages.
*/
static void
bfa_ioim_sm_sgalloc(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_SGALLOCED:
if (!bfa_ioim_send_ioreq(ioim)) {
bfa_sm_set_state(ioim, bfa_ioim_sm_qfull);
break;
}
bfa_sm_set_state(ioim, bfa_ioim_sm_active);
break;
case BFA_IOIM_SM_CLEANUP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_sgpg_wcancel(ioim->bfa, &ioim->iosp->sgpg_wqe);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_ABORT:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_sgpg_wcancel(ioim->bfa, &ioim->iosp->sgpg_wqe);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_sgpg_wcancel(ioim->bfa, &ioim->iosp->sgpg_wqe);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is active.
*/
static void
bfa_ioim_sm_active(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
switch (event) {
case BFA_IOIM_SM_COMP_GOOD:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe,
__bfa_cb_ioim_good_comp, ioim);
break;
case BFA_IOIM_SM_COMP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_comp,
ioim);
break;
case BFA_IOIM_SM_DONE:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_comp,
ioim);
break;
case BFA_IOIM_SM_ABORT:
ioim->iosp->abort_explicit = BFA_TRUE;
ioim->io_cbfn = __bfa_cb_ioim_abort;
if (bfa_ioim_send_abort(ioim))
bfa_sm_set_state(ioim, bfa_ioim_sm_abort);
else {
bfa_sm_set_state(ioim, bfa_ioim_sm_abort_qfull);
bfa_stats(ioim->itnim, qwait);
bfa_reqq_wait(ioim->bfa, ioim->reqq,
&ioim->iosp->reqq_wait);
}
break;
case BFA_IOIM_SM_CLEANUP:
ioim->iosp->abort_explicit = BFA_FALSE;
ioim->io_cbfn = __bfa_cb_ioim_failed;
if (bfa_ioim_send_abort(ioim))
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup);
else {
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup_qfull);
bfa_stats(ioim->itnim, qwait);
bfa_reqq_wait(ioim->bfa, ioim->reqq,
&ioim->iosp->reqq_wait);
}
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
case BFA_IOIM_SM_SQRETRY:
if (bfa_ioim_maxretry_reached(ioim)) {
/* max retry reached, free IO */
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe,
__bfa_cb_ioim_failed, ioim);
break;
}
/* waiting for IO tag resource free */
bfa_sm_set_state(ioim, bfa_ioim_sm_cmnd_retry);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is retried with new tag.
*/
static void
bfa_ioim_sm_cmnd_retry(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
switch (event) {
case BFA_IOIM_SM_FREE:
/* abts and rrq done. Now retry the IO with new tag */
bfa_ioim_update_iotag(ioim);
if (!bfa_ioim_send_ioreq(ioim)) {
bfa_sm_set_state(ioim, bfa_ioim_sm_qfull);
break;
}
bfa_sm_set_state(ioim, bfa_ioim_sm_active);
break;
case BFA_IOIM_SM_CLEANUP:
ioim->iosp->abort_explicit = BFA_FALSE;
ioim->io_cbfn = __bfa_cb_ioim_failed;
if (bfa_ioim_send_abort(ioim))
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup);
else {
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup_qfull);
bfa_stats(ioim->itnim, qwait);
bfa_reqq_wait(ioim->bfa, ioim->reqq,
&ioim->iosp->reqq_wait);
}
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe,
__bfa_cb_ioim_failed, ioim);
break;
case BFA_IOIM_SM_ABORT:
/* in this state IO abort is done.
* Waiting for IO tag resource free.
*/
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is being aborted, waiting for completion from firmware.
*/
static void
bfa_ioim_sm_abort(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_COMP_GOOD:
case BFA_IOIM_SM_COMP:
case BFA_IOIM_SM_DONE:
case BFA_IOIM_SM_FREE:
break;
case BFA_IOIM_SM_ABORT_DONE:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_ABORT_COMP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_COMP_UTAG:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_CLEANUP:
WARN_ON(ioim->iosp->abort_explicit != BFA_TRUE);
ioim->iosp->abort_explicit = BFA_FALSE;
if (bfa_ioim_send_abort(ioim))
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup);
else {
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup_qfull);
bfa_stats(ioim->itnim, qwait);
bfa_reqq_wait(ioim->bfa, ioim->reqq,
&ioim->iosp->reqq_wait);
}
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is being cleaned up (implicit abort), waiting for completion from
* firmware.
*/
static void
bfa_ioim_sm_cleanup(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_COMP_GOOD:
case BFA_IOIM_SM_COMP:
case BFA_IOIM_SM_DONE:
case BFA_IOIM_SM_FREE:
break;
case BFA_IOIM_SM_ABORT:
/*
* IO is already being aborted implicitly
*/
ioim->io_cbfn = __bfa_cb_ioim_abort;
break;
case BFA_IOIM_SM_ABORT_DONE:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, ioim->io_cbfn, ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_ABORT_COMP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, ioim->io_cbfn, ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_COMP_UTAG:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, ioim->io_cbfn, ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
case BFA_IOIM_SM_CLEANUP:
/*
* IO can be in cleanup state already due to TM command.
* 2nd cleanup request comes from ITN offline event.
*/
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is waiting for room in request CQ
*/
static void
bfa_ioim_sm_qfull(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_QRESUME:
bfa_sm_set_state(ioim, bfa_ioim_sm_active);
bfa_ioim_send_ioreq(ioim);
break;
case BFA_IOIM_SM_ABORT:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_CLEANUP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* Active IO is being aborted, waiting for room in request CQ.
*/
static void
bfa_ioim_sm_abort_qfull(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_QRESUME:
bfa_sm_set_state(ioim, bfa_ioim_sm_abort);
bfa_ioim_send_abort(ioim);
break;
case BFA_IOIM_SM_CLEANUP:
WARN_ON(ioim->iosp->abort_explicit != BFA_TRUE);
ioim->iosp->abort_explicit = BFA_FALSE;
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup_qfull);
break;
case BFA_IOIM_SM_COMP_GOOD:
case BFA_IOIM_SM_COMP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_DONE:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_abort,
ioim);
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* Active IO is being cleaned up, waiting for room in request CQ.
*/
static void
bfa_ioim_sm_cleanup_qfull(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_QRESUME:
bfa_sm_set_state(ioim, bfa_ioim_sm_cleanup);
bfa_ioim_send_abort(ioim);
break;
case BFA_IOIM_SM_ABORT:
/*
* IO is already being cleaned up implicitly
*/
ioim->io_cbfn = __bfa_cb_ioim_abort;
break;
case BFA_IOIM_SM_COMP_GOOD:
case BFA_IOIM_SM_COMP:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, ioim->io_cbfn, ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_DONE:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb_free);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, ioim->io_cbfn, ioim);
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
bfa_reqq_wcancel(&ioim->iosp->reqq_wait);
bfa_ioim_move_to_comp_q(ioim);
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, __bfa_cb_ioim_failed,
ioim);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO bfa callback is pending.
*/
static void
bfa_ioim_sm_hcb(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
switch (event) {
case BFA_IOIM_SM_HCB:
bfa_sm_set_state(ioim, bfa_ioim_sm_uninit);
bfa_ioim_free(ioim);
break;
case BFA_IOIM_SM_CLEANUP:
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_HWFAIL:
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO bfa callback is pending. IO resource cannot be freed.
*/
static void
bfa_ioim_sm_hcb_free(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_HCB:
bfa_sm_set_state(ioim, bfa_ioim_sm_resfree);
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &ioim->fcpim->ioim_resfree_q);
break;
case BFA_IOIM_SM_FREE:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
break;
case BFA_IOIM_SM_CLEANUP:
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_HWFAIL:
bfa_sm_set_state(ioim, bfa_ioim_sm_hcb);
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
/*
* IO is completed, waiting resource free from firmware.
*/
static void
bfa_ioim_sm_resfree(struct bfa_ioim_s *ioim, enum bfa_ioim_event event)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, event);
switch (event) {
case BFA_IOIM_SM_FREE:
bfa_sm_set_state(ioim, bfa_ioim_sm_uninit);
bfa_ioim_free(ioim);
break;
case BFA_IOIM_SM_CLEANUP:
bfa_ioim_notify_cleanup(ioim);
break;
case BFA_IOIM_SM_HWFAIL:
break;
default:
bfa_sm_fault(ioim->bfa, event);
}
}
static void
__bfa_cb_ioim_good_comp(void *cbarg, bfa_boolean_t complete)
{
struct bfa_ioim_s *ioim = cbarg;
if (!complete) {
bfa_sm_send_event(ioim, BFA_IOIM_SM_HCB);
return;
}
bfa_cb_ioim_good_comp(ioim->bfa->bfad, ioim->dio);
}
static void
__bfa_cb_ioim_comp(void *cbarg, bfa_boolean_t complete)
{
struct bfa_ioim_s *ioim = cbarg;
struct bfi_ioim_rsp_s *m;
u8 *snsinfo = NULL;
u8 sns_len = 0;
s32 residue = 0;
if (!complete) {
bfa_sm_send_event(ioim, BFA_IOIM_SM_HCB);
return;
}
m = (struct bfi_ioim_rsp_s *) &ioim->iosp->comp_rspmsg;
if (m->io_status == BFI_IOIM_STS_OK) {
/*
* setup sense information, if present
*/
if ((m->scsi_status == SCSI_STATUS_CHECK_CONDITION) &&
m->sns_len) {
sns_len = m->sns_len;
snsinfo = ioim->iosp->snsinfo;
}
/*
* setup residue value correctly for normal completions
*/
if (m->resid_flags == FCP_RESID_UNDER) {
residue = be32_to_cpu(m->residue);
bfa_stats(ioim->itnim, iocomp_underrun);
}
if (m->resid_flags == FCP_RESID_OVER) {
residue = be32_to_cpu(m->residue);
residue = -residue;
bfa_stats(ioim->itnim, iocomp_overrun);
}
}
bfa_cb_ioim_done(ioim->bfa->bfad, ioim->dio, m->io_status,
m->scsi_status, sns_len, snsinfo, residue);
}
static void
__bfa_cb_ioim_failed(void *cbarg, bfa_boolean_t complete)
{
struct bfa_ioim_s *ioim = cbarg;
if (!complete) {
bfa_sm_send_event(ioim, BFA_IOIM_SM_HCB);
return;
}
bfa_cb_ioim_done(ioim->bfa->bfad, ioim->dio, BFI_IOIM_STS_ABORTED,
0, 0, NULL, 0);
}
static void
__bfa_cb_ioim_pathtov(void *cbarg, bfa_boolean_t complete)
{
struct bfa_ioim_s *ioim = cbarg;
bfa_stats(ioim->itnim, path_tov_expired);
if (!complete) {
bfa_sm_send_event(ioim, BFA_IOIM_SM_HCB);
return;
}
bfa_cb_ioim_done(ioim->bfa->bfad, ioim->dio, BFI_IOIM_STS_PATHTOV,
0, 0, NULL, 0);
}
static void
__bfa_cb_ioim_abort(void *cbarg, bfa_boolean_t complete)
{
struct bfa_ioim_s *ioim = cbarg;
if (!complete) {
bfa_sm_send_event(ioim, BFA_IOIM_SM_HCB);
return;
}
bfa_cb_ioim_abort(ioim->bfa->bfad, ioim->dio);
}
static void
bfa_ioim_sgpg_alloced(void *cbarg)
{
struct bfa_ioim_s *ioim = cbarg;
ioim->nsgpgs = BFA_SGPG_NPAGE(ioim->nsges);
list_splice_tail_init(&ioim->iosp->sgpg_wqe.sgpg_q, &ioim->sgpg_q);
ioim->sgpg = bfa_q_first(&ioim->sgpg_q);
bfa_sm_send_event(ioim, BFA_IOIM_SM_SGALLOCED);
}
/*
* Send I/O request to firmware.
*/
static bfa_boolean_t
bfa_ioim_send_ioreq(struct bfa_ioim_s *ioim)
{
struct bfa_itnim_s *itnim = ioim->itnim;
struct bfi_ioim_req_s *m;
static struct fcp_cmnd_s cmnd_z0 = { { { 0 } } };
struct bfi_sge_s *sge, *sgpge;
u32 pgdlen = 0;
u32 fcp_dl;
u64 addr;
struct scatterlist *sg;
struct bfa_sgpg_s *sgpg;
struct scsi_cmnd *cmnd = (struct scsi_cmnd *) ioim->dio;
u32 i, sge_id, pgcumsz;
enum dma_data_direction dmadir;
/*
* check for room in queue to send request now
*/
m = bfa_reqq_next(ioim->bfa, ioim->reqq);
if (!m) {
bfa_stats(ioim->itnim, qwait);
bfa_reqq_wait(ioim->bfa, ioim->reqq,
&ioim->iosp->reqq_wait);
return BFA_FALSE;
}
/*
* build i/o request message next
*/
m->io_tag = cpu_to_be16(ioim->iotag);
m->rport_hdl = ioim->itnim->rport->fw_handle;
m->io_timeout = 0;
sge = &m->sges[0];
sgpg = ioim->sgpg;
sge_id = 0;
sgpge = NULL;
pgcumsz = 0;
scsi_for_each_sg(cmnd, sg, ioim->nsges, i) {
if (i == 0) {
/* build inline IO SG element */
addr = bfa_sgaddr_le(sg_dma_address(sg));
sge->sga = *(union bfi_addr_u *) &addr;
pgdlen = sg_dma_len(sg);
sge->sg_len = pgdlen;
sge->flags = (ioim->nsges > BFI_SGE_INLINE) ?
BFI_SGE_DATA_CPL : BFI_SGE_DATA_LAST;
bfa_sge_to_be(sge);
sge++;
} else {
if (sge_id == 0)
sgpge = sgpg->sgpg->sges;
addr = bfa_sgaddr_le(sg_dma_address(sg));
sgpge->sga = *(union bfi_addr_u *) &addr;
sgpge->sg_len = sg_dma_len(sg);
pgcumsz += sgpge->sg_len;
/* set flags */
if (i < (ioim->nsges - 1) &&
sge_id < (BFI_SGPG_DATA_SGES - 1))
sgpge->flags = BFI_SGE_DATA;
else if (i < (ioim->nsges - 1))
sgpge->flags = BFI_SGE_DATA_CPL;
else
sgpge->flags = BFI_SGE_DATA_LAST;
bfa_sge_to_le(sgpge);
sgpge++;
if (i == (ioim->nsges - 1)) {
sgpge->flags = BFI_SGE_PGDLEN;
sgpge->sga.a32.addr_lo = 0;
sgpge->sga.a32.addr_hi = 0;
sgpge->sg_len = pgcumsz;
bfa_sge_to_le(sgpge);
} else if (++sge_id == BFI_SGPG_DATA_SGES) {
sgpg = (struct bfa_sgpg_s *) bfa_q_next(sgpg);
sgpge->flags = BFI_SGE_LINK;
sgpge->sga = sgpg->sgpg_pa;
sgpge->sg_len = pgcumsz;
bfa_sge_to_le(sgpge);
sge_id = 0;
pgcumsz = 0;
}
}
}
if (ioim->nsges > BFI_SGE_INLINE) {
sge->sga = ioim->sgpg->sgpg_pa;
} else {
sge->sga.a32.addr_lo = 0;
sge->sga.a32.addr_hi = 0;
}
sge->sg_len = pgdlen;
sge->flags = BFI_SGE_PGDLEN;
bfa_sge_to_be(sge);
/*
* set up I/O command parameters
*/
m->cmnd = cmnd_z0;
int_to_scsilun(cmnd->device->lun, &m->cmnd.lun);
dmadir = cmnd->sc_data_direction;
if (dmadir == DMA_TO_DEVICE)
m->cmnd.iodir = FCP_IODIR_WRITE;
else if (dmadir == DMA_FROM_DEVICE)
m->cmnd.iodir = FCP_IODIR_READ;
else
m->cmnd.iodir = FCP_IODIR_NONE;
m->cmnd.cdb = *(struct scsi_cdb_s *) cmnd->cmnd;
fcp_dl = scsi_bufflen(cmnd);
m->cmnd.fcp_dl = cpu_to_be32(fcp_dl);
/*
* set up I/O message header
*/
switch (m->cmnd.iodir) {
case FCP_IODIR_READ:
bfi_h2i_set(m->mh, BFI_MC_IOIM_READ, 0, bfa_lpuid(ioim->bfa));
bfa_stats(itnim, input_reqs);
ioim->itnim->stats.rd_throughput += fcp_dl;
break;
case FCP_IODIR_WRITE:
bfi_h2i_set(m->mh, BFI_MC_IOIM_WRITE, 0, bfa_lpuid(ioim->bfa));
bfa_stats(itnim, output_reqs);
ioim->itnim->stats.wr_throughput += fcp_dl;
break;
case FCP_IODIR_RW:
bfa_stats(itnim, input_reqs);
bfa_stats(itnim, output_reqs);
default:
bfi_h2i_set(m->mh, BFI_MC_IOIM_IO, 0, bfa_lpuid(ioim->bfa));
}
if (itnim->seq_rec ||
(scsi_bufflen(cmnd) & (sizeof(u32) - 1)))
bfi_h2i_set(m->mh, BFI_MC_IOIM_IO, 0, bfa_lpuid(ioim->bfa));
/*
* queue I/O message to firmware
*/
bfa_reqq_produce(ioim->bfa, ioim->reqq);
return BFA_TRUE;
}
/*
* Setup any additional SG pages needed.Inline SG element is setup
* at queuing time.
*/
static bfa_boolean_t
bfa_ioim_sgpg_alloc(struct bfa_ioim_s *ioim)
{
u16 nsgpgs;
WARN_ON(ioim->nsges <= BFI_SGE_INLINE);
/*
* allocate SG pages needed
*/
nsgpgs = BFA_SGPG_NPAGE(ioim->nsges);
if (!nsgpgs)
return BFA_TRUE;
if (bfa_sgpg_malloc(ioim->bfa, &ioim->sgpg_q, nsgpgs)
!= BFA_STATUS_OK) {
bfa_sgpg_wait(ioim->bfa, &ioim->iosp->sgpg_wqe, nsgpgs);
return BFA_FALSE;
}
ioim->nsgpgs = nsgpgs;
ioim->sgpg = bfa_q_first(&ioim->sgpg_q);
return BFA_TRUE;
}
/*
* Send I/O abort request to firmware.
*/
static bfa_boolean_t
bfa_ioim_send_abort(struct bfa_ioim_s *ioim)
{
struct bfi_ioim_abort_req_s *m;
enum bfi_ioim_h2i msgop;
/*
* check for room in queue to send request now
*/
m = bfa_reqq_next(ioim->bfa, ioim->reqq);
if (!m)
return BFA_FALSE;
/*
* build i/o request message next
*/
if (ioim->iosp->abort_explicit)
msgop = BFI_IOIM_H2I_IOABORT_REQ;
else
msgop = BFI_IOIM_H2I_IOCLEANUP_REQ;
bfi_h2i_set(m->mh, BFI_MC_IOIM, msgop, bfa_lpuid(ioim->bfa));
m->io_tag = cpu_to_be16(ioim->iotag);
m->abort_tag = ++ioim->abort_tag;
/*
* queue I/O message to firmware
*/
bfa_reqq_produce(ioim->bfa, ioim->reqq);
return BFA_TRUE;
}
/*
* Call to resume any I/O requests waiting for room in request queue.
*/
static void
bfa_ioim_qresume(void *cbarg)
{
struct bfa_ioim_s *ioim = cbarg;
bfa_stats(ioim->itnim, qresumes);
bfa_sm_send_event(ioim, BFA_IOIM_SM_QRESUME);
}
static void
bfa_ioim_notify_cleanup(struct bfa_ioim_s *ioim)
{
/*
* Move IO from itnim queue to fcpim global queue since itnim will be
* freed.
*/
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &ioim->fcpim->ioim_comp_q);
if (!ioim->iosp->tskim) {
if (ioim->fcpim->delay_comp && ioim->itnim->iotov_active) {
bfa_cb_dequeue(&ioim->hcb_qe);
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &ioim->itnim->delay_comp_q);
}
bfa_itnim_iodone(ioim->itnim);
} else
bfa_wc_down(&ioim->iosp->tskim->wc);
}
static bfa_boolean_t
bfa_ioim_is_abortable(struct bfa_ioim_s *ioim)
{
if ((bfa_sm_cmp_state(ioim, bfa_ioim_sm_uninit) &&
(!bfa_q_is_on_q(&ioim->itnim->pending_q, ioim))) ||
(bfa_sm_cmp_state(ioim, bfa_ioim_sm_abort)) ||
(bfa_sm_cmp_state(ioim, bfa_ioim_sm_abort_qfull)) ||
(bfa_sm_cmp_state(ioim, bfa_ioim_sm_hcb)) ||
(bfa_sm_cmp_state(ioim, bfa_ioim_sm_hcb_free)) ||
(bfa_sm_cmp_state(ioim, bfa_ioim_sm_resfree)))
return BFA_FALSE;
return BFA_TRUE;
}
void
bfa_ioim_delayed_comp(struct bfa_ioim_s *ioim, bfa_boolean_t iotov)
{
/*
* If path tov timer expired, failback with PATHTOV status - these
* IO requests are not normally retried by IO stack.
*
* Otherwise device cameback online and fail it with normal failed
* status so that IO stack retries these failed IO requests.
*/
if (iotov)
ioim->io_cbfn = __bfa_cb_ioim_pathtov;
else {
ioim->io_cbfn = __bfa_cb_ioim_failed;
bfa_stats(ioim->itnim, iocom_nexus_abort);
}
bfa_cb_queue(ioim->bfa, &ioim->hcb_qe, ioim->io_cbfn, ioim);
/*
* Move IO to fcpim global queue since itnim will be
* freed.
*/
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &ioim->fcpim->ioim_comp_q);
}
/*
* Memory allocation and initialization.
*/
void
bfa_ioim_attach(struct bfa_fcpim_mod_s *fcpim, struct bfa_meminfo_s *minfo)
{
struct bfa_ioim_s *ioim;
struct bfa_ioim_sp_s *iosp;
u16 i;
u8 *snsinfo;
u32 snsbufsz;
/*
* claim memory first
*/
ioim = (struct bfa_ioim_s *) bfa_meminfo_kva(minfo);
fcpim->ioim_arr = ioim;
bfa_meminfo_kva(minfo) = (u8 *) (ioim + fcpim->num_ioim_reqs);
iosp = (struct bfa_ioim_sp_s *) bfa_meminfo_kva(minfo);
fcpim->ioim_sp_arr = iosp;
bfa_meminfo_kva(minfo) = (u8 *) (iosp + fcpim->num_ioim_reqs);
/*
* Claim DMA memory for per IO sense data.
*/
snsbufsz = fcpim->num_ioim_reqs * BFI_IOIM_SNSLEN;
fcpim->snsbase.pa = bfa_meminfo_dma_phys(minfo);
bfa_meminfo_dma_phys(minfo) += snsbufsz;
fcpim->snsbase.kva = bfa_meminfo_dma_virt(minfo);
bfa_meminfo_dma_virt(minfo) += snsbufsz;
snsinfo = fcpim->snsbase.kva;
bfa_iocfc_set_snsbase(fcpim->bfa, fcpim->snsbase.pa);
/*
* Initialize ioim free queues
*/
INIT_LIST_HEAD(&fcpim->ioim_free_q);
INIT_LIST_HEAD(&fcpim->ioim_resfree_q);
INIT_LIST_HEAD(&fcpim->ioim_comp_q);
for (i = 0; i < fcpim->num_ioim_reqs;
i++, ioim++, iosp++, snsinfo += BFI_IOIM_SNSLEN) {
/*
* initialize IOIM
*/
memset(ioim, 0, sizeof(struct bfa_ioim_s));
ioim->iotag = i;
ioim->bfa = fcpim->bfa;
ioim->fcpim = fcpim;
ioim->iosp = iosp;
iosp->snsinfo = snsinfo;
INIT_LIST_HEAD(&ioim->sgpg_q);
bfa_reqq_winit(&ioim->iosp->reqq_wait,
bfa_ioim_qresume, ioim);
bfa_sgpg_winit(&ioim->iosp->sgpg_wqe,
bfa_ioim_sgpg_alloced, ioim);
bfa_sm_set_state(ioim, bfa_ioim_sm_uninit);
list_add_tail(&ioim->qe, &fcpim->ioim_free_q);
}
}
void
bfa_ioim_isr(struct bfa_s *bfa, struct bfi_msg_s *m)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfi_ioim_rsp_s *rsp = (struct bfi_ioim_rsp_s *) m;
struct bfa_ioim_s *ioim;
u16 iotag;
enum bfa_ioim_event evt = BFA_IOIM_SM_COMP;
iotag = be16_to_cpu(rsp->io_tag);
ioim = BFA_IOIM_FROM_TAG(fcpim, iotag);
WARN_ON(ioim->iotag != iotag);
bfa_trc(ioim->bfa, ioim->iotag);
bfa_trc(ioim->bfa, rsp->io_status);
bfa_trc(ioim->bfa, rsp->reuse_io_tag);
if (bfa_sm_cmp_state(ioim, bfa_ioim_sm_active))
ioim->iosp->comp_rspmsg = *m;
switch (rsp->io_status) {
case BFI_IOIM_STS_OK:
bfa_stats(ioim->itnim, iocomp_ok);
if (rsp->reuse_io_tag == 0)
evt = BFA_IOIM_SM_DONE;
else
evt = BFA_IOIM_SM_COMP;
break;
case BFI_IOIM_STS_TIMEDOUT:
bfa_stats(ioim->itnim, iocomp_timedout);
case BFI_IOIM_STS_ABORTED:
rsp->io_status = BFI_IOIM_STS_ABORTED;
bfa_stats(ioim->itnim, iocomp_aborted);
if (rsp->reuse_io_tag == 0)
evt = BFA_IOIM_SM_DONE;
else
evt = BFA_IOIM_SM_COMP;
break;
case BFI_IOIM_STS_PROTO_ERR:
bfa_stats(ioim->itnim, iocom_proto_err);
WARN_ON(!rsp->reuse_io_tag);
evt = BFA_IOIM_SM_COMP;
break;
case BFI_IOIM_STS_SQER_NEEDED:
bfa_stats(ioim->itnim, iocom_sqer_needed);
WARN_ON(rsp->reuse_io_tag != 0);
evt = BFA_IOIM_SM_SQRETRY;
break;
case BFI_IOIM_STS_RES_FREE:
bfa_stats(ioim->itnim, iocom_res_free);
evt = BFA_IOIM_SM_FREE;
break;
case BFI_IOIM_STS_HOST_ABORTED:
bfa_stats(ioim->itnim, iocom_hostabrts);
if (rsp->abort_tag != ioim->abort_tag) {
bfa_trc(ioim->bfa, rsp->abort_tag);
bfa_trc(ioim->bfa, ioim->abort_tag);
return;
}
if (rsp->reuse_io_tag)
evt = BFA_IOIM_SM_ABORT_COMP;
else
evt = BFA_IOIM_SM_ABORT_DONE;
break;
case BFI_IOIM_STS_UTAG:
bfa_stats(ioim->itnim, iocom_utags);
evt = BFA_IOIM_SM_COMP_UTAG;
break;
default:
WARN_ON(1);
}
bfa_sm_send_event(ioim, evt);
}
void
bfa_ioim_good_comp_isr(struct bfa_s *bfa, struct bfi_msg_s *m)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfi_ioim_rsp_s *rsp = (struct bfi_ioim_rsp_s *) m;
struct bfa_ioim_s *ioim;
u16 iotag;
iotag = be16_to_cpu(rsp->io_tag);
ioim = BFA_IOIM_FROM_TAG(fcpim, iotag);
WARN_ON(BFA_IOIM_TAG_2_ID(ioim->iotag) != iotag);
bfa_ioim_cb_profile_comp(fcpim, ioim);
bfa_sm_send_event(ioim, BFA_IOIM_SM_COMP_GOOD);
}
/*
* Called by itnim to clean up IO while going offline.
*/
void
bfa_ioim_cleanup(struct bfa_ioim_s *ioim)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_stats(ioim->itnim, io_cleanups);
ioim->iosp->tskim = NULL;
bfa_sm_send_event(ioim, BFA_IOIM_SM_CLEANUP);
}
void
bfa_ioim_cleanup_tm(struct bfa_ioim_s *ioim, struct bfa_tskim_s *tskim)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_stats(ioim->itnim, io_tmaborts);
ioim->iosp->tskim = tskim;
bfa_sm_send_event(ioim, BFA_IOIM_SM_CLEANUP);
}
/*
* IOC failure handling.
*/
void
bfa_ioim_iocdisable(struct bfa_ioim_s *ioim)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_stats(ioim->itnim, io_iocdowns);
bfa_sm_send_event(ioim, BFA_IOIM_SM_HWFAIL);
}
/*
* IO offline TOV popped. Fail the pending IO.
*/
void
bfa_ioim_tov(struct bfa_ioim_s *ioim)
{
bfa_trc(ioim->bfa, ioim->iotag);
bfa_sm_send_event(ioim, BFA_IOIM_SM_IOTOV);
}
/*
* Allocate IOIM resource for initiator mode I/O request.
*/
struct bfa_ioim_s *
bfa_ioim_alloc(struct bfa_s *bfa, struct bfad_ioim_s *dio,
struct bfa_itnim_s *itnim, u16 nsges)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfa_ioim_s *ioim;
/*
* alocate IOIM resource
*/
bfa_q_deq(&fcpim->ioim_free_q, &ioim);
if (!ioim) {
bfa_stats(itnim, no_iotags);
return NULL;
}
ioim->dio = dio;
ioim->itnim = itnim;
ioim->nsges = nsges;
ioim->nsgpgs = 0;
bfa_stats(itnim, total_ios);
fcpim->ios_active++;
list_add_tail(&ioim->qe, &itnim->io_q);
return ioim;
}
void
bfa_ioim_free(struct bfa_ioim_s *ioim)
{
struct bfa_fcpim_mod_s *fcpim = ioim->fcpim;
if (ioim->nsgpgs > 0)
bfa_sgpg_mfree(ioim->bfa, &ioim->sgpg_q, ioim->nsgpgs);
bfa_stats(ioim->itnim, io_comps);
fcpim->ios_active--;
ioim->iotag &= BFA_IOIM_IOTAG_MASK;
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &fcpim->ioim_free_q);
}
void
bfa_ioim_start(struct bfa_ioim_s *ioim)
{
bfa_ioim_cb_profile_start(ioim->fcpim, ioim);
/*
* Obtain the queue over which this request has to be issued
*/
ioim->reqq = bfa_fcpim_ioredirect_enabled(ioim->bfa) ?
BFA_FALSE : bfa_itnim_get_reqq(ioim);
bfa_sm_send_event(ioim, BFA_IOIM_SM_START);
}
/*
* Driver I/O abort request.
*/
bfa_status_t
bfa_ioim_abort(struct bfa_ioim_s *ioim)
{
bfa_trc(ioim->bfa, ioim->iotag);
if (!bfa_ioim_is_abortable(ioim))
return BFA_STATUS_FAILED;
bfa_stats(ioim->itnim, io_aborts);
bfa_sm_send_event(ioim, BFA_IOIM_SM_ABORT);
return BFA_STATUS_OK;
}
/*
* BFA TSKIM state machine functions
*/
/*
* Task management command beginning state.
*/
static void
bfa_tskim_sm_uninit(struct bfa_tskim_s *tskim, enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_START:
bfa_sm_set_state(tskim, bfa_tskim_sm_active);
bfa_tskim_gather_ios(tskim);
/*
* If device is offline, do not send TM on wire. Just cleanup
* any pending IO requests and complete TM request.
*/
if (!bfa_itnim_is_online(tskim->itnim)) {
bfa_sm_set_state(tskim, bfa_tskim_sm_iocleanup);
tskim->tsk_status = BFI_TSKIM_STS_OK;
bfa_tskim_cleanup_ios(tskim);
return;
}
if (!bfa_tskim_send(tskim)) {
bfa_sm_set_state(tskim, bfa_tskim_sm_qfull);
bfa_stats(tskim->itnim, tm_qwait);
bfa_reqq_wait(tskim->bfa, tskim->itnim->reqq,
&tskim->reqq_wait);
}
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
/*
* TM command is active, awaiting completion from firmware to
* cleanup IO requests in TM scope.
*/
static void
bfa_tskim_sm_active(struct bfa_tskim_s *tskim, enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_DONE:
bfa_sm_set_state(tskim, bfa_tskim_sm_iocleanup);
bfa_tskim_cleanup_ios(tskim);
break;
case BFA_TSKIM_SM_CLEANUP:
bfa_sm_set_state(tskim, bfa_tskim_sm_cleanup);
if (!bfa_tskim_send_abort(tskim)) {
bfa_sm_set_state(tskim, bfa_tskim_sm_cleanup_qfull);
bfa_stats(tskim->itnim, tm_qwait);
bfa_reqq_wait(tskim->bfa, tskim->itnim->reqq,
&tskim->reqq_wait);
}
break;
case BFA_TSKIM_SM_HWFAIL:
bfa_sm_set_state(tskim, bfa_tskim_sm_hcb);
bfa_tskim_iocdisable_ios(tskim);
bfa_tskim_qcomp(tskim, __bfa_cb_tskim_failed);
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
/*
* An active TM is being cleaned up since ITN is offline. Awaiting cleanup
* completion event from firmware.
*/
static void
bfa_tskim_sm_cleanup(struct bfa_tskim_s *tskim, enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_DONE:
/*
* Ignore and wait for ABORT completion from firmware.
*/
break;
case BFA_TSKIM_SM_CLEANUP_DONE:
bfa_sm_set_state(tskim, bfa_tskim_sm_iocleanup);
bfa_tskim_cleanup_ios(tskim);
break;
case BFA_TSKIM_SM_HWFAIL:
bfa_sm_set_state(tskim, bfa_tskim_sm_hcb);
bfa_tskim_iocdisable_ios(tskim);
bfa_tskim_qcomp(tskim, __bfa_cb_tskim_failed);
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
static void
bfa_tskim_sm_iocleanup(struct bfa_tskim_s *tskim, enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_IOS_DONE:
bfa_sm_set_state(tskim, bfa_tskim_sm_hcb);
bfa_tskim_qcomp(tskim, __bfa_cb_tskim_done);
break;
case BFA_TSKIM_SM_CLEANUP:
/*
* Ignore, TM command completed on wire.
* Notify TM conmpletion on IO cleanup completion.
*/
break;
case BFA_TSKIM_SM_HWFAIL:
bfa_sm_set_state(tskim, bfa_tskim_sm_hcb);
bfa_tskim_iocdisable_ios(tskim);
bfa_tskim_qcomp(tskim, __bfa_cb_tskim_failed);
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
/*
* Task management command is waiting for room in request CQ
*/
static void
bfa_tskim_sm_qfull(struct bfa_tskim_s *tskim, enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_QRESUME:
bfa_sm_set_state(tskim, bfa_tskim_sm_active);
bfa_tskim_send(tskim);
break;
case BFA_TSKIM_SM_CLEANUP:
/*
* No need to send TM on wire since ITN is offline.
*/
bfa_sm_set_state(tskim, bfa_tskim_sm_iocleanup);
bfa_reqq_wcancel(&tskim->reqq_wait);
bfa_tskim_cleanup_ios(tskim);
break;
case BFA_TSKIM_SM_HWFAIL:
bfa_sm_set_state(tskim, bfa_tskim_sm_hcb);
bfa_reqq_wcancel(&tskim->reqq_wait);
bfa_tskim_iocdisable_ios(tskim);
bfa_tskim_qcomp(tskim, __bfa_cb_tskim_failed);
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
/*
* Task management command is active, awaiting for room in request CQ
* to send clean up request.
*/
static void
bfa_tskim_sm_cleanup_qfull(struct bfa_tskim_s *tskim,
enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_DONE:
bfa_reqq_wcancel(&tskim->reqq_wait);
/*
* Fall through !!!
*/
case BFA_TSKIM_SM_QRESUME:
bfa_sm_set_state(tskim, bfa_tskim_sm_cleanup);
bfa_tskim_send_abort(tskim);
break;
case BFA_TSKIM_SM_HWFAIL:
bfa_sm_set_state(tskim, bfa_tskim_sm_hcb);
bfa_reqq_wcancel(&tskim->reqq_wait);
bfa_tskim_iocdisable_ios(tskim);
bfa_tskim_qcomp(tskim, __bfa_cb_tskim_failed);
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
/*
* BFA callback is pending
*/
static void
bfa_tskim_sm_hcb(struct bfa_tskim_s *tskim, enum bfa_tskim_event event)
{
bfa_trc(tskim->bfa, event);
switch (event) {
case BFA_TSKIM_SM_HCB:
bfa_sm_set_state(tskim, bfa_tskim_sm_uninit);
bfa_tskim_free(tskim);
break;
case BFA_TSKIM_SM_CLEANUP:
bfa_tskim_notify_comp(tskim);
break;
case BFA_TSKIM_SM_HWFAIL:
break;
default:
bfa_sm_fault(tskim->bfa, event);
}
}
static void
__bfa_cb_tskim_done(void *cbarg, bfa_boolean_t complete)
{
struct bfa_tskim_s *tskim = cbarg;
if (!complete) {
bfa_sm_send_event(tskim, BFA_TSKIM_SM_HCB);
return;
}
bfa_stats(tskim->itnim, tm_success);
bfa_cb_tskim_done(tskim->bfa->bfad, tskim->dtsk, tskim->tsk_status);
}
static void
__bfa_cb_tskim_failed(void *cbarg, bfa_boolean_t complete)
{
struct bfa_tskim_s *tskim = cbarg;
if (!complete) {
bfa_sm_send_event(tskim, BFA_TSKIM_SM_HCB);
return;
}
bfa_stats(tskim->itnim, tm_failures);
bfa_cb_tskim_done(tskim->bfa->bfad, tskim->dtsk,
BFI_TSKIM_STS_FAILED);
}
static bfa_boolean_t
bfa_tskim_match_scope(struct bfa_tskim_s *tskim, struct scsi_lun lun)
{
switch (tskim->tm_cmnd) {
case FCP_TM_TARGET_RESET:
return BFA_TRUE;
case FCP_TM_ABORT_TASK_SET:
case FCP_TM_CLEAR_TASK_SET:
case FCP_TM_LUN_RESET:
case FCP_TM_CLEAR_ACA:
return !memcmp(&tskim->lun, &lun, sizeof(lun));
default:
WARN_ON(1);
}
return BFA_FALSE;
}
/*
* Gather affected IO requests and task management commands.
*/
static void
bfa_tskim_gather_ios(struct bfa_tskim_s *tskim)
{
struct bfa_itnim_s *itnim = tskim->itnim;
struct bfa_ioim_s *ioim;
struct list_head *qe, *qen;
struct scsi_cmnd *cmnd;
struct scsi_lun scsilun;
INIT_LIST_HEAD(&tskim->io_q);
/*
* Gather any active IO requests first.
*/
list_for_each_safe(qe, qen, &itnim->io_q) {
ioim = (struct bfa_ioim_s *) qe;
cmnd = (struct scsi_cmnd *) ioim->dio;
int_to_scsilun(cmnd->device->lun, &scsilun);
if (bfa_tskim_match_scope(tskim, scsilun)) {
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &tskim->io_q);
}
}
/*
* Failback any pending IO requests immediately.
*/
list_for_each_safe(qe, qen, &itnim->pending_q) {
ioim = (struct bfa_ioim_s *) qe;
cmnd = (struct scsi_cmnd *) ioim->dio;
int_to_scsilun(cmnd->device->lun, &scsilun);
if (bfa_tskim_match_scope(tskim, scsilun)) {
list_del(&ioim->qe);
list_add_tail(&ioim->qe, &ioim->fcpim->ioim_comp_q);
bfa_ioim_tov(ioim);
}
}
}
/*
* IO cleanup completion
*/
static void
bfa_tskim_cleanp_comp(void *tskim_cbarg)
{
struct bfa_tskim_s *tskim = tskim_cbarg;
bfa_stats(tskim->itnim, tm_io_comps);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_IOS_DONE);
}
/*
* Gather affected IO requests and task management commands.
*/
static void
bfa_tskim_cleanup_ios(struct bfa_tskim_s *tskim)
{
struct bfa_ioim_s *ioim;
struct list_head *qe, *qen;
bfa_wc_init(&tskim->wc, bfa_tskim_cleanp_comp, tskim);
list_for_each_safe(qe, qen, &tskim->io_q) {
ioim = (struct bfa_ioim_s *) qe;
bfa_wc_up(&tskim->wc);
bfa_ioim_cleanup_tm(ioim, tskim);
}
bfa_wc_wait(&tskim->wc);
}
/*
* Send task management request to firmware.
*/
static bfa_boolean_t
bfa_tskim_send(struct bfa_tskim_s *tskim)
{
struct bfa_itnim_s *itnim = tskim->itnim;
struct bfi_tskim_req_s *m;
/*
* check for room in queue to send request now
*/
m = bfa_reqq_next(tskim->bfa, itnim->reqq);
if (!m)
return BFA_FALSE;
/*
* build i/o request message next
*/
bfi_h2i_set(m->mh, BFI_MC_TSKIM, BFI_TSKIM_H2I_TM_REQ,
bfa_lpuid(tskim->bfa));
m->tsk_tag = cpu_to_be16(tskim->tsk_tag);
m->itn_fhdl = tskim->itnim->rport->fw_handle;
m->t_secs = tskim->tsecs;
m->lun = tskim->lun;
m->tm_flags = tskim->tm_cmnd;
/*
* queue I/O message to firmware
*/
bfa_reqq_produce(tskim->bfa, itnim->reqq);
return BFA_TRUE;
}
/*
* Send abort request to cleanup an active TM to firmware.
*/
static bfa_boolean_t
bfa_tskim_send_abort(struct bfa_tskim_s *tskim)
{
struct bfa_itnim_s *itnim = tskim->itnim;
struct bfi_tskim_abortreq_s *m;
/*
* check for room in queue to send request now
*/
m = bfa_reqq_next(tskim->bfa, itnim->reqq);
if (!m)
return BFA_FALSE;
/*
* build i/o request message next
*/
bfi_h2i_set(m->mh, BFI_MC_TSKIM, BFI_TSKIM_H2I_ABORT_REQ,
bfa_lpuid(tskim->bfa));
m->tsk_tag = cpu_to_be16(tskim->tsk_tag);
/*
* queue I/O message to firmware
*/
bfa_reqq_produce(tskim->bfa, itnim->reqq);
return BFA_TRUE;
}
/*
* Call to resume task management cmnd waiting for room in request queue.
*/
static void
bfa_tskim_qresume(void *cbarg)
{
struct bfa_tskim_s *tskim = cbarg;
bfa_stats(tskim->itnim, tm_qresumes);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_QRESUME);
}
/*
* Cleanup IOs associated with a task mangement command on IOC failures.
*/
static void
bfa_tskim_iocdisable_ios(struct bfa_tskim_s *tskim)
{
struct bfa_ioim_s *ioim;
struct list_head *qe, *qen;
list_for_each_safe(qe, qen, &tskim->io_q) {
ioim = (struct bfa_ioim_s *) qe;
bfa_ioim_iocdisable(ioim);
}
}
/*
* Notification on completions from related ioim.
*/
void
bfa_tskim_iodone(struct bfa_tskim_s *tskim)
{
bfa_wc_down(&tskim->wc);
}
/*
* Handle IOC h/w failure notification from itnim.
*/
void
bfa_tskim_iocdisable(struct bfa_tskim_s *tskim)
{
tskim->notify = BFA_FALSE;
bfa_stats(tskim->itnim, tm_iocdowns);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_HWFAIL);
}
/*
* Cleanup TM command and associated IOs as part of ITNIM offline.
*/
void
bfa_tskim_cleanup(struct bfa_tskim_s *tskim)
{
tskim->notify = BFA_TRUE;
bfa_stats(tskim->itnim, tm_cleanups);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_CLEANUP);
}
/*
* Memory allocation and initialization.
*/
void
bfa_tskim_attach(struct bfa_fcpim_mod_s *fcpim, struct bfa_meminfo_s *minfo)
{
struct bfa_tskim_s *tskim;
u16 i;
INIT_LIST_HEAD(&fcpim->tskim_free_q);
tskim = (struct bfa_tskim_s *) bfa_meminfo_kva(minfo);
fcpim->tskim_arr = tskim;
for (i = 0; i < fcpim->num_tskim_reqs; i++, tskim++) {
/*
* initialize TSKIM
*/
memset(tskim, 0, sizeof(struct bfa_tskim_s));
tskim->tsk_tag = i;
tskim->bfa = fcpim->bfa;
tskim->fcpim = fcpim;
tskim->notify = BFA_FALSE;
bfa_reqq_winit(&tskim->reqq_wait, bfa_tskim_qresume,
tskim);
bfa_sm_set_state(tskim, bfa_tskim_sm_uninit);
list_add_tail(&tskim->qe, &fcpim->tskim_free_q);
}
bfa_meminfo_kva(minfo) = (u8 *) tskim;
}
void
bfa_tskim_isr(struct bfa_s *bfa, struct bfi_msg_s *m)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfi_tskim_rsp_s *rsp = (struct bfi_tskim_rsp_s *) m;
struct bfa_tskim_s *tskim;
u16 tsk_tag = be16_to_cpu(rsp->tsk_tag);
tskim = BFA_TSKIM_FROM_TAG(fcpim, tsk_tag);
WARN_ON(tskim->tsk_tag != tsk_tag);
tskim->tsk_status = rsp->tsk_status;
/*
* Firmware sends BFI_TSKIM_STS_ABORTED status for abort
* requests. All other statuses are for normal completions.
*/
if (rsp->tsk_status == BFI_TSKIM_STS_ABORTED) {
bfa_stats(tskim->itnim, tm_cleanup_comps);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_CLEANUP_DONE);
} else {
bfa_stats(tskim->itnim, tm_fw_rsps);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_DONE);
}
}
struct bfa_tskim_s *
bfa_tskim_alloc(struct bfa_s *bfa, struct bfad_tskim_s *dtsk)
{
struct bfa_fcpim_mod_s *fcpim = BFA_FCPIM_MOD(bfa);
struct bfa_tskim_s *tskim;
bfa_q_deq(&fcpim->tskim_free_q, &tskim);
if (tskim)
tskim->dtsk = dtsk;
return tskim;
}
void
bfa_tskim_free(struct bfa_tskim_s *tskim)
{
WARN_ON(!bfa_q_is_on_q_func(&tskim->itnim->tsk_q, &tskim->qe));
list_del(&tskim->qe);
list_add_tail(&tskim->qe, &tskim->fcpim->tskim_free_q);
}
/*
* Start a task management command.
*
* @param[in] tskim BFA task management command instance
* @param[in] itnim i-t nexus for the task management command
* @param[in] lun lun, if applicable
* @param[in] tm_cmnd Task management command code.
* @param[in] t_secs Timeout in seconds
*
* @return None.
*/
void
bfa_tskim_start(struct bfa_tskim_s *tskim, struct bfa_itnim_s *itnim,
struct scsi_lun lun,
enum fcp_tm_cmnd tm_cmnd, u8 tsecs)
{
tskim->itnim = itnim;
tskim->lun = lun;
tskim->tm_cmnd = tm_cmnd;
tskim->tsecs = tsecs;
tskim->notify = BFA_FALSE;
bfa_stats(itnim, tm_cmnds);
list_add_tail(&tskim->qe, &itnim->tsk_q);
bfa_sm_send_event(tskim, BFA_TSKIM_SM_START);
}
| gpl-2.0 |
Krabappel2548/kernel_msm8x60 | drivers/infiniband/hw/mthca/mthca_mad.c | 2643 | 10194 | /*
* Copyright (c) 2004 Topspin Communications. All rights reserved.
* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/string.h>
#include <linux/slab.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_mad.h>
#include <rdma/ib_smi.h>
#include "mthca_dev.h"
#include "mthca_cmd.h"
enum {
MTHCA_VENDOR_CLASS1 = 0x9,
MTHCA_VENDOR_CLASS2 = 0xa
};
static int mthca_update_rate(struct mthca_dev *dev, u8 port_num)
{
struct ib_port_attr *tprops = NULL;
int ret;
tprops = kmalloc(sizeof *tprops, GFP_KERNEL);
if (!tprops)
return -ENOMEM;
ret = ib_query_port(&dev->ib_dev, port_num, tprops);
if (ret) {
printk(KERN_WARNING "ib_query_port failed (%d) for %s port %d\n",
ret, dev->ib_dev.name, port_num);
goto out;
}
dev->rate[port_num - 1] = tprops->active_speed *
ib_width_enum_to_int(tprops->active_width);
out:
kfree(tprops);
return ret;
}
static void update_sm_ah(struct mthca_dev *dev,
u8 port_num, u16 lid, u8 sl)
{
struct ib_ah *new_ah;
struct ib_ah_attr ah_attr;
unsigned long flags;
if (!dev->send_agent[port_num - 1][0])
return;
memset(&ah_attr, 0, sizeof ah_attr);
ah_attr.dlid = lid;
ah_attr.sl = sl;
ah_attr.port_num = port_num;
new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd,
&ah_attr);
if (IS_ERR(new_ah))
return;
spin_lock_irqsave(&dev->sm_lock, flags);
if (dev->sm_ah[port_num - 1])
ib_destroy_ah(dev->sm_ah[port_num - 1]);
dev->sm_ah[port_num - 1] = new_ah;
spin_unlock_irqrestore(&dev->sm_lock, flags);
}
/*
* Snoop SM MADs for port info and P_Key table sets, so we can
* synthesize LID change and P_Key change events.
*/
static void smp_snoop(struct ib_device *ibdev,
u8 port_num,
struct ib_mad *mad,
u16 prev_lid)
{
struct ib_event event;
if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
mad->mad_hdr.method == IB_MGMT_METHOD_SET) {
if (mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO) {
struct ib_port_info *pinfo =
(struct ib_port_info *) ((struct ib_smp *) mad)->data;
u16 lid = be16_to_cpu(pinfo->lid);
mthca_update_rate(to_mdev(ibdev), port_num);
update_sm_ah(to_mdev(ibdev), port_num,
be16_to_cpu(pinfo->sm_lid),
pinfo->neighbormtu_mastersmsl & 0xf);
event.device = ibdev;
event.element.port_num = port_num;
if (pinfo->clientrereg_resv_subnetto & 0x80) {
event.event = IB_EVENT_CLIENT_REREGISTER;
ib_dispatch_event(&event);
}
if (prev_lid != lid) {
event.event = IB_EVENT_LID_CHANGE;
ib_dispatch_event(&event);
}
}
if (mad->mad_hdr.attr_id == IB_SMP_ATTR_PKEY_TABLE) {
event.device = ibdev;
event.event = IB_EVENT_PKEY_CHANGE;
event.element.port_num = port_num;
ib_dispatch_event(&event);
}
}
}
static void node_desc_override(struct ib_device *dev,
struct ib_mad *mad)
{
if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP &&
mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) {
mutex_lock(&to_mdev(dev)->cap_mask_mutex);
memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 64);
mutex_unlock(&to_mdev(dev)->cap_mask_mutex);
}
}
static void forward_trap(struct mthca_dev *dev,
u8 port_num,
struct ib_mad *mad)
{
int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED;
struct ib_mad_send_buf *send_buf;
struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn];
int ret;
unsigned long flags;
if (agent) {
send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
IB_MGMT_MAD_DATA, GFP_ATOMIC);
if (IS_ERR(send_buf))
return;
/*
* We rely here on the fact that MLX QPs don't use the
* address handle after the send is posted (this is
* wrong following the IB spec strictly, but we know
* it's OK for our devices).
*/
spin_lock_irqsave(&dev->sm_lock, flags);
memcpy(send_buf->mad, mad, sizeof *mad);
if ((send_buf->ah = dev->sm_ah[port_num - 1]))
ret = ib_post_send_mad(send_buf, NULL);
else
ret = -EINVAL;
spin_unlock_irqrestore(&dev->sm_lock, flags);
if (ret)
ib_free_send_mad(send_buf);
}
}
int mthca_process_mad(struct ib_device *ibdev,
int mad_flags,
u8 port_num,
struct ib_wc *in_wc,
struct ib_grh *in_grh,
struct ib_mad *in_mad,
struct ib_mad *out_mad)
{
int err;
u8 status;
u16 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE);
u16 prev_lid = 0;
struct ib_port_attr pattr;
/* Forward locally generated traps to the SM */
if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP &&
slid == 0) {
forward_trap(to_mdev(ibdev), port_num, in_mad);
return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
}
/*
* Only handle SM gets, sets and trap represses for SM class
*
* Only handle PMA and Mellanox vendor-specific class gets and
* sets for other classes.
*/
if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
return IB_MAD_RESULT_SUCCESS;
/*
* Don't process SMInfo queries or vendor-specific
* MADs -- the SMA can't handle them.
*/
if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO ||
((in_mad->mad_hdr.attr_id & IB_SMP_ATTR_VENDOR_MASK) ==
IB_SMP_ATTR_VENDOR_MASK))
return IB_MAD_RESULT_SUCCESS;
} else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
in_mad->mad_hdr.mgmt_class == MTHCA_VENDOR_CLASS1 ||
in_mad->mad_hdr.mgmt_class == MTHCA_VENDOR_CLASS2) {
if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
return IB_MAD_RESULT_SUCCESS;
} else
return IB_MAD_RESULT_SUCCESS;
if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
in_mad->mad_hdr.method == IB_MGMT_METHOD_SET &&
in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO &&
!ib_query_port(ibdev, port_num, &pattr))
prev_lid = pattr.lid;
err = mthca_MAD_IFC(to_mdev(ibdev),
mad_flags & IB_MAD_IGNORE_MKEY,
mad_flags & IB_MAD_IGNORE_BKEY,
port_num, in_wc, in_grh, in_mad, out_mad,
&status);
if (err) {
mthca_err(to_mdev(ibdev), "MAD_IFC failed\n");
return IB_MAD_RESULT_FAILURE;
}
if (status == MTHCA_CMD_STAT_BAD_PKT)
return IB_MAD_RESULT_SUCCESS;
if (status) {
mthca_err(to_mdev(ibdev), "MAD_IFC returned status %02x\n",
status);
return IB_MAD_RESULT_FAILURE;
}
if (!out_mad->mad_hdr.status) {
smp_snoop(ibdev, port_num, in_mad, prev_lid);
node_desc_override(ibdev, out_mad);
}
/* set return bit in status of directed route responses */
if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
/* no response for trap repress */
return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
}
static void send_handler(struct ib_mad_agent *agent,
struct ib_mad_send_wc *mad_send_wc)
{
ib_free_send_mad(mad_send_wc->send_buf);
}
int mthca_create_agents(struct mthca_dev *dev)
{
struct ib_mad_agent *agent;
int p, q;
int ret;
spin_lock_init(&dev->sm_lock);
for (p = 0; p < dev->limits.num_ports; ++p)
for (q = 0; q <= 1; ++q) {
agent = ib_register_mad_agent(&dev->ib_dev, p + 1,
q ? IB_QPT_GSI : IB_QPT_SMI,
NULL, 0, send_handler,
NULL, NULL);
if (IS_ERR(agent)) {
ret = PTR_ERR(agent);
goto err;
}
dev->send_agent[p][q] = agent;
}
for (p = 1; p <= dev->limits.num_ports; ++p) {
ret = mthca_update_rate(dev, p);
if (ret) {
mthca_err(dev, "Failed to obtain port %d rate."
" aborting.\n", p);
goto err;
}
}
return 0;
err:
for (p = 0; p < dev->limits.num_ports; ++p)
for (q = 0; q <= 1; ++q)
if (dev->send_agent[p][q])
ib_unregister_mad_agent(dev->send_agent[p][q]);
return ret;
}
void mthca_free_agents(struct mthca_dev *dev)
{
struct ib_mad_agent *agent;
int p, q;
for (p = 0; p < dev->limits.num_ports; ++p) {
for (q = 0; q <= 1; ++q) {
agent = dev->send_agent[p][q];
dev->send_agent[p][q] = NULL;
ib_unregister_mad_agent(agent);
}
if (dev->sm_ah[p])
ib_destroy_ah(dev->sm_ah[p]);
}
}
| gpl-2.0 |
iodak/p920-ICS-kernel | arch/arm/mm/mmap.c | 2899 | 4259 | /*
* linux/arch/arm/mm/mmap.c
*/
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/shm.h>
#include <linux/sched.h>
#include <linux/io.h>
#include <linux/personality.h>
#include <linux/random.h>
#include <asm/cputype.h>
#include <asm/system.h>
#define COLOUR_ALIGN(addr,pgoff) \
((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
(((pgoff)<<PAGE_SHIFT) & (SHMLBA-1)))
/*
* We need to ensure that shared mappings are correctly aligned to
* avoid aliasing issues with VIPT caches. We need to ensure that
* a specific page of an object is always mapped at a multiple of
* SHMLBA bytes.
*
* We unconditionally provide this function for all cases, however
* in the VIVT case, we optimise out the alignment rules.
*/
unsigned long
arch_get_unmapped_area(struct file *filp, unsigned long addr,
unsigned long len, unsigned long pgoff, unsigned long flags)
{
struct mm_struct *mm = current->mm;
struct vm_area_struct *vma;
unsigned long start_addr;
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
unsigned int cache_type;
int do_align = 0, aliasing = 0;
/*
* We only need to do colour alignment if either the I or D
* caches alias. This is indicated by bits 9 and 21 of the
* cache type register.
*/
cache_type = read_cpuid_cachetype();
if (cache_type != read_cpuid_id()) {
aliasing = (cache_type | cache_type >> 12) & (1 << 11);
if (aliasing)
do_align = filp || flags & MAP_SHARED;
}
#else
#define do_align 0
#define aliasing 0
#endif
/*
* We enforce the MAP_FIXED case.
*/
if (flags & MAP_FIXED) {
if (aliasing && flags & MAP_SHARED &&
(addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1))
return -EINVAL;
return addr;
}
if (len > TASK_SIZE)
return -ENOMEM;
if (addr) {
if (do_align)
addr = COLOUR_ALIGN(addr, pgoff);
else
addr = PAGE_ALIGN(addr);
vma = find_vma(mm, addr);
if (TASK_SIZE - len >= addr &&
(!vma || addr + len <= vma->vm_start))
return addr;
}
if (len > mm->cached_hole_size) {
start_addr = addr = mm->free_area_cache;
} else {
start_addr = addr = TASK_UNMAPPED_BASE;
mm->cached_hole_size = 0;
}
/* 8 bits of randomness in 20 address space bits */
if ((current->flags & PF_RANDOMIZE) &&
!(current->personality & ADDR_NO_RANDOMIZE))
addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
full_search:
if (do_align)
addr = COLOUR_ALIGN(addr, pgoff);
else
addr = PAGE_ALIGN(addr);
for (vma = find_vma(mm, addr); ; vma = vma->vm_next) {
/* At this point: (!vma || addr < vma->vm_end). */
if (TASK_SIZE - len < addr) {
/*
* Start a new search - just in case we missed
* some holes.
*/
if (start_addr != TASK_UNMAPPED_BASE) {
start_addr = addr = TASK_UNMAPPED_BASE;
mm->cached_hole_size = 0;
goto full_search;
}
return -ENOMEM;
}
if (!vma || addr + len <= vma->vm_start) {
/*
* Remember the place where we stopped the search:
*/
mm->free_area_cache = addr + len;
return addr;
}
if (addr + mm->cached_hole_size < vma->vm_start)
mm->cached_hole_size = vma->vm_start - addr;
addr = vma->vm_end;
if (do_align)
addr = COLOUR_ALIGN(addr, pgoff);
}
}
/*
* You really shouldn't be using read() or write() on /dev/mem. This
* might go away in the future.
*/
int valid_phys_addr_range(unsigned long addr, size_t size)
{
if (addr < PHYS_OFFSET)
return 0;
if (addr + size > __pa(high_memory - 1) + 1)
return 0;
return 1;
}
/*
* We don't use supersection mappings for mmap() on /dev/mem, which
* means that we can't map the memory area above the 4G barrier into
* userspace.
*/
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
{
return !(pfn + (size >> PAGE_SHIFT) > 0x00100000);
}
#ifdef CONFIG_STRICT_DEVMEM
#include <linux/ioport.h>
/*
* devmem_is_allowed() checks to see if /dev/mem access to a certain
* address is valid. The argument is a physical page number.
* We mimic x86 here by disallowing access to system RAM as well as
* device-exclusive MMIO regions. This effectively disable read()/write()
* on /dev/mem.
*/
int devmem_is_allowed(unsigned long pfn)
{
if (iomem_is_exclusive(pfn << PAGE_SHIFT))
return 0;
if (!page_is_ram(pfn))
return 1;
return 0;
}
#endif
| gpl-2.0 |
starbucks2010/N915F_kernel_permissive | arch/arm/mach-omap2/clockdomain.c | 4179 | 37213 | /*
* OMAP2/3/4 clockdomain framework functions
*
* Copyright (C) 2008-2011 Texas Instruments, Inc.
* Copyright (C) 2008-2011 Nokia Corporation
*
* Written by Paul Walmsley and Jouni Högander
* Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/limits.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include "soc.h"
#include "clock.h"
#include "clockdomain.h"
/* clkdm_list contains all registered struct clockdomains */
static LIST_HEAD(clkdm_list);
/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
static struct clkdm_autodep *autodeps;
static struct clkdm_ops *arch_clkdm;
/* Private functions */
static struct clockdomain *_clkdm_lookup(const char *name)
{
struct clockdomain *clkdm, *temp_clkdm;
if (!name)
return NULL;
clkdm = NULL;
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
if (!strcmp(name, temp_clkdm->name)) {
clkdm = temp_clkdm;
break;
}
}
return clkdm;
}
/**
* _clkdm_register - register a clockdomain
* @clkdm: struct clockdomain * to register
*
* Adds a clockdomain to the internal clockdomain list.
* Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
* already registered by the provided name, or 0 upon success.
*/
static int _clkdm_register(struct clockdomain *clkdm)
{
struct powerdomain *pwrdm;
if (!clkdm || !clkdm->name)
return -EINVAL;
pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
if (!pwrdm) {
pr_err("clockdomain: %s: powerdomain %s does not exist\n",
clkdm->name, clkdm->pwrdm.name);
return -EINVAL;
}
clkdm->pwrdm.ptr = pwrdm;
/* Verify that the clockdomain is not already registered */
if (_clkdm_lookup(clkdm->name))
return -EEXIST;
list_add(&clkdm->node, &clkdm_list);
pwrdm_add_clkdm(pwrdm, clkdm);
pr_debug("clockdomain: registered %s\n", clkdm->name);
return 0;
}
/* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */
static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
struct clkdm_dep *deps)
{
struct clkdm_dep *cd;
if (!clkdm || !deps)
return ERR_PTR(-EINVAL);
for (cd = deps; cd->clkdm_name; cd++) {
if (!cd->clkdm && cd->clkdm_name)
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
if (cd->clkdm == clkdm)
break;
}
if (!cd->clkdm_name)
return ERR_PTR(-ENOENT);
return cd;
}
/**
* _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
* @autodep: struct clkdm_autodep * to resolve
*
* Resolve autodep clockdomain names to clockdomain pointers via
* clkdm_lookup() and store the pointers in the autodep structure. An
* "autodep" is a clockdomain sleep/wakeup dependency that is
* automatically added and removed whenever clocks in the associated
* clockdomain are enabled or disabled (respectively) when the
* clockdomain is in hardware-supervised mode. Meant to be called
* once at clockdomain layer initialization, since these should remain
* fixed for a particular architecture. No return value.
*
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
static void _autodep_lookup(struct clkdm_autodep *autodep)
{
struct clockdomain *clkdm;
if (!autodep)
return;
clkdm = clkdm_lookup(autodep->clkdm.name);
if (!clkdm) {
pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
autodep->clkdm.name);
clkdm = ERR_PTR(-ENOENT);
}
autodep->clkdm.ptr = clkdm;
}
/**
* _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
* @clkdm: clockdomain that we are resolving dependencies for
* @clkdm_deps: ptr to array of struct clkdm_deps to resolve
*
* Iterates through @clkdm_deps, looking up the struct clockdomain named by
* clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
* No return value.
*/
static void _resolve_clkdm_deps(struct clockdomain *clkdm,
struct clkdm_dep *clkdm_deps)
{
struct clkdm_dep *cd;
for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
if (cd->clkdm)
continue;
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
clkdm->name, cd->clkdm_name);
}
}
/**
* _clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 (lockless)
* @clkdm1: wake this struct clockdomain * up (dependent)
* @clkdm2: when this struct clockdomain * wakes up (source)
*
* When the clockdomain represented by @clkdm2 wakes up, wake up
* @clkdm1. Implemented in hardware on the OMAP, this feature is
* designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
* Returns -EINVAL if presented with invalid clockdomain pointers,
* -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
* success.
*/
static int _clkdm_add_wkdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
clkdm1->name, clkdm2->name);
return ret;
}
cd->wkdep_usecount++;
if (cd->wkdep_usecount == 1) {
pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
}
return ret;
}
/**
* _clkdm_del_wkdep - remove a wakeup dep from clkdm2 to clkdm1 (lockless)
* @clkdm1: wake this struct clockdomain * up (dependent)
* @clkdm2: when this struct clockdomain * wakes up (source)
*
* Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
* wakes up. Returns -EINVAL if presented with invalid clockdomain
* pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
* 0 upon success.
*/
static int _clkdm_del_wkdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
clkdm1->name, clkdm2->name);
return ret;
}
cd->wkdep_usecount--;
if (cd->wkdep_usecount == 0) {
pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
}
return ret;
}
/**
* _clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 (lockless)
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
* @clkdm2: when this struct clockdomain * is active (source)
*
* Prevent @clkdm1 from automatically going inactive (and then to
* retention or off) if @clkdm2 is active. Returns -EINVAL if
* presented with invalid clockdomain pointers or called on a machine
* that does not support software-configurable hardware sleep
* dependencies, -ENOENT if the specified dependency cannot be set in
* hardware, or 0 upon success.
*/
static int _clkdm_add_sleepdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
clkdm1->name, clkdm2->name);
return ret;
}
cd->sleepdep_usecount++;
if (cd->sleepdep_usecount == 1) {
pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
}
return ret;
}
/**
* _clkdm_del_sleepdep - remove a sleep dep from clkdm2 to clkdm1 (lockless)
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
* @clkdm2: when this struct clockdomain * is active (source)
*
* Allow @clkdm1 to automatically go inactive (and then to retention or
* off), independent of the activity state of @clkdm2. Returns -EINVAL
* if presented with invalid clockdomain pointers or called on a machine
* that does not support software-configurable hardware sleep dependencies,
* -ENOENT if the specified dependency cannot be cleared in hardware, or
* 0 upon success.
*/
static int _clkdm_del_sleepdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
clkdm1->name, clkdm2->name);
return ret;
}
cd->sleepdep_usecount--;
if (cd->sleepdep_usecount == 0) {
pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
}
return ret;
}
/* Public functions */
/**
* clkdm_register_platform_funcs - register clockdomain implementation fns
* @co: func pointers for arch specific implementations
*
* Register the list of function pointers used to implement the
* clockdomain functions on different OMAP SoCs. Should be called
* before any other clkdm_register*() function. Returns -EINVAL if
* @co is null, -EEXIST if platform functions have already been
* registered, or 0 upon success.
*/
int clkdm_register_platform_funcs(struct clkdm_ops *co)
{
if (!co)
return -EINVAL;
if (arch_clkdm)
return -EEXIST;
arch_clkdm = co;
return 0;
};
/**
* clkdm_register_clkdms - register SoC clockdomains
* @cs: pointer to an array of struct clockdomain to register
*
* Register the clockdomains available on a particular OMAP SoC. Must
* be called after clkdm_register_platform_funcs(). May be called
* multiple times. Returns -EACCES if called before
* clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
* null; or 0 upon success.
*/
int clkdm_register_clkdms(struct clockdomain **cs)
{
struct clockdomain **c = NULL;
if (!arch_clkdm)
return -EACCES;
if (!cs)
return -EINVAL;
for (c = cs; *c; c++)
_clkdm_register(*c);
return 0;
}
/**
* clkdm_register_autodeps - register autodeps (if required)
* @ia: pointer to a static array of struct clkdm_autodep to register
*
* Register clockdomain "automatic dependencies." These are
* clockdomain wakeup and sleep dependencies that are automatically
* added whenever the first clock inside a clockdomain is enabled, and
* removed whenever the last clock inside a clockdomain is disabled.
* These are currently only used on OMAP3 devices, and are deprecated,
* since they waste energy. However, until the OMAP2/3 IP block
* enable/disable sequence can be converted to match the OMAP4
* sequence, they are needed.
*
* Must be called only after all of the SoC clockdomains are
* registered, since the function will resolve autodep clockdomain
* names into clockdomain pointers.
*
* The struct clkdm_autodep @ia array must be static, as this function
* does not copy the array elements.
*
* Returns -EACCES if called before any clockdomains have been
* registered, -EINVAL if called with a null @ia argument, -EEXIST if
* autodeps have already been registered, or 0 upon success.
*/
int clkdm_register_autodeps(struct clkdm_autodep *ia)
{
struct clkdm_autodep *a = NULL;
if (list_empty(&clkdm_list))
return -EACCES;
if (!ia)
return -EINVAL;
if (autodeps)
return -EEXIST;
autodeps = ia;
for (a = autodeps; a->clkdm.ptr; a++)
_autodep_lookup(a);
return 0;
}
/**
* clkdm_complete_init - set up the clockdomain layer
*
* Put all clockdomains into software-supervised mode; PM code should
* later enable hardware-supervised mode as appropriate. Must be
* called after clkdm_register_clkdms(). Returns -EACCES if called
* before clkdm_register_clkdms(), or 0 upon success.
*/
int clkdm_complete_init(void)
{
struct clockdomain *clkdm;
if (list_empty(&clkdm_list))
return -EACCES;
list_for_each_entry(clkdm, &clkdm_list, node) {
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
clkdm_wakeup(clkdm);
else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
clkdm_deny_idle(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
clkdm_clear_all_wkdeps(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
clkdm_clear_all_sleepdeps(clkdm);
}
return 0;
}
/**
* clkdm_lookup - look up a clockdomain by name, return a pointer
* @name: name of clockdomain
*
* Find a registered clockdomain by its name @name. Returns a pointer
* to the struct clockdomain if found, or NULL otherwise.
*/
struct clockdomain *clkdm_lookup(const char *name)
{
struct clockdomain *clkdm, *temp_clkdm;
if (!name)
return NULL;
clkdm = NULL;
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
if (!strcmp(name, temp_clkdm->name)) {
clkdm = temp_clkdm;
break;
}
}
return clkdm;
}
/**
* clkdm_for_each - call function on each registered clockdomain
* @fn: callback function *
*
* Call the supplied function @fn for each registered clockdomain.
* The callback function @fn can return anything but 0 to bail
* out early from the iterator. The callback function is called with
* the clkdm_mutex held, so no clockdomain structure manipulation
* functions should be called from the callback, although hardware
* clockdomain control functions are fine. Returns the last return
* value of the callback function, which should be 0 for success or
* anything else to indicate failure; or -EINVAL if the function pointer
* is null.
*/
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
void *user)
{
struct clockdomain *clkdm;
int ret = 0;
if (!fn)
return -EINVAL;
list_for_each_entry(clkdm, &clkdm_list, node) {
ret = (*fn)(clkdm, user);
if (ret)
break;
}
return ret;
}
/**
* clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
* @clkdm: struct clockdomain *
*
* Return a pointer to the struct powerdomain that the specified clockdomain
* @clkdm exists in, or returns NULL if @clkdm is NULL.
*/
struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
{
if (!clkdm)
return NULL;
return clkdm->pwrdm.ptr;
}
/* Hardware clockdomain control */
/**
* clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1
* @clkdm1: wake this struct clockdomain * up (dependent)
* @clkdm2: when this struct clockdomain * wakes up (source)
*
* When the clockdomain represented by @clkdm2 wakes up, wake up
* @clkdm1. Implemented in hardware on the OMAP, this feature is
* designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
* Returns -EINVAL if presented with invalid clockdomain pointers,
* -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
* success.
*/
int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
return PTR_ERR(cd);
pwrdm_lock(cd->clkdm->pwrdm.ptr);
ret = _clkdm_add_wkdep(clkdm1, clkdm2);
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1
* @clkdm1: wake this struct clockdomain * up (dependent)
* @clkdm2: when this struct clockdomain * wakes up (source)
*
* Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
* wakes up. Returns -EINVAL if presented with invalid clockdomain
* pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
* 0 upon success.
*/
int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
return PTR_ERR(cd);
pwrdm_lock(cd->clkdm->pwrdm.ptr);
ret = _clkdm_del_wkdep(clkdm1, clkdm2);
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1
* @clkdm1: wake this struct clockdomain * up (dependent)
* @clkdm2: when this struct clockdomain * wakes up (source)
*
* Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be
* awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL
* if either clockdomain pointer is invalid; or -ENOENT if the hardware
* is incapable.
*
* REVISIT: Currently this function only represents software-controllable
* wakeup dependencies. Wakeup dependencies fixed in hardware are not
* yet handled here.
*/
int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
clkdm1->name, clkdm2->name);
return ret;
}
/* XXX It's faster to return the wkdep_usecount */
return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
}
/**
* clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm
* @clkdm: struct clockdomain * to remove all wakeup dependencies from
*
* Remove all inter-clockdomain wakeup dependencies that could cause
* @clkdm to wake. Intended to be used during boot to initialize the
* PRCM to a known state, after all clockdomains are put into swsup idle
* and woken up. Returns -EINVAL if @clkdm pointer is invalid, or
* 0 upon success.
*/
int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
return -EINVAL;
return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
}
/**
* clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
* @clkdm2: when this struct clockdomain * is active (source)
*
* Prevent @clkdm1 from automatically going inactive (and then to
* retention or off) if @clkdm2 is active. Returns -EINVAL if
* presented with invalid clockdomain pointers or called on a machine
* that does not support software-configurable hardware sleep
* dependencies, -ENOENT if the specified dependency cannot be set in
* hardware, or 0 upon success.
*/
int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
return PTR_ERR(cd);
pwrdm_lock(cd->clkdm->pwrdm.ptr);
ret = _clkdm_add_sleepdep(clkdm1, clkdm2);
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
* @clkdm2: when this struct clockdomain * is active (source)
*
* Allow @clkdm1 to automatically go inactive (and then to retention or
* off), independent of the activity state of @clkdm2. Returns -EINVAL
* if presented with invalid clockdomain pointers or called on a machine
* that does not support software-configurable hardware sleep dependencies,
* -ENOENT if the specified dependency cannot be cleared in hardware, or
* 0 upon success.
*/
int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd))
return PTR_ERR(cd);
pwrdm_lock(cd->clkdm->pwrdm.ptr);
ret = _clkdm_del_sleepdep(clkdm1, clkdm2);
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
* @clkdm2: when this struct clockdomain * is active (source)
*
* Return 1 if a hardware sleep dependency exists wherein @clkdm1 will
* not be allowed to automatically go inactive if @clkdm2 is active;
* 0 if @clkdm1's automatic power state inactivity transition is independent
* of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called
* on a machine that does not support software-configurable hardware sleep
* dependencies; or -ENOENT if the hardware is incapable.
*
* REVISIT: Currently this function only represents software-controllable
* sleep dependencies. Sleep dependencies fixed in hardware are not
* yet handled here.
*/
int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
clkdm1->name, clkdm2->name);
return ret;
}
/* XXX It's faster to return the sleepdep_usecount */
return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
}
/**
* clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm
* @clkdm: struct clockdomain * to remove all sleep dependencies from
*
* Remove all inter-clockdomain sleep dependencies that could prevent
* @clkdm from idling. Intended to be used during boot to initialize the
* PRCM to a known state, after all clockdomains are put into swsup idle
* and woken up. Returns -EINVAL if @clkdm pointer is invalid, or
* 0 upon success.
*/
int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
return -EINVAL;
return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
}
/**
* clkdm_sleep_nolock - force clockdomain sleep transition (lockless)
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a sleep transition on the specified
* clockdomain @clkdm. Only for use by the powerdomain code. Returns
* -EINVAL if @clkdm is NULL or if clockdomain does not support
* software-initiated sleep; 0 upon success.
*/
int clkdm_sleep_nolock(struct clockdomain *clkdm)
{
int ret;
if (!clkdm)
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
pr_debug("clockdomain: %s does not support forcing sleep via software\n",
clkdm->name);
return -EINVAL;
}
if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
return -EINVAL;
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
ret = arch_clkdm->clkdm_sleep(clkdm);
ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_sleep - force clockdomain sleep transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a sleep transition on the specified
* clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if
* clockdomain does not support software-initiated sleep; 0 upon
* success.
*/
int clkdm_sleep(struct clockdomain *clkdm)
{
int ret;
pwrdm_lock(clkdm->pwrdm.ptr);
ret = clkdm_sleep_nolock(clkdm);
pwrdm_unlock(clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_wakeup_nolock - force clockdomain wakeup transition (lockless)
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a wakeup transition on the specified
* clockdomain @clkdm. Only for use by the powerdomain code. Returns
* -EINVAL if @clkdm is NULL or if the clockdomain does not support
* software-controlled wakeup; 0 upon success.
*/
int clkdm_wakeup_nolock(struct clockdomain *clkdm)
{
int ret;
if (!clkdm)
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
clkdm->name);
return -EINVAL;
}
if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
return -EINVAL;
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
ret = arch_clkdm->clkdm_wakeup(clkdm);
ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_wakeup - force clockdomain wakeup transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a wakeup transition on the specified
* clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the
* clockdomain does not support software-controlled wakeup; 0 upon
* success.
*/
int clkdm_wakeup(struct clockdomain *clkdm)
{
int ret;
pwrdm_lock(clkdm->pwrdm.ptr);
ret = clkdm_wakeup_nolock(clkdm);
pwrdm_unlock(clkdm->pwrdm.ptr);
return ret;
}
/**
* clkdm_allow_idle_nolock - enable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Allow the hardware to automatically switch the clockdomain @clkdm
* into active or idle states, as needed by downstream clocks. If the
* clockdomain has any downstream clocks enabled in the clock
* framework, wkdep/sleepdep autodependencies are added; this is so
* device drivers can read and write to the device. Only for use by
* the powerdomain code. No return value.
*/
void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
{
if (!clkdm)
return;
if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
clkdm->name);
return;
}
if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
return;
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
clkdm->name);
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_allow_idle(clkdm);
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
}
/**
* clkdm_allow_idle - enable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Allow the hardware to automatically switch the clockdomain @clkdm into
* active or idle states, as needed by downstream clocks. If the
* clockdomain has any downstream clocks enabled in the clock
* framework, wkdep/sleepdep autodependencies are added; this is so
* device drivers can read and write to the device. No return value.
*/
void clkdm_allow_idle(struct clockdomain *clkdm)
{
pwrdm_lock(clkdm->pwrdm.ptr);
clkdm_allow_idle_nolock(clkdm);
pwrdm_unlock(clkdm->pwrdm.ptr);
}
/**
* clkdm_deny_idle - disable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Prevent the hardware from automatically switching the clockdomain
* @clkdm into inactive or idle states. If the clockdomain has
* downstream clocks enabled in the clock framework, wkdep/sleepdep
* autodependencies are removed. Only for use by the powerdomain
* code. No return value.
*/
void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
{
if (!clkdm)
return;
if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
clkdm->name);
return;
}
if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
return;
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_deny_idle(clkdm);
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
}
/**
* clkdm_deny_idle - disable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Prevent the hardware from automatically switching the clockdomain
* @clkdm into inactive or idle states. If the clockdomain has
* downstream clocks enabled in the clock framework, wkdep/sleepdep
* autodependencies are removed. No return value.
*/
void clkdm_deny_idle(struct clockdomain *clkdm)
{
pwrdm_lock(clkdm->pwrdm.ptr);
clkdm_deny_idle_nolock(clkdm);
pwrdm_unlock(clkdm->pwrdm.ptr);
}
/**
* clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
* @clkdm: struct clockdomain *
*
* Returns true if clockdomain @clkdm currently has
* hardware-supervised idle enabled, or false if it does not or if
* @clkdm is NULL. It is only valid to call this function after
* clkdm_init() has been called. This function does not actually read
* bits from the hardware; it instead tests an in-memory flag that is
* changed whenever the clockdomain code changes the auto-idle mode.
*/
bool clkdm_in_hwsup(struct clockdomain *clkdm)
{
bool ret;
if (!clkdm)
return false;
ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
return ret;
}
/**
* clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
* @clkdm: struct clockdomain *
*
* Returns true if clockdomain @clkdm has the
* CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
* null. More information is available in the documentation for the
* CLKDM_MISSING_IDLE_REPORTING macro.
*/
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
{
if (!clkdm)
return false;
return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
}
/* Public autodep handling functions (deprecated) */
/**
* clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
* @clkdm: struct clockdomain *
*
* Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
* in hardware-supervised mode. Meant to be called from clock framework
* when a clock inside clockdomain 'clkdm' is enabled. No return value.
*
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
void clkdm_add_autodeps(struct clockdomain *clkdm)
{
struct clkdm_autodep *autodep;
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
return;
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
if (IS_ERR(autodep->clkdm.ptr))
continue;
pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
clkdm->name, autodep->clkdm.ptr->name);
_clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
_clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
}
}
/**
* clkdm_del_autodeps - remove auto sleepdeps/wkdeps from clkdm
* @clkdm: struct clockdomain *
*
* Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
* in hardware-supervised mode. Meant to be called from clock framework
* when a clock inside clockdomain 'clkdm' is disabled. No return value.
*
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
void clkdm_del_autodeps(struct clockdomain *clkdm)
{
struct clkdm_autodep *autodep;
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
return;
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
if (IS_ERR(autodep->clkdm.ptr))
continue;
pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
clkdm->name, autodep->clkdm.ptr->name);
_clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
_clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
}
}
/* Clockdomain-to-clock/hwmod framework interface code */
static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
{
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
/*
* For arch's with no autodeps, clkcm_clk_enable
* should be called for every clock instance or hwmod that is
* enabled, so the clkdm can be force woken up.
*/
clkdm->usecount++;
if (clkdm->usecount > 1 && autodeps) {
pwrdm_unlock(clkdm->pwrdm.ptr);
return 0;
}
arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
pwrdm_unlock(clkdm->pwrdm.ptr);
pr_debug("clockdomain: %s: enabled\n", clkdm->name);
return 0;
}
/**
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the enabled downstream clock
*
* Increment the usecount of the clockdomain @clkdm and ensure that it
* is awake before @clk is enabled. Intended to be called by
* clk_enable() code. If the clockdomain is in software-supervised
* idle mode, force the clockdomain to wake. If the clockdomain is in
* hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
* ensure that devices in the clockdomain can be read from/written to
* by on-chip processors. Returns -EINVAL if passed null pointers;
* returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
{
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream clocks for debugging purposes?
*/
if (!clk)
return -EINVAL;
return _clkdm_clk_hwmod_enable(clkdm);
}
/**
* clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the disabled downstream clock
*
* Decrement the usecount of this clockdomain @clkdm when @clk is
* disabled. Intended to be called by clk_disable() code. If the
* clockdomain usecount goes to 0, put the clockdomain to sleep
* (software-supervised mode) or remove the clkdm autodependencies
* (hardware-supervised mode). Returns -EINVAL if passed null
* pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
* upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
/* corner case: disabling unused clocks */
if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
goto ccd_exit;
if (clkdm->usecount == 0) {
pwrdm_unlock(clkdm->pwrdm.ptr);
WARN_ON(1); /* underflow */
return -ERANGE;
}
clkdm->usecount--;
if (clkdm->usecount > 0) {
pwrdm_unlock(clkdm->pwrdm.ptr);
return 0;
}
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
ccd_exit:
pwrdm_unlock(clkdm->pwrdm.ptr);
return 0;
}
/**
* clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
* @clkdm: struct clockdomain *
* @oh: struct omap_hwmod * of the enabled downstream hwmod
*
* Increment the usecount of the clockdomain @clkdm and ensure that it
* is awake before @oh is enabled. Intended to be called by
* module_enable() code.
* If the clockdomain is in software-supervised idle mode, force the
* clockdomain to wake. If the clockdomain is in hardware-supervised idle
* mode, add clkdm-pwrdm autodependencies, to ensure that devices in the
* clockdomain can be read from/written to by on-chip processors.
* Returns -EINVAL if passed null pointers;
* returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream hwmods for debugging purposes?
*/
if (!oh)
return -EINVAL;
return _clkdm_clk_hwmod_enable(clkdm);
}
/**
* clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
* @clkdm: struct clockdomain *
* @oh: struct omap_hwmod * of the disabled downstream hwmod
*
* Decrement the usecount of this clockdomain @clkdm when @oh is
* disabled. Intended to be called by module_disable() code.
* If the clockdomain usecount goes to 0, put the clockdomain to sleep
* (software-supervised mode) or remove the clkdm autodependencies
* (hardware-supervised mode).
* Returns -EINVAL if passed null pointers; -ERANGE if the @clkdm usecount
* underflows; or returns 0 upon success or if the clockdomain is in hwsup
* idle mode.
*/
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream hwmods for debugging purposes?
*/
if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
if (clkdm->usecount == 0) {
pwrdm_unlock(clkdm->pwrdm.ptr);
WARN_ON(1); /* underflow */
return -ERANGE;
}
clkdm->usecount--;
if (clkdm->usecount > 0) {
pwrdm_unlock(clkdm->pwrdm.ptr);
return 0;
}
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
pwrdm_unlock(clkdm->pwrdm.ptr);
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
return 0;
}
| gpl-2.0 |
eoghan2t9/kernel_qcom_cfx | sound/soc/imx/mx27vis-aic32x4.c | 4947 | 6911 | /*
* mx27vis-aic32x4.c
*
* Copyright 2011 Vista Silicon S.L.
*
* Author: Javier Martin <javier.martin@vista-silicon.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <asm/mach-types.h>
#include <mach/iomux-mx27.h>
#include "../codecs/tlv320aic32x4.h"
#include "imx-ssi.h"
#include "imx-audmux.h"
#define MX27VIS_AMP_GAIN 0
#define MX27VIS_AMP_MUTE 1
#define MX27VIS_PIN_G0 (GPIO_PORTF + 9)
#define MX27VIS_PIN_G1 (GPIO_PORTF + 8)
#define MX27VIS_PIN_SDL (GPIO_PORTE + 5)
#define MX27VIS_PIN_SDR (GPIO_PORTF + 7)
static int mx27vis_amp_gain;
static int mx27vis_amp_mute;
static const int mx27vis_amp_pins[] = {
MX27VIS_PIN_G0 | GPIO_GPIO | GPIO_OUT,
MX27VIS_PIN_G1 | GPIO_GPIO | GPIO_OUT,
MX27VIS_PIN_SDL | GPIO_GPIO | GPIO_OUT,
MX27VIS_PIN_SDR | GPIO_GPIO | GPIO_OUT,
};
static int mx27vis_aic32x4_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret;
u32 dai_format;
dai_format = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM;
/* set codec DAI configuration */
snd_soc_dai_set_fmt(codec_dai, dai_format);
/* set cpu DAI configuration */
snd_soc_dai_set_fmt(cpu_dai, dai_format);
ret = snd_soc_dai_set_sysclk(codec_dai, 0,
25000000, SND_SOC_CLOCK_OUT);
if (ret) {
pr_err("%s: failed setting codec sysclk\n", __func__);
return ret;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
SND_SOC_CLOCK_IN);
if (ret) {
pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
return ret;
}
return 0;
}
static struct snd_soc_ops mx27vis_aic32x4_snd_ops = {
.hw_params = mx27vis_aic32x4_hw_params,
};
static int mx27vis_amp_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int value = ucontrol->value.integer.value[0];
unsigned int reg = mc->reg;
int max = mc->max;
if (value > max)
return -EINVAL;
switch (reg) {
case MX27VIS_AMP_GAIN:
gpio_set_value(MX27VIS_PIN_G0, value & 1);
gpio_set_value(MX27VIS_PIN_G1, value >> 1);
mx27vis_amp_gain = value;
break;
case MX27VIS_AMP_MUTE:
gpio_set_value(MX27VIS_PIN_SDL, value & 1);
gpio_set_value(MX27VIS_PIN_SDR, value >> 1);
mx27vis_amp_mute = value;
break;
}
return 0;
}
static int mx27vis_amp_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
switch (reg) {
case MX27VIS_AMP_GAIN:
ucontrol->value.integer.value[0] = mx27vis_amp_gain;
break;
case MX27VIS_AMP_MUTE:
ucontrol->value.integer.value[0] = mx27vis_amp_mute;
break;
}
return 0;
}
/* From 6dB to 24dB in steps of 6dB */
static const DECLARE_TLV_DB_SCALE(mx27vis_amp_tlv, 600, 600, 0);
static const struct snd_kcontrol_new mx27vis_aic32x4_controls[] = {
SOC_DAPM_PIN_SWITCH("External Mic"),
SOC_SINGLE_EXT_TLV("LO Ext Boost", MX27VIS_AMP_GAIN, 0, 3, 0,
mx27vis_amp_get, mx27vis_amp_set, mx27vis_amp_tlv),
SOC_DOUBLE_EXT("LO Ext Mute Switch", MX27VIS_AMP_MUTE, 0, 1, 1, 0,
mx27vis_amp_get, mx27vis_amp_set),
};
static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
SND_SOC_DAPM_MIC("External Mic", NULL),
};
static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
{"Mic Bias", NULL, "External Mic"},
{"IN1_R", NULL, "Mic Bias"},
{"IN2_R", NULL, "Mic Bias"},
{"IN3_R", NULL, "Mic Bias"},
{"IN1_L", NULL, "Mic Bias"},
{"IN2_L", NULL, "Mic Bias"},
{"IN3_L", NULL, "Mic Bias"},
};
static struct snd_soc_dai_link mx27vis_aic32x4_dai = {
.name = "tlv320aic32x4",
.stream_name = "TLV320AIC32X4",
.codec_dai_name = "tlv320aic32x4-hifi",
.platform_name = "imx-pcm-audio.0",
.codec_name = "tlv320aic32x4.0-0018",
.cpu_dai_name = "imx-ssi.0",
.ops = &mx27vis_aic32x4_snd_ops,
};
static struct snd_soc_card mx27vis_aic32x4 = {
.name = "visstrim_m10-audio",
.owner = THIS_MODULE,
.dai_link = &mx27vis_aic32x4_dai,
.num_links = 1,
.controls = mx27vis_aic32x4_controls,
.num_controls = ARRAY_SIZE(mx27vis_aic32x4_controls),
.dapm_widgets = aic32x4_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
.dapm_routes = aic32x4_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
};
static int __devinit mx27vis_aic32x4_probe(struct platform_device *pdev)
{
int ret;
mx27vis_aic32x4.dev = &pdev->dev;
ret = snd_soc_register_card(&mx27vis_aic32x4);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
ret);
return ret;
}
/* Connect SSI0 as clock slave to SSI1 external pins */
imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
IMX_AUDMUX_V1_PCR_SYN |
IMX_AUDMUX_V1_PCR_TFSDIR |
IMX_AUDMUX_V1_PCR_TCLKDIR |
IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
);
imx_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
IMX_AUDMUX_V1_PCR_SYN |
IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
);
ret = mxc_gpio_setup_multiple_pins(mx27vis_amp_pins,
ARRAY_SIZE(mx27vis_amp_pins), "MX27VIS_AMP");
if (ret)
printk(KERN_ERR "ASoC: unable to setup gpios\n");
return ret;
}
static int __devexit mx27vis_aic32x4_remove(struct platform_device *pdev)
{
snd_soc_unregister_card(&mx27vis_aic32x4);
return 0;
}
static struct platform_driver mx27vis_aic32x4_audio_driver = {
.driver = {
.name = "mx27vis",
.owner = THIS_MODULE,
},
.probe = mx27vis_aic32x4_probe,
.remove = __devexit_p(mx27vis_aic32x4_remove),
};
module_platform_driver(mx27vis_aic32x4_audio_driver);
MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
MODULE_DESCRIPTION("ALSA SoC AIC32X4 mx27 visstrim");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mx27vis");
| gpl-2.0 |
LeJay/android_kernel_samsung_jactivelte | drivers/staging/line6/variax.c | 4947 | 18762 | /*
* Line6 Linux USB driver - 0.9.1beta
*
* Copyright (C) 2004-2010 Markus Grabner (grabner@icg.tugraz.at)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation, version 2.
*
*/
#include <linux/slab.h>
#include "audio.h"
#include "control.h"
#include "driver.h"
#include "variax.h"
#define VARIAX_SYSEX_CODE 7
#define VARIAX_SYSEX_PARAM 0x3b
#define VARIAX_SYSEX_ACTIVATE 0x2a
#define VARIAX_MODEL_HEADER_LENGTH 7
#define VARIAX_MODEL_MESSAGE_LENGTH 199
#define VARIAX_OFFSET_ACTIVATE 7
/*
This message is sent by the device during initialization and identifies
the connected guitar model.
*/
static const char variax_init_model[] = {
0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x69, 0x02,
0x00
};
/*
This message is sent by the device during initialization and identifies
the connected guitar version.
*/
static const char variax_init_version[] = {
0xf0, 0x7e, 0x7f, 0x06, 0x02, 0x00, 0x01, 0x0c,
0x07, 0x00, 0x00, 0x00
};
/*
This message is the last one sent by the device during initialization.
*/
static const char variax_init_done[] = {
0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x6b
};
static const char variax_activate[] = {
0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x2a, 0x01,
0xf7
};
static const char variax_request_bank[] = {
0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x6d, 0xf7
};
static const char variax_request_model1[] = {
0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x3c, 0x00,
0x02, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05, 0x03,
0x00, 0x00, 0x00, 0xf7
};
static const char variax_request_model2[] = {
0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x3c, 0x00,
0x02, 0x00, 0x00, 0x00, 0x00, 0x03, 0x07, 0x03,
0x00, 0x00, 0x00, 0xf7
};
/* forward declarations: */
static int variax_create_files2(struct device *dev);
static void variax_startup2(unsigned long data);
static void variax_startup4(unsigned long data);
static void variax_startup5(unsigned long data);
/*
Decode data transmitted by workbench.
*/
static void variax_decode(const unsigned char *raw_data, unsigned char *data,
int raw_size)
{
for (; raw_size > 0; raw_size -= 6) {
data[2] = raw_data[0] | (raw_data[1] << 4);
data[1] = raw_data[2] | (raw_data[3] << 4);
data[0] = raw_data[4] | (raw_data[5] << 4);
raw_data += 6;
data += 3;
}
}
static void variax_activate_async(struct usb_line6_variax *variax, int a)
{
variax->buffer_activate[VARIAX_OFFSET_ACTIVATE] = a;
line6_send_raw_message_async(&variax->line6, variax->buffer_activate,
sizeof(variax_activate));
}
/*
Variax startup procedure.
This is a sequence of functions with special requirements (e.g., must
not run immediately after initialization, must not run in interrupt
context). After the last one has finished, the device is ready to use.
*/
static void variax_startup1(struct usb_line6_variax *variax)
{
CHECK_STARTUP_PROGRESS(variax->startup_progress, VARIAX_STARTUP_INIT);
/* delay startup procedure: */
line6_start_timer(&variax->startup_timer1, VARIAX_STARTUP_DELAY1,
variax_startup2, (unsigned long)variax);
}
static void variax_startup2(unsigned long data)
{
struct usb_line6_variax *variax = (struct usb_line6_variax *)data;
struct usb_line6 *line6 = &variax->line6;
/* schedule another startup procedure until startup is complete: */
if (variax->startup_progress >= VARIAX_STARTUP_LAST)
return;
variax->startup_progress = VARIAX_STARTUP_VERSIONREQ;
line6_start_timer(&variax->startup_timer1, VARIAX_STARTUP_DELAY1,
variax_startup2, (unsigned long)variax);
/* request firmware version: */
line6_version_request_async(line6);
}
static void variax_startup3(struct usb_line6_variax *variax)
{
CHECK_STARTUP_PROGRESS(variax->startup_progress, VARIAX_STARTUP_WAIT);
/* delay startup procedure: */
line6_start_timer(&variax->startup_timer2, VARIAX_STARTUP_DELAY3,
variax_startup4, (unsigned long)variax);
}
static void variax_startup4(unsigned long data)
{
struct usb_line6_variax *variax = (struct usb_line6_variax *)data;
CHECK_STARTUP_PROGRESS(variax->startup_progress,
VARIAX_STARTUP_ACTIVATE);
/* activate device: */
variax_activate_async(variax, 1);
line6_start_timer(&variax->startup_timer2, VARIAX_STARTUP_DELAY4,
variax_startup5, (unsigned long)variax);
}
static void variax_startup5(unsigned long data)
{
struct usb_line6_variax *variax = (struct usb_line6_variax *)data;
CHECK_STARTUP_PROGRESS(variax->startup_progress,
VARIAX_STARTUP_DUMPREQ);
/* current model dump: */
line6_dump_request_async(&variax->dumpreq, &variax->line6, 0,
VARIAX_DUMP_PASS1);
/* passes 2 and 3 are performed implicitly before entering variax_startup6 */
}
static void variax_startup6(struct usb_line6_variax *variax)
{
CHECK_STARTUP_PROGRESS(variax->startup_progress,
VARIAX_STARTUP_WORKQUEUE);
/* schedule work for global work queue: */
schedule_work(&variax->startup_work);
}
static void variax_startup7(struct work_struct *work)
{
struct usb_line6_variax *variax =
container_of(work, struct usb_line6_variax, startup_work);
struct usb_line6 *line6 = &variax->line6;
CHECK_STARTUP_PROGRESS(variax->startup_progress, VARIAX_STARTUP_SETUP);
/* ALSA audio interface: */
line6_register_audio(&variax->line6);
/* device files: */
line6_variax_create_files(0, 0, line6->ifcdev);
variax_create_files2(line6->ifcdev);
}
/*
Process a completely received message.
*/
void line6_variax_process_message(struct usb_line6_variax *variax)
{
const unsigned char *buf = variax->line6.buffer_message;
switch (buf[0]) {
case LINE6_PARAM_CHANGE | LINE6_CHANNEL_HOST:
switch (buf[1]) {
case VARIAXMIDI_volume:
variax->volume = buf[2];
break;
case VARIAXMIDI_tone:
variax->tone = buf[2];
}
break;
case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE:
case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST:
variax->model = buf[1];
line6_dump_request_async(&variax->dumpreq, &variax->line6, 0,
VARIAX_DUMP_PASS1);
break;
case LINE6_RESET:
dev_info(variax->line6.ifcdev, "VARIAX reset\n");
break;
case LINE6_SYSEX_BEGIN:
if (memcmp(buf + 1, variax_request_model1 + 1,
VARIAX_MODEL_HEADER_LENGTH - 1) == 0) {
if (variax->line6.message_length ==
VARIAX_MODEL_MESSAGE_LENGTH) {
switch (variax->dumpreq.in_progress) {
case VARIAX_DUMP_PASS1:
variax_decode(buf +
VARIAX_MODEL_HEADER_LENGTH,
(unsigned char *)
&variax->model_data,
(sizeof
(variax->model_data.
name) +
sizeof(variax->
model_data.
control)
/ 2) * 2);
line6_dump_request_async
(&variax->dumpreq, &variax->line6,
1, VARIAX_DUMP_PASS2);
break;
case VARIAX_DUMP_PASS2:
/* model name is transmitted twice, so skip it here: */
variax_decode(buf +
VARIAX_MODEL_HEADER_LENGTH,
(unsigned char *)
&variax->
model_data.control +
sizeof(variax->model_data.
control)
/ 2,
sizeof(variax->model_data.
control)
/ 2 * 2);
line6_dump_request_async
(&variax->dumpreq, &variax->line6,
2, VARIAX_DUMP_PASS3);
}
} else {
DEBUG_MESSAGES(dev_err
(variax->line6.ifcdev,
"illegal length %d of model data\n",
variax->line6.message_length));
line6_dump_finished(&variax->dumpreq);
}
} else if (memcmp(buf + 1, variax_request_bank + 1,
sizeof(variax_request_bank) - 2) == 0) {
memcpy(variax->bank,
buf + sizeof(variax_request_bank) - 1,
sizeof(variax->bank));
line6_dump_finished(&variax->dumpreq);
variax_startup6(variax);
} else if (memcmp(buf + 1, variax_init_model + 1,
sizeof(variax_init_model) - 1) == 0) {
memcpy(variax->guitar,
buf + sizeof(variax_init_model),
sizeof(variax->guitar));
} else if (memcmp(buf + 1, variax_init_version + 1,
sizeof(variax_init_version) - 1) == 0) {
variax_startup3(variax);
} else if (memcmp(buf + 1, variax_init_done + 1,
sizeof(variax_init_done) - 1) == 0) {
/* notify of complete initialization: */
variax_startup4((unsigned long)variax);
}
break;
case LINE6_SYSEX_END:
break;
default:
DEBUG_MESSAGES(dev_err
(variax->line6.ifcdev,
"Variax: unknown message %02X\n", buf[0]));
}
}
/*
"read" request on "volume" special file.
*/
static ssize_t variax_get_volume(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
return sprintf(buf, "%d\n", variax->volume);
}
/*
"write" request on "volume" special file.
*/
static ssize_t variax_set_volume(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
unsigned long value;
int ret;
ret = strict_strtoul(buf, 10, &value);
if (ret)
return ret;
if (line6_transmit_parameter(&variax->line6, VARIAXMIDI_volume,
value) == 0)
variax->volume = value;
return count;
}
/*
"read" request on "model" special file.
*/
static ssize_t variax_get_model(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
return sprintf(buf, "%d\n", variax->model);
}
/*
"write" request on "model" special file.
*/
static ssize_t variax_set_model(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
unsigned long value;
int ret;
ret = strict_strtoul(buf, 10, &value);
if (ret)
return ret;
if (line6_send_program(&variax->line6, value) == 0)
variax->model = value;
return count;
}
/*
"read" request on "active" special file.
*/
static ssize_t variax_get_active(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
return sprintf(buf, "%d\n",
variax->buffer_activate[VARIAX_OFFSET_ACTIVATE]);
}
/*
"write" request on "active" special file.
*/
static ssize_t variax_set_active(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
unsigned long value;
int ret;
ret = strict_strtoul(buf, 10, &value);
if (ret)
return ret;
variax_activate_async(variax, value ? 1 : 0);
return count;
}
/*
"read" request on "tone" special file.
*/
static ssize_t variax_get_tone(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
return sprintf(buf, "%d\n", variax->tone);
}
/*
"write" request on "tone" special file.
*/
static ssize_t variax_set_tone(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
unsigned long value;
int ret;
ret = strict_strtoul(buf, 10, &value);
if (ret)
return ret;
if (line6_transmit_parameter(&variax->line6, VARIAXMIDI_tone,
value) == 0)
variax->tone = value;
return count;
}
static ssize_t get_string(char *buf, const char *data, int length)
{
int i;
memcpy(buf, data, length);
for (i = length; i--;) {
char c = buf[i];
if ((c != 0) && (c != ' '))
break;
}
buf[i + 1] = '\n';
return i + 2;
}
/*
"read" request on "name" special file.
*/
static ssize_t variax_get_name(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
line6_dump_wait_interruptible(&variax->dumpreq);
return get_string(buf, variax->model_data.name,
sizeof(variax->model_data.name));
}
/*
"read" request on "bank" special file.
*/
static ssize_t variax_get_bank(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
line6_dump_wait_interruptible(&variax->dumpreq);
return get_string(buf, variax->bank, sizeof(variax->bank));
}
/*
"read" request on "dump" special file.
*/
static ssize_t variax_get_dump(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
int retval;
retval = line6_dump_wait_interruptible(&variax->dumpreq);
if (retval < 0)
return retval;
memcpy(buf, &variax->model_data.control,
sizeof(variax->model_data.control));
return sizeof(variax->model_data.control);
}
/*
"read" request on "guitar" special file.
*/
static ssize_t variax_get_guitar(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
return sprintf(buf, "%s\n", variax->guitar);
}
#ifdef CONFIG_LINE6_USB_RAW
static char *variax_alloc_sysex_buffer(struct usb_line6_variax *variax,
int code, int size)
{
return line6_alloc_sysex_buffer(&variax->line6, VARIAX_SYSEX_CODE, code,
size);
}
/*
"write" request on "raw" special file.
*/
static ssize_t variax_set_raw2(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct usb_line6_variax *variax =
usb_get_intfdata(to_usb_interface(dev));
int size;
int i;
char *sysex;
count -= count % 3;
size = count * 2;
sysex = variax_alloc_sysex_buffer(variax, VARIAX_SYSEX_PARAM, size);
if (!sysex)
return 0;
for (i = 0; i < count; i += 3) {
const unsigned char *p1 = buf + i;
char *p2 = sysex + SYSEX_DATA_OFS + i * 2;
p2[0] = p1[2] & 0x0f;
p2[1] = p1[2] >> 4;
p2[2] = p1[1] & 0x0f;
p2[3] = p1[1] >> 4;
p2[4] = p1[0] & 0x0f;
p2[5] = p1[0] >> 4;
}
line6_send_sysex_message(&variax->line6, sysex, size);
kfree(sysex);
return count;
}
#endif
/* Variax workbench special files: */
static DEVICE_ATTR(model, S_IWUSR | S_IRUGO, variax_get_model,
variax_set_model);
static DEVICE_ATTR(volume, S_IWUSR | S_IRUGO, variax_get_volume,
variax_set_volume);
static DEVICE_ATTR(tone, S_IWUSR | S_IRUGO, variax_get_tone, variax_set_tone);
static DEVICE_ATTR(name, S_IRUGO, variax_get_name, line6_nop_write);
static DEVICE_ATTR(bank, S_IRUGO, variax_get_bank, line6_nop_write);
static DEVICE_ATTR(dump, S_IRUGO, variax_get_dump, line6_nop_write);
static DEVICE_ATTR(active, S_IWUSR | S_IRUGO, variax_get_active,
variax_set_active);
static DEVICE_ATTR(guitar, S_IRUGO, variax_get_guitar, line6_nop_write);
#ifdef CONFIG_LINE6_USB_RAW
static DEVICE_ATTR(raw, S_IWUSR, line6_nop_read, line6_set_raw);
static DEVICE_ATTR(raw2, S_IWUSR, line6_nop_read, variax_set_raw2);
#endif
/*
Variax destructor.
*/
static void variax_destruct(struct usb_interface *interface)
{
struct usb_line6_variax *variax = usb_get_intfdata(interface);
if (variax == NULL)
return;
line6_cleanup_audio(&variax->line6);
del_timer(&variax->startup_timer1);
del_timer(&variax->startup_timer2);
cancel_work_sync(&variax->startup_work);
/* free dump request data: */
line6_dumpreq_destructbuf(&variax->dumpreq, 2);
line6_dumpreq_destructbuf(&variax->dumpreq, 1);
line6_dumpreq_destruct(&variax->dumpreq);
kfree(variax->buffer_activate);
}
/*
Create sysfs entries.
*/
static int variax_create_files2(struct device *dev)
{
int err;
CHECK_RETURN(device_create_file(dev, &dev_attr_model));
CHECK_RETURN(device_create_file(dev, &dev_attr_volume));
CHECK_RETURN(device_create_file(dev, &dev_attr_tone));
CHECK_RETURN(device_create_file(dev, &dev_attr_name));
CHECK_RETURN(device_create_file(dev, &dev_attr_bank));
CHECK_RETURN(device_create_file(dev, &dev_attr_dump));
CHECK_RETURN(device_create_file(dev, &dev_attr_active));
CHECK_RETURN(device_create_file(dev, &dev_attr_guitar));
#ifdef CONFIG_LINE6_USB_RAW
CHECK_RETURN(device_create_file(dev, &dev_attr_raw));
CHECK_RETURN(device_create_file(dev, &dev_attr_raw2));
#endif
return 0;
}
/*
Try to init workbench device.
*/
static int variax_try_init(struct usb_interface *interface,
struct usb_line6_variax *variax)
{
int err;
init_timer(&variax->startup_timer1);
init_timer(&variax->startup_timer2);
INIT_WORK(&variax->startup_work, variax_startup7);
if ((interface == NULL) || (variax == NULL))
return -ENODEV;
/* initialize USB buffers: */
err = line6_dumpreq_init(&variax->dumpreq, variax_request_model1,
sizeof(variax_request_model1));
if (err < 0) {
dev_err(&interface->dev, "Out of memory\n");
return err;
}
err = line6_dumpreq_initbuf(&variax->dumpreq, variax_request_model2,
sizeof(variax_request_model2), 1);
if (err < 0) {
dev_err(&interface->dev, "Out of memory\n");
return err;
}
err = line6_dumpreq_initbuf(&variax->dumpreq, variax_request_bank,
sizeof(variax_request_bank), 2);
if (err < 0) {
dev_err(&interface->dev, "Out of memory\n");
return err;
}
variax->buffer_activate = kmemdup(variax_activate,
sizeof(variax_activate), GFP_KERNEL);
if (variax->buffer_activate == NULL) {
dev_err(&interface->dev, "Out of memory\n");
return -ENOMEM;
}
/* initialize audio system: */
err = line6_init_audio(&variax->line6);
if (err < 0)
return err;
/* initialize MIDI subsystem: */
err = line6_init_midi(&variax->line6);
if (err < 0)
return err;
/* initiate startup procedure: */
variax_startup1(variax);
return 0;
}
/*
Init workbench device (and clean up in case of failure).
*/
int line6_variax_init(struct usb_interface *interface,
struct usb_line6_variax *variax)
{
int err = variax_try_init(interface, variax);
if (err < 0)
variax_destruct(interface);
return err;
}
/*
Workbench device disconnected.
*/
void line6_variax_disconnect(struct usb_interface *interface)
{
struct device *dev;
if (interface == NULL)
return;
dev = &interface->dev;
if (dev != NULL) {
/* remove sysfs entries: */
line6_variax_remove_files(0, 0, dev);
device_remove_file(dev, &dev_attr_model);
device_remove_file(dev, &dev_attr_volume);
device_remove_file(dev, &dev_attr_tone);
device_remove_file(dev, &dev_attr_name);
device_remove_file(dev, &dev_attr_bank);
device_remove_file(dev, &dev_attr_dump);
device_remove_file(dev, &dev_attr_active);
device_remove_file(dev, &dev_attr_guitar);
#ifdef CONFIG_LINE6_USB_RAW
device_remove_file(dev, &dev_attr_raw);
device_remove_file(dev, &dev_attr_raw2);
#endif
}
variax_destruct(interface);
}
| gpl-2.0 |
deatharrow/lge-kernel-e400 | drivers/media/dvb/frontends/dib8000.c | 4947 | 109835 | /*
* Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
*
* Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation, version 2.
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include "dvb_math.h"
#include "dvb_frontend.h"
#include "dib8000.h"
#define LAYER_ALL -1
#define LAYER_A 1
#define LAYER_B 2
#define LAYER_C 3
#define FE_CALLBACK_TIME_NEVER 0xffffffff
#define MAX_NUMBER_OF_FRONTENDS 6
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
#define FE_STATUS_TUNE_FAILED 0
struct i2c_device {
struct i2c_adapter *adap;
u8 addr;
u8 *i2c_write_buffer;
u8 *i2c_read_buffer;
struct mutex *i2c_buffer_lock;
};
struct dib8000_state {
struct dib8000_config cfg;
struct i2c_device i2c;
struct dibx000_i2c_master i2c_master;
u16 wbd_ref;
u8 current_band;
u32 current_bandwidth;
struct dibx000_agc_config *current_agc;
u32 timf;
u32 timf_default;
u8 div_force_off:1;
u8 div_state:1;
u16 div_sync_wait;
u8 agc_state;
u8 differential_constellation;
u8 diversity_onoff;
s16 ber_monitored_layer;
u16 gpio_dir;
u16 gpio_val;
u16 revision;
u8 isdbt_cfg_loaded;
enum frontend_tune_state tune_state;
u32 status;
struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
/* for the I2C transfer */
struct i2c_msg msg[2];
u8 i2c_write_buffer[4];
u8 i2c_read_buffer[2];
struct mutex i2c_buffer_lock;
u8 input_mode_mpeg;
u16 tuner_enable;
struct i2c_adapter dib8096p_tuner_adap;
};
enum dib8000_power_mode {
DIB8000_POWER_ALL = 0,
DIB8000_POWER_INTERFACE_ONLY,
};
static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
{
u16 ret;
struct i2c_msg msg[2] = {
{.addr = i2c->addr >> 1, .flags = 0, .len = 2},
{.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
};
if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock");
return 0;
}
msg[0].buf = i2c->i2c_write_buffer;
msg[0].buf[0] = reg >> 8;
msg[0].buf[1] = reg & 0xff;
msg[1].buf = i2c->i2c_read_buffer;
if (i2c_transfer(i2c->adap, msg, 2) != 2)
dprintk("i2c read error on %d", reg);
ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
mutex_unlock(i2c->i2c_buffer_lock);
return ret;
}
static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
{
u16 ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock");
return 0;
}
state->i2c_write_buffer[0] = reg >> 8;
state->i2c_write_buffer[1] = reg & 0xff;
memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c.addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 2;
state->msg[1].addr = state->i2c.addr >> 1;
state->msg[1].flags = I2C_M_RD;
state->msg[1].buf = state->i2c_read_buffer;
state->msg[1].len = 2;
if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
dprintk("i2c read error on %d", reg);
ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
{
u16 rw[2];
rw[0] = dib8000_read_word(state, reg + 0);
rw[1] = dib8000_read_word(state, reg + 1);
return ((rw[0] << 16) | (rw[1]));
}
static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
{
struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
int ret = 0;
if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock");
return -EINVAL;
}
msg.buf = i2c->i2c_write_buffer;
msg.buf[0] = (reg >> 8) & 0xff;
msg.buf[1] = reg & 0xff;
msg.buf[2] = (val >> 8) & 0xff;
msg.buf[3] = val & 0xff;
ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
mutex_unlock(i2c->i2c_buffer_lock);
return ret;
}
static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
{
int ret;
if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
dprintk("could not acquire lock");
return -EINVAL;
}
state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
state->i2c_write_buffer[1] = reg & 0xff;
state->i2c_write_buffer[2] = (val >> 8) & 0xff;
state->i2c_write_buffer[3] = val & 0xff;
memset(&state->msg[0], 0, sizeof(struct i2c_msg));
state->msg[0].addr = state->i2c.addr >> 1;
state->msg[0].flags = 0;
state->msg[0].buf = state->i2c_write_buffer;
state->msg[0].len = 4;
ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
-EREMOTEIO : 0);
mutex_unlock(&state->i2c_buffer_lock);
return ret;
}
static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
(769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
(920 << 5) | 0x09
};
static const s16 coeff_2k_sb_1seg[8] = {
(692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
};
static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
(832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
(-931 << 5) | 0x0f
};
static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
(622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
(982 << 5) | 0x0c
};
static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
(699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
(-720 << 5) | 0x0d
};
static const s16 coeff_2k_sb_3seg[8] = {
(664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
(-610 << 5) | 0x0a
};
static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
(-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
(-922 << 5) | 0x0d
};
static const s16 coeff_4k_sb_1seg[8] = {
(638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
(-655 << 5) | 0x0a
};
static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
(-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
(-958 << 5) | 0x13
};
static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
(-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
(-568 << 5) | 0x0f
};
static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
(-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
(-848 << 5) | 0x13
};
static const s16 coeff_4k_sb_3seg[8] = {
(612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
(-869 << 5) | 0x13
};
static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
(-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
(-598 << 5) | 0x10
};
static const s16 coeff_8k_sb_1seg[8] = {
(673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
(585 << 5) | 0x0f
};
static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
(863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
(0 << 5) | 0x14
};
static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
(-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
(-877 << 5) | 0x15
};
static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
(-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
(-921 << 5) | 0x14
};
static const s16 coeff_8k_sb_3seg[8] = {
(514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
(690 << 5) | 0x14
};
static const s16 ana_fe_coeff_3seg[24] = {
81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
};
static const s16 ana_fe_coeff_1seg[24] = {
249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
};
static const s16 ana_fe_coeff_13seg[24] = {
396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
};
static u16 fft_to_mode(struct dib8000_state *state)
{
u16 mode;
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
mode = 1;
break;
case TRANSMISSION_MODE_4K:
mode = 2;
break;
default:
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
mode = 3;
break;
}
return mode;
}
static void dib8000_set_acquisition_mode(struct dib8000_state *state)
{
u16 nud = dib8000_read_word(state, 298);
nud |= (1 << 3) | (1 << 0);
dprintk("acquisition mode activated");
dib8000_write_word(state, 298, nud);
}
static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
outreg = 0;
fifo_threshold = 1792;
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
dprintk("-I- Setting output mode for demod %p to %d",
&state->fe[0], mode);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
outreg = (1 << 10); /* 0x0400 */
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
outreg = (1 << 10) | (1 << 6); /* 0x0440 */
break;
case OUTMODE_MPEG2_SERIAL: // STBs with serial input
outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
break;
case OUTMODE_DIVERSITY:
if (state->cfg.hostbus_diversity) {
outreg = (1 << 10) | (4 << 6); /* 0x0500 */
sram &= 0xfdff;
} else
sram |= 0x0c00;
break;
case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
smo_mode |= (3 << 1);
fifo_threshold = 512;
outreg = (1 << 10) | (5 << 6);
break;
case OUTMODE_HIGH_Z: // disable
outreg = 0;
break;
case OUTMODE_ANALOG_ADC:
outreg = (1 << 10) | (3 << 6);
dib8000_set_acquisition_mode(state);
break;
default:
dprintk("Unhandled output_mode passed to be set for demod %p",
&state->fe[0]);
return -EINVAL;
}
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
dib8000_write_word(state, 299, smo_mode);
dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
dib8000_write_word(state, 1286, outreg);
dib8000_write_word(state, 1291, sram);
return 0;
}
static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 sync_wait = dib8000_read_word(state, 273) & 0xfff0;
if (!state->differential_constellation) {
dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
} else {
dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
}
state->diversity_onoff = onoff;
switch (onoff) {
case 0: /* only use the internal way - not the diversity input */
dib8000_write_word(state, 270, 1);
dib8000_write_word(state, 271, 0);
break;
case 1: /* both ways */
dib8000_write_word(state, 270, 6);
dib8000_write_word(state, 271, 6);
break;
case 2: /* only the diversity input */
dib8000_write_word(state, 270, 0);
dib8000_write_word(state, 271, 1);
break;
}
return 0;
}
static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
{
/* by default everything is going to be powered off */
u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
reg_1280;
if (state->revision != 0x8090)
reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
else
reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
/* now, depending on the requested mode, we power on */
switch (mode) {
/* power up everything in the demod */
case DIB8000_POWER_ALL:
reg_774 = 0x0000;
reg_775 = 0x0000;
reg_776 = 0x0000;
reg_900 &= 0xfffc;
if (state->revision != 0x8090)
reg_1280 &= 0x00ff;
else
reg_1280 &= 0x707f;
break;
case DIB8000_POWER_INTERFACE_ONLY:
if (state->revision != 0x8090)
reg_1280 &= 0x00ff;
else
reg_1280 &= 0xfa7b;
break;
}
dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x", reg_774, reg_775, reg_776, reg_900, reg_1280);
dib8000_write_word(state, 774, reg_774);
dib8000_write_word(state, 775, reg_775);
dib8000_write_word(state, 776, reg_776);
dib8000_write_word(state, 900, reg_900);
dib8000_write_word(state, 1280, reg_1280);
}
static int dib8000_init_sdram(struct dib8000_state *state)
{
u16 reg = 0;
dprintk("Init sdram");
reg = dib8000_read_word(state, 274)&0xfff0;
/* P_dintlv_delay_ram = 7 because of MobileSdram */
dib8000_write_word(state, 274, reg | 0x7);
dib8000_write_word(state, 1803, (7<<2));
reg = dib8000_read_word(state, 1280);
/* force restart P_restart_sdram */
dib8000_write_word(state, 1280, reg | (1<<2));
/* release restart P_restart_sdram */
dib8000_write_word(state, 1280, reg);
return 0;
}
static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
{
int ret = 0;
u16 reg, reg_907 = dib8000_read_word(state, 907);
u16 reg_908 = dib8000_read_word(state, 908);
switch (no) {
case DIBX000_SLOW_ADC_ON:
if (state->revision != 0x8090) {
reg_908 |= (1 << 1) | (1 << 0);
ret |= dib8000_write_word(state, 908, reg_908);
reg_908 &= ~(1 << 1);
} else {
reg = dib8000_read_word(state, 1925);
/* en_slowAdc = 1 & reset_sladc = 1 */
dib8000_write_word(state, 1925, reg |
(1<<4) | (1<<2));
/* read acces to make it works... strange ... */
reg = dib8000_read_word(state, 1925);
msleep(20);
/* en_slowAdc = 1 & reset_sladc = 0 */
dib8000_write_word(state, 1925, reg & ~(1<<4));
reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
| (0x3 << 12));
/* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
(Vin2 = Vcm) */
dib8000_write_word(state, 921, reg | (1 << 14)
| (3 << 12));
}
break;
case DIBX000_SLOW_ADC_OFF:
if (state->revision == 0x8090) {
reg = dib8000_read_word(state, 1925);
/* reset_sladc = 1 en_slowAdc = 0 */
dib8000_write_word(state, 1925,
(reg & ~(1<<2)) | (1<<4));
}
reg_908 |= (1 << 1) | (1 << 0);
break;
case DIBX000_ADC_ON:
reg_907 &= 0x0fff;
reg_908 &= 0x0003;
break;
case DIBX000_ADC_OFF: // leave the VBG voltage on
reg_907 |= (1 << 14) | (1 << 13) | (1 << 12);
reg_908 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
break;
case DIBX000_VBG_ENABLE:
reg_907 &= ~(1 << 15);
break;
case DIBX000_VBG_DISABLE:
reg_907 |= (1 << 15);
break;
default:
break;
}
ret |= dib8000_write_word(state, 907, reg_907);
ret |= dib8000_write_word(state, 908, reg_908);
return ret;
}
static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
{
struct dib8000_state *state = fe->demodulator_priv;
u32 timf;
if (bw == 0)
bw = 6000;
if (state->timf == 0) {
dprintk("using default timf");
timf = state->timf_default;
} else {
dprintk("using updated timf");
timf = state->timf;
}
dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
return 0;
}
static int dib8000_sad_calib(struct dib8000_state *state)
{
if (state->revision == 0x8090) {
dprintk("%s: the sad calibration is not needed for the dib8096P",
__func__);
return 0;
}
/* internal */
dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096
/* do the calibration */
dib8000_write_word(state, 923, (1 << 0));
dib8000_write_word(state, 923, (0 << 0));
msleep(1);
return 0;
}
int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
{
struct dib8000_state *state = fe->demodulator_priv;
if (value > 4095)
value = 4095;
state->wbd_ref = value;
return dib8000_write_word(state, 106, value);
}
EXPORT_SYMBOL(dib8000_set_wbd_ref);
static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
{
dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
if (state->revision != 0x8090) {
dib8000_write_word(state, 23,
(u16) (((bw->internal * 1000) >> 16) & 0xffff));
dib8000_write_word(state, 24,
(u16) ((bw->internal * 1000) & 0xffff));
} else {
dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
dib8000_write_word(state, 24,
(u16) ((bw->internal / 2 * 1000) & 0xffff));
}
dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
if (state->revision != 0x8090)
dib8000_write_word(state, 922, bw->sad_cfg);
}
static void dib8000_reset_pll(struct dib8000_state *state)
{
const struct dibx000_bandwidth_config *pll = state->cfg.pll;
u16 clk_cfg1, reg;
if (state->revision != 0x8090) {
dib8000_write_word(state, 901,
(pll->pll_prediv << 8) | (pll->pll_ratio << 0));
clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
(1 << 3) | (pll->pll_range << 1) |
(pll->pll_reset << 0);
dib8000_write_word(state, 902, clk_cfg1);
clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
dib8000_write_word(state, 902, clk_cfg1);
dprintk("clk_cfg1: 0x%04x", clk_cfg1);
/* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
if (state->cfg.pll->ADClkSrc == 0)
dib8000_write_word(state, 904,
(0 << 15) | (0 << 12) | (0 << 10) |
(pll->modulo << 8) |
(pll->ADClkSrc << 7) | (0 << 1));
else if (state->cfg.refclksel != 0)
dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
((state->cfg.refclksel & 0x3) << 10) |
(pll->modulo << 8) |
(pll->ADClkSrc << 7) | (0 << 1));
else
dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
(3 << 10) | (pll->modulo << 8) |
(pll->ADClkSrc << 7) | (0 << 1));
} else {
dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
(pll->pll_range<<12) | (pll->pll_ratio<<6) |
(pll->pll_prediv));
reg = dib8000_read_word(state, 1857);
dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
dib8000_write_word(state, 1858, reg | 1);
dib8000_write_word(state, 904, (pll->modulo << 8));
}
dib8000_reset_pll_common(state, pll);
}
int dib8000_update_pll(struct dvb_frontend *fe,
struct dibx000_bandwidth_config *pll)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
u8 loopdiv, prediv;
u32 internal, xtal;
/* get back old values */
prediv = reg_1856 & 0x3f;
loopdiv = (reg_1856 >> 6) & 0x3f;
if ((pll != NULL) && (pll->pll_prediv != prediv ||
pll->pll_ratio != loopdiv)) {
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
reg_1856 &= 0xf000;
reg_1857 = dib8000_read_word(state, 1857);
/* disable PLL */
dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
dib8000_write_word(state, 1856, reg_1856 |
((pll->pll_ratio & 0x3f) << 6) |
(pll->pll_prediv & 0x3f));
/* write new system clk into P_sec_len */
internal = dib8000_read32(state, 23) / 1000;
dprintk("Old Internal = %d", internal);
xtal = 2 * (internal / loopdiv) * prediv;
internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d", xtal, internal/1000, internal/2000, internal/8000);
dprintk("New Internal = %d", internal);
dib8000_write_word(state, 23,
(u16) (((internal / 2) >> 16) & 0xffff));
dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
/* enable PLL */
dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
dprintk("Waiting for PLL to lock");
/* verify */
reg_1856 = dib8000_read_word(state, 1856);
dprintk("PLL Updated with prediv = %d and loopdiv = %d",
reg_1856&0x3f, (reg_1856>>6)&0x3f);
return 0;
}
return -EINVAL;
}
EXPORT_SYMBOL(dib8000_update_pll);
static int dib8000_reset_gpio(struct dib8000_state *st)
{
/* reset the GPIOs */
dib8000_write_word(st, 1029, st->cfg.gpio_dir);
dib8000_write_word(st, 1030, st->cfg.gpio_val);
/* TODO 782 is P_gpio_od */
dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
return 0;
}
static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
{
st->cfg.gpio_dir = dib8000_read_word(st, 1029);
st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
dib8000_write_word(st, 1029, st->cfg.gpio_dir);
st->cfg.gpio_val = dib8000_read_word(st, 1030);
st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
dib8000_write_word(st, 1030, st->cfg.gpio_val);
dprintk("gpio dir: %x: gpio val: %x", st->cfg.gpio_dir, st->cfg.gpio_val);
return 0;
}
int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
{
struct dib8000_state *state = fe->demodulator_priv;
return dib8000_cfg_gpio(state, num, dir, val);
}
EXPORT_SYMBOL(dib8000_set_gpio);
static const u16 dib8000_defaults[] = {
/* auto search configuration - lock0 by default waiting
* for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
3, 7,
0x0004,
0x0400,
0x0814,
12, 11,
0x001b,
0x7740,
0x005b,
0x8d80,
0x01c9,
0xc380,
0x0000,
0x0080,
0x0000,
0x0090,
0x0001,
0xd4c0,
/*1, 32,
0x6680 // P_corm_thres Lock algorithms configuration */
11, 80, /* set ADC level to -16 */
(1 << 13) - 825 - 117,
(1 << 13) - 837 - 117,
(1 << 13) - 811 - 117,
(1 << 13) - 766 - 117,
(1 << 13) - 737 - 117,
(1 << 13) - 693 - 117,
(1 << 13) - 648 - 117,
(1 << 13) - 619 - 117,
(1 << 13) - 575 - 117,
(1 << 13) - 531 - 117,
(1 << 13) - 501 - 117,
4, 108,
0,
0,
0,
0,
1, 175,
0x0410,
1, 179,
8192, // P_fft_nb_to_cut
6, 181,
0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
0x2800,
0x2800,
0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
0x2800,
0x2800,
2, 193,
0x0666, // P_pha3_thres
0x0000, // P_cti_use_cpe, P_cti_use_prog
2, 205,
0x200f, // P_cspu_regul, P_cspu_win_cut
0x000f, // P_des_shift_work
5, 215,
0x023d, // P_adp_regul_cnt
0x00a4, // P_adp_noise_cnt
0x00a4, // P_adp_regul_ext
0x7ff0, // P_adp_noise_ext
0x3ccc, // P_adp_fil
1, 230,
0x0000, // P_2d_byp_ti_num
1, 263,
0x800, //P_equal_thres_wgn
1, 268,
(2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode
1, 270,
0x0001, // P_div_lock0_wait
1, 285,
0x0020, //p_fec_
1, 299,
0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
1, 338,
(1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
(1 << 10) |
(0 << 9) | /* P_ctrl_pre_freq_inh=0 */
(3 << 5) | /* P_ctrl_pre_freq_step=3 */
(1 << 0), /* P_pre_freq_win_len=1 */
0,
};
static u16 dib8000_identify(struct i2c_device *client)
{
u16 value;
//because of glitches sometimes
value = dib8000_i2c_read16(client, 896);
if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
dprintk("wrong Vendor ID (read=0x%x)", value);
return 0;
}
value = dib8000_i2c_read16(client, 897);
if (value != 0x8000 && value != 0x8001 &&
value != 0x8002 && value != 0x8090) {
dprintk("wrong Device ID (%x)", value);
return 0;
}
switch (value) {
case 0x8000:
dprintk("found DiB8000A");
break;
case 0x8001:
dprintk("found DiB8000B");
break;
case 0x8002:
dprintk("found DiB8000C");
break;
case 0x8090:
dprintk("found DiB8096P");
break;
}
return value;
}
static int dib8000_reset(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
if ((state->revision = dib8000_identify(&state->i2c)) == 0)
return -EINVAL;
/* sram lead in, rdy */
if (state->revision != 0x8090)
dib8000_write_word(state, 1287, 0x0003);
if (state->revision == 0x8000)
dprintk("error : dib8000 MA not supported");
dibx000_reset_i2c_master(&state->i2c_master);
dib8000_set_power_mode(state, DIB8000_POWER_ALL);
/* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
dib8000_set_adc_state(state, DIBX000_VBG_ENABLE);
/* restart all parts */
dib8000_write_word(state, 770, 0xffff);
dib8000_write_word(state, 771, 0xffff);
dib8000_write_word(state, 772, 0xfffc);
if (state->revision == 0x8090)
dib8000_write_word(state, 1280, 0x0045);
else
dib8000_write_word(state, 1280, 0x004d);
dib8000_write_word(state, 1281, 0x000c);
dib8000_write_word(state, 770, 0x0000);
dib8000_write_word(state, 771, 0x0000);
dib8000_write_word(state, 772, 0x0000);
dib8000_write_word(state, 898, 0x0004); // sad
dib8000_write_word(state, 1280, 0x0000);
dib8000_write_word(state, 1281, 0x0000);
/* drives */
if (state->revision != 0x8090) {
if (state->cfg.drives)
dib8000_write_word(state, 906, state->cfg.drives);
else {
dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.");
/* min drive SDRAM - not optimal - adjust */
dib8000_write_word(state, 906, 0x2d98);
}
}
dib8000_reset_pll(state);
if (state->revision != 0x8090)
dib8000_write_word(state, 898, 0x0004);
if (dib8000_reset_gpio(state) != 0)
dprintk("GPIO reset was not successful.");
if ((state->revision != 0x8090) &&
(dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
dprintk("OUTPUT_MODE could not be resetted.");
state->current_agc = NULL;
// P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
/* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
if (state->cfg.pll->ifreq == 0)
dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
else
dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
{
u16 l = 0, r;
const u16 *n;
n = dib8000_defaults;
l = *n++;
while (l) {
r = *n++;
do {
dib8000_write_word(state, r, *n++);
r++;
} while (--l);
l = *n++;
}
}
if (state->revision != 0x8090)
dib8000_write_word(state, 903, (0 << 4) | 2);
state->isdbt_cfg_loaded = 0;
//div_cfg override for special configs
if (state->cfg.div_cfg != 0)
dib8000_write_word(state, 903, state->cfg.div_cfg);
/* unforce divstr regardless whether i2c enumeration was done or not */
dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
dib8000_set_bandwidth(fe, 6000);
dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
if (state->revision != 0x8090) {
dib8000_sad_calib(state);
dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
}
dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
return 0;
}
static void dib8000_restart_agc(struct dib8000_state *state)
{
// P_restart_iqc & P_restart_agc
dib8000_write_word(state, 770, 0x0a00);
dib8000_write_word(state, 770, 0x0000);
}
static int dib8000_update_lna(struct dib8000_state *state)
{
u16 dyn_gain;
if (state->cfg.update_lna) {
// read dyn_gain here (because it is demod-dependent and not tuner)
dyn_gain = dib8000_read_word(state, 390);
if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
dib8000_restart_agc(state);
return 1;
}
}
return 0;
}
static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
{
struct dibx000_agc_config *agc = NULL;
int i;
u16 reg;
if (state->current_band == band && state->current_agc != NULL)
return 0;
state->current_band = band;
for (i = 0; i < state->cfg.agc_config_count; i++)
if (state->cfg.agc[i].band_caps & band) {
agc = &state->cfg.agc[i];
break;
}
if (agc == NULL) {
dprintk("no valid AGC configuration found for band 0x%02x", band);
return -EINVAL;
}
state->current_agc = agc;
/* AGC */
dib8000_write_word(state, 76, agc->setup);
dib8000_write_word(state, 77, agc->inv_gain);
dib8000_write_word(state, 78, agc->time_stabiliz);
dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
// Demod AGC loop configuration
dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
/* AGC continued */
if (state->wbd_ref != 0)
dib8000_write_word(state, 106, state->wbd_ref);
else // use default
dib8000_write_word(state, 106, agc->wbd_ref);
if (state->revision == 0x8090) {
reg = dib8000_read_word(state, 922) & (0x3 << 2);
dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
}
dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
dib8000_write_word(state, 108, agc->agc1_max);
dib8000_write_word(state, 109, agc->agc1_min);
dib8000_write_word(state, 110, agc->agc2_max);
dib8000_write_word(state, 111, agc->agc2_min);
dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
dib8000_write_word(state, 75, agc->agc1_pt3);
if (state->revision != 0x8090)
dib8000_write_word(state, 923,
(dib8000_read_word(state, 923) & 0xffe3) |
(agc->wbd_inv << 4) | (agc->wbd_sel << 2));
return 0;
}
void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
dib8000_set_adc_state(state, DIBX000_ADC_ON);
dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
}
EXPORT_SYMBOL(dib8000_pwm_agc_reset);
static int dib8000_agc_soft_split(struct dib8000_state *state)
{
u16 agc, split_offset;
if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
return FE_CALLBACK_TIME_NEVER;
// n_agc_global
agc = dib8000_read_word(state, 390);
if (agc > state->current_agc->split.min_thres)
split_offset = state->current_agc->split.min;
else if (agc < state->current_agc->split.max_thres)
split_offset = state->current_agc->split.max;
else
split_offset = state->current_agc->split.max *
(agc - state->current_agc->split.min_thres) /
(state->current_agc->split.max_thres - state->current_agc->split.min_thres);
dprintk("AGC split_offset: %d", split_offset);
// P_agc_force_split and P_agc_split_offset
dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
return 5000;
}
static int dib8000_agc_startup(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
enum frontend_tune_state *tune_state = &state->tune_state;
int ret = 0;
u16 reg, upd_demod_gain_period = 0x8000;
switch (*tune_state) {
case CT_AGC_START:
// set power-up level: interf+analog+AGC
if (state->revision != 0x8090)
dib8000_set_adc_state(state, DIBX000_ADC_ON);
else {
dib8000_set_power_mode(state, DIB8000_POWER_ALL);
reg = dib8000_read_word(state, 1947)&0xff00;
dib8000_write_word(state, 1946,
upd_demod_gain_period & 0xFFFF);
/* bit 14 = enDemodGain */
dib8000_write_word(state, 1947, reg | (1<<14) |
((upd_demod_gain_period >> 16) & 0xFF));
/* enable adc i & q */
reg = dib8000_read_word(state, 1920);
dib8000_write_word(state, 1920, (reg | 0x3) &
(~(1 << 7)));
}
if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
*tune_state = CT_AGC_STOP;
state->status = FE_STATUS_TUNE_FAILED;
break;
}
ret = 70;
*tune_state = CT_AGC_STEP_0;
break;
case CT_AGC_STEP_0:
//AGC initialization
if (state->cfg.agc_control)
state->cfg.agc_control(fe, 1);
dib8000_restart_agc(state);
// wait AGC rough lock time
ret = 50;
*tune_state = CT_AGC_STEP_1;
break;
case CT_AGC_STEP_1:
// wait AGC accurate lock time
ret = 70;
if (dib8000_update_lna(state))
// wait only AGC rough lock time
ret = 50;
else
*tune_state = CT_AGC_STEP_2;
break;
case CT_AGC_STEP_2:
dib8000_agc_soft_split(state);
if (state->cfg.agc_control)
state->cfg.agc_control(fe, 0);
*tune_state = CT_AGC_STOP;
break;
default:
ret = dib8000_agc_soft_split(state);
break;
}
return ret;
}
static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
{
u16 reg;
drive &= 0x7;
/* drive host bus 2, 3, 4 */
reg = dib8000_read_word(state, 1798) &
~(0x7 | (0x7 << 6) | (0x7 << 12));
reg |= (drive<<12) | (drive<<6) | drive;
dib8000_write_word(state, 1798, reg);
/* drive host bus 5,6 */
reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
reg |= (drive<<8) | (drive<<2);
dib8000_write_word(state, 1799, reg);
/* drive host bus 7, 8, 9 */
reg = dib8000_read_word(state, 1800) &
~(0x7 | (0x7 << 6) | (0x7 << 12));
reg |= (drive<<12) | (drive<<6) | drive;
dib8000_write_word(state, 1800, reg);
/* drive host bus 10, 11 */
reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
reg |= (drive<<8) | (drive<<2);
dib8000_write_word(state, 1801, reg);
/* drive host bus 12, 13, 14 */
reg = dib8000_read_word(state, 1802) &
~(0x7 | (0x7 << 6) | (0x7 << 12));
reg |= (drive<<12) | (drive<<6) | drive;
dib8000_write_word(state, 1802, reg);
}
static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
u32 insertExtSynchro, u32 syncSize)
{
u32 quantif = 3;
u32 nom = (insertExtSynchro * P_Kin+syncSize);
u32 denom = P_Kout;
u32 syncFreq = ((nom << quantif) / denom);
if ((syncFreq & ((1 << quantif) - 1)) != 0)
syncFreq = (syncFreq >> quantif) + 1;
else
syncFreq = (syncFreq >> quantif);
if (syncFreq != 0)
syncFreq = syncFreq - 1;
return syncFreq;
}
static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
u32 syncWord, u32 syncSize)
{
dprintk("Configure DibStream Tx");
dib8000_write_word(state, 1615, 1);
dib8000_write_word(state, 1603, P_Kin);
dib8000_write_word(state, 1605, P_Kout);
dib8000_write_word(state, 1606, insertExtSynchro);
dib8000_write_word(state, 1608, synchroMode);
dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
dib8000_write_word(state, 1610, syncWord & 0xffff);
dib8000_write_word(state, 1612, syncSize);
dib8000_write_word(state, 1615, 0);
}
static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
u32 syncWord, u32 syncSize, u32 dataOutRate)
{
u32 syncFreq;
dprintk("Configure DibStream Rx synchroMode = %d", synchroMode);
if ((P_Kin != 0) && (P_Kout != 0)) {
syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
insertExtSynchro, syncSize);
dib8000_write_word(state, 1542, syncFreq);
}
dib8000_write_word(state, 1554, 1);
dib8000_write_word(state, 1536, P_Kin);
dib8000_write_word(state, 1537, P_Kout);
dib8000_write_word(state, 1539, synchroMode);
dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
dib8000_write_word(state, 1541, syncWord & 0xffff);
dib8000_write_word(state, 1543, syncSize);
dib8000_write_word(state, 1544, dataOutRate);
dib8000_write_word(state, 1554, 0);
}
static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
{
u16 reg_1287;
reg_1287 = dib8000_read_word(state, 1287);
switch (onoff) {
case 1:
reg_1287 &= ~(1 << 8);
break;
case 0:
reg_1287 |= (1 << 8);
break;
}
dib8000_write_word(state, 1287, reg_1287);
}
static void dib8096p_configMpegMux(struct dib8000_state *state,
u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
{
u16 reg_1287;
dprintk("Enable Mpeg mux");
dib8096p_enMpegMux(state, 0);
/* If the input mode is MPEG do not divide the serial clock */
if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
enSerialClkDiv2 = 0;
reg_1287 = ((pulseWidth & 0x1f) << 3) |
((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
dib8000_write_word(state, 1287, reg_1287);
dib8096p_enMpegMux(state, 1);
}
static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
{
u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
switch (mode) {
case MPEG_ON_DIBTX:
dprintk("SET MPEG ON DIBSTREAM TX");
dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
reg_1288 |= (1 << 9); break;
case DIV_ON_DIBTX:
dprintk("SET DIV_OUT ON DIBSTREAM TX");
dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
reg_1288 |= (1 << 8); break;
case ADC_ON_DIBTX:
dprintk("SET ADC_OUT ON DIBSTREAM TX");
dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
reg_1288 |= (1 << 7); break;
default:
break;
}
dib8000_write_word(state, 1288, reg_1288);
}
static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
{
u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
switch (mode) {
case DEMOUT_ON_HOSTBUS:
dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
dib8096p_enMpegMux(state, 0);
reg_1288 |= (1 << 6);
break;
case DIBTX_ON_HOSTBUS:
dprintk("SET DIBSTREAM TX ON HOST BUS");
dib8096p_enMpegMux(state, 0);
reg_1288 |= (1 << 5);
break;
case MPEG_ON_HOSTBUS:
dprintk("SET MPEG MUX ON HOST BUS");
reg_1288 |= (1 << 4);
break;
default:
break;
}
dib8000_write_word(state, 1288, reg_1288);
}
static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 reg_1287;
switch (onoff) {
case 0: /* only use the internal way - not the diversity input */
dprintk("%s mode OFF : by default Enable Mpeg INPUT",
__func__);
/* outputRate = 8 */
dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
/* Do not divide the serial clock of MPEG MUX in
SERIAL MODE in case input mode MPEG is used */
reg_1287 = dib8000_read_word(state, 1287);
/* enSerialClkDiv2 == 1 ? */
if ((reg_1287 & 0x1) == 1) {
/* force enSerialClkDiv2 = 0 */
reg_1287 &= ~0x1;
dib8000_write_word(state, 1287, reg_1287);
}
state->input_mode_mpeg = 1;
break;
case 1: /* both ways */
case 2: /* only the diversity input */
dprintk("%s ON : Enable diversity INPUT", __func__);
dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
state->input_mode_mpeg = 0;
break;
}
dib8000_set_diversity_in(state->fe[0], onoff);
return 0;
}
static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 outreg, smo_mode, fifo_threshold;
u8 prefer_mpeg_mux_use = 1;
int ret = 0;
dib8096p_host_bus_drive(state, 1);
fifo_threshold = 1792;
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
outreg = dib8000_read_word(state, 1286) &
~((1 << 10) | (0x7 << 6) | (1 << 1));
switch (mode) {
case OUTMODE_HIGH_Z:
outreg = 0;
break;
case OUTMODE_MPEG2_SERIAL:
if (prefer_mpeg_mux_use) {
dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux");
dib8096p_configMpegMux(state, 3, 1, 1);
dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
} else {/* Use Smooth block */
dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc");
dib8096p_setHostBusMux(state,
DEMOUT_ON_HOSTBUS);
outreg |= (2 << 6) | (0 << 1);
}
break;
case OUTMODE_MPEG2_PAR_GATED_CLK:
if (prefer_mpeg_mux_use) {
dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
dib8096p_configMpegMux(state, 2, 0, 0);
dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
} else { /* Use Smooth block */
dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block");
dib8096p_setHostBusMux(state,
DEMOUT_ON_HOSTBUS);
outreg |= (0 << 6);
}
break;
case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block");
dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (1 << 6);
break;
case OUTMODE_MPEG2_FIFO:
/* Using Smooth block because not supported
by new Mpeg Mux bloc */
dprintk("dib8096P setting output mode TS_FIFO using Smooth block");
dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
outreg |= (5 << 6);
smo_mode |= (3 << 1);
fifo_threshold = 512;
break;
case OUTMODE_DIVERSITY:
dprintk("dib8096P setting output mode MODE_DIVERSITY");
dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
break;
case OUTMODE_ANALOG_ADC:
dprintk("dib8096P setting output mode MODE_ANALOG_ADC");
dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
break;
}
if (mode != OUTMODE_HIGH_Z)
outreg |= (1<<10);
dprintk("output_mpeg2_in_188_bytes = %d",
state->cfg.output_mpeg2_in_188_bytes);
if (state->cfg.output_mpeg2_in_188_bytes)
smo_mode |= (1 << 5);
ret |= dib8000_write_word(state, 299, smo_mode);
/* synchronous fread */
ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
ret |= dib8000_write_word(state, 1286, outreg);
return ret;
}
static int map_addr_to_serpar_number(struct i2c_msg *msg)
{
if (msg->buf[0] <= 15)
msg->buf[0] -= 1;
else if (msg->buf[0] == 17)
msg->buf[0] = 15;
else if (msg->buf[0] == 16)
msg->buf[0] = 17;
else if (msg->buf[0] == 19)
msg->buf[0] = 16;
else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
msg->buf[0] -= 3;
else if (msg->buf[0] == 28)
msg->buf[0] = 23;
else if (msg->buf[0] == 99)
msg->buf[0] = 99;
else
return -EINVAL;
return 0;
}
static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u8 n_overflow = 1;
u16 i = 1000;
u16 serpar_num = msg[0].buf[0];
while (n_overflow == 1 && i) {
n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
i--;
if (i == 0)
dprintk("Tuner ITF: write busy (overflow)");
}
dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
return num;
}
static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u8 n_overflow = 1, n_empty = 1;
u16 i = 1000;
u16 serpar_num = msg[0].buf[0];
u16 read_word;
while (n_overflow == 1 && i) {
n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
i--;
if (i == 0)
dprintk("TunerITF: read busy (overflow)");
}
dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
i = 1000;
while (n_empty == 1 && i) {
n_empty = dib8000_read_word(state, 1984)&0x1;
i--;
if (i == 0)
dprintk("TunerITF: read busy (empty)");
}
read_word = dib8000_read_word(state, 1987);
msg[1].buf[0] = (read_word >> 8) & 0xff;
msg[1].buf[1] = (read_word) & 0xff;
return num;
}
static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
if (map_addr_to_serpar_number(&msg[0]) == 0) {
if (num == 1) /* write */
return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
else /* read */
return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
}
return num;
}
static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num, u16 apb_address)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u16 word;
if (num == 1) { /* write */
dib8000_write_word(state, apb_address,
((msg[0].buf[1] << 8) | (msg[0].buf[2])));
} else {
word = dib8000_read_word(state, apb_address);
msg[1].buf[0] = (word >> 8) & 0xff;
msg[1].buf[1] = (word) & 0xff;
}
return num;
}
static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
u16 apb_address = 0, word;
int i = 0;
switch (msg[0].buf[0]) {
case 0x12:
apb_address = 1920;
break;
case 0x14:
apb_address = 1921;
break;
case 0x24:
apb_address = 1922;
break;
case 0x1a:
apb_address = 1923;
break;
case 0x22:
apb_address = 1924;
break;
case 0x33:
apb_address = 1926;
break;
case 0x34:
apb_address = 1927;
break;
case 0x35:
apb_address = 1928;
break;
case 0x36:
apb_address = 1929;
break;
case 0x37:
apb_address = 1930;
break;
case 0x38:
apb_address = 1931;
break;
case 0x39:
apb_address = 1932;
break;
case 0x2a:
apb_address = 1935;
break;
case 0x2b:
apb_address = 1936;
break;
case 0x2c:
apb_address = 1937;
break;
case 0x2d:
apb_address = 1938;
break;
case 0x2e:
apb_address = 1939;
break;
case 0x2f:
apb_address = 1940;
break;
case 0x30:
apb_address = 1941;
break;
case 0x31:
apb_address = 1942;
break;
case 0x32:
apb_address = 1943;
break;
case 0x3e:
apb_address = 1944;
break;
case 0x3f:
apb_address = 1945;
break;
case 0x40:
apb_address = 1948;
break;
case 0x25:
apb_address = 936;
break;
case 0x26:
apb_address = 937;
break;
case 0x27:
apb_address = 938;
break;
case 0x28:
apb_address = 939;
break;
case 0x1d:
/* get sad sel request */
i = ((dib8000_read_word(state, 921) >> 12)&0x3);
word = dib8000_read_word(state, 924+i);
msg[1].buf[0] = (word >> 8) & 0xff;
msg[1].buf[1] = (word) & 0xff;
return num;
case 0x1f:
if (num == 1) { /* write */
word = (u16) ((msg[0].buf[1] << 8) |
msg[0].buf[2]);
/* in the VGAMODE Sel are located on bit 0/1 */
word &= 0x3;
word = (dib8000_read_word(state, 921) &
~(3<<12)) | (word<<12);
/* Set the proper input */
dib8000_write_word(state, 921, word);
return num;
}
}
if (apb_address != 0) /* R/W acces via APB */
return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
else /* R/W access via SERPAR */
return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
return 0;
}
static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static struct i2c_algorithm dib8096p_tuner_xfer_algo = {
.master_xfer = dib8096p_tuner_xfer,
.functionality = dib8096p_i2c_func,
};
struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
{
struct dib8000_state *st = fe->demodulator_priv;
return &st->dib8096p_tuner_adap;
}
EXPORT_SYMBOL(dib8096p_get_i2c_tuner);
int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 en_cur_state;
dprintk("sleep dib8096p: %d", onoff);
en_cur_state = dib8000_read_word(state, 1922);
/* LNAs and MIX are ON and therefore it is a valid configuration */
if (en_cur_state > 0xff)
state->tuner_enable = en_cur_state ;
if (onoff)
en_cur_state &= 0x00ff;
else {
if (state->tuner_enable != 0)
en_cur_state = state->tuner_enable;
}
dib8000_write_word(state, 1922, en_cur_state);
return 0;
}
EXPORT_SYMBOL(dib8096p_tuner_sleep);
static const s32 lut_1000ln_mant[] =
{
908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
};
s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
{
struct dib8000_state *state = fe->demodulator_priv;
u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
s32 val;
val = dib8000_read32(state, 384);
if (mode) {
tmp_val = val;
while (tmp_val >>= 1)
exp++;
mant = (val * 1000 / (1<<exp));
ix = (u8)((mant-1000)/100); /* index of the LUT */
val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
val = (val*256)/1000;
}
return val;
}
EXPORT_SYMBOL(dib8000_get_adc_power);
int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
{
struct dib8000_state *state = fe->demodulator_priv;
int val = 0;
switch (IQ) {
case 1:
val = dib8000_read_word(state, 403);
break;
case 0:
val = dib8000_read_word(state, 404);
break;
}
if (val & 0x200)
val -= 1024;
return val;
}
EXPORT_SYMBOL(dib8090p_get_dc_power);
static void dib8000_update_timf(struct dib8000_state *state)
{
u32 timf = state->timf = dib8000_read32(state, 435);
dib8000_write_word(state, 29, (u16) (timf >> 16));
dib8000_write_word(state, 30, (u16) (timf & 0xffff));
dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
}
u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
{
struct dib8000_state *state = fe->demodulator_priv;
switch (op) {
case DEMOD_TIMF_SET:
state->timf = timf;
break;
case DEMOD_TIMF_UPDATE:
dib8000_update_timf(state);
break;
case DEMOD_TIMF_GET:
break;
}
dib8000_set_bandwidth(state->fe[0], 6000);
return state->timf;
}
EXPORT_SYMBOL(dib8000_ctrl_timf);
static const u16 adc_target_16dB[11] = {
(1 << 13) - 825 - 117,
(1 << 13) - 837 - 117,
(1 << 13) - 811 - 117,
(1 << 13) - 766 - 117,
(1 << 13) - 737 - 117,
(1 << 13) - 693 - 117,
(1 << 13) - 648 - 117,
(1 << 13) - 619 - 117,
(1 << 13) - 575 - 117,
(1 << 13) - 531 - 117,
(1 << 13) - 501 - 117
};
static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
{
u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0;
u8 guard, crate, constellation, timeI;
u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
const s16 *ncoeff = NULL, *ana_fe;
u16 tmcc_pow = 0;
u16 coff_pow = 0x2800;
u16 init_prbs = 0xfff;
u16 ana_gain = 0;
if (state->revision == 0x8090)
dib8000_init_sdram(state);
if (state->ber_monitored_layer != LAYER_ALL)
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer);
else
dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
i = dib8000_read_word(state, 26) & 1; // P_dds_invspec
dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i);
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
//compute new dds_freq for the seg and adjust prbs
int seg_offset =
state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx -
(state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
(state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2);
int clk = state->cfg.pll->internal;
u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26)
int dds_offset = seg_offset * segtodds;
int new_dds, sub_channel;
if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
dds_offset -= (int)(segtodds / 2);
if (state->cfg.pll->ifreq == 0) {
if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) {
dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
new_dds = dds_offset;
} else
new_dds = dds_offset;
// We shift tuning frequency if the wanted segment is :
// - the segment of center frequency with an odd total number of segments
// - the segment to the left of center frequency with an even total number of segments
// - the segment to the right of center frequency with an even total number of segments
if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT)
&& (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
&& (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
&& (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
|| (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
&& (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2)))
|| (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
&& (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
)) {
new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26)
}
} else {
if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0)
new_dds = state->cfg.pll->ifreq - dds_offset;
else
new_dds = state->cfg.pll->ifreq + dds_offset;
}
dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
else
sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
sub_channel -= 6;
if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
|| state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1
dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1
} else {
dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); //adp_pass =0
dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0
}
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
switch (sub_channel) {
case -6:
init_prbs = 0x0;
break; // 41, 0, 1
case -5:
init_prbs = 0x423;
break; // 02~04
case -4:
init_prbs = 0x9;
break; // 05~07
case -3:
init_prbs = 0x5C7;
break; // 08~10
case -2:
init_prbs = 0x7A6;
break; // 11~13
case -1:
init_prbs = 0x3D8;
break; // 14~16
case 0:
init_prbs = 0x527;
break; // 17~19
case 1:
init_prbs = 0x7FF;
break; // 20~22
case 2:
init_prbs = 0x79B;
break; // 23~25
case 3:
init_prbs = 0x3D6;
break; // 26~28
case 4:
init_prbs = 0x3A2;
break; // 29~31
case 5:
init_prbs = 0x53B;
break; // 32~34
case 6:
init_prbs = 0x2F4;
break; // 35~37
default:
case 7:
init_prbs = 0x213;
break; // 38~40
}
break;
case TRANSMISSION_MODE_4K:
switch (sub_channel) {
case -6:
init_prbs = 0x0;
break; // 41, 0, 1
case -5:
init_prbs = 0x208;
break; // 02~04
case -4:
init_prbs = 0xC3;
break; // 05~07
case -3:
init_prbs = 0x7B9;
break; // 08~10
case -2:
init_prbs = 0x423;
break; // 11~13
case -1:
init_prbs = 0x5C7;
break; // 14~16
case 0:
init_prbs = 0x3D8;
break; // 17~19
case 1:
init_prbs = 0x7FF;
break; // 20~22
case 2:
init_prbs = 0x3D6;
break; // 23~25
case 3:
init_prbs = 0x53B;
break; // 26~28
case 4:
init_prbs = 0x213;
break; // 29~31
case 5:
init_prbs = 0x29;
break; // 32~34
case 6:
init_prbs = 0xD0;
break; // 35~37
default:
case 7:
init_prbs = 0x48E;
break; // 38~40
}
break;
default:
case TRANSMISSION_MODE_8K:
switch (sub_channel) {
case -6:
init_prbs = 0x0;
break; // 41, 0, 1
case -5:
init_prbs = 0x740;
break; // 02~04
case -4:
init_prbs = 0x069;
break; // 05~07
case -3:
init_prbs = 0x7DD;
break; // 08~10
case -2:
init_prbs = 0x208;
break; // 11~13
case -1:
init_prbs = 0x7B9;
break; // 14~16
case 0:
init_prbs = 0x5C7;
break; // 17~19
case 1:
init_prbs = 0x7FF;
break; // 20~22
case 2:
init_prbs = 0x53B;
break; // 23~25
case 3:
init_prbs = 0x29;
break; // 26~28
case 4:
init_prbs = 0x48E;
break; // 29~31
case 5:
init_prbs = 0x4C4;
break; // 32~34
case 6:
init_prbs = 0x367;
break; // 33~37
default:
case 7:
init_prbs = 0x684;
break; // 38~40
}
break;
}
} else {
dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
}
/*P_mode == ?? */
dib8000_write_word(state, 10, (seq << 4));
// dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000);
switch (state->fe[0]->dtv_property_cache.guard_interval) {
case GUARD_INTERVAL_1_32:
guard = 0;
break;
case GUARD_INTERVAL_1_16:
guard = 1;
break;
case GUARD_INTERVAL_1_8:
guard = 2;
break;
case GUARD_INTERVAL_1_4:
default:
guard = 3;
break;
}
dib8000_write_word(state, 1, (init_prbs << 2) | (guard & 0x3)); // ADDR 1
max_constellation = DQPSK;
for (i = 0; i < 3; i++) {
switch (state->fe[0]->dtv_property_cache.layer[i].modulation) {
case DQPSK:
constellation = 0;
break;
case QPSK:
constellation = 1;
break;
case QAM_16:
constellation = 2;
break;
case QAM_64:
default:
constellation = 3;
break;
}
switch (state->fe[0]->dtv_property_cache.layer[i].fec) {
case FEC_1_2:
crate = 1;
break;
case FEC_2_3:
crate = 2;
break;
case FEC_3_4:
crate = 3;
break;
case FEC_5_6:
crate = 5;
break;
case FEC_7_8:
default:
crate = 7;
break;
}
if ((state->fe[0]->dtv_property_cache.layer[i].interleaving > 0) &&
((state->fe[0]->dtv_property_cache.layer[i].interleaving <= 3) ||
(state->fe[0]->dtv_property_cache.layer[i].interleaving == 4 && state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1))
)
timeI = state->fe[0]->dtv_property_cache.layer[i].interleaving;
else
timeI = 0;
dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe[0]->dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
(crate << 3) | timeI);
if (state->fe[0]->dtv_property_cache.layer[i].segment_count > 0) {
switch (max_constellation) {
case DQPSK:
case QPSK:
if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_16 ||
state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
break;
case QAM_16:
if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
break;
}
}
}
mode = fft_to_mode(state);
//dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/
dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) |
((state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe[0]->dtv_property_cache.
isdbt_sb_mode & 1) << 4));
dprintk("mode = %d ; guard = %d", mode, state->fe[0]->dtv_property_cache.guard_interval);
/* signal optimization parameter */
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception) {
seg_diff_mask = (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
for (i = 1; i < 3; i++)
nbseg_diff +=
(state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
for (i = 0; i < nbseg_diff; i++)
seg_diff_mask |= 1 << permu_seg[i + 1];
} else {
for (i = 0; i < 3; i++)
nbseg_diff +=
(state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
for (i = 0; i < nbseg_diff; i++)
seg_diff_mask |= 1 << permu_seg[i];
}
dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
state->differential_constellation = (seg_diff_mask != 0);
if (state->revision != 0x8090)
dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
else
dib8096p_set_diversity_in(state->fe[0], state->diversity_onoff);
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
seg_mask13 = 0x00E0;
else // 1-segment
seg_mask13 = 0x0040;
} else
seg_mask13 = 0x1fff;
// WRITE: Mode & Diff mask
dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask);
if ((seg_diff_mask) || (state->fe[0]->dtv_property_cache.isdbt_sb_mode))
dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
else
dib8000_write_word(state, 268, (2 << 9) | 39); //init value
// ---- SMALL ----
// P_small_seg_diff
dib8000_write_word(state, 352, seg_diff_mask); // ADDR 352
dib8000_write_word(state, 353, seg_mask13); // ADDR 353
/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
// ---- SMALL ----
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
ncoeff = coeff_2k_sb_1seg_dqpsk;
else // QPSK or QAM
ncoeff = coeff_2k_sb_1seg;
} else { // 3-segments
if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
else // QPSK or QAM on external segments
ncoeff = coeff_2k_sb_3seg_0dqpsk;
} else { // QPSK or QAM on central segment
if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
ncoeff = coeff_2k_sb_3seg_1dqpsk;
else // QPSK or QAM on external segments
ncoeff = coeff_2k_sb_3seg;
}
}
break;
case TRANSMISSION_MODE_4K:
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
ncoeff = coeff_4k_sb_1seg_dqpsk;
else // QPSK or QAM
ncoeff = coeff_4k_sb_1seg;
} else { // 3-segments
if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
} else { // QPSK or QAM on external segments
ncoeff = coeff_4k_sb_3seg_0dqpsk;
}
} else { // QPSK or QAM on central segment
if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_4k_sb_3seg_1dqpsk;
} else // QPSK or QAM on external segments
ncoeff = coeff_4k_sb_3seg;
}
}
break;
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
default:
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
ncoeff = coeff_8k_sb_1seg_dqpsk;
else // QPSK or QAM
ncoeff = coeff_8k_sb_1seg;
} else { // 3-segments
if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
} else { // QPSK or QAM on external segments
ncoeff = coeff_8k_sb_3seg_0dqpsk;
}
} else { // QPSK or QAM on central segment
if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_8k_sb_3seg_1dqpsk;
} else // QPSK or QAM on external segments
ncoeff = coeff_8k_sb_3seg;
}
}
break;
}
for (i = 0; i < 8; i++)
dib8000_write_word(state, 343 + i, ncoeff[i]);
}
// P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
dib8000_write_word(state, 351,
(state->fe[0]->dtv_property_cache.isdbt_sb_mode << 9) | (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
// ---- COFF ----
// Carloff, the most robust
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
// P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
// P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
dib8000_write_word(state, 187,
(4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 2)
| 0x3);
/* // P_small_coef_ext_enable = 1 */
/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
// P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
if (mode == 3)
dib8000_write_word(state, 180, 0x1fcf | ((mode - 1) << 14));
else
dib8000_write_word(state, 180, 0x0fcf | ((mode - 1) << 14));
// P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1,
// P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4
dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
// P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
// P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
// P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
dib8000_write_word(state, 181, 300);
dib8000_write_word(state, 182, 150);
dib8000_write_word(state, 183, 80);
dib8000_write_word(state, 184, 300);
dib8000_write_word(state, 185, 150);
dib8000_write_word(state, 186, 80);
} else { // Sound Broadcasting mode 3 seg
// P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15
/* if (mode == 3) */
/* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
/* else */
/* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
// P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1,
// P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4
dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
// P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8
dib8000_write_word(state, 340, (16 << 6) | (8 << 0));
//P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1
dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
// P_coff_corthres_8k, 4k, 2k and P_coff_cpilthres_8k, 4k, 2k
dib8000_write_word(state, 181, 350);
dib8000_write_word(state, 182, 300);
dib8000_write_word(state, 183, 250);
dib8000_write_word(state, 184, 350);
dib8000_write_word(state, 185, 300);
dib8000_write_word(state, 186, 250);
}
} else if (state->isdbt_cfg_loaded == 0) { // if not Sound Broadcasting mode : put default values for 13 segments
dib8000_write_word(state, 180, (16 << 6) | 9);
dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
coff_pow = 0x2800;
for (i = 0; i < 6; i++)
dib8000_write_word(state, 181 + i, coff_pow);
// P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1,
// P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1
dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
// P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6
dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
// P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1
dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
}
// ---- FFT ----
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
dib8000_write_word(state, 178, 64); // P_fft_powrange=64
else
dib8000_write_word(state, 178, 32); // P_fft_powrange=32
/* make the cpil_coff_lock more robust but slower p_coff_winlen
* 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
*/
/* if ( ( nbseg_diff>0)&&(nbseg_diff<13))
dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */
dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */
dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */
if ((!state->fe[0]->dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
else
dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */
dib8000_write_word(state, 287, ~seg_mask13 | 0x1000); /* P_tmcc_seg_inh */
//dib8000_write_word(state, 288, ~seg_mask13 | seg_diff_mask); /* P_tmcc_seg_eq_inh */
if (!autosearching)
dib8000_write_word(state, 288, (~seg_mask13 | seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
else
dib8000_write_word(state, 288, 0x1fff); //disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels.
dprintk("287 = %X (%d)", ~seg_mask13 | 0x1000, ~seg_mask13 | 0x1000);
dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */
/* offset loop parameters */
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
/* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
else // Sound Broadcasting mode 3 seg
/* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
dib8000_write_word(state, 32, ((10 - mode) << 12) | (6 << 8) | 0x60);
} else
// TODO in 13 seg, timf_alpha can always be the same or not ?
/* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
/* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */
dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
else // Sound Broadcasting mode 3 seg
/* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (9 - mode));
} else
/* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode));
/* P_dvsy_sync_wait - reuse mode */
switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_8K:
mode = 256;
break;
case TRANSMISSION_MODE_4K:
mode = 128;
break;
default:
case TRANSMISSION_MODE_2K:
mode = 64;
break;
}
if (state->cfg.diversity_delay == 0)
mode = (mode * (1 << (guard)) * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo
else
mode = (mode * (1 << (guard)) * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for DVSY-fifo
mode <<= 4;
dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | mode);
/* channel estimation fine configuration */
switch (max_constellation) {
case QAM_64:
ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
coeff[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
coeff[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
coeff[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
//if (!state->cfg.hostbus_diversity) //if diversity, we should prehaps use the configuration of the max_constallation -1
break;
case QAM_16:
ana_gain = 0x7; // -1 : avoid def_est saturation when ADC target is -16dB
coeff[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
coeff[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
coeff[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
coeff[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
//if (!((state->cfg.hostbus_diversity) && (max_constellation == QAM_16)))
break;
default:
ana_gain = 0; // 0 : goes along with ADC target at -22dB to keep good mobile performance and lock at sensitivity level
coeff[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
coeff[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
coeff[2] = 0x0333; /* P_adp_regul_ext 0.1 */
coeff[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
break;
}
for (mode = 0; mode < 4; mode++)
dib8000_write_word(state, 215 + mode, coeff[mode]);
// update ana_gain depending on max constellation
dib8000_write_word(state, 116, ana_gain);
// update ADC target depending on ana_gain
if (ana_gain) { // set -16dB ADC target for ana_gain=-1
for (i = 0; i < 10; i++)
dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
} else { // set -22dB ADC target for ana_gain=0
for (i = 0; i < 10; i++)
dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
}
// ---- ANA_FE ----
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
ana_fe = ana_fe_coeff_3seg;
else // 1-segment
ana_fe = ana_fe_coeff_1seg;
} else
ana_fe = ana_fe_coeff_13seg;
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
for (mode = 0; mode < 24; mode++)
dib8000_write_word(state, 117 + mode, ana_fe[mode]);
// ---- CHAN_BLK ----
for (i = 0; i < 13; i++) {
if ((((~seg_diff_mask) >> i) & 1) == 1) {
P_cfr_left_edge += (1 << i) * ((i == 0) || ((((seg_mask13 & (~seg_diff_mask)) >> (i - 1)) & 1) == 0));
P_cfr_right_edge += (1 << i) * ((i == 12) || ((((seg_mask13 & (~seg_diff_mask)) >> (i + 1)) & 1) == 0));
}
}
dib8000_write_word(state, 222, P_cfr_left_edge); // P_cfr_left_edge
dib8000_write_word(state, 223, P_cfr_right_edge); // P_cfr_right_edge
// "P_cspu_left_edge" not used => do not care
// "P_cspu_right_edge" not used => do not care
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1
dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0
&& state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
//dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15
}
} else if (state->isdbt_cfg_loaded == 0) {
dib8000_write_word(state, 228, 0); // default value
dib8000_write_word(state, 265, 31); // default value
dib8000_write_word(state, 205, 0x200f); // init value
}
// ---- TMCC ----
for (i = 0; i < 3; i++)
tmcc_pow +=
(((state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe[0]->dtv_property_cache.layer[i].segment_count);
// Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9);
// Threshold is set at 1/4 of max power.
tmcc_pow *= (1 << (9 - 2));
dib8000_write_word(state, 290, tmcc_pow); // P_tmcc_dec_thres_2k
dib8000_write_word(state, 291, tmcc_pow); // P_tmcc_dec_thres_4k
dib8000_write_word(state, 292, tmcc_pow); // P_tmcc_dec_thres_8k
//dib8000_write_word(state, 287, (1 << 13) | 0x1000 );
// ---- PHA3 ----
if (state->isdbt_cfg_loaded == 0)
dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
state->isdbt_cfg_loaded = 0;
else
state->isdbt_cfg_loaded = 1;
}
static int dib8000_autosearch_start(struct dvb_frontend *fe)
{
u8 factor;
u32 value;
struct dib8000_state *state = fe->demodulator_priv;
int slist = 0;
state->fe[0]->dtv_property_cache.inversion = 0;
if (!state->fe[0]->dtv_property_cache.isdbt_sb_mode)
state->fe[0]->dtv_property_cache.layer[0].segment_count = 13;
state->fe[0]->dtv_property_cache.layer[0].modulation = QAM_64;
state->fe[0]->dtv_property_cache.layer[0].fec = FEC_2_3;
state->fe[0]->dtv_property_cache.layer[0].interleaving = 0;
//choose the right list, in sb, always do everything
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
slist = 7;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
} else {
if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
slist = 7;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2
} else
slist = 3;
} else {
if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
slist = 2;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
} else
slist = 0;
}
if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
dprintk("using list for autosearch : %d", slist);
dib8000_set_channel(state, (unsigned char)slist, 1);
//dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
factor = 1;
//set lock_mask values
dib8000_write_word(state, 6, 0x4);
dib8000_write_word(state, 7, 0x8);
dib8000_write_word(state, 8, 0x1000);
//set lock_mask wait time values
value = 50 * state->cfg.pll->internal * factor;
dib8000_write_word(state, 11, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
dib8000_write_word(state, 12, (u16) (value & 0xffff)); // lock0 wait time
value = 100 * state->cfg.pll->internal * factor;
dib8000_write_word(state, 13, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
dib8000_write_word(state, 14, (u16) (value & 0xffff)); // lock1 wait time
value = 1000 * state->cfg.pll->internal * factor;
dib8000_write_word(state, 15, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
dib8000_write_word(state, 16, (u16) (value & 0xffff)); // lock2 wait time
value = dib8000_read_word(state, 0);
dib8000_write_word(state, 0, (u16) ((1 << 15) | value));
dib8000_read_word(state, 1284); // reset the INT. n_irq_pending
dib8000_write_word(state, 0, (u16) value);
}
return 0;
}
static int dib8000_autosearch_irq(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 irq_pending = dib8000_read_word(state, 1284);
if (irq_pending & 0x1) { // failed
dprintk("dib8000_autosearch_irq failed");
return 1;
}
if (irq_pending & 0x2) { // succeeded
dprintk("dib8000_autosearch_irq succeeded");
return 2;
}
return 0; // still pending
}
static int dib8000_tune(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
int ret = 0;
u16 lock, value, mode = fft_to_mode(state);
// we are already tuned - just resuming from suspend
if (state == NULL)
return -EINVAL;
dib8000_set_bandwidth(fe, state->fe[0]->dtv_property_cache.bandwidth_hz / 1000);
dib8000_set_channel(state, 0, 0);
// restart demod
ret |= dib8000_write_word(state, 770, 0x4000);
ret |= dib8000_write_word(state, 770, 0x0000);
msleep(45);
/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3 */
/* ret |= dib8000_write_word(state, 29, (0 << 9) | (4 << 5) | (0 << 4) | (3 << 0) ); workaround inh_isi stays at 1 */
// never achieved a lock before - wait for timfreq to update
if (state->timf == 0) {
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
msleep(300);
else // Sound Broadcasting mode 3 seg
msleep(500);
} else // 13 seg
msleep(200);
}
if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
/* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */
dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
//dib8000_write_word(state, 32, (8 << 12) | (6 << 8) | 0x80);
/* P_ctrl_sfreq_step= (12-P_mode) P_ctrl_sfreq_inh =0 P_ctrl_pha_off_max */
ret |= dib8000_write_word(state, 37, (12 - mode) | ((5 + mode) << 5));
} else { // Sound Broadcasting mode 3 seg
/* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 alpha to check on board */
dib8000_write_word(state, 32, ((12 - mode) << 12) | (6 << 8) | 0x60);
ret |= dib8000_write_word(state, 37, (11 - mode) | ((5 + mode) << 5));
}
} else { // 13 seg
/* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 alpha to check on board */
dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x80);
ret |= dib8000_write_word(state, 37, (10 - mode) | ((5 + mode) << 5));
}
// we achieved a coff_cpil_lock - it's time to update the timf
if (state->revision != 0x8090)
lock = dib8000_read_word(state, 568);
else
lock = dib8000_read_word(state, 570);
if ((lock >> 11) & 0x1)
dib8000_update_timf(state);
//now that tune is finished, lock0 should lock on fec_mpeg to output this lock on MP_LOCK. It's changed in autosearch start
dib8000_write_word(state, 6, 0x200);
if (state->revision == 0x8002) {
value = dib8000_read_word(state, 903);
dib8000_write_word(state, 903, value & ~(1 << 3));
msleep(1);
dib8000_write_word(state, 903, value | (1 << 3));
}
return ret;
}
static int dib8000_wakeup(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
int ret;
dib8000_set_power_mode(state, DIB8000_POWER_ALL);
dib8000_set_adc_state(state, DIBX000_ADC_ON);
if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
dprintk("could not start Slow ADC");
if (state->revision != 0x8090)
dib8000_sad_calib(state);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
if (ret < 0)
return ret;
}
return 0;
}
static int dib8000_sleep(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
int ret;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
if (ret < 0)
return ret;
}
if (state->revision != 0x8090)
dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
}
enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
return state->tune_state;
}
EXPORT_SYMBOL(dib8000_get_tune_state);
int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
{
struct dib8000_state *state = fe->demodulator_priv;
state->tune_state = tune_state;
return 0;
}
EXPORT_SYMBOL(dib8000_set_tune_state);
static int dib8000_get_frontend(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 i, val = 0;
fe_status_t stat;
u8 index_frontend, sub_index_frontend;
fe->dtv_property_cache.bandwidth_hz = 6000000;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
if (stat&FE_HAS_SYNC) {
dprintk("TMCC lock on the slave%i", index_frontend);
/* synchronize the cache with the other frontends */
state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
if (sub_index_frontend != index_frontend) {
state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
for (i = 0; i < 3; i++) {
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
}
}
}
return 0;
}
}
fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
if (state->revision == 0x8090)
val = dib8000_read_word(state, 572);
else
val = dib8000_read_word(state, 570);
fe->dtv_property_cache.inversion = (val & 0x40) >> 6;
switch ((val & 0x30) >> 4) {
case 1:
fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
break;
case 3:
default:
fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
break;
}
switch (val & 0x3) {
case 0:
fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
dprintk("dib8000_get_frontend GI = 1/32 ");
break;
case 1:
fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
dprintk("dib8000_get_frontend GI = 1/16 ");
break;
case 2:
dprintk("dib8000_get_frontend GI = 1/8 ");
fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
dprintk("dib8000_get_frontend GI = 1/4 ");
fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
break;
}
val = dib8000_read_word(state, 505);
fe->dtv_property_cache.isdbt_partial_reception = val & 1;
dprintk("dib8000_get_frontend : partial_reception = %d ", fe->dtv_property_cache.isdbt_partial_reception);
for (i = 0; i < 3; i++) {
val = dib8000_read_word(state, 493 + i);
fe->dtv_property_cache.layer[i].segment_count = val & 0x0F;
dprintk("dib8000_get_frontend : Layer %d segments = %d ", i, fe->dtv_property_cache.layer[i].segment_count);
val = dib8000_read_word(state, 499 + i);
fe->dtv_property_cache.layer[i].interleaving = val & 0x3;
dprintk("dib8000_get_frontend : Layer %d time_intlv = %d ", i, fe->dtv_property_cache.layer[i].interleaving);
val = dib8000_read_word(state, 481 + i);
switch (val & 0x7) {
case 1:
fe->dtv_property_cache.layer[i].fec = FEC_1_2;
dprintk("dib8000_get_frontend : Layer %d Code Rate = 1/2 ", i);
break;
case 2:
fe->dtv_property_cache.layer[i].fec = FEC_2_3;
dprintk("dib8000_get_frontend : Layer %d Code Rate = 2/3 ", i);
break;
case 3:
fe->dtv_property_cache.layer[i].fec = FEC_3_4;
dprintk("dib8000_get_frontend : Layer %d Code Rate = 3/4 ", i);
break;
case 5:
fe->dtv_property_cache.layer[i].fec = FEC_5_6;
dprintk("dib8000_get_frontend : Layer %d Code Rate = 5/6 ", i);
break;
default:
fe->dtv_property_cache.layer[i].fec = FEC_7_8;
dprintk("dib8000_get_frontend : Layer %d Code Rate = 7/8 ", i);
break;
}
val = dib8000_read_word(state, 487 + i);
switch (val & 0x3) {
case 0:
dprintk("dib8000_get_frontend : Layer %d DQPSK ", i);
fe->dtv_property_cache.layer[i].modulation = DQPSK;
break;
case 1:
fe->dtv_property_cache.layer[i].modulation = QPSK;
dprintk("dib8000_get_frontend : Layer %d QPSK ", i);
break;
case 2:
fe->dtv_property_cache.layer[i].modulation = QAM_16;
dprintk("dib8000_get_frontend : Layer %d QAM16 ", i);
break;
case 3:
default:
dprintk("dib8000_get_frontend : Layer %d QAM64 ", i);
fe->dtv_property_cache.layer[i].modulation = QAM_64;
break;
}
}
/* synchronize the cache with the other frontends */
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception;
for (i = 0; i < 3; i++) {
state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count;
state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving;
state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;
state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation;
}
}
return 0;
}
static int dib8000_set_frontend(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 nbr_pending, exit_condition, index_frontend;
s8 index_frontend_success = -1;
int time, ret;
int time_slave = FE_CALLBACK_TIME_NEVER;
if (state->fe[0]->dtv_property_cache.frequency == 0) {
dprintk("dib8000: must at least specify frequency ");
return 0;
}
if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
dprintk("dib8000: no bandwidth specified, set to default ");
state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000;
}
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
/* synchronization of the cache */
state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
if (state->revision != 0x8090)
dib8000_set_output_mode(state->fe[index_frontend],
OUTMODE_HIGH_Z);
else
dib8096p_set_output_mode(state->fe[index_frontend],
OUTMODE_HIGH_Z);
if (state->fe[index_frontend]->ops.tuner_ops.set_params)
state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
}
/* start up the AGC */
do {
time = dib8000_agc_startup(state->fe[0]);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
time_slave = dib8000_agc_startup(state->fe[index_frontend]);
if (time == FE_CALLBACK_TIME_NEVER)
time = time_slave;
else if ((time_slave != FE_CALLBACK_TIME_NEVER) && (time_slave > time))
time = time_slave;
}
if (time != FE_CALLBACK_TIME_NEVER)
msleep(time / 10);
else
break;
exit_condition = 1;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
exit_condition = 0;
break;
}
}
} while (exit_condition == 0);
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) ||
(state->fe[0]->dtv_property_cache.inversion == INVERSION_AUTO) ||
(state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
(state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
(((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
(state->fe[0]->dtv_property_cache.layer[0].segment_count != 0xff) &&
(state->fe[0]->dtv_property_cache.layer[0].segment_count != 0) &&
((state->fe[0]->dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
(state->fe[0]->dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
(((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
(state->fe[0]->dtv_property_cache.layer[1].segment_count != 0xff) &&
(state->fe[0]->dtv_property_cache.layer[1].segment_count != 0) &&
((state->fe[0]->dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
(state->fe[0]->dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
(((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
(state->fe[0]->dtv_property_cache.layer[2].segment_count != 0xff) &&
(state->fe[0]->dtv_property_cache.layer[2].segment_count != 0) &&
((state->fe[0]->dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
(state->fe[0]->dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
(((state->fe[0]->dtv_property_cache.layer[0].segment_count == 0) ||
((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) ||
((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
int i = 100;
u8 found = 0;
u8 tune_failed = 0;
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000);
dib8000_autosearch_start(state->fe[index_frontend]);
}
do {
msleep(20);
nbr_pending = 0;
exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
if (((tune_failed >> index_frontend) & 0x1) == 0) {
found = dib8000_autosearch_irq(state->fe[index_frontend]);
switch (found) {
case 0: /* tune pending */
nbr_pending++;
break;
case 2:
dprintk("autosearch succeed on the frontend%i", index_frontend);
exit_condition = 2;
index_frontend_success = index_frontend;
break;
default:
dprintk("unhandled autosearch result");
case 1:
tune_failed |= (1 << index_frontend);
dprintk("autosearch failed for the frontend%i", index_frontend);
break;
}
}
}
/* if all tune are done and no success, exit: tune failed */
if ((nbr_pending == 0) && (exit_condition == 0))
exit_condition = 1;
} while ((exit_condition == 0) && i--);
if (exit_condition == 1) { /* tune failed */
dprintk("tune failed");
return 0;
}
dprintk("tune success on frontend%i", index_frontend_success);
dib8000_get_frontend(fe);
}
for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
ret = dib8000_tune(state->fe[index_frontend]);
/* set output mode and diversity input */
if (state->revision != 0x8090) {
dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
for (index_frontend = 1;
(index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
(state->fe[index_frontend] != NULL);
index_frontend++) {
dib8000_set_output_mode(state->fe[index_frontend],
OUTMODE_DIVERSITY);
dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
}
/* turn off the diversity of the last chip */
dib8000_set_diversity_in(state->fe[index_frontend-1], 0);
} else {
dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
if (state->cfg.enMpegOutput == 0) {
dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
}
for (index_frontend = 1;
(index_frontend < MAX_NUMBER_OF_FRONTENDS) &&
(state->fe[index_frontend] != NULL);
index_frontend++) {
dib8096p_set_output_mode(state->fe[index_frontend],
OUTMODE_DIVERSITY);
dib8096p_set_diversity_in(state->fe[index_frontend-1], 1);
}
/* turn off the diversity of the last chip */
dib8096p_set_diversity_in(state->fe[index_frontend-1], 0);
}
return ret;
}
static u16 dib8000_read_lock(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
if (state->revision == 0x8090)
return dib8000_read_word(state, 570);
return dib8000_read_word(state, 568);
}
static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 lock_slave = 0, lock;
u8 index_frontend;
if (state->revision == 0x8090)
lock = dib8000_read_word(state, 570);
else
lock = dib8000_read_word(state, 568);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
*stat = 0;
if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
*stat |= FE_HAS_SIGNAL;
if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
*stat |= FE_HAS_CARRIER;
if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
*stat |= FE_HAS_SYNC;
if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
*stat |= FE_HAS_LOCK;
if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
}
return 0;
}
static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct dib8000_state *state = fe->demodulator_priv;
/* 13 segments */
if (state->revision == 0x8090)
*ber = (dib8000_read_word(state, 562) << 16) |
dib8000_read_word(state, 563);
else
*ber = (dib8000_read_word(state, 560) << 16) |
dib8000_read_word(state, 561);
return 0;
}
static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
{
struct dib8000_state *state = fe->demodulator_priv;
/* packet error on 13 seg */
if (state->revision == 0x8090)
*unc = dib8000_read_word(state, 567);
else
*unc = dib8000_read_word(state, 565);
return 0;
}
static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
u16 val;
*strength = 0;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
if (val > 65535 - *strength)
*strength = 65535;
else
*strength += val;
}
val = 65535 - dib8000_read_word(state, 390);
if (val > 65535 - *strength)
*strength = 65535;
else
*strength += val;
return 0;
}
static u32 dib8000_get_snr(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u32 n, s, exp;
u16 val;
if (state->revision != 0x8090)
val = dib8000_read_word(state, 542);
else
val = dib8000_read_word(state, 544);
n = (val >> 6) & 0xff;
exp = (val & 0x3f);
if ((exp & 0x20) != 0)
exp -= 0x40;
n <<= exp+16;
if (state->revision != 0x8090)
val = dib8000_read_word(state, 543);
else
val = dib8000_read_word(state, 545);
s = (val >> 6) & 0xff;
exp = (val & 0x3f);
if ((exp & 0x20) != 0)
exp -= 0x40;
s <<= exp+16;
if (n > 0) {
u32 t = (s/n) << 16;
return t + ((s << 16) - n*t) / n;
}
return 0xffffffff;
}
static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend;
u32 snr_master;
snr_master = dib8000_get_snr(fe);
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
snr_master += dib8000_get_snr(state->fe[index_frontend]);
if ((snr_master >> 16) != 0) {
snr_master = 10*intlog10(snr_master>>16);
*snr = snr_master / ((1 << 24) / 10);
}
else
*snr = 0;
return 0;
}
int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend = 1;
while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
index_frontend++;
if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
state->fe[index_frontend] = fe_slave;
return 0;
}
dprintk("too many slave frontend");
return -ENOMEM;
}
EXPORT_SYMBOL(dib8000_set_slave_frontend);
int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
u8 index_frontend = 1;
while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
index_frontend++;
if (index_frontend != 1) {
dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
state->fe[index_frontend] = NULL;
return 0;
}
dprintk("no frontend to be removed");
return -ENODEV;
}
EXPORT_SYMBOL(dib8000_remove_slave_frontend);
struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
{
struct dib8000_state *state = fe->demodulator_priv;
if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
return NULL;
return state->fe[slave_index];
}
EXPORT_SYMBOL(dib8000_get_slave_frontend);
int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
u8 default_addr, u8 first_addr, u8 is_dib8096p)
{
int k = 0, ret = 0;
u8 new_addr = 0;
struct i2c_device client = {.adap = host };
client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
if (!client.i2c_write_buffer) {
dprintk("%s: not enough memory", __func__);
return -ENOMEM;
}
client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
if (!client.i2c_read_buffer) {
dprintk("%s: not enough memory", __func__);
ret = -ENOMEM;
goto error_memory_read;
}
client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
if (!client.i2c_buffer_lock) {
dprintk("%s: not enough memory", __func__);
ret = -ENOMEM;
goto error_memory_lock;
}
mutex_init(client.i2c_buffer_lock);
for (k = no_of_demods - 1; k >= 0; k--) {
/* designated i2c address */
new_addr = first_addr + (k << 1);
client.addr = new_addr;
if (!is_dib8096p)
dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
if (dib8000_identify(&client) == 0) {
/* sram lead in, rdy */
if (!is_dib8096p)
dib8000_i2c_write16(&client, 1287, 0x0003);
client.addr = default_addr;
if (dib8000_identify(&client) == 0) {
dprintk("#%d: not identified", k);
ret = -EINVAL;
goto error;
}
}
/* start diversity to pull_down div_str - just for i2c-enumeration */
dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
/* set new i2c address and force divstart */
dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
client.addr = new_addr;
dib8000_identify(&client);
dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
}
for (k = 0; k < no_of_demods; k++) {
new_addr = first_addr | (k << 1);
client.addr = new_addr;
// unforce divstr
dib8000_i2c_write16(&client, 1285, new_addr << 2);
/* deactivate div - it was just for i2c-enumeration */
dib8000_i2c_write16(&client, 1286, 0);
}
error:
kfree(client.i2c_buffer_lock);
error_memory_lock:
kfree(client.i2c_read_buffer);
error_memory_read:
kfree(client.i2c_write_buffer);
return ret;
}
EXPORT_SYMBOL(dib8000_i2c_enumeration);
static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
tune->step_size = 0;
tune->max_drift = 0;
return 0;
}
static void dib8000_release(struct dvb_frontend *fe)
{
struct dib8000_state *st = fe->demodulator_priv;
u8 index_frontend;
for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
dvb_frontend_detach(st->fe[index_frontend]);
dibx000_exit_i2c_master(&st->i2c_master);
i2c_del_adapter(&st->dib8096p_tuner_adap);
kfree(st->fe[0]);
kfree(st);
}
struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
{
struct dib8000_state *st = fe->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
}
EXPORT_SYMBOL(dib8000_get_i2c_master);
int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
struct dib8000_state *st = fe->demodulator_priv;
u16 val = dib8000_read_word(st, 299) & 0xffef;
val |= (onoff & 0x1) << 4;
dprintk("pid filter enabled %d", onoff);
return dib8000_write_word(st, 299, val);
}
EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
struct dib8000_state *st = fe->demodulator_priv;
dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
}
EXPORT_SYMBOL(dib8000_pid_filter);
static const struct dvb_frontend_ops dib8000_ops = {
.delsys = { SYS_ISDBT },
.info = {
.name = "DiBcom 8000 ISDB-T",
.frequency_min = 44250000,
.frequency_max = 867250000,
.frequency_stepsize = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
},
.release = dib8000_release,
.init = dib8000_wakeup,
.sleep = dib8000_sleep,
.set_frontend = dib8000_set_frontend,
.get_tune_settings = dib8000_fe_get_tune_settings,
.get_frontend = dib8000_get_frontend,
.read_status = dib8000_read_status,
.read_ber = dib8000_read_ber,
.read_signal_strength = dib8000_read_signal_strength,
.read_snr = dib8000_read_snr,
.read_ucblocks = dib8000_read_unc_blocks,
};
struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
{
struct dvb_frontend *fe;
struct dib8000_state *state;
dprintk("dib8000_attach");
state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
if (state == NULL)
return NULL;
fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
if (fe == NULL)
goto error;
memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
state->i2c.adap = i2c_adap;
state->i2c.addr = i2c_addr;
state->i2c.i2c_write_buffer = state->i2c_write_buffer;
state->i2c.i2c_read_buffer = state->i2c_read_buffer;
mutex_init(&state->i2c_buffer_lock);
state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
state->gpio_val = cfg->gpio_val;
state->gpio_dir = cfg->gpio_dir;
/* Ensure the output mode remains at the previous default if it's
* not specifically set by the caller.
*/
if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
state->fe[0] = fe;
fe->demodulator_priv = state;
memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
state->timf_default = cfg->pll->timf;
if (dib8000_identify(&state->i2c) == 0)
goto error;
dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
/* init 8096p tuner adapter */
strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
sizeof(state->dib8096p_tuner_adap.name));
state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
state->dib8096p_tuner_adap.algo_data = NULL;
state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
i2c_add_adapter(&state->dib8096p_tuner_adap);
dib8000_reset(fe);
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
return fe;
error:
kfree(state);
return NULL;
}
EXPORT_SYMBOL(dib8000_attach);
MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@dibcom.fr, " "Patrick Boettcher <pboettcher@dibcom.fr>");
MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
MODULE_LICENSE("GPL");
| gpl-2.0 |
bruce2728/kernel_lge_d802 | drivers/staging/rtl8712/rtl871x_security.c | 5203 | 45344 | /******************************************************************************
* rtl871x_security.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _RTL871X_SECURITY_C_
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kref.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/circ_buf.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
#include <linux/atomic.h>
#include <linux/semaphore.h>
#include "osdep_service.h"
#include "drv_types.h"
#include "wifi.h"
#include "osdep_intf.h"
/* =====WEP related===== */
#define CRC32_POLY 0x04c11db7
struct arc4context {
u32 x;
u32 y;
u8 state[256];
};
static void arcfour_init(struct arc4context *parc4ctx, u8 * key, u32 key_len)
{
u32 t, u;
u32 keyindex;
u32 stateindex;
u8 *state;
u32 counter;
state = parc4ctx->state;
parc4ctx->x = 0;
parc4ctx->y = 0;
for (counter = 0; counter < 256; counter++)
state[counter] = (u8)counter;
keyindex = 0;
stateindex = 0;
for (counter = 0; counter < 256; counter++) {
t = state[counter];
stateindex = (stateindex + key[keyindex] + t) & 0xff;
u = state[stateindex];
state[stateindex] = (u8)t;
state[counter] = (u8)u;
if (++keyindex >= key_len)
keyindex = 0;
}
}
static u32 arcfour_byte(struct arc4context *parc4ctx)
{
u32 x;
u32 y;
u32 sx, sy;
u8 *state;
state = parc4ctx->state;
x = (parc4ctx->x + 1) & 0xff;
sx = state[x];
y = (sx + parc4ctx->y) & 0xff;
sy = state[y];
parc4ctx->x = x;
parc4ctx->y = y;
state[y] = (u8)sx;
state[x] = (u8)sy;
return state[(sx + sy) & 0xff];
}
static void arcfour_encrypt(struct arc4context *parc4ctx,
u8 *dest, u8 *src, u32 len)
{
u32 i;
for (i = 0; i < len; i++)
dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);
}
static sint bcrc32initialized;
static u32 crc32_table[256];
static u8 crc32_reverseBit(u8 data)
{
return ((u8)(data << 7) & 0x80) | ((data << 5) & 0x40) | ((data << 3)
& 0x20) | ((data << 1) & 0x10) | ((data >> 1) & 0x08) |
((data >> 3) & 0x04) | ((data >> 5) & 0x02) | ((data >> 7) &
0x01);
}
static void crc32_init(void)
{
if (bcrc32initialized == 1)
return;
else {
sint i, j;
u32 c;
u8 *p = (u8 *)&c, *p1;
u8 k;
c = 0x12340000;
for (i = 0; i < 256; ++i) {
k = crc32_reverseBit((u8)i);
for (c = ((u32)k) << 24, j = 8; j > 0; --j)
c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY :
(c << 1);
p1 = (u8 *)&crc32_table[i];
p1[0] = crc32_reverseBit(p[3]);
p1[1] = crc32_reverseBit(p[2]);
p1[2] = crc32_reverseBit(p[1]);
p1[3] = crc32_reverseBit(p[0]);
}
bcrc32initialized = 1;
}
}
static u32 getcrc32(u8 *buf, u32 len)
{
u8 *p;
u32 crc;
if (bcrc32initialized == 0)
crc32_init();
crc = 0xffffffff; /* preload shift register, per CRC-32 spec */
for (p = buf; len > 0; ++p, --len)
crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8);
return ~crc; /* transmit complement, per CRC-32 spec */
}
/*
Need to consider the fragment situation
*/
void r8712_wep_encrypt(struct _adapter *padapter, u8 *pxmitframe)
{ /* exclude ICV */
unsigned char crc[4];
struct arc4context mycontext;
u32 curfragnum, length, keylength;
u8 *pframe, *payload, *iv; /*,*wepkey*/
u8 wepkey[16];
struct pkt_attrib *pattrib = &((struct xmit_frame *)
pxmitframe)->attrib;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
return;
pframe = ((struct xmit_frame *)pxmitframe)->buf_addr+TXDESC_OFFSET;
/*start to encrypt each fragment*/
if ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) {
keylength = psecuritypriv->DefKeylen[psecuritypriv->
PrivacyKeyIndex];
for (curfragnum = 0; curfragnum < pattrib->nr_frags;
curfragnum++) {
iv = pframe+pattrib->hdrlen;
memcpy(&wepkey[0], iv, 3);
memcpy(&wepkey[3], &psecuritypriv->DefKey[
psecuritypriv->PrivacyKeyIndex].skey[0],
keylength);
payload = pframe+pattrib->iv_len+pattrib->hdrlen;
if ((curfragnum + 1) == pattrib->nr_frags) {
length = pattrib->last_txcmdsz-pattrib->
hdrlen-pattrib->iv_len -
pattrib->icv_len;
*((u32 *)crc) = cpu_to_le32(getcrc32(
payload, length));
arcfour_init(&mycontext, wepkey, 3 + keylength);
arcfour_encrypt(&mycontext, payload, payload,
length);
arcfour_encrypt(&mycontext, payload + length,
crc, 4);
} else {
length = pxmitpriv->frag_len-pattrib->hdrlen -
pattrib->iv_len-pattrib->icv_len;
*((u32 *)crc) = cpu_to_le32(getcrc32(
payload, length));
arcfour_init(&mycontext, wepkey, 3 + keylength);
arcfour_encrypt(&mycontext, payload, payload,
length);
arcfour_encrypt(&mycontext, payload+length,
crc, 4);
pframe += pxmitpriv->frag_len;
pframe = (u8 *)RND4((addr_t)(pframe));
}
}
}
}
void r8712_wep_decrypt(struct _adapter *padapter, u8 *precvframe)
{
/* exclude ICV */
u8 crc[4];
struct arc4context mycontext;
u32 length, keylength;
u8 *pframe, *payload, *iv, wepkey[16];
u8 keyindex;
struct rx_pkt_attrib *prxattrib = &(((union recv_frame *)
precvframe)->u.hdr.attrib);
struct security_priv *psecuritypriv = &padapter->securitypriv;
pframe = (unsigned char *)((union recv_frame *)precvframe)->
u.hdr.rx_data;
/* start to decrypt recvframe */
if ((prxattrib->encrypt == _WEP40_) || (prxattrib->encrypt ==
_WEP104_)) {
iv = pframe + prxattrib->hdrlen;
keyindex = (iv[3] & 0x3);
keylength = psecuritypriv->DefKeylen[keyindex];
memcpy(&wepkey[0], iv, 3);
memcpy(&wepkey[3], &psecuritypriv->DefKey[
psecuritypriv->PrivacyKeyIndex].skey[0],
keylength);
length = ((union recv_frame *)precvframe)->
u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len;
payload = pframe+prxattrib->iv_len+prxattrib->hdrlen;
/* decrypt payload include icv */
arcfour_init(&mycontext, wepkey, 3 + keylength);
arcfour_encrypt(&mycontext, payload, payload, length);
/* calculate icv and compare the icv */
*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length - 4));
}
return;
}
/* 3 =====TKIP related===== */
static u32 secmicgetuint32(u8 *p)
/* Convert from Byte[] to Us4Byte32 in a portable way */
{
s32 i;
u32 res = 0;
for (i = 0; i < 4; i++)
res |= ((u32)(*p++)) << (8 * i);
return res;
}
static void secmicputuint32(u8 *p, u32 val)
/* Convert from Us4Byte32 to Byte[] in a portable way */
{
long i;
for (i = 0; i < 4; i++) {
*p++ = (u8) (val & 0xff);
val >>= 8;
}
}
static void secmicclear(struct mic_data *pmicdata)
{
/* Reset the state to the empty message. */
pmicdata->L = pmicdata->K0;
pmicdata->R = pmicdata->K1;
pmicdata->nBytesInM = 0;
pmicdata->M = 0;
}
void r8712_secmicsetkey(struct mic_data *pmicdata, u8 * key)
{
/* Set the key */
pmicdata->K0 = secmicgetuint32(key);
pmicdata->K1 = secmicgetuint32(key + 4);
/* and reset the message */
secmicclear(pmicdata);
}
static void secmicappendbyte(struct mic_data *pmicdata, u8 b)
{
/* Append the byte to our word-sized buffer */
pmicdata->M |= ((u32)b) << (8 * pmicdata->nBytesInM);
pmicdata->nBytesInM++;
/* Process the word if it is full. */
if (pmicdata->nBytesInM >= 4) {
pmicdata->L ^= pmicdata->M;
pmicdata->R ^= ROL32(pmicdata->L, 17);
pmicdata->L += pmicdata->R;
pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) |
((pmicdata->L & 0x00ff00ff) << 8);
pmicdata->L += pmicdata->R;
pmicdata->R ^= ROL32(pmicdata->L, 3);
pmicdata->L += pmicdata->R;
pmicdata->R ^= ROR32(pmicdata->L, 2);
pmicdata->L += pmicdata->R;
/* Clear the buffer */
pmicdata->M = 0;
pmicdata->nBytesInM = 0;
}
}
void r8712_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes)
{
/* This is simple */
while (nbytes > 0) {
secmicappendbyte(pmicdata, *src++);
nbytes--;
}
}
void r8712_secgetmic(struct mic_data *pmicdata, u8 *dst)
{
/* Append the minimum padding */
secmicappendbyte(pmicdata, 0x5a);
secmicappendbyte(pmicdata, 0);
secmicappendbyte(pmicdata, 0);
secmicappendbyte(pmicdata, 0);
secmicappendbyte(pmicdata, 0);
/* and then zeroes until the length is a multiple of 4 */
while (pmicdata->nBytesInM != 0)
secmicappendbyte(pmicdata, 0);
/* The appendByte function has already computed the result. */
secmicputuint32(dst, pmicdata->L);
secmicputuint32(dst + 4, pmicdata->R);
/* Reset to the empty message. */
secmicclear(pmicdata);
}
void seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_code,
u8 pri)
{
struct mic_data micdata;
u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
r8712_secmicsetkey(&micdata, key);
priority[0] = pri;
/* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */
if (header[1] & 1) { /* ToDS==1 */
r8712_secmicappend(&micdata, &header[16], 6); /* DA */
if (header[1] & 2) /* From Ds==1 */
r8712_secmicappend(&micdata, &header[24], 6);
else
r8712_secmicappend(&micdata, &header[10], 6);
} else { /* ToDS==0 */
r8712_secmicappend(&micdata, &header[4], 6); /* DA */
if (header[1] & 2) /* From Ds==1 */
r8712_secmicappend(&micdata, &header[16], 6);
else
r8712_secmicappend(&micdata, &header[10], 6);
}
r8712_secmicappend(&micdata, &priority[0], 4);
r8712_secmicappend(&micdata, data, data_len);
r8712_secgetmic(&micdata, mic_code);
}
/* macros for extraction/creation of unsigned char/unsigned short values */
#define RotR1(v16) ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15))
#define Lo8(v16) ((u8)((v16) & 0x00FF))
#define Hi8(v16) ((u8)(((v16) >> 8) & 0x00FF))
#define Lo16(v32) ((u16)((v32) & 0xFFFF))
#define Hi16(v32) ((u16)(((v32) >> 16) & 0xFFFF))
#define Mk16(hi, lo) ((lo) ^ (((u16)(hi)) << 8))
/* select the Nth 16-bit word of the temporal key unsigned char array TK[] */
#define TK16(N) Mk16(tk[2 * (N) + 1], tk[2 * (N)])
/* S-box lookup: 16 bits --> 16 bits */
#define _S_(v16) (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)])
/* fixed algorithm "parameters" */
#define PHASE1_LOOP_CNT 8 /* this needs to be "big enough" */
#define TA_SIZE 6 /* 48-bit transmitter address */
#define TK_SIZE 16 /* 128-bit temporal key */
#define P1K_SIZE 10 /* 80-bit Phase1 key */
#define RC4_KEY_SIZE 16 /* 128-bit RC4KEY (104 bits unknown) */
/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */
static const unsigned short Sbox1[2][256] = {/* Sbox for hash (can be in ROM) */
{
0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,
0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,
0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,
0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,
0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,
0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,
0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,
0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,
0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,
0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,
0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,
0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,
0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,
0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,
0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,
0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,
0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,
0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,
0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,
0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,
0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,
0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,
0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,
0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,
0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,
0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,
0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,
0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,
0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,
0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,
0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,
0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,
},
{ /* second half is unsigned char-reversed version of first! */
0xA5C6, 0x84F8, 0x99EE, 0x8DF6, 0x0DFF, 0xBDD6, 0xB1DE, 0x5491,
0x5060, 0x0302, 0xA9CE, 0x7D56, 0x19E7, 0x62B5, 0xE64D, 0x9AEC,
0x458F, 0x9D1F, 0x4089, 0x87FA, 0x15EF, 0xEBB2, 0xC98E, 0x0BFB,
0xEC41, 0x67B3, 0xFD5F, 0xEA45, 0xBF23, 0xF753, 0x96E4, 0x5B9B,
0xC275, 0x1CE1, 0xAE3D, 0x6A4C, 0x5A6C, 0x417E, 0x02F5, 0x4F83,
0x5C68, 0xF451, 0x34D1, 0x08F9, 0x93E2, 0x73AB, 0x5362, 0x3F2A,
0x0C08, 0x5295, 0x6546, 0x5E9D, 0x2830, 0xA137, 0x0F0A, 0xB52F,
0x090E, 0x3624, 0x9B1B, 0x3DDF, 0x26CD, 0x694E, 0xCD7F, 0x9FEA,
0x1B12, 0x9E1D, 0x7458, 0x2E34, 0x2D36, 0xB2DC, 0xEEB4, 0xFB5B,
0xF6A4, 0x4D76, 0x61B7, 0xCE7D, 0x7B52, 0x3EDD, 0x715E, 0x9713,
0xF5A6, 0x68B9, 0x0000, 0x2CC1, 0x6040, 0x1FE3, 0xC879, 0xEDB6,
0xBED4, 0x468D, 0xD967, 0x4B72, 0xDE94, 0xD498, 0xE8B0, 0x4A85,
0x6BBB, 0x2AC5, 0xE54F, 0x16ED, 0xC586, 0xD79A, 0x5566, 0x9411,
0xCF8A, 0x10E9, 0x0604, 0x81FE, 0xF0A0, 0x4478, 0xBA25, 0xE34B,
0xF3A2, 0xFE5D, 0xC080, 0x8A05, 0xAD3F, 0xBC21, 0x4870, 0x04F1,
0xDF63, 0xC177, 0x75AF, 0x6342, 0x3020, 0x1AE5, 0x0EFD, 0x6DBF,
0x4C81, 0x1418, 0x3526, 0x2FC3, 0xE1BE, 0xA235, 0xCC88, 0x392E,
0x5793, 0xF255, 0x82FC, 0x477A, 0xACC8, 0xE7BA, 0x2B32, 0x95E6,
0xA0C0, 0x9819, 0xD19E, 0x7FA3, 0x6644, 0x7E54, 0xAB3B, 0x830B,
0xCA8C, 0x29C7, 0xD36B, 0x3C28, 0x79A7, 0xE2BC, 0x1D16, 0x76AD,
0x3BDB, 0x5664, 0x4E74, 0x1E14, 0xDB92, 0x0A0C, 0x6C48, 0xE4B8,
0x5D9F, 0x6EBD, 0xEF43, 0xA6C4, 0xA839, 0xA431, 0x37D3, 0x8BF2,
0x32D5, 0x438B, 0x596E, 0xB7DA, 0x8C01, 0x64B1, 0xD29C, 0xE049,
0xB4D8, 0xFAAC, 0x07F3, 0x25CF, 0xAFCA, 0x8EF4, 0xE947, 0x1810,
0xD56F, 0x88F0, 0x6F4A, 0x725C, 0x2438, 0xF157, 0xC773, 0x5197,
0x23CB, 0x7CA1, 0x9CE8, 0x213E, 0xDD96, 0xDC61, 0x860D, 0x850F,
0x90E0, 0x427C, 0xC471, 0xAACC, 0xD890, 0x0506, 0x01F7, 0x121C,
0xA3C2, 0x5F6A, 0xF9AE, 0xD069, 0x9117, 0x5899, 0x273A, 0xB927,
0x38D9, 0x13EB, 0xB32B, 0x3322, 0xBBD2, 0x70A9, 0x8907, 0xA733,
0xB62D, 0x223C, 0x9215, 0x20C9, 0x4987, 0xFFAA, 0x7850, 0x7AA5,
0x8F03, 0xF859, 0x8009, 0x171A, 0xDA65, 0x31D7, 0xC684, 0xB8D0,
0xC382, 0xB029, 0x775A, 0x111E, 0xCB7B, 0xFCA8, 0xD66D, 0x3A2C,
}
};
/*
**********************************************************************
* Routine: Phase 1 -- generate P1K, given TA, TK, IV32
*
* Inputs:
* tk[] = temporal key [128 bits]
* ta[] = transmitter's MAC address [ 48 bits]
* iv32 = upper 32 bits of IV [ 32 bits]
* Output:
* p1k[] = Phase 1 key [ 80 bits]
*
* Note:
* This function only needs to be called every 2**16 packets,
* although in theory it could be called every packet.
*
**********************************************************************
*/
static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)
{
sint i;
/* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */
p1k[0] = Lo16(iv32);
p1k[1] = Hi16(iv32);
p1k[2] = Mk16(ta[1], ta[0]); /* use TA[] as little-endian */
p1k[3] = Mk16(ta[3], ta[2]);
p1k[4] = Mk16(ta[5], ta[4]);
/* Now compute an unbalanced Feistel cipher with 80-bit block */
/* size on the 80-bit block P1K[], using the 128-bit key TK[] */
for (i = 0; i < PHASE1_LOOP_CNT; i++) { /* Each add is mod 2**16 */
p1k[0] += _S_(p1k[4] ^ TK16((i&1) + 0));
p1k[1] += _S_(p1k[0] ^ TK16((i&1) + 2));
p1k[2] += _S_(p1k[1] ^ TK16((i&1) + 4));
p1k[3] += _S_(p1k[2] ^ TK16((i&1) + 6));
p1k[4] += _S_(p1k[3] ^ TK16((i&1) + 0));
p1k[4] += (unsigned short)i; /* avoid "slide attacks" */
}
}
/*
**********************************************************************
* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16
*
* Inputs:
* tk[] = Temporal key [128 bits]
* p1k[] = Phase 1 output key [ 80 bits]
* iv16 = low 16 bits of IV counter [ 16 bits]
* Output:
* rc4key[] = the key used to encrypt the packet [128 bits]
*
* Note:
* The value {TA,IV32,IV16} for Phase1/Phase2 must be unique
* across all packets using the same key TK value. Then, for a
* given value of TK[], this TKIP48 construction guarantees that
* the final RC4KEY value is unique across all packets.
*
* Suggested implementation optimization: if PPK[] is "overlaid"
* appropriately on RC4KEY[], there is no need for the final
* for loop below that copies the PPK[] result into RC4KEY[].
*
**********************************************************************
*/
static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)
{
sint i;
u16 PPK[6]; /* temporary key for mixing */
/* Note: all adds in the PPK[] equations below are mod 2**16 */
for (i = 0; i < 5; i++)
PPK[i] = p1k[i]; /* first, copy P1K to PPK */
PPK[5] = p1k[4] + iv16; /* next, add in IV16 */
/* Bijective non-linear mixing of the 96 bits of PPK[0..5] */
PPK[0] += _S_(PPK[5] ^ TK16(0)); /* Mix key in each "round" */
PPK[1] += _S_(PPK[0] ^ TK16(1));
PPK[2] += _S_(PPK[1] ^ TK16(2));
PPK[3] += _S_(PPK[2] ^ TK16(3));
PPK[4] += _S_(PPK[3] ^ TK16(4));
PPK[5] += _S_(PPK[4] ^ TK16(5)); /* Total # S-box lookups == 6 */
/* Final sweep: bijective, "linear". Rotates kill LSB correlations */
PPK[0] += RotR1(PPK[5] ^ TK16(6));
PPK[1] += RotR1(PPK[0] ^ TK16(7)); /* Use all of TK[] in Phase2 */
PPK[2] += RotR1(PPK[1]);
PPK[3] += RotR1(PPK[2]);
PPK[4] += RotR1(PPK[3]);
PPK[5] += RotR1(PPK[4]);
/* Note: At this point, for a given key TK[0..15], the 96-bit output */
/* value PPK[0..5] is guaranteed to be unique, as a function */
/* of the 96-bit "input" value {TA,IV32,IV16}. That is, P1K */
/* is now a keyed permutation of {TA,IV32,IV16}. */
/* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key */
rc4key[0] = Hi8(iv16); /* RC4KEY[0..2] is the WEP IV */
rc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */
rc4key[2] = Lo8(iv16);
rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);
/* Copy 96 bits of PPK[0..5] to RC4KEY[4..15] (little-endian) */
for (i = 0; i < 6; i++) {
rc4key[4 + 2 * i] = Lo8(PPK[i]);
rc4key[5 + 2 * i] = Hi8(PPK[i]);
}
}
/*The hlen isn't include the IV*/
u32 r8712_tkip_encrypt(struct _adapter *padapter, u8 *pxmitframe)
{ /* exclude ICV */
u16 pnl;
u32 pnh;
u8 rc4key[16];
u8 ttkey[16];
u8 crc[4];
struct arc4context mycontext;
u32 curfragnum, length, prwskeylen;
u8 *pframe, *payload, *iv, *prwskey;
union pn48 txpn;
struct sta_info *stainfo;
struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
u32 res = _SUCCESS;
if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
return _FAIL;
pframe = ((struct xmit_frame *)pxmitframe)->buf_addr+TXDESC_OFFSET;
/* 4 start to encrypt each fragment */
if (pattrib->encrypt == _TKIP_) {
if (pattrib->psta)
stainfo = pattrib->psta;
else
stainfo = r8712_get_stainfo(&padapter->stapriv,
&pattrib->ra[0]);
if (stainfo != NULL) {
prwskey = &stainfo->x_UncstKey.skey[0];
prwskeylen = 16;
for (curfragnum = 0; curfragnum < pattrib->nr_frags;
curfragnum++) {
iv = pframe + pattrib->hdrlen;
payload = pframe+pattrib->iv_len +
pattrib->hdrlen;
GET_TKIP_PN(iv, txpn);
pnl = (u16)(txpn.val);
pnh = (u32)(txpn.val >> 16);
phase1((u16 *)&ttkey[0], prwskey, &pattrib->
ta[0], pnh);
phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0],
pnl);
if ((curfragnum + 1) == pattrib->nr_frags) {
/* 4 the last fragment */
length = pattrib->last_txcmdsz -
pattrib->hdrlen-pattrib->iv_len -
pattrib->icv_len;
*((u32 *)crc) = cpu_to_le32(
getcrc32(payload, length));
arcfour_init(&mycontext, rc4key, 16);
arcfour_encrypt(&mycontext, payload,
payload, length);
arcfour_encrypt(&mycontext, payload +
length, crc, 4);
} else {
length = pxmitpriv->frag_len-pattrib->
hdrlen-pattrib->
iv_len-pattrib->icv_len;
*((u32 *)crc) = cpu_to_le32(getcrc32(
payload, length));
arcfour_init(&mycontext, rc4key, 16);
arcfour_encrypt(&mycontext, payload,
payload, length);
arcfour_encrypt(&mycontext,
payload+length, crc, 4);
pframe += pxmitpriv->frag_len;
pframe = (u8 *)RND4((addr_t)(pframe));
}
}
} else
res = _FAIL;
}
return res;
}
/* The hlen doesn't include the IV */
u32 r8712_tkip_decrypt(struct _adapter *padapter, u8 *precvframe)
{ /* exclude ICV */
u16 pnl;
u32 pnh;
u8 rc4key[16];
u8 ttkey[16];
u8 crc[4];
struct arc4context mycontext;
u32 length, prwskeylen;
u8 *pframe, *payload, *iv, *prwskey, idx = 0;
union pn48 txpn;
struct sta_info *stainfo;
struct rx_pkt_attrib *prxattrib = &((union recv_frame *)
precvframe)->u.hdr.attrib;
struct security_priv *psecuritypriv = &padapter->securitypriv;
pframe = (unsigned char *)((union recv_frame *)
precvframe)->u.hdr.rx_data;
/* 4 start to decrypt recvframe */
if (prxattrib->encrypt == _TKIP_) {
stainfo = r8712_get_stainfo(&padapter->stapriv,
&prxattrib->ta[0]);
if (stainfo != NULL) {
iv = pframe+prxattrib->hdrlen;
payload = pframe+prxattrib->iv_len + prxattrib->hdrlen;
length = ((union recv_frame *)precvframe)->
u.hdr.len - prxattrib->hdrlen -
prxattrib->iv_len;
if (IS_MCAST(prxattrib->ra)) {
idx = iv[3];
prwskey = &psecuritypriv->XGrpKey[
((idx >> 6) & 0x3) - 1].skey[0];
if (psecuritypriv->binstallGrpkey == false)
return _FAIL;
} else
prwskey = &stainfo->x_UncstKey.skey[0];
prwskeylen = 16;
GET_TKIP_PN(iv, txpn);
pnl = (u16)(txpn.val);
pnh = (u32)(txpn.val >> 16);
phase1((u16 *)&ttkey[0], prwskey, &prxattrib->ta[0],
pnh);
phase2(&rc4key[0], prwskey, (unsigned short *)
&ttkey[0], pnl);
/* 4 decrypt payload include icv */
arcfour_init(&mycontext, rc4key, 16);
arcfour_encrypt(&mycontext, payload, payload, length);
*((u32 *)crc) = cpu_to_le32(getcrc32(payload,
length - 4));
if (crc[3] != payload[length - 1] ||
crc[2] != payload[length - 2] ||
crc[1] != payload[length - 3] ||
crc[0] != payload[length - 4])
return _FAIL;
} else
return _FAIL;
}
return _SUCCESS;
}
/* 3 =====AES related===== */
#define MAX_MSG_SIZE 2048
/*****************************/
/******** SBOX Table *********/
/*****************************/
static const u8 sbox_table[256] = {
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
};
/****************************************/
/* aes128k128d() */
/* Performs a 128 bit AES encrypt with */
/* 128 bit data. */
/****************************************/
static void xor_128(u8 *a, u8 *b, u8 *out)
{
sint i;
for (i = 0; i < 16; i++)
out[i] = a[i] ^ b[i];
}
static void xor_32(u8 *a, u8 *b, u8 *out)
{
sint i;
for (i = 0; i < 4; i++)
out[i] = a[i] ^ b[i];
}
static u8 sbox(u8 a)
{
return sbox_table[(sint)a];
}
static void next_key(u8 *key, sint round)
{
u8 rcon;
u8 sbox_key[4];
u8 rcon_table[12] = {
0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
0x1b, 0x36, 0x36, 0x36
};
sbox_key[0] = sbox(key[13]);
sbox_key[1] = sbox(key[14]);
sbox_key[2] = sbox(key[15]);
sbox_key[3] = sbox(key[12]);
rcon = rcon_table[round];
xor_32(&key[0], sbox_key, &key[0]);
key[0] = key[0] ^ rcon;
xor_32(&key[4], &key[0], &key[4]);
xor_32(&key[8], &key[4], &key[8]);
xor_32(&key[12], &key[8], &key[12]);
}
static void byte_sub(u8 *in, u8 *out)
{
sint i;
for (i = 0; i < 16; i++)
out[i] = sbox(in[i]);
}
static void shift_row(u8 *in, u8 *out)
{
out[0] = in[0];
out[1] = in[5];
out[2] = in[10];
out[3] = in[15];
out[4] = in[4];
out[5] = in[9];
out[6] = in[14];
out[7] = in[3];
out[8] = in[8];
out[9] = in[13];
out[10] = in[2];
out[11] = in[7];
out[12] = in[12];
out[13] = in[1];
out[14] = in[6];
out[15] = in[11];
}
static void mix_column(u8 *in, u8 *out)
{
sint i;
u8 add1b[4];
u8 add1bf7[4];
u8 rotl[4];
u8 swap_halfs[4];
u8 andf7[4];
u8 rotr[4];
u8 temp[4];
u8 tempb[4];
for (i = 0 ; i < 4; i++) {
if ((in[i] & 0x80) == 0x80)
add1b[i] = 0x1b;
else
add1b[i] = 0x00;
}
swap_halfs[0] = in[2]; /* Swap halves */
swap_halfs[1] = in[3];
swap_halfs[2] = in[0];
swap_halfs[3] = in[1];
rotl[0] = in[3]; /* Rotate left 8 bits */
rotl[1] = in[0];
rotl[2] = in[1];
rotl[3] = in[2];
andf7[0] = in[0] & 0x7f;
andf7[1] = in[1] & 0x7f;
andf7[2] = in[2] & 0x7f;
andf7[3] = in[3] & 0x7f;
for (i = 3; i > 0; i--) { /* logical shift left 1 bit */
andf7[i] = andf7[i] << 1;
if ((andf7[i-1] & 0x80) == 0x80)
andf7[i] = (andf7[i] | 0x01);
}
andf7[0] = andf7[0] << 1;
andf7[0] = andf7[0] & 0xfe;
xor_32(add1b, andf7, add1bf7);
xor_32(in, add1bf7, rotr);
temp[0] = rotr[0]; /* Rotate right 8 bits */
rotr[0] = rotr[1];
rotr[1] = rotr[2];
rotr[2] = rotr[3];
rotr[3] = temp[0];
xor_32(add1bf7, rotr, temp);
xor_32(swap_halfs, rotl, tempb);
xor_32(temp, tempb, out);
}
static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
{
sint round;
sint i;
u8 intermediatea[16];
u8 intermediateb[16];
u8 round_key[16];
for (i = 0; i < 16; i++)
round_key[i] = key[i];
for (round = 0; round < 11; round++) {
if (round == 0) {
xor_128(round_key, data, ciphertext);
next_key(round_key, round);
} else if (round == 10) {
byte_sub(ciphertext, intermediatea);
shift_row(intermediatea, intermediateb);
xor_128(intermediateb, round_key, ciphertext);
} else { /* 1 - 9 */
byte_sub(ciphertext, intermediatea);
shift_row(intermediatea, intermediateb);
mix_column(&intermediateb[0], &intermediatea[0]);
mix_column(&intermediateb[4], &intermediatea[4]);
mix_column(&intermediateb[8], &intermediatea[8]);
mix_column(&intermediateb[12], &intermediatea[12]);
xor_128(intermediatea, round_key, ciphertext);
next_key(round_key, round);
}
}
}
/************************************************/
/* construct_mic_iv() */
/* Builds the MIC IV from header fields and PN */
/************************************************/
static void construct_mic_iv(u8 *mic_iv, sint qc_exists, sint a4_exists,
u8 *mpdu, uint payload_length, u8 *pn_vector)
{
sint i;
mic_iv[0] = 0x59;
if (qc_exists && a4_exists)
mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */
if (qc_exists && !a4_exists)
mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */
if (!qc_exists)
mic_iv[1] = 0x00;
for (i = 2; i < 8; i++)
mic_iv[i] = mpdu[i + 8];
for (i = 8; i < 14; i++)
mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */
mic_iv[14] = (unsigned char) (payload_length / 256);
mic_iv[15] = (unsigned char) (payload_length % 256);
}
/************************************************/
/* construct_mic_header1() */
/* Builds the first MIC header block from */
/* header fields. */
/************************************************/
static void construct_mic_header1(u8 *mic_header1, sint header_length, u8 *mpdu)
{
mic_header1[0] = (u8)((header_length - 2) / 256);
mic_header1[1] = (u8)((header_length - 2) % 256);
mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */
/* Mute retry, more data and pwr mgt bits */
mic_header1[3] = mpdu[1] & 0xc7;
mic_header1[4] = mpdu[4]; /* A1 */
mic_header1[5] = mpdu[5];
mic_header1[6] = mpdu[6];
mic_header1[7] = mpdu[7];
mic_header1[8] = mpdu[8];
mic_header1[9] = mpdu[9];
mic_header1[10] = mpdu[10]; /* A2 */
mic_header1[11] = mpdu[11];
mic_header1[12] = mpdu[12];
mic_header1[13] = mpdu[13];
mic_header1[14] = mpdu[14];
mic_header1[15] = mpdu[15];
}
/************************************************/
/* construct_mic_header2() */
/* Builds the last MIC header block from */
/* header fields. */
/************************************************/
static void construct_mic_header2(u8 *mic_header2, u8 *mpdu, sint a4_exists,
sint qc_exists)
{
sint i;
for (i = 0; i < 16; i++)
mic_header2[i] = 0x00;
mic_header2[0] = mpdu[16]; /* A3 */
mic_header2[1] = mpdu[17];
mic_header2[2] = mpdu[18];
mic_header2[3] = mpdu[19];
mic_header2[4] = mpdu[20];
mic_header2[5] = mpdu[21];
mic_header2[6] = 0x00;
mic_header2[7] = 0x00; /* mpdu[23]; */
if (!qc_exists && a4_exists)
for (i = 0; i < 6; i++)
mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
if (qc_exists && !a4_exists) {
mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */
mic_header2[9] = mpdu[25] & 0x00;
}
if (qc_exists && a4_exists) {
for (i = 0; i < 6; i++)
mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
mic_header2[14] = mpdu[30] & 0x0f;
mic_header2[15] = mpdu[31] & 0x00;
}
}
/************************************************/
/* construct_mic_header2() */
/* Builds the last MIC header block from */
/* header fields. */
/************************************************/
static void construct_ctr_preload(u8 *ctr_preload, sint a4_exists, sint qc_exists,
u8 *mpdu, u8 *pn_vector, sint c)
{
sint i;
for (i = 0; i < 16; i++)
ctr_preload[i] = 0x00;
i = 0;
ctr_preload[0] = 0x01; /* flag */
if (qc_exists && a4_exists)
ctr_preload[1] = mpdu[30] & 0x0f;
if (qc_exists && !a4_exists)
ctr_preload[1] = mpdu[24] & 0x0f;
for (i = 2; i < 8; i++)
ctr_preload[i] = mpdu[i + 8];
for (i = 8; i < 14; i++)
ctr_preload[i] = pn_vector[13 - i];
ctr_preload[14] = (unsigned char) (c / 256); /* Ctr */
ctr_preload[15] = (unsigned char) (c % 256);
}
/************************************/
/* bitwise_xor() */
/* A 128 bit, bitwise exclusive or */
/************************************/
static void bitwise_xor(u8 *ina, u8 *inb, u8 *out)
{
sint i;
for (i = 0; i < 16; i++)
out[i] = ina[i] ^ inb[i];
}
static sint aes_cipher(u8 *key, uint hdrlen,
u8 *pframe, uint plen)
{
uint qc_exists, a4_exists, i, j, payload_remainder;
uint num_blocks, payload_index;
u8 pn_vector[6];
u8 mic_iv[16];
u8 mic_header1[16];
u8 mic_header2[16];
u8 ctr_preload[16];
/* Intermediate Buffers */
u8 chain_buffer[16];
u8 aes_out[16];
u8 padded_buffer[16];
u8 mic[8];
uint frtype = GetFrameType(pframe);
uint frsubtype = GetFrameSubType(pframe);
frsubtype = frsubtype >> 4;
memset((void *)mic_iv, 0, 16);
memset((void *)mic_header1, 0, 16);
memset((void *)mic_header2, 0, 16);
memset((void *)ctr_preload, 0, 16);
memset((void *)chain_buffer, 0, 16);
memset((void *)aes_out, 0, 16);
memset((void *)padded_buffer, 0, 16);
if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen == WLAN_HDR_A3_QOS_LEN))
a4_exists = 0;
else
a4_exists = 1;
if ((frtype == WIFI_DATA_CFACK) ||
(frtype == WIFI_DATA_CFPOLL) ||
(frtype == WIFI_DATA_CFACKPOLL)) {
qc_exists = 1;
if (hdrlen != WLAN_HDR_A3_QOS_LEN)
hdrlen += 2;
} else if ((frsubtype == 0x08) ||
(frsubtype == 0x09) ||
(frsubtype == 0x0a) ||
(frsubtype == 0x0b)) {
if (hdrlen != WLAN_HDR_A3_QOS_LEN)
hdrlen += 2;
qc_exists = 1;
} else
qc_exists = 0;
pn_vector[0] = pframe[hdrlen];
pn_vector[1] = pframe[hdrlen+1];
pn_vector[2] = pframe[hdrlen+4];
pn_vector[3] = pframe[hdrlen+5];
pn_vector[4] = pframe[hdrlen+6];
pn_vector[5] = pframe[hdrlen+7];
construct_mic_iv(mic_iv, qc_exists, a4_exists, pframe, plen, pn_vector);
construct_mic_header1(mic_header1, hdrlen, pframe);
construct_mic_header2(mic_header2, pframe, a4_exists, qc_exists);
payload_remainder = plen % 16;
num_blocks = plen / 16;
/* Find start of payload */
payload_index = (hdrlen + 8);
/* Calculate MIC */
aes128k128d(key, mic_iv, aes_out);
bitwise_xor(aes_out, mic_header1, chain_buffer);
aes128k128d(key, chain_buffer, aes_out);
bitwise_xor(aes_out, mic_header2, chain_buffer);
aes128k128d(key, chain_buffer, aes_out);
for (i = 0; i < num_blocks; i++) {
bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
payload_index += 16;
aes128k128d(key, chain_buffer, aes_out);
}
/* Add on the final payload block if it needs padding */
if (payload_remainder > 0) {
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < payload_remainder; j++)
padded_buffer[j] = pframe[payload_index++];
bitwise_xor(aes_out, padded_buffer, chain_buffer);
aes128k128d(key, chain_buffer, aes_out);
}
for (j = 0; j < 8; j++)
mic[j] = aes_out[j];
/* Insert MIC into payload */
for (j = 0; j < 8; j++)
pframe[payload_index+j] = mic[j];
payload_index = hdrlen + 8;
for (i = 0; i < num_blocks; i++) {
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
pframe, pn_vector, i + 1);
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
for (j = 0; j < 16; j++)
pframe[payload_index++] = chain_buffer[j];
}
if (payload_remainder > 0) { /* If short final block, then pad it,*/
/* encrypt and copy unpadded part back */
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
pframe, pn_vector, num_blocks+1);
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < payload_remainder; j++)
padded_buffer[j] = pframe[payload_index+j];
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, padded_buffer, chain_buffer);
for (j = 0; j < payload_remainder; j++)
pframe[payload_index++] = chain_buffer[j];
}
/* Encrypt the MIC */
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
pframe, pn_vector, 0);
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < 8; j++)
padded_buffer[j] = pframe[j+hdrlen+8+plen];
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, padded_buffer, chain_buffer);
for (j = 0; j < 8; j++)
pframe[payload_index++] = chain_buffer[j];
return _SUCCESS;
}
u32 r8712_aes_encrypt(struct _adapter *padapter, u8 *pxmitframe)
{ /* exclude ICV */
/* Intermediate Buffers */
sint curfragnum, length;
u32 prwskeylen;
u8 *pframe, *prwskey;
struct sta_info *stainfo;
struct pkt_attrib *pattrib = &((struct xmit_frame *)
pxmitframe)->attrib;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
u32 res = _SUCCESS;
if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
return _FAIL;
pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
/* 4 start to encrypt each fragment */
if ((pattrib->encrypt == _AES_)) {
if (pattrib->psta)
stainfo = pattrib->psta;
else
stainfo = r8712_get_stainfo(&padapter->stapriv,
&pattrib->ra[0]);
if (stainfo != NULL) {
prwskey = &stainfo->x_UncstKey.skey[0];
prwskeylen = 16;
for (curfragnum = 0; curfragnum < pattrib->nr_frags;
curfragnum++) {
if ((curfragnum + 1) == pattrib->nr_frags) {\
length = pattrib->last_txcmdsz -
pattrib->hdrlen -
pattrib->iv_len -
pattrib->icv_len;
aes_cipher(prwskey, pattrib->
hdrlen, pframe, length);
} else {
length = pxmitpriv->frag_len -
pattrib->hdrlen -
pattrib->iv_len -
pattrib->icv_len ;
aes_cipher(prwskey, pattrib->
hdrlen, pframe, length);
pframe += pxmitpriv->frag_len;
pframe = (u8 *)RND4((addr_t)(pframe));
}
}
} else
res = _FAIL;
}
return res;
}
static sint aes_decipher(u8 *key, uint hdrlen,
u8 *pframe, uint plen)
{
static u8 message[MAX_MSG_SIZE];
uint qc_exists, a4_exists, i, j, payload_remainder;
uint num_blocks, payload_index;
u8 pn_vector[6];
u8 mic_iv[16];
u8 mic_header1[16];
u8 mic_header2[16];
u8 ctr_preload[16];
/* Intermediate Buffers */
u8 chain_buffer[16];
u8 aes_out[16];
u8 padded_buffer[16];
u8 mic[8];
uint frtype = GetFrameType(pframe);
uint frsubtype = GetFrameSubType(pframe);
frsubtype = frsubtype >> 4;
memset((void *)mic_iv, 0, 16);
memset((void *)mic_header1, 0, 16);
memset((void *)mic_header2, 0, 16);
memset((void *)ctr_preload, 0, 16);
memset((void *)chain_buffer, 0, 16);
memset((void *)aes_out, 0, 16);
memset((void *)padded_buffer, 0, 16);
/* start to decrypt the payload */
/*(plen including llc, payload and mic) */
num_blocks = (plen - 8) / 16;
payload_remainder = (plen-8) % 16;
pn_vector[0] = pframe[hdrlen];
pn_vector[1] = pframe[hdrlen+1];
pn_vector[2] = pframe[hdrlen+4];
pn_vector[3] = pframe[hdrlen+5];
pn_vector[4] = pframe[hdrlen+6];
pn_vector[5] = pframe[hdrlen+7];
if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen == WLAN_HDR_A3_QOS_LEN))
a4_exists = 0;
else
a4_exists = 1;
if ((frtype == WIFI_DATA_CFACK) ||
(frtype == WIFI_DATA_CFPOLL) ||
(frtype == WIFI_DATA_CFACKPOLL)) {
qc_exists = 1;
if (hdrlen != WLAN_HDR_A3_QOS_LEN)
hdrlen += 2;
} else if ((frsubtype == 0x08) ||
(frsubtype == 0x09) ||
(frsubtype == 0x0a) ||
(frsubtype == 0x0b)) {
if (hdrlen != WLAN_HDR_A3_QOS_LEN)
hdrlen += 2;
qc_exists = 1;
} else
qc_exists = 0;
/* now, decrypt pframe with hdrlen offset and plen long */
payload_index = hdrlen + 8; /* 8 is for extiv */
for (i = 0; i < num_blocks; i++) {
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
pframe, pn_vector, i + 1);
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
for (j = 0; j < 16; j++)
pframe[payload_index++] = chain_buffer[j];
}
if (payload_remainder > 0) { /* If short final block, pad it,*/
/* encrypt it and copy the unpadded part back */
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
pframe, pn_vector, num_blocks+1);
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < payload_remainder; j++)
padded_buffer[j] = pframe[payload_index + j];
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, padded_buffer, chain_buffer);
for (j = 0; j < payload_remainder; j++)
pframe[payload_index++] = chain_buffer[j];
}
/* start to calculate the mic */
memcpy((void *)message, pframe, (hdrlen + plen + 8));
pn_vector[0] = pframe[hdrlen];
pn_vector[1] = pframe[hdrlen+1];
pn_vector[2] = pframe[hdrlen+4];
pn_vector[3] = pframe[hdrlen+5];
pn_vector[4] = pframe[hdrlen+6];
pn_vector[5] = pframe[hdrlen+7];
construct_mic_iv(mic_iv, qc_exists, a4_exists, message, plen-8,
pn_vector);
construct_mic_header1(mic_header1, hdrlen, message);
construct_mic_header2(mic_header2, message, a4_exists, qc_exists);
payload_remainder = (plen - 8) % 16;
num_blocks = (plen - 8) / 16;
/* Find start of payload */
payload_index = (hdrlen + 8);
/* Calculate MIC */
aes128k128d(key, mic_iv, aes_out);
bitwise_xor(aes_out, mic_header1, chain_buffer);
aes128k128d(key, chain_buffer, aes_out);
bitwise_xor(aes_out, mic_header2, chain_buffer);
aes128k128d(key, chain_buffer, aes_out);
for (i = 0; i < num_blocks; i++) {
bitwise_xor(aes_out, &message[payload_index], chain_buffer);
payload_index += 16;
aes128k128d(key, chain_buffer, aes_out);
}
/* Add on the final payload block if it needs padding */
if (payload_remainder > 0) {
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < payload_remainder; j++)
padded_buffer[j] = message[payload_index++];
bitwise_xor(aes_out, padded_buffer, chain_buffer);
aes128k128d(key, chain_buffer, aes_out);
}
for (j = 0 ; j < 8; j++)
mic[j] = aes_out[j];
/* Insert MIC into payload */
for (j = 0; j < 8; j++)
message[payload_index+j] = mic[j];
payload_index = hdrlen + 8;
for (i = 0; i < num_blocks; i++) {
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
message, pn_vector, i + 1);
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, &message[payload_index], chain_buffer);
for (j = 0; j < 16; j++)
message[payload_index++] = chain_buffer[j];
}
if (payload_remainder > 0) { /* If short final block, pad it,*/
/* encrypt and copy unpadded part back */
construct_ctr_preload(ctr_preload, a4_exists, qc_exists,
message, pn_vector, num_blocks+1);
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < payload_remainder; j++)
padded_buffer[j] = message[payload_index + j];
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, padded_buffer, chain_buffer);
for (j = 0; j < payload_remainder; j++)
message[payload_index++] = chain_buffer[j];
}
/* Encrypt the MIC */
construct_ctr_preload(ctr_preload, a4_exists, qc_exists, message,
pn_vector, 0);
for (j = 0; j < 16; j++)
padded_buffer[j] = 0x00;
for (j = 0; j < 8; j++)
padded_buffer[j] = message[j + hdrlen + plen];
aes128k128d(key, ctr_preload, aes_out);
bitwise_xor(aes_out, padded_buffer, chain_buffer);
for (j = 0; j < 8; j++)
message[payload_index++] = chain_buffer[j];
/* compare the mic */
return _SUCCESS;
}
u32 r8712_aes_decrypt(struct _adapter *padapter, u8 *precvframe)
{ /* exclude ICV */
/* Intermediate Buffers */
sint length;
u32 prwskeylen;
u8 *pframe, *prwskey, *iv, idx;
struct sta_info *stainfo;
struct rx_pkt_attrib *prxattrib = &((union recv_frame *)
precvframe)->u.hdr.attrib;
struct security_priv *psecuritypriv = &padapter->securitypriv;
pframe = (unsigned char *)((union recv_frame*)precvframe)->
u.hdr.rx_data;
/* 4 start to encrypt each fragment */
if ((prxattrib->encrypt == _AES_)) {
stainfo = r8712_get_stainfo(&padapter->stapriv,
&prxattrib->ta[0]);
if (stainfo != NULL) {
if (IS_MCAST(prxattrib->ra)) {
iv = pframe+prxattrib->hdrlen;
idx = iv[3];
prwskey = &psecuritypriv->XGrpKey[
((idx >> 6) & 0x3) - 1].skey[0];
if (psecuritypriv->binstallGrpkey == false)
return _FAIL;
} else
prwskey = &stainfo->x_UncstKey.skey[0];
prwskeylen = 16;
length = ((union recv_frame *)precvframe)->
u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len;
aes_decipher(prwskey, prxattrib->hdrlen, pframe,
length);
} else
return _FAIL;
}
return _SUCCESS;
}
void r8712_use_tkipkey_handler(void *FunctionContext)
{
struct _adapter *padapter = (struct _adapter *)FunctionContext;
padapter->securitypriv.busetkipkey = true;
}
| gpl-2.0 |
savoca/zerofltetmo | scripts/dtc/fdtget.c | 6995 | 8781 | /*
* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
*
* Portions from U-Boot cmd_fdt.c (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
* Based on code written by:
* Pantelis Antoniou <pantelis.antoniou@gmail.com> and
* Matthew McClintock <msm@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <assert.h>
#include <ctype.h>
#include <getopt.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <libfdt.h>
#include "util.h"
enum display_mode {
MODE_SHOW_VALUE, /* show values for node properties */
MODE_LIST_PROPS, /* list the properties for a node */
MODE_LIST_SUBNODES, /* list the subnodes of a node */
};
/* Holds information which controls our output and options */
struct display_info {
int type; /* data type (s/i/u/x or 0 for default) */
int size; /* data size (1/2/4) */
enum display_mode mode; /* display mode that we are using */
const char *default_val; /* default value if node/property not found */
};
static void report_error(const char *where, int err)
{
fprintf(stderr, "Error at '%s': %s\n", where, fdt_strerror(err));
}
/**
* Displays data of a given length according to selected options
*
* If a specific data type is provided in disp, then this is used. Otherwise
* we try to guess the data type / size from the contents.
*
* @param disp Display information / options
* @param data Data to display
* @param len Maximum length of buffer
* @return 0 if ok, -1 if data does not match format
*/
static int show_data(struct display_info *disp, const char *data, int len)
{
int i, size;
const uint8_t *p = (const uint8_t *)data;
const char *s;
int value;
int is_string;
char fmt[3];
/* no data, don't print */
if (len == 0)
return 0;
is_string = (disp->type) == 's' ||
(!disp->type && util_is_printable_string(data, len));
if (is_string) {
if (data[len - 1] != '\0') {
fprintf(stderr, "Unterminated string\n");
return -1;
}
for (s = data; s - data < len; s += strlen(s) + 1) {
if (s != data)
printf(" ");
printf("%s", (const char *)s);
}
return 0;
}
size = disp->size;
if (size == -1) {
size = (len % 4) == 0 ? 4 : 1;
} else if (len % size) {
fprintf(stderr, "Property length must be a multiple of "
"selected data size\n");
return -1;
}
fmt[0] = '%';
fmt[1] = disp->type ? disp->type : 'd';
fmt[2] = '\0';
for (i = 0; i < len; i += size, p += size) {
if (i)
printf(" ");
value = size == 4 ? fdt32_to_cpu(*(const uint32_t *)p) :
size == 2 ? (*p << 8) | p[1] : *p;
printf(fmt, value);
}
return 0;
}
/**
* List all properties in a node, one per line.
*
* @param blob FDT blob
* @param node Node to display
* @return 0 if ok, or FDT_ERR... if not.
*/
static int list_properties(const void *blob, int node)
{
const struct fdt_property *data;
const char *name;
int prop;
prop = fdt_first_property_offset(blob, node);
do {
/* Stop silently when there are no more properties */
if (prop < 0)
return prop == -FDT_ERR_NOTFOUND ? 0 : prop;
data = fdt_get_property_by_offset(blob, prop, NULL);
name = fdt_string(blob, fdt32_to_cpu(data->nameoff));
if (name)
puts(name);
prop = fdt_next_property_offset(blob, prop);
} while (1);
}
#define MAX_LEVEL 32 /* how deeply nested we will go */
/**
* List all subnodes in a node, one per line
*
* @param blob FDT blob
* @param node Node to display
* @return 0 if ok, or FDT_ERR... if not.
*/
static int list_subnodes(const void *blob, int node)
{
int nextoffset; /* next node offset from libfdt */
uint32_t tag; /* current tag */
int level = 0; /* keep track of nesting level */
const char *pathp;
int depth = 1; /* the assumed depth of this node */
while (level >= 0) {
tag = fdt_next_tag(blob, node, &nextoffset);
switch (tag) {
case FDT_BEGIN_NODE:
pathp = fdt_get_name(blob, node, NULL);
if (level <= depth) {
if (pathp == NULL)
pathp = "/* NULL pointer error */";
if (*pathp == '\0')
pathp = "/"; /* root is nameless */
if (level == 1)
puts(pathp);
}
level++;
if (level >= MAX_LEVEL) {
printf("Nested too deep, aborting.\n");
return 1;
}
break;
case FDT_END_NODE:
level--;
if (level == 0)
level = -1; /* exit the loop */
break;
case FDT_END:
return 1;
case FDT_PROP:
break;
default:
if (level <= depth)
printf("Unknown tag 0x%08X\n", tag);
return 1;
}
node = nextoffset;
}
return 0;
}
/**
* Show the data for a given node (and perhaps property) according to the
* display option provided.
*
* @param blob FDT blob
* @param disp Display information / options
* @param node Node to display
* @param property Name of property to display, or NULL if none
* @return 0 if ok, -ve on error
*/
static int show_data_for_item(const void *blob, struct display_info *disp,
int node, const char *property)
{
const void *value = NULL;
int len, err = 0;
switch (disp->mode) {
case MODE_LIST_PROPS:
err = list_properties(blob, node);
break;
case MODE_LIST_SUBNODES:
err = list_subnodes(blob, node);
break;
default:
assert(property);
value = fdt_getprop(blob, node, property, &len);
if (value) {
if (show_data(disp, value, len))
err = -1;
else
printf("\n");
} else if (disp->default_val) {
puts(disp->default_val);
} else {
report_error(property, len);
err = -1;
}
break;
}
return err;
}
/**
* Run the main fdtget operation, given a filename and valid arguments
*
* @param disp Display information / options
* @param filename Filename of blob file
* @param arg List of arguments to process
* @param arg_count Number of arguments
* @param return 0 if ok, -ve on error
*/
static int do_fdtget(struct display_info *disp, const char *filename,
char **arg, int arg_count, int args_per_step)
{
char *blob;
const char *prop;
int i, node;
blob = utilfdt_read(filename);
if (!blob)
return -1;
for (i = 0; i + args_per_step <= arg_count; i += args_per_step) {
node = fdt_path_offset(blob, arg[i]);
if (node < 0) {
if (disp->default_val) {
puts(disp->default_val);
continue;
} else {
report_error(arg[i], node);
return -1;
}
}
prop = args_per_step == 1 ? NULL : arg[i + 1];
if (show_data_for_item(blob, disp, node, prop))
return -1;
}
return 0;
}
static const char *usage_msg =
"fdtget - read values from device tree\n"
"\n"
"Each value is printed on a new line.\n\n"
"Usage:\n"
" fdtget <options> <dt file> [<node> <property>]...\n"
" fdtget -p <options> <dt file> [<node> ]...\n"
"Options:\n"
"\t-t <type>\tType of data\n"
"\t-p\t\tList properties for each node\n"
"\t-l\t\tList subnodes for each node\n"
"\t-d\t\tDefault value to display when the property is "
"missing\n"
"\t-h\t\tPrint this help\n\n"
USAGE_TYPE_MSG;
static void usage(const char *msg)
{
if (msg)
fprintf(stderr, "Error: %s\n\n", msg);
fprintf(stderr, "%s", usage_msg);
exit(2);
}
int main(int argc, char *argv[])
{
char *filename = NULL;
struct display_info disp;
int args_per_step = 2;
/* set defaults */
memset(&disp, '\0', sizeof(disp));
disp.size = -1;
disp.mode = MODE_SHOW_VALUE;
for (;;) {
int c = getopt(argc, argv, "d:hlpt:");
if (c == -1)
break;
switch (c) {
case 'h':
case '?':
usage(NULL);
case 't':
if (utilfdt_decode_type(optarg, &disp.type,
&disp.size))
usage("Invalid type string");
break;
case 'p':
disp.mode = MODE_LIST_PROPS;
args_per_step = 1;
break;
case 'l':
disp.mode = MODE_LIST_SUBNODES;
args_per_step = 1;
break;
case 'd':
disp.default_val = optarg;
break;
}
}
if (optind < argc)
filename = argv[optind++];
if (!filename)
usage("Missing filename");
argv += optind;
argc -= optind;
/* Allow no arguments, and silently succeed */
if (!argc)
return 0;
/* Check for node, property arguments */
if (args_per_step == 2 && (argc % 2))
usage("Must have an even number of arguments");
if (do_fdtget(&disp, filename, argv, argc, args_per_step))
return 1;
return 0;
}
| gpl-2.0 |
antaril/AGK_for_DU | tools/perf/util/callchain.c | 8019 | 10730 | /*
* Copyright (C) 2009-2011, Frederic Weisbecker <fweisbec@gmail.com>
*
* Handle the callchains from the stream in an ad-hoc radix tree and then
* sort them in an rbtree.
*
* Using a radix for code path provides a fast retrieval and factorizes
* memory use. Also that lets us use the paths in a hierarchical graph view.
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <errno.h>
#include <math.h>
#include "util.h"
#include "callchain.h"
bool ip_callchain__valid(struct ip_callchain *chain,
const union perf_event *event)
{
unsigned int chain_size = event->header.size;
chain_size -= (unsigned long)&event->ip.__more_data - (unsigned long)event;
return chain->nr * sizeof(u64) <= chain_size;
}
#define chain_for_each_child(child, parent) \
list_for_each_entry(child, &parent->children, siblings)
#define chain_for_each_child_safe(child, next, parent) \
list_for_each_entry_safe(child, next, &parent->children, siblings)
static void
rb_insert_callchain(struct rb_root *root, struct callchain_node *chain,
enum chain_mode mode)
{
struct rb_node **p = &root->rb_node;
struct rb_node *parent = NULL;
struct callchain_node *rnode;
u64 chain_cumul = callchain_cumul_hits(chain);
while (*p) {
u64 rnode_cumul;
parent = *p;
rnode = rb_entry(parent, struct callchain_node, rb_node);
rnode_cumul = callchain_cumul_hits(rnode);
switch (mode) {
case CHAIN_FLAT:
if (rnode->hit < chain->hit)
p = &(*p)->rb_left;
else
p = &(*p)->rb_right;
break;
case CHAIN_GRAPH_ABS: /* Falldown */
case CHAIN_GRAPH_REL:
if (rnode_cumul < chain_cumul)
p = &(*p)->rb_left;
else
p = &(*p)->rb_right;
break;
case CHAIN_NONE:
default:
break;
}
}
rb_link_node(&chain->rb_node, parent, p);
rb_insert_color(&chain->rb_node, root);
}
static void
__sort_chain_flat(struct rb_root *rb_root, struct callchain_node *node,
u64 min_hit)
{
struct callchain_node *child;
chain_for_each_child(child, node)
__sort_chain_flat(rb_root, child, min_hit);
if (node->hit && node->hit >= min_hit)
rb_insert_callchain(rb_root, node, CHAIN_FLAT);
}
/*
* Once we get every callchains from the stream, we can now
* sort them by hit
*/
static void
sort_chain_flat(struct rb_root *rb_root, struct callchain_root *root,
u64 min_hit, struct callchain_param *param __used)
{
__sort_chain_flat(rb_root, &root->node, min_hit);
}
static void __sort_chain_graph_abs(struct callchain_node *node,
u64 min_hit)
{
struct callchain_node *child;
node->rb_root = RB_ROOT;
chain_for_each_child(child, node) {
__sort_chain_graph_abs(child, min_hit);
if (callchain_cumul_hits(child) >= min_hit)
rb_insert_callchain(&node->rb_root, child,
CHAIN_GRAPH_ABS);
}
}
static void
sort_chain_graph_abs(struct rb_root *rb_root, struct callchain_root *chain_root,
u64 min_hit, struct callchain_param *param __used)
{
__sort_chain_graph_abs(&chain_root->node, min_hit);
rb_root->rb_node = chain_root->node.rb_root.rb_node;
}
static void __sort_chain_graph_rel(struct callchain_node *node,
double min_percent)
{
struct callchain_node *child;
u64 min_hit;
node->rb_root = RB_ROOT;
min_hit = ceil(node->children_hit * min_percent);
chain_for_each_child(child, node) {
__sort_chain_graph_rel(child, min_percent);
if (callchain_cumul_hits(child) >= min_hit)
rb_insert_callchain(&node->rb_root, child,
CHAIN_GRAPH_REL);
}
}
static void
sort_chain_graph_rel(struct rb_root *rb_root, struct callchain_root *chain_root,
u64 min_hit __used, struct callchain_param *param)
{
__sort_chain_graph_rel(&chain_root->node, param->min_percent / 100.0);
rb_root->rb_node = chain_root->node.rb_root.rb_node;
}
int callchain_register_param(struct callchain_param *param)
{
switch (param->mode) {
case CHAIN_GRAPH_ABS:
param->sort = sort_chain_graph_abs;
break;
case CHAIN_GRAPH_REL:
param->sort = sort_chain_graph_rel;
break;
case CHAIN_FLAT:
param->sort = sort_chain_flat;
break;
case CHAIN_NONE:
default:
return -1;
}
return 0;
}
/*
* Create a child for a parent. If inherit_children, then the new child
* will become the new parent of it's parent children
*/
static struct callchain_node *
create_child(struct callchain_node *parent, bool inherit_children)
{
struct callchain_node *new;
new = zalloc(sizeof(*new));
if (!new) {
perror("not enough memory to create child for code path tree");
return NULL;
}
new->parent = parent;
INIT_LIST_HEAD(&new->children);
INIT_LIST_HEAD(&new->val);
if (inherit_children) {
struct callchain_node *next;
list_splice(&parent->children, &new->children);
INIT_LIST_HEAD(&parent->children);
chain_for_each_child(next, new)
next->parent = new;
}
list_add_tail(&new->siblings, &parent->children);
return new;
}
/*
* Fill the node with callchain values
*/
static void
fill_node(struct callchain_node *node, struct callchain_cursor *cursor)
{
struct callchain_cursor_node *cursor_node;
node->val_nr = cursor->nr - cursor->pos;
if (!node->val_nr)
pr_warning("Warning: empty node in callchain tree\n");
cursor_node = callchain_cursor_current(cursor);
while (cursor_node) {
struct callchain_list *call;
call = zalloc(sizeof(*call));
if (!call) {
perror("not enough memory for the code path tree");
return;
}
call->ip = cursor_node->ip;
call->ms.sym = cursor_node->sym;
call->ms.map = cursor_node->map;
list_add_tail(&call->list, &node->val);
callchain_cursor_advance(cursor);
cursor_node = callchain_cursor_current(cursor);
}
}
static void
add_child(struct callchain_node *parent,
struct callchain_cursor *cursor,
u64 period)
{
struct callchain_node *new;
new = create_child(parent, false);
fill_node(new, cursor);
new->children_hit = 0;
new->hit = period;
}
/*
* Split the parent in two parts (a new child is created) and
* give a part of its callchain to the created child.
* Then create another child to host the given callchain of new branch
*/
static void
split_add_child(struct callchain_node *parent,
struct callchain_cursor *cursor,
struct callchain_list *to_split,
u64 idx_parents, u64 idx_local, u64 period)
{
struct callchain_node *new;
struct list_head *old_tail;
unsigned int idx_total = idx_parents + idx_local;
/* split */
new = create_child(parent, true);
/* split the callchain and move a part to the new child */
old_tail = parent->val.prev;
list_del_range(&to_split->list, old_tail);
new->val.next = &to_split->list;
new->val.prev = old_tail;
to_split->list.prev = &new->val;
old_tail->next = &new->val;
/* split the hits */
new->hit = parent->hit;
new->children_hit = parent->children_hit;
parent->children_hit = callchain_cumul_hits(new);
new->val_nr = parent->val_nr - idx_local;
parent->val_nr = idx_local;
/* create a new child for the new branch if any */
if (idx_total < cursor->nr) {
parent->hit = 0;
add_child(parent, cursor, period);
parent->children_hit += period;
} else {
parent->hit = period;
}
}
static int
append_chain(struct callchain_node *root,
struct callchain_cursor *cursor,
u64 period);
static void
append_chain_children(struct callchain_node *root,
struct callchain_cursor *cursor,
u64 period)
{
struct callchain_node *rnode;
/* lookup in childrens */
chain_for_each_child(rnode, root) {
unsigned int ret = append_chain(rnode, cursor, period);
if (!ret)
goto inc_children_hit;
}
/* nothing in children, add to the current node */
add_child(root, cursor, period);
inc_children_hit:
root->children_hit += period;
}
static int
append_chain(struct callchain_node *root,
struct callchain_cursor *cursor,
u64 period)
{
struct callchain_cursor_node *curr_snap = cursor->curr;
struct callchain_list *cnode;
u64 start = cursor->pos;
bool found = false;
u64 matches;
/*
* Lookup in the current node
* If we have a symbol, then compare the start to match
* anywhere inside a function.
*/
list_for_each_entry(cnode, &root->val, list) {
struct callchain_cursor_node *node;
struct symbol *sym;
node = callchain_cursor_current(cursor);
if (!node)
break;
sym = node->sym;
if (cnode->ms.sym && sym) {
if (cnode->ms.sym->start != sym->start)
break;
} else if (cnode->ip != node->ip)
break;
if (!found)
found = true;
callchain_cursor_advance(cursor);
}
/* matches not, relay on the parent */
if (!found) {
cursor->curr = curr_snap;
cursor->pos = start;
return -1;
}
matches = cursor->pos - start;
/* we match only a part of the node. Split it and add the new chain */
if (matches < root->val_nr) {
split_add_child(root, cursor, cnode, start, matches, period);
return 0;
}
/* we match 100% of the path, increment the hit */
if (matches == root->val_nr && cursor->pos == cursor->nr) {
root->hit += period;
return 0;
}
/* We match the node and still have a part remaining */
append_chain_children(root, cursor, period);
return 0;
}
int callchain_append(struct callchain_root *root,
struct callchain_cursor *cursor,
u64 period)
{
if (!cursor->nr)
return 0;
callchain_cursor_commit(cursor);
append_chain_children(&root->node, cursor, period);
if (cursor->nr > root->max_depth)
root->max_depth = cursor->nr;
return 0;
}
static int
merge_chain_branch(struct callchain_cursor *cursor,
struct callchain_node *dst, struct callchain_node *src)
{
struct callchain_cursor_node **old_last = cursor->last;
struct callchain_node *child, *next_child;
struct callchain_list *list, *next_list;
int old_pos = cursor->nr;
int err = 0;
list_for_each_entry_safe(list, next_list, &src->val, list) {
callchain_cursor_append(cursor, list->ip,
list->ms.map, list->ms.sym);
list_del(&list->list);
free(list);
}
if (src->hit) {
callchain_cursor_commit(cursor);
append_chain_children(dst, cursor, src->hit);
}
chain_for_each_child_safe(child, next_child, src) {
err = merge_chain_branch(cursor, dst, child);
if (err)
break;
list_del(&child->siblings);
free(child);
}
cursor->nr = old_pos;
cursor->last = old_last;
return err;
}
int callchain_merge(struct callchain_cursor *cursor,
struct callchain_root *dst, struct callchain_root *src)
{
return merge_chain_branch(cursor, &dst->node, &src->node);
}
int callchain_cursor_append(struct callchain_cursor *cursor,
u64 ip, struct map *map, struct symbol *sym)
{
struct callchain_cursor_node *node = *cursor->last;
if (!node) {
node = calloc(sizeof(*node), 1);
if (!node)
return -ENOMEM;
*cursor->last = node;
}
node->ip = ip;
node->map = map;
node->sym = sym;
cursor->nr++;
cursor->last = &node->next;
return 0;
}
| gpl-2.0 |
arkas/Samsung-GT-I5510-Kernel | sound/pci/ice1712/hoontech.c | 10067 | 11152 | /*
* ALSA driver for ICEnsemble ICE1712 (Envy24)
*
* Lowlevel functions for Hoontech STDSP24
*
* Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include "ice1712.h"
#include "hoontech.h"
/* Hoontech-specific setting */
struct hoontech_spec {
unsigned char boxbits[4];
unsigned int config;
unsigned short boxconfig[4];
};
static void __devinit snd_ice1712_stdsp24_gpio_write(struct snd_ice1712 *ice, unsigned char byte)
{
byte |= ICE1712_STDSP24_CLOCK_BIT;
udelay(100);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
byte &= ~ICE1712_STDSP24_CLOCK_BIT;
udelay(100);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
byte |= ICE1712_STDSP24_CLOCK_BIT;
udelay(100);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
}
static void __devinit snd_ice1712_stdsp24_darear(struct snd_ice1712 *ice, int activate)
{
struct hoontech_spec *spec = ice->spec;
mutex_lock(&ice->gpio_mutex);
ICE1712_STDSP24_0_DAREAR(spec->boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[0]);
mutex_unlock(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_mute(struct snd_ice1712 *ice, int activate)
{
struct hoontech_spec *spec = ice->spec;
mutex_lock(&ice->gpio_mutex);
ICE1712_STDSP24_3_MUTE(spec->boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[3]);
mutex_unlock(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_insel(struct snd_ice1712 *ice, int activate)
{
struct hoontech_spec *spec = ice->spec;
mutex_lock(&ice->gpio_mutex);
ICE1712_STDSP24_3_INSEL(spec->boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[3]);
mutex_unlock(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_box_channel(struct snd_ice1712 *ice, int box, int chn, int activate)
{
struct hoontech_spec *spec = ice->spec;
mutex_lock(&ice->gpio_mutex);
/* select box */
ICE1712_STDSP24_0_BOX(spec->boxbits, box);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[0]);
/* prepare for write */
if (chn == 3)
ICE1712_STDSP24_2_CHN4(spec->boxbits, 0);
ICE1712_STDSP24_2_MIDI1(spec->boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[3]);
ICE1712_STDSP24_1_CHN1(spec->boxbits, 1);
ICE1712_STDSP24_1_CHN2(spec->boxbits, 1);
ICE1712_STDSP24_1_CHN3(spec->boxbits, 1);
ICE1712_STDSP24_2_CHN4(spec->boxbits, 1);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[1]);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
udelay(100);
if (chn == 3) {
ICE1712_STDSP24_2_CHN4(spec->boxbits, 0);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
} else {
switch (chn) {
case 0: ICE1712_STDSP24_1_CHN1(spec->boxbits, 0); break;
case 1: ICE1712_STDSP24_1_CHN2(spec->boxbits, 0); break;
case 2: ICE1712_STDSP24_1_CHN3(spec->boxbits, 0); break;
}
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[1]);
}
udelay(100);
ICE1712_STDSP24_1_CHN1(spec->boxbits, 1);
ICE1712_STDSP24_1_CHN2(spec->boxbits, 1);
ICE1712_STDSP24_1_CHN3(spec->boxbits, 1);
ICE1712_STDSP24_2_CHN4(spec->boxbits, 1);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[1]);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
udelay(100);
ICE1712_STDSP24_2_MIDI1(spec->boxbits, 0);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
mutex_unlock(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_box_midi(struct snd_ice1712 *ice, int box, int master)
{
struct hoontech_spec *spec = ice->spec;
mutex_lock(&ice->gpio_mutex);
/* select box */
ICE1712_STDSP24_0_BOX(spec->boxbits, box);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[0]);
ICE1712_STDSP24_2_MIDIIN(spec->boxbits, 1);
ICE1712_STDSP24_2_MIDI1(spec->boxbits, master);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[3]);
udelay(100);
ICE1712_STDSP24_2_MIDIIN(spec->boxbits, 0);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
mdelay(10);
ICE1712_STDSP24_2_MIDIIN(spec->boxbits, 1);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[2]);
mutex_unlock(&ice->gpio_mutex);
}
static void __devinit snd_ice1712_stdsp24_midi2(struct snd_ice1712 *ice, int activate)
{
struct hoontech_spec *spec = ice->spec;
mutex_lock(&ice->gpio_mutex);
ICE1712_STDSP24_3_MIDI2(spec->boxbits, activate);
snd_ice1712_stdsp24_gpio_write(ice, spec->boxbits[3]);
mutex_unlock(&ice->gpio_mutex);
}
static int __devinit snd_ice1712_hoontech_init(struct snd_ice1712 *ice)
{
struct hoontech_spec *spec;
int box, chn;
ice->num_total_dacs = 8;
ice->num_total_adcs = 8;
spec = kzalloc(sizeof(*spec), GFP_KERNEL);
if (!spec)
return -ENOMEM;
ice->spec = spec;
ICE1712_STDSP24_SET_ADDR(spec->boxbits, 0);
ICE1712_STDSP24_CLOCK(spec->boxbits, 0, 1);
ICE1712_STDSP24_0_BOX(spec->boxbits, 0);
ICE1712_STDSP24_0_DAREAR(spec->boxbits, 0);
ICE1712_STDSP24_SET_ADDR(spec->boxbits, 1);
ICE1712_STDSP24_CLOCK(spec->boxbits, 1, 1);
ICE1712_STDSP24_1_CHN1(spec->boxbits, 1);
ICE1712_STDSP24_1_CHN2(spec->boxbits, 1);
ICE1712_STDSP24_1_CHN3(spec->boxbits, 1);
ICE1712_STDSP24_SET_ADDR(spec->boxbits, 2);
ICE1712_STDSP24_CLOCK(spec->boxbits, 2, 1);
ICE1712_STDSP24_2_CHN4(spec->boxbits, 1);
ICE1712_STDSP24_2_MIDIIN(spec->boxbits, 1);
ICE1712_STDSP24_2_MIDI1(spec->boxbits, 0);
ICE1712_STDSP24_SET_ADDR(spec->boxbits, 3);
ICE1712_STDSP24_CLOCK(spec->boxbits, 3, 1);
ICE1712_STDSP24_3_MIDI2(spec->boxbits, 0);
ICE1712_STDSP24_3_MUTE(spec->boxbits, 1);
ICE1712_STDSP24_3_INSEL(spec->boxbits, 0);
/* let's go - activate only functions in first box */
spec->config = 0;
/* ICE1712_STDSP24_MUTE |
ICE1712_STDSP24_INSEL |
ICE1712_STDSP24_DAREAR; */
/* These boxconfigs have caused problems in the past.
* The code is not optimal, but should now enable a working config to
* be achieved.
* ** MIDI IN can only be configured on one box **
* ICE1712_STDSP24_BOX_MIDI1 needs to be set for that box.
* Tests on a ADAC2000 box suggest the box config flags do not
* work as would be expected, and the inputs are crossed.
* Setting ICE1712_STDSP24_BOX_MIDI1 and ICE1712_STDSP24_BOX_MIDI2
* on the same box connects MIDI-In to both 401 uarts; both outputs
* are then active on all boxes.
* The default config here sets up everything on the first box.
* Alan Horstmann 5.2.2008
*/
spec->boxconfig[0] = ICE1712_STDSP24_BOX_CHN1 |
ICE1712_STDSP24_BOX_CHN2 |
ICE1712_STDSP24_BOX_CHN3 |
ICE1712_STDSP24_BOX_CHN4 |
ICE1712_STDSP24_BOX_MIDI1 |
ICE1712_STDSP24_BOX_MIDI2;
spec->boxconfig[1] =
spec->boxconfig[2] =
spec->boxconfig[3] = 0;
snd_ice1712_stdsp24_darear(ice,
(spec->config & ICE1712_STDSP24_DAREAR) ? 1 : 0);
snd_ice1712_stdsp24_mute(ice,
(spec->config & ICE1712_STDSP24_MUTE) ? 1 : 0);
snd_ice1712_stdsp24_insel(ice,
(spec->config & ICE1712_STDSP24_INSEL) ? 1 : 0);
for (box = 0; box < 4; box++) {
if (spec->boxconfig[box] & ICE1712_STDSP24_BOX_MIDI2)
snd_ice1712_stdsp24_midi2(ice, 1);
for (chn = 0; chn < 4; chn++)
snd_ice1712_stdsp24_box_channel(ice, box, chn,
(spec->boxconfig[box] & (1 << chn)) ? 1 : 0);
if (spec->boxconfig[box] & ICE1712_STDSP24_BOX_MIDI1)
snd_ice1712_stdsp24_box_midi(ice, box, 1);
}
return 0;
}
/*
* AK4524 access
*/
/* start callback for STDSP24 with modified hardware */
static void stdsp24_ak4524_lock(struct snd_akm4xxx *ak, int chip)
{
struct snd_ice1712 *ice = ak->private_data[0];
unsigned char tmp;
snd_ice1712_save_gpio_status(ice);
tmp = ICE1712_STDSP24_SERIAL_DATA |
ICE1712_STDSP24_SERIAL_CLOCK |
ICE1712_STDSP24_AK4524_CS;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
ice->gpio.direction | tmp);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~tmp);
}
static int __devinit snd_ice1712_value_init(struct snd_ice1712 *ice)
{
/* Hoontech STDSP24 with modified hardware */
static struct snd_akm4xxx akm_stdsp24_mv __devinitdata = {
.num_adcs = 2,
.num_dacs = 2,
.type = SND_AK4524,
.ops = {
.lock = stdsp24_ak4524_lock
}
};
static struct snd_ak4xxx_private akm_stdsp24_mv_priv __devinitdata = {
.caddr = 2,
.cif = 1, /* CIF high */
.data_mask = ICE1712_STDSP24_SERIAL_DATA,
.clk_mask = ICE1712_STDSP24_SERIAL_CLOCK,
.cs_mask = ICE1712_STDSP24_AK4524_CS,
.cs_addr = ICE1712_STDSP24_AK4524_CS,
.cs_none = 0,
.add_flags = 0,
};
int err;
struct snd_akm4xxx *ak;
/* set the analog DACs */
ice->num_total_dacs = 2;
/* set the analog ADCs */
ice->num_total_adcs = 2;
/* analog section */
ak = ice->akm = kmalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
if (! ak)
return -ENOMEM;
ice->akm_codecs = 1;
err = snd_ice1712_akm4xxx_init(ak, &akm_stdsp24_mv, &akm_stdsp24_mv_priv, ice);
if (err < 0)
return err;
/* ak4524 controls */
err = snd_ice1712_akm4xxx_build_controls(ice);
if (err < 0)
return err;
return 0;
}
static int __devinit snd_ice1712_ez8_init(struct snd_ice1712 *ice)
{
ice->gpio.write_mask = ice->eeprom.gpiomask;
ice->gpio.direction = ice->eeprom.gpiodir;
snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ice->eeprom.gpiomask);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->eeprom.gpiodir);
snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, ice->eeprom.gpiostate);
return 0;
}
/* entry point */
struct snd_ice1712_card_info snd_ice1712_hoontech_cards[] __devinitdata = {
{
.subvendor = ICE1712_SUBDEVICE_STDSP24,
.name = "Hoontech SoundTrack Audio DSP24",
.model = "dsp24",
.chip_init = snd_ice1712_hoontech_init,
.mpu401_1_name = "MIDI-1 Hoontech/STA DSP24",
.mpu401_2_name = "MIDI-2 Hoontech/STA DSP24",
},
{
.subvendor = ICE1712_SUBDEVICE_STDSP24_VALUE, /* a dummy id */
.name = "Hoontech SoundTrack Audio DSP24 Value",
.model = "dsp24_value",
.chip_init = snd_ice1712_value_init,
},
{
.subvendor = ICE1712_SUBDEVICE_STDSP24_MEDIA7_1,
.name = "Hoontech STA DSP24 Media 7.1",
.model = "dsp24_71",
.chip_init = snd_ice1712_hoontech_init,
},
{
.subvendor = ICE1712_SUBDEVICE_EVENT_EZ8, /* a dummy id */
.name = "Event Electronics EZ8",
.model = "ez8",
.chip_init = snd_ice1712_ez8_init,
},
{ } /* terminator */
};
| gpl-2.0 |
puskyer/android_kernel_motorola_olympus | fs/ncpfs/ncpsign_kernel.c | 12883 | 3729 | /*
* ncpsign_kernel.c
*
* Arne de Bruijn (arne@knoware.nl), 1997
*
*/
#ifdef CONFIG_NCPFS_PACKET_SIGNING
#include <linux/string.h>
#include <linux/ncp.h>
#include <linux/bitops.h>
#include "ncp_fs.h"
#include "ncpsign_kernel.h"
/* i386: 32-bit, little endian, handles mis-alignment */
#ifdef __i386__
#define GET_LE32(p) (*(const int *)(p))
#define PUT_LE32(p,v) { *(int *)(p)=v; }
#else
/* from include/ncplib.h */
#define BVAL(buf,pos) (((const __u8 *)(buf))[pos])
#define PVAL(buf,pos) ((unsigned)BVAL(buf,pos))
#define BSET(buf,pos,val) (((__u8 *)(buf))[pos] = (val))
static inline __u16
WVAL_LH(const __u8 * buf, int pos)
{
return PVAL(buf, pos) | PVAL(buf, pos + 1) << 8;
}
static inline __u32
DVAL_LH(const __u8 * buf, int pos)
{
return WVAL_LH(buf, pos) | WVAL_LH(buf, pos + 2) << 16;
}
static inline void
WSET_LH(__u8 * buf, int pos, __u16 val)
{
BSET(buf, pos, val & 0xff);
BSET(buf, pos + 1, val >> 8);
}
static inline void
DSET_LH(__u8 * buf, int pos, __u32 val)
{
WSET_LH(buf, pos, val & 0xffff);
WSET_LH(buf, pos + 2, val >> 16);
}
#define GET_LE32(p) DVAL_LH(p,0)
#define PUT_LE32(p,v) DSET_LH(p,0,v)
#endif
static void nwsign(char *r_data1, char *r_data2, char *outdata) {
int i;
unsigned int w0,w1,w2,w3;
static int rbit[4]={0, 2, 1, 3};
#ifdef __i386__
unsigned int *data2=(unsigned int *)r_data2;
#else
unsigned int data2[16];
for (i=0;i<16;i++)
data2[i]=GET_LE32(r_data2+(i<<2));
#endif
w0=GET_LE32(r_data1);
w1=GET_LE32(r_data1+4);
w2=GET_LE32(r_data1+8);
w3=GET_LE32(r_data1+12);
for (i=0;i<16;i+=4) {
w0=rol32(w0 + ((w1 & w2) | ((~w1) & w3)) + data2[i+0],3);
w3=rol32(w3 + ((w0 & w1) | ((~w0) & w2)) + data2[i+1],7);
w2=rol32(w2 + ((w3 & w0) | ((~w3) & w1)) + data2[i+2],11);
w1=rol32(w1 + ((w2 & w3) | ((~w2) & w0)) + data2[i+3],19);
}
for (i=0;i<4;i++) {
w0=rol32(w0 + (((w2 | w3) & w1) | (w2 & w3)) + 0x5a827999 + data2[i+0],3);
w3=rol32(w3 + (((w1 | w2) & w0) | (w1 & w2)) + 0x5a827999 + data2[i+4],5);
w2=rol32(w2 + (((w0 | w1) & w3) | (w0 & w1)) + 0x5a827999 + data2[i+8],9);
w1=rol32(w1 + (((w3 | w0) & w2) | (w3 & w0)) + 0x5a827999 + data2[i+12],13);
}
for (i=0;i<4;i++) {
w0=rol32(w0 + ((w1 ^ w2) ^ w3) + 0x6ed9eba1 + data2[rbit[i]+0],3);
w3=rol32(w3 + ((w0 ^ w1) ^ w2) + 0x6ed9eba1 + data2[rbit[i]+8],9);
w2=rol32(w2 + ((w3 ^ w0) ^ w1) + 0x6ed9eba1 + data2[rbit[i]+4],11);
w1=rol32(w1 + ((w2 ^ w3) ^ w0) + 0x6ed9eba1 + data2[rbit[i]+12],15);
}
PUT_LE32(outdata,(w0+GET_LE32(r_data1)) & 0xffffffff);
PUT_LE32(outdata+4,(w1+GET_LE32(r_data1+4)) & 0xffffffff);
PUT_LE32(outdata+8,(w2+GET_LE32(r_data1+8)) & 0xffffffff);
PUT_LE32(outdata+12,(w3+GET_LE32(r_data1+12)) & 0xffffffff);
}
/* Make a signature for the current packet and add it at the end of the */
/* packet. */
void __sign_packet(struct ncp_server *server, const char *packet, size_t size, __u32 totalsize, void *sign_buff) {
unsigned char data[64];
memcpy(data, server->sign_root, 8);
*(__u32*)(data + 8) = totalsize;
if (size < 52) {
memcpy(data + 12, packet, size);
memset(data + 12 + size, 0, 52 - size);
} else {
memcpy(data + 12, packet, 52);
}
nwsign(server->sign_last, data, server->sign_last);
memcpy(sign_buff, server->sign_last, 8);
}
int sign_verify_reply(struct ncp_server *server, const char *packet, size_t size, __u32 totalsize, const void *sign_buff) {
unsigned char data[64];
unsigned char hash[16];
memcpy(data, server->sign_root, 8);
*(__u32*)(data + 8) = totalsize;
if (size < 52) {
memcpy(data + 12, packet, size);
memset(data + 12 + size, 0, 52 - size);
} else {
memcpy(data + 12, packet, 52);
}
nwsign(server->sign_last, data, hash);
return memcmp(sign_buff, hash, 8);
}
#endif /* CONFIG_NCPFS_PACKET_SIGNING */
| gpl-2.0 |
hanjin1987/hw_msm8x25_kernel | arch/mips/pci/fixup-capcella.c | 13651 | 1580 | /*
* fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups.
*
* Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/vr41xx/capcella.h>
/*
* Shortcuts
*/
#define INT1 RTL8139_1_IRQ
#define INT2 RTL8139_2_IRQ
#define INTA PC104PLUS_INTA_IRQ
#define INTB PC104PLUS_INTB_IRQ
#define INTC PC104PLUS_INTC_IRQ
#define INTD PC104PLUS_INTD_IRQ
static char irq_tab_capcella[][5] __initdata = {
[11] = { -1, INT1, INT1, INT1, INT1 },
[12] = { -1, INT2, INT2, INT2, INT2 },
[14] = { -1, INTA, INTB, INTC, INTD }
};
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return irq_tab_capcella[slot][pin];
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
| gpl-2.0 |
SlimRoms/kernel_motorola_msm8992 | arch/mips/pci/fixup-capcella.c | 13651 | 1580 | /*
* fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups.
*
* Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/vr41xx/capcella.h>
/*
* Shortcuts
*/
#define INT1 RTL8139_1_IRQ
#define INT2 RTL8139_2_IRQ
#define INTA PC104PLUS_INTA_IRQ
#define INTB PC104PLUS_INTB_IRQ
#define INTC PC104PLUS_INTC_IRQ
#define INTD PC104PLUS_INTD_IRQ
static char irq_tab_capcella[][5] __initdata = {
[11] = { -1, INT1, INT1, INT1, INT1 },
[12] = { -1, INT2, INT2, INT2, INT2 },
[14] = { -1, INTA, INTB, INTC, INTD }
};
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return irq_tab_capcella[slot][pin];
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
| gpl-2.0 |
KyleCo76/FIK | drivers/video/tegra/host/host1x/host1x_intr.c | 84 | 9345 | /*
* drivers/video/tegra/host/host1x/host1x_intr.c
*
* Tegra Graphics Host Interrupt Management
*
* Copyright (C) 2010 Google, Inc.
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/ktime.h>
#include "nvhost_intr.h"
#include "dev.h"
/* Spacing between sync registers */
#define REGISTER_STRIDE 4
static void t20_intr_syncpt_intr_ack(struct nvhost_intr_syncpt *syncpt,
bool disable_intr);
static void t20_intr_enable_syncpt_intr(struct nvhost_intr *intr, u32 id);
static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
u32 id, u32 thresh);
static void syncpt_thresh_cascade_fn(struct work_struct *work)
{
struct nvhost_intr_syncpt *sp =
container_of(work, struct nvhost_intr_syncpt, work);
nvhost_syncpt_thresh_fn(sp);
}
static irqreturn_t syncpt_thresh_cascade_isr(int irq, void *dev_id)
{
struct nvhost_master *dev = dev_id;
void __iomem *sync_regs = dev->sync_aperture;
struct nvhost_intr *intr = &dev->intr;
unsigned long reg;
int i, id;
for (i = 0; i < DIV_ROUND_UP(dev->info.nb_pts, 32); i++) {
reg = readl(sync_regs +
host1x_sync_syncpt_thresh_cpu0_int_status_r() +
i * REGISTER_STRIDE);
for_each_set_bit(id, ®, 32) {
struct nvhost_intr_syncpt *sp;
int sp_id = i * 32 + id;
if (unlikely(sp_id >= dev->info.nb_pts)) {
dev_err(&dev->dev->dev, "%s(): syncpoint id %d is beyond the number of syncpoints (%d)\n",
__func__, sp_id, dev->info.nb_pts);
goto out;
}
sp = intr->syncpt + sp_id;
ktime_get_ts(&sp->isr_recv);
/* handle syncpoint 0 increments immediately */
if (sp_id == 0) {
dev_warn(&dev->dev->dev, "%s(): syncpoint id 0 incremented\n",
__func__);
nvhost_syncpt_patch_check(&dev->syncpt);
t20_intr_syncpt_intr_ack(sp, false);
} else {
t20_intr_syncpt_intr_ack(sp, true);
queue_work(intr->wq, &sp->work);
}
}
}
out:
return IRQ_HANDLED;
}
static void t20_intr_init_host_sync(struct nvhost_intr *intr)
{
struct nvhost_master *dev = intr_to_dev(intr);
void __iomem *sync_regs = dev->sync_aperture;
int i, err;
intr_op().disable_all_syncpt_intrs(intr);
for (i = 0; i < dev->info.nb_pts; i++)
INIT_WORK(&intr->syncpt[i].work, syncpt_thresh_cascade_fn);
err = request_irq(intr->syncpt_irq,
syncpt_thresh_cascade_isr,
IRQF_SHARED, "host_syncpt", dev);
if (err)
BUG();
/* increase the auto-ack timout to the maximum value. 2d will hang
* otherwise on ap20.
*/
writel(0xff, sync_regs + host1x_sync_ctxsw_timeout_cfg_r());
/* enable syncpoint 0 interrupt */
t20_intr_set_syncpt_threshold(intr, 0, 1);
t20_intr_enable_syncpt_intr(intr, 0);
}
static void t20_intr_set_host_clocks_per_usec(struct nvhost_intr *intr, u32 cpm)
{
struct nvhost_master *dev = intr_to_dev(intr);
void __iomem *sync_regs = dev->sync_aperture;
/* write microsecond clock register */
writel(cpm, sync_regs + host1x_sync_usec_clk_r());
/* set the ip_busy_timeout */
writel(cpm * 500000, sync_regs + host1x_sync_ip_busy_timeout_r());
}
static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
u32 id, u32 thresh)
{
struct nvhost_master *dev = intr_to_dev(intr);
void __iomem *sync_regs = dev->sync_aperture;
writel(thresh, sync_regs +
(host1x_sync_syncpt_int_thresh_0_r() + id * REGISTER_STRIDE));
}
static void t20_intr_enable_syncpt_intr(struct nvhost_intr *intr, u32 id)
{
struct nvhost_master *dev = intr_to_dev(intr);
void __iomem *sync_regs = dev->sync_aperture;
writel(bit_mask(id), sync_regs +
host1x_sync_syncpt_thresh_int_enable_cpu0_r() +
bit_word(id) * REGISTER_STRIDE);
}
static void t20_intr_disable_syncpt_intr(struct nvhost_intr *intr, u32 id)
{
struct nvhost_master *dev = intr_to_dev(intr);
void __iomem *sync_regs = dev->sync_aperture;
writel(bit_mask(id), sync_regs +
host1x_sync_syncpt_thresh_int_disable_r() +
bit_word(id) * REGISTER_STRIDE);
/* clear status for both cpu's */
writel(bit_mask(id), sync_regs +
host1x_sync_syncpt_thresh_cpu0_int_status_r() +
bit_word(id) * REGISTER_STRIDE);
writel(bit_mask(id), sync_regs +
host1x_sync_syncpt_thresh_cpu1_int_status_r() +
bit_word(id) * REGISTER_STRIDE);
}
static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr)
{
struct nvhost_master *dev = intr_to_dev(intr);
void __iomem *sync_regs = dev->sync_aperture;
u32 reg;
for (reg = 0; reg < bit_word(dev->info.nb_pts) * REGISTER_STRIDE;
reg += REGISTER_STRIDE) {
/* disable interrupts for both cpu's */
writel(0xffffffffu, sync_regs +
host1x_sync_syncpt_thresh_int_disable_r() +
reg);
/* clear status for both cpu's */
writel(0xffffffffu, sync_regs +
host1x_sync_syncpt_thresh_cpu0_int_status_r() + reg);
writel(0xffffffffu, sync_regs +
host1x_sync_syncpt_thresh_cpu1_int_status_r() + reg);
}
}
/*
* Acknowledge that the syncpoint interrupt is handled. If disable_intr is set,
* the syncpoint interrupt is also disabled.
*/
static void t20_intr_syncpt_intr_ack(struct nvhost_intr_syncpt *syncpt,
bool disable_intr)
{
unsigned int id = syncpt->id;
struct nvhost_intr *intr = intr_syncpt_to_intr(syncpt);
void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
u32 reg = bit_word(id) * REGISTER_STRIDE;
if (disable_intr)
writel(bit_mask(id), sync_regs +
host1x_sync_syncpt_thresh_int_disable_r() + reg);
writel(bit_mask(id), sync_regs +
host1x_sync_syncpt_thresh_cpu0_int_status_r() + reg);
}
/**
* Host general interrupt service function
* Handles read / write failures
*/
static irqreturn_t t20_intr_host1x_isr(int irq, void *dev_id)
{
struct nvhost_intr *intr = dev_id;
void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
u32 stat;
u32 ext_stat;
u32 addr;
unsigned long intstat;
intstat = readl(sync_regs + host1x_sync_intstatus_r());
intr->intstatus = intstat;
/* Handle host1x interrupt in ISR */
stat = readl(sync_regs + host1x_sync_hintstatus_r());
ext_stat = readl(sync_regs + host1x_sync_hintstatus_ext_r());
if (host1x_sync_hintstatus_ext_ip_read_int_v(ext_stat)) {
addr = readl(sync_regs + host1x_sync_ip_read_timeout_addr_r());
pr_err("Host read timeout at address %x\n", addr);
}
if (host1x_sync_hintstatus_ext_ip_write_int_v(ext_stat)) {
addr = readl(sync_regs + host1x_sync_ip_write_timeout_addr_r());
pr_err("Host write timeout at address %x\n", addr);
}
writel(ext_stat, sync_regs + host1x_sync_hintstatus_ext_r());
writel(stat, sync_regs + host1x_sync_hintstatus_r());
writel(intstat, sync_regs + host1x_sync_intstatus_r());
return IRQ_HANDLED;
}
static int t20_intr_request_host_general_irq(struct nvhost_intr *intr)
{
void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
int err;
/* master disable for general (not syncpt) host interrupts */
writel(0, sync_regs + host1x_sync_intmask_r());
/* clear status & extstatus */
writel(0xfffffffful, sync_regs + host1x_sync_hintstatus_ext_r());
writel(0xfffffffful, sync_regs + host1x_sync_hintstatus_r());
err = request_irq(intr->general_irq, t20_intr_host1x_isr,
0, "host_status", intr);
if (err)
return err;
/* enable extra interrupt sources IP_READ_INT and IP_WRITE_INT */
writel(BIT(30) | BIT(31), sync_regs + host1x_sync_hintmask_ext_r());
/* enable extra interrupt sources */
writel(BIT(31), sync_regs + host1x_sync_hintmask_r());
/* enable host module interrupt to CPU0 */
writel(BIT(0), sync_regs + host1x_sync_intc0mask_r());
/* master enable for general (not syncpt) host interrupts */
writel(BIT(0), sync_regs + host1x_sync_intmask_r());
return err;
}
static void t20_intr_free_host_general_irq(struct nvhost_intr *intr)
{
void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
/* master disable for general (not syncpt) host interrupts */
writel(0, sync_regs + host1x_sync_intmask_r());
free_irq(intr->general_irq, intr);
}
static int t20_free_syncpt_irq(struct nvhost_intr *intr)
{
struct nvhost_master *dev = intr_to_dev(intr);
/* disable syncpoint 0 interrupt */
t20_intr_disable_syncpt_intr(intr, 0);
free_irq(INT_HOST1X_MPCORE_SYNCPT, dev);
flush_workqueue(intr->wq);
return 0;
}
static const struct nvhost_intr_ops host1x_intr_ops = {
.init_host_sync = t20_intr_init_host_sync,
.set_host_clocks_per_usec = t20_intr_set_host_clocks_per_usec,
.set_syncpt_threshold = t20_intr_set_syncpt_threshold,
.enable_syncpt_intr = t20_intr_enable_syncpt_intr,
.disable_syncpt_intr = t20_intr_disable_syncpt_intr,
.disable_all_syncpt_intrs = t20_intr_disable_all_syncpt_intrs,
.request_host_general_irq = t20_intr_request_host_general_irq,
.free_host_general_irq = t20_intr_free_host_general_irq,
.free_syncpt_irq = t20_free_syncpt_irq,
};
| gpl-2.0 |
vwmofo/android_kernel_htc_liberty-villec2 | drivers/cpufreq/cpufreq_intellidemand.c | 84 | 25069 | /*
* drivers/cpufreq/cpufreq_intellidemand.c
*
* Copyright (C) 2001 Russell King
* (C) 2003 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>.
* Jun Nakajima <jun.nakajima@intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/cpu.h>
#include <linux/jiffies.h>
#include <linux/kernel_stat.h>
#include <linux/mutex.h>
#include <linux/hrtimer.h>
#include <linux/tick.h>
#include <linux/ktime.h>
#include <linux/sched.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <linux/earlysuspend.h>
#define _LIMIT_LCD_OFF_CPU_MAX_FREQ_
/*
* dbs is used in this file as a shortform for demandbased switching
* It helps to keep variable names smaller, simpler
*/
#define DEF_FREQUENCY_DOWN_DIFFERENTIAL (10)
#define DEF_FREQUENCY_UP_THRESHOLD (90)
#define DEF_SAMPLING_DOWN_FACTOR (15)
#define MAX_SAMPLING_DOWN_FACTOR (100000)
#define MICRO_FREQUENCY_DOWN_DIFFERENTIAL (3)
#define MICRO_FREQUENCY_UP_THRESHOLD (85)
#define MICRO_FREQUENCY_MIN_SAMPLE_RATE (10000)
#define MIN_FREQUENCY_UP_THRESHOLD (11)
#define MAX_FREQUENCY_UP_THRESHOLD (100)
#define MIN_FREQUENCY_DOWN_DIFFERENTIAL (1)
/*
* The polling frequency of this governor depends on the capability of
* the processor. Default polling frequency is 1000 times the transition
* latency of the processor. The governor will work on any processor with
* transition latency <= 10mS, using appropriate sampling
* rate.
* For CPUs with transition latency > 10mS (mostly drivers with CPUFREQ_ETERNAL)
* this governor will not work.
* All times here are in uS.
*/
#define MIN_SAMPLING_RATE_RATIO (2)
static unsigned int min_sampling_rate;
#define LATENCY_MULTIPLIER (1000)
#define MIN_LATENCY_MULTIPLIER (100)
#define TRANSITION_LATENCY_LIMIT (10 * 1000 * 1000)
static void do_dbs_timer(struct work_struct *work);
static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
unsigned int event);
#ifdef _LIMIT_LCD_OFF_CPU_MAX_FREQ_
#ifdef CONFIG_HAS_EARLYSUSPEND
static struct early_suspend cpufreq_gov_early_suspend;
static unsigned int cpufreq_gov_lcd_status;
#endif
#endif
#ifndef CONFIG_CPU_FREQ_DEFAULT_GOV_INTELLIDEMAND
static
#endif
struct cpufreq_governor cpufreq_gov_intellidemand = {
.name = "intellidemand",
.governor = cpufreq_governor_dbs,
.max_transition_latency = TRANSITION_LATENCY_LIMIT,
.owner = THIS_MODULE,
};
/* Sampling types */
enum {DBS_NORMAL_SAMPLE, DBS_SUB_SAMPLE};
struct cpu_dbs_info_s {
cputime64_t prev_cpu_idle;
cputime64_t prev_cpu_iowait;
cputime64_t prev_cpu_wall;
cputime64_t prev_cpu_nice;
struct cpufreq_policy *cur_policy;
struct delayed_work work;
struct cpufreq_frequency_table *freq_table;
unsigned int freq_lo;
unsigned int freq_lo_jiffies;
unsigned int freq_hi_jiffies;
unsigned int rate_mult;
int cpu;
unsigned int sample_type:1;
/*
* percpu mutex that serializes governor limit change with
* do_dbs_timer invocation. We do not want do_dbs_timer to run
* when user is changing the governor or limits.
*/
struct mutex timer_mutex;
};
static DEFINE_PER_CPU(struct cpu_dbs_info_s, od_cpu_dbs_info);
static unsigned int dbs_enable; /* number of CPUs using this policy */
/*
* dbs_mutex protects data in dbs_tuners_ins from concurrent changes on
* different CPUs. It protects dbs_enable in governor start/stop.
*/
static DEFINE_MUTEX(dbs_mutex);
static struct workqueue_struct *kintellidemand_wq;
static struct dbs_tuners {
unsigned int sampling_rate;
unsigned int up_threshold;
unsigned int down_differential;
unsigned int ignore_nice;
unsigned int sampling_down_factor;
unsigned int powersave_bias;
unsigned int io_is_busy;
} dbs_tuners_ins = {
.up_threshold = DEF_FREQUENCY_UP_THRESHOLD,
.sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR,
.down_differential = DEF_FREQUENCY_DOWN_DIFFERENTIAL,
.ignore_nice = 0,
.powersave_bias = 0,
};
static inline cputime64_t get_cpu_idle_time_jiffy(unsigned int cpu,
cputime64_t *wall)
{
u64 idle_time;
u64 cur_wall_time;
u64 busy_time;
cur_wall_time = jiffies64_to_cputime64(get_jiffies_64());
busy_time = kcpustat_cpu(cpu).cpustat[CPUTIME_USER];
busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_SYSTEM];
busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_IRQ];
busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_SOFTIRQ];
busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_STEAL];
busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_NICE];
idle_time = cur_wall_time - busy_time;
if (wall)
*wall = jiffies_to_usecs(cur_wall_time);
return jiffies_to_usecs(idle_time);
}
static inline cputime64_t get_cpu_idle_time(unsigned int cpu, cputime64_t *wall)
{
u64 idle_time = get_cpu_idle_time_us(cpu, wall);
if (idle_time == -1ULL)
return get_cpu_idle_time_jiffy(cpu, wall);
return idle_time;
}
static inline cputime64_t get_cpu_iowait_time(unsigned int cpu, cputime64_t *wall)
{
u64 iowait_time = get_cpu_iowait_time_us(cpu, wall);
if (iowait_time == -1ULL)
return 0;
return iowait_time;
}
/*
* Find right freq to be set now with powersave_bias on.
* Returns the freq_hi to be used right now and will set freq_hi_jiffies,
* freq_lo, and freq_lo_jiffies in percpu area for averaging freqs.
*/
static unsigned int powersave_bias_target(struct cpufreq_policy *policy,
unsigned int freq_next,
unsigned int relation)
{
unsigned int freq_req, freq_reduc, freq_avg;
unsigned int freq_hi, freq_lo;
unsigned int index = 0;
unsigned int jiffies_total, jiffies_hi, jiffies_lo;
struct cpu_dbs_info_s *dbs_info = &per_cpu(od_cpu_dbs_info,
policy->cpu);
if (!dbs_info->freq_table) {
dbs_info->freq_lo = 0;
dbs_info->freq_lo_jiffies = 0;
return freq_next;
}
cpufreq_frequency_table_target(policy, dbs_info->freq_table, freq_next,
relation, &index);
freq_req = dbs_info->freq_table[index].frequency;
freq_reduc = freq_req * dbs_tuners_ins.powersave_bias / 1000;
freq_avg = freq_req - freq_reduc;
/* Find freq bounds for freq_avg in freq_table */
index = 0;
cpufreq_frequency_table_target(policy, dbs_info->freq_table, freq_avg,
CPUFREQ_RELATION_H, &index);
freq_lo = dbs_info->freq_table[index].frequency;
index = 0;
cpufreq_frequency_table_target(policy, dbs_info->freq_table, freq_avg,
CPUFREQ_RELATION_L, &index);
freq_hi = dbs_info->freq_table[index].frequency;
/* Find out how long we have to be in hi and lo freqs */
if (freq_hi == freq_lo) {
dbs_info->freq_lo = 0;
dbs_info->freq_lo_jiffies = 0;
return freq_lo;
}
jiffies_total = usecs_to_jiffies(dbs_tuners_ins.sampling_rate);
jiffies_hi = (freq_avg - freq_lo) * jiffies_total;
jiffies_hi += ((freq_hi - freq_lo) / 2);
jiffies_hi /= (freq_hi - freq_lo);
jiffies_lo = jiffies_total - jiffies_hi;
dbs_info->freq_lo = freq_lo;
dbs_info->freq_lo_jiffies = jiffies_lo;
dbs_info->freq_hi_jiffies = jiffies_hi;
return freq_hi;
}
static void intellidemand_powersave_bias_init_cpu(int cpu)
{
struct cpu_dbs_info_s *dbs_info = &per_cpu(od_cpu_dbs_info, cpu);
dbs_info->freq_table = cpufreq_frequency_get_table(cpu);
dbs_info->freq_lo = 0;
}
static void intellidemand_powersave_bias_init(void)
{
int i;
for_each_online_cpu(i) {
intellidemand_powersave_bias_init_cpu(i);
}
}
/************************** sysfs interface ************************/
static ssize_t show_sampling_rate_max(struct kobject *kobj,
struct attribute *attr, char *buf)
{
printk_once(KERN_INFO "CPUFREQ: intellidemand sampling_rate_max "
"sysfs file is deprecated - used by: %s\n", current->comm);
return sprintf(buf, "%u\n", -1U);
}
static ssize_t show_sampling_rate_min(struct kobject *kobj,
struct attribute *attr, char *buf)
{
return sprintf(buf, "%u\n", min_sampling_rate);
}
define_one_global_ro(sampling_rate_max);
define_one_global_ro(sampling_rate_min);
/* cpufreq_intellidemand Governor Tunables */
#define show_one(file_name, object) \
static ssize_t show_##file_name \
(struct kobject *kobj, struct attribute *attr, char *buf) \
{ \
return sprintf(buf, "%u\n", dbs_tuners_ins.object); \
}
show_one(sampling_rate, sampling_rate);
show_one(io_is_busy, io_is_busy);
show_one(up_threshold, up_threshold);
show_one(down_differential, down_differential);
show_one(sampling_down_factor, sampling_down_factor);
show_one(ignore_nice_load, ignore_nice);
show_one(powersave_bias, powersave_bias);
static ssize_t store_sampling_rate(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
unsigned int input;
int ret;
ret = sscanf(buf, "%u", &input);
if (ret != 1)
return -EINVAL;
mutex_lock(&dbs_mutex);
dbs_tuners_ins.sampling_rate = max(input, min_sampling_rate);
mutex_unlock(&dbs_mutex);
return count;
}
static ssize_t store_io_is_busy(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
unsigned int input;
int ret;
ret = sscanf(buf, "%u", &input);
if (ret != 1)
return -EINVAL;
mutex_lock(&dbs_mutex);
dbs_tuners_ins.io_is_busy = !!input;
mutex_unlock(&dbs_mutex);
return count;
}
static ssize_t store_up_threshold(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
unsigned int input;
int ret;
ret = sscanf(buf, "%u", &input);
if (ret != 1 || input > MAX_FREQUENCY_UP_THRESHOLD ||
input < MIN_FREQUENCY_UP_THRESHOLD) {
return -EINVAL;
}
mutex_lock(&dbs_mutex);
dbs_tuners_ins.up_threshold = input;
mutex_unlock(&dbs_mutex);
return count;
}
static ssize_t store_sampling_down_factor(struct kobject *a,
struct attribute *b, const char *buf, size_t count)
{
unsigned int input, j;
int ret;
ret = sscanf(buf, "%u", &input);
if (ret != 1 || input > MAX_SAMPLING_DOWN_FACTOR || input < 1)
return -EINVAL;
mutex_lock(&dbs_mutex);
dbs_tuners_ins.sampling_down_factor = input;
/* Reset down sampling multiplier in case it was active */
for_each_online_cpu(j) {
struct cpu_dbs_info_s *dbs_info;
dbs_info = &per_cpu(od_cpu_dbs_info, j);
dbs_info->rate_mult = 1;
}
mutex_unlock(&dbs_mutex);
return count;
}
static ssize_t store_ignore_nice_load(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
unsigned int input;
int ret;
unsigned int j;
ret = sscanf(buf, "%u", &input);
if (ret != 1)
return -EINVAL;
if (input > 1)
input = 1;
if (input == dbs_tuners_ins.ignore_nice) { /* nothing to do */
return count;
}
dbs_tuners_ins.ignore_nice = input;
/* we need to re-evaluate prev_cpu_idle */
for_each_online_cpu(j) {
struct cpu_dbs_info_s *dbs_info;
dbs_info = &per_cpu(od_cpu_dbs_info, j);
dbs_info->prev_cpu_idle = get_cpu_idle_time(j,
&dbs_info->prev_cpu_wall);
if (dbs_tuners_ins.ignore_nice)
dbs_info->prev_cpu_nice = kcpustat_cpu(j).cpustat[CPUTIME_NICE];
}
return count;
}
static ssize_t store_powersave_bias(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
unsigned int input;
int ret;
ret = sscanf(buf, "%u", &input);
if (ret != 1)
return -EINVAL;
if (input > 1000)
input = 1000;
mutex_lock(&dbs_mutex);
dbs_tuners_ins.powersave_bias = input;
intellidemand_powersave_bias_init();
mutex_unlock(&dbs_mutex);
return count;
}
static ssize_t store_down_differential(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
unsigned int input;
int ret;
ret = sscanf(buf, "%u", &input);
mutex_lock(&dbs_mutex);
if (ret != 1 || input >= dbs_tuners_ins.up_threshold ||
input < MIN_FREQUENCY_DOWN_DIFFERENTIAL) {
mutex_unlock(&dbs_mutex);
return -EINVAL;
}
dbs_tuners_ins.down_differential = input;
mutex_unlock(&dbs_mutex);
return count;
}
define_one_global_rw(sampling_rate);
define_one_global_rw(io_is_busy);
define_one_global_rw(up_threshold);
define_one_global_rw(down_differential);
define_one_global_rw(sampling_down_factor);
define_one_global_rw(ignore_nice_load);
define_one_global_rw(powersave_bias);
#ifdef CONFIG_SEC_LIMIT_MAX_FREQ // limit max freq
define_one_global_rw(lmf_temp);
define_one_global_rw(lmf_browser);
define_one_global_rw(lmf_active_load);
define_one_global_rw(lmf_inactive_load);
#endif
static struct attribute *dbs_attributes[] = {
&sampling_rate_max.attr,
&sampling_rate_min.attr,
&sampling_rate.attr,
&up_threshold.attr,
&down_differential.attr,
&sampling_down_factor.attr,
&ignore_nice_load.attr,
&powersave_bias.attr,
&io_is_busy.attr,
#ifdef CONFIG_SEC_LIMIT_MAX_FREQ // limit max freq
&lmf_temp.attr,
&lmf_browser.attr,
&lmf_active_load.attr,
&lmf_inactive_load.attr,
#endif
NULL
};
static struct attribute_group dbs_attr_group = {
.attrs = dbs_attributes,
.name = "intellidemand",
};
/************************** sysfs end ************************/
static void dbs_freq_increase(struct cpufreq_policy *p, unsigned int freq)
{
if (dbs_tuners_ins.powersave_bias)
freq = powersave_bias_target(p, freq, CPUFREQ_RELATION_H);
else if (p->cur == p->max)
return;
__cpufreq_driver_target(p, freq, dbs_tuners_ins.powersave_bias ?
CPUFREQ_RELATION_L : CPUFREQ_RELATION_H);
}
static void dbs_check_cpu(struct cpu_dbs_info_s *this_dbs_info)
{
unsigned int max_load_freq;
struct cpufreq_policy *policy;
unsigned int j;
this_dbs_info->freq_lo = 0;
policy = this_dbs_info->cur_policy;
/*
* Every sampling_rate, we check, if current idle time is less
* than 20% (default), then we try to increase frequency
* Every sampling_rate, we look for a the lowest
* frequency which can sustain the load while keeping idle time over
* 30%. If such a frequency exist, we try to decrease to this frequency.
*
* Any frequency increase takes it to the maximum frequency.
* Frequency reduction happens at minimum steps of
* 5% (default) of current frequency
*/
/* Get Absolute Load - in terms of freq */
max_load_freq = 0;
for_each_cpu(j, policy->cpus) {
struct cpu_dbs_info_s *j_dbs_info;
cputime64_t cur_wall_time, cur_idle_time, cur_iowait_time;
unsigned int idle_time, wall_time, iowait_time;
unsigned int load, load_freq;
int freq_avg;
j_dbs_info = &per_cpu(od_cpu_dbs_info, j);
cur_idle_time = get_cpu_idle_time(j, &cur_wall_time);
cur_iowait_time = get_cpu_iowait_time(j, &cur_wall_time);
wall_time = (unsigned int)
(cur_wall_time - j_dbs_info->prev_cpu_wall);
j_dbs_info->prev_cpu_wall = cur_wall_time;
idle_time = (unsigned int)
(cur_idle_time - j_dbs_info->prev_cpu_idle);
j_dbs_info->prev_cpu_idle = cur_idle_time;
iowait_time = (unsigned int)
(cur_iowait_time - j_dbs_info->prev_cpu_iowait);
j_dbs_info->prev_cpu_iowait = cur_iowait_time;
if (dbs_tuners_ins.ignore_nice) {
u64 cur_nice;
unsigned long cur_nice_jiffies;
cur_nice = kcpustat_cpu(j).cpustat[CPUTIME_NICE] -
j_dbs_info->prev_cpu_nice;
/*
* Assumption: nice time between sampling periods will
* be less than 2^32 jiffies for 32 bit sys
*/
cur_nice_jiffies = (unsigned long)
cputime64_to_jiffies64(cur_nice);
j_dbs_info->prev_cpu_nice = kcpustat_cpu(j).cpustat[CPUTIME_NICE];
idle_time += jiffies_to_usecs(cur_nice_jiffies);
}
/*
* For the purpose of ondemand, waiting for disk IO is an
* indication that you're performance critical, and not that
* the system is actually idle. So subtract the iowait time
* from the cpu idle time.
*/
if (dbs_tuners_ins.io_is_busy && idle_time >= iowait_time)
idle_time -= iowait_time;
if (unlikely(!wall_time || wall_time < idle_time))
continue;
load = 100 * (wall_time - idle_time) / wall_time;
freq_avg = __cpufreq_driver_getavg(policy, j);
if (freq_avg <= 0)
freq_avg = policy->cur;
load_freq = load * freq_avg;
if (load_freq > max_load_freq)
max_load_freq = load_freq;
}
/* Check for frequency increase */
if (max_load_freq > dbs_tuners_ins.up_threshold * policy->cur) {
/* In case of increase to max freq., freq. scales by 2 step for reducing the current consumption*/
#ifdef _LIMIT_LCD_OFF_CPU_MAX_FREQ_
if(!cpufreq_gov_lcd_status) {
if (policy->cur < policy->max) {
if (policy->cur < 400000) dbs_freq_increase(policy, 800000);
else if (policy->cur < 800000) dbs_freq_increase(policy, 1000000);
else {
this_dbs_info->rate_mult = dbs_tuners_ins.sampling_down_factor;
dbs_freq_increase(policy, policy->max);
}
}
return;
} else
#endif
/* If switching to max speed, apply sampling_down_factor */
if (policy->cur < policy->max)
this_dbs_info->rate_mult =
dbs_tuners_ins.sampling_down_factor;
dbs_freq_increase(policy, policy->max);
return;
}
/* Check for frequency decrease */
/* if we cannot reduce the frequency anymore, break out early */
if (policy->cur == policy->min)
return;
/*
* The optimal frequency is the frequency that is the lowest that
* can support the current CPU usage without triggering the up
* policy. To be safe, we focus 10 points under the threshold.
*/
if (max_load_freq <
(dbs_tuners_ins.up_threshold - dbs_tuners_ins.down_differential) *
policy->cur) {
unsigned int freq_next;
freq_next = max_load_freq /
(dbs_tuners_ins.up_threshold -
dbs_tuners_ins.down_differential);
/* No longer fully busy, reset rate_mult */
this_dbs_info->rate_mult = 1;
if (freq_next < policy->min)
freq_next = policy->min;
if (!dbs_tuners_ins.powersave_bias) {
__cpufreq_driver_target(policy, freq_next,
CPUFREQ_RELATION_L);
} else {
int freq = powersave_bias_target(policy, freq_next,
CPUFREQ_RELATION_L);
__cpufreq_driver_target(policy, freq,
CPUFREQ_RELATION_L);
}
}
}
static void do_dbs_timer(struct work_struct *work)
{
struct cpu_dbs_info_s *dbs_info =
container_of(work, struct cpu_dbs_info_s, work.work);
unsigned int cpu = dbs_info->cpu;
int sample_type = dbs_info->sample_type;
/* We want all CPUs to do sampling nearly on same jiffy */
int delay = usecs_to_jiffies(dbs_tuners_ins.sampling_rate
* dbs_info->rate_mult);
#if 0
/* Don't care too much about synchronizing the workqueue in both cpus */
if (num_online_cpus() > 1)
delay -= jiffies % delay;
#endif
mutex_lock(&dbs_info->timer_mutex);
/* Common NORMAL_SAMPLE setup */
dbs_info->sample_type = DBS_NORMAL_SAMPLE;
if (!dbs_tuners_ins.powersave_bias ||
sample_type == DBS_NORMAL_SAMPLE) {
dbs_check_cpu(dbs_info);
if (dbs_info->freq_lo) {
/* Setup timer for SUB_SAMPLE */
dbs_info->sample_type = DBS_SUB_SAMPLE;
delay = dbs_info->freq_hi_jiffies;
}
} else {
__cpufreq_driver_target(dbs_info->cur_policy,
dbs_info->freq_lo, CPUFREQ_RELATION_H);
}
queue_delayed_work_on(cpu, kintellidemand_wq, &dbs_info->work, delay);
mutex_unlock(&dbs_info->timer_mutex);
}
static inline void dbs_timer_init(struct cpu_dbs_info_s *dbs_info)
{
int delay = usecs_to_jiffies(dbs_tuners_ins.sampling_rate);
dbs_info->sample_type = DBS_NORMAL_SAMPLE;
INIT_DELAYED_WORK_DEFERRABLE(&dbs_info->work, do_dbs_timer);
queue_delayed_work_on(dbs_info->cpu, kintellidemand_wq, &dbs_info->work,
delay);
}
static inline void dbs_timer_exit(struct cpu_dbs_info_s *dbs_info)
{
cancel_delayed_work_sync(&dbs_info->work);
}
/*
* Not all CPUs want IO time to be accounted as busy; this dependson how
* efficient idling at a higher frequency/voltage is.
* Pavel Machek says this is not so for various generations of AMD and old
* Intel systems.
* Mike Chan (androidlcom) calis this is also not true for ARM.
* Because of this, whitelist specific known (series) of CPUs by default, and
* leave all others up to the user.
*/
static int should_io_be_busy(void)
{
#if defined(CONFIG_X86)
/*
* For Intel, Core 2 (model 15) andl later have an efficient idle.
*/
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
boot_cpu_data.x86 == 6 &&
boot_cpu_data.x86_model >= 15)
return 1;
#endif
#if defined(CONFIG_ARM)
return 1;
#endif
return 0;
}
static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
unsigned int event)
{
unsigned int cpu = policy->cpu;
struct cpu_dbs_info_s *this_dbs_info;
unsigned int j;
int rc;
this_dbs_info = &per_cpu(od_cpu_dbs_info, cpu);
switch (event) {
case CPUFREQ_GOV_START:
if ((!cpu_online(cpu)) || (!policy->cur))
return -EINVAL;
//per_cpu(cpu_load, cpu) = 0;
mutex_lock(&dbs_mutex);
dbs_enable++;
for_each_cpu(j, policy->cpus) {
struct cpu_dbs_info_s *j_dbs_info;
j_dbs_info = &per_cpu(od_cpu_dbs_info, j);
j_dbs_info->cur_policy = policy;
j_dbs_info->prev_cpu_idle = get_cpu_idle_time(j,
&j_dbs_info->prev_cpu_wall);
if (dbs_tuners_ins.ignore_nice)
j_dbs_info->prev_cpu_nice =
kcpustat_cpu(j).cpustat[CPUTIME_NICE];
}
this_dbs_info->cpu = cpu;
this_dbs_info->rate_mult = 1;
intellidemand_powersave_bias_init_cpu(cpu);
/*
* Start the timerschedule work, when this governor
* is used for first time
*/
if (dbs_enable == 1) {
unsigned int latency;
rc = sysfs_create_group(cpufreq_global_kobject,
&dbs_attr_group);
if (rc) {
mutex_unlock(&dbs_mutex);
return rc;
}
/* policy latency is in nS. Convert it to uS first */
latency = policy->cpuinfo.transition_latency / 1000;
if (latency == 0)
latency = 1;
/* Bring kernel and HW constraints together */
min_sampling_rate = max(min_sampling_rate,
MIN_LATENCY_MULTIPLIER * latency);
dbs_tuners_ins.sampling_rate =
max(min_sampling_rate,
latency * LATENCY_MULTIPLIER);
dbs_tuners_ins.io_is_busy = should_io_be_busy();
}
mutex_unlock(&dbs_mutex);
mutex_init(&this_dbs_info->timer_mutex);
dbs_timer_init(this_dbs_info);
break;
case CPUFREQ_GOV_STOP:
dbs_timer_exit(this_dbs_info);
mutex_lock(&dbs_mutex);
mutex_destroy(&this_dbs_info->timer_mutex);
dbs_enable--;
mutex_unlock(&dbs_mutex);
if (!dbs_enable)
sysfs_remove_group(cpufreq_global_kobject,
&dbs_attr_group);
break;
case CPUFREQ_GOV_LIMITS:
mutex_lock(&this_dbs_info->timer_mutex);
if (policy->max < this_dbs_info->cur_policy->cur)
__cpufreq_driver_target(this_dbs_info->cur_policy,
policy->max, CPUFREQ_RELATION_H);
else if (policy->min > this_dbs_info->cur_policy->cur)
__cpufreq_driver_target(this_dbs_info->cur_policy,
policy->min, CPUFREQ_RELATION_L);
mutex_unlock(&this_dbs_info->timer_mutex);
break;
}
return 0;
}
#ifdef _LIMIT_LCD_OFF_CPU_MAX_FREQ_
#ifdef CONFIG_HAS_EARLYSUSPEND
static void cpufreq_gov_suspend(struct early_suspend *h)
{
cpufreq_gov_lcd_status = 0;
pr_info("%s : cpufreq_gov_lcd_status %d\n", __func__, cpufreq_gov_lcd_status);
}
static void cpufreq_gov_resume(struct early_suspend *h)
{
cpufreq_gov_lcd_status = 1;
pr_info("%s : cpufreq_gov_lcd_status %d\n", __func__, cpufreq_gov_lcd_status);
}
#endif
#endif
static int __init cpufreq_gov_dbs_init(void)
{
int err;
cputime64_t wall;
u64 idle_time;
int cpu = get_cpu();
idle_time = get_cpu_idle_time_us(cpu, &wall);
put_cpu();
if (idle_time != -1ULL) {
/* Idle micro accounting is supported. Use finer thresholds */
dbs_tuners_ins.up_threshold = MICRO_FREQUENCY_UP_THRESHOLD;
dbs_tuners_ins.down_differential =
MICRO_FREQUENCY_DOWN_DIFFERENTIAL;
/*
* In no_hz/micro accounting case we set the minimum frequency
* not depending on HZ, but fixed (very low). The deferred
* timer might skip some samples if idle/sleeping as needed.
*/
min_sampling_rate = MICRO_FREQUENCY_MIN_SAMPLE_RATE;
} else {
/* For correct statistics, we need 10 ticks for each measure */
min_sampling_rate =
MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(1);
}
kintellidemand_wq = create_workqueue("kintellidemand");
if (!kintellidemand_wq) {
printk(KERN_ERR "Creation of kintellidemand failed\n");
return -EFAULT;
}
err = cpufreq_register_governor(&cpufreq_gov_intellidemand);
if (err)
destroy_workqueue(kintellidemand_wq);
#ifdef _LIMIT_LCD_OFF_CPU_MAX_FREQ_
#ifdef CONFIG_HAS_EARLYSUSPEND
cpufreq_gov_lcd_status = 1;
cpufreq_gov_early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
cpufreq_gov_early_suspend.suspend = cpufreq_gov_suspend;
cpufreq_gov_early_suspend.resume = cpufreq_gov_resume;
register_early_suspend(&cpufreq_gov_early_suspend);
#endif
#endif
return err;
}
static void __exit cpufreq_gov_dbs_exit(void)
{
cpufreq_unregister_governor(&cpufreq_gov_intellidemand);
destroy_workqueue(kintellidemand_wq);
}
MODULE_AUTHOR("Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>");
MODULE_AUTHOR("Alexey Starikovskiy <alexey.y.starikovskiy@intel.com>");
MODULE_DESCRIPTION("'cpufreq_intellidemand' - A dynamic cpufreq governor for "
"Low Latency Frequency Transition capable processors");
MODULE_LICENSE("GPL");
#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_INTELLIDEMAND
fs_initcall(cpufreq_gov_dbs_init);
#else
module_init(cpufreq_gov_dbs_init);
#endif
module_exit(cpufreq_gov_dbs_exit);
| gpl-2.0 |
Arakmar/android_kernel_sony_msm8660 | drivers/media/video/msm/msm_mctl_buf.c | 340 | 23470 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/workqueue.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/list.h>
#include <linux/ioctl.h>
#include <linux/spinlock.h>
#include <linux/videodev2.h>
#include <linux/vmalloc.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-device.h>
#include <linux/android_pmem.h>
#include "msm.h"
#include "msm_ispif.h"
#ifdef CONFIG_MSM_CAMERA_DEBUG
#define D(fmt, args...) pr_debug("msm_mctl_buf: " fmt, ##args)
#else
#define D(fmt, args...) do {} while (0)
#endif
static int msm_vb2_ops_queue_setup(struct vb2_queue *vq,
unsigned int *num_buffers,
unsigned int *num_planes,
unsigned long sizes[],
void *alloc_ctxs[])
{
/* get the video device */
struct msm_cam_v4l2_dev_inst *pcam_inst = vb2_get_drv_priv(vq);
struct msm_cam_v4l2_device *pcam = pcam_inst->pcam;
int i;
D("%s\n", __func__);
if (!pcam || !(*num_buffers)) {
pr_err("%s error : invalid input\n", __func__);
return -EINVAL;
}
*num_planes = pcam_inst->plane_info.num_planes;
for (i = 0; i < pcam_inst->vid_fmt.fmt.pix_mp.num_planes; i++) {
sizes[i] = PAGE_ALIGN(pcam_inst->plane_info.plane[i].size);
D("%s Inst %p : Plane %d Offset = %d Size = %ld"
"Aligned Size = %ld", __func__, pcam_inst, i,
pcam_inst->plane_info.plane[i].offset,
pcam_inst->plane_info.plane[i].size, sizes[i]);
}
return 0;
}
static void msm_vb2_ops_wait_prepare(struct vb2_queue *q)
{
/* we use polling so do not use this fn now */
}
static void msm_vb2_ops_wait_finish(struct vb2_queue *q)
{
/* we use polling so do not use this fn now */
}
static int msm_vb2_ops_buf_init(struct vb2_buffer *vb)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
struct msm_cam_v4l2_device *pcam;
struct videobuf2_contig_pmem *mem;
struct vb2_queue *vq;
uint32_t buf_idx;
struct msm_frame_buffer *buf;
int rc = 0, i;
enum videobuf2_buffer_type buf_type;
struct videobuf2_msm_offset offset;
vq = vb->vb2_queue;
pcam_inst = vb2_get_drv_priv(vq);
pcam = pcam_inst->pcam;
D("%s\n", __func__);
D("%s, inst=0x%x,idx=%d, width = %d\n", __func__,
(u32)pcam_inst, pcam_inst->my_index,
pcam_inst->vid_fmt.fmt.pix.width);
D("%s, inst=0x%x,idx=%d, height = %d\n", __func__,
(u32)pcam_inst, pcam_inst->my_index,
pcam_inst->vid_fmt.fmt.pix.height);
buf = container_of(vb, struct msm_frame_buffer, vidbuf);
if (buf->state == MSM_BUFFER_STATE_INITIALIZED)
return rc;
if (pcam_inst->plane_info.buffer_type ==
V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
buf_type = VIDEOBUF2_MULTIPLE_PLANES;
else if (pcam_inst->plane_info.buffer_type ==
V4L2_BUF_TYPE_VIDEO_CAPTURE)
buf_type = VIDEOBUF2_SINGLE_PLANE;
else
return -EINVAL;
if (buf_type == VIDEOBUF2_SINGLE_PLANE) {
offset.sp_off.y_off = pcam_inst->plane_info.sp_y_offset;
offset.sp_off.cbcr_off =
pcam_inst->plane_info.plane[0].offset;
}
buf_idx = vb->v4l2_buf.index;
for (i = 0; i < vb->num_planes; i++) {
mem = vb2_plane_cookie(vb, i);
if (buf_type == VIDEOBUF2_MULTIPLE_PLANES)
offset.data_offset =
pcam_inst->plane_info.plane[i].offset;
if (vb->v4l2_buf.memory == V4L2_MEMORY_USERPTR)
rc = videobuf2_pmem_contig_user_get(mem, &offset,
buf_type,
pcam_inst->buf_offset[buf_idx][i].addr_offset,
pcam_inst->path, pcam->mctl.client);
else
rc = videobuf2_pmem_contig_mmap_get(mem, &offset,
buf_type, pcam_inst->path);
if (rc < 0) {
pr_err("%s error initializing buffer ",
__func__);
return rc;
}
}
buf->state = MSM_BUFFER_STATE_INITIALIZED;
return rc;
}
static int msm_vb2_ops_buf_prepare(struct vb2_buffer *vb)
{
int i, rc = 0;
uint32_t len;
struct msm_cam_v4l2_dev_inst *pcam_inst;
struct msm_cam_v4l2_device *pcam;
struct msm_frame_buffer *buf;
struct vb2_queue *vq = vb->vb2_queue;
D("%s\n", __func__);
if (!vb || !vq) {
pr_err("%s error : input is NULL\n", __func__);
return -EINVAL;
}
pcam_inst = vb2_get_drv_priv(vq);
pcam = pcam_inst->pcam;
buf = container_of(vb, struct msm_frame_buffer, vidbuf);
if (!pcam || !buf) {
pr_err("%s error : pointer is NULL\n", __func__);
return -EINVAL;
}
/* by this time vid_fmt should be already set.
* return error if it is not. */
if ((pcam_inst->vid_fmt.fmt.pix.width == 0) ||
(pcam_inst->vid_fmt.fmt.pix.height == 0)) {
pr_err("%s error : pcam vid_fmt is not set\n", __func__);
return -EINVAL;
}
/* prefill in the byteused field */
for (i = 0; i < vb->num_planes; i++) {
len = vb2_plane_size(vb, i);
vb2_set_plane_payload(vb, i, len);
}
buf->state = MSM_BUFFER_STATE_PREPARED;
return rc;
}
static int msm_vb2_ops_buf_finish(struct vb2_buffer *vb)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
struct msm_cam_v4l2_device *pcam;
struct msm_frame_buffer *buf;
pcam_inst = vb2_get_drv_priv(vb->vb2_queue);
pcam = pcam_inst->pcam;
buf = container_of(vb, struct msm_frame_buffer, vidbuf);
buf->state = MSM_BUFFER_STATE_DEQUEUED;
D("%s: inst=0x%x, buf=0x, %x, idx=%d\n", __func__,
(uint32_t)pcam_inst, (uint32_t)buf, vb->v4l2_buf.index);
D("%s: inst=%p, buf=%x, idx=%d\n", __func__,
pcam_inst, (uint32_t)buf, vb->v4l2_buf.index);
return 0;
}
static void msm_vb2_ops_buf_cleanup(struct vb2_buffer *vb)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
struct msm_cam_v4l2_device *pcam;
struct videobuf2_contig_pmem *mem;
struct msm_frame_buffer *buf, *tmp;
uint32_t i, vb_phyaddr = 0, buf_phyaddr = 0;
unsigned long flags = 0;
pcam_inst = vb2_get_drv_priv(vb->vb2_queue);
pcam = pcam_inst->pcam;
buf = container_of(vb, struct msm_frame_buffer, vidbuf);
if (pcam_inst->vid_fmt.type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
for (i = 0; i < vb->num_planes; i++) {
mem = vb2_plane_cookie(vb, i);
if (!mem) {
D("%s Inst %p memory already freed up. return",
__func__, pcam_inst);
return;
}
D("%s: inst=%p, buf=0x%x, idx=%d plane id = %d\n",
__func__, pcam_inst,
(uint32_t)buf, vb->v4l2_buf.index, i);
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
list_for_each_entry_safe(buf, tmp,
&pcam_inst->free_vq, list) {
if (&buf->vidbuf == vb) {
list_del_init(&buf->list);
break;
}
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
}
} else {
mem = vb2_plane_cookie(vb, 0);
if (!mem)
return;
D("%s: inst=0x%x, buf=0x%x, idx=%d\n", __func__,
(uint32_t)pcam_inst, (uint32_t)buf, vb->v4l2_buf.index);
vb_phyaddr = (unsigned long) videobuf2_to_pmem_contig(vb, 0);
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
list_for_each_entry_safe(buf, tmp,
&pcam_inst->free_vq, list) {
buf_phyaddr = (unsigned long)
videobuf2_to_pmem_contig(&buf->vidbuf, 0);
D("%s vb_idx=%d,vb_paddr=0x%x,phyaddr=0x%x\n",
__func__, buf->vidbuf.v4l2_buf.index,
buf_phyaddr, vb_phyaddr);
if (vb_phyaddr == buf_phyaddr) {
list_del_init(&buf->list);
break;
}
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
}
for (i = 0; i < vb->num_planes; i++) {
mem = vb2_plane_cookie(vb, i);
videobuf2_pmem_contig_user_put(mem, pcam->mctl.client);
}
buf->state = MSM_BUFFER_STATE_UNUSED;
}
static int msm_vb2_ops_start_streaming(struct vb2_queue *q)
{
return 0;
}
static int msm_vb2_ops_stop_streaming(struct vb2_queue *q)
{
return 0;
}
static void msm_vb2_ops_buf_queue(struct vb2_buffer *vb)
{
struct msm_cam_v4l2_dev_inst *pcam_inst = NULL;
struct msm_cam_v4l2_device *pcam = NULL;
unsigned long flags = 0;
struct vb2_queue *vq = vb->vb2_queue;
struct msm_frame_buffer *buf;
D("%s\n", __func__);
if (!vb || !vq) {
pr_err("%s error : input is NULL\n", __func__);
return ;
}
pcam_inst = vb2_get_drv_priv(vq);
pcam = pcam_inst->pcam;
D("%s pcam_inst=%p,(vb=0x%p),idx=%d,len=%d\n",
__func__, pcam_inst,
vb, vb->v4l2_buf.index, vb->v4l2_buf.length);
D("%s pcam_inst=%p, idx=%d\n", __func__, pcam_inst,
vb->v4l2_buf.index);
buf = container_of(vb, struct msm_frame_buffer, vidbuf);
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
/* we are returning a buffer to the queue */
list_add_tail(&buf->list, &pcam_inst->free_vq);
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
buf->state = MSM_BUFFER_STATE_QUEUED;
}
static struct vb2_ops msm_vb2_ops = {
.queue_setup = msm_vb2_ops_queue_setup,
.wait_prepare = msm_vb2_ops_wait_prepare,
.wait_finish = msm_vb2_ops_wait_finish,
.buf_init = msm_vb2_ops_buf_init,
.buf_prepare = msm_vb2_ops_buf_prepare,
.buf_finish = msm_vb2_ops_buf_finish,
.buf_cleanup = msm_vb2_ops_buf_cleanup,
.start_streaming = msm_vb2_ops_start_streaming,
.stop_streaming = msm_vb2_ops_stop_streaming,
.buf_queue = msm_vb2_ops_buf_queue,
};
/* prepare a video buffer queue for a vl42 device*/
static int msm_vbqueue_init(struct msm_cam_v4l2_dev_inst *pcam_inst,
struct vb2_queue *q, enum v4l2_buf_type type)
{
if (!q) {
pr_err("%s error : input is NULL\n", __func__);
return -EINVAL;
}
spin_lock_init(&pcam_inst->vq_irqlock);
INIT_LIST_HEAD(&pcam_inst->free_vq);
videobuf2_queue_pmem_contig_init(q, type,
&msm_vb2_ops,
sizeof(struct msm_frame_buffer),
(void *)pcam_inst);
return 0;
}
int msm_mctl_img_mode_to_inst_index(struct msm_cam_media_controller *pmctl,
int image_mode, int node_type)
{
if ((image_mode >= 0) && node_type &&
pmctl->sync.pcam_sync->mctl_node.dev_inst_map[image_mode])
return pmctl->sync.pcam_sync->
mctl_node.dev_inst_map[image_mode]->my_index;
else if ((image_mode >= 0) &&
pmctl->sync.pcam_sync->dev_inst_map[image_mode])
return pmctl->sync.pcam_sync->
dev_inst_map[image_mode]->my_index;
else
return -EINVAL;
}
void msm_mctl_gettimeofday(struct timeval *tv)
{
struct timespec ts;
BUG_ON(!tv);
ktime_get_ts(&ts);
tv->tv_sec = ts.tv_sec;
tv->tv_usec = ts.tv_nsec/1000;
}
struct msm_frame_buffer *msm_mctl_buf_find(
struct msm_cam_media_controller *pmctl,
struct msm_cam_v4l2_dev_inst *pcam_inst, int del_buf,
int image_mode, struct msm_free_buf *fbuf)
{
struct msm_frame_buffer *buf = NULL, *tmp;
uint32_t buf_phyaddr = 0;
unsigned long flags = 0;
uint32_t buf_idx, offset = 0;
struct videobuf2_contig_pmem *mem;
/* we actually need a list, not a queue */
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
list_for_each_entry_safe(buf, tmp,
&pcam_inst->free_vq, list) {
buf_idx = buf->vidbuf.v4l2_buf.index;
mem = vb2_plane_cookie(&buf->vidbuf, 0);
if (mem->buffer_type == VIDEOBUF2_MULTIPLE_PLANES)
offset = mem->offset.data_offset +
pcam_inst->buf_offset[buf_idx][0].data_offset;
else
offset = mem->offset.sp_off.y_off;
buf_phyaddr = (unsigned long)
videobuf2_to_pmem_contig(&buf->vidbuf, 0) +
offset;
D("%s vb_idx=%d,vb_paddr=0x%x ch0=0x%x\n",
__func__, buf->vidbuf.v4l2_buf.index,
buf_phyaddr, fbuf->ch_paddr[0]);
if (fbuf->ch_paddr[0] == buf_phyaddr) {
if (del_buf)
list_del_init(&buf->list);
spin_unlock_irqrestore(&pcam_inst->vq_irqlock,
flags);
buf->state = MSM_BUFFER_STATE_RESERVED;
return buf;
}
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
return NULL;
}
int msm_mctl_buf_done_proc(
struct msm_cam_media_controller *pmctl,
struct msm_cam_v4l2_dev_inst *pcam_inst,
int image_mode, struct msm_free_buf *fbuf,
uint32_t *frame_id, int gen_timestamp)
{
struct msm_frame_buffer *buf = NULL;
int del_buf = 1;
buf = msm_mctl_buf_find(pmctl, pcam_inst, del_buf,
image_mode, fbuf);
if (!buf) {
pr_err("%s: buf=0x%x not found\n",
__func__, fbuf->ch_paddr[0]);
return -EINVAL;
}
if (gen_timestamp) {
if (frame_id)
buf->vidbuf.v4l2_buf.sequence = *frame_id;
msm_mctl_gettimeofday(
&buf->vidbuf.v4l2_buf.timestamp);
}
vb2_buffer_done(&buf->vidbuf, VB2_BUF_STATE_DONE);
return 0;
}
int msm_mctl_buf_done(struct msm_cam_media_controller *p_mctl,
int image_mode, struct msm_free_buf *fbuf,
uint32_t frame_id)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
int idx, rc;
int pp_divert_type = 0, pp_type = 0;
msm_mctl_check_pp(p_mctl, image_mode, &pp_divert_type, &pp_type);
D("%s: pp_type=%d, pp_divert_type = %d, frame_id = 0x%x",
__func__, pp_type, pp_divert_type, frame_id);
if (pp_type || pp_divert_type)
rc = msm_mctl_do_pp_divert(p_mctl,
image_mode, fbuf, frame_id, pp_type);
else {
idx = msm_mctl_img_mode_to_inst_index(
p_mctl, image_mode, 0);
if (idx < 0) {
pr_err("%s Invalid instance, dropping buffer\n",
__func__);
return idx;
}
pcam_inst = p_mctl->sync.pcam_sync->dev_inst[idx];
rc = msm_mctl_buf_done_proc(p_mctl, pcam_inst,
image_mode, fbuf,
&frame_id, 1);
}
return rc;
}
int msm_mctl_buf_init(struct msm_cam_v4l2_device *pcam)
{
pcam->mctl.mctl_vbqueue_init = msm_vbqueue_init;
return 0;
}
static int is_buffer_queued(struct msm_cam_v4l2_device *pcam, int image_mode)
{
int idx;
int ret = 0;
struct msm_frame_buffer *buf = NULL;
struct msm_cam_v4l2_dev_inst *pcam_inst = NULL;
idx = pcam->mctl_node.dev_inst_map[image_mode]->my_index;
pcam_inst = pcam->mctl_node.dev_inst[idx];
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
if (buf->state != MSM_BUFFER_STATE_QUEUED)
continue;
ret = 1;
}
return ret;
}
struct msm_cam_v4l2_dev_inst *msm_mctl_get_pcam_inst(
struct msm_cam_media_controller *pmctl,
int image_mode)
{
struct msm_cam_v4l2_dev_inst *pcam_inst = NULL;
struct msm_cam_v4l2_device *pcam = pmctl->sync.pcam_sync;
int idx;
if (image_mode >= 0) {
/* Valid image mode. Search the mctl node first.
* If mctl node doesnt have the instance, then
* search in the user's video node */
if (pmctl->vfe_output_mode == VFE_OUTPUTS_MAIN_AND_THUMB
|| pmctl->vfe_output_mode == VFE_OUTPUTS_THUMB_AND_MAIN) {
if (pcam->mctl_node.dev_inst_map[image_mode]
&& is_buffer_queued(pcam, image_mode)) {
idx =
pcam->mctl_node.dev_inst_map[image_mode]
->my_index;
pcam_inst = pcam->mctl_node.dev_inst[idx];
D("%s Found instance %p in mctl node device\n",
__func__, pcam_inst);
} else if (pcam->dev_inst_map[image_mode]) {
idx = pcam->dev_inst_map[image_mode]->my_index;
pcam_inst = pcam->dev_inst[idx];
D("%s Found instance %p in video device",
__func__, pcam_inst);
}
} else {
if (pcam->mctl_node.dev_inst_map[image_mode]) {
idx = pcam->mctl_node.dev_inst_map[image_mode]
->my_index;
pcam_inst = pcam->mctl_node.dev_inst[idx];
D("%s Found instance %p in mctl node device\n",
__func__, pcam_inst);
} else if (pcam->dev_inst_map[image_mode]) {
idx = pcam->dev_inst_map[image_mode]->my_index;
pcam_inst = pcam->dev_inst[idx];
D("%s Found instance %p in video device",
__func__, pcam_inst);
}
}
} else
pr_err("%s Invalid image mode %d. Return NULL\n",
__func__, image_mode);
return pcam_inst;
}
int msm_mctl_reserve_free_buf(
struct msm_cam_media_controller *pmctl,
struct msm_cam_v4l2_dev_inst *pref_pcam_inst,
int image_mode, struct msm_free_buf *free_buf)
{
struct msm_cam_v4l2_dev_inst *pcam_inst = pref_pcam_inst;
unsigned long flags = 0;
struct videobuf2_contig_pmem *mem;
struct msm_frame_buffer *buf = NULL;
int rc = -EINVAL, i;
uint32_t buf_idx, plane_offset = 0;
if (!free_buf || !pmctl) {
pr_err("%s: free_buf/pmctl is null\n", __func__);
return rc;
}
memset(free_buf, 0, sizeof(struct msm_free_buf));
/* If the caller wants to reserve a buffer from a particular
* camera instance, he would send the preferred camera instance.
* If the preferred camera instance is NULL, get the
* camera instance using the image mode passed */
if (!pcam_inst)
pcam_inst = msm_mctl_get_pcam_inst(pmctl, image_mode);
if (!pcam_inst || !pcam_inst->streamon) {
pr_err("%s: stream is turned off\n", __func__);
return rc;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
if (buf->state != MSM_BUFFER_STATE_QUEUED)
continue;
buf_idx = buf->vidbuf.v4l2_buf.index;
if (pcam_inst->vid_fmt.type ==
V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
free_buf->num_planes =
pcam_inst->plane_info.num_planes;
for (i = 0; i < free_buf->num_planes; i++) {
mem = vb2_plane_cookie(&buf->vidbuf, i);
if (mem->buffer_type ==
VIDEOBUF2_MULTIPLE_PLANES)
plane_offset =
mem->offset.data_offset;
else
plane_offset =
mem->offset.sp_off.cbcr_off;
free_buf->ch_paddr[i] = (uint32_t)
videobuf2_to_pmem_contig(&buf->vidbuf, i) +
pcam_inst->buf_offset[buf_idx][i].data_offset +
plane_offset;
}
} else {
mem = vb2_plane_cookie(&buf->vidbuf, 0);
free_buf->ch_paddr[0] = (uint32_t)
videobuf2_to_pmem_contig(&buf->vidbuf, 0) +
mem->offset.sp_off.y_off;
free_buf->ch_paddr[1] = free_buf->ch_paddr[0] +
mem->offset.sp_off.cbcr_off;
}
free_buf->vb = (uint32_t)buf;
buf->state = MSM_BUFFER_STATE_RESERVED;
D("%s inst=0x%p, idx=%d, paddr=0x%x, "
"ch1 addr=0x%x\n", __func__,
pcam_inst, buf->vidbuf.v4l2_buf.index,
free_buf->ch_paddr[0], free_buf->ch_paddr[1]);
rc = 0;
break;
}
if (rc != 0)
D("%s:No free buffer available: inst = 0x%p ",
__func__, pcam_inst);
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
return rc;
}
int msm_mctl_release_free_buf(struct msm_cam_media_controller *pmctl,
struct msm_cam_v4l2_dev_inst *pcam_inst,
int image_mode, struct msm_free_buf *free_buf)
{
unsigned long flags = 0;
struct msm_frame_buffer *buf = NULL;
uint32_t buf_phyaddr = 0;
int rc = -EINVAL;
if (!free_buf)
return rc;
if (!pcam_inst) {
pr_err("%s Invalid instance, buffer not released\n",
__func__);
return rc;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
buf_phyaddr =
(uint32_t) videobuf2_to_pmem_contig(&buf->vidbuf, 0);
if (free_buf->ch_paddr[0] == buf_phyaddr) {
D("%s buf = 0x%x ", __func__, free_buf->ch_paddr[0]);
buf->state = MSM_BUFFER_STATE_UNUSED;
rc = 0;
break;
}
}
if (rc != 0)
pr_err("%s invalid buffer address ", __func__);
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
return rc;
}
int msm_mctl_buf_done_pp(struct msm_cam_media_controller *pmctl,
int image_mode, struct msm_free_buf *frame, int dirty, int node_type)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
int rc = 0, idx;
idx = msm_mctl_img_mode_to_inst_index(pmctl, image_mode, node_type);
if (idx < 0) {
pr_err("%s Invalid instance, buffer not released\n", __func__);
return idx;
}
if (node_type)
pcam_inst = pmctl->sync.pcam_sync->mctl_node.dev_inst[idx];
else
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
if (!pcam_inst) {
pr_err("%s Invalid instance, cannot send buf to user",
__func__);
return -EINVAL;
}
D("%s:inst=0x%p, paddr=0x%x, dirty=%d",
__func__, pcam_inst, frame->ch_paddr[0], dirty);
if (dirty)
/* the frame is dirty, not going to disptach to app */
rc = msm_mctl_release_free_buf(pmctl, pcam_inst,
image_mode, frame);
else
rc = msm_mctl_buf_done_proc(pmctl, pcam_inst,
image_mode, frame, NULL, 0);
return rc;
}
struct msm_frame_buffer *msm_mctl_get_free_buf(
struct msm_cam_media_controller *pmctl,
int image_mode)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
unsigned long flags = 0;
struct msm_frame_buffer *buf = NULL;
int rc = -EINVAL, idx;
idx = msm_mctl_img_mode_to_inst_index(pmctl,
image_mode, 0);
if (idx < 0) {
pr_err("%s Invalid instance, cant get buffer\n", __func__);
return NULL;
}
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
if (!pcam_inst->streamon) {
D("%s: stream 0x%p is off\n", __func__, pcam_inst);
return NULL;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
if (!list_empty(&pcam_inst->free_vq)) {
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
if (buf->state == MSM_BUFFER_STATE_QUEUED) {
buf->state = MSM_BUFFER_STATE_RESERVED;
rc = 0;
break;
}
}
}
if (rc != 0) {
D("%s:No free buffer available: inst = 0x%p ",
__func__, pcam_inst);
buf = NULL;
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
return buf;
}
int msm_mctl_put_free_buf(
struct msm_cam_media_controller *pmctl,
int image_mode, struct msm_frame_buffer *my_buf)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
unsigned long flags = 0;
int rc = 0, idx;
struct msm_frame_buffer *buf = NULL;
idx = msm_mctl_img_mode_to_inst_index(pmctl,
image_mode, 0);
if (idx < 0) {
pr_err("%s Invalid instance, cant put buffer\n", __func__);
return idx;
}
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
if (!pcam_inst->streamon) {
D("%s: stream 0x%p is off\n", __func__, pcam_inst);
return rc;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
if (!list_empty(&pcam_inst->free_vq)) {
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
if (my_buf == buf) {
buf->state = MSM_BUFFER_STATE_QUEUED;
spin_unlock_irqrestore(&pcam_inst->vq_irqlock,
flags);
return 0;
}
}
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
return rc;
}
int msm_mctl_buf_del(struct msm_cam_media_controller *pmctl,
int image_mode,
struct msm_frame_buffer *my_buf)
{
struct msm_cam_v4l2_dev_inst *pcam_inst;
struct msm_frame_buffer *buf = NULL;
unsigned long flags = 0;
int idx;
idx = msm_mctl_img_mode_to_inst_index(pmctl,
image_mode, 0);
if (idx < 0) {
pr_err("%s Invalid instance, cant delete buffer\n", __func__);
return idx;
}
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
D("%s: idx = %d, pinst=0x%p", __func__, idx, pcam_inst);
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
if (!list_empty(&pcam_inst->free_vq)) {
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
if (my_buf == buf) {
list_del_init(&buf->list);
spin_unlock_irqrestore(&pcam_inst->vq_irqlock,
flags);
return 0;
}
}
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
pr_err("%s: buf 0x%p not found", __func__, my_buf);
return -EINVAL;
}
int msm_mctl_buf_return_buf(struct msm_cam_media_controller *pmctl,
int image_mode, struct msm_frame_buffer *rbuf)
{
int idx = 0;
struct msm_frame_buffer *buf = NULL;
struct msm_cam_v4l2_dev_inst *pcam_inst;
struct msm_cam_v4l2_device *pcam = pmctl->sync.pcam_sync;
unsigned long flags = 0;
if (pcam->mctl_node.dev_inst_map[image_mode]) {
idx = pcam->mctl_node.dev_inst_map[image_mode]->my_index;
pcam_inst = pcam->mctl_node.dev_inst[idx];
D("%s Found instance %p in mctl node device\n",
__func__, pcam_inst);
} else {
pr_err("%s Invalid image mode %d ", __func__, image_mode);
return -EINVAL;
}
if (!pcam_inst) {
pr_err("%s Invalid instance\n", __func__);
return -EINVAL;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
if (!list_empty(&pcam_inst->free_vq)) {
list_for_each_entry(buf, &pcam_inst->free_vq, list) {
if (rbuf == buf) {
D("%s Return buffer %x in pcam_inst %p ",
__func__, (int)rbuf, pcam_inst);
buf->state = MSM_BUFFER_STATE_QUEUED;
spin_unlock_irqrestore(&pcam_inst->vq_irqlock,
flags);
return 0;
}
}
}
spin_unlock_irqrestore(&pcam_inst->vq_irqlock, flags);
return -EINVAL;
}
| gpl-2.0 |
windxixi/android_kernel_htc_msm8660 | arch/x86/kernel/process_64.c | 340 | 15764 | /*
* Copyright (C) 1995 Linus Torvalds
*
* Pentium III FXSR, SSE support
* Gareth Hughes <gareth@valinux.com>, May 2000
*
* X86-64 port
* Andi Kleen.
*
* CPU hotplug support - ashok.raj@intel.com
*/
/*
* This file handles the architecture-dependent parts of process handling..
*/
#include <linux/stackprotector.h>
#include <linux/cpu.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/elfcore.h>
#include <linux/smp.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/ptrace.h>
#include <linux/notifier.h>
#include <linux/kprobes.h>
#include <linux/kdebug.h>
#include <linux/tick.h>
#include <linux/prctl.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/ftrace.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/i387.h>
#include <asm/mmu_context.h>
#include <asm/prctl.h>
#include <asm/desc.h>
#include <asm/proto.h>
#include <asm/ia32.h>
#include <asm/idle.h>
#include <asm/syscalls.h>
#include <asm/debugreg.h>
asmlinkage extern void ret_from_fork(void);
DEFINE_PER_CPU(unsigned long, old_rsp);
static DEFINE_PER_CPU(unsigned char, is_idle);
static ATOMIC_NOTIFIER_HEAD(idle_notifier);
void idle_notifier_register(struct notifier_block *n)
{
atomic_notifier_chain_register(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_register);
void idle_notifier_unregister(struct notifier_block *n)
{
atomic_notifier_chain_unregister(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_unregister);
void enter_idle(void)
{
percpu_write(is_idle, 1);
atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
}
static void __exit_idle(void)
{
if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
return;
atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
}
/* Called from interrupts to signify idle end */
void exit_idle(void)
{
/* idle loop has pid 0 */
if (current->pid)
return;
__exit_idle();
}
#ifndef CONFIG_SMP
static inline void play_dead(void)
{
BUG();
}
#endif
/*
* The idle thread. There's no useful work to be
* done, so just try to conserve power and have a
* low exit latency (ie sit in a loop waiting for
* somebody to say that they'd like to reschedule)
*/
void cpu_idle(void)
{
current_thread_info()->status |= TS_POLLING;
/*
* If we're the non-boot CPU, nothing set the stack canary up
* for us. CPU0 already has it initialized but no harm in
* doing it again. This is a good place for updating it, as
* we wont ever return from this function (so the invalid
* canaries already on the stack wont ever trigger).
*/
boot_init_stack_canary();
/* endless idle loop with no priority at all */
while (1) {
tick_nohz_stop_sched_tick(1);
while (!need_resched()) {
rmb();
if (cpu_is_offline(smp_processor_id()))
play_dead();
/*
* Idle routines should keep interrupts disabled
* from here on, until they go to idle.
* Otherwise, idle callbacks can misfire.
*/
local_irq_disable();
enter_idle();
/* Don't trace irqs off for idle */
stop_critical_timings();
pm_idle();
start_critical_timings();
/* In many cases the interrupt that ended idle
has already called exit_idle. But some idle
loops can be woken up without interrupt. */
__exit_idle();
}
tick_nohz_restart_sched_tick();
preempt_enable_no_resched();
schedule();
preempt_disable();
}
}
/* Prints also some state that isn't saved in the pt_regs */
void __show_regs(struct pt_regs *regs, int all)
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
unsigned long d0, d1, d2, d3, d6, d7;
unsigned int fsindex, gsindex;
unsigned int ds, cs, es;
show_regs_common();
printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
printk_address(regs->ip, 1);
printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss,
regs->sp, regs->flags);
printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
regs->ax, regs->bx, regs->cx);
printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
regs->dx, regs->si, regs->di);
printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
regs->bp, regs->r8, regs->r9);
printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
regs->r10, regs->r11, regs->r12);
printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
regs->r13, regs->r14, regs->r15);
asm("movl %%ds,%0" : "=r" (ds));
asm("movl %%cs,%0" : "=r" (cs));
asm("movl %%es,%0" : "=r" (es));
asm("movl %%fs,%0" : "=r" (fsindex));
asm("movl %%gs,%0" : "=r" (gsindex));
rdmsrl(MSR_FS_BASE, fs);
rdmsrl(MSR_GS_BASE, gs);
rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
if (!all)
return;
cr0 = read_cr0();
cr2 = read_cr2();
cr3 = read_cr3();
cr4 = read_cr4();
printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
fs, fsindex, gs, gsindex, shadowgs);
printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
es, cr0);
printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
cr4);
get_debugreg(d0, 0);
get_debugreg(d1, 1);
get_debugreg(d2, 2);
printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
get_debugreg(d3, 3);
get_debugreg(d6, 6);
get_debugreg(d7, 7);
printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
}
void release_thread(struct task_struct *dead_task)
{
if (dead_task->mm) {
if (dead_task->mm->context.size) {
printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",
dead_task->comm,
dead_task->mm->context.ldt,
dead_task->mm->context.size);
BUG();
}
}
}
static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
{
struct user_desc ud = {
.base_addr = addr,
.limit = 0xfffff,
.seg_32bit = 1,
.limit_in_pages = 1,
.useable = 1,
};
struct desc_struct *desc = t->thread.tls_array;
desc += tls;
fill_ldt(desc, &ud);
}
static inline u32 read_32bit_tls(struct task_struct *t, int tls)
{
return get_desc_base(&t->thread.tls_array[tls]);
}
/*
* This gets called before we allocate a new thread and copy
* the current task into it.
*/
void prepare_to_copy(struct task_struct *tsk)
{
unlazy_fpu(tsk);
}
int copy_thread(unsigned long clone_flags, unsigned long sp,
unsigned long unused,
struct task_struct *p, struct pt_regs *regs)
{
int err;
struct pt_regs *childregs;
struct task_struct *me = current;
childregs = ((struct pt_regs *)
(THREAD_SIZE + task_stack_page(p))) - 1;
*childregs = *regs;
childregs->ax = 0;
if (user_mode(regs))
childregs->sp = sp;
else
childregs->sp = (unsigned long)childregs;
p->thread.sp = (unsigned long) childregs;
p->thread.sp0 = (unsigned long) (childregs+1);
p->thread.usersp = me->thread.usersp;
set_tsk_thread_flag(p, TIF_FORK);
p->thread.io_bitmap_ptr = NULL;
savesegment(gs, p->thread.gsindex);
p->thread.gs = p->thread.gsindex ? 0 : me->thread.gs;
savesegment(fs, p->thread.fsindex);
p->thread.fs = p->thread.fsindex ? 0 : me->thread.fs;
savesegment(es, p->thread.es);
savesegment(ds, p->thread.ds);
err = -ENOMEM;
memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
if (!p->thread.io_bitmap_ptr) {
p->thread.io_bitmap_max = 0;
return -ENOMEM;
}
memcpy(p->thread.io_bitmap_ptr, me->thread.io_bitmap_ptr,
IO_BITMAP_BYTES);
set_tsk_thread_flag(p, TIF_IO_BITMAP);
}
/*
* Set a new TLS for the child thread?
*/
if (clone_flags & CLONE_SETTLS) {
#ifdef CONFIG_IA32_EMULATION
if (test_thread_flag(TIF_IA32))
err = do_set_thread_area(p, -1,
(struct user_desc __user *)childregs->si, 0);
else
#endif
err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8);
if (err)
goto out;
}
err = 0;
out:
if (err && p->thread.io_bitmap_ptr) {
kfree(p->thread.io_bitmap_ptr);
p->thread.io_bitmap_max = 0;
}
return err;
}
static void
start_thread_common(struct pt_regs *regs, unsigned long new_ip,
unsigned long new_sp,
unsigned int _cs, unsigned int _ss, unsigned int _ds)
{
loadsegment(fs, 0);
loadsegment(es, _ds);
loadsegment(ds, _ds);
load_gs_index(0);
regs->ip = new_ip;
regs->sp = new_sp;
percpu_write(old_rsp, new_sp);
regs->cs = _cs;
regs->ss = _ss;
regs->flags = X86_EFLAGS_IF;
/*
* Free the old FP and other extended state
*/
free_thread_xstate(current);
}
void
start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
{
start_thread_common(regs, new_ip, new_sp,
__USER_CS, __USER_DS, 0);
}
#ifdef CONFIG_IA32_EMULATION
void start_thread_ia32(struct pt_regs *regs, u32 new_ip, u32 new_sp)
{
start_thread_common(regs, new_ip, new_sp,
__USER32_CS, __USER32_DS, __USER32_DS);
}
#endif
/*
* switch_to(x,y) should switch tasks from x to y.
*
* This could still be optimized:
* - fold all the options into a flag word and test it with a single test.
* - could test fs/gs bitsliced
*
* Kprobes not supported here. Set the probe on schedule instead.
* Function graph tracer not supported too.
*/
__notrace_funcgraph struct task_struct *
__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
{
struct thread_struct *prev = &prev_p->thread;
struct thread_struct *next = &next_p->thread;
int cpu = smp_processor_id();
struct tss_struct *tss = &per_cpu(init_tss, cpu);
unsigned fsindex, gsindex;
fpu_switch_t fpu;
fpu = switch_fpu_prepare(prev_p, next_p);
/*
* Reload esp0, LDT and the page table pointer:
*/
load_sp0(tss, next);
/*
* Switch DS and ES.
* This won't pick up thread selector changes, but I guess that is ok.
*/
savesegment(es, prev->es);
if (unlikely(next->es | prev->es))
loadsegment(es, next->es);
savesegment(ds, prev->ds);
if (unlikely(next->ds | prev->ds))
loadsegment(ds, next->ds);
/* We must save %fs and %gs before load_TLS() because
* %fs and %gs may be cleared by load_TLS().
*
* (e.g. xen_load_tls())
*/
savesegment(fs, fsindex);
savesegment(gs, gsindex);
load_TLS(next, cpu);
/*
* Leave lazy mode, flushing any hypercalls made here.
* This must be done before restoring TLS segments so
* the GDT and LDT are properly updated, and must be
* done before math_state_restore, so the TS bit is up
* to date.
*/
arch_end_context_switch(next_p);
/*
* Switch FS and GS.
*
* Segment register != 0 always requires a reload. Also
* reload when it has changed. When prev process used 64bit
* base always reload to avoid an information leak.
*/
if (unlikely(fsindex | next->fsindex | prev->fs)) {
loadsegment(fs, next->fsindex);
/*
* Check if the user used a selector != 0; if yes
* clear 64bit base, since overloaded base is always
* mapped to the Null selector
*/
if (fsindex)
prev->fs = 0;
}
/* when next process has a 64bit base use it */
if (next->fs)
wrmsrl(MSR_FS_BASE, next->fs);
prev->fsindex = fsindex;
if (unlikely(gsindex | next->gsindex | prev->gs)) {
load_gs_index(next->gsindex);
if (gsindex)
prev->gs = 0;
}
if (next->gs)
wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
prev->gsindex = gsindex;
switch_fpu_finish(next_p, fpu);
/*
* Switch the PDA and FPU contexts.
*/
prev->usersp = percpu_read(old_rsp);
percpu_write(old_rsp, next->usersp);
percpu_write(current_task, next_p);
percpu_write(kernel_stack,
(unsigned long)task_stack_page(next_p) +
THREAD_SIZE - KERNEL_STACK_OFFSET);
/*
* Now maybe reload the debug registers and handle I/O bitmaps
*/
if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
__switch_to_xtra(prev_p, next_p, tss);
return prev_p;
}
void set_personality_64bit(void)
{
/* inherit personality from parent */
/* Make sure to be in 64bit mode */
clear_thread_flag(TIF_IA32);
/* Ensure the corresponding mm is not marked. */
if (current->mm)
current->mm->context.ia32_compat = 0;
/* TBD: overwrites user setup. Should have two bits.
But 64bit processes have always behaved this way,
so it's not too bad. The main problem is just that
32bit childs are affected again. */
current->personality &= ~READ_IMPLIES_EXEC;
}
void set_personality_ia32(void)
{
/* inherit personality from parent */
/* Make sure to be in 32bit mode */
set_thread_flag(TIF_IA32);
current->personality |= force_personality32;
/* Mark the associated mm as containing 32-bit tasks. */
if (current->mm)
current->mm->context.ia32_compat = 1;
/* Prepare the first "return" to user space */
current_thread_info()->status |= TS_COMPAT;
}
unsigned long get_wchan(struct task_struct *p)
{
unsigned long stack;
u64 fp, ip;
int count = 0;
if (!p || p == current || p->state == TASK_RUNNING)
return 0;
stack = (unsigned long)task_stack_page(p);
if (p->thread.sp < stack || p->thread.sp >= stack+THREAD_SIZE)
return 0;
fp = *(u64 *)(p->thread.sp);
do {
if (fp < (unsigned long)stack ||
fp >= (unsigned long)stack+THREAD_SIZE)
return 0;
ip = *(u64 *)(fp+8);
if (!in_sched_functions(ip))
return ip;
fp = *(u64 *)fp;
} while (count++ < 16);
return 0;
}
long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
{
int ret = 0;
int doit = task == current;
int cpu;
switch (code) {
case ARCH_SET_GS:
if (addr >= TASK_SIZE_OF(task))
return -EPERM;
cpu = get_cpu();
/* handle small bases via the GDT because that's faster to
switch. */
if (addr <= 0xffffffff) {
set_32bit_tls(task, GS_TLS, addr);
if (doit) {
load_TLS(&task->thread, cpu);
load_gs_index(GS_TLS_SEL);
}
task->thread.gsindex = GS_TLS_SEL;
task->thread.gs = 0;
} else {
task->thread.gsindex = 0;
task->thread.gs = addr;
if (doit) {
load_gs_index(0);
ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr);
}
}
put_cpu();
break;
case ARCH_SET_FS:
/* Not strictly needed for fs, but do it for symmetry
with gs */
if (addr >= TASK_SIZE_OF(task))
return -EPERM;
cpu = get_cpu();
/* handle small bases via the GDT because that's faster to
switch. */
if (addr <= 0xffffffff) {
set_32bit_tls(task, FS_TLS, addr);
if (doit) {
load_TLS(&task->thread, cpu);
loadsegment(fs, FS_TLS_SEL);
}
task->thread.fsindex = FS_TLS_SEL;
task->thread.fs = 0;
} else {
task->thread.fsindex = 0;
task->thread.fs = addr;
if (doit) {
/* set the selector to 0 to not confuse
__switch_to */
loadsegment(fs, 0);
ret = checking_wrmsrl(MSR_FS_BASE, addr);
}
}
put_cpu();
break;
case ARCH_GET_FS: {
unsigned long base;
if (task->thread.fsindex == FS_TLS_SEL)
base = read_32bit_tls(task, FS_TLS);
else if (doit)
rdmsrl(MSR_FS_BASE, base);
else
base = task->thread.fs;
ret = put_user(base, (unsigned long __user *)addr);
break;
}
case ARCH_GET_GS: {
unsigned long base;
unsigned gsindex;
if (task->thread.gsindex == GS_TLS_SEL)
base = read_32bit_tls(task, GS_TLS);
else if (doit) {
savesegment(gs, gsindex);
if (gsindex)
rdmsrl(MSR_KERNEL_GS_BASE, base);
else
base = task->thread.gs;
} else
base = task->thread.gs;
ret = put_user(base, (unsigned long __user *)addr);
break;
}
default:
ret = -EINVAL;
break;
}
return ret;
}
long sys_arch_prctl(int code, unsigned long addr)
{
return do_arch_prctl(current, code, addr);
}
unsigned long KSTK_ESP(struct task_struct *task)
{
return (test_tsk_thread_flag(task, TIF_IA32)) ?
(task_pt_regs(task)->sp) : ((task)->thread.usersp);
}
| gpl-2.0 |
Fevax/exynos8890_stock | drivers/iio/pressure/st_pressure_buffer.c | 852 | 2360 | /*
* STMicroelectronics pressures driver
*
* Copyright 2013 STMicroelectronics Inc.
*
* Denis Ciocca <denis.ciocca@st.com>
*
* Licensed under the GPL-2.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/stat.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/common/st_sensors.h>
#include "st_pressure.h"
int st_press_trig_set_state(struct iio_trigger *trig, bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
return st_sensors_set_dataready_irq(indio_dev, state);
}
static int st_press_buffer_preenable(struct iio_dev *indio_dev)
{
return st_sensors_set_enable(indio_dev, true);
}
static int st_press_buffer_postenable(struct iio_dev *indio_dev)
{
int err;
struct st_sensor_data *pdata = iio_priv(indio_dev);
pdata->buffer_data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
if (pdata->buffer_data == NULL) {
err = -ENOMEM;
goto allocate_memory_error;
}
err = iio_triggered_buffer_postenable(indio_dev);
if (err < 0)
goto st_press_buffer_postenable_error;
return err;
st_press_buffer_postenable_error:
kfree(pdata->buffer_data);
allocate_memory_error:
return err;
}
static int st_press_buffer_predisable(struct iio_dev *indio_dev)
{
int err;
struct st_sensor_data *pdata = iio_priv(indio_dev);
err = iio_triggered_buffer_predisable(indio_dev);
if (err < 0)
goto st_press_buffer_predisable_error;
err = st_sensors_set_enable(indio_dev, false);
st_press_buffer_predisable_error:
kfree(pdata->buffer_data);
return err;
}
static const struct iio_buffer_setup_ops st_press_buffer_setup_ops = {
.preenable = &st_press_buffer_preenable,
.postenable = &st_press_buffer_postenable,
.predisable = &st_press_buffer_predisable,
};
int st_press_allocate_ring(struct iio_dev *indio_dev)
{
return iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
&st_sensors_trigger_handler, &st_press_buffer_setup_ops);
}
void st_press_deallocate_ring(struct iio_dev *indio_dev)
{
iio_triggered_buffer_cleanup(indio_dev);
}
MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>");
MODULE_DESCRIPTION("STMicroelectronics pressures buffer");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
mparus/android_kernel_huawei_msm8916-caf | kernel/trace/trace_kprobe.c | 1876 | 37239 | /*
* Kprobes-based tracing events
*
* Created by Masami Hiramatsu <mhiramat@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/uaccess.h>
#include "trace_probe.h"
#define KPROBE_EVENT_SYSTEM "kprobes"
/**
* Kprobe event core functions
*/
struct trace_probe {
struct list_head list;
struct kretprobe rp; /* Use rp.kp for kprobe use */
unsigned long nhit;
unsigned int flags; /* For TP_FLAG_* */
const char *symbol; /* symbol name */
struct ftrace_event_class class;
struct ftrace_event_call call;
struct ftrace_event_file * __rcu *files;
ssize_t size; /* trace entry size */
unsigned int nr_args;
struct probe_arg args[];
};
#define SIZEOF_TRACE_PROBE(n) \
(offsetof(struct trace_probe, args) + \
(sizeof(struct probe_arg) * (n)))
static __kprobes bool trace_probe_is_return(struct trace_probe *tp)
{
return tp->rp.handler != NULL;
}
static __kprobes const char *trace_probe_symbol(struct trace_probe *tp)
{
return tp->symbol ? tp->symbol : "unknown";
}
static __kprobes unsigned long trace_probe_offset(struct trace_probe *tp)
{
return tp->rp.kp.offset;
}
static __kprobes bool trace_probe_is_enabled(struct trace_probe *tp)
{
return !!(tp->flags & (TP_FLAG_TRACE | TP_FLAG_PROFILE));
}
static __kprobes bool trace_probe_is_registered(struct trace_probe *tp)
{
return !!(tp->flags & TP_FLAG_REGISTERED);
}
static __kprobes bool trace_probe_has_gone(struct trace_probe *tp)
{
return !!(kprobe_gone(&tp->rp.kp));
}
static __kprobes bool trace_probe_within_module(struct trace_probe *tp,
struct module *mod)
{
int len = strlen(mod->name);
const char *name = trace_probe_symbol(tp);
return strncmp(mod->name, name, len) == 0 && name[len] == ':';
}
static __kprobes bool trace_probe_is_on_module(struct trace_probe *tp)
{
return !!strchr(trace_probe_symbol(tp), ':');
}
static int register_probe_event(struct trace_probe *tp);
static int unregister_probe_event(struct trace_probe *tp);
static DEFINE_MUTEX(probe_lock);
static LIST_HEAD(probe_list);
static int kprobe_dispatcher(struct kprobe *kp, struct pt_regs *regs);
static int kretprobe_dispatcher(struct kretprobe_instance *ri,
struct pt_regs *regs);
/*
* Allocate new trace_probe and initialize it (including kprobes).
*/
static struct trace_probe *alloc_trace_probe(const char *group,
const char *event,
void *addr,
const char *symbol,
unsigned long offs,
int nargs, bool is_return)
{
struct trace_probe *tp;
int ret = -ENOMEM;
tp = kzalloc(SIZEOF_TRACE_PROBE(nargs), GFP_KERNEL);
if (!tp)
return ERR_PTR(ret);
if (symbol) {
tp->symbol = kstrdup(symbol, GFP_KERNEL);
if (!tp->symbol)
goto error;
tp->rp.kp.symbol_name = tp->symbol;
tp->rp.kp.offset = offs;
} else
tp->rp.kp.addr = addr;
if (is_return)
tp->rp.handler = kretprobe_dispatcher;
else
tp->rp.kp.pre_handler = kprobe_dispatcher;
if (!event || !is_good_name(event)) {
ret = -EINVAL;
goto error;
}
tp->call.class = &tp->class;
tp->call.name = kstrdup(event, GFP_KERNEL);
if (!tp->call.name)
goto error;
if (!group || !is_good_name(group)) {
ret = -EINVAL;
goto error;
}
tp->class.system = kstrdup(group, GFP_KERNEL);
if (!tp->class.system)
goto error;
INIT_LIST_HEAD(&tp->list);
return tp;
error:
kfree(tp->call.name);
kfree(tp->symbol);
kfree(tp);
return ERR_PTR(ret);
}
static void free_trace_probe(struct trace_probe *tp)
{
int i;
for (i = 0; i < tp->nr_args; i++)
traceprobe_free_probe_arg(&tp->args[i]);
kfree(tp->call.class->system);
kfree(tp->call.name);
kfree(tp->symbol);
kfree(tp);
}
static struct trace_probe *find_trace_probe(const char *event,
const char *group)
{
struct trace_probe *tp;
list_for_each_entry(tp, &probe_list, list)
if (strcmp(tp->call.name, event) == 0 &&
strcmp(tp->call.class->system, group) == 0)
return tp;
return NULL;
}
static int trace_probe_nr_files(struct trace_probe *tp)
{
struct ftrace_event_file **file;
int ret = 0;
/*
* Since all tp->files updater is protected by probe_enable_lock,
* we don't need to lock an rcu_read_lock.
*/
file = rcu_dereference_raw(tp->files);
if (file)
while (*(file++))
ret++;
return ret;
}
static DEFINE_MUTEX(probe_enable_lock);
/*
* Enable trace_probe
* if the file is NULL, enable "perf" handler, or enable "trace" handler.
*/
static int
enable_trace_probe(struct trace_probe *tp, struct ftrace_event_file *file)
{
int ret = 0;
mutex_lock(&probe_enable_lock);
if (file) {
struct ftrace_event_file **new, **old;
int n = trace_probe_nr_files(tp);
old = rcu_dereference_raw(tp->files);
/* 1 is for new one and 1 is for stopper */
new = kzalloc((n + 2) * sizeof(struct ftrace_event_file *),
GFP_KERNEL);
if (!new) {
ret = -ENOMEM;
goto out_unlock;
}
memcpy(new, old, n * sizeof(struct ftrace_event_file *));
new[n] = file;
/* The last one keeps a NULL */
rcu_assign_pointer(tp->files, new);
tp->flags |= TP_FLAG_TRACE;
if (old) {
/* Make sure the probe is done with old files */
synchronize_sched();
kfree(old);
}
} else
tp->flags |= TP_FLAG_PROFILE;
if (trace_probe_is_enabled(tp) && trace_probe_is_registered(tp) &&
!trace_probe_has_gone(tp)) {
if (trace_probe_is_return(tp))
ret = enable_kretprobe(&tp->rp);
else
ret = enable_kprobe(&tp->rp.kp);
}
out_unlock:
mutex_unlock(&probe_enable_lock);
return ret;
}
static int
trace_probe_file_index(struct trace_probe *tp, struct ftrace_event_file *file)
{
struct ftrace_event_file **files;
int i;
/*
* Since all tp->files updater is protected by probe_enable_lock,
* we don't need to lock an rcu_read_lock.
*/
files = rcu_dereference_raw(tp->files);
if (files) {
for (i = 0; files[i]; i++)
if (files[i] == file)
return i;
}
return -1;
}
/*
* Disable trace_probe
* if the file is NULL, disable "perf" handler, or disable "trace" handler.
*/
static int
disable_trace_probe(struct trace_probe *tp, struct ftrace_event_file *file)
{
struct ftrace_event_file **old = NULL;
int wait = 0;
int ret = 0;
mutex_lock(&probe_enable_lock);
if (file) {
struct ftrace_event_file **new, **old;
int n = trace_probe_nr_files(tp);
int i, j;
old = rcu_dereference_raw(tp->files);
if (n == 0 || trace_probe_file_index(tp, file) < 0) {
ret = -EINVAL;
goto out_unlock;
}
if (n == 1) { /* Remove the last file */
tp->flags &= ~TP_FLAG_TRACE;
new = NULL;
} else {
new = kzalloc(n * sizeof(struct ftrace_event_file *),
GFP_KERNEL);
if (!new) {
ret = -ENOMEM;
goto out_unlock;
}
/* This copy & check loop copies the NULL stopper too */
for (i = 0, j = 0; j < n && i < n + 1; i++)
if (old[i] != file)
new[j++] = old[i];
}
rcu_assign_pointer(tp->files, new);
wait = 1;
} else
tp->flags &= ~TP_FLAG_PROFILE;
if (!trace_probe_is_enabled(tp) && trace_probe_is_registered(tp)) {
if (trace_probe_is_return(tp))
disable_kretprobe(&tp->rp);
else
disable_kprobe(&tp->rp.kp);
wait = 1;
}
out_unlock:
mutex_unlock(&probe_enable_lock);
if (wait) {
/*
* Synchronize with kprobe_trace_func/kretprobe_trace_func
* to ensure disabled (all running handlers are finished).
* This is not only for kfree(), but also the caller,
* trace_remove_event_call() supposes it for releasing
* event_call related objects, which will be accessed in
* the kprobe_trace_func/kretprobe_trace_func.
*/
synchronize_sched();
kfree(old); /* Ignored if link == NULL */
}
return ret;
}
/* Internal register function - just handle k*probes and flags */
static int __register_trace_probe(struct trace_probe *tp)
{
int i, ret;
if (trace_probe_is_registered(tp))
return -EINVAL;
for (i = 0; i < tp->nr_args; i++)
traceprobe_update_arg(&tp->args[i]);
/* Set/clear disabled flag according to tp->flag */
if (trace_probe_is_enabled(tp))
tp->rp.kp.flags &= ~KPROBE_FLAG_DISABLED;
else
tp->rp.kp.flags |= KPROBE_FLAG_DISABLED;
if (trace_probe_is_return(tp))
ret = register_kretprobe(&tp->rp);
else
ret = register_kprobe(&tp->rp.kp);
if (ret == 0)
tp->flags |= TP_FLAG_REGISTERED;
else {
pr_warning("Could not insert probe at %s+%lu: %d\n",
trace_probe_symbol(tp), trace_probe_offset(tp), ret);
if (ret == -ENOENT && trace_probe_is_on_module(tp)) {
pr_warning("This probe might be able to register after"
"target module is loaded. Continue.\n");
ret = 0;
} else if (ret == -EILSEQ) {
pr_warning("Probing address(0x%p) is not an "
"instruction boundary.\n",
tp->rp.kp.addr);
ret = -EINVAL;
}
}
return ret;
}
/* Internal unregister function - just handle k*probes and flags */
static void __unregister_trace_probe(struct trace_probe *tp)
{
if (trace_probe_is_registered(tp)) {
if (trace_probe_is_return(tp))
unregister_kretprobe(&tp->rp);
else
unregister_kprobe(&tp->rp.kp);
tp->flags &= ~TP_FLAG_REGISTERED;
/* Cleanup kprobe for reuse */
if (tp->rp.kp.symbol_name)
tp->rp.kp.addr = NULL;
}
}
/* Unregister a trace_probe and probe_event: call with locking probe_lock */
static int unregister_trace_probe(struct trace_probe *tp)
{
/* Enabled event can not be unregistered */
if (trace_probe_is_enabled(tp))
return -EBUSY;
/* Will fail if probe is being used by ftrace or perf */
if (unregister_probe_event(tp))
return -EBUSY;
__unregister_trace_probe(tp);
list_del(&tp->list);
return 0;
}
/* Register a trace_probe and probe_event */
static int register_trace_probe(struct trace_probe *tp)
{
struct trace_probe *old_tp;
int ret;
mutex_lock(&probe_lock);
/* Delete old (same name) event if exist */
old_tp = find_trace_probe(tp->call.name, tp->call.class->system);
if (old_tp) {
ret = unregister_trace_probe(old_tp);
if (ret < 0)
goto end;
free_trace_probe(old_tp);
}
/* Register new event */
ret = register_probe_event(tp);
if (ret) {
pr_warning("Failed to register probe event(%d)\n", ret);
goto end;
}
/* Register k*probe */
ret = __register_trace_probe(tp);
if (ret < 0)
unregister_probe_event(tp);
else
list_add_tail(&tp->list, &probe_list);
end:
mutex_unlock(&probe_lock);
return ret;
}
/* Module notifier call back, checking event on the module */
static int trace_probe_module_callback(struct notifier_block *nb,
unsigned long val, void *data)
{
struct module *mod = data;
struct trace_probe *tp;
int ret;
if (val != MODULE_STATE_COMING)
return NOTIFY_DONE;
/* Update probes on coming module */
mutex_lock(&probe_lock);
list_for_each_entry(tp, &probe_list, list) {
if (trace_probe_within_module(tp, mod)) {
/* Don't need to check busy - this should have gone. */
__unregister_trace_probe(tp);
ret = __register_trace_probe(tp);
if (ret)
pr_warning("Failed to re-register probe %s on"
"%s: %d\n",
tp->call.name, mod->name, ret);
}
}
mutex_unlock(&probe_lock);
return NOTIFY_DONE;
}
static struct notifier_block trace_probe_module_nb = {
.notifier_call = trace_probe_module_callback,
.priority = 1 /* Invoked after kprobe module callback */
};
static int create_trace_probe(int argc, char **argv)
{
/*
* Argument syntax:
* - Add kprobe: p[:[GRP/]EVENT] [MOD:]KSYM[+OFFS]|KADDR [FETCHARGS]
* - Add kretprobe: r[:[GRP/]EVENT] [MOD:]KSYM[+0] [FETCHARGS]
* Fetch args:
* $retval : fetch return value
* $stack : fetch stack address
* $stackN : fetch Nth of stack (N:0-)
* @ADDR : fetch memory at ADDR (ADDR should be in kernel)
* @SYM[+|-offs] : fetch memory at SYM +|- offs (SYM is a data symbol)
* %REG : fetch register REG
* Dereferencing memory fetch:
* +|-offs(ARG) : fetch memory at ARG +|- offs address.
* Alias name of args:
* NAME=FETCHARG : set NAME as alias of FETCHARG.
* Type of args:
* FETCHARG:TYPE : use TYPE instead of unsigned long.
*/
struct trace_probe *tp;
int i, ret = 0;
bool is_return = false, is_delete = false;
char *symbol = NULL, *event = NULL, *group = NULL;
char *arg;
unsigned long offset = 0;
void *addr = NULL;
char buf[MAX_EVENT_NAME_LEN];
/* argc must be >= 1 */
if (argv[0][0] == 'p')
is_return = false;
else if (argv[0][0] == 'r')
is_return = true;
else if (argv[0][0] == '-')
is_delete = true;
else {
pr_info("Probe definition must be started with 'p', 'r' or"
" '-'.\n");
return -EINVAL;
}
if (argv[0][1] == ':') {
event = &argv[0][2];
if (strchr(event, '/')) {
group = event;
event = strchr(group, '/') + 1;
event[-1] = '\0';
if (strlen(group) == 0) {
pr_info("Group name is not specified\n");
return -EINVAL;
}
}
if (strlen(event) == 0) {
pr_info("Event name is not specified\n");
return -EINVAL;
}
}
if (!group)
group = KPROBE_EVENT_SYSTEM;
if (is_delete) {
if (!event) {
pr_info("Delete command needs an event name.\n");
return -EINVAL;
}
mutex_lock(&probe_lock);
tp = find_trace_probe(event, group);
if (!tp) {
mutex_unlock(&probe_lock);
pr_info("Event %s/%s doesn't exist.\n", group, event);
return -ENOENT;
}
/* delete an event */
ret = unregister_trace_probe(tp);
if (ret == 0)
free_trace_probe(tp);
mutex_unlock(&probe_lock);
return ret;
}
if (argc < 2) {
pr_info("Probe point is not specified.\n");
return -EINVAL;
}
if (isdigit(argv[1][0])) {
if (is_return) {
pr_info("Return probe point must be a symbol.\n");
return -EINVAL;
}
/* an address specified */
ret = kstrtoul(&argv[1][0], 0, (unsigned long *)&addr);
if (ret) {
pr_info("Failed to parse address.\n");
return ret;
}
} else {
/* a symbol specified */
symbol = argv[1];
/* TODO: support .init module functions */
ret = traceprobe_split_symbol_offset(symbol, &offset);
if (ret) {
pr_info("Failed to parse symbol.\n");
return ret;
}
if (offset && is_return) {
pr_info("Return probe must be used without offset.\n");
return -EINVAL;
}
}
argc -= 2; argv += 2;
/* setup a probe */
if (!event) {
/* Make a new event name */
if (symbol)
snprintf(buf, MAX_EVENT_NAME_LEN, "%c_%s_%ld",
is_return ? 'r' : 'p', symbol, offset);
else
snprintf(buf, MAX_EVENT_NAME_LEN, "%c_0x%p",
is_return ? 'r' : 'p', addr);
event = buf;
}
tp = alloc_trace_probe(group, event, addr, symbol, offset, argc,
is_return);
if (IS_ERR(tp)) {
pr_info("Failed to allocate trace_probe.(%d)\n",
(int)PTR_ERR(tp));
return PTR_ERR(tp);
}
/* parse arguments */
ret = 0;
for (i = 0; i < argc && i < MAX_TRACE_ARGS; i++) {
/* Increment count for freeing args in error case */
tp->nr_args++;
/* Parse argument name */
arg = strchr(argv[i], '=');
if (arg) {
*arg++ = '\0';
tp->args[i].name = kstrdup(argv[i], GFP_KERNEL);
} else {
arg = argv[i];
/* If argument name is omitted, set "argN" */
snprintf(buf, MAX_EVENT_NAME_LEN, "arg%d", i + 1);
tp->args[i].name = kstrdup(buf, GFP_KERNEL);
}
if (!tp->args[i].name) {
pr_info("Failed to allocate argument[%d] name.\n", i);
ret = -ENOMEM;
goto error;
}
if (!is_good_name(tp->args[i].name)) {
pr_info("Invalid argument[%d] name: %s\n",
i, tp->args[i].name);
ret = -EINVAL;
goto error;
}
if (traceprobe_conflict_field_name(tp->args[i].name,
tp->args, i)) {
pr_info("Argument[%d] name '%s' conflicts with "
"another field.\n", i, argv[i]);
ret = -EINVAL;
goto error;
}
/* Parse fetch argument */
ret = traceprobe_parse_probe_arg(arg, &tp->size, &tp->args[i],
is_return, true);
if (ret) {
pr_info("Parse error at argument[%d]. (%d)\n", i, ret);
goto error;
}
}
ret = register_trace_probe(tp);
if (ret)
goto error;
return 0;
error:
free_trace_probe(tp);
return ret;
}
static int release_all_trace_probes(void)
{
struct trace_probe *tp;
int ret = 0;
mutex_lock(&probe_lock);
/* Ensure no probe is in use. */
list_for_each_entry(tp, &probe_list, list)
if (trace_probe_is_enabled(tp)) {
ret = -EBUSY;
goto end;
}
/* TODO: Use batch unregistration */
while (!list_empty(&probe_list)) {
tp = list_entry(probe_list.next, struct trace_probe, list);
ret = unregister_trace_probe(tp);
if (ret)
goto end;
free_trace_probe(tp);
}
end:
mutex_unlock(&probe_lock);
return ret;
}
/* Probes listing interfaces */
static void *probes_seq_start(struct seq_file *m, loff_t *pos)
{
mutex_lock(&probe_lock);
return seq_list_start(&probe_list, *pos);
}
static void *probes_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
return seq_list_next(v, &probe_list, pos);
}
static void probes_seq_stop(struct seq_file *m, void *v)
{
mutex_unlock(&probe_lock);
}
static int probes_seq_show(struct seq_file *m, void *v)
{
struct trace_probe *tp = v;
int i;
seq_printf(m, "%c", trace_probe_is_return(tp) ? 'r' : 'p');
seq_printf(m, ":%s/%s", tp->call.class->system, tp->call.name);
if (!tp->symbol)
seq_printf(m, " 0x%p", tp->rp.kp.addr);
else if (tp->rp.kp.offset)
seq_printf(m, " %s+%u", trace_probe_symbol(tp),
tp->rp.kp.offset);
else
seq_printf(m, " %s", trace_probe_symbol(tp));
for (i = 0; i < tp->nr_args; i++)
seq_printf(m, " %s=%s", tp->args[i].name, tp->args[i].comm);
seq_printf(m, "\n");
return 0;
}
static const struct seq_operations probes_seq_op = {
.start = probes_seq_start,
.next = probes_seq_next,
.stop = probes_seq_stop,
.show = probes_seq_show
};
static int probes_open(struct inode *inode, struct file *file)
{
int ret;
if ((file->f_mode & FMODE_WRITE) && (file->f_flags & O_TRUNC)) {
ret = release_all_trace_probes();
if (ret < 0)
return ret;
}
return seq_open(file, &probes_seq_op);
}
static ssize_t probes_write(struct file *file, const char __user *buffer,
size_t count, loff_t *ppos)
{
return traceprobe_probes_write(file, buffer, count, ppos,
create_trace_probe);
}
static const struct file_operations kprobe_events_ops = {
.owner = THIS_MODULE,
.open = probes_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
.write = probes_write,
};
/* Probes profiling interfaces */
static int probes_profile_seq_show(struct seq_file *m, void *v)
{
struct trace_probe *tp = v;
seq_printf(m, " %-44s %15lu %15lu\n", tp->call.name, tp->nhit,
tp->rp.kp.nmissed);
return 0;
}
static const struct seq_operations profile_seq_op = {
.start = probes_seq_start,
.next = probes_seq_next,
.stop = probes_seq_stop,
.show = probes_profile_seq_show
};
static int profile_open(struct inode *inode, struct file *file)
{
return seq_open(file, &profile_seq_op);
}
static const struct file_operations kprobe_profile_ops = {
.owner = THIS_MODULE,
.open = profile_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
/* Sum up total data length for dynamic arraies (strings) */
static __kprobes int __get_data_size(struct trace_probe *tp,
struct pt_regs *regs)
{
int i, ret = 0;
u32 len;
for (i = 0; i < tp->nr_args; i++)
if (unlikely(tp->args[i].fetch_size.fn)) {
call_fetch(&tp->args[i].fetch_size, regs, &len);
ret += len;
}
return ret;
}
/* Store the value of each argument */
static __kprobes void store_trace_args(int ent_size, struct trace_probe *tp,
struct pt_regs *regs,
u8 *data, int maxlen)
{
int i;
u32 end = tp->size;
u32 *dl; /* Data (relative) location */
for (i = 0; i < tp->nr_args; i++) {
if (unlikely(tp->args[i].fetch_size.fn)) {
/*
* First, we set the relative location and
* maximum data length to *dl
*/
dl = (u32 *)(data + tp->args[i].offset);
*dl = make_data_rloc(maxlen, end - tp->args[i].offset);
/* Then try to fetch string or dynamic array data */
call_fetch(&tp->args[i].fetch, regs, dl);
/* Reduce maximum length */
end += get_rloc_len(*dl);
maxlen -= get_rloc_len(*dl);
/* Trick here, convert data_rloc to data_loc */
*dl = convert_rloc_to_loc(*dl,
ent_size + tp->args[i].offset);
} else
/* Just fetching data normally */
call_fetch(&tp->args[i].fetch, regs,
data + tp->args[i].offset);
}
}
/* Kprobe handler */
static __kprobes void
__kprobe_trace_func(struct trace_probe *tp, struct pt_regs *regs,
struct ftrace_event_file *ftrace_file)
{
struct kprobe_trace_entry_head *entry;
struct ring_buffer_event *event;
struct ring_buffer *buffer;
int size, dsize, pc;
unsigned long irq_flags;
struct ftrace_event_call *call = &tp->call;
WARN_ON(call != ftrace_file->event_call);
if (test_bit(FTRACE_EVENT_FL_SOFT_DISABLED_BIT, &ftrace_file->flags))
return;
local_save_flags(irq_flags);
pc = preempt_count();
dsize = __get_data_size(tp, regs);
size = sizeof(*entry) + tp->size + dsize;
event = trace_event_buffer_lock_reserve(&buffer, ftrace_file,
call->event.type,
size, irq_flags, pc);
if (!event)
return;
entry = ring_buffer_event_data(event);
entry->ip = (unsigned long)tp->rp.kp.addr;
store_trace_args(sizeof(*entry), tp, regs, (u8 *)&entry[1], dsize);
if (!filter_current_check_discard(buffer, call, entry, event))
trace_buffer_unlock_commit_regs(buffer, event,
irq_flags, pc, regs);
}
static __kprobes void
kprobe_trace_func(struct trace_probe *tp, struct pt_regs *regs)
{
/*
* Note: preempt is already disabled around the kprobe handler.
* However, we still need an smp_read_barrier_depends() corresponding
* to smp_wmb() in rcu_assign_pointer() to access the pointer.
*/
struct ftrace_event_file **file = rcu_dereference_raw(tp->files);
if (unlikely(!file))
return;
while (*file) {
__kprobe_trace_func(tp, regs, *file);
file++;
}
}
/* Kretprobe handler */
static __kprobes void
__kretprobe_trace_func(struct trace_probe *tp, struct kretprobe_instance *ri,
struct pt_regs *regs,
struct ftrace_event_file *ftrace_file)
{
struct kretprobe_trace_entry_head *entry;
struct ring_buffer_event *event;
struct ring_buffer *buffer;
int size, pc, dsize;
unsigned long irq_flags;
struct ftrace_event_call *call = &tp->call;
WARN_ON(call != ftrace_file->event_call);
if (test_bit(FTRACE_EVENT_FL_SOFT_DISABLED_BIT, &ftrace_file->flags))
return;
local_save_flags(irq_flags);
pc = preempt_count();
dsize = __get_data_size(tp, regs);
size = sizeof(*entry) + tp->size + dsize;
event = trace_event_buffer_lock_reserve(&buffer, ftrace_file,
call->event.type,
size, irq_flags, pc);
if (!event)
return;
entry = ring_buffer_event_data(event);
entry->func = (unsigned long)tp->rp.kp.addr;
entry->ret_ip = (unsigned long)ri->ret_addr;
store_trace_args(sizeof(*entry), tp, regs, (u8 *)&entry[1], dsize);
if (!filter_current_check_discard(buffer, call, entry, event))
trace_buffer_unlock_commit_regs(buffer, event,
irq_flags, pc, regs);
}
static __kprobes void
kretprobe_trace_func(struct trace_probe *tp, struct kretprobe_instance *ri,
struct pt_regs *regs)
{
/*
* Note: preempt is already disabled around the kprobe handler.
* However, we still need an smp_read_barrier_depends() corresponding
* to smp_wmb() in rcu_assign_pointer() to access the pointer.
*/
struct ftrace_event_file **file = rcu_dereference_raw(tp->files);
if (unlikely(!file))
return;
while (*file) {
__kretprobe_trace_func(tp, ri, regs, *file);
file++;
}
}
/* Event entry printers */
static enum print_line_t
print_kprobe_event(struct trace_iterator *iter, int flags,
struct trace_event *event)
{
struct kprobe_trace_entry_head *field;
struct trace_seq *s = &iter->seq;
struct trace_probe *tp;
u8 *data;
int i;
field = (struct kprobe_trace_entry_head *)iter->ent;
tp = container_of(event, struct trace_probe, call.event);
if (!trace_seq_printf(s, "%s: (", tp->call.name))
goto partial;
if (!seq_print_ip_sym(s, field->ip, flags | TRACE_ITER_SYM_OFFSET))
goto partial;
if (!trace_seq_puts(s, ")"))
goto partial;
data = (u8 *)&field[1];
for (i = 0; i < tp->nr_args; i++)
if (!tp->args[i].type->print(s, tp->args[i].name,
data + tp->args[i].offset, field))
goto partial;
if (!trace_seq_puts(s, "\n"))
goto partial;
return TRACE_TYPE_HANDLED;
partial:
return TRACE_TYPE_PARTIAL_LINE;
}
static enum print_line_t
print_kretprobe_event(struct trace_iterator *iter, int flags,
struct trace_event *event)
{
struct kretprobe_trace_entry_head *field;
struct trace_seq *s = &iter->seq;
struct trace_probe *tp;
u8 *data;
int i;
field = (struct kretprobe_trace_entry_head *)iter->ent;
tp = container_of(event, struct trace_probe, call.event);
if (!trace_seq_printf(s, "%s: (", tp->call.name))
goto partial;
if (!seq_print_ip_sym(s, field->ret_ip, flags | TRACE_ITER_SYM_OFFSET))
goto partial;
if (!trace_seq_puts(s, " <- "))
goto partial;
if (!seq_print_ip_sym(s, field->func, flags & ~TRACE_ITER_SYM_OFFSET))
goto partial;
if (!trace_seq_puts(s, ")"))
goto partial;
data = (u8 *)&field[1];
for (i = 0; i < tp->nr_args; i++)
if (!tp->args[i].type->print(s, tp->args[i].name,
data + tp->args[i].offset, field))
goto partial;
if (!trace_seq_puts(s, "\n"))
goto partial;
return TRACE_TYPE_HANDLED;
partial:
return TRACE_TYPE_PARTIAL_LINE;
}
static int kprobe_event_define_fields(struct ftrace_event_call *event_call)
{
int ret, i;
struct kprobe_trace_entry_head field;
struct trace_probe *tp = (struct trace_probe *)event_call->data;
DEFINE_FIELD(unsigned long, ip, FIELD_STRING_IP, 0);
/* Set argument names as fields */
for (i = 0; i < tp->nr_args; i++) {
ret = trace_define_field(event_call, tp->args[i].type->fmttype,
tp->args[i].name,
sizeof(field) + tp->args[i].offset,
tp->args[i].type->size,
tp->args[i].type->is_signed,
FILTER_OTHER);
if (ret)
return ret;
}
return 0;
}
static int kretprobe_event_define_fields(struct ftrace_event_call *event_call)
{
int ret, i;
struct kretprobe_trace_entry_head field;
struct trace_probe *tp = (struct trace_probe *)event_call->data;
DEFINE_FIELD(unsigned long, func, FIELD_STRING_FUNC, 0);
DEFINE_FIELD(unsigned long, ret_ip, FIELD_STRING_RETIP, 0);
/* Set argument names as fields */
for (i = 0; i < tp->nr_args; i++) {
ret = trace_define_field(event_call, tp->args[i].type->fmttype,
tp->args[i].name,
sizeof(field) + tp->args[i].offset,
tp->args[i].type->size,
tp->args[i].type->is_signed,
FILTER_OTHER);
if (ret)
return ret;
}
return 0;
}
static int __set_print_fmt(struct trace_probe *tp, char *buf, int len)
{
int i;
int pos = 0;
const char *fmt, *arg;
if (!trace_probe_is_return(tp)) {
fmt = "(%lx)";
arg = "REC->" FIELD_STRING_IP;
} else {
fmt = "(%lx <- %lx)";
arg = "REC->" FIELD_STRING_FUNC ", REC->" FIELD_STRING_RETIP;
}
/* When len=0, we just calculate the needed length */
#define LEN_OR_ZERO (len ? len - pos : 0)
pos += snprintf(buf + pos, LEN_OR_ZERO, "\"%s", fmt);
for (i = 0; i < tp->nr_args; i++) {
pos += snprintf(buf + pos, LEN_OR_ZERO, " %s=%s",
tp->args[i].name, tp->args[i].type->fmt);
}
pos += snprintf(buf + pos, LEN_OR_ZERO, "\", %s", arg);
for (i = 0; i < tp->nr_args; i++) {
if (strcmp(tp->args[i].type->name, "string") == 0)
pos += snprintf(buf + pos, LEN_OR_ZERO,
", __get_str(%s)",
tp->args[i].name);
else
pos += snprintf(buf + pos, LEN_OR_ZERO, ", REC->%s",
tp->args[i].name);
}
#undef LEN_OR_ZERO
/* return the length of print_fmt */
return pos;
}
static int set_print_fmt(struct trace_probe *tp)
{
int len;
char *print_fmt;
/* First: called with 0 length to calculate the needed length */
len = __set_print_fmt(tp, NULL, 0);
print_fmt = kmalloc(len + 1, GFP_KERNEL);
if (!print_fmt)
return -ENOMEM;
/* Second: actually write the @print_fmt */
__set_print_fmt(tp, print_fmt, len + 1);
tp->call.print_fmt = print_fmt;
return 0;
}
#ifdef CONFIG_PERF_EVENTS
/* Kprobe profile handler */
static __kprobes void
kprobe_perf_func(struct trace_probe *tp, struct pt_regs *regs)
{
struct ftrace_event_call *call = &tp->call;
struct kprobe_trace_entry_head *entry;
struct hlist_head *head;
int size, __size, dsize;
int rctx;
dsize = __get_data_size(tp, regs);
__size = sizeof(*entry) + tp->size + dsize;
size = ALIGN(__size + sizeof(u32), sizeof(u64));
size -= sizeof(u32);
if (WARN_ONCE(size > PERF_MAX_TRACE_SIZE,
"profile buffer not large enough"))
return;
entry = perf_trace_buf_prepare(size, call->event.type, regs, &rctx);
if (!entry)
return;
entry->ip = (unsigned long)tp->rp.kp.addr;
memset(&entry[1], 0, dsize);
store_trace_args(sizeof(*entry), tp, regs, (u8 *)&entry[1], dsize);
head = this_cpu_ptr(call->perf_events);
perf_trace_buf_submit(entry, size, rctx,
entry->ip, 1, regs, head, NULL);
}
/* Kretprobe profile handler */
static __kprobes void
kretprobe_perf_func(struct trace_probe *tp, struct kretprobe_instance *ri,
struct pt_regs *regs)
{
struct ftrace_event_call *call = &tp->call;
struct kretprobe_trace_entry_head *entry;
struct hlist_head *head;
int size, __size, dsize;
int rctx;
dsize = __get_data_size(tp, regs);
__size = sizeof(*entry) + tp->size + dsize;
size = ALIGN(__size + sizeof(u32), sizeof(u64));
size -= sizeof(u32);
if (WARN_ONCE(size > PERF_MAX_TRACE_SIZE,
"profile buffer not large enough"))
return;
entry = perf_trace_buf_prepare(size, call->event.type, regs, &rctx);
if (!entry)
return;
entry->func = (unsigned long)tp->rp.kp.addr;
entry->ret_ip = (unsigned long)ri->ret_addr;
store_trace_args(sizeof(*entry), tp, regs, (u8 *)&entry[1], dsize);
head = this_cpu_ptr(call->perf_events);
perf_trace_buf_submit(entry, size, rctx,
entry->ret_ip, 1, regs, head, NULL);
}
#endif /* CONFIG_PERF_EVENTS */
static __kprobes
int kprobe_register(struct ftrace_event_call *event,
enum trace_reg type, void *data)
{
struct trace_probe *tp = (struct trace_probe *)event->data;
struct ftrace_event_file *file = data;
switch (type) {
case TRACE_REG_REGISTER:
return enable_trace_probe(tp, file);
case TRACE_REG_UNREGISTER:
return disable_trace_probe(tp, file);
#ifdef CONFIG_PERF_EVENTS
case TRACE_REG_PERF_REGISTER:
return enable_trace_probe(tp, NULL);
case TRACE_REG_PERF_UNREGISTER:
return disable_trace_probe(tp, NULL);
case TRACE_REG_PERF_OPEN:
case TRACE_REG_PERF_CLOSE:
case TRACE_REG_PERF_ADD:
case TRACE_REG_PERF_DEL:
return 0;
#endif
}
return 0;
}
static __kprobes
int kprobe_dispatcher(struct kprobe *kp, struct pt_regs *regs)
{
struct trace_probe *tp = container_of(kp, struct trace_probe, rp.kp);
tp->nhit++;
if (tp->flags & TP_FLAG_TRACE)
kprobe_trace_func(tp, regs);
#ifdef CONFIG_PERF_EVENTS
if (tp->flags & TP_FLAG_PROFILE)
kprobe_perf_func(tp, regs);
#endif
return 0; /* We don't tweek kernel, so just return 0 */
}
static __kprobes
int kretprobe_dispatcher(struct kretprobe_instance *ri, struct pt_regs *regs)
{
struct trace_probe *tp = container_of(ri->rp, struct trace_probe, rp);
tp->nhit++;
if (tp->flags & TP_FLAG_TRACE)
kretprobe_trace_func(tp, ri, regs);
#ifdef CONFIG_PERF_EVENTS
if (tp->flags & TP_FLAG_PROFILE)
kretprobe_perf_func(tp, ri, regs);
#endif
return 0; /* We don't tweek kernel, so just return 0 */
}
static struct trace_event_functions kretprobe_funcs = {
.trace = print_kretprobe_event
};
static struct trace_event_functions kprobe_funcs = {
.trace = print_kprobe_event
};
static int register_probe_event(struct trace_probe *tp)
{
struct ftrace_event_call *call = &tp->call;
int ret;
/* Initialize ftrace_event_call */
INIT_LIST_HEAD(&call->class->fields);
if (trace_probe_is_return(tp)) {
call->event.funcs = &kretprobe_funcs;
call->class->define_fields = kretprobe_event_define_fields;
} else {
call->event.funcs = &kprobe_funcs;
call->class->define_fields = kprobe_event_define_fields;
}
if (set_print_fmt(tp) < 0)
return -ENOMEM;
ret = register_ftrace_event(&call->event);
if (!ret) {
kfree(call->print_fmt);
return -ENODEV;
}
call->flags = 0;
call->class->reg = kprobe_register;
call->data = tp;
ret = trace_add_event_call(call);
if (ret) {
pr_info("Failed to register kprobe event: %s\n", call->name);
kfree(call->print_fmt);
unregister_ftrace_event(&call->event);
}
return ret;
}
static int unregister_probe_event(struct trace_probe *tp)
{
int ret;
/* tp->event is unregistered in trace_remove_event_call() */
ret = trace_remove_event_call(&tp->call);
if (!ret)
kfree(tp->call.print_fmt);
return ret;
}
/* Make a debugfs interface for controlling probe points */
static __init int init_kprobe_trace(void)
{
struct dentry *d_tracer;
struct dentry *entry;
if (register_module_notifier(&trace_probe_module_nb))
return -EINVAL;
d_tracer = tracing_init_dentry();
if (!d_tracer)
return 0;
entry = debugfs_create_file("kprobe_events", 0644, d_tracer,
NULL, &kprobe_events_ops);
/* Event list interface */
if (!entry)
pr_warning("Could not create debugfs "
"'kprobe_events' entry\n");
/* Profile interface */
entry = debugfs_create_file("kprobe_profile", 0444, d_tracer,
NULL, &kprobe_profile_ops);
if (!entry)
pr_warning("Could not create debugfs "
"'kprobe_profile' entry\n");
return 0;
}
fs_initcall(init_kprobe_trace);
#ifdef CONFIG_FTRACE_STARTUP_TEST
/*
* The "__used" keeps gcc from removing the function symbol
* from the kallsyms table.
*/
static __used int kprobe_trace_selftest_target(int a1, int a2, int a3,
int a4, int a5, int a6)
{
return a1 + a2 + a3 + a4 + a5 + a6;
}
static struct ftrace_event_file *
find_trace_probe_file(struct trace_probe *tp, struct trace_array *tr)
{
struct ftrace_event_file *file;
list_for_each_entry(file, &tr->events, list)
if (file->event_call == &tp->call)
return file;
return NULL;
}
static __init int kprobe_trace_self_tests_init(void)
{
int ret, warn = 0;
int (*target)(int, int, int, int, int, int);
struct trace_probe *tp;
struct ftrace_event_file *file;
target = kprobe_trace_selftest_target;
pr_info("Testing kprobe tracing: ");
ret = traceprobe_command("p:testprobe kprobe_trace_selftest_target "
"$stack $stack0 +0($stack)",
create_trace_probe);
if (WARN_ON_ONCE(ret)) {
pr_warn("error on probing function entry.\n");
warn++;
} else {
/* Enable trace point */
tp = find_trace_probe("testprobe", KPROBE_EVENT_SYSTEM);
if (WARN_ON_ONCE(tp == NULL)) {
pr_warn("error on getting new probe.\n");
warn++;
} else {
file = find_trace_probe_file(tp, top_trace_array());
if (WARN_ON_ONCE(file == NULL)) {
pr_warn("error on getting probe file.\n");
warn++;
} else
enable_trace_probe(tp, file);
}
}
ret = traceprobe_command("r:testprobe2 kprobe_trace_selftest_target "
"$retval", create_trace_probe);
if (WARN_ON_ONCE(ret)) {
pr_warn("error on probing function return.\n");
warn++;
} else {
/* Enable trace point */
tp = find_trace_probe("testprobe2", KPROBE_EVENT_SYSTEM);
if (WARN_ON_ONCE(tp == NULL)) {
pr_warn("error on getting 2nd new probe.\n");
warn++;
} else {
file = find_trace_probe_file(tp, top_trace_array());
if (WARN_ON_ONCE(file == NULL)) {
pr_warn("error on getting probe file.\n");
warn++;
} else
enable_trace_probe(tp, file);
}
}
if (warn)
goto end;
ret = target(1, 2, 3, 4, 5, 6);
/* Disable trace points before removing it */
tp = find_trace_probe("testprobe", KPROBE_EVENT_SYSTEM);
if (WARN_ON_ONCE(tp == NULL)) {
pr_warn("error on getting test probe.\n");
warn++;
} else {
file = find_trace_probe_file(tp, top_trace_array());
if (WARN_ON_ONCE(file == NULL)) {
pr_warn("error on getting probe file.\n");
warn++;
} else
disable_trace_probe(tp, file);
}
tp = find_trace_probe("testprobe2", KPROBE_EVENT_SYSTEM);
if (WARN_ON_ONCE(tp == NULL)) {
pr_warn("error on getting 2nd test probe.\n");
warn++;
} else {
file = find_trace_probe_file(tp, top_trace_array());
if (WARN_ON_ONCE(file == NULL)) {
pr_warn("error on getting probe file.\n");
warn++;
} else
disable_trace_probe(tp, file);
}
ret = traceprobe_command("-:testprobe", create_trace_probe);
if (WARN_ON_ONCE(ret)) {
pr_warn("error on deleting a probe.\n");
warn++;
}
ret = traceprobe_command("-:testprobe2", create_trace_probe);
if (WARN_ON_ONCE(ret)) {
pr_warn("error on deleting a probe.\n");
warn++;
}
end:
release_all_trace_probes();
if (warn)
pr_cont("NG: Some tests are failed. Please check them.\n");
else
pr_cont("OK\n");
return 0;
}
late_initcall(kprobe_trace_self_tests_init);
#endif
| gpl-2.0 |
SlimRoms/kernel_htc_flounder | drivers/block/rsxx/config.c | 4692 | 5635 | /*
* Filename: config.c
*
*
* Authors: Joshua Morris <josh.h.morris@us.ibm.com>
* Philip Kelleher <pjk1939@linux.vnet.ibm.com>
*
* (C) Copyright 2013 IBM Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/crc32.h>
#include <linux/swab.h>
#include "rsxx_priv.h"
#include "rsxx_cfg.h"
static void initialize_config(struct rsxx_card_cfg *cfg)
{
cfg->hdr.version = RSXX_CFG_VERSION;
cfg->data.block_size = RSXX_HW_BLK_SIZE;
cfg->data.stripe_size = RSXX_HW_BLK_SIZE;
cfg->data.vendor_id = RSXX_VENDOR_ID_IBM;
cfg->data.cache_order = (-1);
cfg->data.intr_coal.mode = RSXX_INTR_COAL_DISABLED;
cfg->data.intr_coal.count = 0;
cfg->data.intr_coal.latency = 0;
}
static u32 config_data_crc32(struct rsxx_card_cfg *cfg)
{
/*
* Return the compliment of the CRC to ensure compatibility
* (i.e. this is how early rsxx drivers did it.)
*/
return ~crc32(~0, &cfg->data, sizeof(cfg->data));
}
/*----------------- Config Byte Swap Functions -------------------*/
static void config_hdr_be_to_cpu(struct card_cfg_hdr *hdr)
{
hdr->version = be32_to_cpu((__force __be32) hdr->version);
hdr->crc = be32_to_cpu((__force __be32) hdr->crc);
}
static void config_hdr_cpu_to_be(struct card_cfg_hdr *hdr)
{
hdr->version = (__force u32) cpu_to_be32(hdr->version);
hdr->crc = (__force u32) cpu_to_be32(hdr->crc);
}
static void config_data_swab(struct rsxx_card_cfg *cfg)
{
u32 *data = (u32 *) &cfg->data;
int i;
for (i = 0; i < (sizeof(cfg->data) / 4); i++)
data[i] = swab32(data[i]);
}
static void config_data_le_to_cpu(struct rsxx_card_cfg *cfg)
{
u32 *data = (u32 *) &cfg->data;
int i;
for (i = 0; i < (sizeof(cfg->data) / 4); i++)
data[i] = le32_to_cpu((__force __le32) data[i]);
}
static void config_data_cpu_to_le(struct rsxx_card_cfg *cfg)
{
u32 *data = (u32 *) &cfg->data;
int i;
for (i = 0; i < (sizeof(cfg->data) / 4); i++)
data[i] = (__force u32) cpu_to_le32(data[i]);
}
/*----------------- Config Operations ------------------*/
static int rsxx_save_config(struct rsxx_cardinfo *card)
{
struct rsxx_card_cfg cfg;
int st;
memcpy(&cfg, &card->config, sizeof(cfg));
if (unlikely(cfg.hdr.version != RSXX_CFG_VERSION)) {
dev_err(CARD_TO_DEV(card),
"Cannot save config with invalid version %d\n",
cfg.hdr.version);
return -EINVAL;
}
/* Convert data to little endian for the CRC calculation. */
config_data_cpu_to_le(&cfg);
cfg.hdr.crc = config_data_crc32(&cfg);
/*
* Swap the data from little endian to big endian so it can be
* stored.
*/
config_data_swab(&cfg);
config_hdr_cpu_to_be(&cfg.hdr);
st = rsxx_creg_write(card, CREG_ADD_CONFIG, sizeof(cfg), &cfg, 1);
if (st)
return st;
return 0;
}
int rsxx_load_config(struct rsxx_cardinfo *card)
{
int st;
u32 crc;
st = rsxx_creg_read(card, CREG_ADD_CONFIG, sizeof(card->config),
&card->config, 1);
if (st) {
dev_err(CARD_TO_DEV(card),
"Failed reading card config.\n");
return st;
}
config_hdr_be_to_cpu(&card->config.hdr);
if (card->config.hdr.version == RSXX_CFG_VERSION) {
/*
* We calculate the CRC with the data in little endian, because
* early drivers did not take big endian CPUs into account.
* The data is always stored in big endian, so we need to byte
* swap it before calculating the CRC.
*/
config_data_swab(&card->config);
/* Check the CRC */
crc = config_data_crc32(&card->config);
if (crc != card->config.hdr.crc) {
dev_err(CARD_TO_DEV(card),
"Config corruption detected!\n");
dev_info(CARD_TO_DEV(card),
"CRC (sb x%08x is x%08x)\n",
card->config.hdr.crc, crc);
return -EIO;
}
/* Convert the data to CPU byteorder */
config_data_le_to_cpu(&card->config);
} else if (card->config.hdr.version != 0) {
dev_err(CARD_TO_DEV(card),
"Invalid config version %d.\n",
card->config.hdr.version);
/*
* Config version changes require special handling from the
* user
*/
return -EINVAL;
} else {
dev_info(CARD_TO_DEV(card),
"Initializing card configuration.\n");
initialize_config(&card->config);
st = rsxx_save_config(card);
if (st)
return st;
}
card->config_valid = 1;
dev_dbg(CARD_TO_DEV(card), "version: x%08x\n",
card->config.hdr.version);
dev_dbg(CARD_TO_DEV(card), "crc: x%08x\n",
card->config.hdr.crc);
dev_dbg(CARD_TO_DEV(card), "block_size: x%08x\n",
card->config.data.block_size);
dev_dbg(CARD_TO_DEV(card), "stripe_size: x%08x\n",
card->config.data.stripe_size);
dev_dbg(CARD_TO_DEV(card), "vendor_id: x%08x\n",
card->config.data.vendor_id);
dev_dbg(CARD_TO_DEV(card), "cache_order: x%08x\n",
card->config.data.cache_order);
dev_dbg(CARD_TO_DEV(card), "mode: x%08x\n",
card->config.data.intr_coal.mode);
dev_dbg(CARD_TO_DEV(card), "count: x%08x\n",
card->config.data.intr_coal.count);
dev_dbg(CARD_TO_DEV(card), "latency: x%08x\n",
card->config.data.intr_coal.latency);
return 0;
}
| gpl-2.0 |
robcore/machinex_kernel | drivers/usb/host/ehci-ls1x.c | 4948 | 3459 | /*
* Bus Glue for Loongson LS1X built-in EHCI controller.
*
* Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/platform_device.h>
static int ehci_ls1x_reset(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
int ret;
ehci->caps = hcd->regs;
ret = ehci_setup(hcd);
if (ret)
return ret;
ehci_port_power(ehci, 0);
return 0;
}
static const struct hc_driver ehci_ls1x_hc_driver = {
.description = hcd_name,
.product_desc = "LOONGSON1 EHCI",
.hcd_priv_size = sizeof(struct ehci_hcd),
/*
* generic hardware linkage
*/
.irq = ehci_irq,
.flags = HCD_MEMORY | HCD_USB2,
/*
* basic lifecycle operations
*/
.reset = ehci_ls1x_reset,
.start = ehci_run,
.stop = ehci_stop,
.shutdown = ehci_shutdown,
/*
* managing i/o requests and associated device resources
*/
.urb_enqueue = ehci_urb_enqueue,
.urb_dequeue = ehci_urb_dequeue,
.endpoint_disable = ehci_endpoint_disable,
.endpoint_reset = ehci_endpoint_reset,
/*
* scheduling support
*/
.get_frame_number = ehci_get_frame,
/*
* root hub support
*/
.hub_status_data = ehci_hub_status_data,
.hub_control = ehci_hub_control,
.relinquish_port = ehci_relinquish_port,
.port_handed_over = ehci_port_handed_over,
.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
};
static int ehci_hcd_ls1x_probe(struct platform_device *pdev)
{
struct usb_hcd *hcd;
struct resource *res;
int irq;
int ret;
pr_debug("initializing loongson1 ehci USB Controller\n");
if (usb_disabled())
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res) {
dev_err(&pdev->dev,
"Found HC with no IRQ. Check %s setup!\n",
dev_name(&pdev->dev));
return -ENODEV;
}
irq = res->start;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev,
"Found HC with no register addr. Check %s setup!\n",
dev_name(&pdev->dev));
return -ENODEV;
}
hcd = usb_create_hcd(&ehci_ls1x_hc_driver, &pdev->dev,
dev_name(&pdev->dev));
if (!hcd)
return -ENOMEM;
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
dev_dbg(&pdev->dev, "controller already in use\n");
ret = -EBUSY;
goto err_put_hcd;
}
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
if (hcd->regs == NULL) {
dev_dbg(&pdev->dev, "error mapping memory\n");
ret = -EFAULT;
goto err_release_region;
}
ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
if (ret)
goto err_iounmap;
return ret;
err_iounmap:
iounmap(hcd->regs);
err_release_region:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err_put_hcd:
usb_put_hcd(hcd);
return ret;
}
static int ehci_hcd_ls1x_remove(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
usb_remove_hcd(hcd);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
return 0;
}
static struct platform_driver ehci_ls1x_driver = {
.probe = ehci_hcd_ls1x_probe,
.remove = ehci_hcd_ls1x_remove,
.shutdown = usb_hcd_platform_shutdown,
.driver = {
.name = "ls1x-ehci",
.owner = THIS_MODULE,
},
};
MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ls1x-ehci");
| gpl-2.0 |
jamison904/kernel_m919 | drivers/staging/rts_pstor/rtsx_scsi.c | 5204 | 77379 | /* Driver for Realtek PCI-Express card reader
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
* Author:
* wwang (wei_wang@realsil.com.cn)
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
*/
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "rtsx_transport.h"
#include "rtsx_sys.h"
#include "rtsx_card.h"
#include "rtsx_chip.h"
#include "rtsx_scsi.h"
#include "sd.h"
#include "ms.h"
#include "spi.h"
void scsi_show_command(struct scsi_cmnd *srb)
{
char *what = NULL;
int i, unknown_cmd = 0;
switch (srb->cmnd[0]) {
case TEST_UNIT_READY: what = "TEST_UNIT_READY"; break;
case REZERO_UNIT: what = "REZERO_UNIT"; break;
case REQUEST_SENSE: what = "REQUEST_SENSE"; break;
case FORMAT_UNIT: what = "FORMAT_UNIT"; break;
case READ_BLOCK_LIMITS: what = "READ_BLOCK_LIMITS"; break;
case REASSIGN_BLOCKS: what = "REASSIGN_BLOCKS"; break;
case READ_6: what = "READ_6"; break;
case WRITE_6: what = "WRITE_6"; break;
case SEEK_6: what = "SEEK_6"; break;
case READ_REVERSE: what = "READ_REVERSE"; break;
case WRITE_FILEMARKS: what = "WRITE_FILEMARKS"; break;
case SPACE: what = "SPACE"; break;
case INQUIRY: what = "INQUIRY"; break;
case RECOVER_BUFFERED_DATA: what = "RECOVER_BUFFERED_DATA"; break;
case MODE_SELECT: what = "MODE_SELECT"; break;
case RESERVE: what = "RESERVE"; break;
case RELEASE: what = "RELEASE"; break;
case COPY: what = "COPY"; break;
case ERASE: what = "ERASE"; break;
case MODE_SENSE: what = "MODE_SENSE"; break;
case START_STOP: what = "START_STOP"; break;
case RECEIVE_DIAGNOSTIC: what = "RECEIVE_DIAGNOSTIC"; break;
case SEND_DIAGNOSTIC: what = "SEND_DIAGNOSTIC"; break;
case ALLOW_MEDIUM_REMOVAL: what = "ALLOW_MEDIUM_REMOVAL"; break;
case SET_WINDOW: what = "SET_WINDOW"; break;
case READ_CAPACITY: what = "READ_CAPACITY"; break;
case READ_10: what = "READ_10"; break;
case WRITE_10: what = "WRITE_10"; break;
case SEEK_10: what = "SEEK_10"; break;
case WRITE_VERIFY: what = "WRITE_VERIFY"; break;
case VERIFY: what = "VERIFY"; break;
case SEARCH_HIGH: what = "SEARCH_HIGH"; break;
case SEARCH_EQUAL: what = "SEARCH_EQUAL"; break;
case SEARCH_LOW: what = "SEARCH_LOW"; break;
case SET_LIMITS: what = "SET_LIMITS"; break;
case READ_POSITION: what = "READ_POSITION"; break;
case SYNCHRONIZE_CACHE: what = "SYNCHRONIZE_CACHE"; break;
case LOCK_UNLOCK_CACHE: what = "LOCK_UNLOCK_CACHE"; break;
case READ_DEFECT_DATA: what = "READ_DEFECT_DATA"; break;
case MEDIUM_SCAN: what = "MEDIUM_SCAN"; break;
case COMPARE: what = "COMPARE"; break;
case COPY_VERIFY: what = "COPY_VERIFY"; break;
case WRITE_BUFFER: what = "WRITE_BUFFER"; break;
case READ_BUFFER: what = "READ_BUFFER"; break;
case UPDATE_BLOCK: what = "UPDATE_BLOCK"; break;
case READ_LONG: what = "READ_LONG"; break;
case WRITE_LONG: what = "WRITE_LONG"; break;
case CHANGE_DEFINITION: what = "CHANGE_DEFINITION"; break;
case WRITE_SAME: what = "WRITE_SAME"; break;
case GPCMD_READ_SUBCHANNEL: what = "READ SUBCHANNEL"; break;
case READ_TOC: what = "READ_TOC"; break;
case GPCMD_READ_HEADER: what = "READ HEADER"; break;
case GPCMD_PLAY_AUDIO_10: what = "PLAY AUDIO (10)"; break;
case GPCMD_PLAY_AUDIO_MSF: what = "PLAY AUDIO MSF"; break;
case GPCMD_GET_EVENT_STATUS_NOTIFICATION:
what = "GET EVENT/STATUS NOTIFICATION"; break;
case GPCMD_PAUSE_RESUME: what = "PAUSE/RESUME"; break;
case LOG_SELECT: what = "LOG_SELECT"; break;
case LOG_SENSE: what = "LOG_SENSE"; break;
case GPCMD_STOP_PLAY_SCAN: what = "STOP PLAY/SCAN"; break;
case GPCMD_READ_DISC_INFO: what = "READ DISC INFORMATION"; break;
case GPCMD_READ_TRACK_RZONE_INFO:
what = "READ TRACK INFORMATION"; break;
case GPCMD_RESERVE_RZONE_TRACK: what = "RESERVE TRACK"; break;
case GPCMD_SEND_OPC: what = "SEND OPC"; break;
case MODE_SELECT_10: what = "MODE_SELECT_10"; break;
case GPCMD_REPAIR_RZONE_TRACK: what = "REPAIR TRACK"; break;
case 0x59: what = "READ MASTER CUE"; break;
case MODE_SENSE_10: what = "MODE_SENSE_10"; break;
case GPCMD_CLOSE_TRACK: what = "CLOSE TRACK/SESSION"; break;
case 0x5C: what = "READ BUFFER CAPACITY"; break;
case 0x5D: what = "SEND CUE SHEET"; break;
case GPCMD_BLANK: what = "BLANK"; break;
case REPORT_LUNS: what = "REPORT LUNS"; break;
case MOVE_MEDIUM: what = "MOVE_MEDIUM or PLAY AUDIO (12)"; break;
case READ_12: what = "READ_12"; break;
case WRITE_12: what = "WRITE_12"; break;
case WRITE_VERIFY_12: what = "WRITE_VERIFY_12"; break;
case SEARCH_HIGH_12: what = "SEARCH_HIGH_12"; break;
case SEARCH_EQUAL_12: what = "SEARCH_EQUAL_12"; break;
case SEARCH_LOW_12: what = "SEARCH_LOW_12"; break;
case SEND_VOLUME_TAG: what = "SEND_VOLUME_TAG"; break;
case READ_ELEMENT_STATUS: what = "READ_ELEMENT_STATUS"; break;
case GPCMD_READ_CD_MSF: what = "READ CD MSF"; break;
case GPCMD_SCAN: what = "SCAN"; break;
case GPCMD_SET_SPEED: what = "SET CD SPEED"; break;
case GPCMD_MECHANISM_STATUS: what = "MECHANISM STATUS"; break;
case GPCMD_READ_CD: what = "READ CD"; break;
case 0xE1: what = "WRITE CONTINUE"; break;
case WRITE_LONG_2: what = "WRITE_LONG_2"; break;
case VENDOR_CMND: what = "Realtek's vendor command"; break;
default: what = "(unknown command)"; unknown_cmd = 1; break;
}
if (srb->cmnd[0] != TEST_UNIT_READY) {
RTSX_DEBUGP("Command %s (%d bytes)\n", what, srb->cmd_len);
}
if (unknown_cmd) {
RTSX_DEBUGP("");
for (i = 0; i < srb->cmd_len && i < 16; i++)
RTSX_DEBUGPN(" %02x", srb->cmnd[i]);
RTSX_DEBUGPN("\n");
}
}
void set_sense_type(struct rtsx_chip *chip, unsigned int lun, int sense_type)
{
switch (sense_type) {
case SENSE_TYPE_MEDIA_CHANGE:
set_sense_data(chip, lun, CUR_ERR, 0x06, 0, 0x28, 0, 0, 0);
break;
case SENSE_TYPE_MEDIA_NOT_PRESENT:
set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x3A, 0, 0, 0);
break;
case SENSE_TYPE_MEDIA_LBA_OVER_RANGE:
set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x21, 0, 0, 0);
break;
case SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT:
set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x25, 0, 0, 0);
break;
case SENSE_TYPE_MEDIA_WRITE_PROTECT:
set_sense_data(chip, lun, CUR_ERR, 0x07, 0, 0x27, 0, 0, 0);
break;
case SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR:
set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x11, 0, 0, 0);
break;
case SENSE_TYPE_MEDIA_WRITE_ERR:
set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x0C, 0x02, 0, 0);
break;
case SENSE_TYPE_MEDIA_INVALID_CMD_FIELD:
set_sense_data(chip, lun, CUR_ERR, ILGAL_REQ, 0,
ASC_INVLD_CDB, ASCQ_INVLD_CDB, CDB_ILLEGAL, 1);
break;
case SENSE_TYPE_FORMAT_IN_PROGRESS:
set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04, 0, 0);
break;
case SENSE_TYPE_FORMAT_CMD_FAILED:
set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x31, 0x01, 0, 0);
break;
#ifdef SUPPORT_MAGIC_GATE
case SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB:
set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x6F, 0x02, 0, 0);
break;
case SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN:
set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x6F, 0x00, 0, 0);
break;
case SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM:
set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x30, 0x00, 0, 0);
break;
case SENSE_TYPE_MG_WRITE_ERR:
set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x0C, 0x00, 0, 0);
break;
#endif
#ifdef SUPPORT_SD_LOCK
case SENSE_TYPE_MEDIA_READ_FORBIDDEN:
set_sense_data(chip, lun, CUR_ERR, 0x07, 0, 0x11, 0x13, 0, 0);
break;
#endif
case SENSE_TYPE_NO_SENSE:
default:
set_sense_data(chip, lun, CUR_ERR, 0, 0, 0, 0, 0, 0);
break;
}
}
void set_sense_data(struct rtsx_chip *chip, unsigned int lun, u8 err_code, u8 sense_key,
u32 info, u8 asc, u8 ascq, u8 sns_key_info0, u16 sns_key_info1)
{
struct sense_data_t *sense = &(chip->sense_buffer[lun]);
sense->err_code = err_code;
sense->sense_key = sense_key;
sense->info[0] = (u8)(info >> 24);
sense->info[1] = (u8)(info >> 16);
sense->info[2] = (u8)(info >> 8);
sense->info[3] = (u8)info;
sense->ad_sense_len = sizeof(struct sense_data_t) - 8;
sense->asc = asc;
sense->ascq = ascq;
if (sns_key_info0 != 0) {
sense->sns_key_info[0] = SKSV | sns_key_info0;
sense->sns_key_info[1] = (sns_key_info1 & 0xf0) >> 8;
sense->sns_key_info[2] = sns_key_info1 & 0x0f;
}
}
static int test_unit_ready(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
return TRANSPORT_FAILED;
}
if (!(CHK_BIT(chip->lun_mc, lun))) {
SET_BIT(chip->lun_mc, lun);
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
return TRANSPORT_FAILED;
}
#ifdef SUPPORT_SD_LOCK
if (get_lun_card(chip, SCSI_LUN(srb)) == SD_CARD) {
struct sd_info *sd_card = &(chip->sd_card);
if (sd_card->sd_lock_notify) {
sd_card->sd_lock_notify = 0;
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
return TRANSPORT_FAILED;
} else if (sd_card->sd_lock_status & SD_LOCKED) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_READ_FORBIDDEN);
return TRANSPORT_FAILED;
}
}
#endif
return TRANSPORT_GOOD;
}
static unsigned char formatter_inquiry_str[20] = {
'M', 'E', 'M', 'O', 'R', 'Y', 'S', 'T', 'I', 'C', 'K',
#ifdef SUPPORT_MAGIC_GATE
'-', 'M', 'G', /* Byte[47:49] */
#else
0x20, 0x20, 0x20, /* Byte[47:49] */
#endif
#ifdef SUPPORT_MAGIC_GATE
0x0B, /* Byte[50]: MG, MS, MSPro, MSXC */
#else
0x09, /* Byte[50]: MS, MSPro, MSXC */
#endif
0x00, /* Byte[51]: Category Specific Commands */
0x00, /* Byte[52]: Access Control and feature */
0x20, 0x20, 0x20, /* Byte[53:55] */
};
static int inquiry(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
char *inquiry_default = (char *)"Generic-xD/SD/M.S. 1.00 ";
char *inquiry_sdms = (char *)"Generic-SD/MemoryStick 1.00 ";
char *inquiry_sd = (char *)"Generic-SD/MMC 1.00 ";
char *inquiry_ms = (char *)"Generic-MemoryStick 1.00 ";
char *inquiry_string;
unsigned char sendbytes;
unsigned char *buf;
u8 card = get_lun_card(chip, lun);
int pro_formatter_flag = 0;
unsigned char inquiry_buf[] = {
QULIFIRE|DRCT_ACCESS_DEV,
RMB_DISC|0x0D,
0x00,
0x01,
0x1f,
0x02,
0,
REL_ADR|WBUS_32|WBUS_16|SYNC|LINKED|CMD_QUE|SFT_RE,
};
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
if (chip->lun2card[lun] == SD_CARD) {
inquiry_string = inquiry_sd;
} else {
inquiry_string = inquiry_ms;
}
} else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
inquiry_string = inquiry_sdms;
} else {
inquiry_string = inquiry_default;
}
buf = vmalloc(scsi_bufflen(srb));
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
#ifdef SUPPORT_MAGIC_GATE
if ((chip->mspro_formatter_enable) &&
(chip->lun2card[lun] & MS_CARD))
#else
if (chip->mspro_formatter_enable)
#endif
{
if (!card || (card == MS_CARD)) {
pro_formatter_flag = 1;
}
}
if (pro_formatter_flag) {
if (scsi_bufflen(srb) < 56) {
sendbytes = (unsigned char)(scsi_bufflen(srb));
} else {
sendbytes = 56;
}
} else {
if (scsi_bufflen(srb) < 36) {
sendbytes = (unsigned char)(scsi_bufflen(srb));
} else {
sendbytes = 36;
}
}
if (sendbytes > 8) {
memcpy(buf, inquiry_buf, 8);
memcpy(buf + 8, inquiry_string, sendbytes - 8);
if (pro_formatter_flag) {
/* Additional Length */
buf[4] = 0x33;
}
} else {
memcpy(buf, inquiry_buf, sendbytes);
}
if (pro_formatter_flag) {
if (sendbytes > 36) {
memcpy(buf + 36, formatter_inquiry_str, sendbytes - 36);
}
}
scsi_set_resid(srb, 0);
rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
vfree(buf);
return TRANSPORT_GOOD;
}
static int start_stop_unit(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
scsi_set_resid(srb, scsi_bufflen(srb));
if (srb->cmnd[1] == 1)
return TRANSPORT_GOOD;
switch (srb->cmnd[0x4]) {
case STOP_MEDIUM:
/* Media disabled */
return TRANSPORT_GOOD;
case UNLOAD_MEDIUM:
/* Media shall be unload */
if (check_card_ready(chip, lun))
eject_card(chip, lun);
return TRANSPORT_GOOD;
case MAKE_MEDIUM_READY:
case LOAD_MEDIUM:
if (check_card_ready(chip, lun)) {
return TRANSPORT_GOOD;
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
}
TRACE_RET(chip, TRANSPORT_ERROR);
}
static int allow_medium_removal(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int prevent;
prevent = srb->cmnd[4] & 0x1;
scsi_set_resid(srb, 0);
if (prevent) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return TRANSPORT_GOOD;
}
static int request_sense(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct sense_data_t *sense;
unsigned int lun = SCSI_LUN(srb);
struct ms_info *ms_card = &(chip->ms_card);
unsigned char *tmp, *buf;
sense = &(chip->sense_buffer[lun]);
if ((get_lun_card(chip, lun) == MS_CARD) && ms_card->pro_under_formatting) {
if (ms_card->format_status == FORMAT_SUCCESS) {
set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
ms_card->pro_under_formatting = 0;
ms_card->progress = 0;
} else if (ms_card->format_status == FORMAT_IN_PROGRESS) {
/* Logical Unit Not Ready Format in Progress */
set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04,
0, (u16)(ms_card->progress));
} else {
/* Format Command Failed */
set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED);
ms_card->pro_under_formatting = 0;
ms_card->progress = 0;
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
}
buf = vmalloc(scsi_bufflen(srb));
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
tmp = (unsigned char *)sense;
memcpy(buf, tmp, scsi_bufflen(srb));
rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
vfree(buf);
scsi_set_resid(srb, 0);
/* Reset Sense Data */
set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
return TRANSPORT_GOOD;
}
static void ms_mode_sense(struct rtsx_chip *chip, u8 cmd,
int lun, u8 *buf, int buf_len)
{
struct ms_info *ms_card = &(chip->ms_card);
int sys_info_offset;
int data_size = buf_len;
int support_format = 0;
int i = 0;
if (cmd == MODE_SENSE) {
sys_info_offset = 8;
if (data_size > 0x68) {
data_size = 0x68;
}
buf[i++] = 0x67; /* Mode Data Length */
} else {
sys_info_offset = 12;
if (data_size > 0x6C) {
data_size = 0x6C;
}
buf[i++] = 0x00; /* Mode Data Length (MSB) */
buf[i++] = 0x6A; /* Mode Data Length (LSB) */
}
/* Medium Type Code */
if (check_card_ready(chip, lun)) {
if (CHK_MSXC(ms_card)) {
support_format = 1;
buf[i++] = 0x40;
} else if (CHK_MSPRO(ms_card)) {
support_format = 1;
buf[i++] = 0x20;
} else {
buf[i++] = 0x10;
}
/* WP */
if (check_card_wp(chip, lun)) {
buf[i++] = 0x80;
} else {
buf[i++] = 0x00;
}
} else {
buf[i++] = 0x00; /* MediaType */
buf[i++] = 0x00; /* WP */
}
buf[i++] = 0x00; /* Reserved */
if (cmd == MODE_SENSE_10) {
buf[i++] = 0x00; /* Reserved */
buf[i++] = 0x00; /* Block descriptor length(MSB) */
buf[i++] = 0x00; /* Block descriptor length(LSB) */
/* The Following Data is the content of "Page 0x20" */
if (data_size >= 9)
buf[i++] = 0x20; /* Page Code */
if (data_size >= 10)
buf[i++] = 0x62; /* Page Length */
if (data_size >= 11)
buf[i++] = 0x00; /* No Access Control */
if (data_size >= 12) {
if (support_format) {
buf[i++] = 0xC0; /* SF, SGM */
} else {
buf[i++] = 0x00;
}
}
} else {
/* The Following Data is the content of "Page 0x20" */
if (data_size >= 5)
buf[i++] = 0x20; /* Page Code */
if (data_size >= 6)
buf[i++] = 0x62; /* Page Length */
if (data_size >= 7)
buf[i++] = 0x00; /* No Access Control */
if (data_size >= 8) {
if (support_format) {
buf[i++] = 0xC0; /* SF, SGM */
} else {
buf[i++] = 0x00;
}
}
}
if (data_size > sys_info_offset) {
/* 96 Bytes Attribute Data */
int len = data_size - sys_info_offset;
len = (len < 96) ? len : 96;
memcpy(buf + sys_info_offset, ms_card->raw_sys_info, len);
}
}
static int mode_sense(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
unsigned int dataSize;
int status;
int pro_formatter_flag;
unsigned char pageCode, *buf;
u8 card = get_lun_card(chip, lun);
#ifndef SUPPORT_MAGIC_GATE
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
scsi_set_resid(srb, scsi_bufflen(srb));
TRACE_RET(chip, TRANSPORT_FAILED);
}
#endif
pro_formatter_flag = 0;
dataSize = 8;
#ifdef SUPPORT_MAGIC_GATE
if ((chip->lun2card[lun] & MS_CARD)) {
if (!card || (card == MS_CARD)) {
dataSize = 108;
if (chip->mspro_formatter_enable) {
pro_formatter_flag = 1;
}
}
}
#else
if (card == MS_CARD) {
if (chip->mspro_formatter_enable) {
pro_formatter_flag = 1;
dataSize = 108;
}
}
#endif
buf = kmalloc(dataSize, GFP_KERNEL);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
pageCode = srb->cmnd[2] & 0x3f;
if ((pageCode == 0x3F) || (pageCode == 0x1C) ||
(pageCode == 0x00) ||
(pro_formatter_flag && (pageCode == 0x20))) {
if (srb->cmnd[0] == MODE_SENSE) {
if ((pageCode == 0x3F) || (pageCode == 0x20)) {
ms_mode_sense(chip, srb->cmnd[0],
lun, buf, dataSize);
} else {
dataSize = 4;
buf[0] = 0x03;
buf[1] = 0x00;
if (check_card_wp(chip, lun)) {
buf[2] = 0x80;
} else {
buf[2] = 0x00;
}
buf[3] = 0x00;
}
} else {
if ((pageCode == 0x3F) || (pageCode == 0x20)) {
ms_mode_sense(chip, srb->cmnd[0],
lun, buf, dataSize);
} else {
dataSize = 8;
buf[0] = 0x00;
buf[1] = 0x06;
buf[2] = 0x00;
if (check_card_wp(chip, lun)) {
buf[3] = 0x80;
} else {
buf[3] = 0x00;
}
buf[4] = 0x00;
buf[5] = 0x00;
buf[6] = 0x00;
buf[7] = 0x00;
}
}
status = TRANSPORT_GOOD;
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
scsi_set_resid(srb, scsi_bufflen(srb));
status = TRANSPORT_FAILED;
}
if (status == TRANSPORT_GOOD) {
unsigned int len = min(scsi_bufflen(srb), dataSize);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
}
kfree(buf);
return status;
}
static int read_write(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
#ifdef SUPPORT_SD_LOCK
struct sd_info *sd_card = &(chip->sd_card);
#endif
unsigned int lun = SCSI_LUN(srb);
int retval;
u32 start_sec;
u16 sec_cnt;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
if (!check_card_ready(chip, lun) || (get_card_size(chip, lun) == 0)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (!(CHK_BIT(chip->lun_mc, lun))) {
SET_BIT(chip->lun_mc, lun);
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
return TRANSPORT_FAILED;
}
#ifdef SUPPORT_SD_LOCK
if (sd_card->sd_erase_status) {
/* Accessing to any card is forbidden
* until the erase procedure of SD is completed
*/
RTSX_DEBUGP("SD card being erased!\n");
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_READ_FORBIDDEN);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (get_lun_card(chip, lun) == SD_CARD) {
if (sd_card->sd_lock_status & SD_LOCKED) {
RTSX_DEBUGP("SD card locked!\n");
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_READ_FORBIDDEN);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
#endif
if ((srb->cmnd[0] == READ_10) || (srb->cmnd[0] == WRITE_10)) {
start_sec = ((u32)srb->cmnd[2] << 24) | ((u32)srb->cmnd[3] << 16) |
((u32)srb->cmnd[4] << 8) | ((u32)srb->cmnd[5]);
sec_cnt = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
} else if ((srb->cmnd[0] == READ_6) || (srb->cmnd[0] == WRITE_6)) {
start_sec = ((u32)(srb->cmnd[1] & 0x1F) << 16) |
((u32)srb->cmnd[2] << 8) | ((u32)srb->cmnd[3]);
sec_cnt = srb->cmnd[4];
} else if ((srb->cmnd[0] == VENDOR_CMND) && (srb->cmnd[1] == SCSI_APP_CMD) &&
((srb->cmnd[2] == PP_READ10) || (srb->cmnd[2] == PP_WRITE10))) {
start_sec = ((u32)srb->cmnd[4] << 24) | ((u32)srb->cmnd[5] << 16) |
((u32)srb->cmnd[6] << 8) | ((u32)srb->cmnd[7]);
sec_cnt = ((u16)(srb->cmnd[9]) << 8) | srb->cmnd[10];
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
/* In some test, we will receive a start_sec like 0xFFFFFFFF.
* In this situation, start_sec + sec_cnt will overflow, so we
* need to judge start_sec at first
*/
if ((start_sec > get_card_size(chip, lun)) ||
((start_sec + sec_cnt) > get_card_size(chip, lun))) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LBA_OVER_RANGE);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (sec_cnt == 0) {
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
if (chip->rw_fail_cnt[lun] == 3) {
RTSX_DEBUGP("read/write fail three times in succession\n");
if (srb->sc_data_direction == DMA_FROM_DEVICE) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
}
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (srb->sc_data_direction == DMA_TO_DEVICE) {
if (check_card_wp(chip, lun)) {
RTSX_DEBUGP("Write protected card!\n");
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_PROTECT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (CHECK_PID(chip, 0x5209) && chip->max_payload) {
u8 val = 0x10 | (chip->max_payload << 5);
retval = rtsx_write_cfg_dw(chip, 0, 0x78, 0xFF, val);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
}
}
retval = card_rw(srb, chip, start_sec, sec_cnt);
if (retval != STATUS_SUCCESS) {
if (chip->need_release & chip->lun2card[lun]) {
chip->rw_fail_cnt[lun] = 0;
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
} else {
chip->rw_fail_cnt[lun]++;
if (srb->sc_data_direction == DMA_FROM_DEVICE) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
}
}
retval = TRANSPORT_FAILED;
TRACE_GOTO(chip, Exit);
} else {
chip->rw_fail_cnt[lun] = 0;
retval = TRANSPORT_GOOD;
}
scsi_set_resid(srb, 0);
Exit:
if (srb->sc_data_direction == DMA_TO_DEVICE) {
if (CHECK_PID(chip, 0x5209) && chip->max_payload) {
retval = rtsx_write_cfg_dw(chip, 0, 0x78, 0xFF, 0x10);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
}
}
return retval;
}
static int read_format_capacity(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned char *buf;
unsigned int lun = SCSI_LUN(srb);
unsigned int buf_len;
u8 card = get_lun_card(chip, lun);
u32 card_size;
int desc_cnt;
int i = 0;
if (!check_card_ready(chip, lun)) {
if (!chip->mspro_formatter_enable) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
buf_len = (scsi_bufflen(srb) > 12) ? 0x14 : 12;
buf = kmalloc(buf_len, GFP_KERNEL);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
buf[i++] = 0;
buf[i++] = 0;
buf[i++] = 0;
/* Capacity List Length */
if ((buf_len > 12) && chip->mspro_formatter_enable &&
(chip->lun2card[lun] & MS_CARD) &&
(!card || (card == MS_CARD))) {
buf[i++] = 0x10;
desc_cnt = 2;
} else {
buf[i++] = 0x08;
desc_cnt = 1;
}
while (desc_cnt) {
if (check_card_ready(chip, lun)) {
card_size = get_card_size(chip, lun);
buf[i++] = (unsigned char)(card_size >> 24);
buf[i++] = (unsigned char)(card_size >> 16);
buf[i++] = (unsigned char)(card_size >> 8);
buf[i++] = (unsigned char)card_size;
if (desc_cnt == 2) {
buf[i++] = 2;
} else {
buf[i++] = 0;
}
} else {
buf[i++] = 0xFF;
buf[i++] = 0xFF;
buf[i++] = 0xFF;
buf[i++] = 0xFF;
if (desc_cnt == 2) {
buf[i++] = 3;
} else {
buf[i++] = 0;
}
}
buf[i++] = 0x00;
buf[i++] = 0x02;
buf[i++] = 0x00;
desc_cnt--;
}
buf_len = min(scsi_bufflen(srb), buf_len);
rtsx_stor_set_xfer_buf(buf, buf_len, srb);
kfree(buf);
scsi_set_resid(srb, scsi_bufflen(srb) - buf_len);
return TRANSPORT_GOOD;
}
static int read_capacity(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned char *buf;
unsigned int lun = SCSI_LUN(srb);
u32 card_size;
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (!(CHK_BIT(chip->lun_mc, lun))) {
SET_BIT(chip->lun_mc, lun);
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
return TRANSPORT_FAILED;
}
buf = kmalloc(8, GFP_KERNEL);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
card_size = get_card_size(chip, lun);
buf[0] = (unsigned char)((card_size - 1) >> 24);
buf[1] = (unsigned char)((card_size - 1) >> 16);
buf[2] = (unsigned char)((card_size - 1) >> 8);
buf[3] = (unsigned char)(card_size - 1);
buf[4] = 0x00;
buf[5] = 0x00;
buf[6] = 0x02;
buf[7] = 0x00;
rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
kfree(buf);
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
static int read_eeprom(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short len, i;
int retval;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len; i++) {
retval = spi_read_eeprom(chip, i, buf + i);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
vfree(buf);
return TRANSPORT_GOOD;
}
static int write_eeprom(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short len, i;
int retval;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (len == 511) {
retval = spi_erase_eeprom_chip(chip);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
buf = (u8 *)vmalloc(len);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
for (i = 0; i < len; i++) {
retval = spi_write_eeprom(chip, i, buf[i]);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
vfree(buf);
}
return TRANSPORT_GOOD;
}
static int read_mem(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr, len, i;
int retval;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = ((u16)srb->cmnd[2] << 8) | srb->cmnd[3];
len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
if (addr < 0xFC00) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len; i++) {
retval = rtsx_read_register(chip, addr + i, buf + i);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
vfree(buf);
return TRANSPORT_GOOD;
}
static int write_mem(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr, len, i;
int retval;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = ((u16)srb->cmnd[2] << 8) | srb->cmnd[3];
len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
if (addr < 0xFC00) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
buf = (u8 *)vmalloc(len);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len; i++) {
retval = rtsx_write_register(chip, addr + i, 0xFF, buf[i]);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
vfree(buf);
return TRANSPORT_GOOD;
}
static int get_sd_csd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
unsigned int lun = SCSI_LUN(srb);
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (get_lun_card(chip, lun) != SD_CARD) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
scsi_set_resid(srb, 0);
rtsx_stor_set_xfer_buf(sd_card->raw_csd, scsi_bufflen(srb), srb);
return TRANSPORT_GOOD;
}
static int toggle_gpio_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
u8 gpio = srb->cmnd[2];
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
if (gpio > 3)
gpio = 1;
toggle_gpio(chip, gpio);
return TRANSPORT_GOOD;
}
#ifdef _MSG_TRACE
static int trace_msg_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned char *ptr, *buf = NULL;
int i, msg_cnt;
u8 clear;
unsigned int buf_len;
buf_len = 4 + ((2 + MSG_FUNC_LEN + MSG_FILE_LEN + TIME_VAL_LEN) * TRACE_ITEM_CNT);
if ((scsi_bufflen(srb) < buf_len) || (scsi_sglist(srb) == NULL)) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
clear = srb->cmnd[2];
buf = (unsigned char *)vmalloc(scsi_bufflen(srb));
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
ptr = buf;
if (chip->trace_msg[chip->msg_idx].valid) {
msg_cnt = TRACE_ITEM_CNT;
} else {
msg_cnt = chip->msg_idx;
}
*(ptr++) = (u8)(msg_cnt >> 24);
*(ptr++) = (u8)(msg_cnt >> 16);
*(ptr++) = (u8)(msg_cnt >> 8);
*(ptr++) = (u8)msg_cnt;
RTSX_DEBUGP("Trace message count is %d\n", msg_cnt);
for (i = 1; i <= msg_cnt; i++) {
int j, idx;
idx = chip->msg_idx - i;
if (idx < 0)
idx += TRACE_ITEM_CNT;
*(ptr++) = (u8)(chip->trace_msg[idx].line >> 8);
*(ptr++) = (u8)(chip->trace_msg[idx].line);
for (j = 0; j < MSG_FUNC_LEN; j++) {
*(ptr++) = chip->trace_msg[idx].func[j];
}
for (j = 0; j < MSG_FILE_LEN; j++) {
*(ptr++) = chip->trace_msg[idx].file[j];
}
for (j = 0; j < TIME_VAL_LEN; j++) {
*(ptr++) = chip->trace_msg[idx].timeval_buf[j];
}
}
rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
vfree(buf);
if (clear) {
chip->msg_idx = 0;
for (i = 0; i < TRACE_ITEM_CNT; i++)
chip->trace_msg[i].valid = 0;
}
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
#endif
static int read_host_reg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
u8 addr, buf[4];
u32 val;
unsigned int len;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = srb->cmnd[4];
val = rtsx_readl(chip, addr);
RTSX_DEBUGP("Host register (0x%x): 0x%x\n", addr, val);
buf[0] = (u8)(val >> 24);
buf[1] = (u8)(val >> 16);
buf[2] = (u8)(val >> 8);
buf[3] = (u8)val;
len = min(scsi_bufflen(srb), (unsigned int)4);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
return TRANSPORT_GOOD;
}
static int write_host_reg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
u8 addr, buf[4];
u32 val;
unsigned int len;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = srb->cmnd[4];
len = min(scsi_bufflen(srb), (unsigned int)4);
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
val = ((u32)buf[0] << 24) | ((u32)buf[1] << 16) | ((u32)buf[2] << 8) | buf[3];
rtsx_writel(chip, addr, val);
return TRANSPORT_GOOD;
}
static int set_variable(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned lun = SCSI_LUN(srb);
if (srb->cmnd[3] == 1) {
/* Variable Clock */
struct xd_info *xd_card = &(chip->xd_card);
struct sd_info *sd_card = &(chip->sd_card);
struct ms_info *ms_card = &(chip->ms_card);
switch (srb->cmnd[4]) {
case XD_CARD:
xd_card->xd_clock = srb->cmnd[5];
break;
case SD_CARD:
sd_card->sd_clock = srb->cmnd[5];
break;
case MS_CARD:
ms_card->ms_clock = srb->cmnd[5];
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else if (srb->cmnd[3] == 2) {
if (srb->cmnd[4]) {
chip->blink_led = 1;
} else {
int retval;
chip->blink_led = 0;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
turn_off_led(chip, LED_GPIO);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return TRANSPORT_GOOD;
}
static int get_variable(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
if (srb->cmnd[3] == 1) {
struct xd_info *xd_card = &(chip->xd_card);
struct sd_info *sd_card = &(chip->sd_card);
struct ms_info *ms_card = &(chip->ms_card);
u8 tmp;
switch (srb->cmnd[4]) {
case XD_CARD:
tmp = (u8)(xd_card->xd_clock);
break;
case SD_CARD:
tmp = (u8)(sd_card->sd_clock);
break;
case MS_CARD:
tmp = (u8)(ms_card->ms_clock);
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_stor_set_xfer_buf(&tmp, 1, srb);
} else if (srb->cmnd[3] == 2) {
u8 tmp = chip->blink_led;
rtsx_stor_set_xfer_buf(&tmp, 1, srb);
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return TRANSPORT_GOOD;
}
static int dma_access_ring_buffer(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval;
unsigned int lun = SCSI_LUN(srb);
u16 len;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
len = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
len = min(len, (u16)scsi_bufflen(srb));
if (srb->sc_data_direction == DMA_FROM_DEVICE) {
RTSX_DEBUGP("Read from device\n");
} else {
RTSX_DEBUGP("Write to device\n");
}
retval = rtsx_transfer_data(chip, 0, scsi_sglist(srb), len,
scsi_sg_count(srb), srb->sc_data_direction, 1000);
if (retval < 0) {
if (srb->sc_data_direction == DMA_FROM_DEVICE) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
}
TRACE_RET(chip, TRANSPORT_FAILED);
}
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
static int get_dev_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
struct ms_info *ms_card = &(chip->ms_card);
int buf_len;
unsigned int lun = SCSI_LUN(srb);
u8 card = get_lun_card(chip, lun);
u8 status[32];
#ifdef SUPPORT_OCP
u8 oc_now_mask = 0, oc_ever_mask = 0;
#endif
memset(status, 0, 32);
status[0] = (u8)(chip->product_id);
status[1] = chip->ic_version;
if (chip->auto_delink_en) {
status[2] = 0x10;
} else {
status[2] = 0x00;
}
status[3] = 20;
status[4] = 10;
status[5] = 05;
status[6] = 21;
if (chip->card_wp) {
status[7] = 0x20;
} else {
status[7] = 0x00;
}
#ifdef SUPPORT_OCP
status[8] = 0;
if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (chip->lun2card[lun] == MS_CARD)) {
oc_now_mask = MS_OC_NOW;
oc_ever_mask = MS_OC_EVER;
} else {
oc_now_mask = SD_OC_NOW;
oc_ever_mask = SD_OC_EVER;
}
if (chip->ocp_stat & oc_now_mask) {
status[8] |= 0x02;
}
if (chip->ocp_stat & oc_ever_mask) {
status[8] |= 0x01;
}
#endif
if (card == SD_CARD) {
if (CHK_SD(sd_card)) {
if (CHK_SD_HCXC(sd_card)) {
if (sd_card->capacity > 0x4000000) {
status[0x0E] = 0x02;
} else {
status[0x0E] = 0x01;
}
} else {
status[0x0E] = 0x00;
}
if (CHK_SD_SDR104(sd_card)) {
status[0x0F] = 0x03;
} else if (CHK_SD_DDR50(sd_card)) {
status[0x0F] = 0x04;
} else if (CHK_SD_SDR50(sd_card)) {
status[0x0F] = 0x02;
} else if (CHK_SD_HS(sd_card)) {
status[0x0F] = 0x01;
} else {
status[0x0F] = 0x00;
}
} else {
if (CHK_MMC_SECTOR_MODE(sd_card)) {
status[0x0E] = 0x01;
} else {
status[0x0E] = 0x00;
}
if (CHK_MMC_DDR52(sd_card)) {
status[0x0F] = 0x03;
} else if (CHK_MMC_52M(sd_card)) {
status[0x0F] = 0x02;
} else if (CHK_MMC_26M(sd_card)) {
status[0x0F] = 0x01;
} else {
status[0x0F] = 0x00;
}
}
} else if (card == MS_CARD) {
if (CHK_MSPRO(ms_card)) {
if (CHK_MSXC(ms_card)) {
status[0x0E] = 0x01;
} else {
status[0x0E] = 0x00;
}
if (CHK_HG8BIT(ms_card)) {
status[0x0F] = 0x01;
} else {
status[0x0F] = 0x00;
}
}
}
#ifdef SUPPORT_SD_LOCK
if (card == SD_CARD) {
status[0x17] = 0x80;
if (sd_card->sd_erase_status)
status[0x17] |= 0x01;
if (sd_card->sd_lock_status & SD_LOCKED) {
status[0x17] |= 0x02;
status[0x07] |= 0x40;
}
if (sd_card->sd_lock_status & SD_PWD_EXIST)
status[0x17] |= 0x04;
} else {
status[0x17] = 0x00;
}
RTSX_DEBUGP("status[0x17] = 0x%x\n", status[0x17]);
#endif
status[0x18] = 0x8A;
status[0x1A] = 0x28;
#ifdef SUPPORT_SD_LOCK
status[0x1F] = 0x01;
#endif
buf_len = min(scsi_bufflen(srb), (unsigned int)sizeof(status));
rtsx_stor_set_xfer_buf(status, buf_len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - buf_len);
return TRANSPORT_GOOD;
}
static int set_chip_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int phy_debug_mode;
int retval;
u16 reg;
if (!CHECK_PID(chip, 0x5208)) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
phy_debug_mode = (int)(srb->cmnd[3]);
if (phy_debug_mode) {
chip->phy_debug_mode = 1;
retval = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_disable_bus_int(chip);
retval = rtsx_read_phy_register(chip, 0x1C, ®);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
reg |= 0x0001;
retval = rtsx_write_phy_register(chip, 0x1C, reg);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
chip->phy_debug_mode = 0;
retval = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0x77);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_enable_bus_int(chip);
retval = rtsx_read_phy_register(chip, 0x1C, ®);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
reg &= 0xFFFE;
retval = rtsx_write_phy_register(chip, 0x1C, reg);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
return TRANSPORT_GOOD;
}
static int rw_mem_cmd_buf(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval = STATUS_SUCCESS;
unsigned int lun = SCSI_LUN(srb);
u8 cmd_type, mask, value, idx;
u16 addr;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
switch (srb->cmnd[3]) {
case INIT_BATCHCMD:
rtsx_init_cmd(chip);
break;
case ADD_BATCHCMD:
cmd_type = srb->cmnd[4];
if (cmd_type > 2) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
addr = (srb->cmnd[5] << 8) | srb->cmnd[6];
mask = srb->cmnd[7];
value = srb->cmnd[8];
rtsx_add_cmd(chip, cmd_type, addr, mask, value);
break;
case SEND_BATCHCMD:
retval = rtsx_send_cmd(chip, 0, 1000);
break;
case GET_BATCHRSP:
idx = srb->cmnd[4];
value = *(rtsx_get_cmd_data(chip) + idx);
if (scsi_bufflen(srb) < 1) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_stor_set_xfer_buf(&value, 1, srb);
scsi_set_resid(srb, 0);
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return TRANSPORT_GOOD;
}
static int suit_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int result;
switch (srb->cmnd[3]) {
case INIT_BATCHCMD:
case ADD_BATCHCMD:
case SEND_BATCHCMD:
case GET_BATCHRSP:
result = rw_mem_cmd_buf(srb, chip);
break;
default:
result = TRANSPORT_ERROR;
}
return result;
}
static int read_phy_register(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr, len, i;
int retval;
u8 *buf;
u16 val;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7];
if (len % 2)
len -= len % 2;
if (len) {
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len / 2; i++) {
retval = rtsx_read_phy_register(chip, addr + i, &val);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
buf[2*i] = (u8)(val >> 8);
buf[2*i+1] = (u8)val;
}
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
vfree(buf);
}
return TRANSPORT_GOOD;
}
static int write_phy_register(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr, len, i;
int retval;
u8 *buf;
u16 val;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7];
if (len % 2)
len -= len % 2;
if (len) {
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
buf = (u8 *)vmalloc(len);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len / 2; i++) {
val = ((u16)buf[2*i] << 8) | buf[2*i+1];
retval = rtsx_write_phy_register(chip, addr + i, val);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
vfree(buf);
}
return TRANSPORT_GOOD;
}
static int erase_eeprom2(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr;
int retval;
u8 mode;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
mode = srb->cmnd[3];
addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
if (mode == 0) {
retval = spi_erase_eeprom_chip(chip);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else if (mode == 1) {
retval = spi_erase_eeprom_byte(chip, addr);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return TRANSPORT_GOOD;
}
static int read_eeprom2(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr, len, i;
int retval;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7];
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len; i++) {
retval = spi_read_eeprom(chip, addr + i, buf + i);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
vfree(buf);
return TRANSPORT_GOOD;
}
static int write_eeprom2(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned short addr, len, i;
int retval;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5];
len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7];
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
buf = (u8 *)vmalloc(len);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len; i++) {
retval = spi_write_eeprom(chip, addr + i, buf[i]);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
vfree(buf);
return TRANSPORT_GOOD;
}
static int read_efuse(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval;
u8 addr, len, i;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = srb->cmnd[4];
len = srb->cmnd[5];
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
for (i = 0; i < len; i++) {
retval = rtsx_read_efuse(chip, addr + i, buf + i);
if (retval != STATUS_SUCCESS) {
vfree(buf);
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
len = (u8)min(scsi_bufflen(srb), (unsigned int)len);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
vfree(buf);
return TRANSPORT_GOOD;
}
static int write_efuse(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval, result = TRANSPORT_GOOD;
u16 val;
u8 addr, len, i;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
addr = srb->cmnd[4];
len = srb->cmnd[5];
len = (u8)min(scsi_bufflen(srb), (unsigned int)len);
buf = (u8 *)vmalloc(len);
if (buf == NULL) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
retval = rtsx_force_power_on(chip, SSC_PDCTL);
if (retval != STATUS_SUCCESS) {
vfree(buf);
TRACE_RET(chip, TRANSPORT_ERROR);
}
if (chip->asic_code) {
retval = rtsx_read_phy_register(chip, 0x08, &val);
if (retval != STATUS_SUCCESS) {
vfree(buf);
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_write_register(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
if (retval != STATUS_SUCCESS) {
vfree(buf);
TRACE_RET(chip, TRANSPORT_ERROR);
}
wait_timeout(600);
retval = rtsx_write_phy_register(chip, 0x08, 0x4C00 | chip->phy_voltage);
if (retval != STATUS_SUCCESS) {
vfree(buf);
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_write_register(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
if (retval != STATUS_SUCCESS) {
vfree(buf);
TRACE_RET(chip, TRANSPORT_ERROR);
}
wait_timeout(600);
}
retval = card_power_on(chip, SPI_CARD);
if (retval != STATUS_SUCCESS) {
vfree(buf);
TRACE_RET(chip, TRANSPORT_ERROR);
}
wait_timeout(50);
for (i = 0; i < len; i++) {
retval = rtsx_write_efuse(chip, addr + i, buf[i]);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
result = TRANSPORT_FAILED;
TRACE_GOTO(chip, Exit);
}
}
Exit:
vfree(buf);
retval = card_power_off(chip, SPI_CARD);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
if (chip->asic_code) {
retval = rtsx_write_register(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
wait_timeout(600);
retval = rtsx_write_phy_register(chip, 0x08, val);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_write_register(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
}
return result;
}
static int read_cfg_byte(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval;
u8 func, func_max;
u16 addr, len;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
func = srb->cmnd[3];
addr = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
len = ((u16)(srb->cmnd[6]) << 8) | srb->cmnd[7];
RTSX_DEBUGP("%s: func = %d, addr = 0x%x, len = %d\n", __func__, func, addr, len);
if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
func_max = 1;
} else {
func_max = 0;
}
if (func > func_max) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
retval = rtsx_read_cfg_seq(chip, func, addr, buf, len);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
vfree(buf);
TRACE_RET(chip, TRANSPORT_FAILED);
}
len = (u16)min(scsi_bufflen(srb), (unsigned int)len);
rtsx_stor_set_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
vfree(buf);
return TRANSPORT_GOOD;
}
static int write_cfg_byte(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval;
u8 func, func_max;
u16 addr, len;
u8 *buf;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
func = srb->cmnd[3];
addr = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
len = ((u16)(srb->cmnd[6]) << 8) | srb->cmnd[7];
RTSX_DEBUGP("%s: func = %d, addr = 0x%x\n", __func__, func, addr);
if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
func_max = 1;
} else {
func_max = 0;
}
if (func > func_max) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
len = (unsigned short)min(scsi_bufflen(srb), (unsigned int)len);
buf = (u8 *)vmalloc(len);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
rtsx_stor_get_xfer_buf(buf, len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - len);
retval = rtsx_write_cfg_seq(chip, func, addr, buf, len);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
vfree(buf);
TRACE_RET(chip, TRANSPORT_FAILED);
}
vfree(buf);
return TRANSPORT_GOOD;
}
static int app_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int result;
switch (srb->cmnd[2]) {
case PP_READ10:
case PP_WRITE10:
result = read_write(srb, chip);
break;
case READ_HOST_REG:
result = read_host_reg(srb, chip);
break;
case WRITE_HOST_REG:
result = write_host_reg(srb, chip);
break;
case GET_VAR:
result = get_variable(srb, chip);
break;
case SET_VAR:
result = set_variable(srb, chip);
break;
case DMA_READ:
case DMA_WRITE:
result = dma_access_ring_buffer(srb, chip);
break;
case READ_PHY:
result = read_phy_register(srb, chip);
break;
case WRITE_PHY:
result = write_phy_register(srb, chip);
break;
case ERASE_EEPROM2:
result = erase_eeprom2(srb, chip);
break;
case READ_EEPROM2:
result = read_eeprom2(srb, chip);
break;
case WRITE_EEPROM2:
result = write_eeprom2(srb, chip);
break;
case READ_EFUSE:
result = read_efuse(srb, chip);
break;
case WRITE_EFUSE:
result = write_efuse(srb, chip);
break;
case READ_CFG:
result = read_cfg_byte(srb, chip);
break;
case WRITE_CFG:
result = write_cfg_byte(srb, chip);
break;
case SET_CHIP_MODE:
result = set_chip_mode(srb, chip);
break;
case SUIT_CMD:
result = suit_cmd(srb, chip);
break;
case GET_DEV_STATUS:
result = get_dev_status(srb, chip);
break;
default:
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return result;
}
static int read_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
u8 rtsx_status[16];
int buf_len;
unsigned int lun = SCSI_LUN(srb);
rtsx_status[0] = (u8)(chip->vendor_id >> 8);
rtsx_status[1] = (u8)(chip->vendor_id);
rtsx_status[2] = (u8)(chip->product_id >> 8);
rtsx_status[3] = (u8)(chip->product_id);
rtsx_status[4] = (u8)lun;
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
if (chip->lun2card[lun] == SD_CARD) {
rtsx_status[5] = 2;
} else {
rtsx_status[5] = 3;
}
} else {
if (chip->card_exist) {
if (chip->card_exist & XD_CARD) {
rtsx_status[5] = 4;
} else if (chip->card_exist & SD_CARD) {
rtsx_status[5] = 2;
} else if (chip->card_exist & MS_CARD) {
rtsx_status[5] = 3;
} else {
rtsx_status[5] = 7;
}
} else {
rtsx_status[5] = 7;
}
}
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
rtsx_status[6] = 2;
} else {
rtsx_status[6] = 1;
}
rtsx_status[7] = (u8)(chip->product_id);
rtsx_status[8] = chip->ic_version;
if (check_card_exist(chip, lun)) {
rtsx_status[9] = 1;
} else {
rtsx_status[9] = 0;
}
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
rtsx_status[10] = 0;
} else {
rtsx_status[10] = 1;
}
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
if (chip->lun2card[lun] == SD_CARD) {
rtsx_status[11] = SD_CARD;
} else {
rtsx_status[11] = MS_CARD;
}
} else {
rtsx_status[11] = XD_CARD | SD_CARD | MS_CARD;
}
if (check_card_ready(chip, lun)) {
rtsx_status[12] = 1;
} else {
rtsx_status[12] = 0;
}
if (get_lun_card(chip, lun) == XD_CARD) {
rtsx_status[13] = 0x40;
} else if (get_lun_card(chip, lun) == SD_CARD) {
struct sd_info *sd_card = &(chip->sd_card);
rtsx_status[13] = 0x20;
if (CHK_SD(sd_card)) {
if (CHK_SD_HCXC(sd_card))
rtsx_status[13] |= 0x04;
if (CHK_SD_HS(sd_card))
rtsx_status[13] |= 0x02;
} else {
rtsx_status[13] |= 0x08;
if (CHK_MMC_52M(sd_card))
rtsx_status[13] |= 0x02;
if (CHK_MMC_SECTOR_MODE(sd_card))
rtsx_status[13] |= 0x04;
}
} else if (get_lun_card(chip, lun) == MS_CARD) {
struct ms_info *ms_card = &(chip->ms_card);
if (CHK_MSPRO(ms_card)) {
rtsx_status[13] = 0x38;
if (CHK_HG8BIT(ms_card))
rtsx_status[13] |= 0x04;
#ifdef SUPPORT_MSXC
if (CHK_MSXC(ms_card))
rtsx_status[13] |= 0x01;
#endif
} else {
rtsx_status[13] = 0x30;
}
} else {
if (CHECK_LUN_MODE(chip, DEFAULT_SINGLE)) {
#ifdef SUPPORT_SDIO
if (chip->sd_io && chip->sd_int) {
rtsx_status[13] = 0x60;
} else {
rtsx_status[13] = 0x70;
}
#else
rtsx_status[13] = 0x70;
#endif
} else {
if (chip->lun2card[lun] == SD_CARD) {
rtsx_status[13] = 0x20;
} else {
rtsx_status[13] = 0x30;
}
}
}
rtsx_status[14] = 0x78;
if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
rtsx_status[15] = 0x83;
} else {
rtsx_status[15] = 0x82;
}
buf_len = min(scsi_bufflen(srb), (unsigned int)sizeof(rtsx_status));
rtsx_stor_set_xfer_buf(rtsx_status, buf_len, srb);
scsi_set_resid(srb, scsi_bufflen(srb) - buf_len);
return TRANSPORT_GOOD;
}
static int get_card_bus_width(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
u8 card, bus_width;
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
card = get_lun_card(chip, lun);
if ((card == SD_CARD) || (card == MS_CARD)) {
bus_width = chip->card_bus_width[lun];
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
TRACE_RET(chip, TRANSPORT_FAILED);
}
scsi_set_resid(srb, 0);
rtsx_stor_set_xfer_buf(&bus_width, scsi_bufflen(srb), srb);
return TRANSPORT_GOOD;
}
static int spi_vendor_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int result;
unsigned int lun = SCSI_LUN(srb);
u8 gpio_dir;
if (CHECK_PID(chip, 0x5208) && CHECK_PID(chip, 0x5288)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
rtsx_force_power_on(chip, SSC_PDCTL);
rtsx_read_register(chip, CARD_GPIO_DIR, &gpio_dir);
rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir & 0x06);
switch (srb->cmnd[2]) {
case SCSI_SPI_GETSTATUS:
result = spi_get_status(srb, chip);
break;
case SCSI_SPI_SETPARAMETER:
result = spi_set_parameter(srb, chip);
break;
case SCSI_SPI_READFALSHID:
result = spi_read_flash_id(srb, chip);
break;
case SCSI_SPI_READFLASH:
result = spi_read_flash(srb, chip);
break;
case SCSI_SPI_WRITEFLASH:
result = spi_write_flash(srb, chip);
break;
case SCSI_SPI_WRITEFLASHSTATUS:
result = spi_write_flash_status(srb, chip);
break;
case SCSI_SPI_ERASEFLASH:
result = spi_erase_flash(srb, chip);
break;
default:
rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir);
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir);
if (result != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
return TRANSPORT_GOOD;
}
static int vendor_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int result;
switch (srb->cmnd[1]) {
case READ_STATUS:
result = read_status(srb, chip);
break;
case READ_MEM:
result = read_mem(srb, chip);
break;
case WRITE_MEM:
result = write_mem(srb, chip);
break;
case READ_EEPROM:
result = read_eeprom(srb, chip);
break;
case WRITE_EEPROM:
result = write_eeprom(srb, chip);
break;
case TOGGLE_GPIO:
result = toggle_gpio_cmd(srb, chip);
break;
case GET_SD_CSD:
result = get_sd_csd(srb, chip);
break;
case GET_BUS_WIDTH:
result = get_card_bus_width(srb, chip);
break;
#ifdef _MSG_TRACE
case TRACE_MSG:
result = trace_msg_cmd(srb, chip);
break;
#endif
case SCSI_APP_CMD:
result = app_cmd(srb, chip);
break;
case SPI_VENDOR_COMMAND:
result = spi_vendor_cmd(srb, chip);
break;
default:
set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return result;
}
#if !defined(LED_AUTO_BLINK) && !defined(REGULAR_BLINK)
void led_shine(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
u16 sec_cnt;
if ((srb->cmnd[0] == READ_10) || (srb->cmnd[0] == WRITE_10)) {
sec_cnt = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
} else if ((srb->cmnd[0] == READ_6) || (srb->cmnd[0] == WRITE_6)) {
sec_cnt = srb->cmnd[4];
} else {
return;
}
if (chip->rw_cap[lun] >= GPIO_TOGGLE_THRESHOLD) {
toggle_gpio(chip, LED_GPIO);
chip->rw_cap[lun] = 0;
} else {
chip->rw_cap[lun] += sec_cnt;
}
}
#endif
static int ms_format_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
unsigned int lun = SCSI_LUN(srb);
int retval, quick_format;
if (get_lun_card(chip, lun) != MS_CARD) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if ((srb->cmnd[3] != 0x4D) || (srb->cmnd[4] != 0x47) ||
(srb->cmnd[5] != 0x66) || (srb->cmnd[6] != 0x6D) ||
(srb->cmnd[7] != 0x74)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
if (!check_card_ready(chip, lun) ||
(get_card_size(chip, lun) == 0)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
if (srb->cmnd[8] & 0x01) {
quick_format = 0;
} else {
quick_format = 1;
}
if (!(chip->card_ready & MS_CARD)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (chip->card_wp & MS_CARD) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_PROTECT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (!CHK_MSPRO(ms_card)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
retval = mspro_format(srb, chip, MS_SHORT_DATA_LEN, quick_format);
if (retval != STATUS_SUCCESS) {
set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED);
TRACE_RET(chip, TRANSPORT_FAILED);
}
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
#ifdef SUPPORT_PCGL_1P18
static int get_ms_information(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
unsigned int lun = SCSI_LUN(srb);
u8 dev_info_id, data_len;
u8 *buf;
unsigned int buf_len;
int i;
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if ((get_lun_card(chip, lun) != MS_CARD)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if ((srb->cmnd[2] != 0xB0) || (srb->cmnd[4] != 0x4D) ||
(srb->cmnd[5] != 0x53) || (srb->cmnd[6] != 0x49) ||
(srb->cmnd[7] != 0x44)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
dev_info_id = srb->cmnd[3];
if ((CHK_MSXC(ms_card) && (dev_info_id == 0x10)) ||
(!CHK_MSXC(ms_card) && (dev_info_id == 0x13)) ||
!CHK_MSPRO(ms_card)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (dev_info_id == 0x15) {
buf_len = data_len = 0x3A;
} else {
buf_len = data_len = 0x6A;
}
buf = kmalloc(buf_len, GFP_KERNEL);
if (!buf) {
TRACE_RET(chip, TRANSPORT_ERROR);
}
i = 0;
/* GET Memory Stick Media Information Response Header */
buf[i++] = 0x00; /* Data length MSB */
buf[i++] = data_len; /* Data length LSB */
/* Device Information Type Code */
if (CHK_MSXC(ms_card)) {
buf[i++] = 0x03;
} else {
buf[i++] = 0x02;
}
/* SGM bit */
buf[i++] = 0x01;
/* Reserved */
buf[i++] = 0x00;
buf[i++] = 0x00;
buf[i++] = 0x00;
/* Number of Device Information */
buf[i++] = 0x01;
/* Device Information Body */
/* Device Information ID Number */
buf[i++] = dev_info_id;
/* Device Information Length */
if (dev_info_id == 0x15) {
data_len = 0x31;
} else {
data_len = 0x61;
}
buf[i++] = 0x00; /* Data length MSB */
buf[i++] = data_len; /* Data length LSB */
/* Valid Bit */
buf[i++] = 0x80;
if ((dev_info_id == 0x10) || (dev_info_id == 0x13)) {
/* System Information */
memcpy(buf+i, ms_card->raw_sys_info, 96);
} else {
/* Model Name */
memcpy(buf+i, ms_card->raw_model_name, 48);
}
rtsx_stor_set_xfer_buf(buf, buf_len, srb);
if (dev_info_id == 0x15) {
scsi_set_resid(srb, scsi_bufflen(srb)-0x3C);
} else {
scsi_set_resid(srb, scsi_bufflen(srb)-0x6C);
}
kfree(buf);
return STATUS_SUCCESS;
}
#endif
static int ms_sp_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
int retval = TRANSPORT_ERROR;
if (srb->cmnd[2] == MS_FORMAT) {
retval = ms_format_cmnd(srb, chip);
}
#ifdef SUPPORT_PCGL_1P18
else if (srb->cmnd[2] == GET_MS_INFORMATION) {
retval = get_ms_information(srb, chip);
}
#endif
return retval;
}
#ifdef SUPPORT_CPRM
static int sd_extention_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
unsigned int lun = SCSI_LUN(srb);
int result;
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
sd_cleanup_work(chip);
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if ((get_lun_card(chip, lun) != SD_CARD)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
switch (srb->cmnd[0]) {
case SD_PASS_THRU_MODE:
result = sd_pass_thru_mode(srb, chip);
break;
case SD_EXECUTE_NO_DATA:
result = sd_execute_no_data(srb, chip);
break;
case SD_EXECUTE_READ:
result = sd_execute_read_data(srb, chip);
break;
case SD_EXECUTE_WRITE:
result = sd_execute_write_data(srb, chip);
break;
case SD_GET_RSP:
result = sd_get_cmd_rsp(srb, chip);
break;
case SD_HW_RST:
result = sd_hw_rst(srb, chip);
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
return result;
}
#endif
#ifdef SUPPORT_MAGIC_GATE
static int mg_report_key(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
unsigned int lun = SCSI_LUN(srb);
int retval;
u8 key_format;
RTSX_DEBUGP("--%s--\n", __func__);
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
ms_cleanup_work(chip);
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if ((get_lun_card(chip, lun) != MS_CARD)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (srb->cmnd[7] != KC_MG_R_PRO) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (!CHK_MSPRO(ms_card)) {
set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
TRACE_RET(chip, TRANSPORT_FAILED);
}
key_format = srb->cmnd[10] & 0x3F;
RTSX_DEBUGP("key_format = 0x%x\n", key_format);
switch (key_format) {
case KF_GET_LOC_EKB:
if ((scsi_bufflen(srb) == 0x41C) &&
(srb->cmnd[8] == 0x04) &&
(srb->cmnd[9] == 0x1C)) {
retval = mg_get_local_EKB(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
case KF_RSP_CHG:
if ((scsi_bufflen(srb) == 0x24) &&
(srb->cmnd[8] == 0x00) &&
(srb->cmnd[9] == 0x24)) {
retval = mg_get_rsp_chg(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
case KF_GET_ICV:
ms_card->mg_entry_num = srb->cmnd[5];
if ((scsi_bufflen(srb) == 0x404) &&
(srb->cmnd[8] == 0x04) &&
(srb->cmnd[9] == 0x04) &&
(srb->cmnd[2] == 0x00) &&
(srb->cmnd[3] == 0x00) &&
(srb->cmnd[4] == 0x00) &&
(srb->cmnd[5] < 32)) {
retval = mg_get_ICV(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
static int mg_send_key(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
unsigned int lun = SCSI_LUN(srb);
int retval;
u8 key_format;
RTSX_DEBUGP("--%s--\n", __func__);
rtsx_disable_aspm(chip);
if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) {
rtsx_exit_ss(chip);
wait_timeout(100);
}
rtsx_set_stat(chip, RTSX_STAT_RUN);
ms_cleanup_work(chip);
if (!check_card_ready(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (check_card_wp(chip, lun)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_PROTECT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if ((get_lun_card(chip, lun) != MS_CARD)) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (srb->cmnd[7] != KC_MG_R_PRO) {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
if (!CHK_MSPRO(ms_card)) {
set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
TRACE_RET(chip, TRANSPORT_FAILED);
}
key_format = srb->cmnd[10] & 0x3F;
RTSX_DEBUGP("key_format = 0x%x\n", key_format);
switch (key_format) {
case KF_SET_LEAF_ID:
if ((scsi_bufflen(srb) == 0x0C) &&
(srb->cmnd[8] == 0x00) &&
(srb->cmnd[9] == 0x0C)) {
retval = mg_set_leaf_id(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
case KF_CHG_HOST:
if ((scsi_bufflen(srb) == 0x0C) &&
(srb->cmnd[8] == 0x00) &&
(srb->cmnd[9] == 0x0C)) {
retval = mg_chg(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
case KF_RSP_HOST:
if ((scsi_bufflen(srb) == 0x0C) &&
(srb->cmnd[8] == 0x00) &&
(srb->cmnd[9] == 0x0C)) {
retval = mg_rsp(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
case KF_SET_ICV:
ms_card->mg_entry_num = srb->cmnd[5];
if ((scsi_bufflen(srb) == 0x404) &&
(srb->cmnd[8] == 0x04) &&
(srb->cmnd[9] == 0x04) &&
(srb->cmnd[2] == 0x00) &&
(srb->cmnd[3] == 0x00) &&
(srb->cmnd[4] == 0x00) &&
(srb->cmnd[5] < 32)) {
retval = mg_set_ICV(srb, chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, TRANSPORT_FAILED);
}
} else {
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
TRACE_RET(chip, TRANSPORT_FAILED);
}
scsi_set_resid(srb, 0);
return TRANSPORT_GOOD;
}
#endif
int rtsx_scsi_handler(struct scsi_cmnd *srb, struct rtsx_chip *chip)
{
#ifdef SUPPORT_SD_LOCK
struct sd_info *sd_card = &(chip->sd_card);
#endif
struct ms_info *ms_card = &(chip->ms_card);
unsigned int lun = SCSI_LUN(srb);
int result;
#ifdef SUPPORT_SD_LOCK
if (sd_card->sd_erase_status) {
/* Block all SCSI command except for
* REQUEST_SENSE and rs_ppstatus
*/
if (!((srb->cmnd[0] == VENDOR_CMND) &&
(srb->cmnd[1] == SCSI_APP_CMD) &&
(srb->cmnd[2] == GET_DEV_STATUS)) &&
(srb->cmnd[0] != REQUEST_SENSE)) {
/* Logical Unit Not Ready Format in Progress */
set_sense_data(chip, lun, CUR_ERR,
0x02, 0, 0x04, 0x04, 0, 0);
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
#endif
if ((get_lun_card(chip, lun) == MS_CARD) &&
(ms_card->format_status == FORMAT_IN_PROGRESS)) {
if ((srb->cmnd[0] != REQUEST_SENSE) && (srb->cmnd[0] != INQUIRY)) {
/* Logical Unit Not Ready Format in Progress */
set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04,
0, (u16)(ms_card->progress));
TRACE_RET(chip, TRANSPORT_FAILED);
}
}
switch (srb->cmnd[0]) {
case READ_10:
case WRITE_10:
case READ_6:
case WRITE_6:
result = read_write(srb, chip);
#if !defined(LED_AUTO_BLINK) && !defined(REGULAR_BLINK)
led_shine(srb, chip);
#endif
break;
case TEST_UNIT_READY:
result = test_unit_ready(srb, chip);
break;
case INQUIRY:
result = inquiry(srb, chip);
break;
case READ_CAPACITY:
result = read_capacity(srb, chip);
break;
case START_STOP:
result = start_stop_unit(srb, chip);
break;
case ALLOW_MEDIUM_REMOVAL:
result = allow_medium_removal(srb, chip);
break;
case REQUEST_SENSE:
result = request_sense(srb, chip);
break;
case MODE_SENSE:
case MODE_SENSE_10:
result = mode_sense(srb, chip);
break;
case 0x23:
result = read_format_capacity(srb, chip);
break;
case VENDOR_CMND:
result = vendor_cmnd(srb, chip);
break;
case MS_SP_CMND:
result = ms_sp_cmnd(srb, chip);
break;
#ifdef SUPPORT_CPRM
case SD_PASS_THRU_MODE:
case SD_EXECUTE_NO_DATA:
case SD_EXECUTE_READ:
case SD_EXECUTE_WRITE:
case SD_GET_RSP:
case SD_HW_RST:
result = sd_extention_cmnd(srb, chip);
break;
#endif
#ifdef SUPPORT_MAGIC_GATE
case CMD_MSPRO_MG_RKEY:
result = mg_report_key(srb, chip);
break;
case CMD_MSPRO_MG_SKEY:
result = mg_send_key(srb, chip);
break;
#endif
case FORMAT_UNIT:
case MODE_SELECT:
case VERIFY:
result = TRANSPORT_GOOD;
break;
default:
set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
result = TRANSPORT_FAILED;
}
return result;
}
| gpl-2.0 |
yajnab/linux-sunxi | drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c | 8020 | 235941 | /******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
/*Created on 2008/11/18, 3: 7*/
#include "r8192E_hwimg.h"
u8 Rtl8192PciEFwBootArray[BootArrayLengthPciE] = {
0x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08,
0x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00,
0x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01,
0x25,0x08,0xa8,0x04,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,
0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b,
0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00,
0x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01,
0x25,0x08,0xa8,0x04,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0,
0x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00,
0x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00,
0x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,
0x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,
0x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01,
0x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24,
0x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10,
0x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,
0x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
0x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10,
0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x4b,0x94,
0x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,};
u8 Rtl8192PciEFwMainArray[MainArrayLengthPciE] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x40,0x04,0x68,0x00,0x40,0x05,0x70,0x00,0x40,0x06,0x40,0x00,0x0c,0x00,0x12,0x98,
0x00,0x00,0x00,0x00,0x40,0x1a,0x68,0x00,0x33,0x5b,0x00,0x3c,0x17,0x60,0x00,0x09,
0x00,0x00,0x00,0x00,0x40,0x1b,0x60,0x00,0x00,0x00,0x00,0x00,0x03,0x5b,0xd0,0x24,
0x40,0x1a,0x70,0x00,0x03,0x40,0x00,0x08,0x42,0x00,0x00,0x10,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0xff,0xff,0x8c,0x43,0x00,0x00,
0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x00,0xd0,
0xac,0x62,0x00,0x00,0x00,0x00,0x20,0x21,0x27,0x85,0x8b,0x70,0x00,0x85,0x18,0x21,
0x24,0x84,0x00,0x01,0x28,0x82,0x00,0x0a,0x14,0x40,0xff,0xfc,0xa0,0x60,0x00,0x00,
0x27,0x82,0x8b,0x7a,0x24,0x04,0x00,0x06,0x24,0x84,0xff,0xff,0xa4,0x40,0x00,0x00,
0x04,0x81,0xff,0xfd,0x24,0x42,0x00,0x02,0x24,0x02,0x00,0x03,0xa3,0x82,0x8b,0x70,
0x24,0x02,0x00,0x0a,0x24,0x03,0x09,0xc4,0xa3,0x82,0x8b,0x72,0x24,0x02,0x00,0x04,
0x24,0x04,0x00,0x01,0x24,0x05,0x00,0x02,0xa7,0x83,0x8b,0x86,0xa3,0x82,0x8b,0x78,
0x24,0x03,0x04,0x00,0x24,0x02,0x02,0x00,0xaf,0x83,0x8b,0x8c,0xa3,0x85,0x8b,0x79,
0xa7,0x82,0x8b,0x7a,0xa7,0x84,0x8b,0x7c,0xaf,0x84,0x8b,0x88,0xa3,0x84,0x8b,0x71,
0xa3,0x80,0x8b,0x73,0xa3,0x80,0x8b,0x74,0xa3,0x80,0x8b,0x75,0xa3,0x84,0x8b,0x76,
0xa3,0x85,0x8b,0x77,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
0x3c,0x02,0x80,0x00,0x24,0x42,0x01,0x7c,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,
0x27,0x84,0x8b,0x98,0x00,0x00,0x10,0x21,0x24,0x42,0x00,0x01,0x00,0x02,0x16,0x00,
0x00,0x02,0x16,0x03,0x28,0x43,0x00,0x03,0xac,0x80,0xff,0xfc,0xa0,0x80,0x00,0x00,
0x14,0x60,0xff,0xf9,0x24,0x84,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x01,0xc0,
0x3c,0x08,0xb0,0x03,0xac,0x62,0x00,0x00,0x35,0x08,0x00,0x70,0x8d,0x02,0x00,0x00,
0x00,0xa0,0x48,0x21,0x00,0x04,0x26,0x00,0x00,0x02,0x2a,0x43,0x00,0x06,0x36,0x00,
0x00,0x07,0x3e,0x00,0x00,0x02,0x12,0x03,0x29,0x23,0x00,0x03,0x00,0x04,0x56,0x03,
0x00,0x06,0x36,0x03,0x00,0x07,0x3e,0x03,0x30,0x48,0x00,0x01,0x10,0x60,0x00,0x11,
0x30,0xa5,0x00,0x07,0x24,0x02,0x00,0x02,0x00,0x49,0x10,0x23,0x00,0x45,0x10,0x07,
0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x66,0x00,0x00,0x00,0x00,0x8f,0xa2,0x00,0x10,
0x00,0x00,0x00,0x00,0x00,0x02,0x21,0x43,0x11,0x00,0x00,0x10,0x00,0x07,0x20,0x0b,
0x15,0x20,0x00,0x06,0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x05,0x34,0x42,0x01,0x20,
0xa4,0x44,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x11,0x22,0x00,0x04,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x24,
0x3c,0x02,0xb0,0x05,0x08,0x00,0x00,0x94,0x34,0x42,0x01,0x22,0x15,0x20,0x00,0x54,
0x24,0x02,0x00,0x01,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x74,0x90,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0x94,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x70,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x6b,0x00,0x08,0x11,0x60,0x00,0x18,
0x00,0x09,0x28,0x40,0x00,0x00,0x40,0x21,0x27,0x85,0x8b,0x90,0x8c,0xa3,0x00,0x00,
0x8c,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x62,0x38,0x23,0x00,0x43,0x10,0x2a,
0x10,0x40,0x00,0x3d,0x00,0x00,0x00,0x00,0xac,0xa7,0x00,0x00,0x25,0x02,0x00,0x01,
0x00,0x02,0x16,0x00,0x00,0x02,0x46,0x03,0x29,0x03,0x00,0x03,0x14,0x60,0xff,0xf3,
0x24,0xa5,0x00,0x0c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x70,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x4b,0x10,0x23,0xa0,0x62,0x00,0x00,0x00,0x09,0x28,0x40,
0x00,0xa9,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x8b,0x98,0x00,0x0a,0x20,0x0b,
0x00,0x43,0x18,0x21,0x10,0xc0,0x00,0x05,0x00,0x00,0x38,0x21,0x80,0x62,0x00,0x01,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x80,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0xa9,0x10,0x21,0x24,0x07,0x00,0x01,
0x00,0xa9,0x10,0x21,0x00,0x02,0x30,0x80,0x27,0x82,0x8b,0x98,0xa0,0x67,0x00,0x01,
0x00,0xc2,0x38,0x21,0x80,0xe3,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x07,
0x00,0x00,0x00,0x00,0x27,0x83,0x8b,0x90,0x00,0xc3,0x18,0x21,0x8c,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x21,0xac,0x62,0x00,0x00,0x27,0x85,0x8b,0x94,
0x27,0x82,0x8b,0x90,0x00,0xc5,0x28,0x21,0x00,0xc2,0x10,0x21,0x8c,0x43,0x00,0x00,
0x8c,0xa4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x2a,0x14,0x60,0x00,0x03,
0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xe2,0x00,0x00,0xa0,0xe0,0x00,0x00,
0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0xb7,0xac,0xa0,0x00,0x00,
0x11,0x22,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x7c,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0xac,0x08,0x00,0x00,0xa7,
0x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x78,0x90,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0xaf,0x83,0x8b,0xa0,0x08,0x00,0x00,0xa7,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x04,0x10,
0x3c,0x05,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0xa5,0x00,0x70,0x8c,0xa2,0x00,0x00,
0x90,0x84,0x00,0x08,0x3c,0x06,0xb0,0x03,0x00,0x02,0x16,0x00,0x2c,0x83,0x00,0x03,
0x34,0xc6,0x00,0x72,0x24,0x07,0x00,0x01,0x10,0x60,0x00,0x11,0x00,0x02,0x2f,0xc2,
0x90,0xc2,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x02,0x16,0x00,0x10,0xa7,0x00,0x09,
0x00,0x02,0x16,0x03,0x14,0x80,0x00,0x0c,0x30,0x43,0x00,0x03,0x83,0x82,0x8b,0x98,
0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x16,0x00,
0x00,0x02,0x1e,0x03,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x72,0xa0,0x43,0x00,0x00,
0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x45,0x00,0x05,0x10,0x87,0x00,0x04,
0x30,0x43,0x00,0x06,0x93,0x82,0x8b,0xb0,0x08,0x00,0x01,0x1f,0x00,0x43,0x10,0x21,
0x83,0x82,0x8b,0xa4,0x00,0x00,0x00,0x00,0x00,0x02,0x10,0x40,0x08,0x00,0x01,0x1f,
0x00,0x45,0x10,0x21,0x10,0x80,0x00,0x05,0x00,0x00,0x18,0x21,0x24,0x63,0x00,0x01,
0x00,0x64,0x10,0x2b,0x14,0x40,0xff,0xfd,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x04,0xe4,
0x3c,0x04,0xb0,0x02,0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x08,
0x24,0x02,0x00,0x01,0xaf,0x84,0x8b,0xc0,0xa3,0x82,0x8b,0xd0,0xa7,0x80,0x8b,0xc4,
0xa7,0x80,0x8b,0xc6,0xaf,0x80,0x8b,0xc8,0xaf,0x80,0x8b,0xcc,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
0x24,0x42,0x05,0x24,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0xac,
0x80,0xa2,0x00,0x15,0x8c,0x83,0x00,0x00,0x27,0xbd,0xff,0xf0,0x00,0x43,0x10,0x21,
0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x10,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,0x24,0x63,0x05,0x5c,0x27,0xbd,0xff,0xe0,
0xac,0x43,0x00,0x00,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,
0x8f,0x90,0x8b,0xc0,0x0c,0x00,0x02,0x98,0x00,0x80,0x88,0x21,0x14,0x40,0x00,0x2a,
0x3c,0x02,0x00,0x80,0x16,0x20,0x00,0x02,0x34,0x42,0x02,0x01,0x24,0x02,0x02,0x01,
0xae,0x02,0x00,0x00,0x97,0x84,0x8b,0xc4,0x97,0x82,0x8b,0xc6,0x3c,0x03,0xb0,0x02,
0x00,0x83,0x20,0x21,0x24,0x42,0x00,0x04,0xa7,0x82,0x8b,0xc6,0xa4,0x82,0x00,0x00,
0x8f,0x84,0x8b,0xc8,0x8f,0x82,0x8b,0xc0,0x93,0x85,0x8b,0x72,0x24,0x84,0x00,0x01,
0x24,0x42,0x00,0x04,0x24,0x03,0x8f,0xff,0x3c,0x07,0xb0,0x06,0x3c,0x06,0xb0,0x03,
0x00,0x43,0x10,0x24,0x00,0x85,0x28,0x2a,0x34,0xe7,0x80,0x18,0xaf,0x82,0x8b,0xc0,
0xaf,0x84,0x8b,0xc8,0x10,0xa0,0x00,0x08,0x34,0xc6,0x01,0x08,0x8f,0x83,0x8b,0xcc,
0x8f,0x84,0x8b,0x8c,0x8c,0xc2,0x00,0x00,0x00,0x64,0x18,0x21,0x00,0x43,0x10,0x2b,
0x14,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x8c,0xe2,0x00,0x00,0x3c,0x03,0x0f,0x00,
0x3c,0x04,0x04,0x00,0x00,0x43,0x10,0x24,0x10,0x44,0x00,0x03,0x00,0x00,0x00,0x00,
0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0x80,0x00,0x24,0x63,0x06,0x48,0xaf,0xb0,0x00,0x10,0x34,0x42,0x00,0x20,
0x8f,0x90,0x8b,0xc0,0xac,0x43,0x00,0x00,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,
0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0x00,0x80,0x88,0x21,0x00,0xa0,0x90,0x21,
0x0c,0x00,0x02,0x98,0x00,0xc0,0x98,0x21,0x24,0x07,0x8f,0xff,0x14,0x40,0x00,0x19,
0x26,0x03,0x00,0x04,0x24,0x02,0x0e,0x03,0xae,0x02,0x00,0x00,0x00,0x67,0x80,0x24,
0x26,0x02,0x00,0x04,0xae,0x11,0x00,0x00,0x00,0x47,0x80,0x24,0x97,0x86,0x8b,0xc4,
0x26,0x03,0x00,0x04,0xae,0x12,0x00,0x00,0x00,0x67,0x80,0x24,0xae,0x13,0x00,0x00,
0x8f,0x84,0x8b,0xc0,0x3c,0x02,0xb0,0x02,0x97,0x85,0x8b,0xc6,0x00,0xc2,0x30,0x21,
0x8f,0x82,0x8b,0xc8,0x24,0x84,0x00,0x10,0x24,0xa5,0x00,0x10,0x00,0x87,0x20,0x24,
0x24,0x42,0x00,0x01,0xa7,0x85,0x8b,0xc6,0xaf,0x84,0x8b,0xc0,0xaf,0x82,0x8b,0xc8,
0xa4,0xc5,0x00,0x00,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,
0x94,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0xe0,0x00,0x14,0x40,0x00,0x14,
0x00,0x00,0x00,0x00,0x90,0x82,0x00,0x02,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfc,
0x00,0x82,0x28,0x21,0x8c,0xa4,0x00,0x00,0x3c,0x02,0x00,0x70,0x8c,0xa6,0x00,0x08,
0x00,0x82,0x10,0x21,0x2c,0x43,0x00,0x06,0x10,0x60,0x00,0x09,0x3c,0x03,0x80,0x01,
0x00,0x02,0x10,0x80,0x24,0x63,0x01,0xe8,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0xaf,0x86,0x80,0x14,
0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
0x8c,0xa4,0x00,0x00,0x0c,0x00,0x17,0x84,0x00,0x00,0x00,0x00,0x08,0x00,0x01,0xdc,
0x00,0x00,0x00,0x00,0x0c,0x00,0x24,0x49,0x00,0xc0,0x20,0x21,0x08,0x00,0x01,0xdc,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,
0x8f,0x82,0x80,0x18,0x3c,0x03,0x00,0x0f,0x34,0x63,0x42,0x40,0x00,0x43,0x10,0x21,
0x00,0x82,0x20,0x2b,0x10,0x80,0x00,0x09,0x24,0x03,0x00,0x05,0x8f,0x82,0x83,0x60,
0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x83,0x60,0x10,0x43,0x00,0x03,
0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
0x8c,0x63,0x01,0x08,0x24,0x02,0x00,0x01,0xa3,0x82,0x80,0x11,0xaf,0x80,0x83,0x60,
0xaf,0x83,0x80,0x18,0x08,0x00,0x01,0xf9,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0xff,
0x14,0x80,0x00,0x2f,0x00,0x00,0x00,0x00,0x8f,0x82,0x80,0x14,0xa3,0x85,0x83,0x93,
0x10,0x40,0x00,0x2b,0x2c,0xa2,0x00,0x04,0x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40,
0x24,0xa2,0xff,0xfc,0x2c,0x42,0x00,0x08,0x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xf0,
0x00,0x05,0x10,0x40,0x27,0x84,0x83,0x9c,0x00,0x44,0x10,0x21,0x94,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0xa4,0x43,0x00,0x00,
0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x0a,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xe0,
0x2c,0x42,0x00,0x10,0x14,0x40,0x00,0x06,0x00,0x05,0x10,0x40,0x24,0xa2,0xff,0xd0,
0x2c,0x42,0x00,0x10,0x10,0x40,0x00,0x09,0x24,0xa2,0xff,0xc0,0x00,0x05,0x10,0x40,
0x27,0x84,0x83,0x9c,0x00,0x44,0x10,0x21,0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00,
0x24,0x63,0x00,0x01,0x03,0xe0,0x00,0x08,0xa4,0x43,0xff,0xf8,0x2c,0x42,0x00,0x10,
0x10,0x40,0x00,0x07,0x00,0x05,0x10,0x40,0x27,0x84,0x83,0x9c,0x00,0x44,0x10,0x21,
0x94,0x43,0xff,0xf8,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0xa4,0x43,0xff,0xf8,
0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0x86,0x8b,0xc0,0x8f,0x82,0x80,0x14,
0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x10,0x40,0x00,0x2a,0x00,0xc0,0x38,0x21,
0x24,0x02,0x00,0x07,0x24,0x03,0xff,0x9c,0xa3,0x82,0x83,0x9b,0xa3,0x83,0x83,0x9a,
0x27,0x8a,0x83,0x98,0x00,0x00,0x20,0x21,0x24,0x09,0x8f,0xff,0x00,0x04,0x10,0x80,
0x00,0x4a,0x28,0x21,0x8c,0xa2,0x00,0x00,0x24,0xe3,0x00,0x04,0x24,0x88,0x00,0x01,
0xac,0xe2,0x00,0x00,0x10,0x80,0x00,0x02,0x00,0x69,0x38,0x24,0xac,0xa0,0x00,0x00,
0x31,0x04,0x00,0xff,0x2c,0x82,0x00,0x27,0x14,0x40,0xff,0xf5,0x00,0x04,0x10,0x80,
0x97,0x83,0x8b,0xc6,0x97,0x85,0x8b,0xc4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x9c,
0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,
0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x9c,
0x3c,0x03,0x0f,0x00,0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,
0xaf,0x86,0x8b,0xc0,0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,
0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x18,0x8f,0x86,0x8b,0xc0,0x27,0xbd,0xff,0xc8,0x24,0x02,0x00,0x08,
0x24,0x03,0x00,0x20,0xaf,0xbf,0x00,0x30,0xa3,0xa2,0x00,0x13,0xa3,0xa3,0x00,0x12,
0xa7,0xa4,0x00,0x10,0x00,0xc0,0x28,0x21,0x27,0xa9,0x00,0x10,0x00,0x00,0x38,0x21,
0x24,0x08,0x8f,0xff,0x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00,
0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,0x24,0xa2,0x00,0x04,0x2c,0xe3,0x00,0x08,
0xac,0xa4,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x48,0x28,0x24,0x97,0x83,0x8b,0xc6,
0x97,0x85,0x8b,0xc4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x20,0x00,0xa2,0x28,0x21,
0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,
0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x20,0x3c,0x03,0x0f,0x00,
0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xc0,
0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,
0x8f,0xbf,0x00,0x30,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,
0x93,0x82,0x8b,0xd0,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11,0x24,0x06,0x00,0x01,
0x8f,0x82,0x8b,0xc8,0x3c,0x05,0xb0,0x06,0x3c,0x04,0xb0,0x03,0x34,0xa5,0x80,0x18,
0x34,0x84,0x01,0x08,0x14,0x40,0x00,0x09,0x00,0x00,0x30,0x21,0x97,0x82,0x8b,0xc4,
0x8c,0x84,0x00,0x00,0x3c,0x03,0xb0,0x02,0x00,0x43,0x10,0x21,0xaf,0x84,0x8b,0xcc,
0xa7,0x80,0x8b,0xc6,0xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0x8c,0xa2,0x00,0x00,
0x03,0xe0,0x00,0x08,0x00,0xc0,0x10,0x21,0x8f,0x86,0x8b,0xc0,0x8f,0x82,0x8b,0xc8,
0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x00,0xc0,0x40,0x21,0x14,0x40,0x00,0x0a,
0x00,0x40,0x50,0x21,0x00,0x00,0x38,0x21,0x27,0x89,0x83,0x68,0x24,0xe2,0x00,0x01,
0x00,0x07,0x18,0x80,0x30,0x47,0x00,0xff,0x00,0x69,0x18,0x21,0x2c,0xe2,0x00,0x0a,
0x14,0x40,0xff,0xfa,0xac,0x60,0x00,0x00,0x3c,0x02,0x00,0x80,0x10,0x82,0x00,0x6f,
0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x6e,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,
0xa7,0x82,0x83,0x6e,0x90,0xa3,0x00,0x15,0x97,0x82,0x83,0x70,0x00,0x03,0x1e,0x00,
0x00,0x03,0x1e,0x03,0x00,0x43,0x10,0x21,0xa7,0x82,0x83,0x70,0x8c,0xa4,0x00,0x20,
0x3c,0x02,0x00,0x60,0x3c,0x03,0x00,0x20,0x00,0x82,0x20,0x24,0x10,0x83,0x00,0x54,
0x00,0x00,0x00,0x00,0x14,0x80,0x00,0x47,0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x74,
0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x74,0x84,0xa3,0x00,0x06,
0x8f,0x82,0x83,0x84,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x84,
0x25,0x42,0x00,0x01,0x28,0x43,0x27,0x10,0xaf,0x82,0x8b,0xc8,0x10,0x60,0x00,0x09,
0x24,0x02,0x00,0x04,0x93,0x83,0x80,0x11,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x05,
0x24,0x02,0x00,0x04,0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x18,0x24,0x03,0x00,0x28,0xa3,0x83,0x83,0x6a,0xa3,0x82,0x83,0x6b,
0x90,0xa2,0x00,0x18,0x93,0x83,0x83,0x93,0x00,0x00,0x38,0x21,0x00,0x02,0x16,0x00,
0x00,0x02,0x16,0x03,0xa7,0x82,0x83,0x7e,0xa3,0x83,0x83,0x8c,0x27,0x89,0x83,0x68,
0x24,0x05,0x8f,0xff,0x00,0x07,0x10,0x80,0x00,0x49,0x10,0x21,0x8c,0x44,0x00,0x00,
0x24,0xe3,0x00,0x01,0x30,0x67,0x00,0xff,0x25,0x02,0x00,0x04,0x2c,0xe3,0x00,0x0a,
0xad,0x04,0x00,0x00,0x14,0x60,0xff,0xf7,0x00,0x45,0x40,0x24,0x97,0x83,0x8b,0xc6,
0x97,0x85,0x8b,0xc4,0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x28,0x00,0xa2,0x28,0x21,
0x3c,0x04,0xb0,0x06,0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,
0x8c,0x85,0x00,0x00,0x24,0x02,0x8f,0xff,0x24,0xc6,0x00,0x28,0x3c,0x03,0x0f,0x00,
0x00,0xc2,0x30,0x24,0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x86,0x8b,0xc0,
0x10,0xa2,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,
0x0c,0x00,0x02,0x36,0x00,0x00,0x00,0x00,0xa3,0x80,0x80,0x11,0x08,0x00,0x02,0xe5,
0x00,0x00,0x00,0x00,0x97,0x82,0x83,0x76,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,
0xa7,0x82,0x83,0x76,0x84,0xa3,0x00,0x06,0x8f,0x82,0x83,0x88,0x00,0x00,0x00,0x00,
0x00,0x43,0x10,0x21,0xaf,0x82,0x83,0x88,0x08,0x00,0x02,0xdd,0x25,0x42,0x00,0x01,
0x97,0x82,0x83,0x72,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x72,
0x84,0xa3,0x00,0x06,0x8f,0x82,0x83,0x80,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,
0xaf,0x82,0x83,0x80,0x08,0x00,0x02,0xdd,0x25,0x42,0x00,0x01,0x97,0x82,0x83,0x6c,
0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xa7,0x82,0x83,0x6c,0x08,0x00,0x02,0xc5,
0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28,0x8c,0xa3,0x00,0x20,
0x8f,0x8a,0x8b,0xc0,0x3c,0x02,0x00,0x10,0x00,0x62,0x10,0x24,0x00,0xa0,0x38,0x21,
0x01,0x40,0x48,0x21,0x10,0x40,0x00,0x3d,0x00,0x80,0x28,0x21,0x8c,0xe4,0x00,0x1c,
0x34,0xa5,0x12,0x06,0xaf,0xa5,0x00,0x10,0x8c,0x82,0x00,0x08,0x00,0x03,0x1c,0x42,
0x30,0x63,0x00,0x30,0x00,0x02,0x13,0x02,0x30,0x42,0x00,0x40,0x00,0x43,0x10,0x25,
0x90,0xe6,0x00,0x10,0x90,0xe4,0x00,0x13,0x94,0xe8,0x00,0x0c,0x94,0xe3,0x00,0x1a,
0x00,0x02,0x16,0x00,0x90,0xe7,0x00,0x12,0x00,0xa2,0x28,0x25,0x24,0x02,0x12,0x34,
0xa7,0xa2,0x00,0x1c,0x24,0x02,0x56,0x78,0xaf,0xa5,0x00,0x10,0xa3,0xa6,0x00,0x18,
0xa3,0xa7,0x00,0x1f,0xa7,0xa3,0x00,0x1a,0xa3,0xa4,0x00,0x19,0xa7,0xa8,0x00,0x20,
0xa7,0xa2,0x00,0x22,0x00,0x00,0x28,0x21,0x27,0xa7,0x00,0x10,0x24,0x06,0x8f,0xff,
0x00,0x05,0x10,0x80,0x00,0x47,0x10,0x21,0x8c,0x44,0x00,0x00,0x24,0xa3,0x00,0x01,
0x30,0x65,0x00,0xff,0x25,0x22,0x00,0x04,0x2c,0xa3,0x00,0x05,0xad,0x24,0x00,0x00,
0x14,0x60,0xff,0xf7,0x00,0x46,0x48,0x24,0x97,0x83,0x8b,0xc6,0x97,0x85,0x8b,0xc4,
0x3c,0x02,0xb0,0x02,0x24,0x63,0x00,0x14,0x00,0xa2,0x28,0x21,0x3c,0x04,0xb0,0x06,
0xa7,0x83,0x8b,0xc6,0x34,0x84,0x80,0x18,0xa4,0xa3,0x00,0x00,0x8c,0x85,0x00,0x00,
0x24,0x02,0x8f,0xff,0x25,0x46,0x00,0x14,0x3c,0x03,0x0f,0x00,0x00,0xc2,0x50,0x24,
0x00,0xa3,0x28,0x24,0x3c,0x02,0x04,0x00,0xaf,0x8a,0x8b,0xc0,0x10,0xa2,0x00,0x03,
0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x28,
0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,0x3c,0x05,0xb0,0x03,
0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xc8,0x00,0x04,0x22,0x00,0x34,0xa5,0x00,0x20,
0x24,0x42,0x0d,0xfc,0x3c,0x03,0xb0,0x00,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,
0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x30,0x00,0x83,0x80,0x21,
0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb3,0x00,0x1c,0xaf,0xb1,0x00,0x14,
0xac,0xa2,0x00,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x90,0x21,0x26,0x10,0x00,0x08,
0x00,0x09,0xa6,0x02,0x12,0x80,0x00,0x13,0x00,0x00,0xa8,0x21,0x24,0x13,0x00,0x02,
0x3c,0x16,0x00,0xff,0x3c,0x17,0xff,0x00,0x8e,0x09,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x09,0x12,0x02,0x24,0x42,0x00,0x02,0x31,0x25,0x00,0xff,0x10,0xb3,0x00,0x76,
0x30,0x51,0x00,0xff,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x18,0x00,0x00,0x00,0x00,
0x02,0x51,0x10,0x21,0x30,0x52,0xff,0xff,0x02,0x54,0x18,0x2b,0x14,0x60,0xff,0xf2,
0x02,0x11,0x80,0x21,0x12,0xa0,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,
0x8c,0x43,0x00,0x00,0x3c,0x04,0x0f,0x00,0x3c,0x02,0x04,0x00,0x00,0x64,0x18,0x24,
0x10,0x62,0x00,0x03,0x00,0x00,0x00,0x00,0x0c,0x00,0x04,0x96,0x00,0x00,0x00,0x00,
0x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,
0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x8e,0x09,0x00,0x04,
0x24,0x15,0x00,0x01,0x8e,0x06,0x00,0x0c,0x00,0x09,0x11,0x42,0x00,0x09,0x18,0xc2,
0x30,0x48,0x00,0x03,0x00,0x09,0x14,0x02,0x30,0x6c,0x00,0x03,0x00,0x09,0x26,0x02,
0x11,0x15,0x00,0x45,0x30,0x43,0x00,0x0f,0x29,0x02,0x00,0x02,0x14,0x40,0x00,0x26,
0x00,0x00,0x00,0x00,0x11,0x13,0x00,0x0f,0x00,0x00,0x38,0x21,0x00,0x07,0x22,0x02,
0x30,0x84,0xff,0x00,0x3c,0x03,0x00,0xff,0x00,0x07,0x2e,0x02,0x00,0x07,0x12,0x00,
0x00,0x43,0x10,0x24,0x00,0xa4,0x28,0x25,0x00,0xa2,0x28,0x25,0x00,0x07,0x1e,0x00,
0x00,0xa3,0x28,0x25,0x0c,0x00,0x01,0x92,0x01,0x20,0x20,0x21,0x08,0x00,0x03,0xa5,
0x02,0x51,0x10,0x21,0x11,0x95,0x00,0x0f,0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x07,
0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x80,0x27,0x83,0x8b,0x70,0x00,0x43,0x10,0x21,
0x8c,0x47,0x00,0x18,0x08,0x00,0x03,0xcc,0x00,0x07,0x22,0x02,0x00,0x04,0x10,0x40,
0x27,0x83,0x8b,0x78,0x00,0x43,0x10,0x21,0x94,0x47,0x00,0x02,0x08,0x00,0x03,0xcc,
0x00,0x07,0x22,0x02,0x27,0x82,0x8b,0x70,0x00,0x82,0x10,0x21,0x90,0x47,0x00,0x00,
0x08,0x00,0x03,0xcc,0x00,0x07,0x22,0x02,0x15,0x00,0xff,0xdc,0x00,0x00,0x38,0x21,
0x10,0x75,0x00,0x05,0x00,0x80,0x38,0x21,0x00,0x65,0x18,0x26,0x24,0x82,0x01,0x00,
0x00,0x00,0x38,0x21,0x00,0x43,0x38,0x0a,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x0e,
0x3c,0x02,0xb0,0x03,0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x06,0x00,0x00,0x00,0x00,
0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x8c,0x47,0x00,0x00,0x08,0x00,0x03,0xcc,
0x00,0x07,0x22,0x02,0x3c,0x02,0xb0,0x03,0x00,0xe2,0x10,0x21,0x94,0x43,0x00,0x00,
0x08,0x00,0x03,0xcb,0x30,0x67,0xff,0xff,0x00,0xe2,0x10,0x21,0x90,0x43,0x00,0x00,
0x08,0x00,0x03,0xcb,0x30,0x67,0x00,0xff,0x30,0x62,0x00,0x03,0x00,0x02,0x12,0x00,
0x11,0x95,0x00,0x07,0x00,0x44,0x38,0x21,0x11,0x93,0x00,0x03,0x00,0x00,0x00,0x00,
0x08,0x00,0x03,0xfd,0x3c,0x02,0xb0,0x0a,0x08,0x00,0x04,0x02,0x3c,0x02,0xb0,0x0a,
0x08,0x00,0x04,0x06,0x3c,0x02,0xb0,0x0a,0x8e,0x09,0x00,0x04,0x8e,0x02,0x00,0x08,
0x8e,0x03,0x00,0x0c,0x00,0x09,0x41,0x42,0x00,0x02,0x22,0x02,0x00,0x03,0x3a,0x02,
0x30,0x84,0xff,0x00,0x30,0xe7,0xff,0x00,0x00,0x02,0x5e,0x02,0x00,0x02,0x32,0x00,
0x00,0x03,0x56,0x02,0x00,0x03,0x2a,0x00,0x01,0x64,0x58,0x25,0x00,0xd6,0x30,0x24,
0x01,0x47,0x50,0x25,0x00,0x02,0x16,0x00,0x00,0xb6,0x28,0x24,0x00,0x03,0x1e,0x00,
0x01,0x66,0x58,0x25,0x01,0x45,0x50,0x25,0x00,0x57,0x10,0x24,0x00,0x77,0x18,0x24,
0x01,0x62,0x38,0x25,0x01,0x43,0x30,0x25,0x00,0x09,0x10,0xc2,0x00,0x09,0x1c,0x02,
0x31,0x08,0x00,0x03,0x30,0x4c,0x00,0x03,0x30,0x63,0x00,0x0f,0x00,0x09,0x26,0x02,
0x00,0xe0,0x58,0x21,0x15,0x00,0x00,0x28,0x00,0xc0,0x50,0x21,0x24,0x02,0x00,0x01,
0x10,0x62,0x00,0x06,0x00,0x80,0x28,0x21,0x24,0x02,0x00,0x03,0x14,0x62,0xff,0x69,
0x02,0x51,0x10,0x21,0x24,0x85,0x01,0x00,0x24,0x02,0x00,0x01,0x11,0x82,0x00,0x15,
0x24,0x02,0x00,0x02,0x11,0x82,0x00,0x0a,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,
0x8c,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,
0x00,0x45,0x10,0x25,0xac,0x62,0x00,0x00,0x08,0x00,0x03,0xa5,0x02,0x51,0x10,0x21,
0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,
0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,0xa4,0x62,0x00,0x00,0x08,0x00,0x03,0xa5,
0x02,0x51,0x10,0x21,0x3c,0x03,0xb0,0x03,0x00,0xa3,0x18,0x21,0x90,0x62,0x00,0x00,
0x00,0x0a,0x20,0x27,0x01,0x6a,0x28,0x24,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,
0x08,0x00,0x03,0xa4,0xa0,0x62,0x00,0x00,0x24,0x02,0x00,0x01,0x11,0x02,0x00,0x21,
0x00,0x00,0x00,0x00,0x15,0x13,0xff,0x42,0x00,0x00,0x00,0x00,0x11,0x82,0x00,0x17,
0x00,0x00,0x00,0x00,0x11,0x88,0x00,0x0b,0x00,0x00,0x00,0x00,0x27,0x83,0x8b,0x70,
0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x18,0x00,0x06,0x18,0x27,
0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa4,
0xac,0x82,0x00,0x18,0x27,0x83,0x8b,0x78,0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x21,
0x94,0x82,0x00,0x02,0x00,0x06,0x18,0x27,0x00,0xe6,0x28,0x24,0x00,0x43,0x10,0x24,
0x00,0x45,0x10,0x25,0x08,0x00,0x03,0xa4,0xa4,0x82,0x00,0x02,0x27,0x83,0x8b,0x70,
0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x5a,
0x00,0xe6,0x28,0x24,0x30,0x62,0x00,0x07,0x00,0x02,0x12,0x00,0x11,0x88,0x00,0x0f,
0x00,0x44,0x10,0x21,0x11,0x93,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x0a,
0x00,0x43,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x47,
0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,0x00,0x43,0x18,0x21,0x94,0x62,0x00,0x00,
0x00,0x06,0x20,0x27,0x08,0x00,0x04,0x50,0x00,0xe6,0x28,0x24,0x3c,0x03,0xb0,0x0a,
0x08,0x00,0x04,0x7d,0x00,0x43,0x18,0x21,0x97,0x85,0x8b,0xc4,0x3c,0x07,0xb0,0x02,
0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x00,0x00,0xa7,0x28,0x21,0x34,0x84,0x00,0x20,
0x24,0x42,0x12,0x58,0x24,0x03,0xff,0x80,0xac,0x82,0x00,0x00,0xa0,0xa3,0x00,0x07,
0x97,0x82,0x8b,0xc6,0x97,0x85,0x8b,0xc4,0x3c,0x06,0xb0,0x06,0x30,0x42,0xff,0xf8,
0x24,0x42,0x00,0x10,0x00,0xa2,0x10,0x21,0x30,0x42,0x0f,0xff,0x24,0x44,0x00,0x08,
0x30,0x84,0x0f,0xff,0x00,0x05,0x28,0xc2,0x3c,0x03,0x00,0x40,0x00,0xa3,0x28,0x25,
0x00,0x87,0x20,0x21,0x34,0xc6,0x80,0x18,0xac,0xc5,0x00,0x00,0xaf,0x84,0x8b,0xc0,
0xa7,0x82,0x8b,0xc4,0xa7,0x80,0x8b,0xc6,0xaf,0x80,0x8b,0xc8,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x30,0x84,0x00,0xff,0x24,0x02,0x00,0x01,
0x00,0xe0,0x48,0x21,0x30,0xc6,0x00,0xff,0x8f,0xa7,0x00,0x10,0x10,0x82,0x00,0x07,
0x00,0xa0,0x40,0x21,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0x03,0x00,0x00,0x00,0x00,
0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0xa8,0x01,0x00,0x3c,0x03,0xb0,0x03,
0x24,0x02,0x00,0x01,0x00,0x07,0x20,0x27,0x01,0x27,0x28,0x24,0x10,0xc2,0x00,0x14,
0x01,0x03,0x18,0x21,0x24,0x02,0x00,0x02,0x10,0xc2,0x00,0x09,0x00,0x07,0x50,0x27,
0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,0x08,0x00,0x04,0xe1,0xac,0x62,0x00,0x00,
0x3c,0x03,0xb0,0x03,0x01,0x03,0x18,0x21,0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x4a,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xa4,0x62,0x00,0x00,
0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x24,0x00,0x45,0x10,0x25,
0xa0,0x62,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0x84,0x00,0x07,
0x00,0x04,0x22,0x00,0x30,0xa5,0x00,0xff,0x00,0x85,0x28,0x21,0x3c,0x02,0xb0,0x0a,
0x00,0xa2,0x40,0x21,0x30,0xc6,0x00,0xff,0x24,0x02,0x00,0x01,0x8f,0xa4,0x00,0x10,
0x10,0xc2,0x00,0x14,0x24,0x02,0x00,0x02,0x00,0x04,0x50,0x27,0x10,0xc2,0x00,0x09,
0x00,0xe4,0x48,0x24,0x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x8c,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08,
0xac,0x62,0x00,0x00,0x3c,0x03,0xb0,0x0a,0x00,0xa3,0x18,0x21,0x94,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x4a,0x10,0x24,0x00,0x49,0x10,0x25,0x03,0xe0,0x00,0x08,
0xa4,0x62,0x00,0x00,0x91,0x02,0x00,0x00,0x00,0x04,0x18,0x27,0x00,0xe4,0x20,0x24,
0x00,0x43,0x10,0x24,0x00,0x44,0x10,0x25,0x03,0xe0,0x00,0x08,0xa1,0x02,0x00,0x00,
0x30,0xa9,0x00,0xff,0x27,0x83,0x8b,0x70,0x30,0x85,0x00,0xff,0x24,0x02,0x00,0x01,
0x00,0x07,0x50,0x27,0x00,0xc7,0x40,0x24,0x11,0x22,0x00,0x17,0x00,0xa3,0x18,0x21,
0x00,0x05,0x20,0x40,0x27,0x82,0x8b,0x70,0x00,0x05,0x28,0x80,0x27,0x83,0x8b,0x78,
0x00,0x83,0x50,0x21,0x00,0xa2,0x20,0x21,0x24,0x02,0x00,0x02,0x00,0x07,0x40,0x27,
0x11,0x22,0x00,0x07,0x00,0xc7,0x28,0x24,0x8c,0x82,0x00,0x18,0x00,0x00,0x00,0x00,
0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x18,
0x95,0x42,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x48,0x10,0x24,0x00,0x45,0x10,0x25,
0x03,0xe0,0x00,0x08,0xa5,0x42,0x00,0x02,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x4a,0x10,0x24,0x00,0x48,0x10,0x25,0x03,0xe0,0x00,0x08,0xa0,0x62,0x00,0x00,
0x00,0x04,0x32,0x02,0x30,0xc6,0xff,0x00,0x00,0x04,0x16,0x02,0x00,0x04,0x1a,0x00,
0x3c,0x05,0x00,0xff,0x00,0x65,0x18,0x24,0x00,0x46,0x10,0x25,0x00,0x43,0x10,0x25,
0x00,0x04,0x26,0x00,0x03,0xe0,0x00,0x08,0x00,0x44,0x10,0x25,0x3c,0x03,0xb0,0x03,
0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,0x24,0x42,0x14,0xdc,
0x3c,0x04,0xb0,0x03,0xaf,0xbf,0x00,0x14,0xac,0x62,0x00,0x00,0xaf,0xb0,0x00,0x10,
0x34,0x84,0x00,0x2c,0x8c,0x83,0x00,0x00,0xa7,0x80,0xbc,0x00,0x00,0x03,0x12,0x02,
0x00,0x03,0x2d,0x02,0x30,0x42,0x0f,0xff,0xa3,0x83,0xbc,0x08,0xa7,0x85,0xbc,0x0c,
0xa7,0x82,0xbc,0x0a,0xa7,0x80,0xbc,0x02,0xa7,0x80,0xbc,0x04,0xa7,0x80,0xbc,0x06,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x05,0x00,0x3c,0x05,0x08,0x00,0x00,0x45,0x28,0x25,
0x24,0x04,0x05,0x00,0x0c,0x00,0x06,0xbf,0x00,0x40,0x80,0x21,0x3c,0x02,0xf7,0xff,
0x34,0x42,0xff,0xff,0x02,0x02,0x80,0x24,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf,
0x24,0x04,0x05,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,0x34,0x42,0x01,0x08,
0x34,0x63,0x01,0x18,0x8c,0x45,0x00,0x00,0x8c,0x64,0x00,0x00,0x3c,0x02,0x00,0x0f,
0x3c,0x03,0x00,0x4c,0x30,0x84,0x02,0x00,0x34,0x63,0x4b,0x40,0xaf,0x85,0xbc,0x10,
0x10,0x80,0x00,0x06,0x34,0x42,0x42,0x40,0xaf,0x83,0xbc,0x14,0x8f,0xbf,0x00,0x14,
0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0xaf,0x82,0xbc,0x14,
0x08,0x00,0x05,0x67,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
0x27,0xbd,0xff,0xc8,0x34,0x63,0x00,0x20,0x24,0x42,0x15,0xb8,0x30,0x84,0x00,0xff,
0xaf,0xbf,0x00,0x30,0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,
0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
0xaf,0xb0,0x00,0x10,0xac,0x62,0x00,0x00,0x10,0x80,0x00,0x1c,0x24,0x02,0x00,0x02,
0x10,0x82,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x30,0x7b,0xb6,0x01,0x7c,
0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x38,0xa7,0x80,0xbc,0x00,0xa7,0x80,0xbc,0x02,0xa7,0x80,0xbc,0x04,
0xa7,0x80,0xbc,0x06,0x0c,0x00,0x06,0xd1,0x24,0x04,0x05,0x00,0x3c,0x05,0x08,0x00,
0x00,0x45,0x28,0x25,0x24,0x04,0x05,0x00,0x0c,0x00,0x06,0xbf,0x00,0x40,0x80,0x21,
0x3c,0x05,0xf7,0xff,0x34,0xa5,0xff,0xff,0x02,0x05,0x28,0x24,0x0c,0x00,0x06,0xbf,
0x24,0x04,0x05,0x00,0x08,0x00,0x05,0x82,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,
0x24,0x04,0x05,0xa0,0x24,0x04,0x05,0xa4,0x0c,0x00,0x06,0xd1,0x00,0x02,0xbc,0x02,
0x24,0x04,0x05,0xa8,0x00,0x02,0xb4,0x02,0x0c,0x00,0x06,0xd1,0x30,0x55,0xff,0xff,
0x00,0x40,0x80,0x21,0x97,0x84,0xbc,0x00,0x97,0x82,0xbc,0x02,0x97,0x83,0xbc,0x06,
0x02,0xe4,0x20,0x23,0x02,0xa2,0x10,0x23,0x00,0x82,0x20,0x21,0x97,0x82,0xbc,0x04,
0x32,0x14,0xff,0xff,0x02,0x83,0x18,0x23,0x02,0xc2,0x10,0x23,0x00,0x82,0x20,0x21,
0x93,0x82,0xbc,0x08,0x00,0x83,0x20,0x21,0x30,0x84,0xff,0xff,0x00,0x82,0x10,0x2b,
0x14,0x40,0x00,0xaa,0x00,0x00,0x00,0x00,0x97,0x82,0xbc,0x0c,0x00,0x00,0x00,0x00,
0x00,0x44,0x10,0x2b,0x14,0x40,0x00,0x7f,0x00,0x00,0x00,0x00,0x97,0x82,0xbc,0x0a,
0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x2b,0x10,0x40,0x00,0x3a,0x00,0x00,0x00,0x00,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,0x00,0x40,0x80,0x21,
0x2e,0x22,0x00,0x32,0x10,0x40,0x00,0x13,0x24,0x02,0x00,0x20,0x12,0x22,0x00,0x17,
0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,0x26,0x31,0x00,0x01,0x00,0x51,0x80,0x25,
0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x50,0x02,0x00,0x28,0x21,
0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x58,0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf,
0x24,0x04,0x04,0x60,0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x68,0x0c,0x00,0x06,0xbf,
0x00,0x00,0x00,0x00,0xa7,0x97,0xbc,0x00,0xa7,0x95,0xbc,0x02,0xa7,0x96,0xbc,0x04,
0xa7,0x94,0xbc,0x06,0x08,0x00,0x05,0x82,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,
0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,
0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,0x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,
0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,
0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c,
0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,
0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x2c,0x08,0x00,0x05,0xc9,
0x24,0x02,0xff,0x80,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,
0x24,0x02,0x00,0x20,0x16,0x22,0xff,0xdb,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,
0x24,0x04,0x02,0x2c,0x34,0x52,0x40,0x00,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,
0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x58,0x24,0x04,0x02,0x5c,
0x0c,0x00,0x06,0xd1,0x00,0x02,0x9e,0x02,0x30,0x43,0x00,0xff,0x00,0x13,0x12,0x00,
0x00,0x43,0x10,0x25,0x2c,0x43,0x00,0x04,0x14,0x60,0x00,0x1d,0x2c,0x42,0x00,0x11,
0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,
0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xbf,
0x36,0x52,0x80,0x00,0x02,0x40,0x28,0x21,0x08,0x00,0x05,0xd7,0x24,0x04,0x02,0x2c,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,0x00,0x40,0x28,0x21,
0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x02,0x14,0x43,0xff,0xee,
0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,
0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08,0x08,0x00,0x06,0x13,0x3c,0x02,0xff,0xff,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,
0x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,0x14,0x43,0xff,0xdf,0x3c,0x02,0xff,0x3f,
0x34,0x42,0xff,0xff,0x00,0xa2,0x10,0x24,0x3c,0x03,0x00,0x80,0x08,0x00,0x06,0x28,
0x00,0x43,0x28,0x25,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x50,0x30,0x51,0x00,0x7f,
0x00,0x40,0x80,0x21,0x2e,0x22,0x00,0x32,0x10,0x40,0xff,0x9a,0x24,0x02,0x00,0x20,
0x12,0x22,0x00,0x04,0x24,0x02,0xff,0x80,0x02,0x02,0x10,0x24,0x08,0x00,0x05,0xcb,
0x26,0x31,0x00,0x02,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,
0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x03,
0x10,0x43,0x00,0x07,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c,0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,
0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,
0x24,0x04,0x02,0x2c,0x08,0x00,0x06,0x42,0x24,0x02,0xff,0x80,0x0c,0x00,0x06,0xd1,
0x24,0x04,0x04,0x50,0x00,0x40,0x80,0x21,0x30,0x51,0x00,0x7f,0x24,0x02,0x00,0x20,
0x12,0x22,0x00,0x1d,0x2e,0x22,0x00,0x21,0x14,0x40,0xff,0x72,0x24,0x02,0xff,0x80,
0x02,0x02,0x10,0x24,0x26,0x31,0xff,0xff,0x00,0x51,0x80,0x25,0x24,0x04,0x04,0x50,
0x0c,0x00,0x06,0xbf,0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x58,0x0c,0x00,0x06,0xbf,
0x02,0x00,0x28,0x21,0x24,0x04,0x04,0x60,0x0c,0x00,0x06,0xbf,0x02,0x00,0x28,0x21,
0x02,0x00,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x68,0x24,0x02,0x00,0x20,
0x16,0x22,0xff,0x60,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c,
0x00,0x40,0x90,0x21,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x10,0x24,
0x08,0x00,0x06,0x19,0x34,0x52,0x80,0x00,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x2c,
0x34,0x52,0x40,0x00,0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x2c,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x58,0x24,0x04,0x02,0x5c,0x0c,0x00,0x06,0xd1,
0x00,0x02,0x9e,0x02,0x30,0x43,0x00,0xff,0x00,0x13,0x12,0x00,0x00,0x43,0x10,0x25,
0x2c,0x43,0x00,0x04,0x14,0x60,0x00,0x20,0x2c,0x42,0x00,0x11,0x10,0x40,0x00,0x0d,
0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0xff,0x34,0x42,0x3f,0xff,0x02,0x42,0x90,0x24,
0x02,0x40,0x28,0x21,0x24,0x04,0x02,0x2c,0x0c,0x00,0x06,0xbf,0x36,0x52,0x80,0x00,
0x02,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x2c,0x08,0x00,0x06,0x66,
0x2e,0x22,0x00,0x21,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,0x3c,0x04,0x00,0xc0,
0x00,0x40,0x28,0x21,0x00,0x44,0x10,0x24,0x00,0x02,0x15,0x82,0x24,0x03,0x00,0x02,
0x14,0x43,0xff,0xec,0x00,0x00,0x00,0x00,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
0x00,0xa2,0x10,0x24,0x00,0x44,0x28,0x25,0x0c,0x00,0x06,0xbf,0x24,0x04,0x02,0x08,
0x08,0x00,0x06,0x96,0x3c,0x02,0xff,0xff,0x0c,0x00,0x06,0xd1,0x24,0x04,0x02,0x08,
0x00,0x40,0x28,0x21,0x00,0x02,0x15,0x82,0x30,0x42,0x00,0x03,0x24,0x03,0x00,0x03,
0x14,0x43,0xff,0xdc,0x3c,0x03,0x00,0x80,0x3c,0x02,0xff,0x3f,0x34,0x42,0xff,0xff,
0x00,0xa2,0x10,0x24,0x08,0x00,0x06,0xae,0x00,0x43,0x28,0x25,0x30,0x83,0x00,0x03,
0x00,0x04,0x20,0x40,0x00,0x83,0x20,0x23,0x3c,0x02,0xb0,0x0a,0x00,0x82,0x20,0x21,
0x3c,0x06,0x00,0x01,0xac,0x85,0x00,0x00,0x24,0x07,0x00,0x01,0x00,0x00,0x28,0x21,
0x34,0xc6,0x86,0x9f,0x8c,0x82,0x10,0x00,0x24,0xa5,0x00,0x01,0x10,0x47,0x00,0x03,
0x00,0xc5,0x18,0x2b,0x10,0x60,0xff,0xfb,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x30,0x83,0x00,0x03,0x00,0x04,0x20,0x40,0x3c,0x02,0xb0,0x0a,
0x00,0x83,0x20,0x23,0x00,0x82,0x20,0x21,0x3c,0x06,0x00,0x01,0x24,0x02,0xff,0xff,
0xac,0x82,0x10,0x00,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x01,0x34,0xc6,0x86,0x9f,
0x8c,0x82,0x10,0x00,0x24,0xa5,0x00,0x01,0x10,0x47,0x00,0x03,0x00,0xc5,0x18,0x2b,
0x10,0x60,0xff,0xfb,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x1b,0x94,
0x24,0x03,0x00,0x01,0x34,0xa5,0x00,0x20,0x3c,0x06,0xb0,0x03,0xac,0xa2,0x00,0x00,
0x34,0xc6,0x01,0x04,0xa0,0x83,0x00,0x48,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,
0xa0,0x80,0x00,0x06,0xa0,0x80,0x00,0x07,0xa0,0x80,0x00,0x08,0xa0,0x80,0x00,0x09,
0xa0,0x80,0x00,0x0a,0xa0,0x80,0x00,0x11,0xa0,0x80,0x00,0x13,0xa0,0x80,0x00,0x49,
0x94,0xc2,0x00,0x00,0xac,0x80,0x00,0x00,0xa0,0x80,0x00,0x4e,0x00,0x02,0x14,0x00,
0x00,0x02,0x14,0x03,0x30,0x43,0x00,0xff,0x30,0x42,0xff,0x00,0xa4,0x82,0x00,0x44,
0xa4,0x83,0x00,0x46,0xac,0x80,0x00,0x24,0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,
0xac,0x80,0x00,0x30,0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xac,0x80,0x00,0x3c,
0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x40,0x84,0x83,0x00,0x0c,0x3c,0x07,0xb0,0x03,
0x34,0xe7,0x00,0x20,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
0x27,0x83,0x90,0x04,0x00,0x43,0x10,0x21,0x8c,0x48,0x00,0x18,0x3c,0x02,0x80,0x00,
0x24,0x42,0x1c,0x28,0xac,0xe2,0x00,0x00,0x8d,0x03,0x00,0x08,0x80,0x82,0x00,0x13,
0x00,0x05,0x2c,0x00,0x00,0x03,0x1e,0x02,0x00,0x02,0x12,0x00,0x30,0x63,0x00,0x7e,
0x00,0x62,0x18,0x21,0x00,0x65,0x18,0x21,0x3c,0x02,0xc0,0x00,0x3c,0x05,0xb0,0x05,
0x34,0x42,0x04,0x00,0x24,0x63,0x00,0x01,0x3c,0x07,0xb0,0x05,0x3c,0x08,0xb0,0x05,
0x34,0xa5,0x04,0x20,0xac,0xa3,0x00,0x00,0x00,0xc2,0x30,0x21,0x34,0xe7,0x04,0x24,
0x35,0x08,0x02,0x28,0x24,0x02,0x00,0x01,0x24,0x03,0x00,0x20,0xac,0xe6,0x00,0x00,
0xac,0x82,0x00,0x3c,0x03,0xe0,0x00,0x08,0xa1,0x03,0x00,0x00,0x27,0xbd,0xff,0xa8,
0x00,0x07,0x60,0x80,0x27,0x82,0xb4,0x00,0xaf,0xbe,0x00,0x50,0xaf,0xb7,0x00,0x4c,
0xaf,0xb5,0x00,0x44,0xaf,0xb4,0x00,0x40,0xaf,0xbf,0x00,0x54,0xaf,0xb6,0x00,0x48,
0xaf,0xb3,0x00,0x3c,0xaf,0xb2,0x00,0x38,0xaf,0xb1,0x00,0x34,0xaf,0xb0,0x00,0x30,
0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0xe0,0x70,0x21,0x3c,0x02,0x80,0x00,
0x94,0x73,0x00,0x14,0x3c,0x07,0xb0,0x03,0x34,0xe7,0x00,0x20,0x24,0x42,0x1c,0xbc,
0x3c,0x03,0xb0,0x05,0xac,0xe2,0x00,0x00,0x34,0x63,0x01,0x28,0x90,0x67,0x00,0x00,
0x00,0x13,0xa8,0xc0,0x02,0xb3,0x18,0x21,0x27,0x82,0x90,0x04,0x00,0x03,0x18,0x80,
0x00,0x62,0x18,0x21,0x00,0x05,0x2c,0x00,0x00,0x07,0x3e,0x00,0x28,0xc2,0x00,0x03,
0x00,0xc0,0xa0,0x21,0x00,0x80,0x78,0x21,0x00,0x05,0xbc,0x03,0x8c,0x68,0x00,0x18,
0x02,0xa0,0x58,0x21,0x10,0x40,0x01,0x81,0x00,0x07,0xf6,0x03,0x00,0xde,0x10,0x07,
0x30,0x5e,0x00,0x01,0x01,0x73,0x10,0x21,0x27,0x83,0x90,0x08,0x00,0x02,0x10,0x80,
0x00,0x43,0x10,0x21,0x80,0x4d,0x00,0x06,0x8d,0x03,0x00,0x00,0x8d,0x02,0x00,0x04,
0x8d,0x0a,0x00,0x08,0x8d,0x03,0x00,0x0c,0xaf,0xa2,0x00,0x20,0x11,0xa0,0x01,0x71,
0xaf,0xa3,0x00,0x18,0x27,0x82,0xb4,0x00,0x01,0x82,0x10,0x21,0x8c,0x44,0x00,0x00,
0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x04,
0x14,0x60,0x00,0x12,0x00,0x00,0xb0,0x21,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x46,
0x90,0x43,0x00,0x00,0x2a,0x84,0x00,0x04,0x10,0x80,0x01,0x56,0x30,0x65,0x00,0x01,
0x91,0xe2,0x00,0x09,0x00,0x00,0x00,0x00,0x12,0x82,0x00,0x02,0x00,0x00,0x00,0x00,
0x00,0x00,0x28,0x21,0x14,0xa0,0x00,0x03,0x00,0x00,0x38,0x21,0x13,0xc0,0x00,0x03,
0x38,0xf6,0x00,0x01,0x24,0x07,0x00,0x01,0x38,0xf6,0x00,0x01,0x01,0x73,0x10,0x21,
0x00,0x02,0x30,0x80,0x27,0x83,0x90,0x10,0x00,0xc3,0x48,0x21,0x91,0x25,0x00,0x00,
0x8f,0xa4,0x00,0x20,0x2c,0xa3,0x00,0x04,0x00,0x04,0x11,0xc3,0x30,0x42,0x00,0x01,
0x00,0x03,0xb0,0x0b,0x12,0xc0,0x00,0xd8,0xaf,0xa2,0x00,0x24,0x93,0x90,0xbb,0xea,
0x00,0x0a,0x16,0x42,0x30,0x52,0x00,0x3f,0x2e,0x06,0x00,0x0c,0x10,0xc0,0x00,0xc0,
0x00,0xa0,0x20,0x21,0x2c,0xa2,0x00,0x10,0x14,0x40,0x00,0x04,0x00,0x90,0x10,0x2b,
0x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x04,0x00,0x90,0x10,0x2b,0x10,0x40,0x00,0x0b,
0x01,0x73,0x10,0x21,0x27,0x85,0xbb,0x1c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21,
0x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b,
0x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x01,0x73,0x10,0x21,0x00,0x02,0x10,0x80,
0x27,0x83,0x90,0x08,0x00,0x43,0x10,0x21,0x31,0xa4,0x00,0x01,0x10,0x80,0x00,0xa5,
0xa0,0x50,0x00,0x07,0x3c,0x04,0xb0,0x05,0x34,0x84,0x00,0x08,0x24,0x02,0x00,0x01,
0x3c,0x03,0x80,0x00,0xa1,0xe2,0x00,0x4e,0xac,0x83,0x00,0x00,0x8c,0x85,0x00,0x00,
0x3c,0x02,0x00,0xf0,0x3c,0x03,0x40,0xf0,0x34,0x42,0xf0,0x00,0x34,0x63,0xf0,0x00,
0x24,0x17,0x00,0x0e,0x24,0x13,0x01,0x06,0xac,0x82,0x00,0x00,0xac,0x83,0x00,0x00,
0x27,0x82,0xb4,0x00,0x01,0x82,0x10,0x21,0x8c,0x43,0x00,0x00,0x24,0x05,0x00,0x01,
0xaf,0xa5,0x00,0x1c,0x90,0x62,0x00,0x16,0x00,0x13,0xa8,0xc0,0x32,0x51,0x00,0x02,
0x34,0x42,0x00,0x04,0xa0,0x62,0x00,0x16,0x8f,0xa3,0x00,0x20,0x8f,0xa4,0x00,0x18,
0x00,0x03,0x13,0x43,0x00,0x04,0x1a,0x02,0x30,0x47,0x00,0x01,0x12,0x20,0x00,0x04,
0x30,0x64,0x07,0xff,0x2e,0x03,0x00,0x04,0x32,0x42,0x00,0x33,0x00,0x43,0x90,0x0b,
0x8f,0xa5,0x00,0x24,0x8f,0xa6,0x00,0x1c,0x00,0x12,0x10,0x40,0x00,0x05,0x19,0xc0,
0x00,0x47,0x10,0x21,0x00,0x06,0x2a,0x80,0x00,0x43,0x10,0x21,0x00,0x10,0x32,0x00,
0x00,0x04,0x24,0x80,0x02,0x65,0x28,0x21,0x00,0xa4,0x28,0x21,0x00,0x46,0x10,0x21,
0x00,0x17,0x1c,0x00,0x3c,0x04,0xc0,0x00,0x00,0x43,0x30,0x21,0x16,0x80,0x00,0x29,
0x00,0xa4,0x28,0x21,0x3c,0x02,0xb0,0x05,0x34,0x42,0x04,0x00,0x3c,0x03,0xb0,0x05,
0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x04,0x34,0x84,0x02,0x28,
0x24,0x02,0x00,0x01,0xac,0x65,0x00,0x00,0xa0,0x82,0x00,0x00,0x3c,0x02,0xb0,0x09,
0x34,0x42,0x01,0x46,0x90,0x44,0x00,0x00,0x91,0xe3,0x00,0x09,0x30,0x86,0x00,0x01,
0x02,0x83,0x18,0x26,0x00,0x03,0x30,0x0b,0x14,0xc0,0x00,0x03,0x00,0x00,0x28,0x21,
0x13,0xc0,0x00,0x03,0x02,0xb3,0x10,0x21,0x24,0x05,0x00,0x01,0x02,0xb3,0x10,0x21,
0x27,0x83,0x90,0x08,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x84,0x48,0x00,0x04,
0x00,0xa0,0x30,0x21,0x00,0xe0,0x20,0x21,0x02,0x80,0x28,0x21,0x02,0xc0,0x38,0x21,
0x0c,0x00,0x00,0x70,0xaf,0xa8,0x00,0x10,0x7b,0xbe,0x02,0xbc,0x7b,0xb6,0x02,0x7c,
0x7b,0xb4,0x02,0x3c,0x7b,0xb2,0x01,0xfc,0x7b,0xb0,0x01,0xbc,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x58,0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x3d,0x3c,0x02,0xb0,0x05,
0x24,0x02,0x00,0x02,0x12,0x82,0x00,0x31,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x03,
0x12,0x82,0x00,0x25,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,0x12,0x82,0x00,0x19,
0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x11,0x12,0x82,0x00,0x0d,0x3c,0x02,0xb0,0x05,
0x24,0x02,0x00,0x12,0x16,0x82,0xff,0xd1,0x3c,0x02,0xb0,0x05,0x3c,0x03,0xb0,0x05,
0x34,0x42,0x04,0x20,0x3c,0x04,0xb0,0x05,0x34,0x63,0x04,0x24,0xac,0x46,0x00,0x00,
0x34,0x84,0x02,0x28,0xac,0x65,0x00,0x00,0x08,0x00,0x07,0xe6,0x24,0x02,0x00,0x20,
0x34,0x42,0x04,0x40,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,
0x34,0x63,0x04,0x44,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x40,0x08,0x00,0x07,0xe6,
0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x28,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,
0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x2c,0x34,0x84,0x02,0x28,0x24,0x02,0xff,0x80,
0x08,0x00,0x07,0xe6,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x18,0x3c,0x03,0xb0,0x05,
0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x1c,0x34,0x84,0x02,0x28,
0x24,0x02,0x00,0x08,0x08,0x00,0x07,0xe6,0xac,0x65,0x00,0x00,0x34,0x42,0x04,0x10,
0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,0x34,0x63,0x04,0x14,
0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x04,0x08,0x00,0x07,0xe6,0xac,0x65,0x00,0x00,
0x34,0x42,0x04,0x08,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0xac,0x46,0x00,0x00,
0x34,0x63,0x04,0x0c,0x34,0x84,0x02,0x28,0x24,0x02,0x00,0x02,0x08,0x00,0x07,0xe6,
0xac,0x65,0x00,0x00,0x24,0x17,0x00,0x14,0x08,0x00,0x07,0xb8,0x24,0x13,0x01,0x02,
0x30,0xa2,0x00,0x07,0x24,0x44,0x00,0x0c,0x00,0x90,0x18,0x2b,0x10,0x60,0x00,0x0c,
0x26,0x02,0x00,0x04,0x27,0x85,0xbb,0x1c,0x00,0x10,0x10,0x40,0x00,0x50,0x10,0x21,
0x00,0x45,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x18,0x2b,
0x14,0x60,0xff,0xfa,0x00,0x10,0x10,0x40,0x2e,0x06,0x00,0x0c,0x26,0x02,0x00,0x04,
0x08,0x00,0x07,0xa2,0x00,0x46,0x80,0x0a,0x27,0x82,0xb4,0x00,0x01,0x82,0x20,0x21,
0x8c,0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0xe2,0x00,0x19,0x00,0x00,0x00,0x00,
0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x27,0x82,0x90,0x20,0x00,0xc2,0x10,0x21,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x00,0x14,0x00,0x00,0x00,0x00,
0x90,0xe3,0x00,0x16,0x27,0x82,0x90,0x08,0x00,0xc2,0x10,0x21,0x34,0x63,0x00,0x20,
0x90,0x50,0x00,0x07,0xa0,0xe3,0x00,0x16,0x8c,0x84,0x00,0x00,0x00,0x0a,0x1e,0x42,
0x24,0x06,0x00,0x01,0x90,0x82,0x00,0x16,0x30,0x71,0x00,0x02,0x30,0x72,0x00,0x3f,
0x30,0x42,0x00,0xfb,0x24,0x17,0x00,0x18,0x24,0x13,0x01,0x03,0x24,0x15,0x08,0x18,
0xaf,0xa6,0x00,0x1c,0x08,0x00,0x07,0xc2,0xa0,0x82,0x00,0x16,0x8d,0x02,0x00,0x04,
0x00,0x0a,0x1c,0x42,0x30,0x42,0x00,0x10,0x14,0x40,0x00,0x15,0x30,0x72,0x00,0x3f,
0x81,0x22,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x11,0x30,0x72,0x00,0x3e,
0x27,0x83,0x90,0x18,0x00,0xc3,0x18,0x21,0x80,0x64,0x00,0x00,0x27,0x83,0xb5,0x78,
0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x05,0x90,0x43,0x00,0x04,
0x00,0x00,0x00,0x00,0x00,0x64,0x18,0x24,0x30,0x63,0x00,0x01,0x02,0x43,0x90,0x25,
0x27,0x85,0xb4,0x00,0x01,0x85,0x28,0x21,0x8c,0xa6,0x00,0x00,0x01,0x73,0x10,0x21,
0x27,0x83,0x90,0x10,0x90,0xc4,0x00,0x16,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
0x30,0x84,0x00,0xdf,0x90,0x50,0x00,0x00,0xa0,0xc4,0x00,0x16,0x80,0xc6,0x00,0x12,
0x8c,0xa3,0x00,0x00,0x2d,0xc4,0x00,0x02,0xaf,0xa6,0x00,0x1c,0x90,0x62,0x00,0x16,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfb,0x14,0x80,0x00,0x06,0xa0,0x62,0x00,0x16,
0x24,0x02,0x00,0x06,0x11,0xc2,0x00,0x03,0x24,0x02,0x00,0x04,0x15,0xc2,0xff,0x0e,
0x32,0x51,0x00,0x02,0x32,0x51,0x00,0x02,0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x0f,
0x00,0x11,0x18,0x2b,0x32,0x02,0x00,0x0f,0x34,0x42,0x00,0x10,0x00,0x03,0x19,0x00,
0x00,0x43,0x18,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xe0,0xa0,0x43,0x00,0x00,
0x00,0x00,0x20,0x21,0x02,0x00,0x28,0x21,0x0c,0x00,0x02,0x03,0xaf,0xaf,0x00,0x28,
0x8f,0xaf,0x00,0x28,0x08,0x00,0x07,0xc2,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0xbd,
0x32,0x03,0x00,0xff,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x42,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0x14,0x40,0xfe,0xaa,0x00,0x00,0x00,0x00,
0x91,0xe2,0x00,0x09,0x00,0x00,0x00,0x00,0x02,0x82,0x10,0x26,0x08,0x00,0x07,0x79,
0x00,0x02,0x28,0x0b,0x08,0x00,0x07,0x7f,0x00,0x00,0xb0,0x21,0x24,0x02,0x00,0x10,
0x10,0xc2,0x00,0x08,0x24,0x02,0x00,0x11,0x10,0xc2,0xfe,0x7d,0x00,0x07,0x17,0x83,
0x24,0x02,0x00,0x12,0x14,0xc2,0xfe,0x7b,0x00,0x07,0x17,0x43,0x08,0x00,0x07,0x59,
0x30,0x5e,0x00,0x01,0x08,0x00,0x07,0x59,0x00,0x07,0xf7,0xc2,0x00,0x04,0x10,0x40,
0x27,0x83,0x80,0x1c,0x00,0x43,0x10,0x21,0x00,0x80,0x40,0x21,0x94,0x44,0x00,0x00,
0x2d,0x07,0x00,0x04,0x24,0xc2,0x00,0x03,0x00,0x47,0x30,0x0a,0x00,0x86,0x00,0x18,
0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x23,0x8c,
0xac,0x62,0x00,0x00,0x2d,0x06,0x00,0x10,0x00,0x00,0x20,0x12,0x00,0x04,0x22,0x42,
0x24,0x84,0x00,0x01,0x24,0x83,0x00,0xc0,0x10,0xe0,0x00,0x0b,0x24,0x82,0x00,0x60,
0x00,0x40,0x20,0x21,0x00,0x65,0x20,0x0a,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00,
0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x00,0x44,0x20,0x04,
0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x24,0x85,0x00,0x28,0x24,0x83,0x00,0x24,
0x31,0x02,0x00,0x08,0x14,0xc0,0xff,0xf4,0x24,0x84,0x00,0x14,0x00,0x60,0x20,0x21,
0x08,0x00,0x08,0xfa,0x00,0xa2,0x20,0x0b,0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x03,
0x3c,0x02,0x80,0x00,0xaf,0xb0,0x00,0x10,0x24,0x42,0x24,0x28,0x00,0x80,0x80,0x21,
0x34,0x63,0x00,0x20,0x3c,0x04,0xb0,0x03,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
0xaf,0xbf,0x00,0x1c,0x83,0xb1,0x00,0x33,0x83,0xa8,0x00,0x37,0x34,0x84,0x01,0x10,
0xac,0x62,0x00,0x00,0x2e,0x02,0x00,0x10,0x00,0xe0,0x90,0x21,0x8c,0x87,0x00,0x00,
0x14,0x40,0x00,0x0c,0x2e,0x02,0x00,0x0c,0x3c,0x02,0x00,0x0f,0x34,0x42,0xf0,0x00,
0x00,0xe2,0x10,0x24,0x14,0x40,0x00,0x37,0x32,0x02,0x00,0x08,0x32,0x02,0x00,0x07,
0x27,0x83,0x80,0xcc,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,0x00,0x00,0x00,0x00,
0x2e,0x02,0x00,0x0c,0x14,0x40,0x00,0x03,0x02,0x00,0x20,0x21,0x32,0x02,0x00,0x0f,
0x24,0x44,0x00,0x0c,0x00,0x87,0x10,0x06,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x07,
0x2c,0x82,0x00,0x0c,0x00,0x04,0x10,0x80,0x27,0x83,0xb4,0x50,0x00,0x43,0x10,0x21,
0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x82,0x00,0x0c,0x14,0x40,0x00,0x05,
0x00,0x05,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x82,0x10,0x21,
0x24,0x44,0x00,0x04,0x15,0x00,0x00,0x02,0x24,0x06,0x00,0x20,0x24,0x06,0x00,0x0e,
0x0c,0x00,0x08,0xe3,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0x3c,0x02,0xb0,0x03,
0x34,0x42,0x01,0x00,0x90,0x43,0x00,0x00,0x2e,0x04,0x00,0x04,0x24,0x02,0x00,0x10,
0x24,0x05,0x00,0x0a,0x00,0x44,0x28,0x0a,0x30,0x63,0x00,0x01,0x14,0x60,0x00,0x02,
0x00,0x05,0x10,0x40,0x00,0xa0,0x10,0x21,0x30,0x45,0x00,0xff,0x00,0xc5,0x10,0x21,
0x24,0x46,0x00,0x46,0x02,0x26,0x18,0x04,0xa6,0x43,0x00,0x00,0x8f,0xbf,0x00,0x1c,
0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0xc0,0x10,0x21,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x20,0x10,0x40,0xff,0xcf,0x2e,0x02,0x00,0x0c,0x32,0x02,0x00,0x07,
0x27,0x83,0x80,0xc4,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,0x08,0x00,0x09,0x28,
0x02,0x04,0x80,0x23,0x27,0xbd,0xff,0xb8,0x00,0x05,0x38,0x80,0x27,0x82,0xb4,0x00,
0xaf,0xbe,0x00,0x40,0xaf,0xb6,0x00,0x38,0xaf,0xb3,0x00,0x2c,0xaf,0xbf,0x00,0x44,
0xaf,0xb7,0x00,0x3c,0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xb2,0x00,0x28,
0xaf,0xb1,0x00,0x24,0xaf,0xb0,0x00,0x20,0x00,0xe2,0x38,0x21,0x8c,0xe6,0x00,0x00,
0xaf,0xa5,0x00,0x4c,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20,
0x24,0x42,0x25,0x84,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,0xa0,0xc3,0x00,0x12,
0x8c,0xe5,0x00,0x00,0x94,0xc3,0x00,0x06,0x90,0xa2,0x00,0x16,0xa4,0xc3,0x00,0x14,
0x27,0x83,0x90,0x00,0x34,0x42,0x00,0x08,0xa0,0xa2,0x00,0x16,0x8c,0xe8,0x00,0x00,
0xaf,0xa4,0x00,0x48,0x27,0x82,0x90,0x04,0x95,0x11,0x00,0x14,0x00,0x00,0x00,0x00,
0x00,0x11,0x98,0xc0,0x02,0x71,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x82,0x10,0x21,
0x8c,0x52,0x00,0x18,0x00,0x83,0x18,0x21,0x84,0x75,0x00,0x06,0x8e,0x45,0x00,0x08,
0x8e,0x46,0x00,0x04,0x8e,0x47,0x00,0x04,0x00,0x05,0x1c,0x82,0x00,0x06,0x31,0x42,
0x27,0x82,0x90,0x10,0x30,0x63,0x00,0x01,0x30,0xc6,0x00,0x01,0x00,0x82,0x20,0x21,
0xa5,0x15,0x00,0x1a,0x00,0x05,0x14,0x42,0xaf,0xa3,0x00,0x18,0xaf,0xa6,0x00,0x1c,
0x30,0xe7,0x00,0x10,0x30,0x56,0x00,0x01,0x80,0x97,0x00,0x06,0x14,0xe0,0x00,0x47,
0x00,0x05,0xf7,0xc2,0x80,0x82,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x44,
0x02,0x71,0x10,0x21,0x93,0x90,0xbb,0xe9,0x00,0x00,0x00,0x00,0x2e,0x02,0x00,0x0c,
0x14,0x40,0x00,0x06,0x02,0x00,0x20,0x21,0x00,0x16,0x10,0x40,0x00,0x43,0x10,0x21,
0x00,0x02,0x11,0x00,0x02,0x02,0x10,0x21,0x24,0x44,0x00,0x04,0x02,0x71,0x10,0x21,
0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0x00,0x80,0x80,0x21,
0xa0,0x44,0x00,0x03,0xa0,0x44,0x00,0x00,0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,
0x0c,0x00,0x08,0xe3,0x02,0xa0,0x30,0x21,0x02,0x71,0x18,0x21,0x00,0x03,0x88,0x80,
0x00,0x40,0xa0,0x21,0x27,0x82,0x90,0x20,0x02,0x22,0x10,0x21,0x8c,0x44,0x00,0x00,
0x26,0xe3,0x00,0x02,0x00,0x03,0x17,0xc2,0x00,0x62,0x18,0x21,0x00,0x04,0x25,0xc2,
0x00,0x03,0x18,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x18,0x40,0x03,0xc4,0x20,0x24,
0x14,0x80,0x00,0x15,0x02,0x43,0x38,0x21,0x3c,0x08,0xb0,0x03,0x35,0x08,0x00,0x28,
0x8d,0x03,0x00,0x00,0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x48,0x27,0x82,0x90,0x08,
0x02,0x22,0x10,0x21,0x24,0x63,0x00,0x01,0x02,0xa0,0x28,0x21,0xa4,0x54,0x00,0x04,
0x00,0xc0,0x38,0x21,0x0c,0x00,0x07,0x2f,0xad,0x03,0x00,0x00,0x7b,0xbe,0x02,0x3c,
0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,0x8f,0xa2,0x00,0x1c,0x8f,0xa6,0x00,0x18,
0x02,0x00,0x20,0x21,0x02,0xc0,0x28,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0x0a,
0xaf,0xa0,0x00,0x14,0x08,0x00,0x09,0xc6,0x02,0x82,0xa0,0x21,0x02,0x71,0x10,0x21,
0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0x90,0x50,0x00,0x00,
0x08,0x00,0x09,0xb2,0xa0,0x50,0x00,0x03,0x27,0xbd,0xff,0xb8,0xaf,0xb1,0x00,0x24,
0x8f,0xb1,0x00,0x5c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
0x24,0x42,0x27,0xa8,0xaf,0xbe,0x00,0x40,0xaf,0xb7,0x00,0x3c,0xaf,0xb6,0x00,0x38,
0xaf,0xb5,0x00,0x34,0xaf,0xb4,0x00,0x30,0xaf,0xa5,0x00,0x4c,0x8f,0xb5,0x00,0x58,
0xaf,0xbf,0x00,0x44,0xaf,0xb3,0x00,0x2c,0xaf,0xb2,0x00,0x28,0xaf,0xb0,0x00,0x20,
0x00,0xe0,0xb0,0x21,0xac,0x62,0x00,0x00,0x00,0x80,0xf0,0x21,0x00,0x00,0xb8,0x21,
0x16,0x20,0x00,0x2b,0x00,0x00,0xa0,0x21,0x27,0x85,0xb4,0x00,0x00,0x07,0x10,0x80,
0x00,0x45,0x10,0x21,0x8c,0x53,0x00,0x00,0x00,0x15,0x18,0x80,0x00,0x65,0x18,0x21,
0x92,0x62,0x00,0x16,0x8c,0x72,0x00,0x00,0x30,0x42,0x00,0x03,0x14,0x40,0x00,0x2d,
0x00,0x00,0x00,0x00,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x03,
0x14,0x40,0x00,0x28,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,
0x14,0x40,0x00,0x18,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x38,0x00,0x00,0x00,0x00,
0x14,0x40,0x00,0x14,0x02,0x20,0x10,0x21,0x8c,0x82,0x00,0x3c,0x00,0x00,0x00,0x00,
0x14,0x40,0x00,0x0f,0x3c,0x03,0xb0,0x09,0x3c,0x05,0xb0,0x05,0x34,0x63,0x01,0x44,
0x34,0xa5,0x02,0x52,0x94,0x66,0x00,0x00,0x90,0xa2,0x00,0x00,0x8f,0xa3,0x00,0x4c,
0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x04,
0x30,0xc6,0xff,0xff,0x2c,0xc2,0x00,0x41,0x10,0x40,0x00,0x09,0x24,0x05,0x00,0x14,
0x02,0x20,0x10,0x21,0x7b,0xbe,0x02,0x3c,0x7b,0xb6,0x01,0xfc,0x7b,0xb4,0x01,0xbc,
0x7b,0xb2,0x01,0x7c,0x7b,0xb0,0x01,0x3c,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x48,
0x0c,0x00,0x07,0x0a,0x24,0x06,0x01,0x07,0x24,0x02,0x00,0x01,0x08,0x00,0x0a,0x2c,
0xa3,0xc2,0x00,0x11,0x10,0xc0,0x00,0x1c,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x17,
0x00,0xc0,0x88,0x21,0x96,0x54,0x00,0x1a,0x02,0xa0,0xb8,0x21,0x12,0x20,0xff,0xed,
0x02,0x20,0x10,0x21,0x27,0x83,0xb4,0x00,0x00,0x17,0x10,0x80,0x00,0x43,0x10,0x21,
0x8c,0x44,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x28,0x80,0x86,0x00,0x12,
0x8c,0x62,0x00,0x00,0x00,0x14,0x2c,0x00,0x00,0x05,0x2c,0x03,0x00,0x46,0x10,0x21,
0x8f,0xa6,0x00,0x4c,0x02,0xe0,0x38,0x21,0x03,0xc0,0x20,0x21,0x0c,0x00,0x07,0x2f,
0xac,0x62,0x00,0x00,0x08,0x00,0x0a,0x2c,0xaf,0xd1,0x00,0x40,0x96,0x74,0x00,0x1a,
0x08,0x00,0x0a,0x3f,0x02,0xc0,0xb8,0x21,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,
0x8c,0x50,0x00,0x00,0x02,0x60,0x20,0x21,0x0c,0x00,0x1e,0xf3,0x02,0x00,0x28,0x21,
0x30,0x42,0x00,0xff,0x02,0x00,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x1e,0xf3,
0xaf,0xa2,0x00,0x18,0x8f,0xa4,0x00,0x18,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0xed,
0x30,0x50,0x00,0xff,0x12,0x00,0x00,0x18,0x24,0x11,0x00,0x01,0x96,0x63,0x00,0x14,
0x96,0x44,0x00,0x14,0x27,0x85,0x90,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x00,0x04,0x18,0xc0,0x8c,0x46,0x00,0x08,
0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x00,0x06,0x17,0x02,
0x24,0x04,0x00,0xff,0x8c,0x63,0x00,0x08,0x10,0x44,0x00,0xd6,0x00,0x03,0x17,0x02,
0x10,0x44,0x00,0xd5,0x3c,0x02,0x80,0x00,0x00,0x66,0x18,0x2b,0x24,0x11,0x00,0x02,
0x24,0x02,0x00,0x01,0x00,0x43,0x88,0x0a,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x5a,
0x24,0x02,0x00,0x02,0x16,0x22,0xff,0xbd,0x00,0x00,0x00,0x00,0x96,0x49,0x00,0x14,
0x27,0x82,0x90,0x04,0x02,0xa0,0xb8,0x21,0x00,0x09,0x50,0xc0,0x01,0x49,0x18,0x21,
0x00,0x03,0x40,0x80,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,0x00,0x00,0x00,0x00,
0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,0x00,0x05,0x24,0x42,
0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,0x14,0x40,0x00,0x41,
0x30,0x87,0x00,0x01,0x27,0x82,0x90,0x18,0x01,0x02,0x10,0x21,0x80,0x44,0x00,0x00,
0x27,0x82,0xb5,0x78,0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,
0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05,
0x27,0x84,0xb4,0xa0,0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2b,
0x2c,0x64,0x00,0x0c,0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00,
0x00,0x62,0x10,0x21,0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xe1,
0x14,0x80,0x00,0x06,0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,
0x00,0x02,0x11,0x00,0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,
0x27,0x83,0x90,0x10,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21,
0xa0,0x45,0x00,0x03,0xa0,0x45,0x00,0x00,0x24,0x02,0x00,0x08,0x12,0x02,0x00,0x0b,
0x24,0x02,0x00,0x01,0x00,0x60,0x28,0x21,0x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x6f,
0xaf,0xa2,0x00,0x10,0x30,0x54,0xff,0xff,0x92,0x42,0x00,0x16,0x00,0x00,0x00,0x00,
0x02,0x02,0x10,0x25,0x08,0x00,0x0a,0x3f,0xa2,0x42,0x00,0x16,0x00,0x60,0x28,0x21,
0x02,0x40,0x20,0x21,0x0c,0x00,0x1f,0x20,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0a,0xc2,
0x30,0x54,0xff,0xff,0x08,0x00,0x0a,0xaa,0x00,0x60,0x10,0x21,0x14,0x80,0xff,0xfd,
0x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x08,0x00,0x0a,0xaa,
0x24,0x42,0x00,0x04,0x27,0x82,0x90,0x10,0x01,0x02,0x10,0x21,0x90,0x43,0x00,0x00,
0x08,0x00,0x0a,0xba,0xa0,0x43,0x00,0x03,0x96,0x69,0x00,0x14,0x02,0xc0,0xb8,0x21,
0x24,0x0b,0x00,0x01,0x00,0x09,0x10,0xc0,0x00,0x49,0x18,0x21,0x00,0x03,0x40,0x80,
0x00,0x40,0x50,0x21,0x27,0x82,0x90,0x04,0x01,0x02,0x10,0x21,0x8c,0x43,0x00,0x18,
0x00,0x00,0x00,0x00,0x8c,0x65,0x00,0x08,0x8c,0x62,0x00,0x0c,0x8c,0x62,0x00,0x04,
0x00,0x05,0x24,0x42,0x00,0x05,0x1c,0x82,0x30,0x42,0x00,0x10,0x30,0x66,0x00,0x01,
0x10,0x40,0x00,0x0d,0x30,0x87,0x00,0x01,0x27,0x82,0x90,0x18,0x01,0x02,0x10,0x21,
0x80,0x43,0x00,0x00,0x00,0x00,0x58,0x21,0x00,0x03,0x11,0x00,0x00,0x43,0x10,0x23,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x23,0x00,0x02,0x10,0x80,0x27,0x83,0xb5,0x70,
0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x04,0x11,0x60,0x00,0x4f,0x00,0x00,0x00,0x00,
0x01,0x49,0x10,0x21,0x00,0x02,0x20,0x80,0x27,0x85,0x90,0x10,0x00,0x85,0x10,0x21,
0x80,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x42,0x01,0x49,0x10,0x21,
0x27,0x82,0x90,0x18,0x00,0x82,0x10,0x21,0x80,0x44,0x00,0x00,0x27,0x82,0xb5,0x78,
0x00,0x04,0x19,0x00,0x00,0x64,0x18,0x23,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x23,
0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x90,0x45,0x00,0x05,0x27,0x84,0xb4,0xa0,
0x00,0x64,0x18,0x21,0x90,0x63,0x00,0x00,0x10,0xa0,0x00,0x2c,0x2c,0x64,0x00,0x0c,
0x14,0x80,0x00,0x04,0x00,0x60,0x10,0x21,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,
0x24,0x42,0x00,0x24,0x3c,0x01,0xb0,0x03,0xa0,0x22,0x00,0xe1,0x14,0x80,0x00,0x06,
0x00,0x60,0x28,0x21,0x00,0x07,0x10,0x40,0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,
0x00,0x62,0x10,0x21,0x24,0x45,0x00,0x04,0x01,0x49,0x10,0x21,0x27,0x83,0x90,0x10,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0xa0,0x18,0x21,0xa0,0x45,0x00,0x03,
0xa0,0x45,0x00,0x00,0x8f,0xa4,0x00,0x18,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x0c,
0x00,0x60,0x28,0x21,0x24,0x02,0x00,0x01,0x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x6f,
0xaf,0xa2,0x00,0x10,0x8f,0xa3,0x00,0x18,0x30,0x54,0xff,0xff,0x92,0x62,0x00,0x16,
0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x25,0x08,0x00,0x0a,0x3f,0xa2,0x62,0x00,0x16,
0x02,0x60,0x20,0x21,0x0c,0x00,0x1f,0x20,0xaf,0xa0,0x00,0x10,0x08,0x00,0x0b,0x31,
0x00,0x00,0x00,0x00,0x08,0x00,0x0b,0x19,0x00,0x60,0x10,0x21,0x14,0x80,0xff,0xfd,
0x00,0x00,0x00,0x00,0x00,0x06,0x11,0x00,0x00,0x62,0x10,0x21,0x08,0x00,0x0b,0x19,
0x24,0x42,0x00,0x04,0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x90,0x43,0x00,0x00,
0x08,0x00,0x0b,0x29,0xa0,0x43,0x00,0x03,0x27,0x85,0x90,0x10,0x08,0x00,0x0b,0x45,
0x01,0x49,0x10,0x21,0x3c,0x02,0x80,0x00,0x00,0x62,0x18,0x26,0x08,0x00,0x0a,0x7a,
0x00,0xc2,0x30,0x26,0x12,0x00,0xff,0x2d,0x24,0x02,0x00,0x01,0x08,0x00,0x0a,0x7f,
0x24,0x11,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0,
0x24,0x42,0x2d,0x54,0x34,0x63,0x00,0x20,0x3c,0x05,0xb0,0x05,0xaf,0xb3,0x00,0x24,
0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x28,0xaf,0xb0,0x00,0x18,
0xac,0x62,0x00,0x00,0x34,0xa5,0x02,0x42,0x90,0xa2,0x00,0x00,0x00,0x80,0x90,0x21,
0x24,0x11,0x00,0x10,0x30,0x53,0x00,0xff,0x24,0x02,0x00,0x10,0x12,0x22,0x00,0xcf,
0x00,0x00,0x18,0x21,0x24,0x02,0x00,0x11,0x12,0x22,0x00,0xc1,0x24,0x02,0x00,0x12,
0x12,0x22,0x00,0xb4,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0xad,0xae,0x43,0x00,0x40,
0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x44,0x00,0x00,0x3c,0x03,0x00,0x02,
0x34,0x63,0x00,0xff,0x00,0x83,0x80,0x24,0x00,0x10,0x14,0x43,0x10,0x40,0x00,0x05,
0x00,0x00,0x00,0x00,0x8e,0x42,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x92,
0x00,0x00,0x00,0x00,0x93,0x83,0x8b,0x71,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,
0x10,0x40,0x00,0x04,0x32,0x10,0x00,0xff,0x00,0x10,0x11,0xc3,0x14,0x40,0x00,0x86,
0x00,0x00,0x00,0x00,0x16,0x00,0x00,0x15,0x02,0x00,0x10,0x21,0x26,0x22,0x00,0x01,
0x30,0x51,0x00,0xff,0x2e,0x23,0x00,0x13,0x14,0x60,0xff,0xdb,0x24,0x03,0x00,0x02,
0x12,0x63,0x00,0x73,0x24,0x02,0x00,0x05,0x2a,0x62,0x00,0x03,0x10,0x40,0x00,0x58,
0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x62,0x00,0x4b,0x02,0x40,0x20,0x21,
0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x70,0x00,0xff,0x12,0x00,0x00,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x28,
0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,0x24,0x02,0x00,0x07,0x02,0x40,0x20,0x21,
0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea,
0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x24,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xec,0x02,0x00,0x10,0x21,
0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x24,0x02,0x00,0x05,0x02,0x40,0x20,0x21,
0x24,0x05,0x00,0x01,0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea,
0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x28,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xdc,0x02,0x00,0x10,0x21,
0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,0x24,0x02,0x00,0x03,0x02,0x40,0x20,0x21,
0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea,
0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x2c,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
0x00,0x00,0x00,0x00,0x30,0x50,0x00,0xff,0x16,0x00,0xff,0xcc,0x02,0x00,0x10,0x21,
0x92,0x46,0x00,0x07,0x8e,0x43,0x00,0x30,0x24,0x02,0x00,0x02,0x02,0x40,0x20,0x21,
0x24,0x05,0x00,0x03,0x24,0x07,0x00,0x01,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea,
0xaf,0xa3,0x00,0x14,0xae,0x42,0x00,0x30,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x02,0x2c,
0x08,0x00,0x0b,0x9b,0x30,0x42,0x00,0xff,0x92,0x46,0x00,0x04,0x8e,0x43,0x00,0x24,
0x24,0x02,0x00,0x07,0x00,0x00,0x28,0x21,0x24,0x07,0x00,0x06,0xaf,0xa2,0x00,0x10,
0x0c,0x00,0x09,0xea,0xaf,0xa3,0x00,0x14,0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x24,
0x12,0x62,0x00,0x0d,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x08,0x16,0x62,0xff,0xa8,
0x02,0x40,0x20,0x21,0x92,0x46,0x00,0x07,0x8e,0x42,0x00,0x30,0x24,0x05,0x00,0x03,
0x24,0x07,0x00,0x01,0xaf,0xa3,0x00,0x10,0x0c,0x00,0x09,0xea,0xaf,0xa2,0x00,0x14,
0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x30,0x92,0x46,0x00,0x06,0x8e,0x43,0x00,0x2c,
0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x02,0x00,0x00,0x38,0x21,0xaf,0xa2,0x00,0x10,
0x0c,0x00,0x09,0xea,0xaf,0xa3,0x00,0x14,0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x2c,
0x92,0x46,0x00,0x05,0x8e,0x43,0x00,0x28,0x02,0x40,0x20,0x21,0x24,0x05,0x00,0x01,
0x24,0x07,0x00,0x04,0xaf,0xa2,0x00,0x10,0x0c,0x00,0x09,0xea,0xaf,0xa3,0x00,0x14,
0x08,0x00,0x0b,0x94,0xae,0x42,0x00,0x28,0x0c,0x00,0x01,0x57,0x24,0x04,0x00,0x01,
0x08,0x00,0x0b,0x85,0x00,0x00,0x00,0x00,0x8f,0x84,0xb4,0x40,0xae,0x40,0x00,0x34,
0x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x66,0x00,0x00,0x00,0x00,0x93,0x83,0x8b,0x71,
0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x02,0x10,0x40,0xff,0x69,0x00,0x00,0x00,0x00,
0x0c,0x00,0x01,0x57,0x00,0x00,0x20,0x21,0x08,0x00,0x0b,0x7d,0x00,0x00,0x00,0x00,
0x02,0x40,0x20,0x21,0x0c,0x00,0x09,0x61,0x02,0x20,0x28,0x21,0x08,0x00,0x0b,0x71,
0x3c,0x02,0xb0,0x05,0x8e,0x42,0x00,0x3c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x4a,
0x00,0x00,0x00,0x00,0x8f,0x82,0xb4,0x48,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,
0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,0x08,0x00,0x0b,0x6e,0xae,0x43,0x00,0x3c,
0x8e,0x42,0x00,0x38,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x3d,0x24,0x02,0x00,0x12,
0x8f,0x82,0xb4,0x44,0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,
0x00,0x02,0x18,0x2b,0x08,0x00,0x0b,0x6e,0xae,0x43,0x00,0x38,0x8e,0x42,0x00,0x34,
0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x30,0x24,0x02,0x00,0x11,0x8f,0x82,0xb4,0x40,
0x00,0x00,0x00,0x00,0x90,0x42,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x2b,
0x08,0x00,0x0b,0x6e,0xae,0x43,0x00,0x34,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
0x27,0xbd,0xff,0xe0,0x34,0x63,0x00,0x20,0x24,0x42,0x31,0x08,0x3c,0x08,0xb0,0x03,
0xaf,0xb1,0x00,0x14,0xac,0x62,0x00,0x00,0x35,0x08,0x01,0x00,0xaf,0xbf,0x00,0x18,
0xaf,0xb0,0x00,0x10,0x91,0x03,0x00,0x00,0x00,0xa0,0x48,0x21,0x24,0x11,0x00,0x0a,
0x2c,0xa5,0x00,0x04,0x24,0x02,0x00,0x10,0x00,0x45,0x88,0x0a,0x30,0x63,0x00,0x01,
0x00,0xc0,0x28,0x21,0x14,0x60,0x00,0x02,0x00,0x11,0x40,0x40,0x02,0x20,0x40,0x21,
0x84,0x83,0x00,0x0c,0x31,0x11,0x00,0xff,0x01,0x20,0x20,0x21,0x00,0x03,0x10,0xc0,
0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x08,0x00,0x43,0x10,0x21,
0x84,0x43,0x00,0x04,0x24,0x06,0x00,0x0e,0x10,0xe0,0x00,0x06,0x02,0x23,0x80,0x21,
0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x20,0x0c,0x00,0x08,0xe3,0x00,0x00,0x00,0x00,0x02,0x11,0x18,0x21,
0x08,0x00,0x0c,0x64,0x00,0x62,0x80,0x21,0x27,0xbd,0xff,0xd0,0xaf,0xbf,0x00,0x28,
0xaf,0xb4,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb5,0x00,0x24,
0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x84,0x82,0x00,0x0c,0x3c,0x06,0xb0,0x03,
0x34,0xc6,0x00,0x20,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,
0x27,0x82,0x90,0x04,0x00,0x62,0x10,0x21,0x8c,0x55,0x00,0x18,0x3c,0x02,0x80,0x00,
0x24,0x42,0x31,0xb8,0xac,0xc2,0x00,0x00,0x8e,0xb0,0x00,0x08,0x27,0x82,0x90,0x08,
0x00,0x62,0x18,0x21,0x90,0x71,0x00,0x07,0x00,0x10,0x86,0x43,0x32,0x10,0x00,0x01,
0x00,0xa0,0x38,0x21,0x02,0x00,0x30,0x21,0x00,0xa0,0x98,0x21,0x02,0x20,0x28,0x21,
0x0c,0x00,0x0c,0x42,0x00,0x80,0x90,0x21,0x02,0x20,0x20,0x21,0x02,0x00,0x28,0x21,
0x24,0x06,0x00,0x14,0x0c,0x00,0x08,0xe3,0x00,0x40,0xa0,0x21,0x86,0x43,0x00,0x0c,
0x3c,0x09,0xb0,0x09,0x3c,0x08,0xb0,0x09,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0x80,0x43,0x00,0x06,
0x3c,0x07,0xb0,0x09,0x3c,0x05,0xb0,0x09,0x28,0x62,0x00,0x00,0x24,0x64,0x00,0x03,
0x00,0x82,0x18,0x0b,0x00,0x03,0x18,0x83,0x3c,0x02,0xb0,0x09,0x00,0x03,0x18,0x80,
0x34,0x42,0x01,0x02,0x35,0x29,0x01,0x10,0x35,0x08,0x01,0x14,0x34,0xe7,0x01,0x20,
0x34,0xa5,0x01,0x24,0xa4,0x54,0x00,0x00,0x12,0x60,0x00,0x11,0x02,0xa3,0xa8,0x21,
0x8e,0xa2,0x00,0x0c,0x8e,0xa3,0x00,0x08,0x00,0x02,0x14,0x00,0x00,0x03,0x1c,0x02,
0x00,0x43,0x10,0x21,0xad,0x22,0x00,0x00,0x8e,0xa3,0x00,0x0c,0x00,0x00,0x00,0x00,
0x00,0x03,0x1c,0x02,0xa5,0x03,0x00,0x00,0x8f,0xbf,0x00,0x28,0x7b,0xb4,0x01,0x3c,
0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
0x8e,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0xad,0x22,0x00,0x00,0x8e,0xa4,0x00,0x08,
0x00,0x00,0x00,0x00,0xa5,0x04,0x00,0x00,0x7a,0xa2,0x00,0x7c,0x00,0x00,0x00,0x00,
0x00,0x03,0x1c,0x00,0x00,0x02,0x14,0x02,0x00,0x62,0x18,0x21,0xac,0xe3,0x00,0x00,
0x8e,0xa2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x02,0x08,0x00,0x0c,0xb6,
0xa4,0xa2,0x00,0x00,0x27,0xbd,0xff,0xe0,0xaf,0xb2,0x00,0x18,0xaf,0xb0,0x00,0x10,
0xaf,0xbf,0x00,0x1c,0xaf,0xb1,0x00,0x14,0x84,0x82,0x00,0x0c,0x00,0x80,0x90,0x21,
0x3c,0x05,0xb0,0x03,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,
0x27,0x82,0x90,0x04,0x00,0x82,0x10,0x21,0x8c,0x51,0x00,0x18,0x3c,0x02,0x80,0x00,
0x34,0xa5,0x00,0x20,0x24,0x42,0x33,0x34,0x27,0x83,0x90,0x08,0xac,0xa2,0x00,0x00,
0x00,0x83,0x20,0x21,0x3c,0x02,0xb0,0x03,0x90,0x86,0x00,0x07,0x34,0x42,0x01,0x00,
0x8e,0x23,0x00,0x08,0x90,0x44,0x00,0x00,0x2c,0xc5,0x00,0x04,0x24,0x02,0x00,0x10,
0x24,0x10,0x00,0x0a,0x00,0x45,0x80,0x0a,0x00,0x03,0x1e,0x43,0x30,0x84,0x00,0x01,
0x30,0x65,0x00,0x01,0x14,0x80,0x00,0x02,0x00,0x10,0x10,0x40,0x02,0x00,0x10,0x21,
0x00,0xc0,0x20,0x21,0x24,0x06,0x00,0x20,0x0c,0x00,0x08,0xe3,0x30,0x50,0x00,0xff,
0x86,0x44,0x00,0x0c,0x27,0x85,0x90,0x10,0x3c,0x06,0xb0,0x09,0x00,0x04,0x18,0xc0,
0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x65,0x18,0x21,0x80,0x64,0x00,0x06,
0x00,0x50,0x10,0x21,0x34,0xc6,0x01,0x02,0x24,0x85,0x00,0x03,0x28,0x83,0x00,0x00,
0x00,0xa3,0x20,0x0b,0x00,0x04,0x20,0x83,0x00,0x04,0x20,0x80,0xa4,0xc2,0x00,0x00,
0x02,0x24,0x20,0x21,0x8c,0x83,0x00,0x04,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x10,
0xac,0x43,0x00,0x00,0x8c,0x86,0x00,0x08,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x14,
0xa4,0x46,0x00,0x00,0x8c,0x85,0x00,0x0c,0x8c,0x82,0x00,0x08,0x3c,0x06,0xb0,0x09,
0x00,0x05,0x2c,0x00,0x00,0x02,0x14,0x02,0x00,0xa2,0x28,0x21,0x34,0xc6,0x01,0x20,
0xac,0xc5,0x00,0x00,0x8c,0x83,0x00,0x0c,0x3c,0x05,0xb0,0x09,0x34,0xa5,0x01,0x24,
0x00,0x03,0x1c,0x02,0xa4,0xa3,0x00,0x00,0x92,0x42,0x00,0x0a,0x3c,0x03,0xb0,0x09,
0x34,0x63,0x01,0x30,0x00,0x02,0x13,0x00,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,
0xa4,0x62,0x00,0x00,0x86,0x44,0x00,0x0c,0x27,0x83,0x90,0x18,0x8f,0xbf,0x00,0x1c,
0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
0x94,0x44,0x00,0x02,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x3c,0x05,0xb0,0x09,
0x34,0xa5,0x01,0x32,0xa4,0xa4,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,
0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0xaf,0xb0,0x00,0x10,
0x34,0x42,0x00,0x20,0x00,0xa0,0x80,0x21,0x24,0x63,0x34,0xc0,0x00,0x05,0x2c,0x43,
0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x18,0xac,0x43,0x00,0x00,0x10,0xa0,0x00,0x05,
0x00,0x80,0x88,0x21,0x8c,0x82,0x00,0x34,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0xb6,
0x00,0x00,0x00,0x00,0x32,0x10,0x00,0xff,0x12,0x00,0x00,0x4c,0x00,0x00,0x10,0x21,
0x24,0x02,0x00,0x08,0x12,0x02,0x00,0xa3,0x2a,0x02,0x00,0x09,0x10,0x40,0x00,0x89,
0x24,0x02,0x00,0x40,0x24,0x04,0x00,0x02,0x12,0x04,0x00,0x79,0x2a,0x02,0x00,0x03,
0x10,0x40,0x00,0x69,0x24,0x02,0x00,0x04,0x24,0x02,0x00,0x01,0x12,0x02,0x00,0x5a,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x00,0x08,0x3c,0x03,0x80,0x00,
0xa2,0x20,0x00,0x4e,0xac,0x43,0x00,0x00,0x82,0x24,0x00,0x11,0x92,0x27,0x00,0x11,
0x10,0x80,0x00,0x4e,0x00,0x00,0x00,0x00,0x92,0x26,0x00,0x0a,0x24,0x02,0x00,0x12,
0x10,0x46,0x00,0x09,0x30,0xc2,0x00,0xff,0x27,0x83,0xb4,0x00,0x00,0x02,0x10,0x80,
0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x94,0x83,0x00,0x14,
0x00,0x00,0x00,0x00,0xa6,0x23,0x00,0x0c,0x3c,0x02,0xb0,0x09,0x34,0x42,0x00,0x40,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x03,0xa2,0x23,0x00,0x10,
0x14,0x60,0x00,0x2b,0x30,0x65,0x00,0x01,0x30,0xc2,0x00,0xff,0x27,0x83,0xb4,0x00,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x82,0x23,0x00,0x12,
0x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x30,0x42,0x00,0x01,
0x00,0x62,0x18,0x21,0x00,0x03,0x26,0x00,0x14,0x80,0x00,0x18,0xa2,0x23,0x00,0x12,
0x00,0x07,0x16,0x00,0x14,0x40,0x00,0x11,0x24,0x02,0x00,0x01,0x96,0x23,0x00,0x0c,
0x27,0x84,0x90,0x10,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,0x3c,0x02,0xb0,0x00,
0x00,0x65,0x18,0x21,0x00,0x62,0x18,0x21,0x90,0x64,0x00,0x00,0x90,0x62,0x00,0x04,
0xa2,0x20,0x00,0x15,0xa3,0x80,0x8b,0xd4,0x24,0x02,0x00,0x01,0x8f,0xbf,0x00,0x18,
0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x0c,0xcd,
0x02,0x20,0x20,0x21,0x92,0x27,0x00,0x11,0x08,0x00,0x0d,0x7d,0x00,0x07,0x16,0x00,
0x0c,0x00,0x0c,0x6e,0x02,0x20,0x20,0x21,0x86,0x23,0x00,0x0c,0x27,0x84,0x90,0x08,
0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x44,0x20,0x21,
0x90,0x85,0x00,0x07,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0xa2,0x25,0x00,0x13,
0x90,0x83,0x00,0x07,0x08,0x00,0x0d,0x95,0xa0,0x43,0x00,0x02,0x92,0x26,0x00,0x0a,
0x08,0x00,0x0d,0x5e,0x30,0xc2,0x00,0xff,0x8e,0x22,0x00,0x24,0x00,0x00,0x00,0x00,
0x10,0x50,0x00,0x07,0xa2,0x20,0x00,0x08,0x24,0x02,0x00,0x07,0xa2,0x22,0x00,0x0a,
0x92,0x22,0x00,0x27,0xae,0x20,0x00,0x24,0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x04,
0x08,0x00,0x0d,0xaf,0x24,0x02,0x00,0x06,0x16,0x02,0xff,0x9b,0x3c,0x02,0xb0,0x05,
0x8e,0x23,0x00,0x2c,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x07,0xa2,0x24,0x00,0x08,
0x24,0x02,0x00,0x03,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2f,0xae,0x20,0x00,0x2c,
0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x06,0x08,0x00,0x0d,0xbe,0xa2,0x20,0x00,0x0a,
0x8e,0x22,0x00,0x28,0x24,0x03,0x00,0x01,0x24,0x04,0x00,0x01,0x10,0x44,0x00,0x07,
0xa2,0x23,0x00,0x08,0x24,0x02,0x00,0x05,0xa2,0x22,0x00,0x0a,0x92,0x22,0x00,0x2b,
0xae,0x20,0x00,0x28,0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x05,0x08,0x00,0x0d,0xca,
0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x12,0x2a,0x02,0x00,0x41,0x10,0x40,0x00,0x09,
0x24,0x02,0x00,0x80,0x24,0x02,0x00,0x20,0x16,0x02,0xff,0x7b,0x3c,0x02,0xb0,0x05,
0x24,0x02,0x00,0x12,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x51,
0xae,0x20,0x00,0x3c,0x16,0x02,0xff,0x74,0x3c,0x02,0xb0,0x05,0x24,0x02,0x00,0x10,
0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x51,0xae,0x20,0x00,0x34,
0x24,0x02,0x00,0x11,0xa2,0x22,0x00,0x0a,0xa2,0x22,0x00,0x08,0x08,0x00,0x0d,0x51,
0xae,0x20,0x00,0x38,0x8e,0x24,0x00,0x30,0x24,0x02,0x00,0x03,0x24,0x03,0x00,0x01,
0x10,0x83,0x00,0x07,0xa2,0x22,0x00,0x08,0x24,0x02,0x00,0x02,0xa2,0x22,0x00,0x0a,
0x92,0x22,0x00,0x33,0xae,0x20,0x00,0x30,0x08,0x00,0x0d,0x51,0xa2,0x22,0x00,0x07,
0x08,0x00,0x0d,0xf0,0xa2,0x24,0x00,0x0a,0x8f,0x84,0xb4,0x40,0xae,0x20,0x00,0x34,
0x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x66,0x32,0x10,0x00,0xff,0x08,0x00,0x0d,0x42,
0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x37,0xf4,
0x34,0x63,0x00,0x20,0xac,0x62,0x00,0x00,0x80,0xa2,0x00,0x15,0x3c,0x06,0xb0,0x05,
0x10,0x40,0x00,0x0a,0x34,0xc6,0x02,0x54,0x83,0x83,0x8b,0xd4,0x00,0x00,0x00,0x00,
0xac,0x83,0x00,0x24,0x8c,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42,
0x30,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x28,0x8c,0x82,0x00,0x2c,
0x3c,0x06,0xb0,0x05,0x34,0xc6,0x04,0x50,0x00,0x02,0x18,0x43,0x30,0x63,0x00,0x01,
0x10,0x40,0x00,0x04,0x30,0x45,0x00,0x01,0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,
0xac,0x85,0x00,0x24,0x90,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,
0x30,0x43,0x00,0x02,0x30,0x42,0x00,0x01,0xac,0x83,0x00,0x28,0x03,0xe0,0x00,0x08,
0xac,0x82,0x00,0x24,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd8,
0x34,0x63,0x00,0x20,0x24,0x42,0x38,0x84,0xac,0x62,0x00,0x00,0xaf,0xb1,0x00,0x1c,
0xaf,0xbf,0x00,0x20,0xaf,0xb0,0x00,0x18,0x90,0xa6,0x00,0x0a,0x27,0x83,0xb4,0x00,
0x00,0xa0,0x88,0x21,0x00,0x06,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,
0x80,0xa5,0x00,0x11,0x92,0x03,0x00,0x12,0x10,0xa0,0x00,0x04,0xa2,0x20,0x00,0x15,
0x24,0x02,0x00,0x12,0x10,0xc2,0x00,0xda,0x00,0x00,0x00,0x00,0x82,0x22,0x00,0x12,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x67,0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x12,
0xa2,0x00,0x00,0x19,0x86,0x23,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,
0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x20,0x00,0x43,0x10,0x21,
0xa0,0x40,0x00,0x00,0x92,0x03,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0xdf,
0xa2,0x03,0x00,0x16,0x82,0x02,0x00,0x12,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,
0x00,0x00,0x00,0x00,0x92,0x23,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x45,
0x24,0x02,0x00,0x01,0xa2,0x20,0x00,0x04,0x92,0x08,0x00,0x04,0x00,0x00,0x00,0x00,
0x15,0x00,0x00,0x1e,0x24,0x02,0x00,0x01,0x92,0x07,0x00,0x0a,0xa2,0x02,0x00,0x17,
0x92,0x02,0x00,0x16,0x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xe4,0x10,0x60,0x00,0x03,
0xa2,0x02,0x00,0x16,0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,0x11,0x00,0x00,0x05,
0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,
0xa2,0x02,0x00,0x16,0x92,0x02,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x08,
0x00,0x00,0x00,0x00,0x96,0x02,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x02,0x00,0x14,
0x8f,0xbf,0x00,0x20,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
0x96,0x02,0x00,0x00,0x08,0x00,0x0e,0x6c,0xa6,0x02,0x00,0x14,0x92,0x07,0x00,0x0a,
0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x58,
0xa2,0x00,0x00,0x17,0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,0x27,0x86,0x90,0x00,
0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,
0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,
0x8c,0x66,0x00,0x08,0x8c,0x45,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xc3,0x20,0x24,
0x10,0x80,0x00,0x08,0x00,0xa3,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,
0x10,0x80,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0xa6,0x18,0x2b,0x08,0x00,0x0e,0x58,
0xa2,0x03,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0xa6,0x18,0x2b,0x08,0x00,0x0e,0x8c,
0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,
0x24,0x02,0x00,0x03,0x14,0x62,0xff,0xb8,0x00,0x00,0x00,0x00,0x08,0x00,0x0e,0x52,
0xa2,0x20,0x00,0x07,0x08,0x00,0x0e,0x52,0xa2,0x20,0x00,0x06,0x08,0x00,0x0e,0x52,
0xa2,0x20,0x00,0x05,0x82,0x22,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x69,
0x2c,0x62,0x00,0x02,0x10,0x40,0x00,0x49,0x3c,0x02,0xb0,0x09,0x92,0x25,0x00,0x08,
0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x3b,
0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,
0xa0,0x83,0x00,0x00,0x86,0x23,0x00,0x0c,0x96,0x26,0x00,0x0c,0x00,0x03,0x10,0xc0,
0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,0x27,0x83,0x90,0x04,0x00,0xa3,0x18,0x21,
0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x18,0x24,0x07,0x00,0x01,0x93,0x82,0x8b,0x71,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x0a,0x24,0x05,0x00,0x24,
0x00,0x06,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1b,0x66,0x02,0x00,0x20,0x21,
0x92,0x02,0x00,0x16,0xa2,0x00,0x00,0x12,0x30,0x42,0x00,0xe7,0x08,0x00,0x0e,0x49,
0xa2,0x02,0x00,0x16,0xf0,0xc5,0x00,0x06,0x00,0x00,0x28,0x12,0x27,0x82,0x90,0x00,
0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49,0x3c,0x04,0x00,0x80,0x96,0x26,0x00,0x0c,
0x08,0x00,0x0e,0xc9,0x00,0x06,0x2c,0x00,0x27,0x83,0x90,0x10,0x27,0x82,0x90,0x18,
0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,0x90,0x65,0x00,0x05,
0x93,0x82,0x80,0x10,0x00,0x00,0x30,0x21,0x0c,0x00,0x21,0x9a,0xaf,0xa2,0x00,0x10,
0x96,0x26,0x00,0x0c,0x08,0x00,0x0e,0xc3,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xcd,
0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,
0x24,0x02,0x00,0x80,0x08,0x00,0x0e,0xb2,0x00,0xa2,0x10,0x07,0x86,0x26,0x00,0x0c,
0x3c,0x03,0xb0,0x09,0x34,0x42,0x01,0x72,0x34,0x63,0x01,0x78,0x94,0x47,0x00,0x00,
0x8c,0x65,0x00,0x00,0x00,0x06,0x10,0xc0,0x00,0x46,0x10,0x21,0x3c,0x04,0xb0,0x09,
0xae,0x25,0x00,0x1c,0x34,0x84,0x01,0x7c,0x27,0x83,0x90,0x04,0x00,0x02,0x10,0x80,
0x8c,0x85,0x00,0x00,0x00,0x43,0x10,0x21,0x8c,0x43,0x00,0x18,0xae,0x25,0x00,0x20,
0xa6,0x27,0x00,0x18,0x8c,0x66,0x00,0x08,0x02,0x20,0x20,0x21,0x0c,0x00,0x0f,0x19,
0x00,0x00,0x28,0x21,0x86,0x25,0x00,0x18,0x8e,0x26,0x00,0x1c,0x8e,0x27,0x00,0x20,
0x02,0x20,0x20,0x21,0x0c,0x00,0x1c,0x68,0xaf,0xa2,0x00,0x10,0x08,0x00,0x0e,0x49,
0xa2,0x02,0x00,0x12,0x92,0x22,0x00,0x08,0x08,0x00,0x0e,0x49,0xa2,0x22,0x00,0x09,
0xa2,0x20,0x00,0x11,0x80,0x82,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xac,0x40,0x00,0x00,0x08,0x00,0x0e,0x49,
0xa0,0x80,0x00,0x50,0x94,0x8a,0x00,0x0c,0x24,0x03,0x00,0x24,0x00,0x80,0x70,0x21,
0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,0x24,0x42,0x3c,0x64,0xf1,0x43,0x00,0x06,
0x34,0x84,0x00,0x20,0x00,0x00,0x18,0x12,0x00,0xa0,0x68,0x21,0xac,0x82,0x00,0x00,
0x27,0x85,0x90,0x10,0x27,0x82,0x90,0x0f,0x27,0xbd,0xff,0xf8,0x00,0x62,0x60,0x21,
0x00,0x65,0x58,0x21,0x00,0x00,0xc0,0x21,0x11,0xa0,0x00,0xcc,0x00,0x00,0x78,0x21,
0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x45,0x10,0x21,0x91,0x87,0x00,0x00,0x80,0x48,0x00,0x04,
0x03,0xa0,0x60,0x21,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,
0x00,0x43,0x10,0x21,0x00,0x02,0x48,0x80,0x27,0x83,0x90,0x04,0xa3,0xa7,0x00,0x00,
0x01,0x23,0x18,0x21,0x8c,0x64,0x00,0x18,0x25,0x02,0xff,0xff,0x00,0x48,0x40,0x0b,
0x8c,0x83,0x00,0x04,0x2d,0x05,0x00,0x07,0x24,0x02,0x00,0x06,0x30,0x63,0x00,0x08,
0x14,0x60,0x00,0x35,0x00,0x45,0x40,0x0a,0x93,0xa7,0x00,0x00,0x27,0x82,0x90,0x18,
0x01,0x22,0x10,0x21,0x30,0xe3,0x00,0xf0,0x38,0x63,0x00,0x50,0x30,0xe5,0x00,0xff,
0x00,0x05,0x20,0x2b,0x00,0x03,0x18,0x2b,0x00,0x64,0x18,0x24,0x90,0x49,0x00,0x00,
0x10,0x60,0x00,0x16,0x30,0xe4,0x00,0x0f,0x24,0x02,0x00,0x04,0x10,0xa2,0x00,0x9d,
0x00,0x00,0x00,0x00,0x11,0xa0,0x00,0x3a,0x2c,0xa2,0x00,0x0c,0x10,0x40,0x00,0x02,
0x24,0x84,0x00,0x0c,0x00,0xe0,0x20,0x21,0x30,0x84,0x00,0xff,0x00,0x04,0x10,0x40,
0x27,0x83,0xbb,0x1c,0x00,0x44,0x10,0x21,0x00,0x43,0x10,0x21,0x90,0x47,0x00,0x00,
0x00,0x00,0x00,0x00,0x2c,0xe3,0x00,0x0c,0xa3,0xa7,0x00,0x00,0x10,0x60,0x00,0x02,
0x24,0xe2,0x00,0x04,0x00,0xe0,0x10,0x21,0xa3,0xa2,0x00,0x00,0x91,0x65,0x00,0x00,
0x91,0x82,0x00,0x00,0x30,0xa3,0x00,0xff,0x00,0x62,0x10,0x2b,0x10,0x40,0x00,0x0e,
0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0x60,0x20,0x21,0x30,0xa2,0x00,0x0f,
0x24,0x44,0x00,0x0c,0x00,0x04,0x10,0x40,0x00,0x44,0x20,0x21,0x27,0x83,0xbb,0x1c,
0x00,0x83,0x18,0x21,0x90,0x62,0x00,0x02,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,
0x00,0x09,0x11,0x00,0xa1,0x85,0x00,0x00,0x93,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x08,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x23,
0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x27,0x83,0xb4,0xa8,0x00,0x43,0x10,0x21,
0x90,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x83,0x00,0x0c,0x14,0x60,0x00,0x06,
0x00,0x80,0x10,0x21,0x00,0x18,0x10,0x40,0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,
0x00,0x82,0x10,0x21,0x24,0x42,0x00,0x04,0x08,0x00,0x0f,0x7a,0xa1,0x82,0x00,0x00,
0x8f,0x8d,0x81,0x5c,0x00,0x00,0x00,0x00,0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xd1,0x00,0x00,0x28,0x21,0x00,0x06,0x74,0x82,
0x30,0xe2,0x00,0xff,0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x03,0x00,0xe0,0x10,0x21,
0x30,0xe2,0x00,0x0f,0x24,0x42,0x00,0x0c,0x30,0x44,0x00,0xff,0xa3,0xa2,0x00,0x00,
0x24,0x02,0x00,0x0c,0x10,0x82,0x00,0x0d,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,
0x00,0x02,0x10,0x80,0x00,0x04,0x18,0x40,0x00,0x49,0x10,0x23,0x00,0x64,0x18,0x21,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x27,0x84,0xb4,0xa8,0x00,0x44,0x10,0x21,
0x90,0x47,0x00,0x00,0x00,0x00,0x00,0x00,0xa3,0xa7,0x00,0x00,0x00,0x0a,0x1c,0x00,
0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
0x27,0x83,0x90,0x04,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,
0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0x00,0x33,
0x00,0x06,0x14,0x42,0x00,0x09,0x11,0x00,0x00,0x49,0x10,0x23,0x00,0x02,0x10,0x80,
0x00,0x49,0x10,0x23,0x27,0x83,0xb5,0x78,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,
0x90,0x44,0x00,0x04,0x90,0x43,0x00,0x05,0x00,0x00,0x00,0x00,0x00,0x64,0xc0,0x24,
0x93,0xa7,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0xe2,0x00,0x0f,0x10,0x40,0x00,0x0f,
0x31,0xcf,0x00,0x01,0x00,0x0a,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,
0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x90,0x00,0x00,0x44,0x10,0x21,
0x84,0x43,0x00,0x06,0x00,0x00,0x00,0x00,0x28,0x63,0x06,0x41,0x14,0x60,0x00,0x04,
0x30,0xe2,0x00,0xff,0x24,0x07,0x00,0x0f,0xa3,0xa7,0x00,0x00,0x30,0xe2,0x00,0xff,
0x2c,0x42,0x00,0x0c,0x14,0x40,0x00,0x06,0x00,0xe0,0x10,0x21,0x00,0x18,0x10,0x40,
0x00,0x4f,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0x47,0x10,0x21,0x24,0x42,0x00,0x04,
0xa3,0xa2,0x00,0x00,0x00,0x40,0x38,0x21,0x01,0xa8,0x10,0x21,0x90,0x43,0x00,0x00,
0x24,0xa4,0x00,0x01,0x30,0x85,0xff,0xff,0x00,0xa3,0x18,0x2b,0x14,0x60,0xff,0xad,
0x30,0xe2,0x00,0xff,0x08,0x00,0x0f,0x67,0x00,0x00,0x00,0x00,0x08,0x00,0x0f,0xc8,
0x30,0x58,0x00,0x01,0x81,0xc2,0x00,0x48,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x73,
0x00,0x00,0x00,0x00,0x08,0x00,0x0f,0x55,0x00,0x00,0x00,0x00,0x00,0x0a,0x1c,0x00,
0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
0x00,0x45,0x10,0x21,0x80,0x48,0x00,0x05,0x91,0x67,0x00,0x00,0x08,0x00,0x0f,0x35,
0x03,0xa0,0x58,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,
0x24,0x42,0x40,0x04,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,
0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,
0xaf,0xb3,0x00,0x24,0xaf,0xb2,0x00,0x20,0xaf,0xbf,0x00,0x3c,0xaf,0xbe,0x00,0x38,
0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0x84,0x82,0x00,0x0c,0x27,0x93,0x90,0x04,
0x3c,0x05,0xb0,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,
0x00,0x73,0x10,0x21,0x8c,0x5e,0x00,0x18,0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,
0x24,0x42,0x40,0x1c,0xac,0xa2,0x00,0x00,0x8f,0xd0,0x00,0x08,0x27,0x95,0x90,0x10,
0x00,0x75,0x18,0x21,0x00,0x00,0x28,0x21,0x02,0x00,0x30,0x21,0x90,0x71,0x00,0x00,
0x0c,0x00,0x0f,0x19,0x00,0x80,0xb0,0x21,0x00,0x40,0x90,0x21,0x00,0x10,0x14,0x42,
0x30,0x54,0x00,0x01,0x02,0x40,0x20,0x21,0x00,0x10,0x14,0x82,0x02,0x80,0x28,0x21,
0x12,0x51,0x00,0x23,0x00,0x10,0xbf,0xc2,0x86,0xc3,0x00,0x0c,0x30,0x50,0x00,0x01,
0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,
0xa0,0x52,0x00,0x00,0x86,0xc3,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,
0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x53,0x30,0x21,0x8c,0xc7,0x00,0x18,
0x27,0x83,0x90,0x00,0x00,0x43,0x10,0x21,0x8c,0xe3,0x00,0x04,0x84,0x46,0x00,0x06,
0x00,0x03,0x19,0x42,0x0c,0x00,0x08,0xe3,0x30,0x73,0x00,0x01,0x00,0x40,0x88,0x21,
0x02,0x40,0x20,0x21,0x02,0x80,0x28,0x21,0x16,0xe0,0x00,0x10,0x02,0x00,0x30,0x21,
0x86,0xc2,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,
0x00,0x03,0x18,0x80,0x27,0x82,0x90,0x08,0x00,0x62,0x18,0x21,0xa4,0x71,0x00,0x04,
0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,
0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0x86,0xc3,0x00,0x0c,
0xaf,0xb3,0x00,0x10,0xaf,0xa0,0x00,0x14,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x55,0x10,0x21,0x80,0x47,0x00,0x06,0x00,0x00,0x00,0x00,
0x24,0xe7,0x00,0x02,0x00,0x07,0x17,0xc2,0x00,0xe2,0x38,0x21,0x00,0x07,0x38,0x43,
0x00,0x07,0x38,0x40,0x0c,0x00,0x09,0x0a,0x03,0xc7,0x38,0x21,0x08,0x00,0x10,0x48,
0x02,0x22,0x88,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0xd0,
0x34,0x63,0x00,0x20,0x24,0x42,0x41,0xa4,0xaf,0xb2,0x00,0x20,0xac,0x62,0x00,0x00,
0xaf,0xbf,0x00,0x28,0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,
0x3c,0x02,0xb0,0x03,0x90,0x83,0x00,0x0a,0x34,0x42,0x01,0x04,0x94,0x45,0x00,0x00,
0x00,0x03,0x18,0x80,0x27,0x82,0xb4,0x00,0x00,0x62,0x18,0x21,0x30,0xa6,0xff,0xff,
0x8c,0x71,0x00,0x00,0x80,0x85,0x00,0x12,0x30,0xc9,0x00,0xff,0x00,0x06,0x32,0x02,
0xa4,0x86,0x00,0x44,0xa4,0x89,0x00,0x46,0x82,0x22,0x00,0x12,0x00,0x80,0x90,0x21,
0x10,0xa0,0x00,0x1b,0xa0,0x80,0x00,0x15,0x00,0xc5,0x10,0x2a,0x10,0x40,0x00,0x14,
0x00,0x00,0x00,0x00,0xa2,0x20,0x00,0x19,0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,
0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x20,
0x00,0x43,0x10,0x21,0xa0,0x40,0x00,0x00,0xa0,0x80,0x00,0x12,0x92,0x22,0x00,0x16,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xdf,0xa2,0x22,0x00,0x16,0x8f,0xbf,0x00,0x28,
0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x30,
0x0c,0x00,0x10,0x01,0x00,0x00,0x00,0x00,0x08,0x00,0x10,0x97,0x00,0x00,0x00,0x00,
0x28,0x42,0x00,0x02,0x10,0x40,0x01,0x76,0x00,0x00,0x28,0x21,0x94,0x87,0x00,0x0c,
0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x21,0x00,0x02,0x14,0x00,0x00,0x02,0x14,0x03,
0x00,0x07,0x24,0x00,0x00,0x04,0x24,0x03,0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,
0x00,0x04,0x28,0xc0,0x00,0xa4,0x28,0x21,0x27,0x82,0x90,0x20,0x00,0x03,0x18,0x80,
0x00,0x62,0x18,0x21,0x00,0x05,0x28,0x80,0x27,0x82,0x90,0x08,0x00,0xa2,0x10,0x21,
0x8c,0x68,0x00,0x00,0x80,0x44,0x00,0x06,0x27,0x82,0x90,0x10,0x00,0x08,0x1d,0x02,
0x00,0xa2,0x28,0x21,0x38,0x84,0x00,0x00,0x30,0x63,0x00,0x01,0x01,0x24,0x30,0x0b,
0x80,0xaa,0x00,0x04,0x80,0xa9,0x00,0x05,0x10,0x60,0x00,0x02,0x00,0x08,0x14,0x02,
0x30,0x46,0x00,0x0f,0x15,0x20,0x00,0x28,0x01,0x49,0x10,0x21,0x15,0x40,0x00,0x11,
0x30,0xe3,0xff,0xff,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa8,0x00,0xff,
0x2d,0x02,0x00,0x04,0x10,0x40,0x01,0x46,0x2d,0x02,0x00,0x10,0x3c,0x04,0xb0,0x05,
0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x01,0x02,0x10,0x04,
0x00,0x62,0x18,0x25,0xa0,0x83,0x00,0x00,0x96,0x47,0x00,0x0c,0x00,0x00,0x00,0x00,
0x30,0xe3,0xff,0xff,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x27,0x84,0x90,0x10,
0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x80,0x45,0x00,0x06,0x00,0x03,0x1a,0x00,
0x3c,0x04,0xb0,0x00,0x00,0x65,0x18,0x21,0x00,0x64,0x20,0x21,0x94,0x82,0x00,0x00,
0x82,0x43,0x00,0x10,0x00,0x02,0x14,0x00,0x14,0x60,0x00,0x06,0x00,0x02,0x3c,0x03,
0x30,0xe2,0x00,0x04,0x14,0x40,0x00,0x04,0x01,0x49,0x10,0x21,0x34,0xe2,0x08,0x00,
0xa4,0x82,0x00,0x00,0x01,0x49,0x10,0x21,0x00,0x02,0x16,0x00,0x00,0x02,0x16,0x03,
0x00,0x46,0x10,0x2a,0x10,0x40,0x00,0x7c,0x00,0x00,0x00,0x00,0x82,0x42,0x00,0x10,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,0x86,0x43,0x00,0x0c,
0x25,0x44,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,
0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x04,0x92,0x23,0x00,0x16,
0x02,0x40,0x20,0x21,0x30,0x63,0x00,0xfb,0x08,0x00,0x10,0x9c,0xa2,0x23,0x00,0x16,
0x86,0x43,0x00,0x0c,0x25,0x24,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,0xa0,0x44,0x00,0x05,
0x86,0x45,0x00,0x0c,0x0c,0x00,0x1e,0xea,0x02,0x20,0x20,0x21,0x10,0x40,0x00,0x5a,
0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa6,0x00,0xff,
0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x4c,0x2c,0xc2,0x00,0x10,0x3c,0x04,0xb0,0x05,
0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,0x00,0xc2,0x10,0x04,
0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,0x92,0x45,0x00,0x08,
0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x33,0x24,0x02,0x00,0x01,
0xa2,0x40,0x00,0x04,0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0c,
0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,
0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x96,0x22,0x00,0x06,0x08,0x00,0x10,0x97,
0xa6,0x22,0x00,0x14,0x96,0x22,0x00,0x00,0x08,0x00,0x10,0x97,0xa6,0x22,0x00,0x14,
0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,
0x08,0x00,0x11,0x26,0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,
0x27,0x86,0x90,0x00,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,
0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,
0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,
0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,
0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,
0x08,0x00,0x11,0x26,0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,
0x08,0x00,0x11,0x49,0x00,0x00,0x00,0x00,0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,
0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xca,0x00,0x00,0x00,0x00,
0x08,0x00,0x11,0x21,0xa2,0x40,0x00,0x07,0x08,0x00,0x11,0x21,0xa2,0x40,0x00,0x06,
0x08,0x00,0x11,0x21,0xa2,0x40,0x00,0x05,0x14,0x40,0xff,0xbe,0x3c,0x04,0xb0,0x05,
0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,
0x08,0x00,0x11,0x18,0x00,0xa2,0x10,0x07,0x0c,0x00,0x10,0x07,0x02,0x40,0x20,0x21,
0x08,0x00,0x10,0x97,0x00,0x00,0x00,0x00,0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,
0x30,0xa6,0x00,0xff,0x2c,0xc2,0x00,0x04,0x10,0x40,0x00,0x99,0x2c,0xc2,0x00,0x10,
0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,0x24,0x02,0x00,0x01,
0x00,0xc2,0x10,0x04,0x00,0x02,0x10,0x27,0x00,0x62,0x18,0x24,0xa0,0x83,0x00,0x00,
0x92,0x45,0x00,0x08,0x00,0x00,0x00,0x00,0x30,0xa5,0x00,0xff,0x14,0xa0,0x00,0x80,
0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x86,0x43,0x00,0x0c,0x27,0x93,0x90,0x04,
0x96,0x47,0x00,0x0c,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x28,0x80,
0x00,0xb3,0x18,0x21,0x8c,0x64,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x10,0x10,0x40,0x00,0x64,0x00,0x00,0x30,0x21,
0x00,0x07,0x1c,0x00,0x00,0x03,0x1c,0x03,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x53,0x10,0x21,0x8c,0x43,0x00,0x18,0x93,0x82,0x8b,0x71,
0x8c,0x64,0x00,0x04,0x30,0x42,0x00,0x01,0x00,0x04,0x21,0x42,0x14,0x40,0x00,0x4d,
0x30,0x90,0x00,0x01,0x00,0x07,0x2c,0x00,0x00,0x05,0x2c,0x03,0x0c,0x00,0x1b,0x66,
0x02,0x20,0x20,0x21,0x96,0x26,0x00,0x06,0x12,0x00,0x00,0x14,0x30,0xc5,0xff,0xff,
0x02,0x60,0x90,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x02,0x10,0x80,
0x00,0x52,0x18,0x21,0x92,0x22,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0b,
0x02,0x20,0x20,0x21,0x8c,0x63,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x62,0x00,0x04,
0x00,0x00,0x00,0x00,0x00,0x02,0x11,0x42,0x0c,0x00,0x1b,0x66,0x30,0x50,0x00,0x01,
0x96,0x26,0x00,0x06,0x16,0x00,0xff,0xef,0x30,0xc5,0xff,0xff,0x92,0x22,0x00,0x04,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x0d,0x24,0x02,0x00,0x01,0xa2,0x22,0x00,0x17,
0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,
0xa6,0x26,0x00,0x14,0x92,0x22,0x00,0x16,0x08,0x00,0x10,0x96,0x30,0x42,0x00,0xc3,
0x96,0x22,0x00,0x00,0x08,0x00,0x11,0xbd,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x0a,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x11,0xb8,
0xa2,0x20,0x00,0x17,0x96,0x24,0x00,0x00,0x30,0xc5,0xff,0xff,0x00,0x05,0x18,0xc0,
0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21,0x27,0x84,0x90,0x00,
0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x21,0x00,0x03,0x18,0x80,0x8c,0x45,0x00,0x08,
0x00,0x64,0x18,0x21,0x8c,0x64,0x00,0x08,0x3c,0x02,0x80,0x00,0x00,0xa2,0x38,0x24,
0x10,0xe0,0x00,0x08,0x00,0x82,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,
0x10,0xe0,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x11,0xb8,
0xa2,0x23,0x00,0x17,0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x11,0xdc,
0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x24,0xf0,0xe5,0x00,0x06,0x00,0x00,0x28,0x12,
0x27,0x82,0x90,0x00,0x00,0xa2,0x28,0x21,0x0c,0x00,0x01,0x49,0x00,0x00,0x20,0x21,
0x96,0x47,0x00,0x0c,0x08,0x00,0x11,0x9a,0x00,0x07,0x2c,0x00,0x27,0x83,0x90,0x10,
0x27,0x82,0x90,0x18,0x00,0xa2,0x10,0x21,0x00,0xa3,0x18,0x21,0x90,0x44,0x00,0x00,
0x90,0x65,0x00,0x05,0x93,0x82,0x80,0x10,0x24,0x07,0x00,0x01,0x0c,0x00,0x21,0x9a,
0xaf,0xa2,0x00,0x10,0x96,0x47,0x00,0x0c,0x08,0x00,0x11,0x8d,0x00,0x07,0x1c,0x00,
0x10,0xa2,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x05,0x24,0x02,0x00,0x03,
0x14,0xa2,0xff,0x7d,0x00,0x00,0x00,0x00,0x08,0x00,0x11,0x7e,0xa2,0x40,0x00,0x07,
0x08,0x00,0x11,0x7e,0xa2,0x40,0x00,0x06,0x08,0x00,0x11,0x7e,0xa2,0x40,0x00,0x05,
0x14,0x40,0xff,0x71,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x11,0x75,0x00,0xa2,0x10,0x07,
0x14,0x40,0xfe,0xc3,0x3c,0x04,0xb0,0x05,0x34,0x84,0x02,0x29,0x90,0x83,0x00,0x00,
0x30,0xa5,0x00,0x0f,0x24,0x02,0x00,0x80,0x08,0x00,0x10,0xd0,0x00,0xa2,0x10,0x07,
0x84,0x83,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,
0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x04,0x00,0x43,0x10,0x21,0x8c,0x47,0x00,0x18,
0x00,0x00,0x00,0x00,0x8c,0xe6,0x00,0x08,0x0c,0x00,0x0f,0x19,0x00,0x00,0x00,0x00,
0x02,0x40,0x20,0x21,0x00,0x00,0x28,0x21,0x00,0x00,0x30,0x21,0x00,0x00,0x38,0x21,
0x0c,0x00,0x1c,0x68,0xaf,0xa2,0x00,0x10,0x00,0x02,0x1e,0x00,0x14,0x60,0xfe,0x6b,
0xa2,0x22,0x00,0x12,0x92,0x43,0x00,0x08,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x40,
0x24,0x02,0x00,0x01,0xa2,0x40,0x00,0x04,0x92,0x28,0x00,0x04,0x00,0x00,0x00,0x00,
0x15,0x00,0x00,0x19,0x24,0x02,0x00,0x01,0x92,0x27,0x00,0x0a,0xa2,0x22,0x00,0x17,
0x92,0x22,0x00,0x17,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x10,0x00,0x00,0x00,0x00,
0x96,0x22,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x22,0x00,0x14,0x92,0x22,0x00,0x16,
0x30,0xe3,0x00,0xff,0x30,0x42,0x00,0xc0,0x10,0x60,0x00,0x03,0xa2,0x22,0x00,0x16,
0x34,0x42,0x00,0x01,0xa2,0x22,0x00,0x16,0x11,0x00,0xfe,0x50,0x00,0x00,0x00,0x00,
0x92,0x22,0x00,0x16,0x08,0x00,0x10,0x96,0x34,0x42,0x00,0x02,0x96,0x22,0x00,0x00,
0x08,0x00,0x12,0x3f,0xa6,0x22,0x00,0x14,0x92,0x27,0x00,0x0a,0x00,0x00,0x00,0x00,
0x14,0xe0,0x00,0x03,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0x38,0xa2,0x20,0x00,0x17,
0x96,0x24,0x00,0x00,0x96,0x25,0x00,0x06,0x27,0x86,0x90,0x00,0x00,0x04,0x18,0xc0,
0x00,0x64,0x18,0x21,0x00,0x05,0x10,0xc0,0x00,0x45,0x10,0x21,0x00,0x03,0x18,0x80,
0x00,0x66,0x18,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,
0x8c,0x44,0x00,0x08,0x3c,0x03,0x80,0x00,0x00,0xa3,0x30,0x24,0x10,0xc0,0x00,0x08,
0x00,0x83,0x10,0x24,0x10,0x40,0x00,0x04,0x00,0x00,0x18,0x21,0x10,0xc0,0x00,0x02,
0x24,0x03,0x00,0x01,0x00,0x85,0x18,0x2b,0x08,0x00,0x12,0x38,0xa2,0x23,0x00,0x17,
0x10,0x40,0xff,0xfd,0x00,0x85,0x18,0x2b,0x08,0x00,0x12,0x67,0x00,0x00,0x00,0x00,
0x10,0x62,0x00,0x09,0x24,0x02,0x00,0x02,0x10,0x62,0x00,0x05,0x24,0x02,0x00,0x03,
0x14,0x62,0xff,0xbd,0x00,0x00,0x00,0x00,0x08,0x00,0x12,0x32,0xa2,0x40,0x00,0x07,
0x08,0x00,0x12,0x32,0xa2,0x40,0x00,0x06,0x08,0x00,0x12,0x32,0xa2,0x40,0x00,0x05,
0x3c,0x02,0x80,0x00,0x00,0x82,0x30,0x24,0x10,0xc0,0x00,0x08,0x00,0xa2,0x18,0x24,
0x10,0x60,0x00,0x04,0x00,0x00,0x10,0x21,0x10,0xc0,0x00,0x02,0x24,0x02,0x00,0x01,
0x00,0xa4,0x10,0x2b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x10,0x60,0xff,0xfd,
0x00,0xa4,0x10,0x2b,0x08,0x00,0x12,0x82,0x00,0x00,0x00,0x00,0x30,0x82,0xff,0xff,
0x00,0x02,0x18,0xc0,0x00,0x62,0x18,0x21,0x27,0x84,0x90,0x10,0x00,0x03,0x18,0x80,
0x00,0x64,0x18,0x21,0x80,0x66,0x00,0x06,0x00,0x02,0x12,0x00,0x3c,0x03,0xb0,0x00,
0x00,0x46,0x10,0x21,0x00,0x45,0x10,0x21,0x03,0xe0,0x00,0x08,0x00,0x43,0x10,0x21,
0x27,0xbd,0xff,0xe0,0x30,0x82,0x00,0x7c,0x30,0x84,0xff,0x00,0xaf,0xbf,0x00,0x1c,
0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x14,0x40,0x00,0x41,
0x00,0x04,0x22,0x03,0x24,0x02,0x00,0x04,0x3c,0x10,0xb0,0x03,0x8e,0x10,0x00,0x00,
0x10,0x82,0x00,0x32,0x24,0x02,0x00,0x08,0x10,0x82,0x00,0x03,0x32,0x02,0x00,0x20,
0x08,0x00,0x12,0xa8,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x17,0x3c,0x02,0xb0,0x06,
0x34,0x42,0x80,0x24,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x67,0x00,0xff,
0x10,0xe0,0x00,0x23,0x00,0x00,0x88,0x21,0x8f,0x85,0x8f,0xe0,0x00,0x40,0x30,0x21,
0x94,0xa2,0x00,0x08,0x8c,0xc3,0x00,0x00,0x26,0x31,0x00,0x01,0x24,0x42,0x00,0x02,
0x30,0x42,0x01,0xff,0x34,0x63,0x01,0x00,0x02,0x27,0x20,0x2a,0xa4,0xa2,0x00,0x08,
0x14,0x80,0xff,0xf7,0xac,0xc3,0x00,0x00,0x84,0xa3,0x00,0x08,0x3c,0x02,0xb0,0x03,
0x34,0x42,0x00,0x30,0xac,0x43,0x00,0x00,0x27,0x92,0xb4,0x00,0x24,0x11,0x00,0x12,
0x8e,0x44,0x00,0x00,0x26,0x31,0xff,0xff,0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,
0x10,0x40,0x00,0x03,0x26,0x52,0x00,0x04,0x0c,0x00,0x18,0xd0,0x00,0x00,0x00,0x00,
0x06,0x21,0xff,0xf7,0x24,0x02,0xff,0xdf,0x02,0x02,0x80,0x24,0x3c,0x01,0xb0,0x03,
0x0c,0x00,0x13,0x1c,0xac,0x30,0x00,0x00,0x08,0x00,0x12,0xa8,0x00,0x00,0x00,0x00,
0x8f,0x85,0x8f,0xe0,0x08,0x00,0x12,0xbe,0x00,0x00,0x00,0x00,0x24,0x02,0xff,0x95,
0x3c,0x03,0xb0,0x03,0x02,0x02,0x80,0x24,0x34,0x63,0x00,0x30,0x3c,0x01,0xb0,0x03,
0xac,0x30,0x00,0x00,0x0c,0x00,0x12,0xe5,0xac,0x60,0x00,0x00,0x08,0x00,0x12,0xa8,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x50,0x08,0x00,0x12,0xa8,
0xac,0x46,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4b,0x94,0x3c,0x0b,0xb0,0x03,
0xad,0x6a,0x00,0x20,0x3c,0x08,0x80,0x01,0x25,0x08,0x00,0x00,0x3c,0x09,0x80,0x01,
0x25,0x29,0x03,0x50,0x11,0x09,0x00,0x10,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,
0x25,0x4a,0x4b,0xbc,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x08,0xb0,0x06,
0x35,0x08,0x80,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,
0x00,0x00,0x00,0x00,0x31,0x29,0x00,0x01,0x00,0x00,0x00,0x00,0x24,0x01,0x00,0x01,
0x15,0x21,0xff,0xf2,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4b,0xf8,
0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0x3c,0x02,0xb0,0x03,0x8c,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x34,0x63,0x00,0x40,0x00,0x00,0x00,0x00,0xac,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0x24,0x3c,0x0b,0xb0,0x03,
0xad,0x6a,0x00,0x20,0x3c,0x02,0x80,0x01,0x24,0x42,0x00,0x00,0x3c,0x03,0x80,0x01,
0x24,0x63,0x03,0x50,0x3c,0x04,0xb0,0x00,0x8c,0x85,0x00,0x00,0x00,0x00,0x00,0x00,
0xac,0x45,0x00,0x00,0x24,0x42,0x00,0x04,0x24,0x84,0x00,0x04,0x00,0x43,0x08,0x2a,
0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,0x0c,0x00,0x13,0x1c,0x00,0x00,0x00,0x00,
0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0x70,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
0x3c,0x02,0x80,0x01,0x24,0x42,0x03,0x50,0x3c,0x03,0x80,0x01,0x24,0x63,0x3f,0x24,
0xac,0x40,0x00,0x00,0xac,0x40,0x00,0x04,0xac,0x40,0x00,0x08,0xac,0x40,0x00,0x0c,
0x24,0x42,0x00,0x10,0x00,0x43,0x08,0x2a,0x14,0x20,0xff,0xf9,0x00,0x00,0x00,0x00,
0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0xb0,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,
0x3c,0x1c,0x80,0x01,0x27,0x9c,0x7f,0xf0,0x27,0x9d,0x8b,0xe0,0x00,0x00,0x00,0x00,
0x27,0x9d,0x8f,0xc8,0x3c,0x0a,0x80,0x00,0x25,0x4a,0x4c,0xd4,0x3c,0x0b,0xb0,0x03,
0xad,0x6a,0x00,0x20,0x40,0x80,0x68,0x00,0x40,0x08,0x60,0x00,0x00,0x00,0x00,0x00,
0x35,0x08,0xff,0x01,0x40,0x88,0x60,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x15,0x62,
0x00,0x00,0x00,0x00,0x24,0x84,0xf8,0x00,0x30,0x87,0x00,0x03,0x00,0x04,0x30,0x40,
0x00,0xc7,0x20,0x23,0x3c,0x02,0xb0,0x0a,0x27,0xbd,0xff,0xe0,0x24,0x03,0xff,0xff,
0x00,0x82,0x20,0x21,0xaf,0xb1,0x00,0x14,0xac,0x83,0x10,0x00,0xaf,0xbf,0x00,0x18,
0xaf,0xb0,0x00,0x10,0x00,0xa0,0x88,0x21,0x24,0x03,0x00,0x01,0x8c,0x82,0x10,0x00,
0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0xc7,0x10,0x23,0x3c,0x03,0xb0,0x0a,
0x00,0x43,0x10,0x21,0x8c,0x50,0x00,0x00,0x0c,0x00,0x13,0x99,0x02,0x20,0x20,0x21,
0x02,0x11,0x80,0x24,0x00,0x50,0x80,0x06,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x18,
0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x27,0xbd,0xff,0xd8,
0xaf,0xb2,0x00,0x18,0x00,0xa0,0x90,0x21,0x24,0x05,0xff,0xff,0xaf,0xb3,0x00,0x1c,
0xaf,0xbf,0x00,0x20,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0x00,0xc0,0x98,0x21,
0x12,0x45,0x00,0x23,0x24,0x84,0xf8,0x00,0x30,0x83,0x00,0x03,0x00,0x04,0x10,0x40,
0x00,0x40,0x88,0x21,0x00,0x60,0x20,0x21,0x00,0x43,0x10,0x23,0x3c,0x03,0xb0,0x0a,
0x00,0x43,0x10,0x21,0xac,0x45,0x10,0x00,0x00,0x40,0x18,0x21,0x24,0x05,0x00,0x01,
0x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x14,0x45,0xff,0xfd,0x3c,0x02,0xb0,0x0a,
0x02,0x24,0x88,0x23,0x02,0x22,0x88,0x21,0x8e,0x30,0x00,0x00,0x0c,0x00,0x13,0x99,
0x02,0x40,0x20,0x21,0x00,0x12,0x18,0x27,0x02,0x03,0x80,0x24,0x00,0x53,0x10,0x04,
0x02,0x02,0x80,0x25,0xae,0x30,0x00,0x00,0x24,0x03,0x00,0x01,0x8e,0x22,0x10,0x00,
0x00,0x00,0x00,0x00,0x14,0x43,0xff,0xfd,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x20,
0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,
0x30,0x82,0x00,0x03,0x00,0x04,0x18,0x40,0x00,0x62,0x18,0x23,0x3c,0x04,0xb0,0x0a,
0x00,0x64,0x18,0x21,0xac,0x66,0x00,0x00,0x24,0x04,0x00,0x01,0x8c,0x62,0x10,0x00,
0x00,0x00,0x00,0x00,0x14,0x44,0xff,0xfd,0x00,0x00,0x00,0x00,0x08,0x00,0x13,0x87,
0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x21,0x00,0x64,0x10,0x06,0x30,0x42,0x00,0x01,
0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,0x24,0x63,0x00,0x01,0x2c,0x62,0x00,0x20,
0x14,0x40,0xff,0xf9,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,
0x27,0xbd,0xff,0xe0,0x3c,0x03,0xb0,0x05,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,
0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,0x00,0x80,0x90,0x21,0x00,0xa0,0x80,0x21,
0x00,0xc0,0x88,0x21,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0x01,0x14,0x40,0xff,0xfc,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0xc0,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x3c,0x02,0xc0,0x00,0x00,0x10,0x1c,0x00,
0x34,0x42,0x04,0x00,0x3c,0x04,0xb0,0x05,0x3c,0x05,0xb0,0x05,0x24,0x63,0x16,0x09,
0x02,0x22,0x10,0x21,0x34,0x84,0x04,0x20,0x34,0xa5,0x04,0x24,0x3c,0x06,0xb0,0x05,
0xac,0x83,0x00,0x00,0x24,0x07,0x00,0x01,0xac,0xa2,0x00,0x00,0x34,0xc6,0x02,0x28,
0x24,0x02,0x00,0x20,0xae,0x47,0x00,0x3c,0x24,0x04,0x08,0x24,0xa0,0xc2,0x00,0x00,
0x3c,0x05,0x00,0xc0,0xa2,0x47,0x00,0x11,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,
0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0xc0,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,
0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x20,0x24,0x02,0x00,0x06,0xac,0x82,0x00,0x0c,0xa0,0x80,0x00,0x50,
0xac,0x80,0x00,0x00,0xac,0x80,0x00,0x04,0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x14,
0xac,0x80,0x00,0x18,0xac,0x80,0x00,0x1c,0xa4,0x80,0x00,0x20,0xac,0x80,0x00,0x24,
0xac,0x80,0x00,0x28,0xac,0x80,0x00,0x2c,0xa0,0x80,0x00,0x30,0xa0,0x80,0x00,0x31,
0xac,0x80,0x00,0x34,0xac,0x80,0x00,0x38,0xa0,0x80,0x00,0x3c,0xac,0x82,0x00,0x10,
0xa0,0x80,0x00,0x44,0xac,0x80,0x00,0x48,0x03,0xe0,0x00,0x08,0xac,0x80,0x00,0x4c,
0x3c,0x04,0xb0,0x06,0x34,0x84,0x80,0x00,0x8c,0x83,0x00,0x00,0x3c,0x02,0x12,0x00,
0x3c,0x05,0xb0,0x03,0x00,0x62,0x18,0x25,0x34,0xa5,0x00,0x8b,0x24,0x02,0xff,0x80,
0xac,0x83,0x00,0x00,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x00,0x3c,0x04,0xb0,0x03,
0x34,0x84,0x00,0x0b,0x24,0x02,0x00,0x22,0x3c,0x05,0xb0,0x01,0x3c,0x06,0x45,0x67,
0x3c,0x0a,0xb0,0x09,0xa0,0x82,0x00,0x00,0x34,0xa5,0x00,0x04,0x34,0xc6,0x89,0xaa,
0x35,0x4a,0x00,0x04,0x24,0x02,0x01,0x23,0x3c,0x0b,0xb0,0x09,0x3c,0x07,0x01,0x23,
0x3c,0x0c,0xb0,0x09,0x3c,0x01,0xb0,0x01,0xac,0x20,0x00,0x00,0x27,0xbd,0xff,0xe0,
0xac,0xa0,0x00,0x00,0x35,0x6b,0x00,0x08,0x3c,0x01,0xb0,0x09,0xac,0x26,0x00,0x00,
0x34,0xe7,0x45,0x66,0xa5,0x42,0x00,0x00,0x35,0x8c,0x00,0x0c,0x24,0x02,0xcd,0xef,
0x3c,0x0d,0xb0,0x09,0x3c,0x08,0xcd,0xef,0x3c,0x0e,0xb0,0x09,0xad,0x67,0x00,0x00,
0xaf,0xb7,0x00,0x1c,0xa5,0x82,0x00,0x00,0xaf,0xb6,0x00,0x18,0xaf,0xb5,0x00,0x14,
0xaf,0xb4,0x00,0x10,0xaf,0xb3,0x00,0x0c,0xaf,0xb2,0x00,0x08,0xaf,0xb1,0x00,0x04,
0xaf,0xb0,0x00,0x00,0x35,0xad,0x00,0x10,0x35,0x08,0x01,0x22,0x35,0xce,0x00,0x14,
0x24,0x02,0x89,0xab,0x3c,0x0f,0xb0,0x09,0x3c,0x09,0x89,0xab,0x3c,0x10,0xb0,0x09,
0x3c,0x11,0xb0,0x09,0x3c,0x12,0xb0,0x09,0x3c,0x13,0xb0,0x09,0x3c,0x14,0xb0,0x09,
0x3c,0x15,0xb0,0x09,0x3c,0x16,0xb0,0x09,0x3c,0x17,0xb0,0x09,0xad,0xa8,0x00,0x00,
0x24,0x03,0xff,0xff,0xa5,0xc2,0x00,0x00,0x35,0xef,0x00,0x18,0x35,0x29,0xcd,0xee,
0x36,0x10,0x00,0x1c,0x36,0x31,0x00,0x20,0x36,0x52,0x00,0x24,0x36,0x73,0x00,0x28,
0x36,0x94,0x00,0x2c,0x36,0xb5,0x00,0x30,0x36,0xd6,0x00,0x34,0x36,0xf7,0x00,0x38,
0x24,0x02,0x45,0x67,0xad,0xe9,0x00,0x00,0xa6,0x02,0x00,0x00,0xae,0x23,0x00,0x00,
0x8f,0xb0,0x00,0x00,0xa6,0x43,0x00,0x00,0x8f,0xb1,0x00,0x04,0xae,0x63,0x00,0x00,
0x8f,0xb2,0x00,0x08,0xa6,0x83,0x00,0x00,0x8f,0xb3,0x00,0x0c,0xae,0xa3,0x00,0x00,
0x8f,0xb4,0x00,0x10,0xa6,0xc3,0x00,0x00,0x8f,0xb5,0x00,0x14,0xae,0xe3,0x00,0x00,
0x7b,0xb6,0x00,0xfc,0x3c,0x18,0xb0,0x09,0x37,0x18,0x00,0x3c,0xa7,0x03,0x00,0x00,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
0x34,0x63,0x00,0x20,0x24,0x42,0x51,0x48,0xac,0x62,0x00,0x00,0x8c,0x83,0x00,0x34,
0x34,0x02,0xff,0xff,0x00,0x43,0x10,0x2a,0x14,0x40,0x01,0x04,0x00,0x80,0x28,0x21,
0x8c,0x86,0x00,0x08,0x24,0x02,0x00,0x03,0x10,0xc2,0x00,0xf7,0x00,0x00,0x00,0x00,
0x8c,0xa2,0x00,0x2c,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x4f,0x24,0x02,0x00,0x06,
0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0xff,0x14,0x40,0x00,0xdd,0xac,0xa2,0x00,0x2c,0x24,0x02,0x00,0x01,
0x10,0xc2,0x00,0xdc,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xc2,0x00,0xca,
0x00,0x00,0x00,0x00,0x8c,0xa7,0x00,0x04,0x24,0x02,0x00,0x02,0x10,0xe2,0x00,0xc0,
0x00,0x00,0x00,0x00,0x8c,0xa2,0x00,0x14,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x09,
0x24,0x02,0x00,0x01,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x05,0xac,0xa2,0x00,0x14,
0x24,0x02,0x00,0x01,0xac,0xa2,0x00,0x00,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x14,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
0x04,0x61,0x00,0x19,0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2e,
0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0x12,
0x3c,0x02,0xb0,0x03,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x42,0x90,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x0c,0x3c,0x02,0xb0,0x03,0x80,0xa2,0x00,0x50,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x08,0x3c,0x02,0xb0,0x03,0x14,0xc0,0x00,0x07,
0x34,0x42,0x00,0x3f,0x24,0x02,0x00,0x0e,0x24,0x03,0x00,0x01,0xac,0xa2,0x00,0x00,
0x03,0xe0,0x00,0x08,0xa0,0xa3,0x00,0x50,0x34,0x42,0x00,0x3f,0x90,0x44,0x00,0x00,
0x24,0x03,0x00,0x01,0x10,0x64,0x00,0x7f,0x3c,0x03,0xb0,0x05,0x80,0xa2,0x00,0x31,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x3c,0x02,0xb0,0x06,0x34,0x42,0x80,0x18,
0x8c,0x43,0x00,0x00,0x3c,0x04,0xf0,0x00,0x3c,0x02,0x80,0x00,0x00,0x64,0x18,0x24,
0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x09,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x00,
0x8c,0xa2,0x00,0x40,0x00,0x00,0x00,0x00,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
0x10,0x60,0x00,0x09,0x3c,0x03,0xb0,0x03,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2c,
0x8c,0x43,0x00,0x00,0x3c,0x04,0x00,0x02,0x00,0x64,0x18,0x24,0x14,0x60,0xff,0xf2,
0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03,0x34,0x63,0x02,0x01,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x80,0x10,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,
0x8c,0xa3,0x00,0x0c,0x00,0x00,0x00,0x00,0xac,0xa3,0x00,0x10,0x3c,0x02,0xb0,0x03,
0x90,0x42,0x02,0x01,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x0f,0xac,0xa2,0x00,0x0c,
0x90,0xa3,0x00,0x0f,0x24,0x02,0x00,0x0d,0x3c,0x01,0xb0,0x03,0x08,0x00,0x14,0xb2,
0xa0,0x23,0x02,0x01,0x3c,0x02,0xb0,0x09,0x34,0x42,0x01,0x80,0x90,0x44,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x04,0x1e,0x00,0x00,0x03,0x1e,0x03,0x10,0x60,0x00,0x15,
0xa0,0xa4,0x00,0x44,0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x0b,0x24,0x02,0x00,0x02,
0x10,0x62,0x00,0x03,0x24,0x03,0x00,0x0d,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x8c,0xa2,0x00,0x0c,0xac,0xa3,0x00,0x00,0x24,0x03,0x00,0x04,0xac,0xa2,0x00,0x10,
0x03,0xe0,0x00,0x08,0xac,0xa3,0x00,0x0c,0x24,0x02,0x00,0x0d,0xac,0xa2,0x00,0x00,
0x24,0x03,0x00,0x04,0x24,0x02,0x00,0x06,0xac,0xa3,0x00,0x10,0x03,0xe0,0x00,0x08,
0xac,0xa2,0x00,0x0c,0x8c,0xa3,0x00,0x38,0x24,0x04,0x00,0x01,0x10,0x64,0x00,0x2d,
0x24,0x02,0x00,0x02,0x10,0x60,0x00,0x19,0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x10,
0x24,0x02,0x00,0x04,0x10,0x62,0x00,0x04,0x00,0x00,0x00,0x00,0xac,0xa0,0x00,0x38,
0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x00,0x10,0xe4,0x00,0x07,0x24,0x02,0x00,0x03,
0x80,0xa2,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x02,0x18,0x0b,0xac,0xa3,0x00,0x00,
0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x38,0x08,0x00,0x15,0x04,0xac,0xa2,0x00,0x00,
0x10,0xe4,0x00,0x02,0x24,0x02,0x00,0x03,0x24,0x02,0x00,0x0c,0xac,0xa2,0x00,0x00,
0x24,0x02,0x00,0x04,0x03,0xe0,0x00,0x08,0xac,0xa2,0x00,0x38,0x10,0xe4,0x00,0x0e,
0x3c,0x03,0xb0,0x06,0x34,0x63,0x80,0x24,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0xff,0x10,0x40,0x00,0x06,0xac,0xa2,0x00,0x18,0x24,0x02,0x00,0x02,
0xac,0xa2,0x00,0x00,0xac,0xa0,0x00,0x18,0x08,0x00,0x15,0x0d,0x24,0x02,0x00,0x01,
0x08,0x00,0x15,0x1a,0xac,0xa0,0x00,0x00,0x24,0x02,0x00,0x03,0x08,0x00,0x15,0x1a,
0xac,0xa2,0x00,0x00,0x24,0x03,0x00,0x0b,0xac,0xa2,0x00,0x38,0x03,0xe0,0x00,0x08,
0xac,0xa3,0x00,0x00,0x34,0x63,0x02,0x2e,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x7d,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x42,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x60,0xff,0x78,0x00,0x00,0x00,0x00,
0x10,0xc0,0xff,0x81,0x24,0x02,0x00,0x0e,0x08,0x00,0x14,0xa7,0x00,0x00,0x00,0x00,
0x80,0xa2,0x00,0x30,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x3e,0x24,0x02,0x00,0x04,
0x08,0x00,0x14,0xb2,0x00,0x00,0x00,0x00,0x84,0xa2,0x00,0x20,0x00,0x00,0x00,0x00,
0x10,0x40,0xff,0x75,0x24,0x02,0x00,0x06,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,
0x00,0x60,0x10,0x21,0x14,0x40,0xff,0x2b,0xa4,0xa3,0x00,0x20,0x08,0x00,0x14,0xb2,
0x24,0x02,0x00,0x06,0x8c,0xa2,0x00,0x1c,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0x66,
0x24,0x02,0x00,0x05,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0x10,0x40,0xff,0x1b,0xac,0xa2,0x00,0x1c,
0x08,0x00,0x14,0xb2,0x24,0x02,0x00,0x05,0x3c,0x02,0xb0,0x05,0x8c,0x42,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x42,0x30,0x42,0x00,0x01,0x14,0x40,0xff,0x56,
0x24,0x02,0x00,0x06,0x08,0x00,0x14,0x60,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x0a,
0x03,0xe0,0x00,0x08,0xac,0x82,0x00,0x00,0x27,0xbd,0xff,0xd8,0xaf,0xb0,0x00,0x10,
0x27,0x90,0x86,0x58,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,
0x0c,0x00,0x29,0xd5,0xaf,0xb1,0x00,0x14,0xaf,0x90,0x8f,0xe0,0x48,0x02,0x00,0x00,
0x0c,0x00,0x13,0xf0,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x1f,0x02,0x00,0x20,0x21,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3a,0x94,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
0xa3,0x83,0x8f,0xe4,0x0c,0x00,0x00,0x34,0x00,0x00,0x00,0x00,0x0c,0x00,0x13,0xfb,
0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x98,0x0c,0x00,0x27,0x59,0x00,0x00,0x00,0x00,
0x93,0x84,0x80,0x10,0x0c,0x00,0x21,0x3f,0x00,0x00,0x00,0x00,0x27,0x84,0x89,0x18,
0x0c,0x00,0x06,0xe5,0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x39,0x00,0x00,0x00,0x00,
0x27,0x84,0x84,0x40,0x0c,0x00,0x13,0xd9,0x00,0x00,0x00,0x00,0x27,0x82,0x89,0x4c,
0xaf,0x82,0x84,0x80,0x0c,0x00,0x00,0x5f,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
0x34,0x63,0x01,0x08,0x3c,0x04,0xb0,0x09,0x3c,0x05,0xb0,0x09,0x8c,0x66,0x00,0x00,
0x34,0x84,0x01,0x68,0x34,0xa5,0x01,0x40,0x24,0x02,0xc8,0x80,0x24,0x03,0x00,0x0a,
0xa4,0x82,0x00,0x00,0xa4,0xa3,0x00,0x00,0x3c,0x04,0xb0,0x03,0x8c,0x82,0x00,0x00,
0x8f,0x85,0x84,0x40,0xaf,0x86,0x84,0x38,0x34,0x42,0x00,0x20,0xac,0x82,0x00,0x00,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x58,0x8c,0x43,0x00,0x00,0x2c,0xa4,0x00,0x11,
0x34,0x63,0x01,0x00,0xac,0x43,0x00,0x00,0x10,0x80,0xff,0xfa,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0x80,0x01,0x00,0x05,0x10,0x80,0x24,0x63,0x02,0x00,0x00,0x43,0x10,0x21,
0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,
0x27,0x84,0x84,0x98,0x0c,0x00,0x26,0x8e,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x40,
0x0c,0x00,0x14,0x52,0x00,0x00,0x00,0x00,0x93,0x83,0x81,0xf1,0x24,0x02,0x00,0x01,
0x10,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0x40,0x8f,0x82,0x84,0x74,
0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x01,0xaf,0x82,0x84,0x74,0x08,0x00,0x15,0x9d,
0x3c,0x02,0xb0,0x03,0x27,0x84,0x84,0x98,0x0c,0x00,0x27,0x0d,0x00,0x00,0x00,0x00,
0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x98,0x0c,0x00,0x28,0xdd,
0x00,0x00,0x00,0x00,0xa3,0x82,0x84,0x71,0x8f,0x82,0x84,0x74,0xaf,0x80,0x84,0x40,
0x24,0x42,0x00,0x01,0xaf,0x82,0x84,0x74,0x08,0x00,0x15,0x9c,0x00,0x00,0x28,0x21,
0x27,0x84,0x86,0x58,0x0c,0x00,0x19,0x5b,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,
0x14,0x40,0x00,0x05,0x3c,0x03,0xb0,0x05,0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x44,
0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x6c,0x14,0x40,0x00,0x20,
0x24,0x02,0x00,0x01,0x8f,0x84,0x84,0x48,0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x20,
0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x54,0x14,0x40,0x00,0x15,0x24,0x02,0x00,0x01,
0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x07,0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x03,
0x24,0x02,0x00,0x01,0xaf,0x82,0x84,0x44,0xaf,0x85,0x84,0x40,0x08,0x00,0x15,0xb6,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,
0xa7,0x83,0x84,0x60,0x14,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0xaf,0x82,0x84,0x44,0xaf,0x80,0x84,0x40,0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,
0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x5c,0x14,0x40,0xff,0xf5,0x24,0x02,0x00,0x01,
0x08,0x00,0x15,0xe1,0x3c,0x03,0xb0,0x09,0x27,0x84,0x86,0x58,0x0c,0x00,0x1a,0xd1,
0x00,0x00,0x00,0x00,0x83,0x82,0x84,0x70,0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xec,
0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,0x34,0x63,0x04,0x50,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x6c,0x14,0x40,0xff,0xe4,
0x24,0x02,0x00,0x02,0x8f,0x84,0x84,0x48,0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x12,
0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x04,0x00,0x00,0x00,0x00,0x24,0x05,0x00,0x04,
0x08,0x00,0x15,0xed,0x24,0x02,0x00,0x02,0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,
0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,
0x00,0x60,0x10,0x21,0xa7,0x83,0x84,0x60,0x14,0x40,0xff,0xf4,0x00,0x00,0x00,0x00,
0x08,0x00,0x15,0xfc,0x24,0x02,0x00,0x02,0x3c,0x03,0xb0,0x05,0x34,0x63,0x02,0x2c,
0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xff,0xaf,0x82,0x84,0x5c,
0x14,0x40,0xff,0xf7,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0x1d,0x24,0x02,0x00,0x02,
0x27,0x84,0x89,0x18,0x0c,0x00,0x0b,0x55,0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x44,
0xaf,0x82,0x84,0x5c,0x38,0x64,0x00,0x02,0x00,0x04,0x18,0x0a,0xaf,0x83,0x84,0x44,
0x14,0x40,0xff,0xad,0x24,0x05,0x00,0x05,0x8f,0x82,0x89,0x58,0xaf,0x80,0x84,0x40,
0x10,0x40,0x00,0x02,0x24,0x04,0x00,0x01,0xaf,0x84,0x84,0x48,0x93,0x82,0x89,0x66,
0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x6c,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x05,
0x34,0x42,0x00,0x08,0x8c,0x43,0x00,0x00,0x3c,0x04,0x20,0x00,0x00,0x64,0x18,0x24,
0x10,0x60,0xff,0x65,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xa0,
0x8c,0x43,0x00,0x00,0x3c,0x04,0x80,0x00,0xaf,0x80,0x89,0x40,0x24,0x63,0x00,0x01,
0xac,0x43,0x00,0x00,0x3c,0x01,0xb0,0x05,0xac,0x24,0x00,0x08,0xaf,0x80,0x89,0x3c,
0xaf,0x80,0x89,0x44,0xaf,0x80,0x89,0x48,0xaf,0x80,0x89,0x54,0xaf,0x80,0x89,0x4c,
0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x83,0x82,0x84,0x90,0x00,0x00,0x00,0x00,
0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x20,0xaf,0x82,0x84,0x5c,0x8f,0x85,0x84,0x5c,
0x27,0x84,0x89,0x18,0x0c,0x00,0x0d,0x30,0x00,0x00,0x00,0x00,0x00,0x02,0x1e,0x00,
0xa3,0x82,0x84,0x70,0xaf,0x80,0x84,0x5c,0x10,0x60,0xff,0x8e,0x00,0x00,0x00,0x00,
0x3c,0x02,0xb0,0x05,0x34,0x42,0x02,0x2e,0x90,0x43,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x63,0x00,0x01,0x30,0x63,0x00,0xff,0x00,0x60,0x10,0x21,0xa7,0x83,0x84,0x60,
0x10,0x40,0x00,0x04,0x24,0x04,0x00,0x02,0xaf,0x84,0x84,0x48,0x08,0x00,0x15,0xfd,
0x00,0x00,0x00,0x00,0x08,0x00,0x15,0xee,0x24,0x05,0x00,0x06,0x27,0x84,0x84,0x40,
0x27,0x85,0x89,0x18,0x0c,0x00,0x0d,0xfd,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x64,
0xaf,0x80,0x84,0x6c,0x14,0x40,0x00,0x19,0x00,0x40,0x18,0x21,0x8f,0x82,0x84,0x68,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x15,0x24,0x02,0x00,0x02,0x8f,0x83,0x84,0x48,
0x00,0x00,0x00,0x00,0x10,0x62,0x00,0x0b,0x3c,0x02,0x40,0x00,0x8f,0x83,0x84,0x44,
0x24,0x02,0x00,0x01,0x10,0x62,0x00,0x02,0x24,0x05,0x00,0x03,0x24,0x05,0x00,0x06,
0xaf,0x85,0x84,0x40,0x24,0x04,0x00,0x03,0xaf,0x84,0x84,0x48,0x08,0x00,0x15,0xb6,
0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x14,0x3c,0x01,0xb0,0x05,0xac,0x22,0x00,0x00,
0xaf,0x80,0x84,0x40,0x08,0x00,0x16,0x96,0x24,0x04,0x00,0x03,0x10,0x60,0x00,0x10,
0x00,0x00,0x00,0x00,0x27,0x85,0x89,0x18,0x27,0x84,0x84,0x40,0x0c,0x00,0x0e,0x21,
0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x44,0x24,0x02,0x00,0x01,0xa3,0x80,0x84,0x70,
0xaf,0x80,0x84,0x48,0x10,0x62,0x00,0x02,0x24,0x05,0x00,0x03,0x24,0x05,0x00,0x04,
0xaf,0x85,0x84,0x40,0xaf,0x80,0x84,0x64,0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,
0x83,0x82,0x84,0x90,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,
0x27,0x84,0x89,0x18,0x0c,0x00,0x10,0x69,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x44,
0xa3,0x80,0x84,0x70,0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x48,0x14,0x40,0x00,0x03,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0xaf,0x82,0x84,0x44,0xaf,0x80,0x84,0x68,
0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x40,0x27,0x85,0x89,0x18,
0x0c,0x00,0x0e,0x21,0x00,0x00,0x00,0x00,0x8f,0x82,0x84,0x44,0xa3,0x80,0x84,0x70,
0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x48,0x14,0x40,0xfe,0xeb,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x02,0xaf,0x82,0x84,0x44,0x08,0x00,0x15,0xb6,0x00,0x00,0x00,0x00,
0x27,0x84,0x89,0x18,0x0c,0x00,0x10,0x69,0x00,0x00,0x00,0x00,0x08,0x00,0x16,0xc6,
0x00,0x00,0x00,0x00,0x27,0x84,0x84,0x98,0x0c,0x00,0x29,0x73,0x00,0x00,0x00,0x00,
0x08,0x00,0x15,0xc5,0x00,0x00,0x00,0x00,0x0c,0x00,0x24,0x05,0x00,0x00,0x00,0x00,
0x0c,0x00,0x26,0xff,0x00,0x00,0x00,0x00,0x0c,0x00,0x18,0x11,0x00,0x00,0x00,0x00,
0x93,0x83,0xbc,0x18,0x00,0x00,0x00,0x00,0x14,0x60,0x00,0x2b,0x3c,0x02,0xb0,0x03,
0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x83,0xbc,0x10,0x8f,0x82,0xbc,0x14,
0x00,0x83,0x18,0x23,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x23,0x3c,0x02,0xb0,0x03,
0x24,0x04,0x05,0xa0,0x34,0x42,0x01,0x18,0x8c,0x42,0x00,0x00,0x0c,0x00,0x06,0xd1,
0x00,0x00,0x00,0x00,0x24,0x04,0x05,0xa4,0x0c,0x00,0x06,0xd1,0x00,0x02,0x84,0x02,
0x30,0x51,0xff,0xff,0x24,0x04,0x05,0xa8,0x00,0x02,0x94,0x02,0x0c,0x00,0x06,0xd1,
0x3a,0x10,0xff,0xff,0x3a,0x31,0xff,0xff,0x30,0x42,0xff,0xff,0x2e,0x10,0x00,0x01,
0x2e,0x31,0x00,0x01,0x3a,0x52,0xff,0xff,0x02,0x11,0x80,0x25,0x2e,0x52,0x00,0x01,
0x38,0x42,0xff,0xff,0x02,0x12,0x80,0x25,0x2c,0x42,0x00,0x01,0x02,0x02,0x80,0x25,
0x16,0x00,0x00,0x02,0x24,0x04,0x00,0x02,0x00,0x00,0x20,0x21,0x0c,0x00,0x05,0x6e,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0xaf,0x83,0xbc,0x10,0x0c,0x00,0x01,0xe9,0x00,0x00,0x00,0x00,
0xaf,0x80,0x84,0x40,0xaf,0x80,0x84,0x74,0x08,0x00,0x15,0x9c,0x00,0x00,0x28,0x21,
0x27,0x90,0xb4,0x00,0x24,0x11,0x00,0x12,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00,
0x90,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x03,0x00,0x00,0x00,0x00,
0x0c,0x00,0x18,0xd0,0x00,0x00,0x00,0x00,0x26,0x31,0xff,0xff,0x06,0x21,0xff,0xf6,
0x26,0x10,0x00,0x04,0xaf,0x80,0x84,0x40,0x08,0x00,0x15,0xb7,0x00,0x00,0x28,0x21,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x08,0x8c,0x44,0x00,0x00,0x8f,0x82,0x84,0x38,
0x00,0x04,0x19,0xc2,0x00,0x02,0x11,0xc2,0x10,0x62,0xff,0xf6,0x00,0x00,0x00,0x00,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x01,0x02,0x90,0x43,0x00,0x00,0x3c,0x12,0xb0,0x05,
0xaf,0x84,0x84,0x38,0x30,0x63,0x00,0xff,0x00,0x03,0x11,0x40,0x00,0x43,0x10,0x23,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x00,0x02,0x99,0x00,0x00,0x00,0x88,0x21,
0x36,0x52,0x02,0x2c,0x27,0x90,0xb4,0x00,0x8e,0x04,0x00,0x00,0x00,0x00,0x00,0x00,
0x90,0x83,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x62,0x00,0x03,0x10,0x40,0x00,0x06,
0x30,0x62,0x00,0x1c,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x8f,0x85,0x84,0x38,
0x0c,0x00,0x1e,0x94,0x02,0x60,0x30,0x21,0x8e,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0xff,0x14,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,0x26,0x31,0x00,0x01,
0x2a,0x22,0x00,0x13,0x14,0x40,0xff,0xec,0x26,0x10,0x00,0x04,0x08,0x00,0x17,0x21,
0x00,0x00,0x00,0x00,0x8f,0x84,0x84,0x4c,0x27,0x85,0x89,0x18,0x0c,0x00,0x17,0xa4,
0x00,0x00,0x00,0x00,0x8f,0x83,0x84,0x4c,0x24,0x02,0x00,0x04,0x14,0x62,0xfe,0xa5,
0x00,0x00,0x00,0x00,0x08,0x00,0x15,0xee,0x24,0x05,0x00,0x05,0x3c,0x02,0xb0,0x03,
0x34,0x42,0x00,0x3f,0x90,0x44,0x00,0x00,0x24,0x03,0x00,0x01,0x10,0x64,0x00,0x08,
0x00,0x00,0x00,0x00,0x27,0x84,0x89,0x18,0x0c,0x00,0x24,0x2c,0x00,0x00,0x00,0x00,
0x24,0x05,0x00,0x05,0xaf,0x85,0x84,0x40,0x08,0x00,0x15,0xb7,0x00,0x00,0x00,0x00,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x14,0x8c,0x44,0x00,0x00,0x0c,0x00,0x24,0x49,
0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x65,0x24,0x05,0x00,0x05,0x8f,0x82,0x89,0x4c,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,0x00,0x00,0x00,0x00,0x8f,0x84,0xb4,0x40,
0xaf,0x80,0x89,0x4c,0x94,0x85,0x00,0x14,0x0c,0x00,0x1b,0x66,0x00,0x00,0x00,0x00,
0x93,0x82,0x8b,0x71,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x10,0x40,0x00,0x03,
0x00,0x00,0x00,0x00,0x0c,0x00,0x01,0x57,0x00,0x00,0x20,0x21,0x8f,0x84,0xb4,0x40,
0x0c,0x00,0x18,0xd0,0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x21,0x00,0x00,0x00,0x00,
0x3c,0x02,0xff,0x90,0x27,0xbd,0xff,0xe8,0x00,0x80,0x18,0x21,0x34,0x42,0x00,0x01,
0x27,0x84,0x89,0x18,0x10,0x62,0x00,0x05,0xaf,0xbf,0x00,0x10,0x8f,0xbf,0x00,0x10,
0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x06,0xe5,
0x00,0x00,0x00,0x00,0x27,0x84,0x86,0x58,0x0c,0x00,0x18,0x1f,0x00,0x00,0x00,0x00,
0x27,0x84,0x84,0x40,0x0c,0x00,0x13,0xd9,0x00,0x00,0x00,0x00,0x08,0x00,0x17,0x8b,
0x00,0x00,0x00,0x00,0x8f,0x82,0x89,0x58,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,
0x00,0x00,0x18,0x21,0x8f,0x82,0x84,0x48,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x02,
0x00,0x00,0x00,0x00,0x24,0x03,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,
0x27,0xbd,0xff,0xe0,0x3c,0x06,0xb0,0x03,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,
0x34,0xc6,0x00,0x5f,0xaf,0xbf,0x00,0x18,0x90,0xc3,0x00,0x00,0x3c,0x07,0xb0,0x03,
0x34,0xe7,0x00,0x5d,0x34,0x63,0x00,0x01,0x3c,0x09,0xb0,0x03,0x24,0x02,0x00,0x01,
0xa0,0xc3,0x00,0x00,0x00,0x80,0x80,0x21,0xa0,0xe2,0x00,0x00,0x00,0xa0,0x88,0x21,
0x35,0x29,0x00,0x5e,0x00,0xe0,0x40,0x21,0x24,0x04,0x00,0x01,0x91,0x22,0x00,0x00,
0x91,0x03,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x83,0x00,0x03,0x30,0x42,0x00,0x01,
0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x04,0x12,0x02,0x00,0x2c,
0x24,0x05,0x0f,0x00,0x24,0x02,0x00,0x06,0x12,0x02,0x00,0x08,0x24,0x05,0x00,0x0f,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x02,0x00,0xa0,0x50,0x00,0x00,0x8f,0xbf,0x00,0x18,
0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x24,0x04,0x0c,0x04,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x0d,0x04,0x24,0x05,0x00,0x0f,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x80,0x24,0x05,0x1e,0x00,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x8c,0x24,0x05,0x0f,0x00,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x0f,0x24,0x04,0x08,0x24,0x3c,0x05,0x00,0x30,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x2c,0x3c,0x05,0x00,0x30,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x34,0x3c,0x05,0x00,0x30,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x24,0x04,0x08,0x3c,0x3c,0x05,0x00,0x30,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x08,0x00,0x17,0xc5,0x3c,0x02,0xb0,0x03,
0x24,0x04,0x08,0x8c,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x80,
0x24,0x05,0x1e,0x00,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x0c,0x04,
0x24,0x05,0x00,0x0f,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x0d,0x04,
0x24,0x05,0x00,0x0f,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x04,0x24,0x04,0x08,0x24,
0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x2c,
0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x03,0x24,0x04,0x08,0x34,
0x3c,0x05,0x00,0x30,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x02,0x3c,0x05,0x00,0x30,
0x24,0x06,0x00,0x03,0x0c,0x00,0x13,0x5f,0x24,0x04,0x08,0x3c,0x02,0x20,0x20,0x21,
0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa4,0x24,0x06,0x01,0x07,0x08,0x00,0x17,0xc5,
0x3c,0x02,0xb0,0x03,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x73,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x02,0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,
0xa3,0x80,0x81,0x58,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0xa3,0x82,0x81,0x58,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
0x3c,0x02,0x80,0x00,0x00,0x80,0x70,0x21,0x34,0x63,0x00,0x20,0x24,0x42,0x60,0x7c,
0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,0x34,0x84,0x00,0x30,0xad,0xc0,0x02,0xb8,
0x8c,0x83,0x00,0x00,0x24,0x02,0x00,0xff,0xa5,0xc0,0x00,0x0a,0x00,0x00,0x30,0x21,
0xa7,0x82,0x8f,0xf0,0x27,0x88,0x90,0x00,0xa5,0xc3,0x00,0x08,0x3c,0x07,0xb0,0x08,
0x30,0xc2,0xff,0xff,0x00,0x02,0x20,0xc0,0x24,0xc3,0x00,0x01,0x00,0x82,0x10,0x21,
0x00,0x60,0x30,0x21,0x00,0x02,0x10,0x80,0x30,0x63,0xff,0xff,0x00,0x48,0x10,0x21,
0x00,0x87,0x20,0x21,0x28,0xc5,0x00,0xff,0xac,0x83,0x00,0x00,0x14,0xa0,0xff,0xf4,
0xa4,0x43,0x00,0x00,0x3c,0x02,0xb0,0x08,0x34,0x03,0xff,0xff,0x25,0xc4,0x00,0x0c,
0x24,0x0a,0x00,0x02,0x34,0x42,0x07,0xf8,0x3c,0x06,0xb0,0x03,0xa7,0x83,0xb3,0xdc,
0xac,0x43,0x00,0x00,0xaf,0x84,0xb4,0x00,0x34,0xc6,0x00,0x64,0xa0,0x8a,0x00,0x18,
0x94,0xc5,0x00,0x00,0x8f,0x82,0xb4,0x00,0x25,0xc4,0x00,0x30,0x24,0x08,0x00,0x03,
0x3c,0x03,0xb0,0x03,0xa0,0x45,0x00,0x21,0x34,0x63,0x00,0x66,0xaf,0x84,0xb4,0x04,
0xa0,0x88,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x04,0x25,0xc4,0x00,0x54,
0x25,0xc7,0x00,0x78,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x08,0xa0,0x88,0x00,0x18,
0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x08,0x25,0xc8,0x00,0x9c,0x24,0x09,0x00,0x01,
0xa0,0x45,0x00,0x21,0xaf,0x87,0xb4,0x0c,0xa0,0xea,0x00,0x18,0x94,0xc4,0x00,0x00,
0x8f,0x82,0xb4,0x0c,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x62,0xa0,0x44,0x00,0x21,
0xaf,0x88,0xb4,0x10,0xa1,0x09,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x10,
0x25,0xc4,0x00,0xc0,0x3c,0x06,0xb0,0x03,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x14,
0xa0,0x89,0x00,0x18,0x94,0x65,0x00,0x00,0x8f,0x82,0xb4,0x14,0x25,0xc4,0x00,0xe4,
0x34,0xc6,0x00,0x60,0xa0,0x45,0x00,0x21,0xaf,0x84,0xb4,0x18,0xa0,0x80,0x00,0x18,
0x94,0xc5,0x00,0x00,0x8f,0x82,0xb4,0x18,0x25,0xc3,0x01,0x08,0x25,0xc7,0x01,0x2c,
0xa0,0x45,0x00,0x21,0xaf,0x83,0xb4,0x1c,0xa0,0x60,0x00,0x18,0x94,0xc8,0x00,0x00,
0x8f,0x82,0xb4,0x1c,0x25,0xc4,0x01,0x50,0x25,0xc5,0x01,0x74,0xa0,0x48,0x00,0x21,
0x25,0xc6,0x01,0x98,0x25,0xc9,0x01,0xbc,0x25,0xca,0x01,0xe0,0x25,0xcb,0x02,0x04,
0x25,0xcc,0x02,0x28,0x25,0xcd,0x02,0x4c,0x24,0x02,0x00,0x10,0x3c,0x03,0xb0,0x03,
0xaf,0x87,0xb4,0x20,0x34,0x63,0x00,0x38,0xa0,0xe0,0x00,0x18,0xaf,0x84,0xb4,0x24,
0xa0,0x80,0x00,0x18,0xaf,0x85,0xb4,0x28,0xa0,0xa0,0x00,0x18,0xaf,0x86,0xb4,0x2c,
0xa0,0xc0,0x00,0x18,0xaf,0x89,0xb4,0x30,0xa1,0x20,0x00,0x18,0xaf,0x8a,0xb4,0x34,
0xa1,0x40,0x00,0x18,0xaf,0x8b,0xb4,0x38,0xa1,0x60,0x00,0x18,0xaf,0x8c,0xb4,0x3c,
0xa1,0x80,0x00,0x18,0xaf,0x8d,0xb4,0x40,0xa1,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,
0x8f,0x82,0xb4,0x40,0x25,0xc5,0x02,0x70,0x3c,0x03,0xb0,0x03,0xa0,0x44,0x00,0x21,
0x24,0x02,0x00,0x11,0xaf,0x85,0xb4,0x44,0x34,0x63,0x00,0x6e,0xa0,0xa2,0x00,0x18,
0x94,0x64,0x00,0x00,0x8f,0x82,0xb4,0x44,0x25,0xc5,0x02,0x94,0x3c,0x03,0xb0,0x03,
0xa0,0x44,0x00,0x21,0x24,0x02,0x00,0x12,0xaf,0x85,0xb4,0x48,0x34,0x63,0x00,0x6c,
0xa0,0xa2,0x00,0x18,0x94,0x64,0x00,0x00,0x8f,0x82,0xb4,0x48,0x24,0x05,0xff,0xff,
0x24,0x07,0x00,0x01,0xa0,0x44,0x00,0x21,0x24,0x06,0x00,0x12,0x27,0x84,0xb4,0x00,
0x8c,0x82,0x00,0x00,0x24,0xc6,0xff,0xff,0xa0,0x40,0x00,0x04,0x8c,0x83,0x00,0x00,
0xa4,0x45,0x00,0x00,0xa4,0x45,0x00,0x02,0xa0,0x60,0x00,0x0a,0x8c,0x82,0x00,0x00,
0xa4,0x65,0x00,0x06,0xa4,0x65,0x00,0x08,0xa0,0x40,0x00,0x10,0x8c,0x83,0x00,0x00,
0xa4,0x45,0x00,0x0c,0xa4,0x45,0x00,0x0e,0xa0,0x60,0x00,0x12,0x8c,0x82,0x00,0x00,
0x00,0x00,0x00,0x00,0xa0,0x40,0x00,0x16,0x8c,0x83,0x00,0x00,0xa4,0x45,0x00,0x14,
0xa0,0x67,0x00,0x17,0x8c,0x82,0x00,0x00,0x24,0x84,0x00,0x04,0xa0,0x40,0x00,0x20,
0x04,0xc1,0xff,0xe7,0xac,0x40,0x00,0x1c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x34,0x42,0x00,0x20,0x24,0x63,0x63,0x40,
0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x10,0x00,0x80,0x60,0x21,0x10,0x40,0x00,0x56,
0x00,0x00,0x70,0x21,0x97,0x82,0x8f,0xf0,0x94,0x8a,0x00,0x0c,0x27,0x87,0x90,0x00,
0x00,0x02,0x40,0xc0,0x01,0x02,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,
0x90,0x8b,0x00,0x18,0xa4,0x4a,0x00,0x00,0x94,0x83,0x00,0x0e,0x39,0x64,0x00,0x10,
0x2c,0x84,0x00,0x01,0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x34,0x85,0x00,0x02,
0x39,0x63,0x00,0x11,0x00,0x83,0x28,0x0b,0x34,0xa3,0x00,0x08,0x39,0x64,0x00,0x12,
0x00,0x02,0x10,0x80,0x00,0xa4,0x18,0x0b,0x00,0x47,0x10,0x21,0x94,0x49,0x00,0x04,
0x34,0x64,0x00,0x20,0x00,0x6b,0x20,0x0b,0x34,0x83,0x00,0x40,0x39,0x62,0x00,0x01,
0x00,0x82,0x18,0x0b,0x00,0x09,0x30,0xc0,0x34,0x64,0x00,0x80,0x00,0xc9,0x28,0x21,
0x39,0x62,0x00,0x02,0x00,0x60,0x68,0x21,0x00,0x82,0x68,0x0a,0x00,0x05,0x28,0x80,
0x3c,0x02,0xb0,0x08,0x00,0xa7,0x28,0x21,0x00,0xc2,0x30,0x21,0x01,0x02,0x40,0x21,
0x34,0x03,0xff,0xff,0x35,0xa4,0x01,0x00,0x39,0x62,0x00,0x03,0x2d,0x67,0x00,0x13,
0xad,0x0a,0x00,0x00,0xa4,0xa3,0x00,0x00,0xac,0xc3,0x00,0x00,0xa7,0x89,0x8f,0xf0,
0x10,0xe0,0x00,0x0f,0x00,0x82,0x68,0x0a,0x3c,0x03,0x80,0x01,0x00,0x0b,0x10,0x80,
0x24,0x63,0x02,0x44,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x60,
0x94,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x14,0x00,0x00,0x02,0x74,0x03,
0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3a,0x94,0x44,0x00,0x00,0x93,0x83,0x8f,0xe4,
0x91,0x82,0x00,0x21,0x01,0xc4,0x20,0x21,0x91,0x85,0x00,0x10,0x00,0x04,0x24,0x00,
0x00,0x62,0x18,0x21,0x00,0x04,0x74,0x03,0x00,0x6e,0x18,0x23,0x00,0x65,0x10,0x2a,
0x00,0xa2,0x18,0x0a,0x00,0x0d,0x24,0x00,0x3c,0x02,0xb0,0x06,0x24,0x05,0xff,0xff,
0x00,0x64,0x18,0x25,0x34,0x42,0x80,0x20,0xac,0x43,0x00,0x00,0xa5,0x85,0x00,0x0e,
0xa1,0x80,0x00,0x10,0xa5,0x85,0x00,0x0c,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x62,0x3c,0x03,0xb0,0x03,
0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x64,0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,
0x34,0x63,0x00,0x66,0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x38,
0x3c,0x03,0xb0,0x03,0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x6e,0x3c,0x03,0xb0,0x03,
0x08,0x00,0x19,0x14,0x34,0x63,0x00,0x6c,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
0x34,0x63,0x00,0x20,0x24,0x42,0x65,0x08,0x00,0x05,0x28,0x40,0xac,0x62,0x00,0x00,
0x00,0xa6,0x28,0x21,0x2c,0xe2,0x00,0x10,0x14,0x80,0x00,0x06,0x00,0x00,0x18,0x21,
0x10,0x40,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0xe0,0x18,0x21,0x03,0xe0,0x00,0x08,
0x00,0x60,0x10,0x21,0x24,0x02,0x00,0x20,0x10,0xe2,0x00,0x06,0x2c,0xe4,0x00,0x10,
0x24,0xa2,0x00,0x01,0x10,0x80,0xff,0xf9,0x00,0x02,0x11,0x00,0x08,0x00,0x19,0x4f,
0x00,0x47,0x18,0x21,0x08,0x00,0x19,0x4f,0x24,0xa3,0x00,0x50,0x27,0xbd,0xff,0xc8,
0xaf,0xb3,0x00,0x1c,0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x30,
0xaf,0xb7,0x00,0x2c,0xaf,0xb6,0x00,0x28,0xaf,0xb5,0x00,0x24,0xaf,0xb4,0x00,0x20,
0xaf,0xb0,0x00,0x10,0x00,0x80,0x88,0x21,0x84,0x84,0x00,0x08,0x3c,0x05,0xb0,0x03,
0x3c,0x02,0x80,0x00,0x34,0xa5,0x00,0x20,0x24,0x42,0x65,0x6c,0x3c,0x03,0xb0,0x06,
0x00,0x04,0x20,0x80,0xac,0xa2,0x00,0x00,0x00,0x83,0x20,0x21,0x3c,0x06,0xb0,0x06,
0x8c,0x82,0x00,0x00,0x34,0xc6,0x80,0x24,0x8c,0x88,0x00,0x00,0x8c,0xc4,0x00,0x00,
0x96,0x25,0x00,0x08,0x30,0x52,0xff,0xff,0x00,0x08,0x44,0x02,0x34,0x84,0x01,0x00,
0x3c,0x02,0xb0,0x00,0x00,0x08,0x18,0xc0,0x00,0x12,0x3a,0x00,0xac,0xc4,0x00,0x00,
0x00,0xe2,0x38,0x21,0xae,0x32,0x02,0xb8,0x00,0x68,0x18,0x21,0x24,0xa5,0x00,0x02,
0x8c,0xf6,0x00,0x00,0x30,0xa5,0x01,0xff,0x8c,0xf4,0x00,0x04,0x27,0x86,0x90,0x00,
0x00,0x03,0x18,0x80,0x00,0x12,0x98,0xc0,0xa6,0x25,0x00,0x08,0x00,0x66,0x18,0x21,
0x02,0x72,0x10,0x21,0x94,0x65,0x00,0x00,0x00,0x02,0x48,0x80,0x01,0x26,0x30,0x21,
0x24,0x02,0xff,0xff,0x00,0x14,0x1a,0x02,0x27,0x84,0x90,0x10,0xa4,0xc2,0x00,0x02,
0x30,0x63,0x00,0x1f,0x24,0x02,0x00,0x10,0x01,0x24,0x20,0x21,0xa4,0xc8,0x00,0x04,
0x8c,0xf0,0x00,0x08,0xa6,0x23,0x00,0x06,0xa6,0x25,0x00,0x0a,0xa0,0x82,0x00,0x06,
0x86,0x25,0x00,0x06,0x27,0x82,0x90,0x04,0x01,0x22,0x10,0x21,0x24,0x03,0x00,0x13,
0x10,0xa3,0x00,0xee,0xac,0x47,0x00,0x18,0x3c,0x03,0xb0,0x03,0x34,0x63,0x01,0x00,
0xa6,0x20,0x00,0x02,0x3c,0x02,0xb0,0x03,0x90,0x64,0x00,0x00,0x34,0x42,0x01,0x08,
0x8c,0x45,0x00,0x00,0x00,0x10,0x1b,0xc2,0x00,0x04,0x20,0x82,0x30,0x63,0x00,0x01,
0xac,0xc5,0x00,0x08,0x10,0x60,0x00,0xc7,0x30,0x97,0x00,0x01,0x00,0x10,0x16,0x82,
0x30,0x46,0x00,0x01,0x00,0x10,0x12,0x02,0x00,0x10,0x19,0xc2,0x00,0x10,0x26,0x02,
0x00,0x10,0x2e,0x42,0x30,0x48,0x00,0x7f,0x24,0x02,0x00,0x01,0x30,0x75,0x00,0x01,
0x30,0x84,0x00,0x01,0x10,0xc2,0x00,0xb3,0x30,0xa3,0x00,0x01,0x00,0x60,0x28,0x21,
0x0c,0x00,0x19,0x42,0x01,0x00,0x38,0x21,0x02,0x72,0x18,0x21,0x00,0x03,0x18,0x80,
0x2c,0x46,0x00,0x54,0x27,0x85,0x90,0x10,0x27,0x84,0x90,0x08,0x00,0x06,0x10,0x0a,
0x00,0x65,0x28,0x21,0x26,0xa6,0x00,0x02,0x00,0x64,0x18,0x21,0xa0,0xa2,0x00,0x02,
0xa0,0x66,0x00,0x06,0xa0,0x62,0x00,0x07,0xa0,0xa2,0x00,0x01,0x02,0x72,0x28,0x21,
0x00,0x05,0x28,0x80,0x27,0x82,0x90,0x04,0x00,0xa2,0x58,0x21,0x8d,0x64,0x00,0x18,
0x00,0x10,0x15,0xc2,0x30,0x42,0x00,0x01,0x8c,0x83,0x00,0x0c,0x27,0x84,0x90,0x20,
0x00,0xa4,0x48,0x21,0xa6,0x22,0x00,0x00,0xa6,0x36,0x00,0x04,0x8d,0x26,0x00,0x00,
0x00,0x03,0x19,0x42,0x3c,0x02,0xff,0xef,0x34,0x42,0xff,0xff,0x30,0x63,0x00,0x01,
0x00,0xc2,0x40,0x24,0x00,0x03,0x1d,0x00,0x01,0x03,0x40,0x25,0x00,0x08,0x15,0x02,
0x00,0x14,0x19,0x82,0x00,0x14,0x25,0x82,0x00,0x10,0x34,0x42,0x00,0x10,0x3c,0x82,
0x00,0x10,0x2c,0x02,0x30,0x42,0x00,0x01,0x30,0xcd,0x00,0x01,0x30,0x6c,0x00,0x01,
0x30,0xe6,0x00,0x01,0x30,0x8a,0x00,0x03,0x32,0x94,0x00,0x07,0x30,0xa5,0x00,0x01,
0xad,0x28,0x00,0x00,0x10,0x40,0x00,0x0b,0x32,0x07,0x00,0x7f,0x8d,0x64,0x00,0x18,
0x3c,0x03,0xff,0xf0,0x34,0x63,0xff,0xff,0x8c,0x82,0x00,0x0c,0x01,0x03,0x18,0x24,
0x00,0x02,0x13,0x82,0x30,0x42,0x00,0x0f,0x00,0x02,0x14,0x00,0x00,0x62,0x18,0x25,
0xad,0x23,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xc2,0x00,0x6a,0x00,0x00,0x00,0x00,
0x15,0x80,0x00,0x03,0x00,0x00,0x00,0x00,0x15,0x40,0x00,0x5b,0x24,0x02,0x00,0x01,
0x96,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x04,0xa6,0x22,0x00,0x04,
0x00,0xa0,0x20,0x21,0x0c,0x00,0x19,0x42,0x01,0xa0,0x28,0x21,0x02,0x72,0x18,0x21,
0x00,0x03,0x40,0x80,0x2c,0x45,0x00,0x54,0x27,0x84,0x90,0x10,0x01,0x04,0x20,0x21,
0x00,0x05,0x10,0x0a,0xa0,0x82,0x00,0x00,0xa0,0x80,0x00,0x04,0xa0,0x80,0x00,0x05,
0x96,0x23,0x00,0x04,0x27,0x82,0x90,0x00,0x01,0x02,0x10,0x21,0xa4,0x43,0x00,0x06,
0x27,0x82,0x90,0x04,0x92,0x26,0x00,0x01,0x01,0x02,0x10,0x21,0x8c,0x45,0x00,0x18,
0x27,0x83,0x90,0x20,0x01,0x03,0x18,0x21,0xa0,0x60,0x00,0x00,0xa0,0x86,0x00,0x07,
0x94,0xa2,0x00,0x10,0x24,0x03,0x00,0x04,0x30,0x42,0x00,0x0f,0x10,0x43,0x00,0x36,
0x24,0xa5,0x00,0x10,0x94,0xa3,0x00,0x16,0x27,0x87,0x90,0x18,0x01,0x07,0x10,0x21,
0xa4,0x43,0x00,0x02,0x94,0xa2,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,
0x14,0x40,0x00,0x24,0x02,0x72,0x20,0x21,0x94,0xa2,0x00,0x00,0x24,0x03,0x00,0xa4,
0x30,0x42,0x00,0xff,0x10,0x43,0x00,0x1f,0x00,0x00,0x00,0x00,0x94,0xa2,0x00,0x00,
0x24,0x03,0x00,0x88,0x30,0x42,0x00,0x88,0x10,0x43,0x00,0x14,0x02,0x72,0x18,0x21,
0x27,0x84,0x90,0x20,0x00,0x03,0x18,0x80,0x00,0x64,0x18,0x21,0x8c,0x62,0x00,0x00,
0x3c,0x04,0x00,0x80,0x00,0x44,0x10,0x25,0xac,0x62,0x00,0x00,0x02,0x72,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0xa0,0x54,0x00,0x00,0x8f,0xbf,0x00,0x30,
0x7b,0xb6,0x01,0x7c,0x7b,0xb4,0x01,0x3c,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,
0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0x94,0xa2,0x00,0x18,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x60,0x10,0x40,0xff,0xe9,0x02,0x72,0x18,0x21,
0x02,0x72,0x20,0x21,0x27,0x82,0x90,0x20,0x00,0x04,0x20,0x80,0x00,0x82,0x20,0x21,
0x8c,0x83,0x00,0x00,0x3c,0x02,0xff,0x7f,0x34,0x42,0xff,0xff,0x00,0x62,0x18,0x24,
0x08,0x00,0x1a,0x37,0xac,0x83,0x00,0x00,0x27,0x87,0x90,0x18,0x01,0x07,0x10,0x21,
0x08,0x00,0x1a,0x21,0xa4,0x40,0x00,0x02,0x11,0x42,0x00,0x07,0x00,0x00,0x00,0x00,
0x2d,0x42,0x00,0x02,0x14,0x40,0xff,0xa7,0x00,0xa0,0x20,0x21,0x96,0x22,0x00,0x04,
0x08,0x00,0x19,0xff,0x24,0x42,0x00,0x0c,0x96,0x22,0x00,0x04,0x08,0x00,0x19,0xff,
0x24,0x42,0x00,0x08,0x16,0xe6,0xff,0x96,0x3c,0x02,0xff,0xfb,0x8d,0x63,0x00,0x18,
0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,0xac,0x62,0x00,0x08,0x08,0x00,0x19,0xf8,
0x00,0x00,0x30,0x21,0x16,0xe6,0xff,0x4e,0x00,0x60,0x28,0x21,0x3c,0x02,0xfb,0xff,
0x34,0x42,0xff,0xff,0x02,0x02,0x10,0x24,0xac,0xe2,0x00,0x08,0x08,0x00,0x19,0xb7,
0x00,0x00,0x30,0x21,0x93,0x87,0xbb,0x14,0x00,0x10,0x1e,0x42,0x00,0x10,0x26,0x82,
0x27,0x82,0x90,0x08,0x2c,0xe5,0x00,0x0c,0x01,0x22,0x48,0x21,0x30,0x63,0x00,0x01,
0x30,0x86,0x00,0x01,0x14,0xa0,0x00,0x06,0x00,0xe0,0x40,0x21,0x00,0x03,0x10,0x40,
0x00,0x46,0x10,0x21,0x00,0x02,0x11,0x00,0x00,0xe2,0x10,0x21,0x24,0x48,0x00,0x04,
0x02,0x72,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x84,0x90,0x10,0x27,0x83,0x90,0x08,
0x00,0x44,0x20,0x21,0x00,0x43,0x10,0x21,0xa1,0x28,0x00,0x07,0xa0,0x40,0x00,0x06,
0xa0,0x80,0x00,0x02,0x08,0x00,0x19,0xc7,0xa0,0x80,0x00,0x01,0x24,0x02,0x00,0x01,
0xa6,0x22,0x00,0x02,0x0c,0x00,0x01,0xc2,0x00,0xe0,0x20,0x21,0x08,0x00,0x1a,0x3b,
0x00,0x00,0x00,0x00,0x30,0xa7,0xff,0xff,0x00,0x07,0x18,0xc0,0x00,0x67,0x18,0x21,
0x3c,0x06,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x6a,0x44,0x27,0x85,0x90,0x10,
0x00,0x03,0x18,0x80,0x34,0xc6,0x00,0x20,0x00,0x65,0x18,0x21,0xac,0xc2,0x00,0x00,
0x80,0x62,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x29,0x00,0x80,0x28,0x21,
0x90,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0x30,0x43,0x00,0x01,
0x14,0x60,0x00,0x02,0xa0,0x82,0x00,0x16,0xa0,0x80,0x00,0x17,0x90,0xa2,0x00,0x04,
0x3c,0x03,0xb0,0x03,0x27,0x86,0x90,0x00,0x14,0x40,0x00,0x06,0x34,0x63,0x00,0x20,
0x24,0x02,0x00,0x01,0xa0,0xa2,0x00,0x04,0xa4,0xa7,0x00,0x02,0x03,0xe0,0x00,0x08,
0xa4,0xa7,0x00,0x00,0x94,0xa4,0x00,0x02,0x3c,0x02,0x80,0x01,0x24,0x42,0x82,0x6c,
0xac,0x62,0x00,0x00,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,
0x00,0x66,0x18,0x21,0x94,0x62,0x00,0x04,0xa4,0x67,0x00,0x02,0x3c,0x03,0xb0,0x08,
0x00,0x02,0x20,0xc0,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x46,0x10,0x21,
0x00,0x83,0x20,0x21,0xa4,0x47,0x00,0x00,0xac,0x87,0x00,0x00,0x90,0xa2,0x00,0x04,
0xa4,0xa7,0x00,0x02,0x24,0x42,0x00,0x01,0x03,0xe0,0x00,0x08,0xa0,0xa2,0x00,0x04,
0x90,0x82,0x00,0x16,0x24,0x85,0x00,0x06,0x34,0x42,0x00,0x01,0x30,0x43,0x00,0x02,
0x14,0x60,0xff,0xda,0xa0,0x82,0x00,0x16,0x24,0x02,0x00,0x01,0x08,0x00,0x1a,0xa7,
0xa0,0x82,0x00,0x17,0x27,0xbd,0xff,0xe8,0xaf,0xbf,0x00,0x10,0x00,0x80,0x38,0x21,
0x84,0x84,0x00,0x02,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x3c,0x0a,0xb0,0x06,
0x34,0x63,0x00,0x20,0x24,0x42,0x6b,0x44,0x3c,0x0b,0xb0,0x08,0x27,0x89,0x90,0x00,
0x34,0x0c,0xff,0xff,0x35,0x4a,0x80,0x20,0x10,0x80,0x00,0x30,0xac,0x62,0x00,0x00,
0x97,0x82,0x8f,0xf0,0x94,0xe6,0x02,0xba,0x00,0x02,0x18,0xc0,0x00,0x6b,0x28,0x21,
0xac,0xa6,0x00,0x00,0x8c,0xe4,0x02,0xb8,0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x80,
0x00,0x04,0x10,0xc0,0x00,0x44,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21,
0x94,0x48,0x00,0x04,0x00,0x69,0x18,0x21,0xa4,0x66,0x00,0x00,0x00,0x08,0x28,0xc0,
0x00,0xab,0x10,0x21,0xac,0x4c,0x00,0x00,0x8c,0xe4,0x02,0xb8,0x27,0x82,0x90,0x04,
0x00,0xa8,0x28,0x21,0x00,0x04,0x18,0xc0,0x00,0x64,0x18,0x21,0x00,0x03,0x18,0x80,
0x00,0x62,0x10,0x21,0x8c,0x46,0x00,0x18,0x27,0x84,0x90,0x10,0x00,0x64,0x18,0x21,
0x8c,0xc2,0x00,0x00,0x80,0x67,0x00,0x06,0x00,0x05,0x28,0x80,0x30,0x42,0xff,0xff,
0x00,0x47,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,0x00,0x02,0x12,0x02,
0x00,0x43,0x10,0x21,0x3c,0x04,0x00,0x04,0x00,0xa9,0x28,0x21,0x00,0x44,0x10,0x25,
0xa4,0xac,0x00,0x00,0xad,0x42,0x00,0x00,0xa7,0x88,0x8f,0xf0,0x8f,0xbf,0x00,0x10,
0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x84,0xe3,0x00,0x06,
0x27,0x82,0xb4,0x00,0x94,0xe5,0x02,0xba,0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,
0x8c,0x64,0x00,0x00,0x0c,0x00,0x1a,0x91,0x00,0x00,0x00,0x00,0x08,0x00,0x1b,0x0b,
0x00,0x00,0x00,0x00,0x94,0x88,0x00,0x00,0x00,0x80,0x58,0x21,0x27,0x8a,0x90,0x00,
0x00,0x08,0x18,0xc0,0x00,0x68,0x18,0x21,0x3c,0x04,0xb0,0x03,0x00,0x03,0x18,0x80,
0x3c,0x02,0x80,0x00,0x00,0x6a,0x18,0x21,0x34,0x84,0x00,0x20,0x24,0x42,0x6c,0x64,
0x30,0xa5,0xff,0xff,0xac,0x82,0x00,0x00,0x94,0x67,0x00,0x02,0x11,0x05,0x00,0x35,
0x24,0x04,0x00,0x01,0x91,0x66,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x86,0x10,0x2a,
0x10,0x40,0x00,0x10,0x00,0xc0,0x48,0x21,0x3c,0x0d,0xb0,0x03,0x01,0x40,0x60,0x21,
0x35,0xad,0x00,0x20,0x10,0xe5,0x00,0x0d,0x24,0x84,0x00,0x01,0x00,0x07,0x10,0xc0,
0x00,0x47,0x10,0x21,0x00,0x02,0x10,0x80,0x01,0x20,0x30,0x21,0x00,0x4a,0x10,0x21,
0x00,0x86,0x18,0x2a,0x00,0xe0,0x40,0x21,0x94,0x47,0x00,0x02,0x14,0x60,0xff,0xf5,
0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x10,0x21,0x00,0x08,0x20,0xc0,
0x00,0x88,0x20,0x21,0x24,0xc2,0xff,0xff,0x00,0x04,0x20,0x80,0xa1,0x62,0x00,0x04,
0x00,0x8c,0x20,0x21,0x94,0x83,0x00,0x04,0x00,0x07,0x10,0xc0,0x00,0x47,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x4c,0x10,0x21,0x00,0x03,0x28,0xc0,0x94,0x46,0x00,0x02,
0x00,0xa3,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x6c,0x18,0x21,0xa4,0x66,0x00,0x00,
0xa4,0x86,0x00,0x02,0x95,0x64,0x00,0x02,0x3c,0x03,0xb0,0x08,0x3c,0x02,0x80,0x01,
0x00,0xa3,0x28,0x21,0x24,0x42,0x82,0x6c,0xad,0xa2,0x00,0x00,0x10,0x87,0x00,0x03,
0xac,0xa6,0x00,0x00,0x03,0xe0,0x00,0x08,0x24,0x02,0x00,0x01,0x08,0x00,0x1b,0x59,
0xa5,0x68,0x00,0x02,0x91,0x62,0x00,0x04,0xa5,0x67,0x00,0x00,0x24,0x42,0xff,0xff,
0x30,0x43,0x00,0xff,0x14,0x60,0xff,0xf7,0xa1,0x62,0x00,0x04,0x24,0x02,0xff,0xff,
0x08,0x00,0x1b,0x59,0xa5,0x62,0x00,0x02,0x00,0x05,0x40,0xc0,0x01,0x05,0x30,0x21,
0x27,0xbd,0xff,0xd8,0x00,0x06,0x30,0x80,0x27,0x82,0x90,0x04,0xaf,0xb2,0x00,0x18,
0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0xaf,0xb0,0x00,0x10,
0x00,0xc2,0x10,0x21,0x8c,0x47,0x00,0x18,0x00,0xa0,0x90,0x21,0x3c,0x02,0x80,0x00,
0x3c,0x05,0xb0,0x03,0x34,0xa5,0x00,0x20,0x24,0x42,0x6d,0x98,0xac,0xa2,0x00,0x00,
0x27,0x83,0x90,0x10,0x00,0xc3,0x30,0x21,0x8c,0xe2,0x00,0x00,0x80,0xc5,0x00,0x06,
0x00,0x80,0x88,0x21,0x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,0x30,0x43,0x00,0xff,
0x10,0x60,0x00,0x02,0x00,0x02,0x12,0x02,0x24,0x42,0x00,0x01,0x30,0x53,0x00,0xff,
0x01,0x12,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x10,0x00,0x43,0x10,0x21,
0x80,0x44,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x80,0x00,0x4b,0x26,0x24,0x00,0x06,
0x32,0x50,0xff,0xff,0x02,0x20,0x20,0x21,0x0c,0x00,0x1b,0x19,0x02,0x00,0x28,0x21,
0x92,0x22,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x2e,0x3c,0x03,0xb0,0x08,
0x3c,0x09,0x80,0x01,0x27,0x88,0x90,0x00,0xa6,0x32,0x00,0x0c,0x00,0x10,0x20,0xc0,
0x00,0x90,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,
0x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0x48,0x10,0x21,0x00,0xa3,0x28,0x21,0x25,0x26,0x82,0x6c,
0x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,0xa4,0x83,0x00,0x02,
0xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,0x92,0x22,0x00,0x10,0x92,0x23,0x00,0x0a,
0xa6,0x32,0x00,0x0e,0x02,0x62,0x10,0x21,0x14,0x60,0x00,0x05,0xa2,0x22,0x00,0x10,
0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfe,0xa2,0x22,0x00,0x16,
0x92,0x22,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x05,0x00,0x00,0x00,0x00,
0x92,0x22,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,0xa2,0x22,0x00,0x16,
0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x28,0x96,0x22,0x00,0x0e,0x27,0x88,0x90,0x00,0x00,0x02,0x20,0xc0,
0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x88,0x20,0x21,0x94,0x82,0x00,0x04,
0x3c,0x06,0xb0,0x03,0x3c,0x09,0x80,0x01,0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,
0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,0x00,0x48,0x10,0x21,0x34,0xc6,0x00,0x20,
0x25,0x23,0x82,0x6c,0xac,0xc3,0x00,0x00,0xa4,0x50,0x00,0x00,0xac,0xb0,0x00,0x00,
0x08,0x00,0x1b,0x97,0xa4,0x90,0x00,0x02,0x08,0x00,0x1b,0x8e,0x32,0x50,0xff,0xff,
0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,0x24,0x42,0x6f,0x60,0x34,0x63,0x00,0x20,
0xac,0x62,0x00,0x00,0x90,0x82,0x00,0x04,0x97,0xaa,0x00,0x12,0x00,0x80,0x60,0x21,
0x30,0xa8,0xff,0xff,0x00,0x4a,0x20,0x23,0x34,0x09,0xff,0xff,0x30,0xcf,0xff,0xff,
0x30,0xee,0xff,0xff,0x11,0x09,0x00,0x73,0xa1,0x84,0x00,0x04,0x00,0x0e,0xc0,0xc0,
0x00,0x08,0x10,0xc0,0x00,0x48,0x10,0x21,0x03,0x0e,0x20,0x21,0x27,0x8d,0x90,0x00,
0x00,0x04,0x20,0x80,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0x8d,0x20,0x21,
0x94,0x86,0x00,0x02,0x94,0x43,0x00,0x04,0x3c,0x19,0x80,0x01,0xa4,0x46,0x00,0x02,
0x00,0x03,0x28,0xc0,0x00,0xa3,0x18,0x21,0x94,0x87,0x00,0x02,0x3c,0x02,0xb0,0x08,
0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x21,0x00,0x6d,0x18,0x21,0x27,0x22,0x82,0x6c,
0x3c,0x01,0xb0,0x03,0xac,0x22,0x00,0x20,0xa4,0x66,0x00,0x00,0x10,0xe9,0x00,0x57,
0xac,0xa6,0x00,0x00,0x01,0xe0,0x30,0x21,0x11,0x40,0x00,0x1d,0x00,0x00,0x48,0x21,
0x01,0x40,0x38,0x21,0x27,0x8b,0x90,0x04,0x27,0x8a,0x90,0x10,0x00,0x06,0x40,0xc0,
0x01,0x06,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x6b,0x10,0x21,0x8c,0x44,0x00,0x18,
0x00,0x6a,0x18,0x21,0x80,0x65,0x00,0x06,0x8c,0x82,0x00,0x00,0x00,0x00,0x00,0x00,
0x30,0x42,0xff,0xff,0x00,0x45,0x10,0x21,0x30,0x44,0x00,0xff,0x00,0x02,0x12,0x02,
0x01,0x22,0x18,0x21,0x24,0x62,0x00,0x01,0x14,0x80,0x00,0x02,0x30,0x49,0x00,0xff,
0x30,0x69,0x00,0xff,0x01,0x06,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,
0x24,0xe7,0xff,0xff,0x94,0x46,0x00,0x02,0x14,0xe0,0xff,0xe9,0x00,0x06,0x40,0xc0,
0x91,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x20,0x3c,0x06,0xb0,0x03,
0xa5,0x8f,0x00,0x0c,0x03,0x0e,0x20,0x21,0x00,0x04,0x20,0x80,0x00,0x8d,0x20,0x21,
0x94,0x82,0x00,0x04,0x3c,0x03,0xb0,0x08,0x3c,0x07,0xb0,0x03,0x00,0x02,0x28,0xc0,
0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4d,0x10,0x21,0x00,0xa3,0x28,0x21,
0x27,0x26,0x82,0x6c,0x34,0x03,0xff,0xff,0x34,0xe7,0x00,0x20,0xac,0xe6,0x00,0x00,
0xa4,0x83,0x00,0x02,0xa4,0x43,0x00,0x00,0xac,0xa3,0x00,0x00,0x91,0x82,0x00,0x10,
0x91,0x83,0x00,0x04,0xa5,0x8e,0x00,0x0e,0x01,0x22,0x10,0x21,0x14,0x60,0x00,0x05,
0xa1,0x82,0x00,0x10,0x91,0x82,0x00,0x16,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0xfd,
0xa1,0x82,0x00,0x16,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x95,0x82,0x00,0x0e,
0x3c,0x03,0xb0,0x08,0x00,0x02,0x20,0xc0,0x00,0x82,0x20,0x21,0x00,0x04,0x20,0x80,
0x00,0x8d,0x20,0x21,0x94,0x82,0x00,0x04,0x34,0xc6,0x00,0x20,0x27,0x27,0x82,0x6c,
0x00,0x02,0x28,0xc0,0x00,0xa2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0xa3,0x28,0x21,
0x00,0x4d,0x10,0x21,0xac,0xc7,0x00,0x00,0xa4,0x8f,0x00,0x02,0xa4,0x4f,0x00,0x00,
0xac,0xaf,0x00,0x00,0x08,0x00,0x1c,0x26,0x03,0x0e,0x20,0x21,0x08,0x00,0x1c,0x01,
0xa5,0x88,0x00,0x02,0x00,0x0e,0xc0,0xc0,0x03,0x0e,0x10,0x21,0x00,0x02,0x10,0x80,
0x27,0x8d,0x90,0x00,0x00,0x4d,0x10,0x21,0x94,0x43,0x00,0x02,0x30,0x84,0x00,0xff,
0x14,0x80,0x00,0x05,0xa5,0x83,0x00,0x00,0x24,0x02,0xff,0xff,0x3c,0x19,0x80,0x01,
0x08,0x00,0x1c,0x01,0xa5,0x82,0x00,0x02,0x08,0x00,0x1c,0x01,0x3c,0x19,0x80,0x01,
0x3c,0x08,0xb0,0x03,0x3c,0x02,0x80,0x00,0x27,0xbd,0xff,0x78,0x35,0x08,0x00,0x20,
0x24,0x42,0x71,0xa0,0xaf,0xb2,0x00,0x68,0xaf,0xb1,0x00,0x64,0xaf,0xb0,0x00,0x60,
0xad,0x02,0x00,0x00,0xaf,0xbf,0x00,0x84,0xaf,0xbe,0x00,0x80,0xaf,0xb7,0x00,0x7c,
0xaf,0xb6,0x00,0x78,0xaf,0xb5,0x00,0x74,0xaf,0xb4,0x00,0x70,0xaf,0xb3,0x00,0x6c,
0xaf,0xa4,0x00,0x88,0x90,0x83,0x00,0x0a,0x27,0x82,0xb4,0x00,0xaf,0xa6,0x00,0x90,
0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x63,0x00,0x00,0xaf,0xa7,0x00,0x94,
0x27,0x86,0x90,0x04,0xaf,0xa3,0x00,0x1c,0x94,0x63,0x00,0x14,0x30,0xb1,0xff,0xff,
0x24,0x08,0x00,0x01,0x00,0x03,0x20,0xc0,0xaf,0xa3,0x00,0x18,0x00,0x83,0x18,0x21,
0xaf,0xa4,0x00,0x54,0x00,0x03,0x18,0x80,0x27,0x84,0x90,0x10,0x00,0x64,0x20,0x21,
0x80,0x82,0x00,0x06,0x00,0x66,0x18,0x21,0x8c,0x66,0x00,0x18,0x24,0x42,0x00,0x02,
0x00,0x02,0x1f,0xc2,0x8c,0xc4,0x00,0x08,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,
0x00,0x02,0x10,0x40,0x00,0x04,0x2f,0xc2,0x00,0x04,0x1c,0x82,0x00,0xc2,0x38,0x21,
0x00,0x04,0x24,0x42,0x8f,0xa2,0x00,0x1c,0x30,0x63,0x00,0x01,0x30,0x84,0x00,0x01,
0xaf,0xa5,0x00,0x3c,0xaf,0xa3,0x00,0x34,0xaf,0xa4,0x00,0x38,0xaf,0xa0,0x00,0x40,
0xaf,0xa0,0x00,0x44,0xaf,0xa0,0x00,0x50,0xaf,0xa8,0x00,0x20,0x80,0x42,0x00,0x12,
0x8f,0xb2,0x00,0x18,0xaf,0xa2,0x00,0x28,0x8c,0xd0,0x00,0x0c,0x14,0xa0,0x01,0xe4,
0x00,0x60,0x30,0x21,0x00,0x10,0x10,0x82,0x30,0x45,0x00,0x07,0x10,0xa0,0x00,0x11,
0xaf,0xa0,0x00,0x30,0x8f,0xa4,0x00,0x98,0x27,0x82,0x80,0x1c,0x00,0x04,0x18,0x40,
0x00,0x62,0x18,0x21,0x24,0xa2,0x00,0x06,0x8f,0xa5,0x00,0x20,0x94,0x64,0x00,0x00,
0x00,0x45,0x10,0x04,0x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,0x00,0x00,0x00,0x00,
0x00,0x07,0x00,0x0d,0x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20,0x30,0x42,0xff,0xfc,
0xaf,0xa2,0x00,0x30,0x8f,0xa3,0x00,0x18,0x8f,0xa4,0x00,0x28,0x34,0x02,0xff,0xff,
0xaf,0xa0,0x00,0x2c,0xaf,0xa2,0x00,0x48,0xaf,0xa3,0x00,0x4c,0x00,0x60,0xf0,0x21,
0x00,0x00,0xb8,0x21,0x18,0x80,0x00,0x48,0xaf,0xa0,0x00,0x24,0x00,0x11,0x89,0x02,
0xaf,0xb1,0x00,0x58,0x00,0x80,0xa8,0x21,0x00,0x12,0x10,0xc0,0x00,0x52,0x18,0x21,
0x00,0x03,0x80,0x80,0x27,0x85,0x90,0x00,0x02,0x40,0x20,0x21,0x00,0x40,0xa0,0x21,
0x02,0x05,0x10,0x21,0x94,0x56,0x00,0x02,0x0c,0x00,0x12,0x8b,0x00,0x00,0x28,0x21,
0x90,0x42,0x00,0x00,0x24,0x03,0x00,0x08,0x30,0x42,0x00,0x0c,0x10,0x43,0x01,0x9e,
0x24,0x04,0x00,0x01,0x24,0x02,0x00,0x01,0x10,0x82,0x01,0x7c,0x3c,0x02,0xb0,0x03,
0x8f,0xa6,0x00,0x88,0x34,0x42,0x01,0x04,0x84,0xc5,0x00,0x0c,0x02,0x92,0x18,0x21,
0x94,0x46,0x00,0x00,0x00,0x05,0x20,0xc0,0x00,0x85,0x20,0x21,0x00,0x03,0x18,0x80,
0x27,0x82,0x90,0x10,0x27,0x85,0x90,0x08,0x00,0x65,0x28,0x21,0x00,0x62,0x18,0x21,
0x80,0x71,0x00,0x05,0x80,0x73,0x00,0x04,0x8f,0xa3,0x00,0x88,0x30,0xd0,0xff,0xff,
0x00,0x10,0x3a,0x03,0x32,0x08,0x00,0xff,0x27,0x82,0x90,0x20,0x00,0x04,0x20,0x80,
0x80,0xa6,0x00,0x06,0x00,0x82,0x20,0x21,0xa4,0x67,0x00,0x44,0xa4,0x68,0x00,0x46,
0x8c,0x84,0x00,0x00,0x38,0xc6,0x00,0x00,0x01,0x00,0x80,0x21,0x00,0x04,0x15,0x02,
0x30,0x42,0x00,0x01,0x10,0x40,0x00,0x03,0x00,0xe6,0x80,0x0a,0x00,0x04,0x14,0x02,
0x30,0x50,0x00,0x0f,0x12,0x20,0x01,0x50,0x02,0x40,0x20,0x21,0x02,0x71,0x10,0x21,
0x00,0x50,0x10,0x2a,0x14,0x40,0x00,0xed,0x02,0x92,0x10,0x21,0x93,0x82,0x8b,0x71,
0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,0x14,0x40,0x00,0xe0,0x02,0x92,0x28,0x21,
0x26,0xe2,0x00,0x01,0x30,0x57,0xff,0xff,0x02,0x40,0xf0,0x21,0x26,0xb5,0xff,0xff,
0x16,0xa0,0xff,0xbd,0x02,0xc0,0x90,0x21,0x16,0xe0,0x00,0xd0,0x00,0x00,0x00,0x00,
0x8f,0xa3,0x00,0x98,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x10,0x10,0x40,0x00,0x2e,
0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x24,0x00,0x00,0x00,0x00,0x18,0x80,0x00,0x2a,
0x24,0x03,0x00,0x01,0x8f,0xa5,0x00,0x1c,0x27,0x84,0x90,0x04,0x94,0xb2,0x00,0x14,
0xa0,0xa3,0x00,0x12,0x8f,0xa6,0x00,0x3c,0x00,0x12,0x10,0xc0,0x00,0x52,0x10,0x21,
0x00,0x02,0x80,0x80,0x27,0x82,0x90,0x10,0x02,0x02,0x10,0x21,0x80,0x43,0x00,0x06,
0x02,0x04,0x20,0x21,0x8c,0x85,0x00,0x18,0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,
0x00,0x62,0x18,0x21,0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,0x14,0xc0,0x00,0x0e,
0x00,0xa3,0x38,0x21,0x27,0x82,0x90,0x00,0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,
0x8f,0xa8,0x00,0x1c,0x24,0x02,0x00,0x01,0xa5,0x03,0x00,0x1a,0x7b,0xbe,0x04,0x3c,
0x7b,0xb6,0x03,0xfc,0x7b,0xb4,0x03,0xbc,0x7b,0xb2,0x03,0x7c,0x7b,0xb0,0x03,0x3c,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x88,0x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38,
0x8f,0xa6,0x00,0x34,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x0a,0xaf,0xa0,0x00,0x14,
0x08,0x00,0x1d,0x2d,0x00,0x00,0x00,0x00,0x8f,0xa3,0x00,0x44,0x93,0x82,0x81,0x58,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x61,0x30,0x69,0x00,0x03,0x8f,0xa4,0x00,0x24,
0x8f,0xa5,0x00,0x28,0x00,0x00,0x00,0x00,0x00,0x85,0x10,0x2a,0x10,0x40,0x00,0x8f,
0x00,0x00,0x00,0x00,0x8f,0xa6,0x00,0x1c,0x00,0x00,0x00,0x00,0x90,0xc4,0x00,0x04,
0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,0x00,0xa3,0x10,0x2a,0x10,0x40,0x00,0x87,
0x00,0x00,0x00,0x00,0x8f,0xa8,0x00,0x24,0x00,0x00,0x00,0x00,0x11,0x00,0x00,0x83,
0x00,0x65,0x10,0x23,0x00,0xa8,0x18,0x23,0x00,0x62,0x10,0x2a,0x14,0x40,0x00,0x7d,
0x30,0x63,0x00,0xff,0x00,0x85,0x10,0x23,0x30,0x42,0x00,0xff,0xaf,0xa2,0x00,0x50,
0x8f,0xa2,0x00,0x50,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x73,0x00,0x00,0xa8,0x21,
0x27,0x8c,0x90,0x00,0x3c,0x0b,0x80,0xff,0x24,0x10,0x00,0x04,0x27,0x91,0x90,0x04,
0x35,0x6b,0xff,0xff,0x3c,0x0d,0x7f,0x00,0x27,0x8e,0x90,0x10,0x01,0x80,0x78,0x21,
0x00,0x12,0x30,0xc0,0x00,0xd2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x4c,0x10,0x21,
0x94,0x42,0x00,0x06,0x8f,0xa3,0x00,0x2c,0x8f,0xa4,0x00,0x30,0xaf,0xa2,0x00,0x44,
0x8f,0xa5,0x00,0x44,0x30,0x49,0x00,0x03,0x02,0x09,0x10,0x23,0x30,0x42,0x00,0x03,
0x00,0xa2,0x10,0x21,0x8f,0xa8,0x00,0x30,0x24,0x42,0x00,0x04,0x30,0x42,0xff,0xff,
0x00,0x64,0x38,0x21,0x01,0x02,0x28,0x23,0x00,0x62,0x18,0x21,0x00,0x48,0x10,0x2b,
0x10,0x40,0x00,0x52,0x00,0x00,0x20,0x21,0x30,0xe7,0xff,0xff,0x30,0xa4,0xff,0xff,
0xaf,0xa7,0x00,0x2c,0x00,0xd2,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x51,0x18,0x21,
0x8c,0x65,0x00,0x18,0x00,0x04,0x25,0x40,0x00,0x8d,0x20,0x24,0x8c,0xa8,0x00,0x04,
0x00,0x4e,0x18,0x21,0x00,0x4f,0x50,0x21,0x01,0x0b,0x40,0x24,0x01,0x04,0x40,0x25,
0xac,0xa8,0x00,0x04,0x8f,0xa4,0x00,0x98,0x8f,0xa2,0x00,0x50,0x26,0xb5,0x00,0x01,
0xa0,0x64,0x00,0x00,0x8c,0xa4,0x00,0x08,0x00,0x00,0x00,0x00,0x04,0x81,0x00,0x0c,
0x02,0xa2,0x30,0x2a,0x80,0x62,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,
0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,
0x00,0xa2,0x38,0x21,0x8f,0xa5,0x00,0x40,0x00,0x00,0x00,0x00,0xa4,0xe5,0x00,0x00,
0x95,0x52,0x00,0x02,0x14,0xc0,0xff,0xc7,0x00,0x12,0x30,0xc0,0x8f,0xa4,0x00,0x24,
0x8f,0xa5,0x00,0x50,0x8f,0xa6,0x00,0x1c,0x8f,0xa3,0x00,0x2c,0x00,0x85,0x80,0x21,
0xa0,0xd0,0x00,0x12,0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03,0x8f,0xa8,0x00,0x88,
0x00,0x62,0x10,0x23,0xa4,0xc2,0x00,0x1a,0x85,0x03,0x00,0x0c,0x00,0x00,0x00,0x00,
0x00,0x03,0x10,0xc0,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x04,
0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x18,0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,
0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,0x14,0x60,0xff,0x74,0x02,0x00,0x10,0x21,
0x8f,0xa3,0x00,0x54,0x8f,0xa4,0x00,0x18,0x8f,0xa5,0x00,0x24,0x00,0x64,0x10,0x21,
0x00,0x02,0x10,0x80,0x27,0x83,0x90,0x18,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x00,
0x10,0xa0,0x00,0x03,0x00,0x00,0x30,0x21,0x08,0x00,0x1d,0x33,0x02,0x00,0x10,0x21,
0x93,0x82,0x80,0x10,0x00,0x00,0x28,0x21,0x00,0x00,0x38,0x21,0x0c,0x00,0x21,0x9a,
0xaf,0xa2,0x00,0x10,0x08,0x00,0x1d,0x33,0x02,0x00,0x10,0x21,0x30,0x63,0xff,0xff,
0x08,0x00,0x1d,0x85,0xaf,0xa3,0x00,0x2c,0x8f,0xa8,0x00,0x44,0x08,0x00,0x1d,0xa7,
0x31,0x09,0x00,0x03,0x08,0x00,0x1d,0x60,0xaf,0xa3,0x00,0x50,0x8f,0xa6,0x00,0x44,
0xaf,0xa0,0x00,0x50,0x08,0x00,0x1d,0xa7,0x30,0xc9,0x00,0x03,0x8f,0xa5,0x00,0x48,
0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,0x03,0xc0,0x38,0x21,0x0c,0x00,0x1b,0xd8,
0xaf,0xb7,0x00,0x10,0x08,0x00,0x1d,0x10,0x00,0x00,0x00,0x00,0x00,0x05,0x28,0x80,
0x27,0x82,0x90,0x00,0x00,0xa2,0x28,0x21,0x00,0x00,0x20,0x21,0x0c,0x00,0x01,0x49,
0x00,0x00,0x00,0x00,0x08,0x00,0x1d,0x09,0x26,0xe2,0x00,0x01,0x00,0x02,0x80,0x80,
0x27,0x83,0x90,0x10,0x8f,0xa4,0x00,0x1c,0x02,0x03,0x18,0x21,0x26,0x31,0x00,0x01,
0x02,0x40,0x28,0x21,0x0c,0x00,0x1e,0xea,0xa0,0x71,0x00,0x05,0x14,0x40,0xff,0x13,
0x00,0x00,0x00,0x00,0x16,0xe0,0x00,0x4d,0x03,0xc0,0x38,0x21,0x8f,0xa4,0x00,0x24,
0x8f,0xa5,0x00,0x20,0x24,0x02,0x00,0x01,0x24,0x84,0x00,0x01,0xaf,0xb2,0x00,0x48,
0xaf,0xb6,0x00,0x4c,0x02,0xc0,0xf0,0x21,0x10,0xa2,0x00,0x41,0xaf,0xa4,0x00,0x24,
0x27,0x82,0x90,0x00,0x02,0x02,0x10,0x21,0x94,0x42,0x00,0x06,0x8f,0xa4,0x00,0x30,
0xaf,0xa0,0x00,0x20,0xaf,0xa2,0x00,0x44,0x30,0x49,0x00,0x03,0x8f,0xa8,0x00,0x44,
0x00,0x09,0x10,0x23,0x30,0x42,0x00,0x03,0x01,0x02,0x10,0x21,0x24,0x42,0x00,0x04,
0x30,0x42,0xff,0xff,0x00,0x44,0x18,0x2b,0x10,0x60,0x00,0x2b,0x00,0x00,0x00,0x00,
0x8f,0xa5,0x00,0x2c,0x00,0x82,0x10,0x23,0x00,0xa4,0x18,0x21,0x30,0x63,0xff,0xff,
0x30,0x44,0xff,0xff,0xaf,0xa3,0x00,0x2c,0x02,0x92,0x28,0x21,0x00,0x05,0x28,0x80,
0x27,0x82,0x90,0x04,0x00,0xa2,0x10,0x21,0x8c,0x46,0x00,0x18,0x3c,0x03,0x80,0xff,
0x3c,0x02,0x7f,0x00,0x8c,0xc8,0x00,0x04,0x00,0x04,0x25,0x40,0x34,0x63,0xff,0xff,
0x00,0x82,0x20,0x24,0x01,0x03,0x40,0x24,0x01,0x04,0x40,0x25,0xac,0xc8,0x00,0x04,
0x8f,0xa8,0x00,0x98,0x27,0x82,0x90,0x10,0x00,0xa2,0x10,0x21,0xa0,0x48,0x00,0x00,
0x8c,0xc4,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x04,0x27,0xc2,0x10,0x80,0xfe,0xdb,
0xaf,0xa4,0x00,0x3c,0x80,0x42,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,
0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,
0x00,0xc2,0x38,0x21,0x8f,0xa2,0x00,0x40,0x00,0x00,0x00,0x00,0xa4,0xe2,0x00,0x00,
0x08,0x00,0x1d,0x0c,0x26,0xb5,0xff,0xff,0x8f,0xa6,0x00,0x2c,0x00,0x00,0x20,0x21,
0x00,0xc2,0x10,0x21,0x30,0x42,0xff,0xff,0x08,0x00,0x1e,0x1a,0xaf,0xa2,0x00,0x2c,
0x8f,0xa6,0x00,0x1c,0x08,0x00,0x1e,0x04,0xa4,0xd2,0x00,0x14,0x8f,0xa5,0x00,0x48,
0x8f,0xa6,0x00,0x4c,0x8f,0xa4,0x00,0x1c,0x0c,0x00,0x1b,0xd8,0xaf,0xb7,0x00,0x10,
0x08,0x00,0x1d,0xfb,0x00,0x00,0xb8,0x21,0x0c,0x00,0x12,0x8b,0x00,0x00,0x28,0x21,
0x00,0x40,0x18,0x21,0x94,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x42,0x08,0x00,
0xa4,0x62,0x00,0x00,0x08,0x00,0x1d,0x00,0x02,0x71,0x10,0x21,0x02,0x92,0x18,0x21,
0x00,0x03,0x80,0x80,0x27,0x82,0x90,0x04,0x02,0x02,0x10,0x21,0x8c,0x44,0x00,0x18,
0x00,0x00,0x00,0x00,0x8c,0x83,0x00,0x04,0x00,0x00,0x00,0x00,0x30,0x63,0x00,0x10,
0x10,0x60,0x00,0x09,0x24,0x06,0x00,0x01,0x93,0x82,0x8b,0x71,0x00,0x00,0x00,0x00,
0x30,0x42,0x00,0x01,0x10,0x40,0xfe,0xa2,0x3c,0x04,0x00,0x80,0x27,0x85,0x90,0x00,
0x08,0x00,0x1d,0xeb,0x02,0x05,0x28,0x21,0x27,0x83,0x90,0x18,0x27,0x82,0x90,0x10,
0x02,0x03,0x18,0x21,0x02,0x02,0x10,0x21,0x90,0x64,0x00,0x00,0x90,0x45,0x00,0x05,
0x93,0x83,0x80,0x10,0x00,0x00,0x38,0x21,0x0c,0x00,0x21,0x9a,0xaf,0xa3,0x00,0x10,
0x08,0x00,0x1e,0x62,0x00,0x00,0x00,0x00,0x27,0x82,0x90,0x18,0x02,0x02,0x10,0x21,
0x94,0x43,0x00,0x02,0x8f,0xa6,0x00,0x58,0x00,0x03,0x19,0x02,0x00,0x66,0x18,0x23,
0x30,0x63,0x0f,0xff,0x28,0x62,0x00,0x20,0x10,0x40,0x00,0x06,0x28,0x62,0x00,0x40,
0x8f,0xa8,0x00,0x90,0x00,0x00,0x00,0x00,0x00,0x68,0x10,0x06,0x08,0x00,0x1c,0xd9,
0x30,0x44,0x00,0x01,0x10,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0x8f,0xa4,0x00,0x94,
0x08,0x00,0x1e,0x83,0x00,0x64,0x10,0x06,0x08,0x00,0x1c,0xd9,0x00,0x00,0x20,0x21,
0x8f,0xa4,0x00,0x98,0x8f,0xa5,0x00,0x38,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x0a,
0xaf,0xa8,0x00,0x14,0x30,0x42,0xff,0xff,0x08,0x00,0x1c,0xa9,0xaf,0xa2,0x00,0x40,
0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x00,0x27,0xbd,0xff,0xe0,0x34,0x42,0x00,0x20,
0x24,0x63,0x7a,0x50,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x18,
0xac,0x43,0x00,0x00,0x90,0x82,0x00,0x0a,0x00,0x80,0x80,0x21,0x14,0x40,0x00,0x45,
0x00,0x00,0x88,0x21,0x92,0x02,0x00,0x04,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x3c,
0x00,0x00,0x00,0x00,0x12,0x20,0x00,0x18,0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,
0x92,0x05,0x00,0x0a,0x30,0x42,0x00,0xfc,0x10,0xa0,0x00,0x03,0xa2,0x02,0x00,0x16,
0x34,0x42,0x00,0x01,0xa2,0x02,0x00,0x16,0x92,0x04,0x00,0x04,0x00,0x00,0x00,0x00,
0x30,0x83,0x00,0xff,0x10,0x60,0x00,0x05,0x00,0x00,0x00,0x00,0x92,0x02,0x00,0x16,
0x00,0x00,0x00,0x00,0x34,0x42,0x00,0x02,0xa2,0x02,0x00,0x16,0x10,0x60,0x00,0x0a,
0x00,0x00,0x00,0x00,0x14,0xa0,0x00,0x08,0x00,0x00,0x00,0x00,0x96,0x02,0x00,0x00,
0xa2,0x00,0x00,0x17,0xa6,0x02,0x00,0x14,0x8f,0xbf,0x00,0x18,0x7b,0xb0,0x00,0xbc,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x14,0x80,0x00,0x05,0x24,0x02,0x00,0x01,
0x96,0x03,0x00,0x06,0xa2,0x02,0x00,0x17,0x08,0x00,0x1e,0xbe,0xa6,0x03,0x00,0x14,
0x96,0x04,0x00,0x00,0x96,0x05,0x00,0x06,0x27,0x86,0x90,0x00,0x00,0x04,0x10,0xc0,
0x00,0x05,0x18,0xc0,0x00,0x44,0x10,0x21,0x00,0x65,0x18,0x21,0x00,0x02,0x10,0x80,
0x00,0x03,0x18,0x80,0x00,0x66,0x18,0x21,0x00,0x46,0x10,0x21,0x8c,0x65,0x00,0x08,
0x8c,0x44,0x00,0x08,0x0c,0x00,0x12,0x7c,0x00,0x00,0x00,0x00,0x30,0x43,0x00,0xff,
0x10,0x60,0x00,0x04,0xa2,0x02,0x00,0x17,0x96,0x02,0x00,0x06,0x08,0x00,0x1e,0xbe,
0xa6,0x02,0x00,0x14,0x96,0x02,0x00,0x00,0x08,0x00,0x1e,0xbe,0xa6,0x02,0x00,0x14,
0x96,0x05,0x00,0x00,0x0c,0x00,0x1e,0xea,0x02,0x00,0x20,0x21,0x08,0x00,0x1e,0xa5,
0x02,0x22,0x88,0x21,0x94,0x85,0x00,0x06,0x0c,0x00,0x1e,0xea,0x00,0x00,0x00,0x00,
0x08,0x00,0x1e,0xa1,0x00,0x40,0x88,0x21,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x00,
0x34,0x63,0x00,0x20,0x24,0x42,0x7b,0xa8,0x27,0xbd,0xff,0xf0,0xac,0x62,0x00,0x00,
0x00,0x00,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x10,0x3c,0x03,0xb0,0x03,
0x3c,0x02,0x80,0x00,0x34,0x63,0x00,0x20,0x24,0x42,0x7b,0xcc,0xac,0x62,0x00,0x00,
0x90,0x89,0x00,0x0a,0x00,0x80,0x30,0x21,0x11,0x20,0x00,0x05,0x00,0xa0,0x50,0x21,
0x90,0x82,0x00,0x17,0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1b,0x00,0x00,0x00,0x00,
0x90,0xc7,0x00,0x04,0x00,0x00,0x00,0x00,0x10,0xe0,0x00,0x1b,0x00,0x00,0x00,0x00,
0x94,0xc8,0x00,0x00,0x27,0x83,0x90,0x00,0x93,0x85,0x8b,0x70,0x00,0x08,0x10,0xc0,
0x00,0x48,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x08,
0x00,0xe5,0x28,0x2b,0x10,0xa0,0x00,0x06,0x01,0x44,0x18,0x23,0x8f,0x82,0x8b,0x88,
0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x2b,0x10,0x40,0x00,0x05,0x00,0x00,0x00,0x00,
0x24,0x03,0x00,0x10,0xa4,0xc8,0x00,0x14,0x03,0xe0,0x00,0x08,0x00,0x60,0x10,0x21,
0x11,0x20,0x00,0x05,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x06,0x24,0x03,0x00,0x08,
0x08,0x00,0x1f,0x16,0xa4,0xc2,0x00,0x14,0x08,0x00,0x1f,0x16,0x00,0x00,0x18,0x21,
0x27,0xbd,0xff,0xc8,0xaf,0xb5,0x00,0x2c,0xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,
0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x30,0xaf,0xb2,0x00,0x20,0xaf,0xb1,0x00,0x1c,
0x94,0x91,0x00,0x06,0x00,0x80,0xa0,0x21,0x3c,0x02,0x80,0x00,0x3c,0x04,0xb0,0x03,
0x00,0x11,0xa8,0xc0,0x34,0x84,0x00,0x20,0x24,0x42,0x7c,0x80,0x02,0xb1,0x48,0x21,
0xac,0x82,0x00,0x00,0x00,0x09,0x48,0x80,0x24,0x03,0x00,0x01,0x27,0x82,0x90,0x10,
0xa2,0x83,0x00,0x12,0x01,0x22,0x10,0x21,0x27,0x84,0x90,0x04,0x01,0x24,0x20,0x21,
0x80,0x48,0x00,0x06,0x8c,0x8a,0x00,0x18,0x27,0x83,0x90,0x20,0x01,0x23,0x48,0x21,
0x8d,0x24,0x00,0x00,0x25,0x08,0x00,0x02,0x8d,0x42,0x00,0x00,0x8d,0x49,0x00,0x04,
0x00,0x08,0x17,0xc2,0x8d,0x43,0x00,0x08,0x01,0x02,0x40,0x21,0x00,0x04,0x25,0xc2,
0x00,0x08,0x40,0x43,0x30,0x84,0x00,0x01,0x00,0x03,0x1f,0xc2,0x00,0x08,0x40,0x40,
0x00,0xe0,0x80,0x21,0x00,0x64,0x18,0x24,0x00,0x09,0x49,0x42,0x01,0x48,0x10,0x21,
0x00,0xa0,0x98,0x21,0x00,0xa0,0x20,0x21,0x00,0x40,0x38,0x21,0x02,0x00,0x28,0x21,
0x14,0x60,0x00,0x19,0x31,0x29,0x00,0x01,0x94,0x42,0x00,0x00,0x02,0xb1,0x88,0x21,
0x02,0x00,0x28,0x21,0x00,0x11,0x88,0x80,0x27,0x90,0x90,0x00,0x02,0x30,0x80,0x21,
0x96,0x03,0x00,0x06,0x30,0x52,0xff,0xff,0x02,0x60,0x20,0x21,0x00,0x60,0x30,0x21,
0xa6,0x83,0x00,0x1a,0x27,0x82,0x90,0x08,0x0c,0x00,0x08,0xe3,0x02,0x22,0x88,0x21,
0x00,0x52,0x10,0x21,0x96,0x03,0x00,0x06,0xa6,0x22,0x00,0x04,0x8f,0xbf,0x00,0x30,
0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x00,0x60,0x10,0x21,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x38,0xaf,0xa9,0x00,0x10,0x0c,0x00,0x09,0x0a,
0xaf,0xa0,0x00,0x14,0x08,0x00,0x1f,0x54,0x02,0xb1,0x88,0x21,0x27,0xbd,0xff,0xc0,
0xaf,0xbe,0x00,0x38,0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb5,0x00,0x2c,
0xaf,0xb3,0x00,0x24,0xaf,0xb1,0x00,0x1c,0xaf,0xbf,0x00,0x3c,0xaf,0xb4,0x00,0x28,
0xaf,0xb2,0x00,0x20,0xaf,0xb0,0x00,0x18,0x94,0x90,0x00,0x00,0x3c,0x08,0xb0,0x03,
0x35,0x08,0x00,0x20,0x00,0x10,0x10,0xc0,0x00,0x50,0x18,0x21,0x00,0x40,0x88,0x21,
0x3c,0x02,0x80,0x00,0x00,0x03,0x48,0x80,0x24,0x42,0x7d,0xbc,0x00,0x80,0x98,0x21,
0x27,0x84,0x90,0x10,0x01,0x24,0x20,0x21,0x93,0xb7,0x00,0x53,0xad,0x02,0x00,0x00,
0x80,0x83,0x00,0x06,0x27,0x82,0x90,0x04,0x01,0x22,0x10,0x21,0x8c,0x44,0x00,0x18,
0x24,0x63,0x00,0x02,0x00,0x03,0x17,0xc2,0x8c,0x88,0x00,0x08,0x00,0x62,0x18,0x21,
0x00,0x03,0x18,0x43,0x00,0x03,0x18,0x40,0xaf,0xa7,0x00,0x4c,0x2c,0xa2,0x00,0x10,
0x00,0xa0,0xa8,0x21,0x00,0x83,0x50,0x21,0x00,0x08,0x47,0xc2,0x00,0xc0,0x58,0x21,
0x00,0x00,0xb0,0x21,0x8c,0x92,0x00,0x0c,0x14,0x40,0x00,0x13,0x00,0x00,0xf0,0x21,
0x92,0x67,0x00,0x04,0x24,0x14,0x00,0x01,0x12,0x87,0x00,0x10,0x02,0x30,0x10,0x21,
0x27,0x83,0x90,0x18,0x01,0x23,0x18,0x21,0x80,0x64,0x00,0x00,0x27,0x83,0xb5,0x70,
0x00,0x04,0x11,0x00,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,
0x00,0x02,0x10,0x80,0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x04,0x00,0x00,0x00,0x00,
0x10,0x80,0x00,0x23,0x00,0x00,0x00,0x00,0x02,0x30,0x10,0x21,0x00,0x02,0x80,0x80,
0x24,0x04,0x00,0x01,0x27,0x83,0x90,0x20,0xa2,0x64,0x00,0x12,0x02,0x03,0x18,0x21,
0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,
0x01,0x02,0x10,0x24,0x14,0x40,0x00,0x0e,0x02,0xa0,0x20,0x21,0x27,0x82,0x90,0x00,
0x02,0x02,0x10,0x21,0x94,0x43,0x00,0x06,0x00,0x00,0x00,0x00,0xa6,0x63,0x00,0x1a,
0x94,0x42,0x00,0x06,0x7b,0xbe,0x01,0xfc,0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,
0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,
0x8f,0xa5,0x00,0x4c,0x01,0x60,0x30,0x21,0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,
0x0c,0x00,0x09,0x0a,0xaf,0xa0,0x00,0x14,0x08,0x00,0x1f,0xbb,0x00,0x00,0x00,0x00,
0x27,0x83,0x90,0x20,0x01,0x23,0x18,0x21,0x8c,0x62,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x02,0x15,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x14,0x40,0x00,0xaf,
0x00,0xa0,0x20,0x21,0x32,0x4f,0x00,0x03,0x00,0x12,0x10,0x82,0x25,0xe3,0x00,0x0d,
0x30,0x45,0x00,0x07,0x00,0x74,0x78,0x04,0x10,0xa0,0x00,0x0e,0x00,0x00,0x90,0x21,
0x27,0x82,0x80,0x1c,0x00,0x15,0x18,0x40,0x00,0x62,0x18,0x21,0x94,0x64,0x00,0x00,
0x24,0xa2,0x00,0x06,0x00,0x54,0x10,0x04,0x00,0x44,0x00,0x1a,0x14,0x80,0x00,0x02,
0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,0x00,0x00,0x10,0x12,0x24,0x42,0x00,0x20,
0x30,0x52,0xff,0xfc,0x02,0x30,0x10,0x21,0x27,0x83,0x90,0x10,0x00,0x02,0x10,0x80,
0x00,0x43,0x10,0x21,0x90,0x44,0x00,0x03,0x00,0x00,0x00,0x00,0x30,0x83,0x00,0xff,
0x2c,0x62,0x00,0x0c,0x14,0x40,0x00,0x04,0x2c,0x62,0x00,0x19,0x30,0x82,0x00,0x0f,
0x24,0x43,0x00,0x0c,0x2c,0x62,0x00,0x19,0x10,0x40,0x00,0x19,0x24,0x0e,0x00,0x20,
0x24,0x62,0xff,0xe9,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x15,0x24,0x0e,0x00,0x10,
0x24,0x62,0xff,0xeb,0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x11,0x24,0x0e,0x00,0x08,
0x24,0x02,0x00,0x14,0x10,0x62,0x00,0x0e,0x24,0x0e,0x00,0x02,0x24,0x62,0xff,0xef,
0x2c,0x42,0x00,0x03,0x14,0x40,0x00,0x0a,0x24,0x0e,0x00,0x10,0x24,0x62,0xff,0xf1,
0x2c,0x42,0x00,0x02,0x14,0x40,0x00,0x06,0x24,0x0e,0x00,0x08,0x24,0x62,0xff,0xf3,
0x2c,0x42,0x00,0x02,0x24,0x0e,0x00,0x04,0x24,0x03,0x00,0x02,0x00,0x62,0x70,0x0a,
0x30,0xe2,0x00,0xff,0x00,0x00,0x48,0x21,0x00,0x00,0x68,0x21,0x10,0x40,0x00,0x6d,
0x00,0x00,0x58,0x21,0x3c,0x14,0x80,0xff,0x27,0x99,0x90,0x00,0x01,0xf2,0xc0,0x23,
0x36,0x94,0xff,0xff,0x01,0xc9,0x10,0x2a,0x14,0x40,0x00,0x64,0x24,0x03,0x00,0x04,
0x00,0x10,0x28,0xc0,0x00,0xb0,0x10,0x21,0x00,0x02,0x10,0x80,0x00,0x59,0x10,0x21,
0x94,0x56,0x00,0x06,0x00,0x00,0x00,0x00,0x32,0xcc,0x00,0x03,0x00,0x6c,0x10,0x23,
0x30,0x42,0x00,0x03,0x02,0xc2,0x10,0x21,0x24,0x42,0x00,0x04,0x30,0x51,0xff,0xff,
0x02,0x32,0x18,0x2b,0x10,0x60,0x00,0x4d,0x01,0xf1,0x10,0x23,0x02,0x51,0x10,0x23,
0x01,0x78,0x18,0x2b,0x10,0x60,0x00,0x34,0x30,0x44,0xff,0xff,0x29,0x22,0x00,0x40,
0x10,0x40,0x00,0x31,0x01,0x72,0x18,0x21,0x25,0x22,0x00,0x01,0x00,0x02,0x16,0x00,
0x00,0x02,0x4e,0x03,0x00,0xb0,0x10,0x21,0x00,0x02,0x30,0x80,0x27,0x82,0x90,0x04,
0x30,0x6b,0xff,0xff,0x00,0xc2,0x18,0x21,0x8c,0x67,0x00,0x18,0x00,0x04,0x25,0x40,
0x3c,0x03,0x7f,0x00,0x8c,0xe2,0x00,0x04,0x00,0x83,0x20,0x24,0x27,0x83,0x90,0x10,
0x00,0x54,0x10,0x24,0x00,0xc3,0x28,0x21,0x00,0x44,0x10,0x25,0xac,0xe2,0x00,0x04,
0x16,0xe0,0x00,0x02,0xa0,0xb5,0x00,0x00,0xa0,0xb5,0x00,0x03,0x27,0x84,0x90,0x20,
0x00,0xc4,0x18,0x21,0x8c,0x62,0x00,0x00,0x8c,0xe8,0x00,0x08,0x00,0x02,0x15,0xc2,
0x00,0x08,0x47,0xc2,0x30,0x42,0x00,0x01,0x01,0x02,0x10,0x24,0x10,0x40,0x00,0x0a,
0x00,0x00,0x00,0x00,0x80,0xa2,0x00,0x06,0x00,0x00,0x00,0x00,0x24,0x42,0x00,0x02,
0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,0x00,0x02,0x10,0x40,
0x00,0xe2,0x50,0x21,0xa5,0x5e,0x00,0x00,0x92,0x62,0x00,0x04,0x25,0xad,0x00,0x01,
0x27,0x84,0x90,0x00,0x00,0xc4,0x18,0x21,0x01,0xa2,0x10,0x2a,0x94,0x70,0x00,0x02,
0x14,0x40,0xff,0xb8,0x00,0x00,0x00,0x00,0x96,0x63,0x00,0x14,0x00,0x0c,0x10,0x23,
0xa2,0x69,0x00,0x12,0x30,0x42,0x00,0x03,0x01,0x62,0x10,0x23,0x00,0x03,0x80,0xc0,
0x8f,0xa5,0x00,0x4c,0x30,0x4b,0xff,0xff,0x02,0x03,0x80,0x21,0x27,0x82,0x90,0x08,
0x00,0x10,0x80,0x80,0xa6,0x6b,0x00,0x1a,0x02,0xa0,0x20,0x21,0x01,0x60,0x30,0x21,
0x01,0x60,0x88,0x21,0x0c,0x00,0x08,0xe3,0x02,0x02,0x80,0x21,0x00,0x5e,0x10,0x21,
0xa6,0x02,0x00,0x04,0x08,0x00,0x1f,0xc1,0x02,0x20,0x10,0x21,0x01,0x62,0x10,0x2b,
0x10,0x40,0xff,0xe9,0x00,0x00,0x20,0x21,0x29,0x22,0x00,0x40,0x10,0x40,0xff,0xe6,
0x01,0x71,0x18,0x21,0x08,0x00,0x20,0x37,0x25,0x22,0x00,0x01,0x08,0x00,0x20,0x66,
0x32,0xcc,0x00,0x03,0x08,0x00,0x20,0x66,0x00,0x00,0x60,0x21,0x8f,0xa5,0x00,0x4c,
0x01,0x40,0x38,0x21,0xaf,0xa0,0x00,0x10,0x0c,0x00,0x09,0x0a,0xaf,0xb4,0x00,0x14,
0x92,0x67,0x00,0x04,0x08,0x00,0x1f,0xd9,0x30,0x5e,0xff,0xff,0x30,0x84,0xff,0xff,
0x00,0x04,0x30,0xc0,0x00,0xc4,0x20,0x21,0x00,0x04,0x20,0x80,0x27,0x82,0x90,0x00,
0x3c,0x03,0xb0,0x08,0x30,0xa5,0xff,0xff,0x00,0x82,0x20,0x21,0x00,0xc3,0x30,0x21,
0xac,0xc5,0x00,0x00,0x03,0xe0,0x00,0x08,0xa4,0x85,0x00,0x00,0x30,0x84,0xff,0xff,
0x00,0x04,0x30,0xc0,0x00,0xc4,0x30,0x21,0x27,0x88,0x90,0x00,0x00,0x06,0x30,0x80,
0x00,0xc8,0x30,0x21,0x94,0xc3,0x00,0x04,0x3c,0x02,0xb0,0x08,0x3c,0x07,0xb0,0x03,
0x00,0x03,0x20,0xc0,0x00,0x83,0x18,0x21,0x00,0x03,0x18,0x80,0x00,0x82,0x20,0x21,
0x3c,0x02,0x80,0x01,0x30,0xa5,0xff,0xff,0x00,0x68,0x18,0x21,0x34,0xe7,0x00,0x20,
0x24,0x42,0x82,0x6c,0xac,0xe2,0x00,0x00,0xa4,0xc5,0x00,0x02,0xa4,0x65,0x00,0x00,
0x03,0xe0,0x00,0x08,0xac,0x85,0x00,0x00,0x30,0x84,0xff,0xff,0x00,0x04,0x10,0xc0,
0x00,0x44,0x10,0x21,0x27,0x89,0x90,0x00,0x00,0x02,0x10,0x80,0x00,0x49,0x10,0x21,
0x97,0x83,0x8f,0xf0,0x94,0x4a,0x00,0x04,0x3c,0x02,0xb0,0x08,0x00,0x03,0x38,0xc0,
0x00,0x0a,0x40,0xc0,0x00,0xe3,0x18,0x21,0x01,0x0a,0x28,0x21,0x00,0xe2,0x38,0x21,
0x01,0x02,0x40,0x21,0x00,0x03,0x18,0x80,0x00,0x05,0x28,0x80,0x3c,0x06,0xb0,0x03,
0x3c,0x02,0x80,0x01,0x00,0xa9,0x28,0x21,0x00,0x69,0x18,0x21,0x34,0xc6,0x00,0x20,
0x34,0x09,0xff,0xff,0x24,0x42,0x82,0xc8,0xac,0xc2,0x00,0x00,0xa4,0x64,0x00,0x00,
0xac,0xe4,0x00,0x00,0xa4,0xa9,0x00,0x00,0xad,0x09,0x00,0x00,0xa7,0x8a,0x8f,0xf0,
0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,
0x34,0x63,0x00,0x20,0x24,0x42,0x83,0x48,0x3c,0x04,0xb0,0x03,0xac,0x62,0x00,0x00,
0x34,0x84,0x01,0x10,0x8c,0x82,0x00,0x00,0x97,0x83,0x81,0x60,0x30,0x42,0xff,0xff,
0x10,0x62,0x00,0x16,0x24,0x0a,0x00,0x01,0xa7,0x82,0x81,0x60,0xaf,0x80,0xb4,0x50,
0x00,0x40,0x28,0x21,0x24,0x06,0x00,0x01,0x27,0x84,0xb4,0x54,0x25,0x43,0xff,0xff,
0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,0x14,0x40,0x00,0x07,0x00,0x00,0x00,0x00,
0x8c,0x83,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x66,0x10,0x04,0x00,0xa2,0x10,0x24,
0x38,0x42,0x00,0x00,0x01,0x42,0x18,0x0a,0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x14,
0xac,0x83,0x00,0x00,0x14,0x40,0xff,0xf1,0x24,0x84,0x00,0x04,0x3c,0x0b,0xb0,0x03,
0x00,0x00,0x50,0x21,0x3c,0x0c,0x80,0x00,0x27,0x89,0xb4,0xa0,0x35,0x6b,0x01,0x20,
0x8d,0x68,0x00,0x00,0x8d,0x23,0x00,0x04,0x01,0x0c,0x10,0x24,0x00,0x02,0x17,0xc2,
0x11,0x03,0x00,0x37,0xa1,0x22,0x00,0xdc,0xa1,0x20,0x00,0xd5,0xa1,0x20,0x00,0xd6,
0x01,0x20,0x30,0x21,0x00,0x00,0x38,0x21,0x00,0x00,0x28,0x21,0x01,0x20,0x20,0x21,
0x00,0xa8,0x10,0x06,0x30,0x42,0x00,0x01,0x10,0xe0,0x00,0x10,0xa0,0x82,0x00,0x0a,
0x90,0x82,0x00,0x07,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x31,0x24,0xa2,0xff,0xff,
0xa0,0x82,0x00,0x08,0x90,0x82,0x00,0x0a,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x09,
0x00,0x00,0x00,0x00,0x90,0x83,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x40,
0x00,0x43,0x10,0x21,0x00,0x46,0x10,0x21,0xa0,0x45,0x00,0x09,0x90,0x82,0x00,0x0a,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x07,0x00,0x00,0x00,0x00,0x14,0xe0,0x00,0x04,
0x00,0x00,0x00,0x00,0xa0,0xc5,0x00,0xd5,0x24,0x07,0x00,0x01,0xa0,0x85,0x00,0x08,
0xa0,0xc5,0x00,0xd6,0x24,0xa5,0x00,0x01,0x2c,0xa2,0x00,0x1c,0x14,0x40,0xff,0xe0,
0x24,0x84,0x00,0x03,0x90,0xc4,0x00,0xd5,0x00,0x00,0x28,0x21,0x00,0xa4,0x10,0x2b,
0x10,0x40,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0xc0,0x18,0x21,0xa0,0x64,0x00,0x08,
0x90,0xc2,0x00,0xd5,0x24,0xa5,0x00,0x01,0xa0,0x62,0x00,0x09,0x90,0xc4,0x00,0xd5,
0x00,0x00,0x00,0x00,0x00,0xa4,0x10,0x2b,0x14,0x40,0xff,0xf8,0x24,0x63,0x00,0x03,
0x25,0x4a,0x00,0x01,0x2d,0x42,0x00,0x08,0xad,0x28,0x00,0x04,0x25,0x6b,0x00,0x04,
0x14,0x40,0xff,0xbf,0x25,0x29,0x00,0xec,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x90,0x82,0x00,0x05,0x08,0x00,0x21,0x0d,0xa0,0x82,0x00,0x08,0x97,0x85,0x8b,0x7a,
0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x63,0x00,0x20,
0x24,0x42,0x84,0xfc,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x62,0x00,0x00,
0x30,0x90,0x00,0xff,0x00,0x05,0x28,0x42,0x00,0x00,0x48,0x21,0x27,0x8f,0xb4,0xa4,
0x00,0x00,0x50,0x21,0x00,0x00,0x58,0x21,0x27,0x98,0xb5,0x84,0x27,0x99,0xb5,0x80,
0x27,0x8e,0xb5,0x7e,0x27,0x8c,0xb4,0xa8,0x27,0x8d,0xb5,0x00,0x27,0x88,0xb5,0x78,
0x00,0x0a,0x18,0x80,0x01,0x6f,0x10,0x21,0xac,0x40,0x00,0x00,0xac,0x45,0x00,0x58,
0x00,0x6e,0x20,0x21,0x00,0x78,0x10,0x21,0xa1,0x00,0xff,0xfc,0xad,0x00,0x00,0x00,
0xa1,0x00,0x00,0x04,0xa1,0x00,0x00,0x05,0xad,0x00,0xff,0xf8,0x00,0x79,0x18,0x21,
0x24,0x06,0x00,0x01,0x24,0xc6,0xff,0xff,0xa0,0x80,0x00,0x00,0xa4,0x60,0x00,0x00,
0xac,0x40,0x00,0x00,0x24,0x63,0x00,0x02,0x24,0x42,0x00,0x04,0x04,0xc1,0xff,0xf9,
0x24,0x84,0x00,0x01,0x00,0x0a,0x10,0x80,0x00,0x4d,0x20,0x21,0x00,0x00,0x30,0x21,
0x00,0x4c,0x18,0x21,0x27,0x87,0x81,0x64,0x8c,0xe2,0x00,0x00,0x24,0xe7,0x00,0x04,
0xac,0x82,0x00,0x00,0xa0,0x66,0x00,0x00,0xa0,0x66,0x00,0x01,0x24,0xc6,0x00,0x01,
0x28,0xc2,0x00,0x1c,0xa0,0x60,0x00,0x02,0x24,0x84,0x00,0x04,0x14,0x40,0xff,0xf6,
0x24,0x63,0x00,0x03,0x25,0x29,0x00,0x01,0x29,0x22,0x00,0x08,0x25,0x4a,0x00,0x3b,
0x25,0x08,0x00,0xec,0x14,0x40,0xff,0xd6,0x25,0x6b,0x00,0xec,0xa7,0x80,0x81,0x60,
0x00,0x00,0x48,0x21,0x27,0x83,0xb4,0x50,0xac,0x69,0x00,0x00,0x25,0x29,0x00,0x01,
0x29,0x22,0x00,0x0c,0x14,0x40,0xff,0xfc,0x24,0x63,0x00,0x04,0x0c,0x00,0x20,0xd2,
0x00,0x00,0x00,0x00,0x2e,0x04,0x00,0x14,0x27,0x83,0xb4,0xa0,0x24,0x09,0x00,0x07,
0x10,0x80,0x00,0x0a,0x00,0x00,0x00,0x00,0x90,0x62,0x00,0xd5,0x25,0x29,0xff,0xff,
0xa0,0x62,0x00,0x00,0x05,0x21,0xff,0xfa,0x24,0x63,0x00,0xec,0x8f,0xbf,0x00,0x14,
0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x90,0x62,0x00,0xd6,
0x08,0x00,0x21,0x90,0x25,0x29,0xff,0xff,0x30,0x84,0x00,0xff,0x00,0x04,0x11,0x00,
0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,0x00,0x44,0x10,0x23,0x00,0x02,0x10,0x80,
0x27,0x83,0xb4,0xa0,0x00,0x43,0x60,0x21,0x3c,0x04,0xb0,0x03,0x3c,0x02,0x80,0x01,
0x34,0x84,0x00,0x20,0x24,0x42,0x86,0x68,0x30,0xc6,0x00,0xff,0x93,0xaa,0x00,0x13,
0x30,0xa5,0x00,0xff,0x30,0xe7,0x00,0xff,0xac,0x82,0x00,0x00,0x10,0xc0,0x00,0xe8,
0x25,0x8f,0x00,0xd0,0x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xfc,
0x2c,0x43,0x00,0x18,0x10,0x60,0x00,0xc7,0x3c,0x03,0x80,0x01,0x00,0x02,0x10,0x80,
0x24,0x63,0x02,0x90,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x30,0x14,0x40,0x00,0x1c,
0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x17,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0x00,0x11,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0c,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x06,0x00,0x00,0x00,0x00,
0x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xe0,0x03,0xe0,0x00,0x08,
0xad,0x82,0x00,0xd0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xe8,
0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,
0x24,0x42,0x00,0x01,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,0x24,0x42,0x00,0x02,
0x10,0xa0,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x0a,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe9,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xe6,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,
0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xd0,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,
0x24,0x42,0xff,0xfc,0x10,0xa0,0xff,0xeb,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0xe5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xe0,
0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xdb,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,
0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xf8,0x2d,0x42,0x00,0x19,0x14,0x40,0xff,0xc5,
0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xdb,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0xd5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd0,
0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,
0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xf0,0x2d,0x42,0x00,0x1b,0x10,0x40,0xff,0xf1,
0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xcb,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0xc5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x14,0xa2,0xff,0xb5,
0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,0x24,0x42,0xff,0xf4,
0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xe3,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xbd,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xb5,0x24,0x02,0x00,0x02,
0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xc6,0x24,0x02,0x00,0x03,
0x2d,0x42,0x00,0x23,0x10,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xae,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xa9,0x24,0x02,0x00,0x02,
0x14,0xa2,0xff,0xb7,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x03,0x00,0x00,0x00,0x00,
0x2d,0x42,0x00,0x25,0x10,0x40,0xff,0xcb,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xd8,
0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x16,0x14,0x40,0x00,0x0e,0x00,0x00,0x00,0x00,
0x10,0xa0,0xff,0xa0,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x9a,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x95,0x24,0x02,0x00,0x03,
0x14,0xa2,0xff,0xb6,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x21,0xcb,
0x24,0x42,0xff,0xfa,0x10,0xa0,0xff,0x93,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0x8d,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x88,
0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xf3,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x17,
0x14,0x40,0xff,0xac,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x34,0x00,0x00,0x00,0x00,
0x2d,0x42,0x00,0x19,0x10,0x40,0xff,0xe2,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x81,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x7b,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x76,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x97,
0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xc8,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0x51,
0x2d,0x42,0x00,0x1b,0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xde,0x00,0x00,0x00,0x00,
0x10,0xa0,0xff,0x70,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x6a,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x65,0x24,0x02,0x00,0x03,
0x10,0xa2,0xff,0x96,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xc8,0x00,0x00,0x00,0x00,
0x2d,0x42,0x00,0x23,0x14,0x40,0xff,0xf2,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xf9,
0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xf7,0x2d,0x42,0x00,0x25,0x08,0x00,0x22,0x2d,
0x2d,0x42,0x00,0x27,0x10,0xa0,0xff,0x5b,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0x55,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x50,
0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x71,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xe6,
0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x27,0x14,0x40,0xff,0xad,0x00,0x00,0x00,0x00,
0x08,0x00,0x22,0x79,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2a,0x14,0x40,0xff,0xd8,
0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xe9,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2c,
0x14,0x40,0xff,0x78,0x00,0x00,0x00,0x00,0x08,0x00,0x21,0xbd,0x00,0x00,0x00,0x00,
0x91,0x86,0x00,0x00,0x91,0x83,0x00,0xd4,0x25,0x8d,0x00,0x5c,0x30,0xc4,0x00,0xff,
0x00,0x04,0x10,0x40,0x00,0x44,0x10,0x21,0x00,0x04,0x48,0x80,0x01,0x82,0x58,0x21,
0x01,0x89,0x40,0x21,0x25,0x78,0x00,0x08,0x10,0x60,0x00,0x37,0x25,0x0e,0x00,0x60,
0x2c,0xa2,0x00,0x03,0x14,0x40,0x00,0x25,0x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd,
0x00,0x00,0x00,0x00,0x14,0x40,0x00,0x1e,0x00,0x00,0x00,0x00,0x27,0x87,0x81,0x64,
0x01,0x27,0x10,0x21,0x8c,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x03,0x00,0x60,
0x91,0x62,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x40,0x30,0x21,0xa1,0x82,0x00,0x00,
0x30,0xc2,0x00,0xff,0x00,0x02,0x10,0x80,0x00,0x47,0x10,0x21,0x8c,0x43,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x03,0x18,0x42,0xad,0xa3,0x00,0x00,0x91,0x84,0x00,0x00,
0x8d,0xc5,0x00,0x00,0x00,0x04,0x20,0x80,0x00,0x87,0x10,0x21,0x8c,0x43,0x00,0x00,
0x00,0x05,0x28,0x40,0x00,0x8c,0x20,0x21,0x00,0x03,0x18,0x80,0x00,0xa3,0x10,0x2b,
0x00,0x62,0x28,0x0a,0xac,0x85,0x00,0x60,0x03,0xe0,0x00,0x08,0xa1,0x80,0x00,0xd4,
0x27,0x87,0x81,0x64,0x08,0x00,0x22,0xb0,0xa1,0x80,0x00,0xdd,0x27,0x82,0x81,0xd4,
0x8d,0x83,0x00,0xd8,0x00,0x82,0x10,0x21,0x90,0x44,0x00,0x00,0x24,0x63,0x00,0x01,
0x00,0x64,0x20,0x2b,0x14,0x80,0xff,0x02,0xad,0x83,0x00,0xd8,0x8d,0x02,0x00,0x60,
0xa1,0x80,0x00,0xd4,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,
0x03,0xe0,0x00,0x08,0xad,0x82,0x00,0x5c,0x10,0xe0,0x00,0x1d,0x24,0x83,0xff,0xfc,
0x2c,0x62,0x00,0x18,0x10,0x40,0x01,0x10,0x00,0x03,0x10,0x80,0x3c,0x03,0x80,0x01,
0x24,0x63,0x02,0xf0,0x00,0x43,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x80,0x00,0x08,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x30,0x14,0x40,0x00,0x65,
0x00,0x00,0x00,0x00,0x10,0xa0,0x00,0x60,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0x00,0x5a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x08,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x51,0x00,0x00,0x00,0x00,
0x8d,0x82,0x00,0xd0,0x00,0x00,0x00,0x00,0x24,0x42,0xff,0xe0,0xad,0x82,0x00,0xd0,
0x8d,0xe3,0x00,0x00,0x8d,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x21,
0xad,0xa2,0x00,0x00,0xad,0xe0,0x00,0x00,0x8d,0xa3,0x00,0x00,0x8d,0xc4,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x83,0x10,0x2a,0x10,0x40,0x00,0x22,0x00,0x00,0x00,0x00,
0x93,0x05,0x00,0x01,0x91,0x82,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x45,0x00,0x05,
0x24,0x02,0x00,0x01,0xa1,0x85,0x00,0x00,0xa1,0x82,0x00,0xd4,0x03,0xe0,0x00,0x08,
0xad,0x80,0x00,0xd8,0x91,0x82,0x00,0xdd,0x24,0x03,0x00,0x01,0x10,0x43,0x00,0x05,
0x00,0x00,0x00,0x00,0xa1,0x83,0x00,0xd4,0xad,0x80,0x00,0xd8,0x03,0xe0,0x00,0x08,
0xa1,0x83,0x00,0xdd,0x00,0x04,0x17,0xc2,0x00,0x82,0x10,0x21,0x00,0x02,0x10,0x43,
0xad,0xa2,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x81,0x64,0x8d,0xc5,0x00,0x00,
0x00,0x03,0x18,0x80,0x00,0x62,0x18,0x21,0x8c,0x64,0x00,0x00,0x00,0x05,0x28,0x40,
0x00,0x04,0x18,0x80,0x00,0xa3,0x10,0x2b,0x00,0x62,0x28,0x0a,0x08,0x00,0x22,0xc2,
0xad,0xc5,0x00,0x00,0x97,0x82,0x8b,0x7c,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x2a,
0x10,0x40,0xfe,0xab,0x00,0x00,0x00,0x00,0x91,0x82,0x00,0xdd,0x00,0x00,0x00,0x00,
0x14,0x40,0x00,0x15,0x00,0x00,0x00,0x00,0x91,0x83,0x00,0x00,0x27,0x82,0x81,0x64,
0x00,0x03,0x18,0x80,0x00,0x62,0x10,0x21,0x8c,0x44,0x00,0x00,0x00,0x6c,0x18,0x21,
0xac,0x64,0x00,0x60,0x93,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x10,0x80,
0x01,0x82,0x10,0x21,0x24,0x4e,0x00,0x60,0xa1,0x85,0x00,0x00,0x8d,0xc2,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x02,0x1f,0xc2,0x00,0x43,0x10,0x21,0x00,0x02,0x10,0x43,
0x03,0xe0,0x00,0x08,0xad,0xa2,0x00,0x00,0x08,0x00,0x23,0x37,0xa1,0x80,0x00,0xdd,
0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xe8,0x8d,0x82,0x00,0xd0,
0x08,0x00,0x22,0xf3,0x24,0x42,0x00,0x01,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,
0x24,0x42,0x00,0x02,0x10,0xa0,0xff,0xf9,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0x00,0x0a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xa0,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x9d,0x00,0x00,0x00,0x00,
0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xd0,0x8d,0x82,0x00,0xd0,
0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xfc,0x10,0xa0,0xff,0xeb,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xe5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
0x10,0xa2,0xff,0x93,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xdd,0x00,0x00,0x00,0x00,
0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xf8,0x2d,0x42,0x00,0x19,
0x14,0x40,0xff,0x7c,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xdb,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xd5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
0x10,0xa2,0xff,0x83,0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0xf1,0x00,0x00,0x00,0x00,
0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xf0,0x2d,0x42,0x00,0x1b,
0x10,0x40,0xff,0xf1,0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xcb,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0xc5,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
0x14,0xa2,0xff,0x6c,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,0x08,0x00,0x22,0xf3,
0x24,0x42,0xff,0xf4,0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xe3,0x00,0x00,0x00,0x00,
0x10,0xa0,0xff,0xbd,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x68,
0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0xd6,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xee,
0x24,0x02,0x00,0x03,0x2d,0x42,0x00,0x23,0x10,0x40,0xff,0xd7,0x00,0x00,0x00,0x00,
0x10,0xa0,0xff,0xae,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x5c,
0x24,0x02,0x00,0x02,0x14,0xa2,0xff,0xb7,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x74,
0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x25,0x10,0x40,0xff,0xcb,0x00,0x00,0x00,0x00,
0x08,0x00,0x23,0x49,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x16,0x14,0x40,0x00,0x0e,
0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0xa0,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0x9a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x48,
0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0xb6,0x00,0x00,0x00,0x00,0x8d,0x82,0x00,0xd0,
0x08,0x00,0x22,0xf3,0x24,0x42,0xff,0xfa,0x10,0xa0,0xff,0x93,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x8d,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
0x10,0xa2,0xff,0x3b,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x64,0x00,0x00,0x00,0x00,
0x2d,0x42,0x00,0x17,0x14,0x40,0xff,0xac,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xa5,
0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x19,0x10,0x40,0xff,0xe2,0x00,0x00,0x00,0x00,
0x10,0xa0,0xff,0x81,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x7b,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x29,0x24,0x02,0x00,0x03,
0x10,0xa2,0xff,0x97,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xf0,0x00,0x00,0x00,0x00,
0x08,0x00,0x23,0xc2,0x2d,0x42,0x00,0x1b,0x2d,0x42,0x00,0x1e,0x10,0x40,0xff,0xde,
0x00,0x00,0x00,0x00,0x10,0xa0,0xff,0x70,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,
0x10,0xa2,0xff,0x6a,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0xa2,0xff,0x18,
0x24,0x02,0x00,0x03,0x10,0xa2,0xff,0x96,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xf0,
0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x23,0x14,0x40,0xff,0xf2,0x00,0x00,0x00,0x00,
0x08,0x00,0x23,0x6a,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x68,0x2d,0x42,0x00,0x25,
0x08,0x00,0x23,0x9e,0x2d,0x42,0x00,0x27,0x10,0xa0,0xff,0x5b,0x00,0x00,0x00,0x00,
0x24,0x02,0x00,0x01,0x10,0xa2,0xff,0x55,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,
0x10,0xa2,0xff,0x03,0x24,0x02,0x00,0x03,0x14,0xa2,0xff,0x71,0x00,0x00,0x00,0x00,
0x08,0x00,0x23,0x57,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x27,0x14,0x40,0xff,0xad,
0x00,0x00,0x00,0x00,0x08,0x00,0x23,0xea,0x00,0x00,0x00,0x00,0x2d,0x42,0x00,0x2a,
0x14,0x40,0xff,0xd8,0x00,0x00,0x00,0x00,0x08,0x00,0x23,0x5a,0x00,0x00,0x00,0x00,
0x2d,0x42,0x00,0x2c,0x14,0x40,0xff,0x78,0x00,0x00,0x00,0x00,0x08,0x00,0x22,0xe5,
0x00,0x00,0x00,0x00,0x27,0xbd,0xff,0xe8,0x3c,0x02,0xb0,0x03,0xaf,0xbf,0x00,0x14,
0xaf,0xb0,0x00,0x10,0x34,0x42,0x01,0x18,0x3c,0x03,0xb0,0x03,0x8c,0x50,0x00,0x00,
0x34,0x63,0x01,0x2c,0x90,0x62,0x00,0x00,0x32,0x05,0x00,0x01,0xa3,0x82,0x80,0x10,
0x14,0xa0,0x00,0x14,0x30,0x44,0x00,0xff,0x32,0x02,0x01,0x00,0x14,0x40,0x00,0x09,
0x00,0x00,0x00,0x00,0x32,0x02,0x08,0x00,0x10,0x40,0x00,0x02,0x24,0x02,0x00,0x01,
0xa3,0x82,0xbc,0x18,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x18,0x0c,0x00,0x05,0x37,0x00,0x00,0x00,0x00,0x26,0x02,0xff,0x00,
0xa3,0x80,0xbc,0x18,0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x24,0x16,
0x32,0x02,0x08,0x00,0x0c,0x00,0x21,0x3f,0x00,0x00,0x00,0x00,0x26,0x02,0xff,0xff,
0x3c,0x01,0xb0,0x03,0xac,0x22,0x01,0x18,0x08,0x00,0x24,0x13,0x32,0x02,0x01,0x00,
0x27,0xbd,0xff,0xe0,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0xd0,0xaf,0xbf,0x00,0x18,
0x8c,0x43,0x00,0x00,0x3c,0x02,0x00,0x40,0x24,0x07,0x0f,0xff,0x00,0x03,0x33,0x02,
0x00,0x03,0x2d,0x02,0x00,0x03,0x43,0x02,0x30,0x69,0x0f,0xff,0x00,0x62,0x18,0x24,
0x30,0xa5,0x00,0x03,0x30,0xc6,0x00,0xff,0x10,0x60,0x00,0x08,0x31,0x08,0x00,0xff,
0x01,0x00,0x30,0x21,0x0c,0x00,0x24,0xdf,0xaf,0xa9,0x00,0x10,0x8f,0xbf,0x00,0x18,
0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x0c,0x00,0x25,0x31,
0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0xd4,0x08,0x00,0x24,0x3f,
0xac,0x62,0x00,0x00,0x27,0xbd,0xff,0xc0,0x3c,0x02,0xb0,0x03,0xaf,0xbe,0x00,0x38,
0xaf,0xb5,0x00,0x2c,0xaf,0xb1,0x00,0x1c,0xaf,0xb0,0x00,0x18,0xaf,0xbf,0x00,0x3c,
0xaf,0xb7,0x00,0x34,0xaf,0xb6,0x00,0x30,0xaf,0xb4,0x00,0x28,0xaf,0xb3,0x00,0x24,
0xaf,0xb2,0x00,0x20,0x34,0x42,0x00,0x3f,0x90,0x43,0x00,0x00,0x00,0x80,0x80,0x21,
0x00,0x00,0xf0,0x21,0x00,0x00,0x88,0x21,0x10,0x60,0x00,0x76,0x00,0x00,0xa8,0x21,
0x3c,0x01,0xb0,0x03,0xa0,0x20,0x00,0x3f,0x00,0x10,0x12,0x02,0x24,0x04,0x06,0x14,
0x0c,0x00,0x06,0xd1,0x30,0x54,0x00,0x0f,0x24,0x04,0x06,0x14,0x0c,0x00,0x06,0xd1,
0xaf,0xa2,0x00,0x10,0x3c,0x03,0x00,0xff,0x34,0x63,0xff,0xff,0x32,0x10,0x00,0x7f,
0x00,0x43,0x10,0x24,0x00,0x10,0x86,0x00,0x02,0x02,0x80,0x25,0x02,0x00,0x28,0x21,
0x24,0x04,0x06,0x14,0x3c,0x13,0xbf,0xff,0x0c,0x00,0x06,0xbf,0x3c,0x16,0xb0,0x03,
0x00,0x00,0x90,0x21,0x3c,0x17,0x40,0x00,0x36,0x73,0xff,0xff,0x36,0xd6,0x00,0x3e,
0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x00,0x00,0x57,0x10,0x25,0x00,0x40,0x28,0x21,
0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x00,0x00,0x00,0x80,0x21,0x0c,0x00,0x25,0xf9,
0x00,0x00,0x00,0x00,0x26,0x03,0x00,0x01,0x10,0x40,0x00,0x46,0x30,0x70,0x00,0xff,
0x12,0x00,0xff,0xfa,0x00,0x00,0x00,0x00,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0x00,
0x00,0x53,0x10,0x24,0x00,0x40,0x28,0x21,0x0c,0x00,0x06,0xbf,0x24,0x04,0x04,0x00,
0x24,0x02,0x00,0x01,0x12,0x82,0x00,0x37,0x00,0x00,0x00,0x00,0x12,0x80,0x00,0x35,
0x00,0x00,0x00,0x00,0x32,0x31,0x00,0x7f,0x12,0x20,0x00,0x04,0x24,0x03,0x00,0x04,
0x27,0xc2,0x00,0x01,0x30,0x5e,0x00,0xff,0x02,0xb1,0xa8,0x21,0x12,0x43,0x00,0x2a,
0x3c,0x03,0xb0,0x03,0x02,0x43,0x10,0x21,0xa0,0x51,0x00,0x34,0x26,0x42,0x00,0x01,
0x30,0x52,0x00,0xff,0x2e,0x43,0x00,0x05,0x14,0x60,0xff,0xd9,0x00,0x00,0x00,0x00,
0x8f,0xa5,0x00,0x10,0x0c,0x00,0x06,0xbf,0x24,0x04,0x06,0x14,0x12,0xa0,0x00,0x0e,
0x3c,0x02,0xb0,0x03,0x13,0xc0,0x00,0x0d,0x34,0x42,0x00,0x3c,0x00,0x15,0x10,0x40,
0x00,0x55,0x10,0x21,0x00,0x02,0x10,0xc0,0x00,0x55,0x10,0x21,0x00,0x02,0xa8,0x80,
0x02,0xbe,0x00,0x1b,0x17,0xc0,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0d,
0x00,0x00,0xa8,0x12,0x3c,0x02,0xb0,0x03,0x34,0x42,0x00,0x3c,0x3c,0x03,0xb0,0x03,
0x3c,0x04,0xb0,0x03,0xa4,0x55,0x00,0x00,0x34,0x63,0x00,0x1c,0x34,0x84,0x00,0x1d,
0x24,0x02,0x00,0x01,0xa0,0x60,0x00,0x00,0xa0,0x82,0x00,0x00,0x7b,0xbe,0x01,0xfc,
0x7b,0xb6,0x01,0xbc,0x7b,0xb4,0x01,0x7c,0x7b,0xb2,0x01,0x3c,0x7b,0xb0,0x00,0xfc,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x40,0xa2,0xd1,0x00,0x00,0x08,0x00,0x24,0x98,
0x26,0x42,0x00,0x01,0x0c,0x00,0x06,0xd1,0x24,0x04,0x04,0xfc,0x08,0x00,0x24,0x8d,
0x00,0x40,0x88,0x21,0x3c,0x03,0xb0,0x03,0x34,0x63,0x00,0x3c,0x3c,0x04,0xb0,0x03,
0x3c,0x05,0xb0,0x03,0xa4,0x60,0x00,0x00,0x34,0x84,0x00,0x1c,0x34,0xa5,0x00,0x1d,
0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x01,0xa0,0x82,0x00,0x00,0x08,0x00,0x24,0xb7,
0xa0,0xa3,0x00,0x00,0x0c,0x00,0x17,0x99,0x00,0x00,0x00,0x00,0x10,0x40,0xff,0x8b,
0x00,0x10,0x12,0x02,0x3c,0x02,0xb0,0x03,0x3c,0x04,0xb0,0x03,0x34,0x42,0x00,0x3c,
0x34,0x84,0x00,0x14,0x24,0x03,0x00,0x01,0xa4,0x40,0x00,0x00,0x3c,0x01,0xb0,0x03,
0xa0,0x23,0x00,0x3f,0x08,0x00,0x24,0xb7,0xac,0x90,0x00,0x00,0x27,0xbd,0xff,0xd8,
0xaf,0xb0,0x00,0x10,0x30,0xd0,0x00,0xff,0x2e,0x02,0x00,0x2e,0xaf,0xb2,0x00,0x18,
0xaf,0xb1,0x00,0x14,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,0x30,0xb1,0x00,0xff,
0x14,0x40,0x00,0x06,0x00,0x80,0x90,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,
0x7b,0xb0,0x00,0xbc,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x13,0x00,0x10,
0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa4,0x24,0x06,0x01,0x07,0x12,0x60,0x00,0x38,
0x02,0x00,0x30,0x21,0x8f,0xa2,0x00,0x38,0x30,0xc3,0x00,0x3f,0x3c,0x04,0xb0,0x09,
0x00,0x02,0x14,0x00,0x00,0x43,0x30,0x25,0x34,0x84,0x01,0x60,0x90,0x82,0x00,0x00,
0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x2a,
0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x24,0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x20,
0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x19,0x00,0x00,0x00,0x00,0x16,0x60,0xff,0xe2,
0x24,0x02,0x00,0x01,0x12,0x22,0x00,0x13,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0d,
0x24,0x02,0x00,0x02,0x12,0x22,0x00,0x09,0x24,0x02,0x00,0x03,0x16,0x22,0xff,0xda,
0x00,0x00,0x00,0x00,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5f,
0x3c,0x06,0x0c,0xb8,0x08,0x00,0x24,0xea,0x00,0x00,0x00,0x00,0x08,0x00,0x25,0x12,
0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xd0,0x00,0x00,0x00,0x00,0x08,0x00,0x25,0x12,
0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x12,0x24,0x04,0x08,0x44,0x24,0x04,0x08,0x4c,
0x0c,0x00,0x13,0x5f,0x24,0x05,0xff,0xff,0x08,0x00,0x25,0x07,0x00,0x00,0x00,0x00,
0x08,0x00,0x25,0x20,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xe0,0x00,0x00,0x00,0x00,
0x08,0x00,0x25,0x20,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x20,0x24,0x04,0x08,0x44,
0x02,0x40,0x20,0x21,0x0c,0x00,0x25,0x71,0x02,0x20,0x28,0x21,0x08,0x00,0x24,0xf5,
0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xd8,0x2c,0xc2,0x00,0x2e,0xaf,0xb2,0x00,0x18,
0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x20,0xaf,0xb3,0x00,0x1c,
0x00,0xc0,0x80,0x21,0x30,0xb1,0x00,0xff,0x00,0x80,0x90,0x21,0x14,0x40,0x00,0x07,
0x00,0x00,0x18,0x21,0x8f,0xbf,0x00,0x20,0x7b,0xb2,0x00,0xfc,0x7b,0xb0,0x00,0xbc,
0x00,0x60,0x10,0x21,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x28,0x2e,0x13,0x00,0x10,
0x24,0x05,0x00,0x14,0x0c,0x00,0x13,0xa4,0x24,0x06,0x01,0x07,0x12,0x60,0x00,0x24,
0x02,0x00,0x30,0x21,0x3c,0x03,0xb0,0x09,0x34,0x63,0x01,0x60,0x90,0x62,0x00,0x00,
0x00,0x00,0x00,0x00,0x14,0x40,0xff,0xfd,0x30,0xc5,0x00,0x3f,0x0c,0x00,0x25,0xae,
0x02,0x20,0x20,0x21,0x16,0x60,0x00,0x0a,0x00,0x40,0x80,0x21,0x24,0x02,0x00,0x01,
0x12,0x22,0x00,0x15,0x2a,0x22,0x00,0x02,0x14,0x40,0x00,0x0f,0x24,0x02,0x00,0x02,
0x12,0x22,0x00,0x0b,0x24,0x02,0x00,0x03,0x12,0x22,0x00,0x03,0x00,0x00,0x00,0x00,
0x08,0x00,0x25,0x3d,0x02,0x00,0x18,0x21,0x24,0x04,0x08,0x4c,0x24,0x05,0xff,0xff,
0x0c,0x00,0x13,0x5f,0x3c,0x06,0x0c,0xb8,0x08,0x00,0x25,0x3d,0x02,0x00,0x18,0x21,
0x08,0x00,0x25,0x5f,0x24,0x04,0x08,0x48,0x16,0x20,0xff,0xf5,0x00,0x00,0x00,0x00,
0x08,0x00,0x25,0x5f,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0x5f,0x24,0x04,0x08,0x44,
0x02,0x40,0x20,0x21,0x0c,0x00,0x25,0x71,0x02,0x20,0x28,0x21,0x08,0x00,0x25,0x49,
0x00,0x40,0x30,0x21,0x27,0xbd,0xff,0xe8,0x2c,0xc2,0x00,0x1f,0xaf,0xb0,0x00,0x10,
0xaf,0xbf,0x00,0x14,0x00,0xc0,0x80,0x21,0x14,0x40,0x00,0x1d,0x30,0xa5,0x00,0xff,
0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x18,0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x12,
0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0e,0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x07,
0x24,0x04,0x08,0x4c,0x26,0x10,0xff,0xe2,0x02,0x00,0x10,0x21,0x8f,0xbf,0x00,0x14,
0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x24,0x05,0xff,0xff,
0x0c,0x00,0x13,0x5f,0x3c,0x06,0x0d,0xf8,0x08,0x00,0x25,0x82,0x26,0x10,0xff,0xe2,
0x08,0x00,0x25,0x87,0x24,0x04,0x08,0x48,0x14,0xa0,0xff,0xf2,0x24,0x04,0x08,0x40,
0x08,0x00,0x25,0x88,0x24,0x05,0xff,0xff,0x08,0x00,0x25,0x87,0x24,0x04,0x08,0x44,
0x2c,0xc2,0x00,0x10,0x14,0x40,0xff,0xec,0x24,0x02,0x00,0x01,0x10,0xa2,0x00,0x14,
0x28,0xa2,0x00,0x02,0x14,0x40,0x00,0x0e,0x24,0x02,0x00,0x02,0x10,0xa2,0x00,0x0a,
0x24,0x02,0x00,0x03,0x10,0xa2,0x00,0x03,0x24,0x04,0x08,0x4c,0x08,0x00,0x25,0x82,
0x26,0x10,0xff,0xf1,0x24,0x05,0xff,0xff,0x0c,0x00,0x13,0x5f,0x3c,0x06,0x0d,0xb8,
0x08,0x00,0x25,0x82,0x26,0x10,0xff,0xf1,0x08,0x00,0x25,0xa1,0x24,0x04,0x08,0x48,
0x14,0xa0,0xff,0xf6,0x24,0x04,0x08,0x40,0x08,0x00,0x25,0xa2,0x24,0x05,0xff,0xff,
0x08,0x00,0x25,0xa1,0x24,0x04,0x08,0x44,0x27,0xbd,0xff,0xe8,0x30,0x84,0x00,0xff,
0x24,0x02,0x00,0x01,0x10,0x82,0x00,0x39,0xaf,0xbf,0x00,0x10,0x28,0x82,0x00,0x02,
0x14,0x40,0x00,0x27,0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x02,0x10,0x82,0x00,0x17,
0x00,0xa0,0x30,0x21,0x24,0x02,0x00,0x03,0x10,0x82,0x00,0x05,0x24,0x04,0x08,0x3c,
0x8f,0xbf,0x00,0x10,0x00,0x00,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,
0x0c,0x00,0x13,0x5f,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x3c,0x3c,0x05,0x80,0x00,
0x0c,0x00,0x13,0x5f,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x3c,0x3c,0x05,0x80,0x00,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,0x24,0x04,0x08,0xac,0x0c,0x00,0x13,0x41,
0x24,0x05,0x0f,0xff,0x08,0x00,0x25,0xbc,0x00,0x00,0x00,0x00,0x24,0x04,0x08,0x34,
0x0c,0x00,0x13,0x5f,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x34,0x3c,0x05,0x80,0x00,
0x0c,0x00,0x13,0x5f,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x34,0x3c,0x05,0x80,0x00,
0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,0x08,0x00,0x25,0xcb,0x24,0x04,0x08,0xa8,
0x14,0x80,0xff,0xdf,0x00,0xa0,0x30,0x21,0x24,0x04,0x08,0x24,0x0c,0x00,0x13,0x5f,
0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x24,0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f,
0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x24,0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f,
0x24,0x06,0x00,0x01,0x08,0x00,0x25,0xcb,0x24,0x04,0x08,0xa0,0x00,0xa0,0x30,0x21,
0x24,0x04,0x08,0x2c,0x0c,0x00,0x13,0x5f,0x3c,0x05,0x3f,0x00,0x24,0x04,0x08,0x2c,
0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f,0x00,0x00,0x30,0x21,0x24,0x04,0x08,0x2c,
0x3c,0x05,0x80,0x00,0x0c,0x00,0x13,0x5f,0x24,0x06,0x00,0x01,0x08,0x00,0x25,0xcb,
0x24,0x04,0x08,0xa4,0x3c,0x05,0x00,0x14,0x3c,0x02,0xb0,0x05,0x34,0x42,0x04,0x20,
0x3c,0x06,0xc0,0x00,0x3c,0x03,0xb0,0x05,0x3c,0x04,0xb0,0x05,0x34,0xa5,0x17,0x09,
0xac,0x45,0x00,0x00,0x34,0xc6,0x05,0x07,0x34,0x63,0x04,0x24,0x34,0x84,0x02,0x28,
0x3c,0x07,0xb0,0x05,0x24,0x02,0x00,0x20,0xac,0x66,0x00,0x00,0x34,0xe7,0x04,0x50,
0xa0,0x82,0x00,0x00,0x90,0xe2,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x03,
0x10,0x40,0xff,0xfc,0x24,0x02,0x00,0x01,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x93,0x85,0x81,0xf1,0x24,0x02,0x00,0x01,0x14,0xa2,0x00,0x53,0x00,0x80,0x40,0x21,
0x8c,0x89,0x00,0x04,0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21,0x8c,0xc3,0x00,0x04,
0x3c,0x02,0x01,0x00,0x00,0x62,0x10,0x24,0x10,0x40,0x00,0x4b,0x30,0x62,0x00,0x08,
0x10,0x45,0x00,0x59,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,0x24,0x03,0x00,0xb4,
0x30,0x44,0x00,0xff,0x10,0x83,0x00,0x61,0x24,0x02,0x00,0xc4,0x10,0x82,0x00,0x54,
0x24,0x02,0x00,0x94,0x10,0x82,0x00,0x45,0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x38,
0x00,0x00,0x00,0x00,0x30,0x47,0xff,0xff,0x30,0xe3,0x40,0xff,0x24,0x02,0x40,0x88,
0x14,0x62,0x00,0x39,0x30,0xe3,0x03,0x00,0x24,0x02,0x03,0x00,0x10,0x62,0x00,0x38,
0x00,0x00,0x00,0x00,0x94,0xc2,0x00,0x56,0x00,0x00,0x00,0x00,0x30,0x47,0xff,0xff,
0x30,0xe2,0x00,0x80,0x14,0x40,0x00,0x30,0x3c,0x02,0xb0,0x01,0x01,0x22,0x30,0x21,
0x94,0xc3,0x00,0x60,0x24,0x02,0x00,0x08,0x14,0x43,0x00,0x3b,0x00,0x00,0x00,0x00,
0x90,0xc2,0x00,0x62,0x24,0x03,0x00,0x04,0x00,0x02,0x39,0x02,0x10,0xe3,0x00,0x15,
0x24,0x02,0x00,0x06,0x14,0xe2,0x00,0x34,0x00,0x00,0x00,0x00,0x8d,0x05,0x01,0xac,
0x94,0xc4,0x00,0x66,0x27,0x82,0x89,0x68,0x00,0x05,0x28,0x80,0x30,0x87,0xff,0xff,
0x00,0xa2,0x28,0x21,0x00,0x07,0x1a,0x00,0x8c,0xa4,0x00,0x00,0x00,0x07,0x12,0x02,
0x00,0x43,0x10,0x25,0x24,0x42,0x00,0x5e,0x24,0x03,0xc0,0x00,0x30,0x47,0xff,0xff,
0x00,0x83,0x20,0x24,0x00,0x87,0x20,0x25,0xac,0xa4,0x00,0x00,0x08,0x00,0x26,0x76,
0xad,0x07,0x00,0x10,0x8d,0x05,0x01,0xac,0x94,0xc4,0x00,0x64,0x27,0x82,0x89,0x68,
0x00,0x05,0x28,0x80,0x30,0x87,0xff,0xff,0x00,0xa2,0x28,0x21,0x00,0x07,0x1a,0x00,
0x8c,0xa4,0x00,0x00,0x00,0x07,0x12,0x02,0x00,0x43,0x10,0x25,0x24,0x42,0x00,0x36,
0x3c,0x03,0xff,0xff,0x30,0x47,0xff,0xff,0x00,0x83,0x20,0x24,0x00,0x87,0x20,0x25,
0xac,0xa4,0x00,0x00,0xad,0x07,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x94,0xc2,0x00,0x50,0x08,0x00,0x26,0x34,0x30,0x47,0xff,0xff,0x8d,0x04,0x01,0xac,
0x27,0x83,0x89,0x68,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,
0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x2e,0xac,0x82,0x00,0x00,
0x24,0x03,0x00,0x2e,0xad,0x03,0x00,0x10,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x8d,0x04,0x01,0xac,0x27,0x83,0x89,0x68,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,
0x8c,0x82,0x00,0x00,0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x0e,
0x24,0x03,0x00,0x0e,0x08,0x00,0x26,0x75,0xac,0x82,0x00,0x00,0x8d,0x04,0x01,0xac,
0x27,0x83,0x89,0x68,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,
0x3c,0x03,0xff,0xff,0x00,0x43,0x10,0x24,0x34,0x42,0x00,0x14,0x24,0x03,0x00,0x14,
0x08,0x00,0x26,0x75,0xac,0x82,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x30,0xc6,0x00,0xff,0x00,0x06,0x48,0x40,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80,
0x27,0x8b,0xbc,0x30,0x27,0x83,0xbc,0x36,0x00,0x4b,0x40,0x21,0x00,0x43,0x10,0x21,
0x94,0x47,0x00,0x00,0x30,0xa2,0x3f,0xff,0x10,0xe2,0x00,0x29,0x30,0x8a,0xff,0xff,
0x95,0x02,0x00,0x02,0x24,0x03,0x00,0x01,0x00,0x02,0x11,0x82,0x30,0x42,0x00,0x01,
0x10,0x43,0x00,0x18,0x00,0x00,0x00,0x00,0x01,0x26,0x10,0x21,0x00,0x02,0x10,0x80,
0x00,0x4b,0x30,0x21,0x94,0xc4,0x00,0x02,0x27,0x83,0xbc,0x36,0x27,0x85,0xbc,0x34,
0x00,0x45,0x28,0x21,0x30,0x84,0xff,0xdf,0x00,0x43,0x10,0x21,0xa4,0xc4,0x00,0x02,
0xa4,0x40,0x00,0x00,0xa4,0xa0,0x00,0x00,0x94,0xc3,0x00,0x02,0x3c,0x04,0xb0,0x01,
0x01,0x44,0x20,0x21,0x30,0x63,0xff,0xbf,0xa4,0xc3,0x00,0x02,0xa0,0xc0,0x00,0x00,
0x8c,0x82,0x00,0x04,0x24,0x03,0xf0,0xff,0x00,0x43,0x10,0x24,0x03,0xe0,0x00,0x08,
0xac,0x82,0x00,0x04,0x24,0x02,0xc0,0x00,0x91,0x04,0x00,0x01,0x00,0xa2,0x10,0x24,
0x00,0x47,0x28,0x25,0x3c,0x03,0xb0,0x01,0x24,0x02,0x00,0x02,0x14,0x82,0xff,0xe2,
0x01,0x43,0x18,0x21,0xac,0x65,0x00,0x00,0x08,0x00,0x26,0xa3,0x01,0x26,0x10,0x21,
0x08,0x00,0x26,0xa3,0x01,0x26,0x10,0x21,0x93,0x83,0x81,0xf1,0x24,0x02,0x00,0x01,
0x14,0x62,0x00,0x0d,0x3c,0x02,0xb0,0x01,0x8c,0x84,0x00,0x04,0x3c,0x06,0xb0,0x09,
0x00,0x82,0x20,0x21,0x8c,0x85,0x00,0x08,0x8c,0x83,0x00,0x04,0x3c,0x02,0x01,0x00,
0x34,0xc6,0x01,0x00,0x00,0x62,0x18,0x24,0x14,0x60,0x00,0x05,0x30,0xa5,0x20,0x00,
0x24,0x02,0x00,0x06,0xa0,0xc2,0x00,0x00,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,
0x3c,0x03,0xb0,0x09,0x10,0xa0,0xff,0xfc,0x34,0x63,0x01,0x00,0x24,0x02,0x00,0x0e,
0x08,0x00,0x26,0xd6,0xa0,0x62,0x00,0x00,0x3c,0x02,0xb0,0x01,0x30,0xa5,0xff,0xff,
0x00,0xa2,0x28,0x21,0x8c,0xa3,0x00,0x00,0x3c,0x02,0x10,0x00,0x00,0x80,0x30,0x21,
0x00,0x62,0x18,0x24,0x8c,0xa2,0x00,0x04,0x10,0x60,0x00,0x04,0x00,0x00,0x00,0x00,
0x30,0x42,0x80,0x00,0x10,0x40,0x00,0x13,0x00,0x00,0x00,0x00,0x8c,0xc2,0x01,0xa8,
0x00,0x00,0x00,0x00,0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,
0x00,0x83,0x10,0x0a,0x93,0x83,0x81,0xf0,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,
0x00,0x82,0x20,0x23,0x24,0x63,0xff,0xff,0xac,0xc4,0x01,0xa8,0xa3,0x83,0x81,0xf0,
0x8c,0xc4,0x01,0xac,0x8c,0xc2,0x01,0xa8,0x00,0x00,0x00,0x00,0x00,0x44,0x10,0x26,
0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x3c,0x03,0xb0,0x03,
0x34,0x63,0x00,0x73,0x90,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x42,0x00,0x01,
0x14,0x40,0x00,0x04,0x00,0x00,0x00,0x00,0xa3,0x80,0x81,0xf1,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x24,0x02,0x00,0x01,0xa3,0x82,0x81,0xf1,0x03,0xe0,0x00,0x08,
0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x04,0x3c,0x05,0xb0,0x01,0x00,0x80,0x50,0x21,
0x00,0x45,0x10,0x21,0x8c,0x43,0x00,0x04,0x24,0x02,0x00,0x05,0x00,0x03,0x1a,0x02,
0x30,0x69,0x00,0x0f,0x11,0x22,0x00,0x0b,0x24,0x02,0x00,0x07,0x11,0x22,0x00,0x09,
0x24,0x02,0x00,0x0a,0x11,0x22,0x00,0x07,0x24,0x02,0x00,0x0b,0x11,0x22,0x00,0x05,
0x24,0x02,0x00,0x01,0x93,0x83,0x81,0xf0,0x3c,0x04,0xb0,0x06,0x10,0x62,0x00,0x03,
0x34,0x84,0x80,0x18,0x03,0xe0,0x00,0x08,0x00,0x00,0x00,0x00,0x8c,0x82,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x02,0x17,0x02,0x14,0x40,0xff,0xfa,0x00,0x00,0x00,0x00,
0x8d,0x43,0x01,0xa8,0x27,0x82,0x89,0x68,0x00,0x03,0x18,0x80,0x00,0x6a,0x20,0x21,
0x8c,0x87,0x00,0xa8,0x00,0x62,0x18,0x21,0x8c,0x68,0x00,0x00,0x00,0xe5,0x28,0x21,
0x8c,0xa9,0x00,0x00,0x3c,0x02,0xff,0xff,0x27,0x83,0x8a,0x68,0x01,0x22,0x10,0x24,
0x00,0x48,0x10,0x25,0xac,0xa2,0x00,0x00,0x8d,0x44,0x01,0xa8,0x00,0x07,0x30,0xc2,
0x3c,0x02,0x00,0x80,0x00,0x04,0x20,0x80,0x00,0x83,0x20,0x21,0x00,0x06,0x32,0x00,
0x8c,0xa9,0x00,0x04,0x00,0xc2,0x30,0x25,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00,
0x01,0x22,0x10,0x25,0x00,0x43,0x10,0x25,0xac,0xa2,0x00,0x04,0xaf,0x87,0xbc,0x20,
0x8c,0xa2,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x82,0xbc,0x28,0x8c,0xa3,0x00,0x04,
0x3c,0x01,0xb0,0x07,0xac,0x26,0x80,0x18,0x8d,0x42,0x01,0xa8,0xaf,0x83,0xbc,0x24,
0x93,0x85,0x81,0xf0,0x24,0x44,0x00,0x01,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,
0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0xa5,0xff,0xff,
0x00,0x82,0x20,0x23,0xad,0x44,0x01,0xa8,0xa3,0x85,0x81,0xf0,0x08,0x00,0x27,0x21,
0x00,0x00,0x00,0x00,0x3c,0x05,0xb0,0x03,0x3c,0x02,0x80,0x01,0x34,0xa5,0x00,0x20,
0x24,0x42,0x9d,0x64,0xac,0xa2,0x00,0x00,0x24,0x02,0x00,0x02,0x24,0x03,0x00,0x20,
0xac,0x82,0x00,0x64,0x3c,0x02,0x80,0x01,0xac,0x83,0x00,0x60,0xac,0x80,0x00,0x00,
0xac,0x80,0x00,0x04,0xac,0x80,0x00,0x08,0xac,0x80,0x00,0x4c,0xac,0x80,0x00,0x50,
0xac,0x80,0x00,0x54,0xac,0x80,0x00,0x0c,0xac,0x80,0x00,0x58,0xa0,0x80,0x00,0x5c,
0x24,0x42,0x9e,0x28,0x24,0x83,0x00,0x68,0x24,0x05,0x00,0x0f,0x24,0xa5,0xff,0xff,
0xac,0x62,0x00,0x00,0x04,0xa1,0xff,0xfd,0x24,0x63,0x00,0x04,0x3c,0x02,0x80,0x01,
0x24,0x42,0x9f,0x10,0xac,0x82,0x00,0x78,0x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01,
0x24,0x63,0xa0,0x9c,0x24,0x42,0xa0,0x08,0xac,0x83,0x00,0x88,0xac,0x82,0x00,0x98,
0x3c,0x03,0x80,0x01,0x3c,0x02,0x80,0x01,0x24,0x63,0xa1,0x44,0x24,0x42,0xa2,0x5c,
0xac,0x83,0x00,0xa0,0xac,0x82,0x00,0xa4,0xa0,0x80,0x01,0xba,0xac,0x80,0x01,0xa8,
0xac,0x80,0x01,0xac,0xac,0x80,0x01,0xb0,0xac,0x80,0x01,0xb4,0xa0,0x80,0x01,0xb8,
0x03,0xe0,0x00,0x08,0xa0,0x80,0x01,0xb9,0x3c,0x03,0xb0,0x03,0x3c,0x02,0x80,0x01,
0x34,0x63,0x00,0x20,0x24,0x42,0x9e,0x28,0x03,0xe0,0x00,0x08,0xac,0x62,0x00,0x00,
0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0x9e,0x40,
0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x10,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x11,
0x00,0x80,0x28,0x21,0x8c,0x82,0x00,0x14,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0d,
0x00,0x00,0x00,0x00,0x8c,0x84,0x00,0x10,0x8c,0xa3,0x00,0x14,0x8c,0xa2,0x00,0x04,
0x00,0x83,0x20,0x21,0x00,0x44,0x10,0x21,0x30,0x43,0x00,0xff,0x00,0x03,0x18,0x2b,
0x00,0x02,0x12,0x02,0x00,0x43,0x10,0x21,0x00,0x02,0x12,0x00,0x30,0x42,0x3f,0xff,
0xac,0xa2,0x00,0x04,0xac,0xa0,0x00,0x00,0xac,0xa0,0x00,0x4c,0xac,0xa0,0x00,0x50,
0xac,0xa0,0x00,0x54,0x03,0xe0,0x00,0x08,0xac,0xa0,0x00,0x0c,0x3c,0x03,0xb0,0x03,
0x3c,0x02,0x80,0x01,0x34,0x63,0x00,0x20,0x24,0x42,0x9e,0xbc,0xac,0x62,0x00,0x00,
0x8c,0x86,0x00,0x04,0x3c,0x02,0xb0,0x01,0x24,0x03,0x00,0x01,0x00,0xc2,0x10,0x21,
0x8c,0x45,0x00,0x00,0xac,0x83,0x00,0x4c,0x00,0x05,0x14,0x02,0x30,0xa3,0x3f,0xff,
0x30,0x42,0x00,0xff,0xac,0x83,0x00,0x10,0xac,0x82,0x00,0x14,0x8c,0x83,0x00,0x14,
0xac,0x85,0x00,0x40,0x00,0xc3,0x30,0x21,0x03,0xe0,0x00,0x08,0xac,0x86,0x00,0x08,
0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,
0x24,0x63,0x9f,0x10,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,
0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x0a,0x00,0x80,0x80,0x21,
0xae,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,
0xae,0x00,0x00,0x0c,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xaf,0x00,0x00,0x00,0x00,0x08,0x00,0x27,0xd1,
0xae,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
0x34,0x42,0x00,0x20,0x24,0x63,0x9f,0x74,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x4c,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x16,
0x00,0x80,0x80,0x21,0x8e,0x03,0x00,0x08,0x3c,0x02,0xb0,0x01,0x8e,0x04,0x00,0x44,
0x00,0x62,0x18,0x21,0x90,0x65,0x00,0x00,0x24,0x02,0x00,0x01,0xae,0x02,0x00,0x50,
0x30,0xa3,0x00,0xff,0x00,0x03,0x10,0x82,0x00,0x04,0x23,0x02,0x30,0x84,0x00,0x0f,
0x30,0x42,0x00,0x03,0x00,0x03,0x19,0x02,0xae,0x04,0x00,0x34,0xae,0x02,0x00,0x2c,
0xae,0x03,0x00,0x30,0xa2,0x05,0x00,0x48,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,
0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xaf,0x00,0x00,0x00,0x00,
0x08,0x00,0x27,0xe9,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,
0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa0,0x08,0xaf,0xb0,0x00,0x10,
0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,0x00,0x00,0x00,0x00,
0x10,0x40,0x00,0x16,0x00,0x80,0x80,0x21,0x92,0x03,0x00,0x44,0x8e,0x02,0x00,0x40,
0x83,0x85,0x8b,0xd4,0x92,0x04,0x00,0x41,0x30,0x63,0x00,0x01,0x00,0x02,0x16,0x02,
0xae,0x04,0x00,0x14,0x00,0x00,0x30,0x21,0xae,0x02,0x00,0x18,0x10,0xa0,0x00,0x04,
0xae,0x03,0x00,0x3c,0x10,0x60,0x00,0x03,0x24,0x02,0x00,0x01,0x24,0x06,0x00,0x01,
0x24,0x02,0x00,0x01,0xa3,0x86,0x8b,0xd4,0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,
0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xdd,
0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x0e,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa0,0x9c,
0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x50,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x1b,0x00,0x80,0x80,0x21,0x3c,0x02,0xb0,0x03,
0x8c,0x42,0x00,0x00,0x92,0x04,0x00,0x44,0x8e,0x03,0x00,0x40,0x83,0x86,0x8b,0xd4,
0x92,0x05,0x00,0x41,0x30,0x42,0x08,0x00,0x30,0x84,0x00,0x01,0x00,0x02,0x12,0xc2,
0x00,0x03,0x1e,0x02,0x00,0x82,0x20,0x25,0xae,0x05,0x00,0x14,0x00,0x00,0x38,0x21,
0xae,0x03,0x00,0x18,0x10,0xc0,0x00,0x04,0xae,0x04,0x00,0x3c,0x10,0x80,0x00,0x03,
0x24,0x02,0x00,0x01,0x24,0x07,0x00,0x01,0x24,0x02,0x00,0x01,0xa3,0x87,0x8b,0xd4,
0x8f,0xbf,0x00,0x14,0xae,0x02,0x00,0x54,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x18,0x0c,0x00,0x27,0xdd,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x33,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,
0x34,0x42,0x00,0x20,0x24,0x63,0xa1,0x44,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,
0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x37,
0x00,0x80,0x80,0x21,0x8e,0x04,0x00,0x04,0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00,
0x3c,0x05,0xb0,0x01,0x34,0x42,0x00,0x10,0x00,0x85,0x20,0x21,0x00,0x62,0x18,0x25,
0xac,0x83,0x00,0x04,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x02,0x00,0x20,0x21,
0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x00,0x00,0x03,0x18,0x80,0x27,0x82,0x89,0x68,
0x00,0x62,0x18,0x21,0xac,0x66,0x00,0x00,0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,
0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x04,0x00,0x03,0x18,0x80,0x27,0x82,0x8a,0x68,
0x00,0x62,0x18,0x21,0x0c,0x00,0x26,0x10,0xac,0x66,0x00,0x00,0x8e,0x03,0x01,0xac,
0x8e,0x07,0x00,0x04,0x3c,0x06,0xb0,0x03,0x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00,
0x24,0x62,0x00,0x40,0x00,0xa4,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,
0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x23,0x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac,
0xac,0x67,0x00,0xa8,0x34,0xc6,0x00,0x30,0x8c,0xc3,0x00,0x00,0x93,0x82,0x81,0xf0,
0x02,0x00,0x20,0x21,0x24,0x63,0x00,0x01,0x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00,
0xa3,0x82,0x81,0xf0,0x0c,0x00,0x27,0x90,0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,
0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0x27,
0x00,0x00,0x00,0x00,0x08,0x00,0x28,0x5d,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0x80,0x01,0x27,0xbd,0xff,0xe8,0x34,0x42,0x00,0x20,0x24,0x63,0xa2,0x5c,
0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x14,0xac,0x43,0x00,0x00,0x8c,0x82,0x00,0x54,
0x00,0x00,0x00,0x00,0x10,0x40,0x00,0x37,0x00,0x80,0x80,0x21,0x8e,0x04,0x00,0x04,
0x8e,0x03,0x00,0x44,0x3c,0x02,0x80,0x00,0x3c,0x05,0xb0,0x01,0x34,0x42,0x00,0x10,
0x00,0x85,0x20,0x21,0x00,0x62,0x18,0x25,0xac,0x83,0x00,0x04,0x8e,0x02,0x00,0x04,
0x8e,0x03,0x01,0xac,0x02,0x00,0x20,0x21,0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x00,
0x00,0x03,0x18,0x80,0x27,0x82,0x89,0x68,0x00,0x62,0x18,0x21,0xac,0x66,0x00,0x00,
0x8e,0x02,0x00,0x04,0x8e,0x03,0x01,0xac,0x00,0x45,0x10,0x21,0x8c,0x46,0x00,0x04,
0x00,0x03,0x18,0x80,0x27,0x82,0x8a,0x68,0x00,0x62,0x18,0x21,0x0c,0x00,0x26,0x10,
0xac,0x66,0x00,0x00,0x8e,0x03,0x01,0xac,0x8e,0x07,0x00,0x04,0x3c,0x06,0xb0,0x03,
0x24,0x65,0x00,0x01,0x28,0xa4,0x00,0x00,0x24,0x62,0x00,0x40,0x00,0xa4,0x10,0x0a,
0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x03,0x18,0x80,0x00,0xa2,0x28,0x23,
0x00,0x70,0x18,0x21,0xae,0x05,0x01,0xac,0xac,0x67,0x00,0xa8,0x34,0xc6,0x00,0x30,
0x8c,0xc3,0x00,0x00,0x93,0x82,0x81,0xf0,0x02,0x00,0x20,0x21,0x24,0x63,0x00,0x01,
0x24,0x42,0x00,0x01,0xac,0xc3,0x00,0x00,0xa3,0x82,0x81,0xf0,0x0c,0x00,0x27,0x90,
0x00,0x00,0x00,0x00,0x8f,0xbf,0x00,0x14,0x8f,0xb0,0x00,0x10,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x18,0x0c,0x00,0x28,0x27,0x00,0x00,0x00,0x00,0x08,0x00,0x28,0xa3,
0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,
0x24,0x63,0xa3,0x74,0x27,0xbd,0xff,0xe0,0xac,0x43,0x00,0x00,0x3c,0x02,0x80,0x01,
0xaf,0xb2,0x00,0x18,0xaf,0xb1,0x00,0x14,0xaf,0xb0,0x00,0x10,0xaf,0xbf,0x00,0x1c,
0x00,0x80,0x80,0x21,0x24,0x52,0x9e,0x28,0x00,0x00,0x88,0x21,0x3c,0x03,0xb0,0x09,
0x34,0x63,0x00,0x06,0x8e,0x06,0x00,0x04,0x90,0x62,0x00,0x00,0x00,0x06,0x22,0x02,
0x00,0x44,0x10,0x23,0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f,
0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x24,0x84,0xff,0xff,
0x10,0x44,0x00,0x68,0x00,0x00,0x28,0x21,0x3c,0x02,0xb0,0x01,0x00,0xc2,0x10,0x21,
0x8c,0x44,0x00,0x04,0x3c,0x03,0x7c,0x00,0x34,0x63,0x00,0xf0,0x00,0x83,0x18,0x24,
0xae,0x04,0x00,0x44,0x8c,0x44,0x00,0x00,0x10,0x60,0x00,0x69,0x00,0x00,0x38,0x21,
0x3c,0x09,0xb0,0x03,0x3c,0x06,0x7c,0x00,0x35,0x29,0x00,0x99,0x3c,0x0a,0xb0,0x01,
0x24,0x08,0x00,0x40,0x34,0xc6,0x00,0xf0,0x3c,0x0b,0xff,0xff,0x3c,0x0c,0x28,0x38,
0x16,0x20,0x00,0x06,0x24,0xa5,0x00,0x01,0x93,0x82,0x81,0xf6,0x24,0x11,0x00,0x01,
0x24,0x42,0x00,0x01,0xa1,0x22,0x00,0x00,0xa3,0x82,0x81,0xf6,0x8e,0x02,0x00,0x04,
0x24,0x07,0x00,0x01,0x24,0x42,0x01,0x00,0x30,0x42,0x3f,0xff,0xae,0x02,0x00,0x04,
0x00,0x4a,0x10,0x21,0x8c,0x43,0x00,0x04,0x00,0x00,0x00,0x00,0xae,0x03,0x00,0x44,
0x8c,0x44,0x00,0x00,0x10,0xa8,0x00,0x2d,0x00,0x66,0x18,0x24,0x14,0x60,0xff,0xec,
0x00,0x8b,0x10,0x24,0x14,0x4c,0xff,0xea,0x24,0x02,0x00,0x01,0x10,0xe2,0x00,0x2f,
0x3c,0x03,0xb0,0x09,0x8e,0x02,0x00,0x44,0x8e,0x04,0x00,0x60,0x00,0x02,0x1e,0x42,
0x00,0x02,0x12,0x02,0x30,0x42,0x00,0x0f,0x30,0x63,0x00,0x01,0xae,0x02,0x00,0x00,
0x10,0x44,0x00,0x1a,0xae,0x03,0x00,0x58,0x8e,0x02,0x00,0x64,0x8e,0x04,0x00,0x58,
0x00,0x00,0x00,0x00,0x10,0x82,0x00,0x05,0x00,0x00,0x00,0x00,0xae,0x00,0x00,0x4c,
0xae,0x00,0x00,0x50,0xae,0x00,0x00,0x54,0xae,0x00,0x00,0x0c,0x8e,0x03,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x03,0x10,0x80,0x00,0x50,0x10,0x21,0x8c,0x42,0x00,0x68,
0x00,0x00,0x00,0x00,0x10,0x52,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x40,0xf8,0x09,
0x02,0x00,0x20,0x21,0x8e,0x04,0x00,0x58,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,
0xae,0x03,0x00,0x60,0x08,0x00,0x28,0xeb,0xae,0x04,0x00,0x64,0x8e,0x02,0x00,0x64,
0x00,0x00,0x00,0x00,0x14,0x62,0xff,0xe5,0x00,0x00,0x00,0x00,0x7a,0x02,0x0d,0x7c,
0x8f,0xbf,0x00,0x1c,0x8f,0xb2,0x00,0x18,0x7b,0xb0,0x00,0xbc,0x00,0x43,0x10,0x26,
0x00,0x02,0x10,0x2b,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x20,0x34,0x63,0x00,0x06,
0x8e,0x04,0x00,0x04,0x90,0x62,0x00,0x00,0x00,0x04,0x22,0x02,0x00,0x44,0x10,0x23,
0x24,0x44,0x00,0x40,0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x7f,0x00,0x83,0x10,0x0a,
0x00,0x02,0x11,0x83,0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0x14,0x87,0xff,0xc5,
0x00,0x00,0x00,0x00,0x8e,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x62,0x00,0x03,
0x14,0x40,0x00,0x05,0x24,0x02,0x00,0x0d,0x10,0x62,0x00,0x03,0x24,0x02,0x00,0x01,
0x08,0x00,0x29,0x4b,0xa2,0x02,0x00,0x5c,0x08,0x00,0x29,0x4b,0xa2,0x00,0x00,0x5c,
0x3c,0x02,0xff,0xff,0x00,0x82,0x10,0x24,0x3c,0x03,0x28,0x38,0x14,0x43,0xff,0x94,
0x24,0x02,0x00,0x01,0x08,0x00,0x29,0x23,0x00,0x00,0x00,0x00,0x3c,0x02,0xb0,0x03,
0x3c,0x03,0x80,0x01,0x34,0x42,0x00,0x20,0x24,0x63,0xa5,0xcc,0xac,0x43,0x00,0x00,
0x8c,0x83,0x01,0xa8,0x8c,0x82,0x01,0xac,0x00,0x80,0x40,0x21,0x10,0x62,0x00,0x20,
0x00,0x00,0x20,0x21,0x93,0x82,0x81,0xf1,0x00,0x03,0x28,0x80,0x3c,0x07,0xb0,0x06,
0x00,0xa8,0x18,0x21,0x24,0x04,0x00,0x01,0x8c,0x66,0x00,0xa8,0x10,0x44,0x00,0x1c,
0x34,0xe7,0x80,0x18,0x3c,0x05,0xb0,0x01,0xaf,0x86,0xbc,0x20,0x00,0xc5,0x28,0x21,
0x8c,0xa3,0x00,0x00,0x00,0x06,0x20,0xc2,0x3c,0x02,0x00,0x80,0x00,0x04,0x22,0x00,
0x00,0x82,0x20,0x25,0xaf,0x83,0xbc,0x28,0x8c,0xa2,0x00,0x04,0xac,0xe4,0x00,0x00,
0x8d,0x03,0x01,0xa8,0xaf,0x82,0xbc,0x24,0x24,0x64,0x00,0x01,0x04,0x80,0x00,0x0a,
0x00,0x80,0x10,0x21,0x00,0x02,0x11,0x83,0x8d,0x03,0x01,0xac,0x00,0x02,0x11,0x80,
0x00,0x82,0x10,0x23,0x00,0x43,0x18,0x26,0xad,0x02,0x01,0xa8,0x00,0x03,0x20,0x2b,
0x03,0xe0,0x00,0x08,0x00,0x80,0x10,0x21,0x08,0x00,0x29,0x95,0x24,0x62,0x00,0x40,
0x27,0x82,0x89,0x68,0x00,0x06,0x20,0xc2,0x00,0x04,0x22,0x00,0x00,0xa2,0x48,0x21,
0x3c,0x02,0x00,0x80,0x00,0x82,0x58,0x25,0x93,0x82,0x81,0xf0,0x3c,0x0a,0xb0,0x06,
0x3c,0x03,0xb0,0x01,0x2c,0x42,0x00,0x02,0x00,0xc3,0x38,0x21,0x35,0x4a,0x80,0x18,
0x14,0x40,0xff,0xef,0x00,0x00,0x20,0x21,0x8c,0xe5,0x00,0x00,0x8d,0x23,0x00,0x00,
0x24,0x02,0xc0,0x00,0x00,0xa2,0x10,0x24,0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x00,
0x8d,0x04,0x01,0xa8,0x27,0x83,0x8a,0x68,0x8c,0xe5,0x00,0x04,0x00,0x04,0x20,0x80,
0x00,0x83,0x20,0x21,0x8c,0x82,0x00,0x00,0x3c,0x03,0x80,0x00,0x00,0xa2,0x10,0x25,
0x00,0x43,0x10,0x25,0xac,0xe2,0x00,0x04,0xaf,0x86,0xbc,0x20,0x8c,0xe2,0x00,0x00,
0x93,0x85,0x81,0xf0,0xaf,0x82,0xbc,0x28,0x8c,0xe3,0x00,0x04,0xad,0x4b,0x00,0x00,
0x8d,0x02,0x01,0xa8,0xaf,0x83,0xbc,0x24,0x24,0xa5,0xff,0xff,0x24,0x44,0x00,0x01,
0x28,0x83,0x00,0x00,0x24,0x42,0x00,0x40,0x00,0x83,0x10,0x0a,0x00,0x02,0x11,0x83,
0x00,0x02,0x11,0x80,0x00,0x82,0x20,0x23,0xad,0x04,0x01,0xa8,0xa3,0x85,0x81,0xf0,
0x79,0x02,0x0d,0x7c,0x00,0x00,0x00,0x00,0x00,0x43,0x10,0x26,0x08,0x00,0x29,0x9c,
0x00,0x02,0x20,0x2b,0x3c,0x04,0xb0,0x03,0x3c,0x06,0xb0,0x07,0x3c,0x02,0x80,0x01,
0x34,0xc6,0x00,0x18,0x34,0x84,0x00,0x20,0x24,0x42,0xa7,0x54,0x24,0x03,0xff,0x83,
0xac,0x82,0x00,0x00,0xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8,
0x3c,0x03,0xb0,0x07,0x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00,
0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01,
0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07,
0xa3,0xa3,0x00,0x00,0xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10,
0x24,0x02,0x00,0x06,0x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38,
0xa0,0xa2,0x00,0x00,0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20,
0xa3,0xa4,0x00,0x00,0xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xbf,0x30,
0xa3,0xa3,0x00,0x00,0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08,
0x27,0xbd,0x00,0x08,};
u8 Rtl8192PciEFwDataArray[DataArrayLengthPciE] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x00,0x08,0x00,
0x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4,0x00,0xab,0x00,0x72,
0x00,0x55,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x00,0x4c,0x02,0x76,0x01,0x3b,
0x00,0xd2,0x00,0x9e,0x00,0x69,0x00,0x4f,0x00,0x46,0x00,0x3f,0x01,0x3b,0x00,0x9e,
0x00,0x69,0x00,0x4f,0x00,0x35,0x00,0x27,0x00,0x23,0x00,0x20,0x01,0x2f,0x00,0x98,
0x00,0x65,0x00,0x4c,0x00,0x33,0x00,0x26,0x00,0x22,0x00,0x1e,0x00,0x98,0x00,0x4c,
0x00,0x33,0x00,0x26,0x00,0x19,0x00,0x13,0x00,0x11,0x00,0x0f,0x02,0x39,0x01,0x1c,
0x00,0xbd,0x00,0x8e,0x00,0x5f,0x00,0x47,0x00,0x3f,0x00,0x39,0x01,0x1c,0x00,0x8e,
0x00,0x5f,0x00,0x47,0x00,0x2f,0x00,0x23,0x00,0x20,0x00,0x1c,0x01,0x11,0x00,0x89,
0x00,0x5b,0x00,0x44,0x00,0x2e,0x00,0x22,0x00,0x1e,0x00,0x1b,0x00,0x89,0x00,0x44,
0x00,0x2e,0x00,0x22,0x00,0x17,0x00,0x11,0x00,0x0f,0x00,0x0e,0x02,0xab,0x02,0xab,
0x02,0x66,0x02,0x66,0x07,0x06,0x06,0x06,0x05,0x06,0x07,0x08,0x04,0x06,0x07,0x08,
0x09,0x0a,0x0b,0x0b,0x49,0x6e,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x4c,
0x42,0x4d,0x4f,0x44,0x00,0x00,0x00,0x00,0x54,0x4c,0x42,0x4c,0x5f,0x64,0x61,0x74,
0x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x64,0x45,0x4c,
0x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00,0x00,0x00,0x00,0x00,
0x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64,
0x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x70,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4f,0x76,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x0b,0x63,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x2c,
0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,0x60,
0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20,0x00,0x00,0x01,0x80,
0x00,0x00,0x01,0xb0,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x9c,
0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,0x00,0x00,0x01,0xa0,0x00,0x00,0x01,0xd4,
0x00,0x00,0x02,0x08,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,
0x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x6f,0x00,0x00,0x03,0x40,0x00,0x00,0x03,0xa8,
0x00,0x00,0x04,0x10,0x01,0x01,0x01,0x02,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,
0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x07,0x6c,0x80,0x00,0x07,0x80,
0x80,0x00,0x07,0x80,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x70,0x80,0x00,0x07,0x94,
0x80,0x00,0x56,0xb0,0x80,0x00,0x57,0x08,0x80,0x00,0x57,0x30,0x80,0x00,0x58,0x28,
0x80,0x00,0x58,0xe0,0x80,0x00,0x59,0x88,0x80,0x00,0x59,0xfc,0x80,0x00,0x5b,0x08,
0x80,0x00,0x5b,0x40,0x80,0x00,0x5b,0x54,0x80,0x00,0x5b,0x68,0x80,0x00,0x5c,0x50,
0x80,0x00,0x5c,0x90,0x80,0x00,0x5d,0x44,0x80,0x00,0x5d,0x6c,0x80,0x00,0x56,0x70,
0x80,0x00,0x5d,0xbc,0x80,0x00,0x64,0x48,0x80,0x00,0x64,0xc0,0x80,0x00,0x64,0xcc,
0x80,0x00,0x64,0xd8,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,
0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,
0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,0x80,0x00,0x64,0x60,
0x80,0x00,0x64,0x60,0x80,0x00,0x64,0xe4,0x80,0x00,0x64,0xf0,0x80,0x00,0x64,0xfc,
0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xa4,0x80,0x00,0x87,0xd8,
0x80,0x00,0x88,0x18,0x80,0x00,0x88,0x50,0x80,0x00,0x88,0x80,0x80,0x00,0x88,0xb0,
0x80,0x00,0x88,0xc4,0x80,0x00,0x89,0x2c,0x80,0x00,0x89,0x40,0x80,0x00,0x89,0x7c,
0x80,0x00,0x89,0x84,0x80,0x00,0x89,0xc0,0x80,0x00,0x89,0xd4,0x80,0x00,0x89,0xdc,
0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,0x80,0x00,0x89,0xe4,
0x80,0x00,0x8a,0x14,0x80,0x00,0x8a,0x28,0x80,0x00,0x8a,0x3c,0x80,0x00,0x86,0xe8,
0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x68,0x80,0x00,0x8d,0x9c,
0x80,0x00,0x8d,0xdc,0x80,0x00,0x8e,0x14,0x80,0x00,0x8e,0x44,0x80,0x00,0x8e,0x74,
0x80,0x00,0x8e,0x88,0x80,0x00,0x8e,0xf0,0x80,0x00,0x8f,0x04,0x80,0x00,0x8f,0x40,
0x80,0x00,0x8f,0x48,0x80,0x00,0x8f,0x84,0x80,0x00,0x8f,0x98,0x80,0x00,0x8f,0xa0,
0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,0x80,0x00,0x8f,0xa8,
0x80,0x00,0x8f,0xd8,0x80,0x00,0x8f,0xec,0x80,0x00,0x90,0x00,0x80,0x00,0x8b,0x88,
};
u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE] = {0x0,};
u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] = {
0x800, 0x00000000,
0x804, 0x00000001,
0x808, 0x0000fc00,
0x80c, 0x0000001c,
0x810, 0x801010aa,
0x814, 0x008514d0,
0x818, 0x00000040,
0x81c, 0x00000000,
0x820, 0x00000004,
0x824, 0x00690000,
0x828, 0x00000004,
0x82c, 0x00e90000,
0x830, 0x00000004,
0x834, 0x00690000,
0x838, 0x00000004,
0x83c, 0x00e90000,
0x840, 0x00000000,
0x844, 0x00000000,
0x848, 0x00000000,
0x84c, 0x00000000,
0x850, 0x00000000,
0x854, 0x00000000,
0x858, 0x65a965a9,
0x85c, 0x65a965a9,
0x860, 0x001f0010,
0x864, 0x007f0010,
0x868, 0x001f0010,
0x86c, 0x007f0010,
0x870, 0x0f100f70,
0x874, 0x0f100f70,
0x878, 0x00000000,
0x87c, 0x00000000,
0x880, 0x6870e36c,
0x884, 0xe3573600,
0x888, 0x4260c340,
0x88c, 0x0000ff00,
0x890, 0x00000000,
0x894, 0xfffffffe,
0x898, 0x4c42382f,
0x89c, 0x00656056,
0x8b0, 0x00000000,
0x8e0, 0x00000000,
0x8e4, 0x00000000,
0x900, 0x00000000,
0x904, 0x00000023,
0x908, 0x00000000,
0x90c, 0x31121311,
0xa00, 0x00d0c7d8,
0xa04, 0x811f0008,
0xa08, 0x80cd8300,
0xa0c, 0x2e62740f,
0xa10, 0x95009b78,
0xa14, 0x11145008,
0xa18, 0x00881117,
0xa1c, 0x89140fa0,
0xa20, 0x1a1b0000,
0xa24, 0x090e1317,
0xa28, 0x00000204,
0xa2c, 0x00000000,
0xc00, 0x00000040,
0xc04, 0x00005433,
0xc08, 0x000000e4,
0xc0c, 0x6c6c6c6c,
0xc10, 0x08800000,
0xc14, 0x40000100,
0xc18, 0x08000000,
0xc1c, 0x40000100,
0xc20, 0x08000000,
0xc24, 0x40000100,
0xc28, 0x08000000,
0xc2c, 0x40000100,
0xc30, 0x6de9ac44,
0xc34, 0x465c52cd,
0xc38, 0x497f5994,
0xc3c, 0x0a969764,
0xc40, 0x1f7c403f,
0xc44, 0x000100b7,
0xc48, 0xec020000,
0xc4c, 0x00000300,
0xc50, 0x69543420,
0xc54, 0x433c0094,
0xc58, 0x69543420,
0xc5c, 0x433c0094,
0xc60, 0x69543420,
0xc64, 0x433c0094,
0xc68, 0x69543420,
0xc6c, 0x433c0094,
0xc70, 0x2c7f000d,
0xc74, 0x0186175b,
0xc78, 0x0000001f,
0xc7c, 0x00b91612,
0xc80, 0x40000100,
0xc84, 0x20000000,
0xc88, 0x40000100,
0xc8c, 0x20200000,
0xc90, 0x40000100,
0xc94, 0x00000000,
0xc98, 0x40000100,
0xc9c, 0x00000000,
0xca0, 0x00492492,
0xca4, 0x00000000,
0xca8, 0x00000000,
0xcac, 0x00000000,
0xcb0, 0x00000000,
0xcb4, 0x00000000,
0xcb8, 0x00000000,
0xcbc, 0x00492492,
0xcc0, 0x00000000,
0xcc4, 0x00000000,
0xcc8, 0x00000000,
0xccc, 0x00000000,
0xcd0, 0x00000000,
0xcd4, 0x00000000,
0xcd8, 0x64b22427,
0xcdc, 0x00766932,
0xce0, 0x00222222,
0xd00, 0x00000750,
0xd04, 0x00000403,
0xd08, 0x0000907f,
0xd0c, 0x00000001,
0xd10, 0xa0633333,
0xd14, 0x33333c63,
0xd18, 0x6a8f5b6b,
0xd1c, 0x00000000,
0xd20, 0x00000000,
0xd24, 0x00000000,
0xd28, 0x00000000,
0xd2c, 0xcc979975,
0xd30, 0x00000000,
0xd34, 0x00000000,
0xd38, 0x00000000,
0xd3c, 0x00027293,
0xd40, 0x00000000,
0xd44, 0x00000000,
0xd48, 0x00000000,
0xd4c, 0x00000000,
0xd50, 0x6437140a,
0xd54, 0x024dbd02,
0xd58, 0x00000000,
0xd5c, 0x04032064,
0xe00, 0x161a1a1a,
0xe04, 0x12121416,
0xe08, 0x00001800,
0xe0c, 0x00000000,
0xe10, 0x161a1a1a,
0xe14, 0x12121416,
0xe18, 0x161a1a1a,
0xe1c, 0x12121416,
};
u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] = {
0x019, 0x00000003,
0x000, 0x000000bf,
0x001, 0x00000ee0,
0x002, 0x0000004c,
0x003, 0x000007f1,
0x004, 0x00000975,
0x005, 0x00000c58,
0x006, 0x00000ae6,
0x007, 0x000000ca,
0x008, 0x00000e1c,
0x009, 0x000007f0,
0x00a, 0x000009d0,
0x00b, 0x000001ba,
0x00c, 0x00000240,
0x00e, 0x00000020,
0x00f, 0x00000990,
0x012, 0x00000806,
0x014, 0x000005ab,
0x015, 0x00000f80,
0x016, 0x00000020,
0x017, 0x00000597,
0x018, 0x0000050a,
0x01a, 0x00000f80,
0x01b, 0x00000f5e,
0x01c, 0x00000008,
0x01d, 0x00000607,
0x01e, 0x000006cc,
0x01f, 0x00000000,
0x020, 0x000001a5,
0x01f, 0x00000001,
0x020, 0x00000165,
0x01f, 0x00000002,
0x020, 0x000000c6,
0x01f, 0x00000003,
0x020, 0x00000086,
0x01f, 0x00000004,
0x020, 0x00000046,
0x01f, 0x00000005,
0x020, 0x000001e6,
0x01f, 0x00000006,
0x020, 0x000001a6,
0x01f, 0x00000007,
0x020, 0x00000166,
0x01f, 0x00000008,
0x020, 0x000000c7,
0x01f, 0x00000009,
0x020, 0x00000087,
0x01f, 0x0000000a,
0x020, 0x000000f7,
0x01f, 0x0000000b,
0x020, 0x000000d7,
0x01f, 0x0000000c,
0x020, 0x000000b7,
0x01f, 0x0000000d,
0x020, 0x00000097,
0x01f, 0x0000000e,
0x020, 0x00000077,
0x01f, 0x0000000f,
0x020, 0x00000057,
0x01f, 0x00000010,
0x020, 0x00000037,
0x01f, 0x00000011,
0x020, 0x000000fb,
0x01f, 0x00000012,
0x020, 0x000000db,
0x01f, 0x00000013,
0x020, 0x000000bb,
0x01f, 0x00000014,
0x020, 0x000000ff,
0x01f, 0x00000015,
0x020, 0x000000e3,
0x01f, 0x00000016,
0x020, 0x000000c3,
0x01f, 0x00000017,
0x020, 0x000000a3,
0x01f, 0x00000018,
0x020, 0x00000083,
0x01f, 0x00000019,
0x020, 0x00000063,
0x01f, 0x0000001a,
0x020, 0x00000043,
0x01f, 0x0000001b,
0x020, 0x00000023,
0x01f, 0x0000001c,
0x020, 0x00000003,
0x01f, 0x0000001d,
0x020, 0x000001e3,
0x01f, 0x0000001e,
0x020, 0x000001c3,
0x01f, 0x0000001f,
0x020, 0x000001a3,
0x01f, 0x00000020,
0x020, 0x00000183,
0x01f, 0x00000021,
0x020, 0x00000163,
0x01f, 0x00000022,
0x020, 0x00000143,
0x01f, 0x00000023,
0x020, 0x00000123,
0x01f, 0x00000024,
0x020, 0x00000103,
0x023, 0x00000203,
0x024, 0x00000100,
0x00b, 0x000001ba,
0x02c, 0x000003d7,
0x02d, 0x00000ff0,
0x000, 0x00000037,
0x004, 0x00000160,
0x007, 0x00000080,
0x002, 0x0000088d,
0x0fe, 0x00000000,
0x0fe, 0x00000000,
0x016, 0x00000200,
0x016, 0x00000380,
0x016, 0x00000020,
0x016, 0x000001a0,
0x000, 0x000000bf,
0x00d, 0x0000001f,
0x00d, 0x00000c9f,
0x002, 0x0000004d,
0x000, 0x00000cbf,
0x004, 0x00000975,
0x007, 0x00000700,
};
u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] = {
0x019, 0x00000003,
0x000, 0x000000bf,
0x001, 0x000006e0,
0x002, 0x0000004c,
0x003, 0x000007f1,
0x004, 0x00000975,
0x005, 0x00000c58,
0x006, 0x00000ae6,
0x007, 0x000000ca,
0x008, 0x00000e1c,
0x000, 0x000000b7,
0x00a, 0x00000850,
0x000, 0x000000bf,
0x00b, 0x000001ba,
0x00c, 0x00000240,
0x00e, 0x00000020,
0x015, 0x00000f80,
0x016, 0x00000020,
0x017, 0x00000597,
0x018, 0x0000050a,
0x01a, 0x00000e00,
0x01b, 0x00000f5e,
0x01d, 0x00000607,
0x01e, 0x000006cc,
0x00b, 0x000001ba,
0x023, 0x00000203,
0x024, 0x00000100,
0x000, 0x00000037,
0x004, 0x00000160,
0x016, 0x00000200,
0x016, 0x00000380,
0x016, 0x00000020,
0x016, 0x000001a0,
0x00d, 0x00000ccc,
0x000, 0x000000bf,
0x002, 0x0000004d,
0x000, 0x00000cbf,
0x004, 0x00000975,
0x007, 0x00000700,
};
u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] = {
0x0, };
u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] = {
0x0, };
u32 Rtl8192PciEMACPHY_Array[] = {
0x03c, 0xffff0000, 0x00000f0f,
0x340, 0xffffffff, 0x161a1a1a,
0x344, 0xffffffff, 0x12121416,
0x348, 0x0000ffff, 0x00001818,
0x12c, 0xffffffff, 0x04000802,
0x318, 0x00000fff, 0x00000100,
};
u32 Rtl8192PciEMACPHY_Array_PG[] = {
0x03c, 0xffff0000, 0x00000f0f,
0xe00, 0xffffffff, 0x06090909,
0xe04, 0xffffffff, 0x00030306,
0xe08, 0x0000ff00, 0x00000000,
0xe10, 0xffffffff, 0x0a0c0d0f,
0xe14, 0xffffffff, 0x06070809,
0xe18, 0xffffffff, 0x0a0c0d0f,
0xe1c, 0xffffffff, 0x06070809,
0x12c, 0xffffffff, 0x04000802,
0x318, 0x00000fff, 0x00000800,
};
u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] = {
0xc78, 0x7d000001,
0xc78, 0x7d010001,
0xc78, 0x7d020001,
0xc78, 0x7d030001,
0xc78, 0x7d040001,
0xc78, 0x7d050001,
0xc78, 0x7c060001,
0xc78, 0x7b070001,
0xc78, 0x7a080001,
0xc78, 0x79090001,
0xc78, 0x780a0001,
0xc78, 0x770b0001,
0xc78, 0x760c0001,
0xc78, 0x750d0001,
0xc78, 0x740e0001,
0xc78, 0x730f0001,
0xc78, 0x72100001,
0xc78, 0x71110001,
0xc78, 0x70120001,
0xc78, 0x6f130001,
0xc78, 0x6e140001,
0xc78, 0x6d150001,
0xc78, 0x6c160001,
0xc78, 0x6b170001,
0xc78, 0x6a180001,
0xc78, 0x69190001,
0xc78, 0x681a0001,
0xc78, 0x671b0001,
0xc78, 0x661c0001,
0xc78, 0x651d0001,
0xc78, 0x641e0001,
0xc78, 0x491f0001,
0xc78, 0x48200001,
0xc78, 0x47210001,
0xc78, 0x46220001,
0xc78, 0x45230001,
0xc78, 0x44240001,
0xc78, 0x43250001,
0xc78, 0x28260001,
0xc78, 0x27270001,
0xc78, 0x26280001,
0xc78, 0x25290001,
0xc78, 0x242a0001,
0xc78, 0x232b0001,
0xc78, 0x222c0001,
0xc78, 0x212d0001,
0xc78, 0x202e0001,
0xc78, 0x0a2f0001,
0xc78, 0x08300001,
0xc78, 0x06310001,
0xc78, 0x05320001,
0xc78, 0x04330001,
0xc78, 0x03340001,
0xc78, 0x02350001,
0xc78, 0x01360001,
0xc78, 0x00370001,
0xc78, 0x00380001,
0xc78, 0x00390001,
0xc78, 0x003a0001,
0xc78, 0x003b0001,
0xc78, 0x003c0001,
0xc78, 0x003d0001,
0xc78, 0x003e0001,
0xc78, 0x003f0001,
0xc78, 0x7d400001,
0xc78, 0x7d410001,
0xc78, 0x7d420001,
0xc78, 0x7d430001,
0xc78, 0x7d440001,
0xc78, 0x7d450001,
0xc78, 0x7c460001,
0xc78, 0x7b470001,
0xc78, 0x7a480001,
0xc78, 0x79490001,
0xc78, 0x784a0001,
0xc78, 0x774b0001,
0xc78, 0x764c0001,
0xc78, 0x754d0001,
0xc78, 0x744e0001,
0xc78, 0x734f0001,
0xc78, 0x72500001,
0xc78, 0x71510001,
0xc78, 0x70520001,
0xc78, 0x6f530001,
0xc78, 0x6e540001,
0xc78, 0x6d550001,
0xc78, 0x6c560001,
0xc78, 0x6b570001,
0xc78, 0x6a580001,
0xc78, 0x69590001,
0xc78, 0x685a0001,
0xc78, 0x675b0001,
0xc78, 0x665c0001,
0xc78, 0x655d0001,
0xc78, 0x645e0001,
0xc78, 0x495f0001,
0xc78, 0x48600001,
0xc78, 0x47610001,
0xc78, 0x46620001,
0xc78, 0x45630001,
0xc78, 0x44640001,
0xc78, 0x43650001,
0xc78, 0x28660001,
0xc78, 0x27670001,
0xc78, 0x26680001,
0xc78, 0x25690001,
0xc78, 0x246a0001,
0xc78, 0x236b0001,
0xc78, 0x226c0001,
0xc78, 0x216d0001,
0xc78, 0x206e0001,
0xc78, 0x0a6f0001,
0xc78, 0x08700001,
0xc78, 0x06710001,
0xc78, 0x05720001,
0xc78, 0x04730001,
0xc78, 0x03740001,
0xc78, 0x02750001,
0xc78, 0x01760001,
0xc78, 0x00770001,
0xc78, 0x00780001,
0xc78, 0x00790001,
0xc78, 0x007a0001,
0xc78, 0x007b0001,
0xc78, 0x007c0001,
0xc78, 0x007d0001,
0xc78, 0x007e0001,
0xc78, 0x007f0001,
0xc78, 0x2e00001e,
0xc78, 0x2e01001e,
0xc78, 0x2e02001e,
0xc78, 0x2e03001e,
0xc78, 0x2e04001e,
0xc78, 0x2e05001e,
0xc78, 0x3006001e,
0xc78, 0x3407001e,
0xc78, 0x3908001e,
0xc78, 0x3c09001e,
0xc78, 0x3f0a001e,
0xc78, 0x420b001e,
0xc78, 0x440c001e,
0xc78, 0x450d001e,
0xc78, 0x460e001e,
0xc78, 0x460f001e,
0xc78, 0x4710001e,
0xc78, 0x4811001e,
0xc78, 0x4912001e,
0xc78, 0x4a13001e,
0xc78, 0x4b14001e,
0xc78, 0x4b15001e,
0xc78, 0x4c16001e,
0xc78, 0x4d17001e,
0xc78, 0x4e18001e,
0xc78, 0x4f19001e,
0xc78, 0x4f1a001e,
0xc78, 0x501b001e,
0xc78, 0x511c001e,
0xc78, 0x521d001e,
0xc78, 0x521e001e,
0xc78, 0x531f001e,
0xc78, 0x5320001e,
0xc78, 0x5421001e,
0xc78, 0x5522001e,
0xc78, 0x5523001e,
0xc78, 0x5624001e,
0xc78, 0x5725001e,
0xc78, 0x5726001e,
0xc78, 0x5827001e,
0xc78, 0x5828001e,
0xc78, 0x5929001e,
0xc78, 0x592a001e,
0xc78, 0x5a2b001e,
0xc78, 0x5b2c001e,
0xc78, 0x5c2d001e,
0xc78, 0x5c2e001e,
0xc78, 0x5d2f001e,
0xc78, 0x5e30001e,
0xc78, 0x5f31001e,
0xc78, 0x6032001e,
0xc78, 0x6033001e,
0xc78, 0x6134001e,
0xc78, 0x6235001e,
0xc78, 0x6336001e,
0xc78, 0x6437001e,
0xc78, 0x6438001e,
0xc78, 0x6539001e,
0xc78, 0x663a001e,
0xc78, 0x673b001e,
0xc78, 0x673c001e,
0xc78, 0x683d001e,
0xc78, 0x693e001e,
0xc78, 0x6a3f001e,
};
| gpl-2.0 |
kevin78/linux-kevin | drivers/net/ethernet/ibm/emac/phy.c | 9300 | 12820 | /*
* drivers/net/ethernet/ibm/emac/phy.c
*
* Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
* Borrowed from sungem_phy.c, though I only kept the generic MII
* driver for now.
*
* This file should be shared with other drivers or eventually
* merged as the "low level" part of miilib
*
* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
* <benh@kernel.crashing.org>
*
* Based on the arch/ppc version of the driver:
*
* (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
* (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
#include "emac.h"
#include "phy.h"
#define phy_read _phy_read
#define phy_write _phy_write
static inline int _phy_read(struct mii_phy *phy, int reg)
{
return phy->mdio_read(phy->dev, phy->address, reg);
}
static inline void _phy_write(struct mii_phy *phy, int reg, int val)
{
phy->mdio_write(phy->dev, phy->address, reg, val);
}
static inline int gpcs_phy_read(struct mii_phy *phy, int reg)
{
return phy->mdio_read(phy->dev, phy->gpcs_address, reg);
}
static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val)
{
phy->mdio_write(phy->dev, phy->gpcs_address, reg, val);
}
int emac_mii_reset_phy(struct mii_phy *phy)
{
int val;
int limit = 10000;
val = phy_read(phy, MII_BMCR);
val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
val |= BMCR_RESET;
phy_write(phy, MII_BMCR, val);
udelay(300);
while (--limit) {
val = phy_read(phy, MII_BMCR);
if (val >= 0 && (val & BMCR_RESET) == 0)
break;
udelay(10);
}
if ((val & BMCR_ISOLATE) && limit > 0)
phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
return limit <= 0;
}
int emac_mii_reset_gpcs(struct mii_phy *phy)
{
int val;
int limit = 10000;
val = gpcs_phy_read(phy, MII_BMCR);
val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
val |= BMCR_RESET;
gpcs_phy_write(phy, MII_BMCR, val);
udelay(300);
while (--limit) {
val = gpcs_phy_read(phy, MII_BMCR);
if (val >= 0 && (val & BMCR_RESET) == 0)
break;
udelay(10);
}
if ((val & BMCR_ISOLATE) && limit > 0)
gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
if (limit > 0 && phy->mode == PHY_MODE_SGMII) {
/* Configure GPCS interface to recommended setting for SGMII */
gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */
gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */
gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */
}
return limit <= 0;
}
static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
{
int ctl, adv;
phy->autoneg = AUTONEG_ENABLE;
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = phy->asym_pause = 0;
phy->advertising = advertise;
ctl = phy_read(phy, MII_BMCR);
if (ctl < 0)
return ctl;
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
/* First clear the PHY */
phy_write(phy, MII_BMCR, ctl);
/* Setup standard advertise */
adv = phy_read(phy, MII_ADVERTISE);
if (adv < 0)
return adv;
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
ADVERTISE_PAUSE_ASYM);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
if (advertise & ADVERTISED_Pause)
adv |= ADVERTISE_PAUSE_CAP;
if (advertise & ADVERTISED_Asym_Pause)
adv |= ADVERTISE_PAUSE_ASYM;
phy_write(phy, MII_ADVERTISE, adv);
if (phy->features &
(SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
adv = phy_read(phy, MII_CTRL1000);
if (adv < 0)
return adv;
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
if (advertise & ADVERTISED_1000baseT_Full)
adv |= ADVERTISE_1000FULL;
if (advertise & ADVERTISED_1000baseT_Half)
adv |= ADVERTISE_1000HALF;
phy_write(phy, MII_CTRL1000, adv);
}
/* Start/Restart aneg */
ctl = phy_read(phy, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
{
int ctl;
phy->autoneg = AUTONEG_DISABLE;
phy->speed = speed;
phy->duplex = fd;
phy->pause = phy->asym_pause = 0;
ctl = phy_read(phy, MII_BMCR);
if (ctl < 0)
return ctl;
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
/* First clear the PHY */
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
/* Select speed & duplex */
switch (speed) {
case SPEED_10:
break;
case SPEED_100:
ctl |= BMCR_SPEED100;
break;
case SPEED_1000:
ctl |= BMCR_SPEED1000;
break;
default:
return -EINVAL;
}
if (fd == DUPLEX_FULL)
ctl |= BMCR_FULLDPLX;
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int genmii_poll_link(struct mii_phy *phy)
{
int status;
/* Clear latched value with dummy read */
phy_read(phy, MII_BMSR);
status = phy_read(phy, MII_BMSR);
if (status < 0 || (status & BMSR_LSTATUS) == 0)
return 0;
if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
return 0;
return 1;
}
static int genmii_read_link(struct mii_phy *phy)
{
if (phy->autoneg == AUTONEG_ENABLE) {
int glpa = 0;
int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
if (lpa < 0)
return lpa;
if (phy->features &
(SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
int adv = phy_read(phy, MII_CTRL1000);
glpa = phy_read(phy, MII_STAT1000);
if (glpa < 0 || adv < 0)
return adv;
glpa &= adv << 2;
}
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = phy->asym_pause = 0;
if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
phy->speed = SPEED_1000;
if (glpa & LPA_1000FULL)
phy->duplex = DUPLEX_FULL;
} else if (lpa & (LPA_100FULL | LPA_100HALF)) {
phy->speed = SPEED_100;
if (lpa & LPA_100FULL)
phy->duplex = DUPLEX_FULL;
} else if (lpa & LPA_10FULL)
phy->duplex = DUPLEX_FULL;
if (phy->duplex == DUPLEX_FULL) {
phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
}
} else {
int bmcr = phy_read(phy, MII_BMCR);
if (bmcr < 0)
return bmcr;
if (bmcr & BMCR_FULLDPLX)
phy->duplex = DUPLEX_FULL;
else
phy->duplex = DUPLEX_HALF;
if (bmcr & BMCR_SPEED1000)
phy->speed = SPEED_1000;
else if (bmcr & BMCR_SPEED100)
phy->speed = SPEED_100;
else
phy->speed = SPEED_10;
phy->pause = phy->asym_pause = 0;
}
return 0;
}
/* Generic implementation for most 10/100/1000 PHYs */
static struct mii_phy_ops generic_phy_ops = {
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link
};
static struct mii_phy_def genmii_phy_def = {
.phy_id = 0x00000000,
.phy_id_mask = 0x00000000,
.name = "Generic MII",
.ops = &generic_phy_ops
};
/* CIS8201 */
#define MII_CIS8201_10BTCSR 0x16
#define TENBTCSR_ECHO_DISABLE 0x2000
#define MII_CIS8201_EPCR 0x17
#define EPCR_MODE_MASK 0x3000
#define EPCR_GMII_MODE 0x0000
#define EPCR_RGMII_MODE 0x1000
#define EPCR_TBI_MODE 0x2000
#define EPCR_RTBI_MODE 0x3000
#define MII_CIS8201_ACSR 0x1c
#define ACSR_PIN_PRIO_SELECT 0x0004
static int cis8201_init(struct mii_phy *phy)
{
int epcr;
epcr = phy_read(phy, MII_CIS8201_EPCR);
if (epcr < 0)
return epcr;
epcr &= ~EPCR_MODE_MASK;
switch (phy->mode) {
case PHY_MODE_TBI:
epcr |= EPCR_TBI_MODE;
break;
case PHY_MODE_RTBI:
epcr |= EPCR_RTBI_MODE;
break;
case PHY_MODE_GMII:
epcr |= EPCR_GMII_MODE;
break;
case PHY_MODE_RGMII:
default:
epcr |= EPCR_RGMII_MODE;
}
phy_write(phy, MII_CIS8201_EPCR, epcr);
/* MII regs override strap pins */
phy_write(phy, MII_CIS8201_ACSR,
phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
/* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
phy_write(phy, MII_CIS8201_10BTCSR,
phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
return 0;
}
static struct mii_phy_ops cis8201_phy_ops = {
.init = cis8201_init,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link
};
static struct mii_phy_def cis8201_phy_def = {
.phy_id = 0x000fc410,
.phy_id_mask = 0x000ffff0,
.name = "CIS8201 Gigabit Ethernet",
.ops = &cis8201_phy_ops
};
static struct mii_phy_def bcm5248_phy_def = {
.phy_id = 0x0143bc00,
.phy_id_mask = 0x0ffffff0,
.name = "BCM5248 10/100 SMII Ethernet",
.ops = &generic_phy_ops
};
static int m88e1111_init(struct mii_phy *phy)
{
pr_debug("%s: Marvell 88E1111 Ethernet\n", __func__);
phy_write(phy, 0x14, 0x0ce3);
phy_write(phy, 0x18, 0x4101);
phy_write(phy, 0x09, 0x0e00);
phy_write(phy, 0x04, 0x01e1);
phy_write(phy, 0x00, 0x9140);
phy_write(phy, 0x00, 0x1140);
return 0;
}
static int m88e1112_init(struct mii_phy *phy)
{
/*
* Marvell 88E1112 PHY needs to have the SGMII MAC
* interace (page 2) properly configured to
* communicate with the 460EX/GT GPCS interface.
*/
u16 reg_short;
pr_debug("%s: Marvell 88E1112 Ethernet\n", __func__);
/* Set access to Page 2 */
phy_write(phy, 0x16, 0x0002);
phy_write(phy, 0x00, 0x0040); /* 1Gbps */
reg_short = (u16)(phy_read(phy, 0x1a));
reg_short |= 0x8000; /* bypass Auto-Negotiation */
phy_write(phy, 0x1a, reg_short);
emac_mii_reset_phy(phy); /* reset MAC interface */
/* Reset access to Page 0 */
phy_write(phy, 0x16, 0x0000);
return 0;
}
static int et1011c_init(struct mii_phy *phy)
{
u16 reg_short;
reg_short = (u16)(phy_read(phy, 0x16));
reg_short &= ~(0x7);
reg_short |= 0x6; /* RGMII Trace Delay*/
phy_write(phy, 0x16, reg_short);
reg_short = (u16)(phy_read(phy, 0x17));
reg_short &= ~(0x40);
phy_write(phy, 0x17, reg_short);
phy_write(phy, 0x1c, 0x74f0);
return 0;
}
static struct mii_phy_ops et1011c_phy_ops = {
.init = et1011c_init,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link
};
static struct mii_phy_def et1011c_phy_def = {
.phy_id = 0x0282f000,
.phy_id_mask = 0x0fffff00,
.name = "ET1011C Gigabit Ethernet",
.ops = &et1011c_phy_ops
};
static struct mii_phy_ops m88e1111_phy_ops = {
.init = m88e1111_init,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link
};
static struct mii_phy_def m88e1111_phy_def = {
.phy_id = 0x01410CC0,
.phy_id_mask = 0x0ffffff0,
.name = "Marvell 88E1111 Ethernet",
.ops = &m88e1111_phy_ops,
};
static struct mii_phy_ops m88e1112_phy_ops = {
.init = m88e1112_init,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link
};
static struct mii_phy_def m88e1112_phy_def = {
.phy_id = 0x01410C90,
.phy_id_mask = 0x0ffffff0,
.name = "Marvell 88E1112 Ethernet",
.ops = &m88e1112_phy_ops,
};
static struct mii_phy_def *mii_phy_table[] = {
&et1011c_phy_def,
&cis8201_phy_def,
&bcm5248_phy_def,
&m88e1111_phy_def,
&m88e1112_phy_def,
&genmii_phy_def,
NULL
};
int emac_mii_phy_probe(struct mii_phy *phy, int address)
{
struct mii_phy_def *def;
int i;
u32 id;
phy->autoneg = AUTONEG_DISABLE;
phy->advertising = 0;
phy->address = address;
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = phy->asym_pause = 0;
/* Take PHY out of isolate mode and reset it. */
if (emac_mii_reset_phy(phy))
return -ENODEV;
/* Read ID and find matching entry */
id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
if ((id & def->phy_id_mask) == def->phy_id)
break;
/* Should never be NULL (we have a generic entry), but... */
if (!def)
return -ENODEV;
phy->def = def;
/* Determine PHY features if needed */
phy->features = def->features;
if (!phy->features) {
u16 bmsr = phy_read(phy, MII_BMSR);
if (bmsr & BMSR_ANEGCAPABLE)
phy->features |= SUPPORTED_Autoneg;
if (bmsr & BMSR_10HALF)
phy->features |= SUPPORTED_10baseT_Half;
if (bmsr & BMSR_10FULL)
phy->features |= SUPPORTED_10baseT_Full;
if (bmsr & BMSR_100HALF)
phy->features |= SUPPORTED_100baseT_Half;
if (bmsr & BMSR_100FULL)
phy->features |= SUPPORTED_100baseT_Full;
if (bmsr & BMSR_ESTATEN) {
u16 esr = phy_read(phy, MII_ESTATUS);
if (esr & ESTATUS_1000_TFULL)
phy->features |= SUPPORTED_1000baseT_Full;
if (esr & ESTATUS_1000_THALF)
phy->features |= SUPPORTED_1000baseT_Half;
}
phy->features |= SUPPORTED_MII;
}
/* Setup default advertising */
phy->advertising = phy->features;
return 0;
}
MODULE_LICENSE("GPL");
| gpl-2.0 |
Split-Screen/android_kernel_lge_hammerhead | drivers/isdn/hisax/hisax_isac.c | 9556 | 22142 | /*
* Driver for ISAC-S and ISAC-SX
* ISDN Subscriber Access Controller for Terminals
*
* Author Kai Germaschewski
* Copyright 2001 by Kai Germaschewski <kai.germaschewski@gmx.de>
* 2001 by Karsten Keil <keil@isdn4linux.de>
*
* based upon Karsten Keil's original isac.c driver
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
* Thanks to Wizard Computersysteme GmbH, Bremervoerde and
* SoHaNet Technology GmbH, Berlin
* for supporting the development of this driver
*/
/* TODO:
* specifically handle level vs edge triggered?
*/
#include <linux/module.h>
#include <linux/gfp.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include "hisax_isac.h"
// debugging cruft
#define __debug_variable debug
#include "hisax_debug.h"
#ifdef CONFIG_HISAX_DEBUG
static int debug = 1;
module_param(debug, int, 0);
static char *ISACVer[] = {
"2086/2186 V1.1",
"2085 B1",
"2085 B2",
"2085 V2.3"
};
#endif
MODULE_AUTHOR("Kai Germaschewski <kai.germaschewski@gmx.de>/Karsten Keil <kkeil@suse.de>");
MODULE_DESCRIPTION("ISAC/ISAC-SX driver");
MODULE_LICENSE("GPL");
#define DBG_WARN 0x0001
#define DBG_IRQ 0x0002
#define DBG_L1M 0x0004
#define DBG_PR 0x0008
#define DBG_RFIFO 0x0100
#define DBG_RPACKET 0x0200
#define DBG_XFIFO 0x1000
#define DBG_XPACKET 0x2000
// we need to distinguish ISAC-S and ISAC-SX
#define TYPE_ISAC 0x00
#define TYPE_ISACSX 0x01
// registers etc.
#define ISAC_MASK 0x20
#define ISAC_ISTA 0x20
#define ISAC_ISTA_EXI 0x01
#define ISAC_ISTA_SIN 0x02
#define ISAC_ISTA_CISQ 0x04
#define ISAC_ISTA_XPR 0x10
#define ISAC_ISTA_RSC 0x20
#define ISAC_ISTA_RPF 0x40
#define ISAC_ISTA_RME 0x80
#define ISAC_STAR 0x21
#define ISAC_CMDR 0x21
#define ISAC_CMDR_XRES 0x01
#define ISAC_CMDR_XME 0x02
#define ISAC_CMDR_XTF 0x08
#define ISAC_CMDR_RRES 0x40
#define ISAC_CMDR_RMC 0x80
#define ISAC_EXIR 0x24
#define ISAC_EXIR_MOS 0x04
#define ISAC_EXIR_XDU 0x40
#define ISAC_EXIR_XMR 0x80
#define ISAC_ADF2 0x39
#define ISAC_SPCR 0x30
#define ISAC_ADF1 0x38
#define ISAC_CIR0 0x31
#define ISAC_CIX0 0x31
#define ISAC_CIR0_CIC0 0x02
#define ISAC_CIR0_CIC1 0x01
#define ISAC_CIR1 0x33
#define ISAC_CIX1 0x33
#define ISAC_STCR 0x37
#define ISAC_MODE 0x22
#define ISAC_RSTA 0x27
#define ISAC_RSTA_RDO 0x40
#define ISAC_RSTA_CRC 0x20
#define ISAC_RSTA_RAB 0x10
#define ISAC_RBCL 0x25
#define ISAC_RBCH 0x2A
#define ISAC_TIMR 0x23
#define ISAC_SQXR 0x3b
#define ISAC_MOSR 0x3a
#define ISAC_MOCR 0x3a
#define ISAC_MOR0 0x32
#define ISAC_MOX0 0x32
#define ISAC_MOR1 0x34
#define ISAC_MOX1 0x34
#define ISAC_RBCH_XAC 0x80
#define ISAC_CMD_TIM 0x0
#define ISAC_CMD_RES 0x1
#define ISAC_CMD_SSP 0x2
#define ISAC_CMD_SCP 0x3
#define ISAC_CMD_AR8 0x8
#define ISAC_CMD_AR10 0x9
#define ISAC_CMD_ARL 0xa
#define ISAC_CMD_DI 0xf
#define ISACSX_MASK 0x60
#define ISACSX_ISTA 0x60
#define ISACSX_ISTA_ICD 0x01
#define ISACSX_ISTA_CIC 0x10
#define ISACSX_MASKD 0x20
#define ISACSX_ISTAD 0x20
#define ISACSX_ISTAD_XDU 0x04
#define ISACSX_ISTAD_XMR 0x08
#define ISACSX_ISTAD_XPR 0x10
#define ISACSX_ISTAD_RFO 0x20
#define ISACSX_ISTAD_RPF 0x40
#define ISACSX_ISTAD_RME 0x80
#define ISACSX_CMDRD 0x21
#define ISACSX_CMDRD_XRES 0x01
#define ISACSX_CMDRD_XME 0x02
#define ISACSX_CMDRD_XTF 0x08
#define ISACSX_CMDRD_RRES 0x40
#define ISACSX_CMDRD_RMC 0x80
#define ISACSX_MODED 0x22
#define ISACSX_RBCLD 0x26
#define ISACSX_RSTAD 0x28
#define ISACSX_RSTAD_RAB 0x10
#define ISACSX_RSTAD_CRC 0x20
#define ISACSX_RSTAD_RDO 0x40
#define ISACSX_RSTAD_VFR 0x80
#define ISACSX_CIR0 0x2e
#define ISACSX_CIR0_CIC0 0x08
#define ISACSX_CIX0 0x2e
#define ISACSX_TR_CONF0 0x30
#define ISACSX_TR_CONF2 0x32
static struct Fsm l1fsm;
enum {
ST_L1_RESET,
ST_L1_F3_PDOWN,
ST_L1_F3_PUP,
ST_L1_F3_PEND_DEACT,
ST_L1_F4,
ST_L1_F5,
ST_L1_F6,
ST_L1_F7,
ST_L1_F8,
};
#define L1_STATE_COUNT (ST_L1_F8 + 1)
static char *strL1State[] =
{
"ST_L1_RESET",
"ST_L1_F3_PDOWN",
"ST_L1_F3_PUP",
"ST_L1_F3_PEND_DEACT",
"ST_L1_F4",
"ST_L1_F5",
"ST_L1_F6",
"ST_L1_F7",
"ST_L1_F8",
};
enum {
EV_PH_DR, // 0000
EV_PH_RES, // 0001
EV_PH_TMA, // 0010
EV_PH_SLD, // 0011
EV_PH_RSY, // 0100
EV_PH_DR6, // 0101
EV_PH_EI, // 0110
EV_PH_PU, // 0111
EV_PH_AR, // 1000
EV_PH_9, // 1001
EV_PH_ARL, // 1010
EV_PH_CVR, // 1011
EV_PH_AI8, // 1100
EV_PH_AI10, // 1101
EV_PH_AIL, // 1110
EV_PH_DC, // 1111
EV_PH_ACTIVATE_REQ,
EV_PH_DEACTIVATE_REQ,
EV_TIMER3,
};
#define L1_EVENT_COUNT (EV_TIMER3 + 1)
static char *strL1Event[] =
{
"EV_PH_DR", // 0000
"EV_PH_RES", // 0001
"EV_PH_TMA", // 0010
"EV_PH_SLD", // 0011
"EV_PH_RSY", // 0100
"EV_PH_DR6", // 0101
"EV_PH_EI", // 0110
"EV_PH_PU", // 0111
"EV_PH_AR", // 1000
"EV_PH_9", // 1001
"EV_PH_ARL", // 1010
"EV_PH_CVR", // 1011
"EV_PH_AI8", // 1100
"EV_PH_AI10", // 1101
"EV_PH_AIL", // 1110
"EV_PH_DC", // 1111
"EV_PH_ACTIVATE_REQ",
"EV_PH_DEACTIVATE_REQ",
"EV_TIMER3",
};
static inline void D_L1L2(struct isac *isac, int pr, void *arg)
{
struct hisax_if *ifc = (struct hisax_if *) &isac->hisax_d_if;
DBG(DBG_PR, "pr %#x", pr);
ifc->l1l2(ifc, pr, arg);
}
static void ph_command(struct isac *isac, unsigned int command)
{
DBG(DBG_L1M, "ph_command %#x", command);
switch (isac->type) {
case TYPE_ISAC:
isac->write_isac(isac, ISAC_CIX0, (command << 2) | 3);
break;
case TYPE_ISACSX:
isac->write_isac(isac, ISACSX_CIX0, (command << 4) | (7 << 1));
break;
}
}
// ----------------------------------------------------------------------
static void l1_di(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmChangeState(fi, ST_L1_RESET);
ph_command(isac, ISAC_CMD_DI);
}
static void l1_di_deact_ind(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmChangeState(fi, ST_L1_RESET);
D_L1L2(isac, PH_DEACTIVATE | INDICATION, NULL);
ph_command(isac, ISAC_CMD_DI);
}
static void l1_go_f3pdown(struct FsmInst *fi, int event, void *arg)
{
FsmChangeState(fi, ST_L1_F3_PDOWN);
}
static void l1_go_f3pend_deact_ind(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmChangeState(fi, ST_L1_F3_PEND_DEACT);
D_L1L2(isac, PH_DEACTIVATE | INDICATION, NULL);
ph_command(isac, ISAC_CMD_DI);
}
static void l1_go_f3pend(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmChangeState(fi, ST_L1_F3_PEND_DEACT);
ph_command(isac, ISAC_CMD_DI);
}
static void l1_go_f4(struct FsmInst *fi, int event, void *arg)
{
FsmChangeState(fi, ST_L1_F4);
}
static void l1_go_f5(struct FsmInst *fi, int event, void *arg)
{
FsmChangeState(fi, ST_L1_F5);
}
static void l1_go_f6(struct FsmInst *fi, int event, void *arg)
{
FsmChangeState(fi, ST_L1_F6);
}
static void l1_go_f6_deact_ind(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmChangeState(fi, ST_L1_F6);
D_L1L2(isac, PH_DEACTIVATE | INDICATION, NULL);
}
static void l1_go_f7_act_ind(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmDelTimer(&isac->timer, 0);
FsmChangeState(fi, ST_L1_F7);
ph_command(isac, ISAC_CMD_AR8);
D_L1L2(isac, PH_ACTIVATE | INDICATION, NULL);
}
static void l1_go_f8(struct FsmInst *fi, int event, void *arg)
{
FsmChangeState(fi, ST_L1_F8);
}
static void l1_go_f8_deact_ind(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmChangeState(fi, ST_L1_F8);
D_L1L2(isac, PH_DEACTIVATE | INDICATION, NULL);
}
static void l1_ar8(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
FsmRestartTimer(&isac->timer, TIMER3_VALUE, EV_TIMER3, NULL, 2);
ph_command(isac, ISAC_CMD_AR8);
}
static void l1_timer3(struct FsmInst *fi, int event, void *arg)
{
struct isac *isac = fi->userdata;
ph_command(isac, ISAC_CMD_DI);
D_L1L2(isac, PH_DEACTIVATE | INDICATION, NULL);
}
// state machines according to data sheet PSB 2186 / 3186
static struct FsmNode L1FnList[] __initdata =
{
{ST_L1_RESET, EV_PH_RES, l1_di},
{ST_L1_RESET, EV_PH_EI, l1_di},
{ST_L1_RESET, EV_PH_DC, l1_go_f3pdown},
{ST_L1_RESET, EV_PH_AR, l1_go_f6},
{ST_L1_RESET, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F3_PDOWN, EV_PH_RES, l1_di},
{ST_L1_F3_PDOWN, EV_PH_EI, l1_di},
{ST_L1_F3_PDOWN, EV_PH_AR, l1_go_f6},
{ST_L1_F3_PDOWN, EV_PH_RSY, l1_go_f5},
{ST_L1_F3_PDOWN, EV_PH_PU, l1_go_f4},
{ST_L1_F3_PDOWN, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F3_PDOWN, EV_PH_ACTIVATE_REQ, l1_ar8},
{ST_L1_F3_PDOWN, EV_TIMER3, l1_timer3},
{ST_L1_F3_PEND_DEACT, EV_PH_RES, l1_di},
{ST_L1_F3_PEND_DEACT, EV_PH_EI, l1_di},
{ST_L1_F3_PEND_DEACT, EV_PH_DC, l1_go_f3pdown},
{ST_L1_F3_PEND_DEACT, EV_PH_RSY, l1_go_f5},
{ST_L1_F3_PEND_DEACT, EV_PH_AR, l1_go_f6},
{ST_L1_F3_PEND_DEACT, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F4, EV_PH_RES, l1_di},
{ST_L1_F4, EV_PH_EI, l1_di},
{ST_L1_F4, EV_PH_RSY, l1_go_f5},
{ST_L1_F4, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F4, EV_TIMER3, l1_timer3},
{ST_L1_F4, EV_PH_DC, l1_go_f3pdown},
{ST_L1_F5, EV_PH_RES, l1_di},
{ST_L1_F5, EV_PH_EI, l1_di},
{ST_L1_F5, EV_PH_AR, l1_go_f6},
{ST_L1_F5, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F5, EV_TIMER3, l1_timer3},
{ST_L1_F5, EV_PH_DR, l1_go_f3pend},
{ST_L1_F5, EV_PH_DC, l1_go_f3pdown},
{ST_L1_F6, EV_PH_RES, l1_di},
{ST_L1_F6, EV_PH_EI, l1_di},
{ST_L1_F6, EV_PH_RSY, l1_go_f8},
{ST_L1_F6, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F6, EV_PH_DR6, l1_go_f3pend},
{ST_L1_F6, EV_TIMER3, l1_timer3},
{ST_L1_F6, EV_PH_DC, l1_go_f3pdown},
{ST_L1_F7, EV_PH_RES, l1_di_deact_ind},
{ST_L1_F7, EV_PH_EI, l1_di_deact_ind},
{ST_L1_F7, EV_PH_AR, l1_go_f6_deact_ind},
{ST_L1_F7, EV_PH_RSY, l1_go_f8_deact_ind},
{ST_L1_F7, EV_PH_DR, l1_go_f3pend_deact_ind},
{ST_L1_F8, EV_PH_RES, l1_di},
{ST_L1_F8, EV_PH_EI, l1_di},
{ST_L1_F8, EV_PH_AR, l1_go_f6},
{ST_L1_F8, EV_PH_DR, l1_go_f3pend},
{ST_L1_F8, EV_PH_AI8, l1_go_f7_act_ind},
{ST_L1_F8, EV_TIMER3, l1_timer3},
{ST_L1_F8, EV_PH_DC, l1_go_f3pdown},
};
static void l1m_debug(struct FsmInst *fi, char *fmt, ...)
{
va_list args;
char buf[256];
va_start(args, fmt);
vsnprintf(buf, sizeof(buf), fmt, args);
DBG(DBG_L1M, "%s", buf);
va_end(args);
}
static void isac_version(struct isac *cs)
{
int val;
val = cs->read_isac(cs, ISAC_RBCH);
DBG(1, "ISAC version (%x): %s", val, ISACVer[(val >> 5) & 3]);
}
static void isac_empty_fifo(struct isac *isac, int count)
{
// this also works for isacsx, since
// CMDR(D) register works the same
u_char *ptr;
DBG(DBG_IRQ, "count %d", count);
if ((isac->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
DBG(DBG_WARN, "overrun %d", isac->rcvidx + count);
isac->write_isac(isac, ISAC_CMDR, ISAC_CMDR_RMC);
isac->rcvidx = 0;
return;
}
ptr = isac->rcvbuf + isac->rcvidx;
isac->rcvidx += count;
isac->read_isac_fifo(isac, ptr, count);
isac->write_isac(isac, ISAC_CMDR, ISAC_CMDR_RMC);
DBG_PACKET(DBG_RFIFO, ptr, count);
}
static void isac_fill_fifo(struct isac *isac)
{
// this also works for isacsx, since
// CMDR(D) register works the same
int count;
unsigned char cmd;
u_char *ptr;
BUG_ON(!isac->tx_skb);
count = isac->tx_skb->len;
BUG_ON(count <= 0);
DBG(DBG_IRQ, "count %d", count);
if (count > 0x20) {
count = 0x20;
cmd = ISAC_CMDR_XTF;
} else {
cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME;
}
ptr = isac->tx_skb->data;
skb_pull(isac->tx_skb, count);
isac->tx_cnt += count;
DBG_PACKET(DBG_XFIFO, ptr, count);
isac->write_isac_fifo(isac, ptr, count);
isac->write_isac(isac, ISAC_CMDR, cmd);
}
static void isac_retransmit(struct isac *isac)
{
if (!isac->tx_skb) {
DBG(DBG_WARN, "no skb");
return;
}
skb_push(isac->tx_skb, isac->tx_cnt);
isac->tx_cnt = 0;
}
static inline void isac_cisq_interrupt(struct isac *isac)
{
unsigned char val;
val = isac->read_isac(isac, ISAC_CIR0);
DBG(DBG_IRQ, "CIR0 %#x", val);
if (val & ISAC_CIR0_CIC0) {
DBG(DBG_IRQ, "CODR0 %#x", (val >> 2) & 0xf);
FsmEvent(&isac->l1m, (val >> 2) & 0xf, NULL);
}
if (val & ISAC_CIR0_CIC1) {
val = isac->read_isac(isac, ISAC_CIR1);
DBG(DBG_WARN, "ISAC CIR1 %#x", val);
}
}
static inline void isac_rme_interrupt(struct isac *isac)
{
unsigned char val;
int count;
struct sk_buff *skb;
val = isac->read_isac(isac, ISAC_RSTA);
if ((val & (ISAC_RSTA_RDO | ISAC_RSTA_CRC | ISAC_RSTA_RAB))
!= ISAC_RSTA_CRC) {
DBG(DBG_WARN, "RSTA %#x, dropped", val);
isac->write_isac(isac, ISAC_CMDR, ISAC_CMDR_RMC);
goto out;
}
count = isac->read_isac(isac, ISAC_RBCL) & 0x1f;
DBG(DBG_IRQ, "RBCL %#x", count);
if (count == 0)
count = 0x20;
isac_empty_fifo(isac, count);
count = isac->rcvidx;
if (count < 1) {
DBG(DBG_WARN, "count %d < 1", count);
goto out;
}
skb = alloc_skb(count, GFP_ATOMIC);
if (!skb) {
DBG(DBG_WARN, "no memory, dropping\n");
goto out;
}
memcpy(skb_put(skb, count), isac->rcvbuf, count);
DBG_SKB(DBG_RPACKET, skb);
D_L1L2(isac, PH_DATA | INDICATION, skb);
out:
isac->rcvidx = 0;
}
static inline void isac_xpr_interrupt(struct isac *isac)
{
if (!isac->tx_skb)
return;
if (isac->tx_skb->len > 0) {
isac_fill_fifo(isac);
return;
}
dev_kfree_skb_irq(isac->tx_skb);
isac->tx_cnt = 0;
isac->tx_skb = NULL;
D_L1L2(isac, PH_DATA | CONFIRM, NULL);
}
static inline void isac_exi_interrupt(struct isac *isac)
{
unsigned char val;
val = isac->read_isac(isac, ISAC_EXIR);
DBG(2, "EXIR %#x", val);
if (val & ISAC_EXIR_XMR) {
DBG(DBG_WARN, "ISAC XMR");
isac_retransmit(isac);
}
if (val & ISAC_EXIR_XDU) {
DBG(DBG_WARN, "ISAC XDU");
isac_retransmit(isac);
}
if (val & ISAC_EXIR_MOS) { /* MOS */
DBG(DBG_WARN, "MOS");
val = isac->read_isac(isac, ISAC_MOSR);
DBG(2, "ISAC MOSR %#x", val);
}
}
void isac_irq(struct isac *isac)
{
unsigned char val;
val = isac->read_isac(isac, ISAC_ISTA);
DBG(DBG_IRQ, "ISTA %#x", val);
if (val & ISAC_ISTA_EXI) {
DBG(DBG_IRQ, "EXI");
isac_exi_interrupt(isac);
}
if (val & ISAC_ISTA_XPR) {
DBG(DBG_IRQ, "XPR");
isac_xpr_interrupt(isac);
}
if (val & ISAC_ISTA_RME) {
DBG(DBG_IRQ, "RME");
isac_rme_interrupt(isac);
}
if (val & ISAC_ISTA_RPF) {
DBG(DBG_IRQ, "RPF");
isac_empty_fifo(isac, 0x20);
}
if (val & ISAC_ISTA_CISQ) {
DBG(DBG_IRQ, "CISQ");
isac_cisq_interrupt(isac);
}
if (val & ISAC_ISTA_RSC) {
DBG(DBG_WARN, "RSC");
}
if (val & ISAC_ISTA_SIN) {
DBG(DBG_WARN, "SIN");
}
isac->write_isac(isac, ISAC_MASK, 0xff);
isac->write_isac(isac, ISAC_MASK, 0x00);
}
// ======================================================================
static inline void isacsx_cic_interrupt(struct isac *isac)
{
unsigned char val;
val = isac->read_isac(isac, ISACSX_CIR0);
DBG(DBG_IRQ, "CIR0 %#x", val);
if (val & ISACSX_CIR0_CIC0) {
DBG(DBG_IRQ, "CODR0 %#x", val >> 4);
FsmEvent(&isac->l1m, val >> 4, NULL);
}
}
static inline void isacsx_rme_interrupt(struct isac *isac)
{
int count;
struct sk_buff *skb;
unsigned char val;
val = isac->read_isac(isac, ISACSX_RSTAD);
if ((val & (ISACSX_RSTAD_VFR |
ISACSX_RSTAD_RDO |
ISACSX_RSTAD_CRC |
ISACSX_RSTAD_RAB))
!= (ISACSX_RSTAD_VFR | ISACSX_RSTAD_CRC)) {
DBG(DBG_WARN, "RSTAD %#x, dropped", val);
isac->write_isac(isac, ISACSX_CMDRD, ISACSX_CMDRD_RMC);
goto out;
}
count = isac->read_isac(isac, ISACSX_RBCLD) & 0x1f;
DBG(DBG_IRQ, "RBCLD %#x", count);
if (count == 0)
count = 0x20;
isac_empty_fifo(isac, count);
// strip trailing status byte
count = isac->rcvidx - 1;
if (count < 1) {
DBG(DBG_WARN, "count %d < 1", count);
goto out;
}
skb = dev_alloc_skb(count);
if (!skb) {
DBG(DBG_WARN, "no memory, dropping");
goto out;
}
memcpy(skb_put(skb, count), isac->rcvbuf, count);
DBG_SKB(DBG_RPACKET, skb);
D_L1L2(isac, PH_DATA | INDICATION, skb);
out:
isac->rcvidx = 0;
}
static inline void isacsx_xpr_interrupt(struct isac *isac)
{
if (!isac->tx_skb)
return;
if (isac->tx_skb->len > 0) {
isac_fill_fifo(isac);
return;
}
dev_kfree_skb_irq(isac->tx_skb);
isac->tx_skb = NULL;
isac->tx_cnt = 0;
D_L1L2(isac, PH_DATA | CONFIRM, NULL);
}
static inline void isacsx_icd_interrupt(struct isac *isac)
{
unsigned char val;
val = isac->read_isac(isac, ISACSX_ISTAD);
DBG(DBG_IRQ, "ISTAD %#x", val);
if (val & ISACSX_ISTAD_XDU) {
DBG(DBG_WARN, "ISTAD XDU");
isac_retransmit(isac);
}
if (val & ISACSX_ISTAD_XMR) {
DBG(DBG_WARN, "ISTAD XMR");
isac_retransmit(isac);
}
if (val & ISACSX_ISTAD_XPR) {
DBG(DBG_IRQ, "ISTAD XPR");
isacsx_xpr_interrupt(isac);
}
if (val & ISACSX_ISTAD_RFO) {
DBG(DBG_WARN, "ISTAD RFO");
isac->write_isac(isac, ISACSX_CMDRD, ISACSX_CMDRD_RMC);
}
if (val & ISACSX_ISTAD_RME) {
DBG(DBG_IRQ, "ISTAD RME");
isacsx_rme_interrupt(isac);
}
if (val & ISACSX_ISTAD_RPF) {
DBG(DBG_IRQ, "ISTAD RPF");
isac_empty_fifo(isac, 0x20);
}
}
void isacsx_irq(struct isac *isac)
{
unsigned char val;
val = isac->read_isac(isac, ISACSX_ISTA);
DBG(DBG_IRQ, "ISTA %#x", val);
if (val & ISACSX_ISTA_ICD)
isacsx_icd_interrupt(isac);
if (val & ISACSX_ISTA_CIC)
isacsx_cic_interrupt(isac);
}
void isac_init(struct isac *isac)
{
isac->tx_skb = NULL;
isac->l1m.fsm = &l1fsm;
isac->l1m.state = ST_L1_RESET;
#ifdef CONFIG_HISAX_DEBUG
isac->l1m.debug = 1;
#else
isac->l1m.debug = 0;
#endif
isac->l1m.userdata = isac;
isac->l1m.printdebug = l1m_debug;
FsmInitTimer(&isac->l1m, &isac->timer);
}
void isac_setup(struct isac *isac)
{
int val, eval;
isac->type = TYPE_ISAC;
isac_version(isac);
ph_command(isac, ISAC_CMD_RES);
isac->write_isac(isac, ISAC_MASK, 0xff);
isac->mocr = 0xaa;
if (test_bit(ISAC_IOM1, &isac->flags)) {
/* IOM 1 Mode */
isac->write_isac(isac, ISAC_ADF2, 0x0);
isac->write_isac(isac, ISAC_SPCR, 0xa);
isac->write_isac(isac, ISAC_ADF1, 0x2);
isac->write_isac(isac, ISAC_STCR, 0x70);
isac->write_isac(isac, ISAC_MODE, 0xc9);
} else {
/* IOM 2 Mode */
if (!isac->adf2)
isac->adf2 = 0x80;
isac->write_isac(isac, ISAC_ADF2, isac->adf2);
isac->write_isac(isac, ISAC_SQXR, 0x2f);
isac->write_isac(isac, ISAC_SPCR, 0x00);
isac->write_isac(isac, ISAC_STCR, 0x70);
isac->write_isac(isac, ISAC_MODE, 0xc9);
isac->write_isac(isac, ISAC_TIMR, 0x00);
isac->write_isac(isac, ISAC_ADF1, 0x00);
}
val = isac->read_isac(isac, ISAC_STAR);
DBG(2, "ISAC STAR %x", val);
val = isac->read_isac(isac, ISAC_MODE);
DBG(2, "ISAC MODE %x", val);
val = isac->read_isac(isac, ISAC_ADF2);
DBG(2, "ISAC ADF2 %x", val);
val = isac->read_isac(isac, ISAC_ISTA);
DBG(2, "ISAC ISTA %x", val);
if (val & 0x01) {
eval = isac->read_isac(isac, ISAC_EXIR);
DBG(2, "ISAC EXIR %x", eval);
}
val = isac->read_isac(isac, ISAC_CIR0);
DBG(2, "ISAC CIR0 %x", val);
FsmEvent(&isac->l1m, (val >> 2) & 0xf, NULL);
isac->write_isac(isac, ISAC_MASK, 0x0);
// RESET Receiver and Transmitter
isac->write_isac(isac, ISAC_CMDR, ISAC_CMDR_XRES | ISAC_CMDR_RRES);
}
void isacsx_setup(struct isac *isac)
{
isac->type = TYPE_ISACSX;
// clear LDD
isac->write_isac(isac, ISACSX_TR_CONF0, 0x00);
// enable transmitter
isac->write_isac(isac, ISACSX_TR_CONF2, 0x00);
// transparent mode 0, RAC, stop/go
isac->write_isac(isac, ISACSX_MODED, 0xc9);
// all HDLC IRQ unmasked
isac->write_isac(isac, ISACSX_MASKD, 0x03);
// unmask ICD, CID IRQs
isac->write_isac(isac, ISACSX_MASK,
~(ISACSX_ISTA_ICD | ISACSX_ISTA_CIC));
}
void isac_d_l2l1(struct hisax_if *hisax_d_if, int pr, void *arg)
{
struct isac *isac = hisax_d_if->priv;
struct sk_buff *skb = arg;
DBG(DBG_PR, "pr %#x", pr);
switch (pr) {
case PH_ACTIVATE | REQUEST:
FsmEvent(&isac->l1m, EV_PH_ACTIVATE_REQ, NULL);
break;
case PH_DEACTIVATE | REQUEST:
FsmEvent(&isac->l1m, EV_PH_DEACTIVATE_REQ, NULL);
break;
case PH_DATA | REQUEST:
DBG(DBG_PR, "PH_DATA REQUEST len %d", skb->len);
DBG_SKB(DBG_XPACKET, skb);
if (isac->l1m.state != ST_L1_F7) {
DBG(1, "L1 wrong state %d\n", isac->l1m.state);
dev_kfree_skb(skb);
break;
}
BUG_ON(isac->tx_skb);
isac->tx_skb = skb;
isac_fill_fifo(isac);
break;
}
}
static int __init hisax_isac_init(void)
{
printk(KERN_INFO "hisax_isac: ISAC-S/ISAC-SX ISDN driver v0.1.0\n");
l1fsm.state_count = L1_STATE_COUNT;
l1fsm.event_count = L1_EVENT_COUNT;
l1fsm.strState = strL1State;
l1fsm.strEvent = strL1Event;
return FsmNew(&l1fsm, L1FnList, ARRAY_SIZE(L1FnList));
}
static void __exit hisax_isac_exit(void)
{
FsmFree(&l1fsm);
}
EXPORT_SYMBOL(isac_init);
EXPORT_SYMBOL(isac_d_l2l1);
EXPORT_SYMBOL(isacsx_setup);
EXPORT_SYMBOL(isacsx_irq);
EXPORT_SYMBOL(isac_setup);
EXPORT_SYMBOL(isac_irq);
module_init(hisax_isac_init);
module_exit(hisax_isac_exit);
| gpl-2.0 |
RazerRom/kernel_lge_hammerhead | drivers/misc/eeprom/digsy_mtc_eeprom.c | 10324 | 2098 | /*
* EEPROMs access control driver for display configuration EEPROMs
* on DigsyMTC board.
*
* (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <linux/eeprom_93xx46.h>
#define GPIO_EEPROM_CLK 216
#define GPIO_EEPROM_CS 210
#define GPIO_EEPROM_DI 217
#define GPIO_EEPROM_DO 249
#define GPIO_EEPROM_OE 255
#define EE_SPI_BUS_NUM 1
static void digsy_mtc_op_prepare(void *p)
{
/* enable */
gpio_set_value(GPIO_EEPROM_OE, 0);
}
static void digsy_mtc_op_finish(void *p)
{
/* disable */
gpio_set_value(GPIO_EEPROM_OE, 1);
}
struct eeprom_93xx46_platform_data digsy_mtc_eeprom_data = {
.flags = EE_ADDR8,
.prepare = digsy_mtc_op_prepare,
.finish = digsy_mtc_op_finish,
};
static struct spi_gpio_platform_data eeprom_spi_gpio_data = {
.sck = GPIO_EEPROM_CLK,
.mosi = GPIO_EEPROM_DI,
.miso = GPIO_EEPROM_DO,
.num_chipselect = 1,
};
static struct platform_device digsy_mtc_eeprom = {
.name = "spi_gpio",
.id = EE_SPI_BUS_NUM,
.dev = {
.platform_data = &eeprom_spi_gpio_data,
},
};
static struct spi_board_info digsy_mtc_eeprom_info[] __initdata = {
{
.modalias = "93xx46",
.max_speed_hz = 1000000,
.bus_num = EE_SPI_BUS_NUM,
.chip_select = 0,
.mode = SPI_MODE_0,
.controller_data = (void *)GPIO_EEPROM_CS,
.platform_data = &digsy_mtc_eeprom_data,
},
};
static int __init digsy_mtc_eeprom_devices_init(void)
{
int ret;
ret = gpio_request_one(GPIO_EEPROM_OE, GPIOF_OUT_INIT_HIGH,
"93xx46 EEPROMs OE");
if (ret) {
pr_err("can't request gpio %d\n", GPIO_EEPROM_OE);
return ret;
}
spi_register_board_info(digsy_mtc_eeprom_info,
ARRAY_SIZE(digsy_mtc_eeprom_info));
return platform_device_register(&digsy_mtc_eeprom);
}
device_initcall(digsy_mtc_eeprom_devices_init);
| gpl-2.0 |
awh44/CS370 | linux-2.6.22.19-cs543/arch/arm/mach-ep93xx/gesbc9312.c | 85 | 2225 | /*
* arch/arm/mach-ep93xx/gesbc9312.c
* Glomation GESBC-9312-sx support.
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static struct physmap_flash_data gesbc9312_flash_data = {
.width = 4,
};
static struct resource gesbc9312_flash_resource = {
.start = 0x60000000,
.end = 0x607fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device gesbc9312_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &gesbc9312_flash_data,
},
.num_resources = 1,
.resource = &gesbc9312_flash_resource,
};
static struct ep93xx_eth_data gesbc9312_eth_data = {
.phy_id = 1,
};
static struct resource gesbc9312_eth_resource[] = {
{
.start = EP93XX_ETHERNET_PHYS_BASE,
.end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_EP93XX_ETHERNET,
.end = IRQ_EP93XX_ETHERNET,
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device gesbc9312_eth_device = {
.name = "ep93xx-eth",
.id = -1,
.dev = {
.platform_data = &gesbc9312_eth_data,
},
.num_resources = 2,
.resource = gesbc9312_eth_resource,
};
static void __init gesbc9312_init_machine(void)
{
ep93xx_init_devices();
platform_device_register(&gesbc9312_flash);
platform_device_register(&gesbc9312_eth_device);
}
MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.phys_io = EP93XX_APB_PHYS_BASE,
.io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.timer = &ep93xx_timer,
.init_machine = gesbc9312_init_machine,
MACHINE_END
| gpl-2.0 |
suhorng/vm14hw1 | hw/bt-sdp.c | 85 | 29506 | /*
* Service Discover Protocol server for QEMU L2CAP devices
*
* Copyright (C) 2008 Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu-common.h"
#include "bt.h"
struct bt_l2cap_sdp_state_s {
struct bt_l2cap_conn_params_s *channel;
struct sdp_service_record_s {
int match;
int *uuid;
int uuids;
struct sdp_service_attribute_s {
int match;
int attribute_id;
int len;
void *pair;
} *attribute_list;
int attributes;
} *service_list;
int services;
};
static ssize_t sdp_datalen(const uint8_t **element, ssize_t *left)
{
size_t len = *(*element) ++ & SDP_DSIZE_MASK;
if (!*left)
return -1;
(*left) --;
if (len < SDP_DSIZE_NEXT1)
return 1 << len;
else if (len == SDP_DSIZE_NEXT1) {
if (*left < 1)
return -1;
(*left) --;
return *(*element) ++;
} else if (len == SDP_DSIZE_NEXT2) {
if (*left < 2)
return -1;
(*left) -= 2;
len = (*(*element) ++) << 8;
return len | (*(*element) ++);
} else {
if (*left < 4)
return -1;
(*left) -= 4;
len = (*(*element) ++) << 24;
len |= (*(*element) ++) << 16;
len |= (*(*element) ++) << 8;
return len | (*(*element) ++);
}
}
static const uint8_t bt_base_uuid[12] = {
0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0x80, 0x5f, 0x9b, 0x34, 0xfb,
};
static int sdp_uuid_match(struct sdp_service_record_s *record,
const uint8_t *uuid, ssize_t datalen)
{
int *lo, hi, val;
if (datalen == 16 || datalen == 4) {
if (datalen == 16 && memcmp(uuid + 4, bt_base_uuid, 12))
return 0;
if (uuid[0] | uuid[1])
return 0;
uuid += 2;
}
val = (uuid[0] << 8) | uuid[1];
lo = record->uuid;
hi = record->uuids;
while (hi >>= 1)
if (lo[hi] <= val)
lo += hi;
return *lo == val;
}
#define CONTINUATION_PARAM_SIZE (1 + sizeof(int))
#define MAX_PDU_OUT_SIZE 96 /* Arbitrary */
#define PDU_HEADER_SIZE 5
#define MAX_RSP_PARAM_SIZE (MAX_PDU_OUT_SIZE - PDU_HEADER_SIZE - \
CONTINUATION_PARAM_SIZE)
static int sdp_svc_match(struct bt_l2cap_sdp_state_s *sdp,
const uint8_t **req, ssize_t *len)
{
size_t datalen;
int i;
if ((**req & ~SDP_DSIZE_MASK) != SDP_DTYPE_UUID)
return 1;
datalen = sdp_datalen(req, len);
if (datalen != 2 && datalen != 4 && datalen != 16)
return 1;
for (i = 0; i < sdp->services; i ++)
if (sdp_uuid_match(&sdp->service_list[i], *req, datalen))
sdp->service_list[i].match = 1;
(*req) += datalen;
(*len) -= datalen;
return 0;
}
static ssize_t sdp_svc_search(struct bt_l2cap_sdp_state_s *sdp,
uint8_t *rsp, const uint8_t *req, ssize_t len)
{
ssize_t seqlen;
int i, count, start, end, max;
int32_t handle;
/* Perform the search */
for (i = 0; i < sdp->services; i ++)
sdp->service_list[i].match = 0;
if (len < 1)
return -SDP_INVALID_SYNTAX;
if ((*req & ~SDP_DSIZE_MASK) == SDP_DTYPE_SEQ) {
seqlen = sdp_datalen(&req, &len);
if (seqlen < 3 || len < seqlen)
return -SDP_INVALID_SYNTAX;
len -= seqlen;
while (seqlen)
if (sdp_svc_match(sdp, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
} else if (sdp_svc_match(sdp, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
if (len < 3)
return -SDP_INVALID_SYNTAX;
max = (req[0] << 8) | req[1];
req += 2;
len -= 2;
if (*req) {
if (len <= sizeof(int))
return -SDP_INVALID_SYNTAX;
len -= sizeof(int);
memcpy(&start, req + 1, sizeof(int));
} else
start = 0;
if (len > 1)
return -SDP_INVALID_SYNTAX;
/* Output the results */
len = 4;
count = 0;
end = start;
for (i = 0; i < sdp->services; i ++)
if (sdp->service_list[i].match) {
if (count >= start && count < max && len + 4 < MAX_RSP_PARAM_SIZE) {
handle = i;
memcpy(rsp + len, &handle, 4);
len += 4;
end = count + 1;
}
count ++;
}
rsp[0] = count >> 8;
rsp[1] = count & 0xff;
rsp[2] = (end - start) >> 8;
rsp[3] = (end - start) & 0xff;
if (end < count) {
rsp[len ++] = sizeof(int);
memcpy(rsp + len, &end, sizeof(int));
len += 4;
} else
rsp[len ++] = 0;
return len;
}
static int sdp_attr_match(struct sdp_service_record_s *record,
const uint8_t **req, ssize_t *len)
{
int i, start, end;
if (**req == (SDP_DTYPE_UINT | SDP_DSIZE_2)) {
(*req) ++;
if (*len < 3)
return 1;
start = (*(*req) ++) << 8;
start |= *(*req) ++;
end = start;
*len -= 3;
} else if (**req == (SDP_DTYPE_UINT | SDP_DSIZE_4)) {
(*req) ++;
if (*len < 5)
return 1;
start = (*(*req) ++) << 8;
start |= *(*req) ++;
end = (*(*req) ++) << 8;
end |= *(*req) ++;
*len -= 5;
} else
return 1;
for (i = 0; i < record->attributes; i ++)
if (record->attribute_list[i].attribute_id >= start &&
record->attribute_list[i].attribute_id <= end)
record->attribute_list[i].match = 1;
return 0;
}
static ssize_t sdp_attr_get(struct bt_l2cap_sdp_state_s *sdp,
uint8_t *rsp, const uint8_t *req, ssize_t len)
{
ssize_t seqlen;
int i, start, end, max;
int32_t handle;
struct sdp_service_record_s *record;
uint8_t *lst;
/* Perform the search */
if (len < 7)
return -SDP_INVALID_SYNTAX;
memcpy(&handle, req, 4);
req += 4;
len -= 4;
if (handle < 0 || handle > sdp->services)
return -SDP_INVALID_RECORD_HANDLE;
record = &sdp->service_list[handle];
for (i = 0; i < record->attributes; i ++)
record->attribute_list[i].match = 0;
max = (req[0] << 8) | req[1];
req += 2;
len -= 2;
if (max < 0x0007)
return -SDP_INVALID_SYNTAX;
if ((*req & ~SDP_DSIZE_MASK) == SDP_DTYPE_SEQ) {
seqlen = sdp_datalen(&req, &len);
if (seqlen < 3 || len < seqlen)
return -SDP_INVALID_SYNTAX;
len -= seqlen;
while (seqlen)
if (sdp_attr_match(record, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
} else if (sdp_attr_match(record, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
if (len < 1)
return -SDP_INVALID_SYNTAX;
if (*req) {
if (len <= sizeof(int))
return -SDP_INVALID_SYNTAX;
len -= sizeof(int);
memcpy(&start, req + 1, sizeof(int));
} else
start = 0;
if (len > 1)
return -SDP_INVALID_SYNTAX;
/* Output the results */
lst = rsp + 2;
max = MIN(max, MAX_RSP_PARAM_SIZE);
len = 3 - start;
end = 0;
for (i = 0; i < record->attributes; i ++)
if (record->attribute_list[i].match) {
if (len >= 0 && len + record->attribute_list[i].len < max) {
memcpy(lst + len, record->attribute_list[i].pair,
record->attribute_list[i].len);
end = len + record->attribute_list[i].len;
}
len += record->attribute_list[i].len;
}
if (0 >= start) {
lst[0] = SDP_DTYPE_SEQ | SDP_DSIZE_NEXT2;
lst[1] = (len + start - 3) >> 8;
lst[2] = (len + start - 3) & 0xff;
}
rsp[0] = end >> 8;
rsp[1] = end & 0xff;
if (end < len) {
len = end + start;
lst[end ++] = sizeof(int);
memcpy(lst + end, &len, sizeof(int));
end += sizeof(int);
} else
lst[end ++] = 0;
return end + 2;
}
static int sdp_svc_attr_match(struct bt_l2cap_sdp_state_s *sdp,
const uint8_t **req, ssize_t *len)
{
int i, j, start, end;
struct sdp_service_record_s *record;
if (**req == (SDP_DTYPE_UINT | SDP_DSIZE_2)) {
(*req) ++;
if (*len < 3)
return 1;
start = (*(*req) ++) << 8;
start |= *(*req) ++;
end = start;
*len -= 3;
} else if (**req == (SDP_DTYPE_UINT | SDP_DSIZE_4)) {
(*req) ++;
if (*len < 5)
return 1;
start = (*(*req) ++) << 8;
start |= *(*req) ++;
end = (*(*req) ++) << 8;
end |= *(*req) ++;
*len -= 5;
} else
return 1;
for (i = 0; i < sdp->services; i ++)
if ((record = &sdp->service_list[i])->match)
for (j = 0; j < record->attributes; j ++)
if (record->attribute_list[j].attribute_id >= start &&
record->attribute_list[j].attribute_id <= end)
record->attribute_list[j].match = 1;
return 0;
}
static ssize_t sdp_svc_search_attr_get(struct bt_l2cap_sdp_state_s *sdp,
uint8_t *rsp, const uint8_t *req, ssize_t len)
{
ssize_t seqlen;
int i, j, start, end, max;
struct sdp_service_record_s *record;
uint8_t *lst;
/* Perform the search */
for (i = 0; i < sdp->services; i ++) {
sdp->service_list[i].match = 0;
for (j = 0; j < sdp->service_list[i].attributes; j ++)
sdp->service_list[i].attribute_list[j].match = 0;
}
if (len < 1)
return -SDP_INVALID_SYNTAX;
if ((*req & ~SDP_DSIZE_MASK) == SDP_DTYPE_SEQ) {
seqlen = sdp_datalen(&req, &len);
if (seqlen < 3 || len < seqlen)
return -SDP_INVALID_SYNTAX;
len -= seqlen;
while (seqlen)
if (sdp_svc_match(sdp, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
} else if (sdp_svc_match(sdp, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
if (len < 3)
return -SDP_INVALID_SYNTAX;
max = (req[0] << 8) | req[1];
req += 2;
len -= 2;
if (max < 0x0007)
return -SDP_INVALID_SYNTAX;
if ((*req & ~SDP_DSIZE_MASK) == SDP_DTYPE_SEQ) {
seqlen = sdp_datalen(&req, &len);
if (seqlen < 3 || len < seqlen)
return -SDP_INVALID_SYNTAX;
len -= seqlen;
while (seqlen)
if (sdp_svc_attr_match(sdp, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
} else if (sdp_svc_attr_match(sdp, &req, &seqlen))
return -SDP_INVALID_SYNTAX;
if (len < 1)
return -SDP_INVALID_SYNTAX;
if (*req) {
if (len <= sizeof(int))
return -SDP_INVALID_SYNTAX;
len -= sizeof(int);
memcpy(&start, req + 1, sizeof(int));
} else
start = 0;
if (len > 1)
return -SDP_INVALID_SYNTAX;
/* Output the results */
/* This assumes empty attribute lists are never to be returned even
* for matching Service Records. In practice this shouldn't happen
* as the requestor will usually include the always present
* ServiceRecordHandle AttributeID in AttributeIDList. */
lst = rsp + 2;
max = MIN(max, MAX_RSP_PARAM_SIZE);
len = 3 - start;
end = 0;
for (i = 0; i < sdp->services; i ++)
if ((record = &sdp->service_list[i])->match) {
len += 3;
seqlen = len;
for (j = 0; j < record->attributes; j ++)
if (record->attribute_list[j].match) {
if (len >= 0)
if (len + record->attribute_list[j].len < max) {
memcpy(lst + len, record->attribute_list[j].pair,
record->attribute_list[j].len);
end = len + record->attribute_list[j].len;
}
len += record->attribute_list[j].len;
}
if (seqlen == len)
len -= 3;
else if (seqlen >= 3 && seqlen < max) {
lst[seqlen - 3] = SDP_DTYPE_SEQ | SDP_DSIZE_NEXT2;
lst[seqlen - 2] = (len - seqlen) >> 8;
lst[seqlen - 1] = (len - seqlen) & 0xff;
}
}
if (len == 3 - start)
len -= 3;
else if (0 >= start) {
lst[0] = SDP_DTYPE_SEQ | SDP_DSIZE_NEXT2;
lst[1] = (len + start - 3) >> 8;
lst[2] = (len + start - 3) & 0xff;
}
rsp[0] = end >> 8;
rsp[1] = end & 0xff;
if (end < len) {
len = end + start;
lst[end ++] = sizeof(int);
memcpy(lst + end, &len, sizeof(int));
end += sizeof(int);
} else
lst[end ++] = 0;
return end + 2;
}
static void bt_l2cap_sdp_sdu_in(void *opaque, const uint8_t *data, int len)
{
struct bt_l2cap_sdp_state_s *sdp = opaque;
enum bt_sdp_cmd pdu_id;
uint8_t rsp[MAX_PDU_OUT_SIZE - PDU_HEADER_SIZE], *sdu_out;
int transaction_id, plen;
int err = 0;
int rsp_len = 0;
if (len < 5) {
fprintf(stderr, "%s: short SDP PDU (%iB).\n", __FUNCTION__, len);
return;
}
pdu_id = *data ++;
transaction_id = (data[0] << 8) | data[1];
plen = (data[2] << 8) | data[3];
data += 4;
len -= 5;
if (len != plen) {
fprintf(stderr, "%s: wrong SDP PDU length (%iB != %iB).\n",
__FUNCTION__, plen, len);
err = SDP_INVALID_PDU_SIZE;
goto respond;
}
switch (pdu_id) {
case SDP_SVC_SEARCH_REQ:
rsp_len = sdp_svc_search(sdp, rsp, data, len);
pdu_id = SDP_SVC_SEARCH_RSP;
break;
case SDP_SVC_ATTR_REQ:
rsp_len = sdp_attr_get(sdp, rsp, data, len);
pdu_id = SDP_SVC_ATTR_RSP;
break;
case SDP_SVC_SEARCH_ATTR_REQ:
rsp_len = sdp_svc_search_attr_get(sdp, rsp, data, len);
pdu_id = SDP_SVC_SEARCH_ATTR_RSP;
break;
case SDP_ERROR_RSP:
case SDP_SVC_ATTR_RSP:
case SDP_SVC_SEARCH_RSP:
case SDP_SVC_SEARCH_ATTR_RSP:
default:
fprintf(stderr, "%s: unexpected SDP PDU ID %02x.\n",
__FUNCTION__, pdu_id);
err = SDP_INVALID_SYNTAX;
break;
}
if (rsp_len < 0) {
err = -rsp_len;
rsp_len = 0;
}
respond:
if (err) {
pdu_id = SDP_ERROR_RSP;
rsp[rsp_len ++] = err >> 8;
rsp[rsp_len ++] = err & 0xff;
}
sdu_out = sdp->channel->sdu_out(sdp->channel, rsp_len + PDU_HEADER_SIZE);
sdu_out[0] = pdu_id;
sdu_out[1] = transaction_id >> 8;
sdu_out[2] = transaction_id & 0xff;
sdu_out[3] = rsp_len >> 8;
sdu_out[4] = rsp_len & 0xff;
memcpy(sdu_out + PDU_HEADER_SIZE, rsp, rsp_len);
sdp->channel->sdu_submit(sdp->channel);
}
static void bt_l2cap_sdp_close_ch(void *opaque)
{
struct bt_l2cap_sdp_state_s *sdp = opaque;
int i;
for (i = 0; i < sdp->services; i ++) {
qemu_free(sdp->service_list[i].attribute_list->pair);
qemu_free(sdp->service_list[i].attribute_list);
qemu_free(sdp->service_list[i].uuid);
}
qemu_free(sdp->service_list);
qemu_free(sdp);
}
struct sdp_def_service_s {
uint16_t class_uuid;
struct sdp_def_attribute_s {
uint16_t id;
struct sdp_def_data_element_s {
uint8_t type;
union {
uint32_t uint;
const char *str;
struct sdp_def_data_element_s *list;
} value;
} data;
} attributes[];
};
/* Calculate a safe byte count to allocate that will store the given
* element, at the same time count elements of a UUID type. */
static int sdp_attr_max_size(struct sdp_def_data_element_s *element,
int *uuids)
{
int type = element->type & ~SDP_DSIZE_MASK;
int len;
if (type == SDP_DTYPE_UINT || type == SDP_DTYPE_UUID ||
type == SDP_DTYPE_BOOL) {
if (type == SDP_DTYPE_UUID)
(*uuids) ++;
return 1 + (1 << (element->type & SDP_DSIZE_MASK));
}
if (type == SDP_DTYPE_STRING || type == SDP_DTYPE_URL) {
if (element->type & SDP_DSIZE_MASK) {
for (len = 0; element->value.str[len] |
element->value.str[len + 1]; len ++);
return len;
} else
return 2 + strlen(element->value.str);
}
if (type != SDP_DTYPE_SEQ)
exit(-1);
len = 2;
element = element->value.list;
while (element->type)
len += sdp_attr_max_size(element ++, uuids);
if (len > 255)
exit (-1);
return len;
}
static int sdp_attr_write(uint8_t *data,
struct sdp_def_data_element_s *element, int **uuid)
{
int type = element->type & ~SDP_DSIZE_MASK;
int len = 0;
if (type == SDP_DTYPE_UINT || type == SDP_DTYPE_BOOL) {
data[len ++] = element->type;
if ((element->type & SDP_DSIZE_MASK) == SDP_DSIZE_1)
data[len ++] = (element->value.uint >> 0) & 0xff;
else if ((element->type & SDP_DSIZE_MASK) == SDP_DSIZE_2) {
data[len ++] = (element->value.uint >> 8) & 0xff;
data[len ++] = (element->value.uint >> 0) & 0xff;
} else if ((element->type & SDP_DSIZE_MASK) == SDP_DSIZE_4) {
data[len ++] = (element->value.uint >> 24) & 0xff;
data[len ++] = (element->value.uint >> 16) & 0xff;
data[len ++] = (element->value.uint >> 8) & 0xff;
data[len ++] = (element->value.uint >> 0) & 0xff;
}
return len;
}
if (type == SDP_DTYPE_UUID) {
*(*uuid) ++ = element->value.uint;
data[len ++] = element->type;
data[len ++] = (element->value.uint >> 24) & 0xff;
data[len ++] = (element->value.uint >> 16) & 0xff;
data[len ++] = (element->value.uint >> 8) & 0xff;
data[len ++] = (element->value.uint >> 0) & 0xff;
memcpy(data + len, bt_base_uuid, 12);
return len + 12;
}
data[0] = type | SDP_DSIZE_NEXT1;
if (type == SDP_DTYPE_STRING || type == SDP_DTYPE_URL) {
if (element->type & SDP_DSIZE_MASK)
for (len = 0; element->value.str[len] |
element->value.str[len + 1]; len ++);
else
len = strlen(element->value.str);
memcpy(data + 2, element->value.str, data[1] = len);
return len + 2;
}
len = 2;
element = element->value.list;
while (element->type)
len += sdp_attr_write(data + len, element ++, uuid);
data[1] = len - 2;
return len;
}
static int sdp_attributeid_compare(const struct sdp_service_attribute_s *a,
const struct sdp_service_attribute_s *b)
{
return (int) b->attribute_id - a->attribute_id;
}
static int sdp_uuid_compare(const int *a, const int *b)
{
return *a - *b;
}
static void sdp_service_record_build(struct sdp_service_record_s *record,
struct sdp_def_service_s *def, int handle)
{
int len = 0;
uint8_t *data;
int *uuid;
record->uuids = 0;
while (def->attributes[record->attributes].data.type) {
len += 3;
len += sdp_attr_max_size(&def->attributes[record->attributes ++].data,
&record->uuids);
}
record->uuids = 1 << ffs(record->uuids - 1);
record->attribute_list =
qemu_mallocz(record->attributes * sizeof(*record->attribute_list));
record->uuid =
qemu_mallocz(record->uuids * sizeof(*record->uuid));
data = qemu_malloc(len);
record->attributes = 0;
uuid = record->uuid;
while (def->attributes[record->attributes].data.type) {
record->attribute_list[record->attributes].pair = data;
len = 0;
data[len ++] = SDP_DTYPE_UINT | SDP_DSIZE_2;
data[len ++] = def->attributes[record->attributes].id >> 8;
data[len ++] = def->attributes[record->attributes].id & 0xff;
len += sdp_attr_write(data + len,
&def->attributes[record->attributes].data, &uuid);
/* Special case: assign a ServiceRecordHandle in sequence */
if (def->attributes[record->attributes].id == SDP_ATTR_RECORD_HANDLE)
def->attributes[record->attributes].data.value.uint = handle;
/* Note: we could also assign a ServiceDescription based on
* sdp->device.device->lmp_name. */
record->attribute_list[record->attributes ++].len = len;
data += len;
}
/* Sort the attribute list by the AttributeID */
qsort(record->attribute_list, record->attributes,
sizeof(*record->attribute_list),
(void *) sdp_attributeid_compare);
/* Sort the searchable UUIDs list for bisection */
qsort(record->uuid, record->uuids,
sizeof(*record->uuid),
(void *) sdp_uuid_compare);
}
static void sdp_service_db_build(struct bt_l2cap_sdp_state_s *sdp,
struct sdp_def_service_s **service)
{
sdp->services = 0;
while (service[sdp->services])
sdp->services ++;
sdp->service_list =
qemu_mallocz(sdp->services * sizeof(*sdp->service_list));
sdp->services = 0;
while (*service) {
sdp_service_record_build(&sdp->service_list[sdp->services],
*service, sdp->services);
service ++;
sdp->services ++;
}
}
#define LAST { .type = 0 }
#define SERVICE(name, attrs) \
static struct sdp_def_service_s glue(glue(sdp_service_, name), _s) = { \
.attributes = { attrs { .data = LAST } }, \
};
#define ATTRIBUTE(attrid, val) { .id = glue(SDP_ATTR_, attrid), .data = val },
#define UINT8(val) { \
.type = SDP_DTYPE_UINT | SDP_DSIZE_1, \
.value.uint = val, \
},
#define UINT16(val) { \
.type = SDP_DTYPE_UINT | SDP_DSIZE_2, \
.value.uint = val, \
},
#define UINT32(val) { \
.type = SDP_DTYPE_UINT | SDP_DSIZE_4, \
.value.uint = val, \
},
#define UUID128(val) { \
.type = SDP_DTYPE_UUID | SDP_DSIZE_16, \
.value.uint = val, \
},
#define TRUE { \
.type = SDP_DTYPE_BOOL | SDP_DSIZE_1, \
.value.uint = 1, \
},
#define FALSE { \
.type = SDP_DTYPE_BOOL | SDP_DSIZE_1, \
.value.uint = 0, \
},
#define STRING(val) { \
.type = SDP_DTYPE_STRING, \
.value.str = val, \
},
#define ARRAY(...) { \
.type = SDP_DTYPE_STRING | SDP_DSIZE_2, \
.value.str = (char []) { __VA_ARGS__, 0, 0 }, \
},
#define URL(val) { \
.type = SDP_DTYPE_URL, \
.value.str = val, \
},
#if 1
#define LIST(val) { \
.type = SDP_DTYPE_SEQ, \
.value.list = (struct sdp_def_data_element_s []) { val LAST }, \
},
#endif
/* Try to keep each single attribute below MAX_PDU_OUT_SIZE bytes
* in resulting SDP data representation size. */
SERVICE(hid,
ATTRIBUTE(RECORD_HANDLE, UINT32(0)) /* Filled in later */
ATTRIBUTE(SVCLASS_ID_LIST, LIST(UUID128(HID_SVCLASS_ID)))
ATTRIBUTE(RECORD_STATE, UINT32(1))
ATTRIBUTE(PROTO_DESC_LIST, LIST(
LIST(UUID128(L2CAP_UUID) UINT16(BT_PSM_HID_CTRL))
LIST(UUID128(HIDP_UUID))
))
ATTRIBUTE(BROWSE_GRP_LIST, LIST(UUID128(0x1002)))
ATTRIBUTE(LANG_BASE_ATTR_ID_LIST, LIST(
UINT16(0x656e) UINT16(0x006a) UINT16(0x0100)
))
ATTRIBUTE(PFILE_DESC_LIST, LIST(
LIST(UUID128(HID_PROFILE_ID) UINT16(0x0100))
))
ATTRIBUTE(DOC_URL, URL("http://bellard.org/qemu/user-doc.html"))
ATTRIBUTE(SVCNAME_PRIMARY, STRING("QEMU Bluetooth HID"))
ATTRIBUTE(SVCDESC_PRIMARY, STRING("QEMU Keyboard/Mouse"))
ATTRIBUTE(SVCPROV_PRIMARY, STRING("QEMU " QEMU_VERSION))
/* Profile specific */
ATTRIBUTE(DEVICE_RELEASE_NUMBER, UINT16(0x0091)) /* Deprecated, remove */
ATTRIBUTE(PARSER_VERSION, UINT16(0x0111))
/* TODO: extract from l2cap_device->device.class[0] */
ATTRIBUTE(DEVICE_SUBCLASS, UINT8(0x40))
ATTRIBUTE(COUNTRY_CODE, UINT8(0x15))
ATTRIBUTE(VIRTUAL_CABLE, TRUE)
ATTRIBUTE(RECONNECT_INITIATE, FALSE)
/* TODO: extract from hid->usbdev->report_desc */
ATTRIBUTE(DESCRIPTOR_LIST, LIST(
LIST(UINT8(0x22) ARRAY(
0x05, 0x01, /* Usage Page (Generic Desktop) */
0x09, 0x06, /* Usage (Keyboard) */
0xa1, 0x01, /* Collection (Application) */
0x75, 0x01, /* Report Size (1) */
0x95, 0x08, /* Report Count (8) */
0x05, 0x07, /* Usage Page (Key Codes) */
0x19, 0xe0, /* Usage Minimum (224) */
0x29, 0xe7, /* Usage Maximum (231) */
0x15, 0x00, /* Logical Minimum (0) */
0x25, 0x01, /* Logical Maximum (1) */
0x81, 0x02, /* Input (Data, Variable, Absolute) */
0x95, 0x01, /* Report Count (1) */
0x75, 0x08, /* Report Size (8) */
0x81, 0x01, /* Input (Constant) */
0x95, 0x05, /* Report Count (5) */
0x75, 0x01, /* Report Size (1) */
0x05, 0x08, /* Usage Page (LEDs) */
0x19, 0x01, /* Usage Minimum (1) */
0x29, 0x05, /* Usage Maximum (5) */
0x91, 0x02, /* Output (Data, Variable, Absolute) */
0x95, 0x01, /* Report Count (1) */
0x75, 0x03, /* Report Size (3) */
0x91, 0x01, /* Output (Constant) */
0x95, 0x06, /* Report Count (6) */
0x75, 0x08, /* Report Size (8) */
0x15, 0x00, /* Logical Minimum (0) */
0x25, 0xff, /* Logical Maximum (255) */
0x05, 0x07, /* Usage Page (Key Codes) */
0x19, 0x00, /* Usage Minimum (0) */
0x29, 0xff, /* Usage Maximum (255) */
0x81, 0x00, /* Input (Data, Array) */
0xc0 /* End Collection */
))))
ATTRIBUTE(LANG_ID_BASE_LIST, LIST(
LIST(UINT16(0x0409) UINT16(0x0100))
))
ATTRIBUTE(SDP_DISABLE, FALSE)
ATTRIBUTE(BATTERY_POWER, TRUE)
ATTRIBUTE(REMOTE_WAKEUP, TRUE)
ATTRIBUTE(BOOT_DEVICE, TRUE) /* XXX: untested */
ATTRIBUTE(SUPERVISION_TIMEOUT, UINT16(0x0c80))
ATTRIBUTE(NORMALLY_CONNECTABLE, TRUE)
ATTRIBUTE(PROFILE_VERSION, UINT16(0x0100))
)
SERVICE(sdp,
ATTRIBUTE(RECORD_HANDLE, UINT32(0)) /* Filled in later */
ATTRIBUTE(SVCLASS_ID_LIST, LIST(UUID128(SDP_SERVER_SVCLASS_ID)))
ATTRIBUTE(RECORD_STATE, UINT32(1))
ATTRIBUTE(PROTO_DESC_LIST, LIST(
LIST(UUID128(L2CAP_UUID) UINT16(BT_PSM_SDP))
LIST(UUID128(SDP_UUID))
))
ATTRIBUTE(BROWSE_GRP_LIST, LIST(UUID128(0x1002)))
ATTRIBUTE(LANG_BASE_ATTR_ID_LIST, LIST(
UINT16(0x656e) UINT16(0x006a) UINT16(0x0100)
))
ATTRIBUTE(PFILE_DESC_LIST, LIST(
LIST(UUID128(SDP_SERVER_PROFILE_ID) UINT16(0x0100))
))
ATTRIBUTE(DOC_URL, URL("http://bellard.org/qemu/user-doc.html"))
ATTRIBUTE(SVCPROV_PRIMARY, STRING("QEMU " QEMU_VERSION))
/* Profile specific */
ATTRIBUTE(VERSION_NUM_LIST, LIST(UINT16(0x0100)))
ATTRIBUTE(SVCDB_STATE , UINT32(1))
)
SERVICE(pnp,
ATTRIBUTE(RECORD_HANDLE, UINT32(0)) /* Filled in later */
ATTRIBUTE(SVCLASS_ID_LIST, LIST(UUID128(PNP_INFO_SVCLASS_ID)))
ATTRIBUTE(RECORD_STATE, UINT32(1))
ATTRIBUTE(PROTO_DESC_LIST, LIST(
LIST(UUID128(L2CAP_UUID) UINT16(BT_PSM_SDP))
LIST(UUID128(SDP_UUID))
))
ATTRIBUTE(BROWSE_GRP_LIST, LIST(UUID128(0x1002)))
ATTRIBUTE(LANG_BASE_ATTR_ID_LIST, LIST(
UINT16(0x656e) UINT16(0x006a) UINT16(0x0100)
))
ATTRIBUTE(PFILE_DESC_LIST, LIST(
LIST(UUID128(PNP_INFO_PROFILE_ID) UINT16(0x0100))
))
ATTRIBUTE(DOC_URL, URL("http://bellard.org/qemu/user-doc.html"))
ATTRIBUTE(SVCPROV_PRIMARY, STRING("QEMU " QEMU_VERSION))
/* Profile specific */
ATTRIBUTE(SPECIFICATION_ID, UINT16(0x0100))
ATTRIBUTE(VERSION, UINT16(0x0100))
ATTRIBUTE(PRIMARY_RECORD, TRUE)
)
static int bt_l2cap_sdp_new_ch(struct bt_l2cap_device_s *dev,
struct bt_l2cap_conn_params_s *params)
{
struct bt_l2cap_sdp_state_s *sdp = qemu_mallocz(sizeof(*sdp));
struct sdp_def_service_s *services[] = {
&sdp_service_sdp_s,
&sdp_service_hid_s,
&sdp_service_pnp_s,
NULL,
};
sdp->channel = params;
sdp->channel->opaque = sdp;
sdp->channel->close = bt_l2cap_sdp_close_ch;
sdp->channel->sdu_in = bt_l2cap_sdp_sdu_in;
sdp_service_db_build(sdp, services);
return 0;
}
void bt_l2cap_sdp_init(struct bt_l2cap_device_s *dev)
{
bt_l2cap_psm_register(dev, BT_PSM_SDP,
MAX_PDU_OUT_SIZE, bt_l2cap_sdp_new_ch);
}
| gpl-2.0 |
mozilla-b2g/valgrind | none/tests/s390x/tr.c | 85 | 1368 | #include<stdio.h>
#include<stdlib.h>
#include<asm/types.h>
#include<stdint.h>
#include<string.h>
#include "table.h"
uint8_t buff[40];
void tr(uint8_t *codepage, uint8_t *addr, uint64_t len)
{
asm volatile(
" larl 1,1f\n"
"1: tr 0(1,%0),0(%2)\n"
" ex %1,0(1)"
: "+&a" (addr), "+a" (len)
: "a" (codepage) : "cc", "memory", "1");
}
void run_test(void *tran_table, void *srcaddr, uint64_t len)
{
int i;
tr(tran_table, buff, len);
printf("the translated string is ");
for (i = 0; i < len; i++) {
printf("%c", buff[i]);
}
printf("\n");
}
int main()
{
/* Test 1: length = 0 */
run_test((char *)&touppercase, &buff, 0);
run_test((char *)&touppercase, &buff, 0);
/* Test 2 : length > 0 */
memset(buff, 'a', 1);
run_test((char *)&touppercase, &buff, 1);
memcpy(buff, "abcdefgh", 8);
run_test((char *)&touppercase, &buff, 3);
run_test((char *)&touppercase, &buff, 3);
run_test((char *)&touppercase, &buff, 8);
memcpy(buff, "ABCDEFGH", 8);
run_test((char *)&tolowercase, &buff, 3);
run_test((char *)&tolowercase, &buff, 3);
run_test((char *)&tolowercase, &buff, 8);
memcpy(buff, "0123456789", 9);
run_test((char *)&touppercase, &buff, 9);
run_test((char *)&tolowercase, &buff, 9);
return 0;
}
| gpl-2.0 |
shane87/linux_wx435kt-froyo | drivers/md/linear.c | 341 | 9552 | /*
linear.c : Multiple Devices driver for Linux
Copyright (C) 1994-96 Marc ZYNGIER
<zyngier@ufr-info-p7.ibp.fr> or
<maz@gloups.fdn.fr>
Linear mode management functions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
You should have received a copy of the GNU General Public License
(for example /usr/src/linux/COPYING); if not, write to the Free
Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/blkdev.h>
#include <linux/raid/md_u.h>
#include <linux/seq_file.h>
#include "md.h"
#include "linear.h"
/*
* find which device holds a particular offset
*/
static inline dev_info_t *which_dev(mddev_t *mddev, sector_t sector)
{
int lo, mid, hi;
linear_conf_t *conf;
lo = 0;
hi = mddev->raid_disks - 1;
conf = rcu_dereference(mddev->private);
/*
* Binary Search
*/
while (hi > lo) {
mid = (hi + lo) / 2;
if (sector < conf->disks[mid].end_sector)
hi = mid;
else
lo = mid + 1;
}
return conf->disks + lo;
}
/**
* linear_mergeable_bvec -- tell bio layer if two requests can be merged
* @q: request queue
* @bvm: properties of new bio
* @biovec: the request that could be merged to it.
*
* Return amount of bytes we can take at this offset
*/
static int linear_mergeable_bvec(struct request_queue *q,
struct bvec_merge_data *bvm,
struct bio_vec *biovec)
{
mddev_t *mddev = q->queuedata;
dev_info_t *dev0;
unsigned long maxsectors, bio_sectors = bvm->bi_size >> 9;
sector_t sector = bvm->bi_sector + get_start_sect(bvm->bi_bdev);
rcu_read_lock();
dev0 = which_dev(mddev, sector);
maxsectors = dev0->end_sector - sector;
rcu_read_unlock();
if (maxsectors < bio_sectors)
maxsectors = 0;
else
maxsectors -= bio_sectors;
if (maxsectors <= (PAGE_SIZE >> 9 ) && bio_sectors == 0)
return biovec->bv_len;
/* The bytes available at this offset could be really big,
* so we cap at 2^31 to avoid overflow */
if (maxsectors > (1 << (31-9)))
return 1<<31;
return maxsectors << 9;
}
static void linear_unplug(struct request_queue *q)
{
mddev_t *mddev = q->queuedata;
linear_conf_t *conf;
int i;
rcu_read_lock();
conf = rcu_dereference(mddev->private);
for (i=0; i < mddev->raid_disks; i++) {
struct request_queue *r_queue = bdev_get_queue(conf->disks[i].rdev->bdev);
blk_unplug(r_queue);
}
rcu_read_unlock();
}
static int linear_congested(void *data, int bits)
{
mddev_t *mddev = data;
linear_conf_t *conf;
int i, ret = 0;
if (mddev_congested(mddev, bits))
return 1;
rcu_read_lock();
conf = rcu_dereference(mddev->private);
for (i = 0; i < mddev->raid_disks && !ret ; i++) {
struct request_queue *q = bdev_get_queue(conf->disks[i].rdev->bdev);
ret |= bdi_congested(&q->backing_dev_info, bits);
}
rcu_read_unlock();
return ret;
}
static sector_t linear_size(mddev_t *mddev, sector_t sectors, int raid_disks)
{
linear_conf_t *conf;
sector_t array_sectors;
rcu_read_lock();
conf = rcu_dereference(mddev->private);
WARN_ONCE(sectors || raid_disks,
"%s does not support generic reshape\n", __func__);
array_sectors = conf->array_sectors;
rcu_read_unlock();
return array_sectors;
}
static linear_conf_t *linear_conf(mddev_t *mddev, int raid_disks)
{
linear_conf_t *conf;
mdk_rdev_t *rdev;
int i, cnt;
conf = kzalloc (sizeof (*conf) + raid_disks*sizeof(dev_info_t),
GFP_KERNEL);
if (!conf)
return NULL;
cnt = 0;
conf->array_sectors = 0;
list_for_each_entry(rdev, &mddev->disks, same_set) {
int j = rdev->raid_disk;
dev_info_t *disk = conf->disks + j;
sector_t sectors;
if (j < 0 || j >= raid_disks || disk->rdev) {
printk("linear: disk numbering problem. Aborting!\n");
goto out;
}
disk->rdev = rdev;
if (mddev->chunk_sectors) {
sectors = rdev->sectors;
sector_div(sectors, mddev->chunk_sectors);
rdev->sectors = sectors * mddev->chunk_sectors;
}
disk_stack_limits(mddev->gendisk, rdev->bdev,
rdev->data_offset << 9);
/* as we don't honour merge_bvec_fn, we must never risk
* violating it, so limit ->max_sector to one PAGE, as
* a one page request is never in violation.
*/
if (rdev->bdev->bd_disk->queue->merge_bvec_fn &&
queue_max_sectors(mddev->queue) > (PAGE_SIZE>>9))
blk_queue_max_sectors(mddev->queue, PAGE_SIZE>>9);
conf->array_sectors += rdev->sectors;
cnt++;
}
if (cnt != raid_disks) {
printk("linear: not enough drives present. Aborting!\n");
goto out;
}
/*
* Here we calculate the device offsets.
*/
conf->disks[0].end_sector = conf->disks[0].rdev->sectors;
for (i = 1; i < raid_disks; i++)
conf->disks[i].end_sector =
conf->disks[i-1].end_sector +
conf->disks[i].rdev->sectors;
return conf;
out:
kfree(conf);
return NULL;
}
static int linear_run (mddev_t *mddev)
{
linear_conf_t *conf;
if (md_check_no_bitmap(mddev))
return -EINVAL;
mddev->queue->queue_lock = &mddev->queue->__queue_lock;
conf = linear_conf(mddev, mddev->raid_disks);
if (!conf)
return 1;
mddev->private = conf;
md_set_array_sectors(mddev, linear_size(mddev, 0, 0));
blk_queue_merge_bvec(mddev->queue, linear_mergeable_bvec);
mddev->queue->unplug_fn = linear_unplug;
mddev->queue->backing_dev_info.congested_fn = linear_congested;
mddev->queue->backing_dev_info.congested_data = mddev;
md_integrity_register(mddev);
return 0;
}
static void free_conf(struct rcu_head *head)
{
linear_conf_t *conf = container_of(head, linear_conf_t, rcu);
kfree(conf);
}
static int linear_add(mddev_t *mddev, mdk_rdev_t *rdev)
{
/* Adding a drive to a linear array allows the array to grow.
* It is permitted if the new drive has a matching superblock
* already on it, with raid_disk equal to raid_disks.
* It is achieved by creating a new linear_private_data structure
* and swapping it in in-place of the current one.
* The current one is never freed until the array is stopped.
* This avoids races.
*/
linear_conf_t *newconf, *oldconf;
if (rdev->saved_raid_disk != mddev->raid_disks)
return -EINVAL;
rdev->raid_disk = rdev->saved_raid_disk;
newconf = linear_conf(mddev,mddev->raid_disks+1);
if (!newconf)
return -ENOMEM;
oldconf = rcu_dereference(mddev->private);
mddev->raid_disks++;
rcu_assign_pointer(mddev->private, newconf);
md_set_array_sectors(mddev, linear_size(mddev, 0, 0));
set_capacity(mddev->gendisk, mddev->array_sectors);
revalidate_disk(mddev->gendisk);
call_rcu(&oldconf->rcu, free_conf);
return 0;
}
static int linear_stop (mddev_t *mddev)
{
linear_conf_t *conf = mddev->private;
/*
* We do not require rcu protection here since
* we hold reconfig_mutex for both linear_add and
* linear_stop, so they cannot race.
* We should make sure any old 'conf's are properly
* freed though.
*/
rcu_barrier();
blk_sync_queue(mddev->queue); /* the unplug fn references 'conf'*/
kfree(conf);
return 0;
}
static int linear_make_request (struct request_queue *q, struct bio *bio)
{
const int rw = bio_data_dir(bio);
mddev_t *mddev = q->queuedata;
dev_info_t *tmp_dev;
sector_t start_sector;
int cpu;
if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) {
bio_endio(bio, -EOPNOTSUPP);
return 0;
}
cpu = part_stat_lock();
part_stat_inc(cpu, &mddev->gendisk->part0, ios[rw]);
part_stat_add(cpu, &mddev->gendisk->part0, sectors[rw],
bio_sectors(bio));
part_stat_unlock();
rcu_read_lock();
tmp_dev = which_dev(mddev, bio->bi_sector);
start_sector = tmp_dev->end_sector - tmp_dev->rdev->sectors;
if (unlikely(bio->bi_sector >= (tmp_dev->end_sector)
|| (bio->bi_sector < start_sector))) {
char b[BDEVNAME_SIZE];
printk("linear_make_request: Sector %llu out of bounds on "
"dev %s: %llu sectors, offset %llu\n",
(unsigned long long)bio->bi_sector,
bdevname(tmp_dev->rdev->bdev, b),
(unsigned long long)tmp_dev->rdev->sectors,
(unsigned long long)start_sector);
rcu_read_unlock();
bio_io_error(bio);
return 0;
}
if (unlikely(bio->bi_sector + (bio->bi_size >> 9) >
tmp_dev->end_sector)) {
/* This bio crosses a device boundary, so we have to
* split it.
*/
struct bio_pair *bp;
sector_t end_sector = tmp_dev->end_sector;
rcu_read_unlock();
bp = bio_split(bio, end_sector - bio->bi_sector);
if (linear_make_request(q, &bp->bio1))
generic_make_request(&bp->bio1);
if (linear_make_request(q, &bp->bio2))
generic_make_request(&bp->bio2);
bio_pair_release(bp);
return 0;
}
bio->bi_bdev = tmp_dev->rdev->bdev;
bio->bi_sector = bio->bi_sector - start_sector
+ tmp_dev->rdev->data_offset;
rcu_read_unlock();
return 1;
}
static void linear_status (struct seq_file *seq, mddev_t *mddev)
{
seq_printf(seq, " %dk rounding", mddev->chunk_sectors / 2);
}
static struct mdk_personality linear_personality =
{
.name = "linear",
.level = LEVEL_LINEAR,
.owner = THIS_MODULE,
.make_request = linear_make_request,
.run = linear_run,
.stop = linear_stop,
.status = linear_status,
.hot_add_disk = linear_add,
.size = linear_size,
};
static int __init linear_init (void)
{
return register_md_personality (&linear_personality);
}
static void linear_exit (void)
{
unregister_md_personality (&linear_personality);
}
module_init(linear_init);
module_exit(linear_exit);
MODULE_LICENSE("GPL");
MODULE_ALIAS("md-personality-1"); /* LINEAR - deprecated*/
MODULE_ALIAS("md-linear");
MODULE_ALIAS("md-level--1");
| gpl-2.0 |
y10g/lge-kernel-startablet-l06c | drivers/gpu/drm/nouveau/nv50_fbcon.c | 853 | 6784 | #include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_fbcon.h"
void
nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct nouveau_fbdev *nfbdev = info->par;
struct drm_device *dev = nfbdev->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *chan = dev_priv->channel;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
nouveau_fbcon_gpu_lockup(info);
}
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, rect);
return;
}
if (rect->rop != ROP_COPY) {
BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
OUT_RING(chan, 1);
}
BEGIN_RING(chan, NvSub2D, 0x0588, 1);
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR)
OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
else
OUT_RING(chan, rect->color);
BEGIN_RING(chan, NvSub2D, 0x0600, 4);
OUT_RING(chan, rect->dx);
OUT_RING(chan, rect->dy);
OUT_RING(chan, rect->dx + rect->width);
OUT_RING(chan, rect->dy + rect->height);
if (rect->rop != ROP_COPY) {
BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
OUT_RING(chan, 3);
}
FIRE_RING(chan);
}
void
nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct nouveau_fbdev *nfbdev = info->par;
struct drm_device *dev = nfbdev->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *chan = dev_priv->channel;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
nouveau_fbcon_gpu_lockup(info);
}
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, region);
return;
}
BEGIN_RING(chan, NvSub2D, 0x0110, 1);
OUT_RING(chan, 0);
BEGIN_RING(chan, NvSub2D, 0x08b0, 4);
OUT_RING(chan, region->dx);
OUT_RING(chan, region->dy);
OUT_RING(chan, region->width);
OUT_RING(chan, region->height);
BEGIN_RING(chan, NvSub2D, 0x08d0, 4);
OUT_RING(chan, 0);
OUT_RING(chan, region->sx);
OUT_RING(chan, 0);
OUT_RING(chan, region->sy);
FIRE_RING(chan);
}
void
nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct nouveau_fbdev *nfbdev = info->par;
struct drm_device *dev = nfbdev->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *chan = dev_priv->channel;
uint32_t width, dwords, *data = (uint32_t *)image->data;
uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
uint32_t *palette = info->pseudo_palette;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (image->depth != 1) {
cfb_imageblit(info, image);
return;
}
if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
nouveau_fbcon_gpu_lockup(info);
}
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_imageblit(info, image);
return;
}
width = ALIGN(image->width, 32);
dwords = (width * image->height) >> 5;
BEGIN_RING(chan, NvSub2D, 0x0814, 2);
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
OUT_RING(chan, palette[image->bg_color] | mask);
OUT_RING(chan, palette[image->fg_color] | mask);
} else {
OUT_RING(chan, image->bg_color);
OUT_RING(chan, image->fg_color);
}
BEGIN_RING(chan, NvSub2D, 0x0838, 2);
OUT_RING(chan, image->width);
OUT_RING(chan, image->height);
BEGIN_RING(chan, NvSub2D, 0x0850, 4);
OUT_RING(chan, 0);
OUT_RING(chan, image->dx);
OUT_RING(chan, 0);
OUT_RING(chan, image->dy);
while (dwords) {
int push = dwords > 2047 ? 2047 : dwords;
if (RING_SPACE(chan, push + 1)) {
nouveau_fbcon_gpu_lockup(info);
cfb_imageblit(info, image);
return;
}
dwords -= push;
BEGIN_RING(chan, NvSub2D, 0x40000860, push);
OUT_RINGp(chan, data, push);
data += push;
}
FIRE_RING(chan);
}
int
nv50_fbcon_accel_init(struct fb_info *info)
{
struct nouveau_fbdev *nfbdev = info->par;
struct drm_device *dev = nfbdev->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *chan = dev_priv->channel;
struct nouveau_gpuobj *eng2d = NULL;
uint64_t fb;
int ret, format;
fb = info->fix.smem_start - dev_priv->fb_phys + dev_priv->vm_vram_base;
switch (info->var.bits_per_pixel) {
case 8:
format = 0xf3;
break;
case 15:
format = 0xf8;
break;
case 16:
format = 0xe8;
break;
case 32:
switch (info->var.transp.length) {
case 0: /* depth 24 */
case 8: /* depth 32, just use 24.. */
format = 0xe6;
break;
case 2: /* depth 30 */
format = 0xd1;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
ret = nouveau_gpuobj_gr_new(dev_priv->channel, 0x502d, &eng2d);
if (ret)
return ret;
ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, Nv2D, eng2d, NULL);
if (ret)
return ret;
ret = RING_SPACE(chan, 59);
if (ret) {
nouveau_fbcon_gpu_lockup(info);
return ret;
}
BEGIN_RING(chan, NvSub2D, 0x0000, 1);
OUT_RING(chan, Nv2D);
BEGIN_RING(chan, NvSub2D, 0x0180, 4);
OUT_RING(chan, NvNotify0);
OUT_RING(chan, chan->vram_handle);
OUT_RING(chan, chan->vram_handle);
OUT_RING(chan, chan->vram_handle);
BEGIN_RING(chan, NvSub2D, 0x0290, 1);
OUT_RING(chan, 0);
BEGIN_RING(chan, NvSub2D, 0x0888, 1);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
OUT_RING(chan, 3);
BEGIN_RING(chan, NvSub2D, 0x02a0, 1);
OUT_RING(chan, 0x55);
BEGIN_RING(chan, NvSub2D, 0x08c0, 4);
OUT_RING(chan, 0);
OUT_RING(chan, 1);
OUT_RING(chan, 0);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0580, 2);
OUT_RING(chan, 4);
OUT_RING(chan, format);
BEGIN_RING(chan, NvSub2D, 0x02e8, 2);
OUT_RING(chan, 2);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0804, 1);
OUT_RING(chan, format);
BEGIN_RING(chan, NvSub2D, 0x0800, 1);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0808, 3);
OUT_RING(chan, 0);
OUT_RING(chan, 0);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x081c, 1);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0840, 4);
OUT_RING(chan, 0);
OUT_RING(chan, 1);
OUT_RING(chan, 0);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0200, 2);
OUT_RING(chan, format);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0214, 5);
OUT_RING(chan, info->fix.line_length);
OUT_RING(chan, info->var.xres_virtual);
OUT_RING(chan, info->var.yres_virtual);
OUT_RING(chan, upper_32_bits(fb));
OUT_RING(chan, lower_32_bits(fb));
BEGIN_RING(chan, NvSub2D, 0x0230, 2);
OUT_RING(chan, format);
OUT_RING(chan, 1);
BEGIN_RING(chan, NvSub2D, 0x0244, 5);
OUT_RING(chan, info->fix.line_length);
OUT_RING(chan, info->var.xres_virtual);
OUT_RING(chan, info->var.yres_virtual);
OUT_RING(chan, upper_32_bits(fb));
OUT_RING(chan, lower_32_bits(fb));
return 0;
}
| gpl-2.0 |
stargo/android_kernel_amazon_ford | drivers/ata/sata_sil.c | 1365 | 22375 | /*
* sata_sil.c - Silicon Image SATA
*
* Maintained by: Tejun Heo <tj@kernel.org>
* Please ALWAYS copy linux-ide@vger.kernel.org
* on emails.
*
* Copyright 2003-2005 Red Hat, Inc.
* Copyright 2003 Benjamin Herrenschmidt
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* libata documentation is available via 'make {ps|pdf}docs',
* as Documentation/DocBook/libata.*
*
* Documentation for SiI 3112:
* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
*
* Other errata and documentation available under NDA.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/dmi.h>
#define DRV_NAME "sata_sil"
#define DRV_VERSION "2.4"
#define SIL_DMA_BOUNDARY 0x7fffffffUL
enum {
SIL_MMIO_BAR = 5,
/*
* host flags
*/
SIL_FLAG_NO_SATA_IRQ = (1 << 28),
SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
SIL_FLAG_MOD15WRITE = (1 << 30),
SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA,
/*
* Controller IDs
*/
sil_3112 = 0,
sil_3112_no_sata_irq = 1,
sil_3512 = 2,
sil_3114 = 3,
/*
* Register offsets
*/
SIL_SYSCFG = 0x48,
/*
* Register bits
*/
/* SYSCFG */
SIL_MASK_IDE0_INT = (1 << 22),
SIL_MASK_IDE1_INT = (1 << 23),
SIL_MASK_IDE2_INT = (1 << 24),
SIL_MASK_IDE3_INT = (1 << 25),
SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
SIL_MASK_4PORT = SIL_MASK_2PORT |
SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
/* BMDMA/BMDMA2 */
SIL_INTR_STEERING = (1 << 1),
SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
/* SIEN */
SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
/*
* Others
*/
SIL_QUIRK_MOD15WRITE = (1 << 0),
SIL_QUIRK_UDMA5MAX = (1 << 1),
};
static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
#ifdef CONFIG_PM
static int sil_pci_device_resume(struct pci_dev *pdev);
#endif
static void sil_dev_config(struct ata_device *dev);
static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
static void sil_qc_prep(struct ata_queued_cmd *qc);
static void sil_bmdma_setup(struct ata_queued_cmd *qc);
static void sil_bmdma_start(struct ata_queued_cmd *qc);
static void sil_bmdma_stop(struct ata_queued_cmd *qc);
static void sil_freeze(struct ata_port *ap);
static void sil_thaw(struct ata_port *ap);
static const struct pci_device_id sil_pci_tbl[] = {
{ PCI_VDEVICE(CMD, 0x3112), sil_3112 },
{ PCI_VDEVICE(CMD, 0x0240), sil_3112 },
{ PCI_VDEVICE(CMD, 0x3512), sil_3512 },
{ PCI_VDEVICE(CMD, 0x3114), sil_3114 },
{ PCI_VDEVICE(ATI, 0x436e), sil_3112 },
{ PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
{ PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
{ } /* terminate list */
};
/* TODO firmware versions should be added - eric */
static const struct sil_drivelist {
const char *product;
unsigned int quirk;
} sil_blacklist [] = {
{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
{ "TOSHIBA MK2561GSYN", SIL_QUIRK_MOD15WRITE },
{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
{ }
};
static struct pci_driver sil_pci_driver = {
.name = DRV_NAME,
.id_table = sil_pci_tbl,
.probe = sil_init_one,
.remove = ata_pci_remove_one,
#ifdef CONFIG_PM
.suspend = ata_pci_device_suspend,
.resume = sil_pci_device_resume,
#endif
};
static struct scsi_host_template sil_sht = {
ATA_BASE_SHT(DRV_NAME),
/** These controllers support Large Block Transfer which allows
transfer chunks up to 2GB and which cross 64KB boundaries,
therefore the DMA limits are more relaxed than standard ATA SFF. */
.dma_boundary = SIL_DMA_BOUNDARY,
.sg_tablesize = ATA_MAX_PRD
};
static struct ata_port_operations sil_ops = {
.inherits = &ata_bmdma32_port_ops,
.dev_config = sil_dev_config,
.set_mode = sil_set_mode,
.bmdma_setup = sil_bmdma_setup,
.bmdma_start = sil_bmdma_start,
.bmdma_stop = sil_bmdma_stop,
.qc_prep = sil_qc_prep,
.freeze = sil_freeze,
.thaw = sil_thaw,
.scr_read = sil_scr_read,
.scr_write = sil_scr_write,
};
static const struct ata_port_info sil_port_info[] = {
/* sil_3112 */
{
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5,
.port_ops = &sil_ops,
},
/* sil_3112_no_sata_irq */
{
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
SIL_FLAG_NO_SATA_IRQ,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5,
.port_ops = &sil_ops,
},
/* sil_3512 */
{
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5,
.port_ops = &sil_ops,
},
/* sil_3114 */
{
.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5,
.port_ops = &sil_ops,
},
};
/* per-port register offsets */
/* TODO: we can probably calculate rather than use a table */
static const struct {
unsigned long tf; /* ATA taskfile register block */
unsigned long ctl; /* ATA control/altstatus register block */
unsigned long bmdma; /* DMA register block */
unsigned long bmdma2; /* DMA register block #2 */
unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
unsigned long scr; /* SATA control register block */
unsigned long sien; /* SATA Interrupt Enable register */
unsigned long xfer_mode;/* data transfer mode register */
unsigned long sfis_cfg; /* SATA FIS reception config register */
} sil_port[] = {
/* port 0 ... */
/* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
{ 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
{ 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
{ 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
{ 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
/* ... port 3 */
};
MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
MODULE_VERSION(DRV_VERSION);
static int slow_down;
module_param(slow_down, int, 0444);
MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
static void sil_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
/* clear start/stop bit - can safely always write 0 */
iowrite8(0, bmdma2);
/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
ata_sff_dma_pause(ap);
}
static void sil_bmdma_setup(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
void __iomem *bmdma = ap->ioaddr.bmdma_addr;
/* load PRD table addr. */
iowrite32(ap->bmdma_prd_dma, bmdma + ATA_DMA_TABLE_OFS);
/* issue r/w command */
ap->ops->sff_exec_command(ap, &qc->tf);
}
static void sil_bmdma_start(struct ata_queued_cmd *qc)
{
unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
struct ata_port *ap = qc->ap;
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
u8 dmactl = ATA_DMA_START;
/* set transfer direction, start host DMA transaction
Note: For Large Block Transfer to work, the DMA must be started
using the bmdma2 register. */
if (!rw)
dmactl |= ATA_DMA_WR;
iowrite8(dmactl, bmdma2);
}
/* The way God intended PCI IDE scatter/gather lists to look and behave... */
static void sil_fill_sg(struct ata_queued_cmd *qc)
{
struct scatterlist *sg;
struct ata_port *ap = qc->ap;
struct ata_bmdma_prd *prd, *last_prd = NULL;
unsigned int si;
prd = &ap->bmdma_prd[0];
for_each_sg(qc->sg, sg, qc->n_elem, si) {
/* Note h/w doesn't support 64-bit, so we unconditionally
* truncate dma_addr_t to u32.
*/
u32 addr = (u32) sg_dma_address(sg);
u32 sg_len = sg_dma_len(sg);
prd->addr = cpu_to_le32(addr);
prd->flags_len = cpu_to_le32(sg_len);
VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
last_prd = prd;
prd++;
}
if (likely(last_prd))
last_prd->flags_len |= cpu_to_le32(ATA_PRD_EOT);
}
static void sil_qc_prep(struct ata_queued_cmd *qc)
{
if (!(qc->flags & ATA_QCFLAG_DMAMAP))
return;
sil_fill_sg(qc);
}
static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
{
u8 cache_line = 0;
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
return cache_line;
}
/**
* sil_set_mode - wrap set_mode functions
* @link: link to set up
* @r_failed: returned device when we fail
*
* Wrap the libata method for device setup as after the setup we need
* to inspect the results and do some configuration work
*/
static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
{
struct ata_port *ap = link->ap;
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
struct ata_device *dev;
u32 tmp, dev_mode[2] = { };
int rc;
rc = ata_do_set_mode(link, r_failed);
if (rc)
return rc;
ata_for_each_dev(dev, link, ALL) {
if (!ata_dev_enabled(dev))
dev_mode[dev->devno] = 0; /* PIO0/1/2 */
else if (dev->flags & ATA_DFLAG_PIO)
dev_mode[dev->devno] = 1; /* PIO3/4 */
else
dev_mode[dev->devno] = 3; /* UDMA */
/* value 2 indicates MDMA */
}
tmp = readl(addr);
tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
tmp |= dev_mode[0];
tmp |= (dev_mode[1] << 4);
writel(tmp, addr);
readl(addr); /* flush */
return 0;
}
static inline void __iomem *sil_scr_addr(struct ata_port *ap,
unsigned int sc_reg)
{
void __iomem *offset = ap->ioaddr.scr_addr;
switch (sc_reg) {
case SCR_STATUS:
return offset + 4;
case SCR_ERROR:
return offset + 8;
case SCR_CONTROL:
return offset;
default:
/* do nothing */
break;
}
return NULL;
}
static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
{
void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
if (mmio) {
*val = readl(mmio);
return 0;
}
return -EINVAL;
}
static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
if (mmio) {
writel(val, mmio);
return 0;
}
return -EINVAL;
}
static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
{
struct ata_eh_info *ehi = &ap->link.eh_info;
struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
u8 status;
if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
u32 serror = 0xffffffff;
/* SIEN doesn't mask SATA IRQs on some 3112s. Those
* controllers continue to assert IRQ as long as
* SError bits are pending. Clear SError immediately.
*/
sil_scr_read(&ap->link, SCR_ERROR, &serror);
sil_scr_write(&ap->link, SCR_ERROR, serror);
/* Sometimes spurious interrupts occur, double check
* it's PHYRDY CHG.
*/
if (serror & SERR_PHYRDY_CHG) {
ap->link.eh_info.serror |= serror;
goto freeze;
}
if (!(bmdma2 & SIL_DMA_COMPLETE))
return;
}
if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
/* this sometimes happens, just clear IRQ */
ap->ops->sff_check_status(ap);
return;
}
/* Check whether we are expecting interrupt in this state */
switch (ap->hsm_task_state) {
case HSM_ST_FIRST:
/* Some pre-ATAPI-4 devices assert INTRQ
* at this state when ready to receive CDB.
*/
/* Check the ATA_DFLAG_CDB_INTR flag is enough here.
* The flag was turned on only for atapi devices. No
* need to check ata_is_atapi(qc->tf.protocol) again.
*/
if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
goto err_hsm;
break;
case HSM_ST_LAST:
if (ata_is_dma(qc->tf.protocol)) {
/* clear DMA-Start bit */
ap->ops->bmdma_stop(qc);
if (bmdma2 & SIL_DMA_ERROR) {
qc->err_mask |= AC_ERR_HOST_BUS;
ap->hsm_task_state = HSM_ST_ERR;
}
}
break;
case HSM_ST:
break;
default:
goto err_hsm;
}
/* check main status, clearing INTRQ */
status = ap->ops->sff_check_status(ap);
if (unlikely(status & ATA_BUSY))
goto err_hsm;
/* ack bmdma irq events */
ata_bmdma_irq_clear(ap);
/* kick HSM in the ass */
ata_sff_hsm_move(ap, qc, status, 0);
if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
return;
err_hsm:
qc->err_mask |= AC_ERR_HSM;
freeze:
ata_port_freeze(ap);
}
static irqreturn_t sil_interrupt(int irq, void *dev_instance)
{
struct ata_host *host = dev_instance;
void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
int handled = 0;
int i;
spin_lock(&host->lock);
for (i = 0; i < host->n_ports; i++) {
struct ata_port *ap = host->ports[i];
u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
/* turn off SATA_IRQ if not supported */
if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
bmdma2 &= ~SIL_DMA_SATA_IRQ;
if (bmdma2 == 0xffffffff ||
!(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
continue;
sil_host_intr(ap, bmdma2);
handled = 1;
}
spin_unlock(&host->lock);
return IRQ_RETVAL(handled);
}
static void sil_freeze(struct ata_port *ap)
{
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
u32 tmp;
/* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
writel(0, mmio_base + sil_port[ap->port_no].sien);
/* plug IRQ */
tmp = readl(mmio_base + SIL_SYSCFG);
tmp |= SIL_MASK_IDE0_INT << ap->port_no;
writel(tmp, mmio_base + SIL_SYSCFG);
readl(mmio_base + SIL_SYSCFG); /* flush */
/* Ensure DMA_ENABLE is off.
*
* This is because the controller will not give us access to the
* taskfile registers while a DMA is in progress
*/
iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
ap->ioaddr.bmdma_addr);
/* According to ata_bmdma_stop, an HDMA transition requires
* on PIO cycle. But we can't read a taskfile register.
*/
ioread8(ap->ioaddr.bmdma_addr);
}
static void sil_thaw(struct ata_port *ap)
{
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
u32 tmp;
/* clear IRQ */
ap->ops->sff_check_status(ap);
ata_bmdma_irq_clear(ap);
/* turn on SATA IRQ if supported */
if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
/* turn on IRQ */
tmp = readl(mmio_base + SIL_SYSCFG);
tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
writel(tmp, mmio_base + SIL_SYSCFG);
}
/**
* sil_dev_config - Apply device/host-specific errata fixups
* @dev: Device to be examined
*
* After the IDENTIFY [PACKET] DEVICE step is complete, and a
* device is known to be present, this function is called.
* We apply two errata fixups which are specific to Silicon Image,
* a Seagate and a Maxtor fixup.
*
* For certain Seagate devices, we must limit the maximum sectors
* to under 8K.
*
* For certain Maxtor devices, we must not program the drive
* beyond udma5.
*
* Both fixups are unfairly pessimistic. As soon as I get more
* information on these errata, I will create a more exhaustive
* list, and apply the fixups to only the specific
* devices/hosts/firmwares that need it.
*
* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
* The Maxtor quirk is in the blacklist, but I'm keeping the original
* pessimistic fix for the following reasons...
* - There seems to be less info on it, only one device gleaned off the
* Windows driver, maybe only one is affected. More info would be greatly
* appreciated.
* - But then again UDMA5 is hardly anything to complain about
*/
static void sil_dev_config(struct ata_device *dev)
{
struct ata_port *ap = dev->link->ap;
int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
unsigned int n, quirks = 0;
unsigned char model_num[ATA_ID_PROD_LEN + 1];
ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
for (n = 0; sil_blacklist[n].product; n++)
if (!strcmp(sil_blacklist[n].product, model_num)) {
quirks = sil_blacklist[n].quirk;
break;
}
/* limit requests to 15 sectors */
if (slow_down ||
((ap->flags & SIL_FLAG_MOD15WRITE) &&
(quirks & SIL_QUIRK_MOD15WRITE))) {
if (print_info)
ata_dev_info(dev,
"applying Seagate errata fix (mod15write workaround)\n");
dev->max_sectors = 15;
return;
}
/* limit to udma5 */
if (quirks & SIL_QUIRK_UDMA5MAX) {
if (print_info)
ata_dev_info(dev, "applying Maxtor errata fix %s\n",
model_num);
dev->udma_mask &= ATA_UDMA5;
return;
}
}
static void sil_init_controller(struct ata_host *host)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
u8 cls;
u32 tmp;
int i;
/* Initialize FIFO PCI bus arbitration */
cls = sil_get_device_cache_line(pdev);
if (cls) {
cls >>= 3;
cls++; /* cls = (line_size/8)+1 */
for (i = 0; i < host->n_ports; i++)
writew(cls << 8 | cls,
mmio_base + sil_port[i].fifo_cfg);
} else
dev_warn(&pdev->dev,
"cache line size not set. Driver may not function\n");
/* Apply R_ERR on DMA activate FIS errata workaround */
if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
int cnt;
for (i = 0, cnt = 0; i < host->n_ports; i++) {
tmp = readl(mmio_base + sil_port[i].sfis_cfg);
if ((tmp & 0x3) != 0x01)
continue;
if (!cnt)
dev_info(&pdev->dev,
"Applying R_ERR on DMA activate FIS errata fix\n");
writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
cnt++;
}
}
if (host->n_ports == 4) {
/* flip the magic "make 4 ports work" bit */
tmp = readl(mmio_base + sil_port[2].bmdma);
if ((tmp & SIL_INTR_STEERING) == 0)
writel(tmp | SIL_INTR_STEERING,
mmio_base + sil_port[2].bmdma);
}
}
static bool sil_broken_system_poweroff(struct pci_dev *pdev)
{
static const struct dmi_system_id broken_systems[] = {
{
.ident = "HP Compaq nx6325",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
},
/* PCI slot number of the controller */
.driver_data = (void *)0x12UL,
},
{ } /* terminate list */
};
const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
if (dmi) {
unsigned long slot = (unsigned long)dmi->driver_data;
/* apply the quirk only to on-board controllers */
return slot == PCI_SLOT(pdev->devfn);
}
return false;
}
static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int board_id = ent->driver_data;
struct ata_port_info pi = sil_port_info[board_id];
const struct ata_port_info *ppi[] = { &pi, NULL };
struct ata_host *host;
void __iomem *mmio_base;
int n_ports, rc;
unsigned int i;
ata_print_version_once(&pdev->dev, DRV_VERSION);
/* allocate host */
n_ports = 2;
if (board_id == sil_3114)
n_ports = 4;
if (sil_broken_system_poweroff(pdev)) {
pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN |
ATA_FLAG_NO_HIBERNATE_SPINDOWN;
dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
"on poweroff and hibernation\n");
}
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
if (!host)
return -ENOMEM;
/* acquire resources and fill host */
rc = pcim_enable_device(pdev);
if (rc)
return rc;
rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
if (rc == -EBUSY)
pcim_pin_device(pdev);
if (rc)
return rc;
host->iomap = pcim_iomap_table(pdev);
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
if (rc)
return rc;
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
if (rc)
return rc;
mmio_base = host->iomap[SIL_MMIO_BAR];
for (i = 0; i < host->n_ports; i++) {
struct ata_port *ap = host->ports[i];
struct ata_ioports *ioaddr = &ap->ioaddr;
ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
ioaddr->altstatus_addr =
ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
ioaddr->scr_addr = mmio_base + sil_port[i].scr;
ata_sff_std_ports(ioaddr);
ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
}
/* initialize and activate */
sil_init_controller(host);
pci_set_master(pdev);
return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
&sil_sht);
}
#ifdef CONFIG_PM
static int sil_pci_device_resume(struct pci_dev *pdev)
{
struct ata_host *host = dev_get_drvdata(&pdev->dev);
int rc;
rc = ata_pci_device_do_resume(pdev);
if (rc)
return rc;
sil_init_controller(host);
ata_host_resume(host);
return 0;
}
#endif
module_pci_driver(sil_pci_driver);
| gpl-2.0 |
olegsvs/android_kernel_archos_persimmon_3_18 | drivers/usb/atm/cxacru.c | 1365 | 40276 | /******************************************************************************
* cxacru.c - driver for USB ADSL modems based on
* Conexant AccessRunner chipset
*
* Copyright (C) 2004 David Woodhouse, Duncan Sands, Roman Kagan
* Copyright (C) 2005 Duncan Sands, Roman Kagan (rkagan % mail ! ru)
* Copyright (C) 2007 Simon Arlott
* Copyright (C) 2009 Simon Arlott
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
******************************************************************************/
/*
* Credit is due for Josep Comas, who created the original patch to speedtch.c
* to support the different padding used by the AccessRunner (now generalized
* into usbatm), and the userspace firmware loading utility.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/mutex.h>
#include <asm/unaligned.h>
#include "usbatm.h"
#define DRIVER_AUTHOR "Roman Kagan, David Woodhouse, Duncan Sands, Simon Arlott"
#define DRIVER_VERSION "0.4"
#define DRIVER_DESC "Conexant AccessRunner ADSL USB modem driver"
static const char cxacru_driver_name[] = "cxacru";
#define CXACRU_EP_CMD 0x01 /* Bulk/interrupt in/out */
#define CXACRU_EP_DATA 0x02 /* Bulk in/out */
#define CMD_PACKET_SIZE 64 /* Should be maxpacket(ep)? */
#define CMD_MAX_CONFIG ((CMD_PACKET_SIZE / 4 - 1) / 2)
/* Addresses */
#define PLLFCLK_ADDR 0x00350068
#define PLLBCLK_ADDR 0x0035006c
#define SDRAMEN_ADDR 0x00350010
#define FW_ADDR 0x00801000
#define BR_ADDR 0x00180600
#define SIG_ADDR 0x00180500
#define BR_STACK_ADDR 0x00187f10
/* Values */
#define SDRAM_ENA 0x1
#define CMD_TIMEOUT 2000 /* msecs */
#define POLL_INTERVAL 1 /* secs */
/* commands for interaction with the modem through the control channel before
* firmware is loaded */
enum cxacru_fw_request {
FW_CMD_ERR,
FW_GET_VER,
FW_READ_MEM,
FW_WRITE_MEM,
FW_RMW_MEM,
FW_CHECKSUM_MEM,
FW_GOTO_MEM,
};
/* commands for interaction with the modem through the control channel once
* firmware is loaded */
enum cxacru_cm_request {
CM_REQUEST_UNDEFINED = 0x80,
CM_REQUEST_TEST,
CM_REQUEST_CHIP_GET_MAC_ADDRESS,
CM_REQUEST_CHIP_GET_DP_VERSIONS,
CM_REQUEST_CHIP_ADSL_LINE_START,
CM_REQUEST_CHIP_ADSL_LINE_STOP,
CM_REQUEST_CHIP_ADSL_LINE_GET_STATUS,
CM_REQUEST_CHIP_ADSL_LINE_GET_SPEED,
CM_REQUEST_CARD_INFO_GET,
CM_REQUEST_CARD_DATA_GET,
CM_REQUEST_CARD_DATA_SET,
CM_REQUEST_COMMAND_HW_IO,
CM_REQUEST_INTERFACE_HW_IO,
CM_REQUEST_CARD_SERIAL_DATA_PATH_GET,
CM_REQUEST_CARD_SERIAL_DATA_PATH_SET,
CM_REQUEST_CARD_CONTROLLER_VERSION_GET,
CM_REQUEST_CARD_GET_STATUS,
CM_REQUEST_CARD_GET_MAC_ADDRESS,
CM_REQUEST_CARD_GET_DATA_LINK_STATUS,
CM_REQUEST_MAX,
};
/* commands for interaction with the flash memory
*
* read: response is the contents of the first 60 bytes of flash memory
* write: request contains the 60 bytes of data to write to flash memory
* response is the contents of the first 60 bytes of flash memory
*
* layout: PP PP VV VV MM MM MM MM MM MM ?? ?? SS SS SS SS SS SS SS SS
* SS SS SS SS SS SS SS SS 00 00 00 00 00 00 00 00 00 00 00 00
* 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
* P: le16 USB Product ID
* V: le16 USB Vendor ID
* M: be48 MAC Address
* S: le16 ASCII Serial Number
*/
enum cxacru_cm_flash {
CM_FLASH_READ = 0xa1,
CM_FLASH_WRITE = 0xa2
};
/* reply codes to the commands above */
enum cxacru_cm_status {
CM_STATUS_UNDEFINED,
CM_STATUS_SUCCESS,
CM_STATUS_ERROR,
CM_STATUS_UNSUPPORTED,
CM_STATUS_UNIMPLEMENTED,
CM_STATUS_PARAMETER_ERROR,
CM_STATUS_DBG_LOOPBACK,
CM_STATUS_MAX,
};
/* indices into CARD_INFO_GET return array */
enum cxacru_info_idx {
CXINF_DOWNSTREAM_RATE,
CXINF_UPSTREAM_RATE,
CXINF_LINK_STATUS,
CXINF_LINE_STATUS,
CXINF_MAC_ADDRESS_HIGH,
CXINF_MAC_ADDRESS_LOW,
CXINF_UPSTREAM_SNR_MARGIN,
CXINF_DOWNSTREAM_SNR_MARGIN,
CXINF_UPSTREAM_ATTENUATION,
CXINF_DOWNSTREAM_ATTENUATION,
CXINF_TRANSMITTER_POWER,
CXINF_UPSTREAM_BITS_PER_FRAME,
CXINF_DOWNSTREAM_BITS_PER_FRAME,
CXINF_STARTUP_ATTEMPTS,
CXINF_UPSTREAM_CRC_ERRORS,
CXINF_DOWNSTREAM_CRC_ERRORS,
CXINF_UPSTREAM_FEC_ERRORS,
CXINF_DOWNSTREAM_FEC_ERRORS,
CXINF_UPSTREAM_HEC_ERRORS,
CXINF_DOWNSTREAM_HEC_ERRORS,
CXINF_LINE_STARTABLE,
CXINF_MODULATION,
CXINF_ADSL_HEADEND,
CXINF_ADSL_HEADEND_ENVIRONMENT,
CXINF_CONTROLLER_VERSION,
/* dunno what the missing two mean */
CXINF_MAX = 0x1c,
};
enum cxacru_poll_state {
CXPOLL_STOPPING,
CXPOLL_STOPPED,
CXPOLL_POLLING,
CXPOLL_SHUTDOWN
};
struct cxacru_modem_type {
u32 pll_f_clk;
u32 pll_b_clk;
int boot_rom_patch;
};
struct cxacru_data {
struct usbatm_data *usbatm;
const struct cxacru_modem_type *modem_type;
int line_status;
struct mutex adsl_state_serialize;
int adsl_status;
struct delayed_work poll_work;
u32 card_info[CXINF_MAX];
struct mutex poll_state_serialize;
enum cxacru_poll_state poll_state;
/* contol handles */
struct mutex cm_serialize;
u8 *rcv_buf;
u8 *snd_buf;
struct urb *rcv_urb;
struct urb *snd_urb;
struct completion rcv_done;
struct completion snd_done;
};
static int cxacru_cm(struct cxacru_data *instance, enum cxacru_cm_request cm,
u8 *wdata, int wsize, u8 *rdata, int rsize);
static void cxacru_poll_status(struct work_struct *work);
/* Card info exported through sysfs */
#define CXACRU__ATTR_INIT(_name) \
static DEVICE_ATTR(_name, S_IRUGO, cxacru_sysfs_show_##_name, NULL)
#define CXACRU_CMD_INIT(_name) \
static DEVICE_ATTR(_name, S_IWUSR | S_IRUGO, \
cxacru_sysfs_show_##_name, cxacru_sysfs_store_##_name)
#define CXACRU_SET_INIT(_name) \
static DEVICE_ATTR(_name, S_IWUSR, \
NULL, cxacru_sysfs_store_##_name)
#define CXACRU_ATTR_INIT(_value, _type, _name) \
static ssize_t cxacru_sysfs_show_##_name(struct device *dev, \
struct device_attribute *attr, char *buf) \
{ \
struct cxacru_data *instance = to_usbatm_driver_data(\
to_usb_interface(dev)); \
\
if (instance == NULL) \
return -ENODEV; \
\
return cxacru_sysfs_showattr_##_type(instance->card_info[_value], buf); \
} \
CXACRU__ATTR_INIT(_name)
#define CXACRU_ATTR_CREATE(_v, _t, _name) CXACRU_DEVICE_CREATE_FILE(_name)
#define CXACRU_CMD_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name)
#define CXACRU_SET_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name)
#define CXACRU__ATTR_CREATE(_name) CXACRU_DEVICE_CREATE_FILE(_name)
#define CXACRU_ATTR_REMOVE(_v, _t, _name) CXACRU_DEVICE_REMOVE_FILE(_name)
#define CXACRU_CMD_REMOVE(_name) CXACRU_DEVICE_REMOVE_FILE(_name)
#define CXACRU_SET_REMOVE(_name) CXACRU_DEVICE_REMOVE_FILE(_name)
#define CXACRU__ATTR_REMOVE(_name) CXACRU_DEVICE_REMOVE_FILE(_name)
static ssize_t cxacru_sysfs_showattr_u32(u32 value, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%u\n", value);
}
static ssize_t cxacru_sysfs_showattr_s8(s8 value, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", value);
}
static ssize_t cxacru_sysfs_showattr_dB(s16 value, char *buf)
{
if (likely(value >= 0)) {
return snprintf(buf, PAGE_SIZE, "%u.%02u\n",
value / 100, value % 100);
} else {
value = -value;
return snprintf(buf, PAGE_SIZE, "-%u.%02u\n",
value / 100, value % 100);
}
}
static ssize_t cxacru_sysfs_showattr_bool(u32 value, char *buf)
{
static char *str[] = { "no", "yes" };
if (unlikely(value >= ARRAY_SIZE(str)))
return snprintf(buf, PAGE_SIZE, "%u\n", value);
return snprintf(buf, PAGE_SIZE, "%s\n", str[value]);
}
static ssize_t cxacru_sysfs_showattr_LINK(u32 value, char *buf)
{
static char *str[] = { NULL, "not connected", "connected", "lost" };
if (unlikely(value >= ARRAY_SIZE(str) || str[value] == NULL))
return snprintf(buf, PAGE_SIZE, "%u\n", value);
return snprintf(buf, PAGE_SIZE, "%s\n", str[value]);
}
static ssize_t cxacru_sysfs_showattr_LINE(u32 value, char *buf)
{
static char *str[] = { "down", "attempting to activate",
"training", "channel analysis", "exchange", "up",
"waiting", "initialising"
};
if (unlikely(value >= ARRAY_SIZE(str)))
return snprintf(buf, PAGE_SIZE, "%u\n", value);
return snprintf(buf, PAGE_SIZE, "%s\n", str[value]);
}
static ssize_t cxacru_sysfs_showattr_MODU(u32 value, char *buf)
{
static char *str[] = {
"",
"ANSI T1.413",
"ITU-T G.992.1 (G.DMT)",
"ITU-T G.992.2 (G.LITE)"
};
if (unlikely(value >= ARRAY_SIZE(str)))
return snprintf(buf, PAGE_SIZE, "%u\n", value);
return snprintf(buf, PAGE_SIZE, "%s\n", str[value]);
}
/*
* This could use MAC_ADDRESS_HIGH and MAC_ADDRESS_LOW, but since
* this data is already in atm_dev there's no point.
*
* MAC_ADDRESS_HIGH = 0x????5544
* MAC_ADDRESS_LOW = 0x33221100
* Where 00-55 are bytes 0-5 of the MAC.
*/
static ssize_t cxacru_sysfs_show_mac_address(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct cxacru_data *instance = to_usbatm_driver_data(
to_usb_interface(dev));
if (instance == NULL || instance->usbatm->atm_dev == NULL)
return -ENODEV;
return snprintf(buf, PAGE_SIZE, "%pM\n",
instance->usbatm->atm_dev->esi);
}
static ssize_t cxacru_sysfs_show_adsl_state(struct device *dev,
struct device_attribute *attr, char *buf)
{
static char *str[] = { "running", "stopped" };
struct cxacru_data *instance = to_usbatm_driver_data(
to_usb_interface(dev));
u32 value;
if (instance == NULL)
return -ENODEV;
value = instance->card_info[CXINF_LINE_STARTABLE];
if (unlikely(value >= ARRAY_SIZE(str)))
return snprintf(buf, PAGE_SIZE, "%u\n", value);
return snprintf(buf, PAGE_SIZE, "%s\n", str[value]);
}
static ssize_t cxacru_sysfs_store_adsl_state(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct cxacru_data *instance = to_usbatm_driver_data(
to_usb_interface(dev));
int ret;
int poll = -1;
char str_cmd[8];
int len = strlen(buf);
if (!capable(CAP_NET_ADMIN))
return -EACCES;
ret = sscanf(buf, "%7s", str_cmd);
if (ret != 1)
return -EINVAL;
ret = 0;
if (instance == NULL)
return -ENODEV;
if (mutex_lock_interruptible(&instance->adsl_state_serialize))
return -ERESTARTSYS;
if (!strcmp(str_cmd, "stop") || !strcmp(str_cmd, "restart")) {
ret = cxacru_cm(instance, CM_REQUEST_CHIP_ADSL_LINE_STOP, NULL, 0, NULL, 0);
if (ret < 0) {
atm_err(instance->usbatm, "change adsl state:"
" CHIP_ADSL_LINE_STOP returned %d\n", ret);
ret = -EIO;
} else {
ret = len;
poll = CXPOLL_STOPPED;
}
}
/* Line status is only updated every second
* and the device appears to only react to
* START/STOP every second too. Wait 1.5s to
* be sure that restart will have an effect. */
if (!strcmp(str_cmd, "restart"))
msleep(1500);
if (!strcmp(str_cmd, "start") || !strcmp(str_cmd, "restart")) {
ret = cxacru_cm(instance, CM_REQUEST_CHIP_ADSL_LINE_START, NULL, 0, NULL, 0);
if (ret < 0) {
atm_err(instance->usbatm, "change adsl state:"
" CHIP_ADSL_LINE_START returned %d\n", ret);
ret = -EIO;
} else {
ret = len;
poll = CXPOLL_POLLING;
}
}
if (!strcmp(str_cmd, "poll")) {
ret = len;
poll = CXPOLL_POLLING;
}
if (ret == 0) {
ret = -EINVAL;
poll = -1;
}
if (poll == CXPOLL_POLLING) {
mutex_lock(&instance->poll_state_serialize);
switch (instance->poll_state) {
case CXPOLL_STOPPED:
/* start polling */
instance->poll_state = CXPOLL_POLLING;
break;
case CXPOLL_STOPPING:
/* abort stop request */
instance->poll_state = CXPOLL_POLLING;
case CXPOLL_POLLING:
case CXPOLL_SHUTDOWN:
/* don't start polling */
poll = -1;
}
mutex_unlock(&instance->poll_state_serialize);
} else if (poll == CXPOLL_STOPPED) {
mutex_lock(&instance->poll_state_serialize);
/* request stop */
if (instance->poll_state == CXPOLL_POLLING)
instance->poll_state = CXPOLL_STOPPING;
mutex_unlock(&instance->poll_state_serialize);
}
mutex_unlock(&instance->adsl_state_serialize);
if (poll == CXPOLL_POLLING)
cxacru_poll_status(&instance->poll_work.work);
return ret;
}
/* CM_REQUEST_CARD_DATA_GET times out, so no show attribute */
static ssize_t cxacru_sysfs_store_adsl_config(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct cxacru_data *instance = to_usbatm_driver_data(
to_usb_interface(dev));
int len = strlen(buf);
int ret, pos, num;
__le32 data[CMD_PACKET_SIZE / 4];
if (!capable(CAP_NET_ADMIN))
return -EACCES;
if (instance == NULL)
return -ENODEV;
pos = 0;
num = 0;
while (pos < len) {
int tmp;
u32 index;
u32 value;
ret = sscanf(buf + pos, "%x=%x%n", &index, &value, &tmp);
if (ret < 2)
return -EINVAL;
if (index < 0 || index > 0x7f)
return -EINVAL;
pos += tmp;
/* skip trailing newline */
if (buf[pos] == '\n' && pos == len-1)
pos++;
data[num * 2 + 1] = cpu_to_le32(index);
data[num * 2 + 2] = cpu_to_le32(value);
num++;
/* send config values when data buffer is full
* or no more data
*/
if (pos >= len || num >= CMD_MAX_CONFIG) {
char log[CMD_MAX_CONFIG * 12 + 1]; /* %02x=%08x */
data[0] = cpu_to_le32(num);
ret = cxacru_cm(instance, CM_REQUEST_CARD_DATA_SET,
(u8 *) data, 4 + num * 8, NULL, 0);
if (ret < 0) {
atm_err(instance->usbatm,
"set card data returned %d\n", ret);
return -EIO;
}
for (tmp = 0; tmp < num; tmp++)
snprintf(log + tmp*12, 13, " %02x=%08x",
le32_to_cpu(data[tmp * 2 + 1]),
le32_to_cpu(data[tmp * 2 + 2]));
atm_info(instance->usbatm, "config%s\n", log);
num = 0;
}
}
return len;
}
/*
* All device attributes are included in CXACRU_ALL_FILES
* so that the same list can be used multiple times:
* INIT (define the device attributes)
* CREATE (create all the device files)
* REMOVE (remove all the device files)
*
* With the last two being defined as needed in the functions
* they are used in before calling CXACRU_ALL_FILES()
*/
#define CXACRU_ALL_FILES(_action) \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_RATE, u32, downstream_rate); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_RATE, u32, upstream_rate); \
CXACRU_ATTR_##_action(CXINF_LINK_STATUS, LINK, link_status); \
CXACRU_ATTR_##_action(CXINF_LINE_STATUS, LINE, line_status); \
CXACRU__ATTR_##_action( mac_address); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_SNR_MARGIN, dB, upstream_snr_margin); \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_SNR_MARGIN, dB, downstream_snr_margin); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_ATTENUATION, dB, upstream_attenuation); \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_ATTENUATION, dB, downstream_attenuation); \
CXACRU_ATTR_##_action(CXINF_TRANSMITTER_POWER, s8, transmitter_power); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_BITS_PER_FRAME, u32, upstream_bits_per_frame); \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_BITS_PER_FRAME, u32, downstream_bits_per_frame); \
CXACRU_ATTR_##_action(CXINF_STARTUP_ATTEMPTS, u32, startup_attempts); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_CRC_ERRORS, u32, upstream_crc_errors); \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_CRC_ERRORS, u32, downstream_crc_errors); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_FEC_ERRORS, u32, upstream_fec_errors); \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_FEC_ERRORS, u32, downstream_fec_errors); \
CXACRU_ATTR_##_action(CXINF_UPSTREAM_HEC_ERRORS, u32, upstream_hec_errors); \
CXACRU_ATTR_##_action(CXINF_DOWNSTREAM_HEC_ERRORS, u32, downstream_hec_errors); \
CXACRU_ATTR_##_action(CXINF_LINE_STARTABLE, bool, line_startable); \
CXACRU_ATTR_##_action(CXINF_MODULATION, MODU, modulation); \
CXACRU_ATTR_##_action(CXINF_ADSL_HEADEND, u32, adsl_headend); \
CXACRU_ATTR_##_action(CXINF_ADSL_HEADEND_ENVIRONMENT, u32, adsl_headend_environment); \
CXACRU_ATTR_##_action(CXINF_CONTROLLER_VERSION, u32, adsl_controller_version); \
CXACRU_CMD_##_action( adsl_state); \
CXACRU_SET_##_action( adsl_config);
CXACRU_ALL_FILES(INIT);
/* the following three functions are stolen from drivers/usb/core/message.c */
static void cxacru_blocking_completion(struct urb *urb)
{
complete(urb->context);
}
static void cxacru_timeout_kill(unsigned long data)
{
usb_unlink_urb((struct urb *) data);
}
static int cxacru_start_wait_urb(struct urb *urb, struct completion *done,
int *actual_length)
{
struct timer_list timer;
init_timer(&timer);
timer.expires = jiffies + msecs_to_jiffies(CMD_TIMEOUT);
timer.data = (unsigned long) urb;
timer.function = cxacru_timeout_kill;
add_timer(&timer);
wait_for_completion(done);
del_timer_sync(&timer);
if (actual_length)
*actual_length = urb->actual_length;
return urb->status; /* must read status after completion */
}
static int cxacru_cm(struct cxacru_data *instance, enum cxacru_cm_request cm,
u8 *wdata, int wsize, u8 *rdata, int rsize)
{
int ret, actlen;
int offb, offd;
const int stride = CMD_PACKET_SIZE - 4;
u8 *wbuf = instance->snd_buf;
u8 *rbuf = instance->rcv_buf;
int wbuflen = ((wsize - 1) / stride + 1) * CMD_PACKET_SIZE;
int rbuflen = ((rsize - 1) / stride + 1) * CMD_PACKET_SIZE;
if (wbuflen > PAGE_SIZE || rbuflen > PAGE_SIZE) {
if (printk_ratelimit())
usb_err(instance->usbatm, "requested transfer size too large (%d, %d)\n",
wbuflen, rbuflen);
ret = -ENOMEM;
goto err;
}
mutex_lock(&instance->cm_serialize);
/* submit reading urb before the writing one */
init_completion(&instance->rcv_done);
ret = usb_submit_urb(instance->rcv_urb, GFP_KERNEL);
if (ret < 0) {
if (printk_ratelimit())
usb_err(instance->usbatm, "submit of read urb for cm %#x failed (%d)\n",
cm, ret);
goto fail;
}
memset(wbuf, 0, wbuflen);
/* handle wsize == 0 */
wbuf[0] = cm;
for (offb = offd = 0; offd < wsize; offd += stride, offb += CMD_PACKET_SIZE) {
wbuf[offb] = cm;
memcpy(wbuf + offb + 4, wdata + offd, min_t(int, stride, wsize - offd));
}
instance->snd_urb->transfer_buffer_length = wbuflen;
init_completion(&instance->snd_done);
ret = usb_submit_urb(instance->snd_urb, GFP_KERNEL);
if (ret < 0) {
if (printk_ratelimit())
usb_err(instance->usbatm, "submit of write urb for cm %#x failed (%d)\n",
cm, ret);
goto fail;
}
ret = cxacru_start_wait_urb(instance->snd_urb, &instance->snd_done, NULL);
if (ret < 0) {
if (printk_ratelimit())
usb_err(instance->usbatm, "send of cm %#x failed (%d)\n", cm, ret);
goto fail;
}
ret = cxacru_start_wait_urb(instance->rcv_urb, &instance->rcv_done, &actlen);
if (ret < 0) {
if (printk_ratelimit())
usb_err(instance->usbatm, "receive of cm %#x failed (%d)\n", cm, ret);
goto fail;
}
if (actlen % CMD_PACKET_SIZE || !actlen) {
if (printk_ratelimit())
usb_err(instance->usbatm, "invalid response length to cm %#x: %d\n",
cm, actlen);
ret = -EIO;
goto fail;
}
/* check the return status and copy the data to the output buffer, if needed */
for (offb = offd = 0; offd < rsize && offb < actlen; offb += CMD_PACKET_SIZE) {
if (rbuf[offb] != cm) {
if (printk_ratelimit())
usb_err(instance->usbatm, "wrong cm %#x in response to cm %#x\n",
rbuf[offb], cm);
ret = -EIO;
goto fail;
}
if (rbuf[offb + 1] != CM_STATUS_SUCCESS) {
if (printk_ratelimit())
usb_err(instance->usbatm, "response to cm %#x failed: %#x\n",
cm, rbuf[offb + 1]);
ret = -EIO;
goto fail;
}
if (offd >= rsize)
break;
memcpy(rdata + offd, rbuf + offb + 4, min_t(int, stride, rsize - offd));
offd += stride;
}
ret = offd;
usb_dbg(instance->usbatm, "cm %#x\n", cm);
fail:
mutex_unlock(&instance->cm_serialize);
err:
return ret;
}
static int cxacru_cm_get_array(struct cxacru_data *instance, enum cxacru_cm_request cm,
u32 *data, int size)
{
int ret, len;
__le32 *buf;
int offb;
unsigned int offd;
const int stride = CMD_PACKET_SIZE / (4 * 2) - 1;
int buflen = ((size - 1) / stride + 1 + size * 2) * 4;
buf = kmalloc(buflen, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = cxacru_cm(instance, cm, NULL, 0, (u8 *) buf, buflen);
if (ret < 0)
goto cleanup;
/* len > 0 && len % 4 == 0 guaranteed by cxacru_cm() */
len = ret / 4;
for (offb = 0; offb < len; ) {
int l = le32_to_cpu(buf[offb++]);
if (l < 0 || l > stride || l > (len - offb) / 2) {
if (printk_ratelimit())
usb_err(instance->usbatm, "invalid data length from cm %#x: %d\n",
cm, l);
ret = -EIO;
goto cleanup;
}
while (l--) {
offd = le32_to_cpu(buf[offb++]);
if (offd >= size) {
if (printk_ratelimit())
usb_err(instance->usbatm, "wrong index %#x in response to cm %#x\n",
offd, cm);
ret = -EIO;
goto cleanup;
}
data[offd] = le32_to_cpu(buf[offb++]);
}
}
ret = 0;
cleanup:
kfree(buf);
return ret;
}
static int cxacru_card_status(struct cxacru_data *instance)
{
int ret = cxacru_cm(instance, CM_REQUEST_CARD_GET_STATUS, NULL, 0, NULL, 0);
if (ret < 0) { /* firmware not loaded */
usb_dbg(instance->usbatm, "cxacru_adsl_start: CARD_GET_STATUS returned %d\n", ret);
return ret;
}
return 0;
}
static void cxacru_remove_device_files(struct usbatm_data *usbatm_instance,
struct atm_dev *atm_dev)
{
struct usb_interface *intf = usbatm_instance->usb_intf;
#define CXACRU_DEVICE_REMOVE_FILE(_name) \
device_remove_file(&intf->dev, &dev_attr_##_name);
CXACRU_ALL_FILES(REMOVE);
#undef CXACRU_DEVICE_REMOVE_FILE
}
static int cxacru_atm_start(struct usbatm_data *usbatm_instance,
struct atm_dev *atm_dev)
{
struct cxacru_data *instance = usbatm_instance->driver_data;
struct usb_interface *intf = usbatm_instance->usb_intf;
int ret;
int start_polling = 1;
dev_dbg(&intf->dev, "%s\n", __func__);
/* Read MAC address */
ret = cxacru_cm(instance, CM_REQUEST_CARD_GET_MAC_ADDRESS, NULL, 0,
atm_dev->esi, sizeof(atm_dev->esi));
if (ret < 0) {
atm_err(usbatm_instance, "cxacru_atm_start: CARD_GET_MAC_ADDRESS returned %d\n", ret);
return ret;
}
#define CXACRU_DEVICE_CREATE_FILE(_name) \
ret = device_create_file(&intf->dev, &dev_attr_##_name); \
if (unlikely(ret)) \
goto fail_sysfs;
CXACRU_ALL_FILES(CREATE);
#undef CXACRU_DEVICE_CREATE_FILE
/* start ADSL */
mutex_lock(&instance->adsl_state_serialize);
ret = cxacru_cm(instance, CM_REQUEST_CHIP_ADSL_LINE_START, NULL, 0, NULL, 0);
if (ret < 0)
atm_err(usbatm_instance, "cxacru_atm_start: CHIP_ADSL_LINE_START returned %d\n", ret);
/* Start status polling */
mutex_lock(&instance->poll_state_serialize);
switch (instance->poll_state) {
case CXPOLL_STOPPED:
/* start polling */
instance->poll_state = CXPOLL_POLLING;
break;
case CXPOLL_STOPPING:
/* abort stop request */
instance->poll_state = CXPOLL_POLLING;
case CXPOLL_POLLING:
case CXPOLL_SHUTDOWN:
/* don't start polling */
start_polling = 0;
}
mutex_unlock(&instance->poll_state_serialize);
mutex_unlock(&instance->adsl_state_serialize);
printk(KERN_INFO "%s%d: %s %pM\n", atm_dev->type, atm_dev->number,
usbatm_instance->description, atm_dev->esi);
if (start_polling)
cxacru_poll_status(&instance->poll_work.work);
return 0;
fail_sysfs:
usb_err(usbatm_instance, "cxacru_atm_start: device_create_file failed (%d)\n", ret);
cxacru_remove_device_files(usbatm_instance, atm_dev);
return ret;
}
static void cxacru_poll_status(struct work_struct *work)
{
struct cxacru_data *instance =
container_of(work, struct cxacru_data, poll_work.work);
u32 buf[CXINF_MAX] = {};
struct usbatm_data *usbatm = instance->usbatm;
struct atm_dev *atm_dev = usbatm->atm_dev;
int keep_polling = 1;
int ret;
ret = cxacru_cm_get_array(instance, CM_REQUEST_CARD_INFO_GET, buf, CXINF_MAX);
if (ret < 0) {
if (ret != -ESHUTDOWN)
atm_warn(usbatm, "poll status: error %d\n", ret);
mutex_lock(&instance->poll_state_serialize);
if (instance->poll_state != CXPOLL_SHUTDOWN) {
instance->poll_state = CXPOLL_STOPPED;
if (ret != -ESHUTDOWN)
atm_warn(usbatm, "polling disabled, set adsl_state"
" to 'start' or 'poll' to resume\n");
}
mutex_unlock(&instance->poll_state_serialize);
goto reschedule;
}
memcpy(instance->card_info, buf, sizeof(instance->card_info));
if (instance->adsl_status != buf[CXINF_LINE_STARTABLE]) {
instance->adsl_status = buf[CXINF_LINE_STARTABLE];
switch (instance->adsl_status) {
case 0:
atm_printk(KERN_INFO, usbatm, "ADSL state: running\n");
break;
case 1:
atm_printk(KERN_INFO, usbatm, "ADSL state: stopped\n");
break;
default:
atm_printk(KERN_INFO, usbatm, "Unknown adsl status %02x\n", instance->adsl_status);
break;
}
}
if (instance->line_status == buf[CXINF_LINE_STATUS])
goto reschedule;
instance->line_status = buf[CXINF_LINE_STATUS];
switch (instance->line_status) {
case 0:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: down\n");
break;
case 1:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: attempting to activate\n");
break;
case 2:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: training\n");
break;
case 3:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: channel analysis\n");
break;
case 4:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: exchange\n");
break;
case 5:
atm_dev->link_rate = buf[CXINF_DOWNSTREAM_RATE] * 1000 / 424;
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_FOUND);
atm_info(usbatm, "ADSL line: up (%d kb/s down | %d kb/s up)\n",
buf[CXINF_DOWNSTREAM_RATE], buf[CXINF_UPSTREAM_RATE]);
break;
case 6:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: waiting\n");
break;
case 7:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_LOST);
atm_info(usbatm, "ADSL line: initializing\n");
break;
default:
atm_dev_signal_change(atm_dev, ATM_PHY_SIG_UNKNOWN);
atm_info(usbatm, "Unknown line state %02x\n", instance->line_status);
break;
}
reschedule:
mutex_lock(&instance->poll_state_serialize);
if (instance->poll_state == CXPOLL_STOPPING &&
instance->adsl_status == 1 && /* stopped */
instance->line_status == 0) /* down */
instance->poll_state = CXPOLL_STOPPED;
if (instance->poll_state == CXPOLL_STOPPED)
keep_polling = 0;
mutex_unlock(&instance->poll_state_serialize);
if (keep_polling)
schedule_delayed_work(&instance->poll_work,
round_jiffies_relative(POLL_INTERVAL*HZ));
}
static int cxacru_fw(struct usb_device *usb_dev, enum cxacru_fw_request fw,
u8 code1, u8 code2, u32 addr, const u8 *data, int size)
{
int ret;
u8 *buf;
int offd, offb;
const int stride = CMD_PACKET_SIZE - 8;
buf = (u8 *) __get_free_page(GFP_KERNEL);
if (!buf)
return -ENOMEM;
offb = offd = 0;
do {
int l = min_t(int, stride, size - offd);
buf[offb++] = fw;
buf[offb++] = l;
buf[offb++] = code1;
buf[offb++] = code2;
put_unaligned(cpu_to_le32(addr), (__le32 *)(buf + offb));
offb += 4;
addr += l;
if (l)
memcpy(buf + offb, data + offd, l);
if (l < stride)
memset(buf + offb + l, 0, stride - l);
offb += stride;
offd += stride;
if ((offb >= PAGE_SIZE) || (offd >= size)) {
ret = usb_bulk_msg(usb_dev, usb_sndbulkpipe(usb_dev, CXACRU_EP_CMD),
buf, offb, NULL, CMD_TIMEOUT);
if (ret < 0) {
dev_dbg(&usb_dev->dev, "sending fw %#x failed\n", fw);
goto cleanup;
}
offb = 0;
}
} while (offd < size);
dev_dbg(&usb_dev->dev, "sent fw %#x\n", fw);
ret = 0;
cleanup:
free_page((unsigned long) buf);
return ret;
}
static void cxacru_upload_firmware(struct cxacru_data *instance,
const struct firmware *fw,
const struct firmware *bp)
{
int ret;
struct usbatm_data *usbatm = instance->usbatm;
struct usb_device *usb_dev = usbatm->usb_dev;
__le16 signature[] = { usb_dev->descriptor.idVendor,
usb_dev->descriptor.idProduct };
__le32 val;
usb_dbg(usbatm, "%s\n", __func__);
/* FirmwarePllFClkValue */
val = cpu_to_le32(instance->modem_type->pll_f_clk);
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, PLLFCLK_ADDR, (u8 *) &val, 4);
if (ret) {
usb_err(usbatm, "FirmwarePllFClkValue failed: %d\n", ret);
return;
}
/* FirmwarePllBClkValue */
val = cpu_to_le32(instance->modem_type->pll_b_clk);
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, PLLBCLK_ADDR, (u8 *) &val, 4);
if (ret) {
usb_err(usbatm, "FirmwarePllBClkValue failed: %d\n", ret);
return;
}
/* Enable SDRAM */
val = cpu_to_le32(SDRAM_ENA);
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, SDRAMEN_ADDR, (u8 *) &val, 4);
if (ret) {
usb_err(usbatm, "Enable SDRAM failed: %d\n", ret);
return;
}
/* Firmware */
usb_info(usbatm, "loading firmware\n");
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, FW_ADDR, fw->data, fw->size);
if (ret) {
usb_err(usbatm, "Firmware upload failed: %d\n", ret);
return;
}
/* Boot ROM patch */
if (instance->modem_type->boot_rom_patch) {
usb_info(usbatm, "loading boot ROM patch\n");
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, BR_ADDR, bp->data, bp->size);
if (ret) {
usb_err(usbatm, "Boot ROM patching failed: %d\n", ret);
return;
}
}
/* Signature */
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, SIG_ADDR, (u8 *) signature, 4);
if (ret) {
usb_err(usbatm, "Signature storing failed: %d\n", ret);
return;
}
usb_info(usbatm, "starting device\n");
if (instance->modem_type->boot_rom_patch) {
val = cpu_to_le32(BR_ADDR);
ret = cxacru_fw(usb_dev, FW_WRITE_MEM, 0x2, 0x0, BR_STACK_ADDR, (u8 *) &val, 4);
} else {
ret = cxacru_fw(usb_dev, FW_GOTO_MEM, 0x0, 0x0, FW_ADDR, NULL, 0);
}
if (ret) {
usb_err(usbatm, "Passing control to firmware failed: %d\n", ret);
return;
}
/* Delay to allow firmware to start up. */
msleep_interruptible(1000);
usb_clear_halt(usb_dev, usb_sndbulkpipe(usb_dev, CXACRU_EP_CMD));
usb_clear_halt(usb_dev, usb_rcvbulkpipe(usb_dev, CXACRU_EP_CMD));
usb_clear_halt(usb_dev, usb_sndbulkpipe(usb_dev, CXACRU_EP_DATA));
usb_clear_halt(usb_dev, usb_rcvbulkpipe(usb_dev, CXACRU_EP_DATA));
ret = cxacru_cm(instance, CM_REQUEST_CARD_GET_STATUS, NULL, 0, NULL, 0);
if (ret < 0) {
usb_err(usbatm, "modem failed to initialize: %d\n", ret);
return;
}
}
static int cxacru_find_firmware(struct cxacru_data *instance,
char *phase, const struct firmware **fw_p)
{
struct usbatm_data *usbatm = instance->usbatm;
struct device *dev = &usbatm->usb_intf->dev;
char buf[16];
sprintf(buf, "cxacru-%s.bin", phase);
usb_dbg(usbatm, "cxacru_find_firmware: looking for %s\n", buf);
if (request_firmware(fw_p, buf, dev)) {
usb_dbg(usbatm, "no stage %s firmware found\n", phase);
return -ENOENT;
}
usb_info(usbatm, "found firmware %s\n", buf);
return 0;
}
static int cxacru_heavy_init(struct usbatm_data *usbatm_instance,
struct usb_interface *usb_intf)
{
const struct firmware *fw, *bp;
struct cxacru_data *instance = usbatm_instance->driver_data;
int ret = cxacru_find_firmware(instance, "fw", &fw);
if (ret) {
usb_warn(usbatm_instance, "firmware (cxacru-fw.bin) unavailable (system misconfigured?)\n");
return ret;
}
if (instance->modem_type->boot_rom_patch) {
ret = cxacru_find_firmware(instance, "bp", &bp);
if (ret) {
usb_warn(usbatm_instance, "boot ROM patch (cxacru-bp.bin) unavailable (system misconfigured?)\n");
release_firmware(fw);
return ret;
}
}
cxacru_upload_firmware(instance, fw, bp);
if (instance->modem_type->boot_rom_patch)
release_firmware(bp);
release_firmware(fw);
ret = cxacru_card_status(instance);
if (ret)
usb_dbg(usbatm_instance, "modem initialisation failed\n");
else
usb_dbg(usbatm_instance, "done setting up the modem\n");
return ret;
}
static int cxacru_bind(struct usbatm_data *usbatm_instance,
struct usb_interface *intf, const struct usb_device_id *id)
{
struct cxacru_data *instance;
struct usb_device *usb_dev = interface_to_usbdev(intf);
struct usb_host_endpoint *cmd_ep = usb_dev->ep_in[CXACRU_EP_CMD];
int ret;
/* instance init */
instance = kzalloc(sizeof(*instance), GFP_KERNEL);
if (!instance) {
usb_dbg(usbatm_instance, "cxacru_bind: no memory for instance data\n");
return -ENOMEM;
}
instance->usbatm = usbatm_instance;
instance->modem_type = (struct cxacru_modem_type *) id->driver_info;
mutex_init(&instance->poll_state_serialize);
instance->poll_state = CXPOLL_STOPPED;
instance->line_status = -1;
instance->adsl_status = -1;
mutex_init(&instance->adsl_state_serialize);
instance->rcv_buf = (u8 *) __get_free_page(GFP_KERNEL);
if (!instance->rcv_buf) {
usb_dbg(usbatm_instance, "cxacru_bind: no memory for rcv_buf\n");
ret = -ENOMEM;
goto fail;
}
instance->snd_buf = (u8 *) __get_free_page(GFP_KERNEL);
if (!instance->snd_buf) {
usb_dbg(usbatm_instance, "cxacru_bind: no memory for snd_buf\n");
ret = -ENOMEM;
goto fail;
}
instance->rcv_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!instance->rcv_urb) {
usb_dbg(usbatm_instance, "cxacru_bind: no memory for rcv_urb\n");
ret = -ENOMEM;
goto fail;
}
instance->snd_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!instance->snd_urb) {
usb_dbg(usbatm_instance, "cxacru_bind: no memory for snd_urb\n");
ret = -ENOMEM;
goto fail;
}
if (!cmd_ep) {
usb_dbg(usbatm_instance, "cxacru_bind: no command endpoint\n");
ret = -ENODEV;
goto fail;
}
if ((cmd_ep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
== USB_ENDPOINT_XFER_INT) {
usb_fill_int_urb(instance->rcv_urb,
usb_dev, usb_rcvintpipe(usb_dev, CXACRU_EP_CMD),
instance->rcv_buf, PAGE_SIZE,
cxacru_blocking_completion, &instance->rcv_done, 1);
usb_fill_int_urb(instance->snd_urb,
usb_dev, usb_sndintpipe(usb_dev, CXACRU_EP_CMD),
instance->snd_buf, PAGE_SIZE,
cxacru_blocking_completion, &instance->snd_done, 4);
} else {
usb_fill_bulk_urb(instance->rcv_urb,
usb_dev, usb_rcvbulkpipe(usb_dev, CXACRU_EP_CMD),
instance->rcv_buf, PAGE_SIZE,
cxacru_blocking_completion, &instance->rcv_done);
usb_fill_bulk_urb(instance->snd_urb,
usb_dev, usb_sndbulkpipe(usb_dev, CXACRU_EP_CMD),
instance->snd_buf, PAGE_SIZE,
cxacru_blocking_completion, &instance->snd_done);
}
mutex_init(&instance->cm_serialize);
INIT_DELAYED_WORK(&instance->poll_work, cxacru_poll_status);
usbatm_instance->driver_data = instance;
usbatm_instance->flags = (cxacru_card_status(instance) ? 0 : UDSL_SKIP_HEAVY_INIT);
return 0;
fail:
free_page((unsigned long) instance->snd_buf);
free_page((unsigned long) instance->rcv_buf);
usb_free_urb(instance->snd_urb);
usb_free_urb(instance->rcv_urb);
kfree(instance);
return ret;
}
static void cxacru_unbind(struct usbatm_data *usbatm_instance,
struct usb_interface *intf)
{
struct cxacru_data *instance = usbatm_instance->driver_data;
int is_polling = 1;
usb_dbg(usbatm_instance, "cxacru_unbind entered\n");
if (!instance) {
usb_dbg(usbatm_instance, "cxacru_unbind: NULL instance!\n");
return;
}
mutex_lock(&instance->poll_state_serialize);
BUG_ON(instance->poll_state == CXPOLL_SHUTDOWN);
/* ensure that status polling continues unless
* it has already stopped */
if (instance->poll_state == CXPOLL_STOPPED)
is_polling = 0;
/* stop polling from being stopped or started */
instance->poll_state = CXPOLL_SHUTDOWN;
mutex_unlock(&instance->poll_state_serialize);
if (is_polling)
cancel_delayed_work_sync(&instance->poll_work);
usb_kill_urb(instance->snd_urb);
usb_kill_urb(instance->rcv_urb);
usb_free_urb(instance->snd_urb);
usb_free_urb(instance->rcv_urb);
free_page((unsigned long) instance->snd_buf);
free_page((unsigned long) instance->rcv_buf);
kfree(instance);
usbatm_instance->driver_data = NULL;
}
static const struct cxacru_modem_type cxacru_cafe = {
.pll_f_clk = 0x02d874df,
.pll_b_clk = 0x0196a51a,
.boot_rom_patch = 1,
};
static const struct cxacru_modem_type cxacru_cb00 = {
.pll_f_clk = 0x5,
.pll_b_clk = 0x3,
.boot_rom_patch = 0,
};
static const struct usb_device_id cxacru_usb_ids[] = {
{ /* V = Conexant P = ADSL modem (Euphrates project) */
USB_DEVICE(0x0572, 0xcafe), .driver_info = (unsigned long) &cxacru_cafe
},
{ /* V = Conexant P = ADSL modem (Hasbani project) */
USB_DEVICE(0x0572, 0xcb00), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Conexant P = ADSL modem */
USB_DEVICE(0x0572, 0xcb01), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Conexant P = ADSL modem (Well PTI-800) */
USB_DEVICE(0x0572, 0xcb02), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Conexant P = ADSL modem */
USB_DEVICE(0x0572, 0xcb06), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Conexant P = ADSL modem (ZTE ZXDSL 852) */
USB_DEVICE(0x0572, 0xcb07), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Olitec P = ADSL modem version 2 */
USB_DEVICE(0x08e3, 0x0100), .driver_info = (unsigned long) &cxacru_cafe
},
{ /* V = Olitec P = ADSL modem version 3 */
USB_DEVICE(0x08e3, 0x0102), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Trust/Amigo Technology Co. P = AMX-CA86U */
USB_DEVICE(0x0eb0, 0x3457), .driver_info = (unsigned long) &cxacru_cafe
},
{ /* V = Zoom P = 5510 */
USB_DEVICE(0x1803, 0x5510), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Draytek P = Vigor 318 */
USB_DEVICE(0x0675, 0x0200), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Zyxel P = 630-C1 aka OMNI ADSL USB (Annex A) */
USB_DEVICE(0x0586, 0x330a), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Zyxel P = 630-C3 aka OMNI ADSL USB (Annex B) */
USB_DEVICE(0x0586, 0x330b), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Aethra P = Starmodem UM1020 */
USB_DEVICE(0x0659, 0x0020), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Aztech Systems P = ? AKA Pirelli AUA-010 */
USB_DEVICE(0x0509, 0x0812), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Netopia P = Cayman 3341(Annex A)/3351(Annex B) */
USB_DEVICE(0x100d, 0xcb01), .driver_info = (unsigned long) &cxacru_cb00
},
{ /* V = Netopia P = Cayman 3342(Annex A)/3352(Annex B) */
USB_DEVICE(0x100d, 0x3342), .driver_info = (unsigned long) &cxacru_cb00
},
{}
};
MODULE_DEVICE_TABLE(usb, cxacru_usb_ids);
static struct usbatm_driver cxacru_driver = {
.driver_name = cxacru_driver_name,
.bind = cxacru_bind,
.heavy_init = cxacru_heavy_init,
.unbind = cxacru_unbind,
.atm_start = cxacru_atm_start,
.atm_stop = cxacru_remove_device_files,
.bulk_in = CXACRU_EP_DATA,
.bulk_out = CXACRU_EP_DATA,
.rx_padding = 3,
.tx_padding = 11,
};
static int cxacru_usb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
struct usb_device *usb_dev = interface_to_usbdev(intf);
char buf[15];
/* Avoid ADSL routers (cx82310_eth).
* Abort if bDeviceClass is 0xff and iProduct is "USB NET CARD".
*/
if (usb_dev->descriptor.bDeviceClass == USB_CLASS_VENDOR_SPEC
&& usb_string(usb_dev, usb_dev->descriptor.iProduct,
buf, sizeof(buf)) > 0) {
if (!strcmp(buf, "USB NET CARD")) {
dev_info(&intf->dev, "ignoring cx82310_eth device\n");
return -ENODEV;
}
}
return usbatm_usb_probe(intf, id, &cxacru_driver);
}
static struct usb_driver cxacru_usb_driver = {
.name = cxacru_driver_name,
.probe = cxacru_usb_probe,
.disconnect = usbatm_usb_disconnect,
.id_table = cxacru_usb_ids
};
module_usb_driver(cxacru_usb_driver);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_VERSION(DRIVER_VERSION);
| gpl-2.0 |
mythos234/NB_ET_Kernel | drivers/block/xen-blkback/blkback.c | 1621 | 31802 | /******************************************************************************
*
* Back-end of the driver for virtual block devices. This portion of the
* driver exports a 'unified' block-device interface that can be accessed
* by any operating system that implements a compatible front end. A
* reference front-end implementation can be found in:
* drivers/block/xen-blkfront.c
*
* Copyright (c) 2003-2004, Keir Fraser & Steve Hand
* Copyright (c) 2005, Christopher Clark
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation; or, when distributed
* separately from the Linux kernel or incorporated into other
* software packages, subject to the following license:
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this source file (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify,
* merge, publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include <linux/spinlock.h>
#include <linux/kthread.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/freezer.h>
#include <linux/bitmap.h>
#include <xen/events.h>
#include <xen/page.h>
#include <xen/xen.h>
#include <asm/xen/hypervisor.h>
#include <asm/xen/hypercall.h>
#include <xen/balloon.h>
#include "common.h"
/*
* These are rather arbitrary. They are fairly large because adjacent requests
* pulled from a communication ring are quite likely to end up being part of
* the same scatter/gather request at the disc.
*
* ** TRY INCREASING 'xen_blkif_reqs' IF WRITE SPEEDS SEEM TOO LOW **
*
* This will increase the chances of being able to write whole tracks.
* 64 should be enough to keep us competitive with Linux.
*/
static int xen_blkif_reqs = 64;
module_param_named(reqs, xen_blkif_reqs, int, 0);
MODULE_PARM_DESC(reqs, "Number of blkback requests to allocate");
/* Run-time switchable: /sys/module/blkback/parameters/ */
static unsigned int log_stats;
module_param(log_stats, int, 0644);
/*
* Each outstanding request that we've passed to the lower device layers has a
* 'pending_req' allocated to it. Each buffer_head that completes decrements
* the pendcnt towards zero. When it hits zero, the specified domain has a
* response queued for it, with the saved 'id' passed back.
*/
struct pending_req {
struct xen_blkif *blkif;
u64 id;
int nr_pages;
atomic_t pendcnt;
unsigned short operation;
int status;
struct list_head free_list;
DECLARE_BITMAP(unmap_seg, BLKIF_MAX_SEGMENTS_PER_REQUEST);
};
#define BLKBACK_INVALID_HANDLE (~0)
struct xen_blkbk {
struct pending_req *pending_reqs;
/* List of all 'pending_req' available */
struct list_head pending_free;
/* And its spinlock. */
spinlock_t pending_free_lock;
wait_queue_head_t pending_free_wq;
/* The list of all pages that are available. */
struct page **pending_pages;
/* And the grant handles that are available. */
grant_handle_t *pending_grant_handles;
};
static struct xen_blkbk *blkbk;
/*
* Maximum number of grant pages that can be mapped in blkback.
* BLKIF_MAX_SEGMENTS_PER_REQUEST * RING_SIZE is the maximum number of
* pages that blkback will persistently map.
* Currently, this is:
* RING_SIZE = 32 (for all known ring types)
* BLKIF_MAX_SEGMENTS_PER_REQUEST = 11
* sizeof(struct persistent_gnt) = 48
* So the maximum memory used to store the grants is:
* 32 * 11 * 48 = 16896 bytes
*/
static inline unsigned int max_mapped_grant_pages(enum blkif_protocol protocol)
{
switch (protocol) {
case BLKIF_PROTOCOL_NATIVE:
return __CONST_RING_SIZE(blkif, PAGE_SIZE) *
BLKIF_MAX_SEGMENTS_PER_REQUEST;
case BLKIF_PROTOCOL_X86_32:
return __CONST_RING_SIZE(blkif_x86_32, PAGE_SIZE) *
BLKIF_MAX_SEGMENTS_PER_REQUEST;
case BLKIF_PROTOCOL_X86_64:
return __CONST_RING_SIZE(blkif_x86_64, PAGE_SIZE) *
BLKIF_MAX_SEGMENTS_PER_REQUEST;
default:
BUG();
}
return 0;
}
/*
* Little helpful macro to figure out the index and virtual address of the
* pending_pages[..]. For each 'pending_req' we have have up to
* BLKIF_MAX_SEGMENTS_PER_REQUEST (11) pages. The seg would be from 0 through
* 10 and would index in the pending_pages[..].
*/
static inline int vaddr_pagenr(struct pending_req *req, int seg)
{
return (req - blkbk->pending_reqs) *
BLKIF_MAX_SEGMENTS_PER_REQUEST + seg;
}
#define pending_page(req, seg) pending_pages[vaddr_pagenr(req, seg)]
static inline unsigned long vaddr(struct pending_req *req, int seg)
{
unsigned long pfn = page_to_pfn(blkbk->pending_page(req, seg));
return (unsigned long)pfn_to_kaddr(pfn);
}
#define pending_handle(_req, _seg) \
(blkbk->pending_grant_handles[vaddr_pagenr(_req, _seg)])
static int do_block_io_op(struct xen_blkif *blkif);
static int dispatch_rw_block_io(struct xen_blkif *blkif,
struct blkif_request *req,
struct pending_req *pending_req);
static void make_response(struct xen_blkif *blkif, u64 id,
unsigned short op, int st);
#define foreach_grant_safe(pos, n, rbtree, node) \
for ((pos) = container_of(rb_first((rbtree)), typeof(*(pos)), node), \
(n) = (&(pos)->node != NULL) ? rb_next(&(pos)->node) : NULL; \
&(pos)->node != NULL; \
(pos) = container_of(n, typeof(*(pos)), node), \
(n) = (&(pos)->node != NULL) ? rb_next(&(pos)->node) : NULL)
static void add_persistent_gnt(struct rb_root *root,
struct persistent_gnt *persistent_gnt)
{
struct rb_node **new = &(root->rb_node), *parent = NULL;
struct persistent_gnt *this;
/* Figure out where to put new node */
while (*new) {
this = container_of(*new, struct persistent_gnt, node);
parent = *new;
if (persistent_gnt->gnt < this->gnt)
new = &((*new)->rb_left);
else if (persistent_gnt->gnt > this->gnt)
new = &((*new)->rb_right);
else {
pr_alert(DRV_PFX " trying to add a gref that's already in the tree\n");
BUG();
}
}
/* Add new node and rebalance tree. */
rb_link_node(&(persistent_gnt->node), parent, new);
rb_insert_color(&(persistent_gnt->node), root);
}
static struct persistent_gnt *get_persistent_gnt(struct rb_root *root,
grant_ref_t gref)
{
struct persistent_gnt *data;
struct rb_node *node = root->rb_node;
while (node) {
data = container_of(node, struct persistent_gnt, node);
if (gref < data->gnt)
node = node->rb_left;
else if (gref > data->gnt)
node = node->rb_right;
else
return data;
}
return NULL;
}
static void free_persistent_gnts(struct rb_root *root, unsigned int num)
{
struct gnttab_unmap_grant_ref unmap[BLKIF_MAX_SEGMENTS_PER_REQUEST];
struct page *pages[BLKIF_MAX_SEGMENTS_PER_REQUEST];
struct persistent_gnt *persistent_gnt;
struct rb_node *n;
int ret = 0;
int segs_to_unmap = 0;
foreach_grant_safe(persistent_gnt, n, root, node) {
BUG_ON(persistent_gnt->handle ==
BLKBACK_INVALID_HANDLE);
gnttab_set_unmap_op(&unmap[segs_to_unmap],
(unsigned long) pfn_to_kaddr(page_to_pfn(
persistent_gnt->page)),
GNTMAP_host_map,
persistent_gnt->handle);
pages[segs_to_unmap] = persistent_gnt->page;
if (++segs_to_unmap == BLKIF_MAX_SEGMENTS_PER_REQUEST ||
!rb_next(&persistent_gnt->node)) {
ret = gnttab_unmap_refs(unmap, NULL, pages,
segs_to_unmap);
BUG_ON(ret);
free_xenballooned_pages(segs_to_unmap, pages);
segs_to_unmap = 0;
}
rb_erase(&persistent_gnt->node, root);
kfree(persistent_gnt);
num--;
}
BUG_ON(num != 0);
}
/*
* Retrieve from the 'pending_reqs' a free pending_req structure to be used.
*/
static struct pending_req *alloc_req(void)
{
struct pending_req *req = NULL;
unsigned long flags;
spin_lock_irqsave(&blkbk->pending_free_lock, flags);
if (!list_empty(&blkbk->pending_free)) {
req = list_entry(blkbk->pending_free.next, struct pending_req,
free_list);
list_del(&req->free_list);
}
spin_unlock_irqrestore(&blkbk->pending_free_lock, flags);
return req;
}
/*
* Return the 'pending_req' structure back to the freepool. We also
* wake up the thread if it was waiting for a free page.
*/
static void free_req(struct pending_req *req)
{
unsigned long flags;
int was_empty;
spin_lock_irqsave(&blkbk->pending_free_lock, flags);
was_empty = list_empty(&blkbk->pending_free);
list_add(&req->free_list, &blkbk->pending_free);
spin_unlock_irqrestore(&blkbk->pending_free_lock, flags);
if (was_empty)
wake_up(&blkbk->pending_free_wq);
}
/*
* Routines for managing virtual block devices (vbds).
*/
static int xen_vbd_translate(struct phys_req *req, struct xen_blkif *blkif,
int operation)
{
struct xen_vbd *vbd = &blkif->vbd;
int rc = -EACCES;
if ((operation != READ) && vbd->readonly)
goto out;
if (likely(req->nr_sects)) {
blkif_sector_t end = req->sector_number + req->nr_sects;
if (unlikely(end < req->sector_number))
goto out;
if (unlikely(end > vbd_sz(vbd)))
goto out;
}
req->dev = vbd->pdevice;
req->bdev = vbd->bdev;
rc = 0;
out:
return rc;
}
static void xen_vbd_resize(struct xen_blkif *blkif)
{
struct xen_vbd *vbd = &blkif->vbd;
struct xenbus_transaction xbt;
int err;
struct xenbus_device *dev = xen_blkbk_xenbus(blkif->be);
unsigned long long new_size = vbd_sz(vbd);
pr_info(DRV_PFX "VBD Resize: Domid: %d, Device: (%d, %d)\n",
blkif->domid, MAJOR(vbd->pdevice), MINOR(vbd->pdevice));
pr_info(DRV_PFX "VBD Resize: new size %llu\n", new_size);
vbd->size = new_size;
again:
err = xenbus_transaction_start(&xbt);
if (err) {
pr_warn(DRV_PFX "Error starting transaction");
return;
}
err = xenbus_printf(xbt, dev->nodename, "sectors", "%llu",
(unsigned long long)vbd_sz(vbd));
if (err) {
pr_warn(DRV_PFX "Error writing new size");
goto abort;
}
/*
* Write the current state; we will use this to synchronize
* the front-end. If the current state is "connected" the
* front-end will get the new size information online.
*/
err = xenbus_printf(xbt, dev->nodename, "state", "%d", dev->state);
if (err) {
pr_warn(DRV_PFX "Error writing the state");
goto abort;
}
err = xenbus_transaction_end(xbt, 0);
if (err == -EAGAIN)
goto again;
if (err)
pr_warn(DRV_PFX "Error ending transaction");
return;
abort:
xenbus_transaction_end(xbt, 1);
}
/*
* Notification from the guest OS.
*/
static void blkif_notify_work(struct xen_blkif *blkif)
{
blkif->waiting_reqs = 1;
wake_up(&blkif->wq);
}
irqreturn_t xen_blkif_be_int(int irq, void *dev_id)
{
blkif_notify_work(dev_id);
return IRQ_HANDLED;
}
/*
* SCHEDULER FUNCTIONS
*/
static void print_stats(struct xen_blkif *blkif)
{
pr_info("xen-blkback (%s): oo %3llu | rd %4llu | wr %4llu | f %4llu"
" | ds %4llu\n",
current->comm, blkif->st_oo_req,
blkif->st_rd_req, blkif->st_wr_req,
blkif->st_f_req, blkif->st_ds_req);
blkif->st_print = jiffies + msecs_to_jiffies(10 * 1000);
blkif->st_rd_req = 0;
blkif->st_wr_req = 0;
blkif->st_oo_req = 0;
blkif->st_ds_req = 0;
}
int xen_blkif_schedule(void *arg)
{
struct xen_blkif *blkif = arg;
struct xen_vbd *vbd = &blkif->vbd;
xen_blkif_get(blkif);
while (!kthread_should_stop()) {
if (try_to_freeze())
continue;
if (unlikely(vbd->size != vbd_sz(vbd)))
xen_vbd_resize(blkif);
wait_event_interruptible(
blkif->wq,
blkif->waiting_reqs || kthread_should_stop());
wait_event_interruptible(
blkbk->pending_free_wq,
!list_empty(&blkbk->pending_free) ||
kthread_should_stop());
blkif->waiting_reqs = 0;
smp_mb(); /* clear flag *before* checking for work */
if (do_block_io_op(blkif))
blkif->waiting_reqs = 1;
if (log_stats && time_after(jiffies, blkif->st_print))
print_stats(blkif);
}
/* Free all persistent grant pages */
if (!RB_EMPTY_ROOT(&blkif->persistent_gnts))
free_persistent_gnts(&blkif->persistent_gnts,
blkif->persistent_gnt_c);
BUG_ON(!RB_EMPTY_ROOT(&blkif->persistent_gnts));
blkif->persistent_gnt_c = 0;
if (log_stats)
print_stats(blkif);
blkif->xenblkd = NULL;
xen_blkif_put(blkif);
return 0;
}
struct seg_buf {
unsigned int offset;
unsigned int nsec;
};
/*
* Unmap the grant references, and also remove the M2P over-rides
* used in the 'pending_req'.
*/
static void xen_blkbk_unmap(struct pending_req *req)
{
struct gnttab_unmap_grant_ref unmap[BLKIF_MAX_SEGMENTS_PER_REQUEST];
struct page *pages[BLKIF_MAX_SEGMENTS_PER_REQUEST];
unsigned int i, invcount = 0;
grant_handle_t handle;
int ret;
for (i = 0; i < req->nr_pages; i++) {
if (!test_bit(i, req->unmap_seg))
continue;
handle = pending_handle(req, i);
if (handle == BLKBACK_INVALID_HANDLE)
continue;
gnttab_set_unmap_op(&unmap[invcount], vaddr(req, i),
GNTMAP_host_map, handle);
pending_handle(req, i) = BLKBACK_INVALID_HANDLE;
pages[invcount] = virt_to_page(vaddr(req, i));
invcount++;
}
ret = gnttab_unmap_refs(unmap, NULL, pages, invcount);
BUG_ON(ret);
}
static int xen_blkbk_map(struct blkif_request *req,
struct pending_req *pending_req,
struct seg_buf seg[],
struct page *pages[])
{
struct gnttab_map_grant_ref map[BLKIF_MAX_SEGMENTS_PER_REQUEST];
struct persistent_gnt *persistent_gnts[BLKIF_MAX_SEGMENTS_PER_REQUEST];
struct page *pages_to_gnt[BLKIF_MAX_SEGMENTS_PER_REQUEST];
struct persistent_gnt *persistent_gnt = NULL;
struct xen_blkif *blkif = pending_req->blkif;
phys_addr_t addr = 0;
int i, j;
bool new_map;
int nseg = req->u.rw.nr_segments;
int segs_to_map = 0;
int ret = 0;
int use_persistent_gnts;
use_persistent_gnts = (blkif->vbd.feature_gnt_persistent);
BUG_ON(blkif->persistent_gnt_c >
max_mapped_grant_pages(pending_req->blkif->blk_protocol));
/*
* Fill out preq.nr_sects with proper amount of sectors, and setup
* assign map[..] with the PFN of the page in our domain with the
* corresponding grant reference for each page.
*/
for (i = 0; i < nseg; i++) {
uint32_t flags;
if (use_persistent_gnts)
persistent_gnt = get_persistent_gnt(
&blkif->persistent_gnts,
req->u.rw.seg[i].gref);
if (persistent_gnt) {
/*
* We are using persistent grants and
* the grant is already mapped
*/
new_map = false;
} else if (use_persistent_gnts &&
blkif->persistent_gnt_c <
max_mapped_grant_pages(blkif->blk_protocol)) {
/*
* We are using persistent grants, the grant is
* not mapped but we have room for it
*/
new_map = true;
persistent_gnt = kmalloc(
sizeof(struct persistent_gnt),
GFP_KERNEL);
if (!persistent_gnt)
return -ENOMEM;
if (alloc_xenballooned_pages(1, &persistent_gnt->page,
false)) {
kfree(persistent_gnt);
return -ENOMEM;
}
persistent_gnt->gnt = req->u.rw.seg[i].gref;
persistent_gnt->handle = BLKBACK_INVALID_HANDLE;
pages_to_gnt[segs_to_map] =
persistent_gnt->page;
addr = (unsigned long) pfn_to_kaddr(
page_to_pfn(persistent_gnt->page));
add_persistent_gnt(&blkif->persistent_gnts,
persistent_gnt);
blkif->persistent_gnt_c++;
pr_debug(DRV_PFX " grant %u added to the tree of persistent grants, using %u/%u\n",
persistent_gnt->gnt, blkif->persistent_gnt_c,
max_mapped_grant_pages(blkif->blk_protocol));
} else {
/*
* We are either using persistent grants and
* hit the maximum limit of grants mapped,
* or we are not using persistent grants.
*/
if (use_persistent_gnts &&
!blkif->vbd.overflow_max_grants) {
blkif->vbd.overflow_max_grants = 1;
pr_alert(DRV_PFX " domain %u, device %#x is using maximum number of persistent grants\n",
blkif->domid, blkif->vbd.handle);
}
new_map = true;
pages[i] = blkbk->pending_page(pending_req, i);
addr = vaddr(pending_req, i);
pages_to_gnt[segs_to_map] =
blkbk->pending_page(pending_req, i);
}
if (persistent_gnt) {
pages[i] = persistent_gnt->page;
persistent_gnts[i] = persistent_gnt;
} else {
persistent_gnts[i] = NULL;
}
if (new_map) {
flags = GNTMAP_host_map;
if (!persistent_gnt &&
(pending_req->operation != BLKIF_OP_READ))
flags |= GNTMAP_readonly;
gnttab_set_map_op(&map[segs_to_map++], addr,
flags, req->u.rw.seg[i].gref,
blkif->domid);
}
}
if (segs_to_map) {
ret = gnttab_map_refs(map, NULL, pages_to_gnt, segs_to_map);
BUG_ON(ret);
}
/*
* Now swizzle the MFN in our domain with the MFN from the other domain
* so that when we access vaddr(pending_req,i) it has the contents of
* the page from the other domain.
*/
bitmap_zero(pending_req->unmap_seg, BLKIF_MAX_SEGMENTS_PER_REQUEST);
for (i = 0, j = 0; i < nseg; i++) {
if (!persistent_gnts[i] ||
persistent_gnts[i]->handle == BLKBACK_INVALID_HANDLE) {
/* This is a newly mapped grant */
BUG_ON(j >= segs_to_map);
if (unlikely(map[j].status != 0)) {
pr_debug(DRV_PFX "invalid buffer -- could not remap it\n");
map[j].handle = BLKBACK_INVALID_HANDLE;
ret |= 1;
if (persistent_gnts[i]) {
rb_erase(&persistent_gnts[i]->node,
&blkif->persistent_gnts);
blkif->persistent_gnt_c--;
kfree(persistent_gnts[i]);
persistent_gnts[i] = NULL;
}
}
}
if (persistent_gnts[i]) {
if (persistent_gnts[i]->handle ==
BLKBACK_INVALID_HANDLE) {
/*
* If this is a new persistent grant
* save the handler
*/
persistent_gnts[i]->handle = map[j++].handle;
}
pending_handle(pending_req, i) =
persistent_gnts[i]->handle;
if (ret)
continue;
} else {
pending_handle(pending_req, i) = map[j++].handle;
bitmap_set(pending_req->unmap_seg, i, 1);
if (ret)
continue;
}
seg[i].offset = (req->u.rw.seg[i].first_sect << 9);
}
return ret;
}
static int dispatch_discard_io(struct xen_blkif *blkif,
struct blkif_request *req)
{
int err = 0;
int status = BLKIF_RSP_OKAY;
struct block_device *bdev = blkif->vbd.bdev;
unsigned long secure;
struct phys_req preq;
xen_blkif_get(blkif);
preq.sector_number = req->u.discard.sector_number;
preq.nr_sects = req->u.discard.nr_sectors;
err = xen_vbd_translate(&preq, blkif, WRITE);
if (err) {
pr_warn(DRV_PFX "access denied: DISCARD [%llu->%llu] on dev=%04x\n",
preq.sector_number,
preq.sector_number + preq.nr_sects, blkif->vbd.pdevice);
goto fail_response;
}
blkif->st_ds_req++;
secure = (blkif->vbd.discard_secure &&
(req->u.discard.flag & BLKIF_DISCARD_SECURE)) ?
BLKDEV_DISCARD_SECURE : 0;
err = blkdev_issue_discard(bdev, req->u.discard.sector_number,
req->u.discard.nr_sectors,
GFP_KERNEL, secure);
fail_response:
if (err == -EOPNOTSUPP) {
pr_debug(DRV_PFX "discard op failed, not supported\n");
status = BLKIF_RSP_EOPNOTSUPP;
} else if (err)
status = BLKIF_RSP_ERROR;
make_response(blkif, req->u.discard.id, req->operation, status);
xen_blkif_put(blkif);
return err;
}
static int dispatch_other_io(struct xen_blkif *blkif,
struct blkif_request *req,
struct pending_req *pending_req)
{
free_req(pending_req);
make_response(blkif, req->u.other.id, req->operation,
BLKIF_RSP_EOPNOTSUPP);
return -EIO;
}
static void xen_blk_drain_io(struct xen_blkif *blkif)
{
atomic_set(&blkif->drain, 1);
do {
/* The initial value is one, and one refcnt taken at the
* start of the xen_blkif_schedule thread. */
if (atomic_read(&blkif->refcnt) <= 2)
break;
wait_for_completion_interruptible_timeout(
&blkif->drain_complete, HZ);
if (!atomic_read(&blkif->drain))
break;
} while (!kthread_should_stop());
atomic_set(&blkif->drain, 0);
}
/*
* Completion callback on the bio's. Called as bh->b_end_io()
*/
static void __end_block_io_op(struct pending_req *pending_req, int error)
{
/* An error fails the entire request. */
if ((pending_req->operation == BLKIF_OP_FLUSH_DISKCACHE) &&
(error == -EOPNOTSUPP)) {
pr_debug(DRV_PFX "flush diskcache op failed, not supported\n");
xen_blkbk_flush_diskcache(XBT_NIL, pending_req->blkif->be, 0);
pending_req->status = BLKIF_RSP_EOPNOTSUPP;
} else if ((pending_req->operation == BLKIF_OP_WRITE_BARRIER) &&
(error == -EOPNOTSUPP)) {
pr_debug(DRV_PFX "write barrier op failed, not supported\n");
xen_blkbk_barrier(XBT_NIL, pending_req->blkif->be, 0);
pending_req->status = BLKIF_RSP_EOPNOTSUPP;
} else if (error) {
pr_debug(DRV_PFX "Buffer not up-to-date at end of operation,"
" error=%d\n", error);
pending_req->status = BLKIF_RSP_ERROR;
}
/*
* If all of the bio's have completed it is time to unmap
* the grant references associated with 'request' and provide
* the proper response on the ring.
*/
if (atomic_dec_and_test(&pending_req->pendcnt)) {
xen_blkbk_unmap(pending_req);
make_response(pending_req->blkif, pending_req->id,
pending_req->operation, pending_req->status);
xen_blkif_put(pending_req->blkif);
if (atomic_read(&pending_req->blkif->refcnt) <= 2) {
if (atomic_read(&pending_req->blkif->drain))
complete(&pending_req->blkif->drain_complete);
}
free_req(pending_req);
}
}
/*
* bio callback.
*/
static void end_block_io_op(struct bio *bio, int error)
{
__end_block_io_op(bio->bi_private, error);
bio_put(bio);
}
/*
* Function to copy the from the ring buffer the 'struct blkif_request'
* (which has the sectors we want, number of them, grant references, etc),
* and transmute it to the block API to hand it over to the proper block disk.
*/
static int
__do_block_io_op(struct xen_blkif *blkif)
{
union blkif_back_rings *blk_rings = &blkif->blk_rings;
struct blkif_request req;
struct pending_req *pending_req;
RING_IDX rc, rp;
int more_to_do = 0;
rc = blk_rings->common.req_cons;
rp = blk_rings->common.sring->req_prod;
rmb(); /* Ensure we see queued requests up to 'rp'. */
while (rc != rp) {
if (RING_REQUEST_CONS_OVERFLOW(&blk_rings->common, rc))
break;
if (kthread_should_stop()) {
more_to_do = 1;
break;
}
pending_req = alloc_req();
if (NULL == pending_req) {
blkif->st_oo_req++;
more_to_do = 1;
break;
}
switch (blkif->blk_protocol) {
case BLKIF_PROTOCOL_NATIVE:
memcpy(&req, RING_GET_REQUEST(&blk_rings->native, rc), sizeof(req));
break;
case BLKIF_PROTOCOL_X86_32:
blkif_get_x86_32_req(&req, RING_GET_REQUEST(&blk_rings->x86_32, rc));
break;
case BLKIF_PROTOCOL_X86_64:
blkif_get_x86_64_req(&req, RING_GET_REQUEST(&blk_rings->x86_64, rc));
break;
default:
BUG();
}
blk_rings->common.req_cons = ++rc; /* before make_response() */
/* Apply all sanity checks to /private copy/ of request. */
barrier();
switch (req.operation) {
case BLKIF_OP_READ:
case BLKIF_OP_WRITE:
case BLKIF_OP_WRITE_BARRIER:
case BLKIF_OP_FLUSH_DISKCACHE:
if (dispatch_rw_block_io(blkif, &req, pending_req))
goto done;
break;
case BLKIF_OP_DISCARD:
free_req(pending_req);
if (dispatch_discard_io(blkif, &req))
goto done;
break;
default:
if (dispatch_other_io(blkif, &req, pending_req))
goto done;
break;
}
/* Yield point for this unbounded loop. */
cond_resched();
}
done:
return more_to_do;
}
static int
do_block_io_op(struct xen_blkif *blkif)
{
union blkif_back_rings *blk_rings = &blkif->blk_rings;
int more_to_do;
do {
more_to_do = __do_block_io_op(blkif);
if (more_to_do)
break;
RING_FINAL_CHECK_FOR_REQUESTS(&blk_rings->common, more_to_do);
} while (more_to_do);
return more_to_do;
}
/*
* Transmutation of the 'struct blkif_request' to a proper 'struct bio'
* and call the 'submit_bio' to pass it to the underlying storage.
*/
static int dispatch_rw_block_io(struct xen_blkif *blkif,
struct blkif_request *req,
struct pending_req *pending_req)
{
struct phys_req preq;
struct seg_buf seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
unsigned int nseg;
struct bio *bio = NULL;
struct bio *biolist[BLKIF_MAX_SEGMENTS_PER_REQUEST];
int i, nbio = 0;
int operation;
struct blk_plug plug;
bool drain = false;
struct page *pages[BLKIF_MAX_SEGMENTS_PER_REQUEST];
switch (req->operation) {
case BLKIF_OP_READ:
blkif->st_rd_req++;
operation = READ;
break;
case BLKIF_OP_WRITE:
blkif->st_wr_req++;
operation = WRITE_ODIRECT;
break;
case BLKIF_OP_WRITE_BARRIER:
drain = true;
case BLKIF_OP_FLUSH_DISKCACHE:
blkif->st_f_req++;
operation = WRITE_FLUSH;
break;
default:
operation = 0; /* make gcc happy */
goto fail_response;
break;
}
/* Check that the number of segments is sane. */
nseg = req->u.rw.nr_segments;
if (unlikely(nseg == 0 && operation != WRITE_FLUSH) ||
unlikely(nseg > BLKIF_MAX_SEGMENTS_PER_REQUEST)) {
pr_debug(DRV_PFX "Bad number of segments in request (%d)\n",
nseg);
/* Haven't submitted any bio's yet. */
goto fail_response;
}
preq.sector_number = req->u.rw.sector_number;
preq.nr_sects = 0;
pending_req->blkif = blkif;
pending_req->id = req->u.rw.id;
pending_req->operation = req->operation;
pending_req->status = BLKIF_RSP_OKAY;
pending_req->nr_pages = nseg;
for (i = 0; i < nseg; i++) {
seg[i].nsec = req->u.rw.seg[i].last_sect -
req->u.rw.seg[i].first_sect + 1;
if ((req->u.rw.seg[i].last_sect >= (PAGE_SIZE >> 9)) ||
(req->u.rw.seg[i].last_sect < req->u.rw.seg[i].first_sect))
goto fail_response;
preq.nr_sects += seg[i].nsec;
}
if (xen_vbd_translate(&preq, blkif, operation) != 0) {
pr_debug(DRV_PFX "access denied: %s of [%llu,%llu] on dev=%04x\n",
operation == READ ? "read" : "write",
preq.sector_number,
preq.sector_number + preq.nr_sects,
blkif->vbd.pdevice);
goto fail_response;
}
/*
* This check _MUST_ be done after xen_vbd_translate as the preq.bdev
* is set there.
*/
for (i = 0; i < nseg; i++) {
if (((int)preq.sector_number|(int)seg[i].nsec) &
((bdev_logical_block_size(preq.bdev) >> 9) - 1)) {
pr_debug(DRV_PFX "Misaligned I/O request from domain %d",
blkif->domid);
goto fail_response;
}
}
/* Wait on all outstanding I/O's and once that has been completed
* issue the WRITE_FLUSH.
*/
if (drain)
xen_blk_drain_io(pending_req->blkif);
/*
* If we have failed at this point, we need to undo the M2P override,
* set gnttab_set_unmap_op on all of the grant references and perform
* the hypercall to unmap the grants - that is all done in
* xen_blkbk_unmap.
*/
if (xen_blkbk_map(req, pending_req, seg, pages))
goto fail_flush;
/*
* This corresponding xen_blkif_put is done in __end_block_io_op, or
* below (in "!bio") if we are handling a BLKIF_OP_DISCARD.
*/
xen_blkif_get(blkif);
for (i = 0; i < nseg; i++) {
while ((bio == NULL) ||
(bio_add_page(bio,
pages[i],
seg[i].nsec << 9,
seg[i].offset) == 0)) {
bio = bio_alloc(GFP_KERNEL, nseg-i);
if (unlikely(bio == NULL))
goto fail_put_bio;
biolist[nbio++] = bio;
bio->bi_bdev = preq.bdev;
bio->bi_private = pending_req;
bio->bi_end_io = end_block_io_op;
bio->bi_sector = preq.sector_number;
}
preq.sector_number += seg[i].nsec;
}
/* This will be hit if the operation was a flush or discard. */
if (!bio) {
BUG_ON(operation != WRITE_FLUSH);
bio = bio_alloc(GFP_KERNEL, 0);
if (unlikely(bio == NULL))
goto fail_put_bio;
biolist[nbio++] = bio;
bio->bi_bdev = preq.bdev;
bio->bi_private = pending_req;
bio->bi_end_io = end_block_io_op;
}
atomic_set(&pending_req->pendcnt, nbio);
blk_start_plug(&plug);
for (i = 0; i < nbio; i++)
submit_bio(operation, biolist[i]);
/* Let the I/Os go.. */
blk_finish_plug(&plug);
if (operation == READ)
blkif->st_rd_sect += preq.nr_sects;
else if (operation & WRITE)
blkif->st_wr_sect += preq.nr_sects;
return 0;
fail_flush:
xen_blkbk_unmap(pending_req);
fail_response:
/* Haven't submitted any bio's yet. */
make_response(blkif, req->u.rw.id, req->operation, BLKIF_RSP_ERROR);
free_req(pending_req);
msleep(1); /* back off a bit */
return -EIO;
fail_put_bio:
for (i = 0; i < nbio; i++)
bio_put(biolist[i]);
atomic_set(&pending_req->pendcnt, 1);
__end_block_io_op(pending_req, -EINVAL);
msleep(1); /* back off a bit */
return -EIO;
}
/*
* Put a response on the ring on how the operation fared.
*/
static void make_response(struct xen_blkif *blkif, u64 id,
unsigned short op, int st)
{
struct blkif_response resp;
unsigned long flags;
union blkif_back_rings *blk_rings = &blkif->blk_rings;
int notify;
resp.id = id;
resp.operation = op;
resp.status = st;
spin_lock_irqsave(&blkif->blk_ring_lock, flags);
/* Place on the response ring for the relevant domain. */
switch (blkif->blk_protocol) {
case BLKIF_PROTOCOL_NATIVE:
memcpy(RING_GET_RESPONSE(&blk_rings->native, blk_rings->native.rsp_prod_pvt),
&resp, sizeof(resp));
break;
case BLKIF_PROTOCOL_X86_32:
memcpy(RING_GET_RESPONSE(&blk_rings->x86_32, blk_rings->x86_32.rsp_prod_pvt),
&resp, sizeof(resp));
break;
case BLKIF_PROTOCOL_X86_64:
memcpy(RING_GET_RESPONSE(&blk_rings->x86_64, blk_rings->x86_64.rsp_prod_pvt),
&resp, sizeof(resp));
break;
default:
BUG();
}
blk_rings->common.rsp_prod_pvt++;
RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&blk_rings->common, notify);
spin_unlock_irqrestore(&blkif->blk_ring_lock, flags);
if (notify)
notify_remote_via_irq(blkif->irq);
}
static int __init xen_blkif_init(void)
{
int i, mmap_pages;
int rc = 0;
if (!xen_domain())
return -ENODEV;
blkbk = kzalloc(sizeof(struct xen_blkbk), GFP_KERNEL);
if (!blkbk) {
pr_alert(DRV_PFX "%s: out of memory!\n", __func__);
return -ENOMEM;
}
mmap_pages = xen_blkif_reqs * BLKIF_MAX_SEGMENTS_PER_REQUEST;
blkbk->pending_reqs = kzalloc(sizeof(blkbk->pending_reqs[0]) *
xen_blkif_reqs, GFP_KERNEL);
blkbk->pending_grant_handles = kmalloc(sizeof(blkbk->pending_grant_handles[0]) *
mmap_pages, GFP_KERNEL);
blkbk->pending_pages = kzalloc(sizeof(blkbk->pending_pages[0]) *
mmap_pages, GFP_KERNEL);
if (!blkbk->pending_reqs || !blkbk->pending_grant_handles ||
!blkbk->pending_pages) {
rc = -ENOMEM;
goto out_of_memory;
}
for (i = 0; i < mmap_pages; i++) {
blkbk->pending_grant_handles[i] = BLKBACK_INVALID_HANDLE;
blkbk->pending_pages[i] = alloc_page(GFP_KERNEL);
if (blkbk->pending_pages[i] == NULL) {
rc = -ENOMEM;
goto out_of_memory;
}
}
rc = xen_blkif_interface_init();
if (rc)
goto failed_init;
INIT_LIST_HEAD(&blkbk->pending_free);
spin_lock_init(&blkbk->pending_free_lock);
init_waitqueue_head(&blkbk->pending_free_wq);
for (i = 0; i < xen_blkif_reqs; i++)
list_add_tail(&blkbk->pending_reqs[i].free_list,
&blkbk->pending_free);
rc = xen_blkif_xenbus_init();
if (rc)
goto failed_init;
return 0;
out_of_memory:
pr_alert(DRV_PFX "%s: out of memory\n", __func__);
failed_init:
kfree(blkbk->pending_reqs);
kfree(blkbk->pending_grant_handles);
if (blkbk->pending_pages) {
for (i = 0; i < mmap_pages; i++) {
if (blkbk->pending_pages[i])
__free_page(blkbk->pending_pages[i]);
}
kfree(blkbk->pending_pages);
}
kfree(blkbk);
blkbk = NULL;
return rc;
}
module_init(xen_blkif_init);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("xen-backend:vbd");
| gpl-2.0 |
PennPanda/litmus-rt | arch/mips/ath79/clock.c | 1877 | 12954 | /*
* Atheros AR71XX/AR724X/AR913X common routines
*
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/div64.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 5000000
#define AR913X_BASE_FREQ 5000000
struct clk {
unsigned long rate;
};
static struct clk ath79_ref_clk;
static struct clk ath79_cpu_clk;
static struct clk ath79_ddr_clk;
static struct clk ath79_ahb_clk;
static struct clk ath79_wdt_clk;
static struct clk ath79_uart_clk;
static void __init ar71xx_clocks_init(void)
{
u32 pll;
u32 freq;
u32 div;
ath79_ref_clk.rate = AR71XX_BASE_FREQ;
pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
freq = div * ath79_ref_clk.rate;
div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
ath79_cpu_clk.rate = freq / div;
div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
ath79_ddr_clk.rate = freq / div;
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
ath79_uart_clk.rate = ath79_ahb_clk.rate;
}
static void __init ar724x_clocks_init(void)
{
u32 pll;
u32 freq;
u32 div;
ath79_ref_clk.rate = AR724X_BASE_FREQ;
pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
freq = div * ath79_ref_clk.rate;
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
freq *= div;
ath79_cpu_clk.rate = freq;
div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ath79_ddr_clk.rate = freq / div;
div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
ath79_uart_clk.rate = ath79_ahb_clk.rate;
}
static void __init ar913x_clocks_init(void)
{
u32 pll;
u32 freq;
u32 div;
ath79_ref_clk.rate = AR913X_BASE_FREQ;
pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
freq = div * ath79_ref_clk.rate;
ath79_cpu_clk.rate = freq;
div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
ath79_ddr_clk.rate = freq / div;
div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
ath79_uart_clk.rate = ath79_ahb_clk.rate;
}
static void __init ar933x_clocks_init(void)
{
u32 clock_ctrl;
u32 cpu_config;
u32 freq;
u32 t;
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
ath79_ref_clk.rate = (40 * 1000 * 1000);
else
ath79_ref_clk.rate = (25 * 1000 * 1000);
clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
ath79_cpu_clk.rate = ath79_ref_clk.rate;
ath79_ahb_clk.rate = ath79_ref_clk.rate;
ath79_ddr_clk.rate = ath79_ref_clk.rate;
} else {
cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
freq = ath79_ref_clk.rate / t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR933X_PLL_CPU_CONFIG_NINT_MASK;
freq *= t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
if (t == 0)
t = 1;
freq >>= t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
ath79_cpu_clk.rate = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
ath79_ddr_clk.rate = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
ath79_ahb_clk.rate = freq / t;
}
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
ath79_uart_clk.rate = ath79_ref_clk.rate;
}
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
u32 frac, u32 out_div)
{
u64 t;
u32 ret;
t = ath79_ref_clk.rate;
t *= nint;
do_div(t, ref_div);
ret = t;
t = ath79_ref_clk.rate;
t *= nfrac;
do_div(t, ref_div * frac);
ret += t;
ret /= (1 << out_div);
return ret;
}
static void __init ar934x_clocks_init(void)
{
u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
u32 bootstrap;
void __iomem *dpll_base;
dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
ath79_ref_clk.rate = 40 * 1000 * 1000;
else
ath79_ref_clk.rate = 25 * 1000 * 1000;
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
AR934X_SRIF_DPLL2_OUTDIV_MASK;
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
AR934X_SRIF_DPLL1_NINT_MASK;
nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR934X_PLL_CPU_CONFIG_NINT_MASK;
nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
frac = 1 << 6;
}
cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
nfrac, frac, out_div);
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
AR934X_SRIF_DPLL2_OUTDIV_MASK;
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
AR934X_SRIF_DPLL1_NINT_MASK;
nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
AR934X_PLL_DDR_CONFIG_NINT_MASK;
nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
frac = 1 << 10;
}
ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
nfrac, frac, out_div);
clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
ath79_cpu_clk.rate = ath79_ref_clk.rate;
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
else
ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
ath79_ddr_clk.rate = ath79_ref_clk.rate;
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
else
ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
ath79_ahb_clk.rate = ath79_ref_clk.rate;
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
else
ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
ath79_wdt_clk.rate = ath79_ref_clk.rate;
ath79_uart_clk.rate = ath79_ref_clk.rate;
iounmap(dpll_base);
}
static void __init qca955x_clocks_init(void)
{
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
u32 bootstrap;
bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
ath79_ref_clk.rate = 40 * 1000 * 1000;
else
ath79_ref_clk.rate = 25 * 1000 * 1000;
pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
QCA955X_PLL_CPU_CONFIG_NINT_MASK;
frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
cpu_pll = nint * ath79_ref_clk.rate / ref_div;
cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
cpu_pll /= (1 << out_div);
pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
QCA955X_PLL_DDR_CONFIG_NINT_MASK;
frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
ddr_pll = nint * ath79_ref_clk.rate / ref_div;
ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
ddr_pll /= (1 << out_div);
clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
ath79_cpu_clk.rate = ath79_ref_clk.rate;
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
else
ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ath79_ddr_clk.rate = ath79_ref_clk.rate;
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
else
ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ath79_ahb_clk.rate = ath79_ref_clk.rate;
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
else
ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
ath79_wdt_clk.rate = ath79_ref_clk.rate;
ath79_uart_clk.rate = ath79_ref_clk.rate;
}
void __init ath79_clocks_init(void)
{
if (soc_is_ar71xx())
ar71xx_clocks_init();
else if (soc_is_ar724x())
ar724x_clocks_init();
else if (soc_is_ar913x())
ar913x_clocks_init();
else if (soc_is_ar933x())
ar933x_clocks_init();
else if (soc_is_ar934x())
ar934x_clocks_init();
else if (soc_is_qca955x())
qca955x_clocks_init();
else
BUG();
pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "
"Ref:%lu.%03luMHz",
ath79_cpu_clk.rate / 1000000,
(ath79_cpu_clk.rate / 1000) % 1000,
ath79_ddr_clk.rate / 1000000,
(ath79_ddr_clk.rate / 1000) % 1000,
ath79_ahb_clk.rate / 1000000,
(ath79_ahb_clk.rate / 1000) % 1000,
ath79_ref_clk.rate / 1000000,
(ath79_ref_clk.rate / 1000) % 1000);
}
/*
* Linux clock API
*/
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "ref"))
return &ath79_ref_clk;
if (!strcmp(id, "cpu"))
return &ath79_cpu_clk;
if (!strcmp(id, "ddr"))
return &ath79_ddr_clk;
if (!strcmp(id, "ahb"))
return &ath79_ahb_clk;
if (!strcmp(id, "wdt"))
return &ath79_wdt_clk;
if (!strcmp(id, "uart"))
return &ath79_uart_clk;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
| gpl-2.0 |
crewrktablets/android_kernel_odys_neox_3.0.8 | net/irda/irlan/irlan_provider.c | 2389 | 11183 | /*********************************************************************
*
* Filename: irlan_provider.c
* Version: 0.9
* Description: IrDA LAN Access Protocol Implementation
* Status: Experimental.
* Author: Dag Brattli <dagb@cs.uit.no>
* Created at: Sun Aug 31 20:14:37 1997
* Modified at: Sat Oct 30 12:52:10 1999
* Modified by: Dag Brattli <dagb@cs.uit.no>
* Sources: skeleton.c by Donald Becker <becker@CESDIS.gsfc.nasa.gov>
* slip.c by Laurence Culhane, <loz@holmes.demon.co.uk>
* Fred N. van Kempen, <waltje@uwalt.nl.mugnet.org>
*
* Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Neither Dag Brattli nor University of Tromsø admit liability nor
* provide warranty for any of this software. This material is
* provided "AS-IS" and at no charge.
*
********************************************************************/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/random.h>
#include <linux/bitops.h>
#include <linux/slab.h>
#include <asm/system.h>
#include <asm/byteorder.h>
#include <net/irda/irda.h>
#include <net/irda/irttp.h>
#include <net/irda/irlmp.h>
#include <net/irda/irias_object.h>
#include <net/irda/iriap.h>
#include <net/irda/timer.h>
#include <net/irda/irlan_common.h>
#include <net/irda/irlan_eth.h>
#include <net/irda/irlan_event.h>
#include <net/irda/irlan_provider.h>
#include <net/irda/irlan_filter.h>
#include <net/irda/irlan_client.h>
static void irlan_provider_connect_indication(void *instance, void *sap,
struct qos_info *qos,
__u32 max_sdu_size,
__u8 max_header_size,
struct sk_buff *skb);
/*
* Function irlan_provider_control_data_indication (handle, skb)
*
* This function gets the data that is received on the control channel
*
*/
static int irlan_provider_data_indication(void *instance, void *sap,
struct sk_buff *skb)
{
struct irlan_cb *self;
__u8 code;
IRDA_DEBUG(4, "%s()\n", __func__ );
self = (struct irlan_cb *) instance;
IRDA_ASSERT(self != NULL, return -1;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return -1;);
IRDA_ASSERT(skb != NULL, return -1;);
code = skb->data[0];
switch(code) {
case CMD_GET_PROVIDER_INFO:
IRDA_DEBUG(4, "Got GET_PROVIDER_INFO command!\n");
irlan_do_provider_event(self, IRLAN_GET_INFO_CMD, skb);
break;
case CMD_GET_MEDIA_CHAR:
IRDA_DEBUG(4, "Got GET_MEDIA_CHAR command!\n");
irlan_do_provider_event(self, IRLAN_GET_MEDIA_CMD, skb);
break;
case CMD_OPEN_DATA_CHANNEL:
IRDA_DEBUG(4, "Got OPEN_DATA_CHANNEL command!\n");
irlan_do_provider_event(self, IRLAN_OPEN_DATA_CMD, skb);
break;
case CMD_FILTER_OPERATION:
IRDA_DEBUG(4, "Got FILTER_OPERATION command!\n");
irlan_do_provider_event(self, IRLAN_FILTER_CONFIG_CMD, skb);
break;
case CMD_RECONNECT_DATA_CHAN:
IRDA_DEBUG(2, "%s(), Got RECONNECT_DATA_CHAN command\n", __func__ );
IRDA_DEBUG(2, "%s(), NOT IMPLEMENTED\n", __func__ );
break;
case CMD_CLOSE_DATA_CHAN:
IRDA_DEBUG(2, "Got CLOSE_DATA_CHAN command!\n");
IRDA_DEBUG(2, "%s(), NOT IMPLEMENTED\n", __func__ );
break;
default:
IRDA_DEBUG(2, "%s(), Unknown command!\n", __func__ );
break;
}
return 0;
}
/*
* Function irlan_provider_connect_indication (handle, skb, priv)
*
* Got connection from peer IrLAN client
*
*/
static void irlan_provider_connect_indication(void *instance, void *sap,
struct qos_info *qos,
__u32 max_sdu_size,
__u8 max_header_size,
struct sk_buff *skb)
{
struct irlan_cb *self;
struct tsap_cb *tsap;
IRDA_DEBUG(0, "%s()\n", __func__ );
self = (struct irlan_cb *) instance;
tsap = (struct tsap_cb *) sap;
IRDA_ASSERT(self != NULL, return;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return;);
IRDA_ASSERT(tsap == self->provider.tsap_ctrl,return;);
IRDA_ASSERT(self->provider.state == IRLAN_IDLE, return;);
self->provider.max_sdu_size = max_sdu_size;
self->provider.max_header_size = max_header_size;
irlan_do_provider_event(self, IRLAN_CONNECT_INDICATION, NULL);
/*
* If we are in peer mode, the client may not have got the discovery
* indication it needs to make progress. If the client is still in
* IDLE state, we must kick it.
*/
if ((self->provider.access_type == ACCESS_PEER) &&
(self->client.state == IRLAN_IDLE))
{
irlan_client_wakeup(self, self->saddr, self->daddr);
}
}
/*
* Function irlan_provider_connect_response (handle)
*
* Accept incoming connection
*
*/
void irlan_provider_connect_response(struct irlan_cb *self,
struct tsap_cb *tsap)
{
IRDA_ASSERT(self != NULL, return;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return;);
/* Just accept */
irttp_connect_response(tsap, IRLAN_MTU, NULL);
}
static void irlan_provider_disconnect_indication(void *instance, void *sap,
LM_REASON reason,
struct sk_buff *userdata)
{
struct irlan_cb *self;
struct tsap_cb *tsap;
IRDA_DEBUG(4, "%s(), reason=%d\n", __func__ , reason);
self = (struct irlan_cb *) instance;
tsap = (struct tsap_cb *) sap;
IRDA_ASSERT(self != NULL, return;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return;);
IRDA_ASSERT(tsap != NULL, return;);
IRDA_ASSERT(tsap->magic == TTP_TSAP_MAGIC, return;);
IRDA_ASSERT(tsap == self->provider.tsap_ctrl, return;);
irlan_do_provider_event(self, IRLAN_LMP_DISCONNECT, NULL);
}
/*
* Function irlan_parse_open_data_cmd (self, skb)
*
*
*
*/
int irlan_parse_open_data_cmd(struct irlan_cb *self, struct sk_buff *skb)
{
int ret;
ret = irlan_provider_parse_command(self, CMD_OPEN_DATA_CHANNEL, skb);
/* Open data channel */
irlan_open_data_tsap(self);
return ret;
}
/*
* Function parse_command (skb)
*
* Extract all parameters from received buffer, then feed them to
* check_params for parsing
*
*/
int irlan_provider_parse_command(struct irlan_cb *self, int cmd,
struct sk_buff *skb)
{
__u8 *frame;
__u8 *ptr;
int count;
__u16 val_len;
int i;
char *name;
char *value;
int ret = RSP_SUCCESS;
IRDA_ASSERT(skb != NULL, return -RSP_PROTOCOL_ERROR;);
IRDA_DEBUG(4, "%s(), skb->len=%d\n", __func__ , (int)skb->len);
IRDA_ASSERT(self != NULL, return -RSP_PROTOCOL_ERROR;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return -RSP_PROTOCOL_ERROR;);
if (!skb)
return -RSP_PROTOCOL_ERROR;
frame = skb->data;
name = kmalloc(255, GFP_ATOMIC);
if (!name)
return -RSP_INSUFFICIENT_RESOURCES;
value = kmalloc(1016, GFP_ATOMIC);
if (!value) {
kfree(name);
return -RSP_INSUFFICIENT_RESOURCES;
}
/* How many parameters? */
count = frame[1];
IRDA_DEBUG(4, "Got %d parameters\n", count);
ptr = frame+2;
/* For all parameters */
for (i=0; i<count;i++) {
ret = irlan_extract_param(ptr, name, value, &val_len);
if (ret < 0) {
IRDA_DEBUG(2, "%s(), IrLAN, Error!\n", __func__ );
break;
}
ptr+=ret;
ret = RSP_SUCCESS;
irlan_check_command_param(self, name, value);
}
/* Cleanup */
kfree(name);
kfree(value);
return ret;
}
/*
* Function irlan_provider_send_reply (self, info)
*
* Send reply to query to peer IrLAN layer
*
*/
void irlan_provider_send_reply(struct irlan_cb *self, int command,
int ret_code)
{
struct sk_buff *skb;
IRDA_DEBUG(4, "%s()\n", __func__ );
IRDA_ASSERT(self != NULL, return;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return;);
skb = alloc_skb(IRLAN_MAX_HEADER + IRLAN_CMD_HEADER +
/* Bigger param length comes from CMD_GET_MEDIA_CHAR */
IRLAN_STRING_PARAMETER_LEN("FILTER_TYPE", "DIRECTED") +
IRLAN_STRING_PARAMETER_LEN("FILTER_TYPE", "BORADCAST") +
IRLAN_STRING_PARAMETER_LEN("FILTER_TYPE", "MULTICAST") +
IRLAN_STRING_PARAMETER_LEN("ACCESS_TYPE", "HOSTED"),
GFP_ATOMIC);
if (!skb)
return;
/* Reserve space for TTP, LMP, and LAP header */
skb_reserve(skb, self->provider.max_header_size);
skb_put(skb, 2);
switch (command) {
case CMD_GET_PROVIDER_INFO:
skb->data[0] = 0x00; /* Success */
skb->data[1] = 0x02; /* 2 parameters */
switch (self->media) {
case MEDIA_802_3:
irlan_insert_string_param(skb, "MEDIA", "802.3");
break;
case MEDIA_802_5:
irlan_insert_string_param(skb, "MEDIA", "802.5");
break;
default:
IRDA_DEBUG(2, "%s(), unknown media type!\n", __func__ );
break;
}
irlan_insert_short_param(skb, "IRLAN_VER", 0x0101);
break;
case CMD_GET_MEDIA_CHAR:
skb->data[0] = 0x00; /* Success */
skb->data[1] = 0x05; /* 5 parameters */
irlan_insert_string_param(skb, "FILTER_TYPE", "DIRECTED");
irlan_insert_string_param(skb, "FILTER_TYPE", "BROADCAST");
irlan_insert_string_param(skb, "FILTER_TYPE", "MULTICAST");
switch (self->provider.access_type) {
case ACCESS_DIRECT:
irlan_insert_string_param(skb, "ACCESS_TYPE", "DIRECT");
break;
case ACCESS_PEER:
irlan_insert_string_param(skb, "ACCESS_TYPE", "PEER");
break;
case ACCESS_HOSTED:
irlan_insert_string_param(skb, "ACCESS_TYPE", "HOSTED");
break;
default:
IRDA_DEBUG(2, "%s(), Unknown access type\n", __func__ );
break;
}
irlan_insert_short_param(skb, "MAX_FRAME", 0x05ee);
break;
case CMD_OPEN_DATA_CHANNEL:
skb->data[0] = 0x00; /* Success */
if (self->provider.send_arb_val) {
skb->data[1] = 0x03; /* 3 parameters */
irlan_insert_short_param(skb, "CON_ARB",
self->provider.send_arb_val);
} else
skb->data[1] = 0x02; /* 2 parameters */
irlan_insert_byte_param(skb, "DATA_CHAN", self->stsap_sel_data);
irlan_insert_string_param(skb, "RECONNECT_KEY", "LINUX RULES!");
break;
case CMD_FILTER_OPERATION:
irlan_filter_request(self, skb);
break;
default:
IRDA_DEBUG(2, "%s(), Unknown command!\n", __func__ );
break;
}
irttp_data_request(self->provider.tsap_ctrl, skb);
}
/*
* Function irlan_provider_register(void)
*
* Register provider support so we can accept incoming connections.
*
*/
int irlan_provider_open_ctrl_tsap(struct irlan_cb *self)
{
struct tsap_cb *tsap;
notify_t notify;
IRDA_DEBUG(4, "%s()\n", __func__ );
IRDA_ASSERT(self != NULL, return -1;);
IRDA_ASSERT(self->magic == IRLAN_MAGIC, return -1;);
/* Check if already open */
if (self->provider.tsap_ctrl)
return -1;
/*
* First register well known control TSAP
*/
irda_notify_init(¬ify);
notify.data_indication = irlan_provider_data_indication;
notify.connect_indication = irlan_provider_connect_indication;
notify.disconnect_indication = irlan_provider_disconnect_indication;
notify.instance = self;
strlcpy(notify.name, "IrLAN ctrl (p)", sizeof(notify.name));
tsap = irttp_open_tsap(LSAP_ANY, 1, ¬ify);
if (!tsap) {
IRDA_DEBUG(2, "%s(), Got no tsap!\n", __func__ );
return -1;
}
self->provider.tsap_ctrl = tsap;
/* Register with LM-IAS */
irlan_ias_register(self, tsap->stsap_sel);
return 0;
}
| gpl-2.0 |
sony-omni/android_kernel_caf_msm8x26 | net/caif/cfctrl.c | 2389 | 16228 | /*
* Copyright (C) ST-Ericsson AB 2010
* Author: Sjur Brendeland
* License terms: GNU General Public License (GPL) version 2
*/
#define pr_fmt(fmt) KBUILD_MODNAME ":%s(): " fmt, __func__
#include <linux/stddef.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/pkt_sched.h>
#include <net/caif/caif_layer.h>
#include <net/caif/cfpkt.h>
#include <net/caif/cfctrl.h>
#define container_obj(layr) container_of(layr, struct cfctrl, serv.layer)
#define UTILITY_NAME_LENGTH 16
#define CFPKT_CTRL_PKT_LEN 20
#ifdef CAIF_NO_LOOP
static int handle_loop(struct cfctrl *ctrl,
int cmd, struct cfpkt *pkt){
return -1;
}
#else
static int handle_loop(struct cfctrl *ctrl,
int cmd, struct cfpkt *pkt);
#endif
static int cfctrl_recv(struct cflayer *layr, struct cfpkt *pkt);
static void cfctrl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl,
int phyid);
struct cflayer *cfctrl_create(void)
{
struct dev_info dev_info;
struct cfctrl *this =
kzalloc(sizeof(struct cfctrl), GFP_ATOMIC);
if (!this)
return NULL;
caif_assert(offsetof(struct cfctrl, serv.layer) == 0);
memset(&dev_info, 0, sizeof(dev_info));
dev_info.id = 0xff;
cfsrvl_init(&this->serv, 0, &dev_info, false);
atomic_set(&this->req_seq_no, 1);
atomic_set(&this->rsp_seq_no, 1);
this->serv.layer.receive = cfctrl_recv;
sprintf(this->serv.layer.name, "ctrl");
this->serv.layer.ctrlcmd = cfctrl_ctrlcmd;
#ifndef CAIF_NO_LOOP
spin_lock_init(&this->loop_linkid_lock);
this->loop_linkid = 1;
#endif
spin_lock_init(&this->info_list_lock);
INIT_LIST_HEAD(&this->list);
return &this->serv.layer;
}
void cfctrl_remove(struct cflayer *layer)
{
struct cfctrl_request_info *p, *tmp;
struct cfctrl *ctrl = container_obj(layer);
spin_lock_bh(&ctrl->info_list_lock);
list_for_each_entry_safe(p, tmp, &ctrl->list, list) {
list_del(&p->list);
kfree(p);
}
spin_unlock_bh(&ctrl->info_list_lock);
kfree(layer);
}
static bool param_eq(const struct cfctrl_link_param *p1,
const struct cfctrl_link_param *p2)
{
bool eq =
p1->linktype == p2->linktype &&
p1->priority == p2->priority &&
p1->phyid == p2->phyid &&
p1->endpoint == p2->endpoint && p1->chtype == p2->chtype;
if (!eq)
return false;
switch (p1->linktype) {
case CFCTRL_SRV_VEI:
return true;
case CFCTRL_SRV_DATAGRAM:
return p1->u.datagram.connid == p2->u.datagram.connid;
case CFCTRL_SRV_RFM:
return
p1->u.rfm.connid == p2->u.rfm.connid &&
strcmp(p1->u.rfm.volume, p2->u.rfm.volume) == 0;
case CFCTRL_SRV_UTIL:
return
p1->u.utility.fifosize_kb == p2->u.utility.fifosize_kb
&& p1->u.utility.fifosize_bufs ==
p2->u.utility.fifosize_bufs
&& strcmp(p1->u.utility.name, p2->u.utility.name) == 0
&& p1->u.utility.paramlen == p2->u.utility.paramlen
&& memcmp(p1->u.utility.params, p2->u.utility.params,
p1->u.utility.paramlen) == 0;
case CFCTRL_SRV_VIDEO:
return p1->u.video.connid == p2->u.video.connid;
case CFCTRL_SRV_DBG:
return true;
case CFCTRL_SRV_DECM:
return false;
default:
return false;
}
return false;
}
static bool cfctrl_req_eq(const struct cfctrl_request_info *r1,
const struct cfctrl_request_info *r2)
{
if (r1->cmd != r2->cmd)
return false;
if (r1->cmd == CFCTRL_CMD_LINK_SETUP)
return param_eq(&r1->param, &r2->param);
else
return r1->channel_id == r2->channel_id;
}
/* Insert request at the end */
static void cfctrl_insert_req(struct cfctrl *ctrl,
struct cfctrl_request_info *req)
{
spin_lock_bh(&ctrl->info_list_lock);
atomic_inc(&ctrl->req_seq_no);
req->sequence_no = atomic_read(&ctrl->req_seq_no);
list_add_tail(&req->list, &ctrl->list);
spin_unlock_bh(&ctrl->info_list_lock);
}
/* Compare and remove request */
static struct cfctrl_request_info *cfctrl_remove_req(struct cfctrl *ctrl,
struct cfctrl_request_info *req)
{
struct cfctrl_request_info *p, *tmp, *first;
first = list_first_entry(&ctrl->list, struct cfctrl_request_info, list);
list_for_each_entry_safe(p, tmp, &ctrl->list, list) {
if (cfctrl_req_eq(req, p)) {
if (p != first)
pr_warn("Requests are not received in order\n");
atomic_set(&ctrl->rsp_seq_no,
p->sequence_no);
list_del(&p->list);
goto out;
}
}
p = NULL;
out:
return p;
}
struct cfctrl_rsp *cfctrl_get_respfuncs(struct cflayer *layer)
{
struct cfctrl *this = container_obj(layer);
return &this->res;
}
static void init_info(struct caif_payload_info *info, struct cfctrl *cfctrl)
{
info->hdr_len = 0;
info->channel_id = cfctrl->serv.layer.id;
info->dev_info = &cfctrl->serv.dev_info;
}
void cfctrl_enum_req(struct cflayer *layer, u8 physlinkid)
{
struct cfpkt *pkt;
struct cfctrl *cfctrl = container_obj(layer);
struct cflayer *dn = cfctrl->serv.layer.dn;
if (!dn) {
pr_debug("not able to send enum request\n");
return;
}
pkt = cfpkt_create(CFPKT_CTRL_PKT_LEN);
if (!pkt)
return;
caif_assert(offsetof(struct cfctrl, serv.layer) == 0);
init_info(cfpkt_info(pkt), cfctrl);
cfpkt_info(pkt)->dev_info->id = physlinkid;
cfctrl->serv.dev_info.id = physlinkid;
cfpkt_addbdy(pkt, CFCTRL_CMD_ENUM);
cfpkt_addbdy(pkt, physlinkid);
cfpkt_set_prio(pkt, TC_PRIO_CONTROL);
dn->transmit(dn, pkt);
}
int cfctrl_linkup_request(struct cflayer *layer,
struct cfctrl_link_param *param,
struct cflayer *user_layer)
{
struct cfctrl *cfctrl = container_obj(layer);
u32 tmp32;
u16 tmp16;
u8 tmp8;
struct cfctrl_request_info *req;
int ret;
char utility_name[16];
struct cfpkt *pkt;
struct cflayer *dn = cfctrl->serv.layer.dn;
if (!dn) {
pr_debug("not able to send linkup request\n");
return -ENODEV;
}
if (cfctrl_cancel_req(layer, user_layer) > 0) {
/* Slight Paranoia, check if already connecting */
pr_err("Duplicate connect request for same client\n");
WARN_ON(1);
return -EALREADY;
}
pkt = cfpkt_create(CFPKT_CTRL_PKT_LEN);
if (!pkt)
return -ENOMEM;
cfpkt_addbdy(pkt, CFCTRL_CMD_LINK_SETUP);
cfpkt_addbdy(pkt, (param->chtype << 4) | param->linktype);
cfpkt_addbdy(pkt, (param->priority << 3) | param->phyid);
cfpkt_addbdy(pkt, param->endpoint & 0x03);
switch (param->linktype) {
case CFCTRL_SRV_VEI:
break;
case CFCTRL_SRV_VIDEO:
cfpkt_addbdy(pkt, (u8) param->u.video.connid);
break;
case CFCTRL_SRV_DBG:
break;
case CFCTRL_SRV_DATAGRAM:
tmp32 = cpu_to_le32(param->u.datagram.connid);
cfpkt_add_body(pkt, &tmp32, 4);
break;
case CFCTRL_SRV_RFM:
/* Construct a frame, convert DatagramConnectionID to network
* format long and copy it out...
*/
tmp32 = cpu_to_le32(param->u.rfm.connid);
cfpkt_add_body(pkt, &tmp32, 4);
/* Add volume name, including zero termination... */
cfpkt_add_body(pkt, param->u.rfm.volume,
strlen(param->u.rfm.volume) + 1);
break;
case CFCTRL_SRV_UTIL:
tmp16 = cpu_to_le16(param->u.utility.fifosize_kb);
cfpkt_add_body(pkt, &tmp16, 2);
tmp16 = cpu_to_le16(param->u.utility.fifosize_bufs);
cfpkt_add_body(pkt, &tmp16, 2);
memset(utility_name, 0, sizeof(utility_name));
strncpy(utility_name, param->u.utility.name,
UTILITY_NAME_LENGTH - 1);
cfpkt_add_body(pkt, utility_name, UTILITY_NAME_LENGTH);
tmp8 = param->u.utility.paramlen;
cfpkt_add_body(pkt, &tmp8, 1);
cfpkt_add_body(pkt, param->u.utility.params,
param->u.utility.paramlen);
break;
default:
pr_warn("Request setup of bad link type = %d\n",
param->linktype);
return -EINVAL;
}
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
req->client_layer = user_layer;
req->cmd = CFCTRL_CMD_LINK_SETUP;
req->param = *param;
cfctrl_insert_req(cfctrl, req);
init_info(cfpkt_info(pkt), cfctrl);
/*
* NOTE:Always send linkup and linkdown request on the same
* device as the payload. Otherwise old queued up payload
* might arrive with the newly allocated channel ID.
*/
cfpkt_info(pkt)->dev_info->id = param->phyid;
cfpkt_set_prio(pkt, TC_PRIO_CONTROL);
ret =
dn->transmit(dn, pkt);
if (ret < 0) {
int count;
count = cfctrl_cancel_req(&cfctrl->serv.layer,
user_layer);
if (count != 1) {
pr_err("Could not remove request (%d)", count);
return -ENODEV;
}
}
return 0;
}
int cfctrl_linkdown_req(struct cflayer *layer, u8 channelid,
struct cflayer *client)
{
int ret;
struct cfpkt *pkt;
struct cfctrl *cfctrl = container_obj(layer);
struct cflayer *dn = cfctrl->serv.layer.dn;
if (!dn) {
pr_debug("not able to send link-down request\n");
return -ENODEV;
}
pkt = cfpkt_create(CFPKT_CTRL_PKT_LEN);
if (!pkt)
return -ENOMEM;
cfpkt_addbdy(pkt, CFCTRL_CMD_LINK_DESTROY);
cfpkt_addbdy(pkt, channelid);
init_info(cfpkt_info(pkt), cfctrl);
cfpkt_set_prio(pkt, TC_PRIO_CONTROL);
ret =
dn->transmit(dn, pkt);
#ifndef CAIF_NO_LOOP
cfctrl->loop_linkused[channelid] = 0;
#endif
return ret;
}
int cfctrl_cancel_req(struct cflayer *layr, struct cflayer *adap_layer)
{
struct cfctrl_request_info *p, *tmp;
struct cfctrl *ctrl = container_obj(layr);
int found = 0;
spin_lock_bh(&ctrl->info_list_lock);
list_for_each_entry_safe(p, tmp, &ctrl->list, list) {
if (p->client_layer == adap_layer) {
list_del(&p->list);
kfree(p);
found++;
}
}
spin_unlock_bh(&ctrl->info_list_lock);
return found;
}
static int cfctrl_recv(struct cflayer *layer, struct cfpkt *pkt)
{
u8 cmdrsp;
u8 cmd;
int ret = -1;
u16 tmp16;
u8 len;
u8 param[255];
u8 linkid;
struct cfctrl *cfctrl = container_obj(layer);
struct cfctrl_request_info rsp, *req;
cfpkt_extr_head(pkt, &cmdrsp, 1);
cmd = cmdrsp & CFCTRL_CMD_MASK;
if (cmd != CFCTRL_CMD_LINK_ERR
&& CFCTRL_RSP_BIT != (CFCTRL_RSP_BIT & cmdrsp)
&& CFCTRL_ERR_BIT != (CFCTRL_ERR_BIT & cmdrsp)) {
if (handle_loop(cfctrl, cmd, pkt) != 0)
cmdrsp |= CFCTRL_ERR_BIT;
}
switch (cmd) {
case CFCTRL_CMD_LINK_SETUP:
{
enum cfctrl_srv serv;
enum cfctrl_srv servtype;
u8 endpoint;
u8 physlinkid;
u8 prio;
u8 tmp;
u32 tmp32;
u8 *cp;
int i;
struct cfctrl_link_param linkparam;
memset(&linkparam, 0, sizeof(linkparam));
cfpkt_extr_head(pkt, &tmp, 1);
serv = tmp & CFCTRL_SRV_MASK;
linkparam.linktype = serv;
servtype = tmp >> 4;
linkparam.chtype = servtype;
cfpkt_extr_head(pkt, &tmp, 1);
physlinkid = tmp & 0x07;
prio = tmp >> 3;
linkparam.priority = prio;
linkparam.phyid = physlinkid;
cfpkt_extr_head(pkt, &endpoint, 1);
linkparam.endpoint = endpoint & 0x03;
switch (serv) {
case CFCTRL_SRV_VEI:
case CFCTRL_SRV_DBG:
if (CFCTRL_ERR_BIT & cmdrsp)
break;
/* Link ID */
cfpkt_extr_head(pkt, &linkid, 1);
break;
case CFCTRL_SRV_VIDEO:
cfpkt_extr_head(pkt, &tmp, 1);
linkparam.u.video.connid = tmp;
if (CFCTRL_ERR_BIT & cmdrsp)
break;
/* Link ID */
cfpkt_extr_head(pkt, &linkid, 1);
break;
case CFCTRL_SRV_DATAGRAM:
cfpkt_extr_head(pkt, &tmp32, 4);
linkparam.u.datagram.connid =
le32_to_cpu(tmp32);
if (CFCTRL_ERR_BIT & cmdrsp)
break;
/* Link ID */
cfpkt_extr_head(pkt, &linkid, 1);
break;
case CFCTRL_SRV_RFM:
/* Construct a frame, convert
* DatagramConnectionID
* to network format long and copy it out...
*/
cfpkt_extr_head(pkt, &tmp32, 4);
linkparam.u.rfm.connid =
le32_to_cpu(tmp32);
cp = (u8 *) linkparam.u.rfm.volume;
for (cfpkt_extr_head(pkt, &tmp, 1);
cfpkt_more(pkt) && tmp != '\0';
cfpkt_extr_head(pkt, &tmp, 1))
*cp++ = tmp;
*cp = '\0';
if (CFCTRL_ERR_BIT & cmdrsp)
break;
/* Link ID */
cfpkt_extr_head(pkt, &linkid, 1);
break;
case CFCTRL_SRV_UTIL:
/* Construct a frame, convert
* DatagramConnectionID
* to network format long and copy it out...
*/
/* Fifosize KB */
cfpkt_extr_head(pkt, &tmp16, 2);
linkparam.u.utility.fifosize_kb =
le16_to_cpu(tmp16);
/* Fifosize bufs */
cfpkt_extr_head(pkt, &tmp16, 2);
linkparam.u.utility.fifosize_bufs =
le16_to_cpu(tmp16);
/* name */
cp = (u8 *) linkparam.u.utility.name;
caif_assert(sizeof(linkparam.u.utility.name)
>= UTILITY_NAME_LENGTH);
for (i = 0;
i < UTILITY_NAME_LENGTH
&& cfpkt_more(pkt); i++) {
cfpkt_extr_head(pkt, &tmp, 1);
*cp++ = tmp;
}
/* Length */
cfpkt_extr_head(pkt, &len, 1);
linkparam.u.utility.paramlen = len;
/* Param Data */
cp = linkparam.u.utility.params;
while (cfpkt_more(pkt) && len--) {
cfpkt_extr_head(pkt, &tmp, 1);
*cp++ = tmp;
}
if (CFCTRL_ERR_BIT & cmdrsp)
break;
/* Link ID */
cfpkt_extr_head(pkt, &linkid, 1);
/* Length */
cfpkt_extr_head(pkt, &len, 1);
/* Param Data */
cfpkt_extr_head(pkt, ¶m, len);
break;
default:
pr_warn("Request setup, invalid type (%d)\n",
serv);
goto error;
}
rsp.cmd = cmd;
rsp.param = linkparam;
spin_lock_bh(&cfctrl->info_list_lock);
req = cfctrl_remove_req(cfctrl, &rsp);
if (CFCTRL_ERR_BIT == (CFCTRL_ERR_BIT & cmdrsp) ||
cfpkt_erroneous(pkt)) {
pr_err("Invalid O/E bit or parse error "
"on CAIF control channel\n");
cfctrl->res.reject_rsp(cfctrl->serv.layer.up,
0,
req ? req->client_layer
: NULL);
} else {
cfctrl->res.linksetup_rsp(cfctrl->serv.
layer.up, linkid,
serv, physlinkid,
req ? req->
client_layer : NULL);
}
kfree(req);
spin_unlock_bh(&cfctrl->info_list_lock);
}
break;
case CFCTRL_CMD_LINK_DESTROY:
cfpkt_extr_head(pkt, &linkid, 1);
cfctrl->res.linkdestroy_rsp(cfctrl->serv.layer.up, linkid);
break;
case CFCTRL_CMD_LINK_ERR:
pr_err("Frame Error Indication received\n");
cfctrl->res.linkerror_ind();
break;
case CFCTRL_CMD_ENUM:
cfctrl->res.enum_rsp();
break;
case CFCTRL_CMD_SLEEP:
cfctrl->res.sleep_rsp();
break;
case CFCTRL_CMD_WAKE:
cfctrl->res.wake_rsp();
break;
case CFCTRL_CMD_LINK_RECONF:
cfctrl->res.restart_rsp();
break;
case CFCTRL_CMD_RADIO_SET:
cfctrl->res.radioset_rsp();
break;
default:
pr_err("Unrecognized Control Frame\n");
goto error;
break;
}
ret = 0;
error:
cfpkt_destroy(pkt);
return ret;
}
static void cfctrl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl,
int phyid)
{
struct cfctrl *this = container_obj(layr);
switch (ctrl) {
case _CAIF_CTRLCMD_PHYIF_FLOW_OFF_IND:
case CAIF_CTRLCMD_FLOW_OFF_IND:
spin_lock_bh(&this->info_list_lock);
if (!list_empty(&this->list))
pr_debug("Received flow off in control layer\n");
spin_unlock_bh(&this->info_list_lock);
break;
case _CAIF_CTRLCMD_PHYIF_DOWN_IND: {
struct cfctrl_request_info *p, *tmp;
/* Find all connect request and report failure */
spin_lock_bh(&this->info_list_lock);
list_for_each_entry_safe(p, tmp, &this->list, list) {
if (p->param.phyid == phyid) {
list_del(&p->list);
p->client_layer->ctrlcmd(p->client_layer,
CAIF_CTRLCMD_INIT_FAIL_RSP,
phyid);
kfree(p);
}
}
spin_unlock_bh(&this->info_list_lock);
break;
}
default:
break;
}
}
#ifndef CAIF_NO_LOOP
static int handle_loop(struct cfctrl *ctrl, int cmd, struct cfpkt *pkt)
{
static int last_linkid;
static int dec;
u8 linkid, linktype, tmp;
switch (cmd) {
case CFCTRL_CMD_LINK_SETUP:
spin_lock_bh(&ctrl->loop_linkid_lock);
if (!dec) {
for (linkid = last_linkid + 1; linkid < 254; linkid++)
if (!ctrl->loop_linkused[linkid])
goto found;
}
dec = 1;
for (linkid = last_linkid - 1; linkid > 1; linkid--)
if (!ctrl->loop_linkused[linkid])
goto found;
spin_unlock_bh(&ctrl->loop_linkid_lock);
return -1;
found:
if (linkid < 10)
dec = 0;
if (!ctrl->loop_linkused[linkid])
ctrl->loop_linkused[linkid] = 1;
last_linkid = linkid;
cfpkt_add_trail(pkt, &linkid, 1);
spin_unlock_bh(&ctrl->loop_linkid_lock);
cfpkt_peek_head(pkt, &linktype, 1);
if (linktype == CFCTRL_SRV_UTIL) {
tmp = 0x01;
cfpkt_add_trail(pkt, &tmp, 1);
cfpkt_add_trail(pkt, &tmp, 1);
}
break;
case CFCTRL_CMD_LINK_DESTROY:
spin_lock_bh(&ctrl->loop_linkid_lock);
cfpkt_peek_head(pkt, &linkid, 1);
ctrl->loop_linkused[linkid] = 0;
spin_unlock_bh(&ctrl->loop_linkid_lock);
break;
default:
break;
}
return 0;
}
#endif
| gpl-2.0 |
FennyFatal/i747_kernel_ics | drivers/input/misc/ab8500-ponkey.c | 3157 | 3880 | /*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Author: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
*
* AB8500 Power-On Key handler
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/mfd/ab8500.h>
#include <linux/slab.h>
/**
* struct ab8500_ponkey - ab8500 ponkey information
* @input_dev: pointer to input device
* @ab8500: ab8500 parent
* @irq_dbf: irq number for falling transition
* @irq_dbr: irq number for rising transition
*/
struct ab8500_ponkey {
struct input_dev *idev;
struct ab8500 *ab8500;
int irq_dbf;
int irq_dbr;
};
/* AB8500 gives us an interrupt when ONKEY is held */
static irqreturn_t ab8500_ponkey_handler(int irq, void *data)
{
struct ab8500_ponkey *ponkey = data;
if (irq == ponkey->irq_dbf)
input_report_key(ponkey->idev, KEY_POWER, true);
else if (irq == ponkey->irq_dbr)
input_report_key(ponkey->idev, KEY_POWER, false);
input_sync(ponkey->idev);
return IRQ_HANDLED;
}
static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
{
struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
struct ab8500_ponkey *ponkey;
struct input_dev *input;
int irq_dbf, irq_dbr;
int error;
irq_dbf = platform_get_irq_byname(pdev, "ONKEY_DBF");
if (irq_dbf < 0) {
dev_err(&pdev->dev, "No IRQ for ONKEY_DBF, error=%d\n", irq_dbf);
return irq_dbf;
}
irq_dbr = platform_get_irq_byname(pdev, "ONKEY_DBR");
if (irq_dbr < 0) {
dev_err(&pdev->dev, "No IRQ for ONKEY_DBR, error=%d\n", irq_dbr);
return irq_dbr;
}
ponkey = kzalloc(sizeof(struct ab8500_ponkey), GFP_KERNEL);
input = input_allocate_device();
if (!ponkey || !input) {
error = -ENOMEM;
goto err_free_mem;
}
ponkey->idev = input;
ponkey->ab8500 = ab8500;
ponkey->irq_dbf = irq_dbf;
ponkey->irq_dbr = irq_dbr;
input->name = "AB8500 POn(PowerOn) Key";
input->dev.parent = &pdev->dev;
input_set_capability(input, EV_KEY, KEY_POWER);
error = request_any_context_irq(ponkey->irq_dbf, ab8500_ponkey_handler,
0, "ab8500-ponkey-dbf", ponkey);
if (error < 0) {
dev_err(ab8500->dev, "Failed to request dbf IRQ#%d: %d\n",
ponkey->irq_dbf, error);
goto err_free_mem;
}
error = request_any_context_irq(ponkey->irq_dbr, ab8500_ponkey_handler,
0, "ab8500-ponkey-dbr", ponkey);
if (error < 0) {
dev_err(ab8500->dev, "Failed to request dbr IRQ#%d: %d\n",
ponkey->irq_dbr, error);
goto err_free_dbf_irq;
}
error = input_register_device(ponkey->idev);
if (error) {
dev_err(ab8500->dev, "Can't register input device: %d\n", error);
goto err_free_dbr_irq;
}
platform_set_drvdata(pdev, ponkey);
return 0;
err_free_dbr_irq:
free_irq(ponkey->irq_dbr, ponkey);
err_free_dbf_irq:
free_irq(ponkey->irq_dbf, ponkey);
err_free_mem:
input_free_device(input);
kfree(ponkey);
return error;
}
static int __devexit ab8500_ponkey_remove(struct platform_device *pdev)
{
struct ab8500_ponkey *ponkey = platform_get_drvdata(pdev);
free_irq(ponkey->irq_dbf, ponkey);
free_irq(ponkey->irq_dbr, ponkey);
input_unregister_device(ponkey->idev);
kfree(ponkey);
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver ab8500_ponkey_driver = {
.driver = {
.name = "ab8500-poweron-key",
.owner = THIS_MODULE,
},
.probe = ab8500_ponkey_probe,
.remove = __devexit_p(ab8500_ponkey_remove),
};
static int __init ab8500_ponkey_init(void)
{
return platform_driver_register(&ab8500_ponkey_driver);
}
module_init(ab8500_ponkey_init);
static void __exit ab8500_ponkey_exit(void)
{
platform_driver_unregister(&ab8500_ponkey_driver);
}
module_exit(ab8500_ponkey_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
MODULE_DESCRIPTION("ST-Ericsson AB8500 Power-ON(Pon) Key driver");
| gpl-2.0 |
CyanHacker-Lollipop/kernel_lge_hammerhead | arch/mips/rb532/irq.c | 4693 | 6111 | /*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
*/
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/delay.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mach-rc32434/irq.h>
#include <asm/mach-rc32434/gpio.h>
struct intr_group {
u32 mask; /* mask of valid bits in pending/mask registers */
volatile u32 *base_addr;
};
#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
#if (NR_IRQS < RC32434_NR_IRQS)
#error Too little irqs defined. Did you override <asm/irq.h> ?
#endif
static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
{
.mask = 0x0000efff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
{
.mask = 0x00001fff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
{
.mask = 0x00000007,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
{
.mask = 0x0003ffff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
{
.mask = 0xffffffff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
};
#define READ_PEND(base) (*(base))
#define READ_MASK(base) (*(base + 2))
#define WRITE_MASK(base, val) (*(base + 2) = (val))
static inline int irq_to_group(unsigned int irq_nr)
{
return (irq_nr - GROUP0_IRQ_BASE) >> 5;
}
static inline int group_to_ip(unsigned int group)
{
return group + 2;
}
static inline void enable_local_irq(unsigned int ip)
{
int ipnum = 0x100 << ip;
set_c0_status(ipnum);
}
static inline void disable_local_irq(unsigned int ip)
{
int ipnum = 0x100 << ip;
clear_c0_status(ipnum);
}
static inline void ack_local_irq(unsigned int ip)
{
int ipnum = 0x100 << ip;
clear_c0_cause(ipnum);
}
static void rb532_enable_irq(struct irq_data *d)
{
unsigned int group, intr_bit, irq_nr = d->irq;
int ip = irq_nr - GROUP0_IRQ_BASE;
volatile unsigned int *addr;
if (ip < 0)
enable_local_irq(irq_nr);
else {
group = ip >> 5;
ip &= (1 << 5) - 1;
intr_bit = 1 << ip;
enable_local_irq(group_to_ip(group));
addr = intr_group[group].base_addr;
WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
}
}
static void rb532_disable_irq(struct irq_data *d)
{
unsigned int group, intr_bit, mask, irq_nr = d->irq;
int ip = irq_nr - GROUP0_IRQ_BASE;
volatile unsigned int *addr;
if (ip < 0) {
disable_local_irq(irq_nr);
} else {
group = ip >> 5;
ip &= (1 << 5) - 1;
intr_bit = 1 << ip;
addr = intr_group[group].base_addr;
mask = READ_MASK(addr);
mask |= intr_bit;
WRITE_MASK(addr, mask);
/* There is a maximum of 14 GPIO interrupts */
if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
/*
* if there are no more interrupts enabled in this
* group, disable corresponding IP
*/
if (mask == intr_group[group].mask)
disable_local_irq(group_to_ip(group));
}
}
static void rb532_mask_and_ack_irq(struct irq_data *d)
{
rb532_disable_irq(d);
ack_local_irq(group_to_ip(irq_to_group(d->irq)));
}
static int rb532_set_type(struct irq_data *d, unsigned type)
{
int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
int group = irq_to_group(d->irq);
if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
rb532_gpio_set_ilevel(1, gpio);
break;
case IRQ_TYPE_LEVEL_LOW:
rb532_gpio_set_ilevel(0, gpio);
break;
default:
return -EINVAL;
}
return 0;
}
static struct irq_chip rc32434_irq_type = {
.name = "RB532",
.irq_ack = rb532_disable_irq,
.irq_mask = rb532_disable_irq,
.irq_mask_ack = rb532_mask_and_ack_irq,
.irq_unmask = rb532_enable_irq,
.irq_set_type = rb532_set_type,
};
void __init arch_init_irq(void)
{
int i;
pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
for (i = 0; i < RC32434_NR_IRQS; i++)
irq_set_chip_and_handler(i, &rc32434_irq_type,
handle_level_irq);
}
/* Main Interrupt dispatcher */
asmlinkage void plat_irq_dispatch(void)
{
unsigned int ip, pend, group;
volatile unsigned int *addr;
unsigned int cp0_cause = read_c0_cause() & read_c0_status();
if (cp0_cause & CAUSEF_IP7) {
do_IRQ(7);
} else {
ip = (cp0_cause & 0x7c00);
if (ip) {
group = 21 + (fls(ip) - 32);
addr = intr_group[group].base_addr;
pend = READ_PEND(addr);
pend &= ~READ_MASK(addr); /* only unmasked interrupts */
pend = 39 + (fls(pend) - 32);
do_IRQ((group << 5) + pend);
}
}
}
| gpl-2.0 |
shinobisoft/android_kernel_lge_msm8226 | drivers/s390/block/dasd_ioctl.c | 4949 | 13032 | /*
* File...........: linux/drivers/s390/block/dasd_ioctl.c
* Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
* Horst Hummel <Horst.Hummel@de.ibm.com>
* Carsten Otte <Cotte@de.ibm.com>
* Martin Schwidefsky <schwidefsky@de.ibm.com>
* Bugreports.to..: <Linux390@de.ibm.com>
* (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999-2001
*
* i/o controls for the dasd driver.
*/
#define KMSG_COMPONENT "dasd"
#include <linux/interrupt.h>
#include <linux/compat.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/blkpg.h>
#include <linux/slab.h>
#include <asm/compat.h>
#include <asm/ccwdev.h>
#include <asm/cmb.h>
#include <asm/uaccess.h>
/* This is ugly... */
#define PRINTK_HEADER "dasd_ioctl:"
#include "dasd_int.h"
static int
dasd_ioctl_api_version(void __user *argp)
{
int ver = DASD_API_VERSION;
return put_user(ver, (int __user *)argp);
}
/*
* Enable device.
* used by dasdfmt after BIODASDDISABLE to retrigger blocksize detection
*/
static int
dasd_ioctl_enable(struct block_device *bdev)
{
struct dasd_device *base;
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
base = dasd_device_from_gendisk(bdev->bd_disk);
if (!base)
return -ENODEV;
dasd_enable_device(base);
/* Formatting the dasd device can change the capacity. */
mutex_lock(&bdev->bd_mutex);
i_size_write(bdev->bd_inode,
(loff_t)get_capacity(base->block->gdp) << 9);
mutex_unlock(&bdev->bd_mutex);
dasd_put_device(base);
return 0;
}
/*
* Disable device.
* Used by dasdfmt. Disable I/O operations but allow ioctls.
*/
static int
dasd_ioctl_disable(struct block_device *bdev)
{
struct dasd_device *base;
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
base = dasd_device_from_gendisk(bdev->bd_disk);
if (!base)
return -ENODEV;
/*
* Man this is sick. We don't do a real disable but only downgrade
* the device to DASD_STATE_BASIC. The reason is that dasdfmt uses
* BIODASDDISABLE to disable accesses to the device via the block
* device layer but it still wants to do i/o on the device by
* using the BIODASDFMT ioctl. Therefore the correct state for the
* device is DASD_STATE_BASIC that allows to do basic i/o.
*/
dasd_set_target_state(base, DASD_STATE_BASIC);
/*
* Set i_size to zero, since read, write, etc. check against this
* value.
*/
mutex_lock(&bdev->bd_mutex);
i_size_write(bdev->bd_inode, 0);
mutex_unlock(&bdev->bd_mutex);
dasd_put_device(base);
return 0;
}
/*
* Quiesce device.
*/
static int dasd_ioctl_quiesce(struct dasd_block *block)
{
unsigned long flags;
struct dasd_device *base;
base = block->base;
if (!capable (CAP_SYS_ADMIN))
return -EACCES;
pr_info("%s: The DASD has been put in the quiesce "
"state\n", dev_name(&base->cdev->dev));
spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags);
dasd_device_set_stop_bits(base, DASD_STOPPED_QUIESCE);
spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags);
return 0;
}
/*
* Resume device.
*/
static int dasd_ioctl_resume(struct dasd_block *block)
{
unsigned long flags;
struct dasd_device *base;
base = block->base;
if (!capable (CAP_SYS_ADMIN))
return -EACCES;
pr_info("%s: I/O operations have been resumed "
"on the DASD\n", dev_name(&base->cdev->dev));
spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags);
dasd_device_remove_stop_bits(base, DASD_STOPPED_QUIESCE);
spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags);
dasd_schedule_block_bh(block);
return 0;
}
/*
* performs formatting of _device_ according to _fdata_
* Note: The discipline's format_function is assumed to deliver formatting
* commands to format a single unit of the device. In terms of the ECKD
* devices this means CCWs are generated to format a single track.
*/
static int dasd_format(struct dasd_block *block, struct format_data_t *fdata)
{
struct dasd_ccw_req *cqr;
struct dasd_device *base;
int rc;
base = block->base;
if (base->discipline->format_device == NULL)
return -EPERM;
if (base->state != DASD_STATE_BASIC) {
pr_warning("%s: The DASD cannot be formatted while it is "
"enabled\n", dev_name(&base->cdev->dev));
return -EBUSY;
}
DBF_DEV_EVENT(DBF_NOTICE, base,
"formatting units %u to %u (%u B blocks) flags %u",
fdata->start_unit,
fdata->stop_unit, fdata->blksize, fdata->intensity);
/* Since dasdfmt keeps the device open after it was disabled,
* there still exists an inode for this device.
* We must update i_blkbits, otherwise we might get errors when
* enabling the device later.
*/
if (fdata->start_unit == 0) {
struct block_device *bdev = bdget_disk(block->gdp, 0);
bdev->bd_inode->i_blkbits = blksize_bits(fdata->blksize);
bdput(bdev);
}
while (fdata->start_unit <= fdata->stop_unit) {
cqr = base->discipline->format_device(base, fdata);
if (IS_ERR(cqr))
return PTR_ERR(cqr);
rc = dasd_sleep_on_interruptible(cqr);
dasd_sfree_request(cqr, cqr->memdev);
if (rc) {
if (rc != -ERESTARTSYS)
pr_err("%s: Formatting unit %d failed with "
"rc=%d\n", dev_name(&base->cdev->dev),
fdata->start_unit, rc);
return rc;
}
fdata->start_unit++;
}
return 0;
}
/*
* Format device.
*/
static int
dasd_ioctl_format(struct block_device *bdev, void __user *argp)
{
struct dasd_device *base;
struct format_data_t fdata;
int rc;
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
if (!argp)
return -EINVAL;
base = dasd_device_from_gendisk(bdev->bd_disk);
if (!base)
return -ENODEV;
if (base->features & DASD_FEATURE_READONLY ||
test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) {
dasd_put_device(base);
return -EROFS;
}
if (copy_from_user(&fdata, argp, sizeof(struct format_data_t))) {
dasd_put_device(base);
return -EFAULT;
}
if (bdev != bdev->bd_contains) {
pr_warning("%s: The specified DASD is a partition and cannot "
"be formatted\n",
dev_name(&base->cdev->dev));
dasd_put_device(base);
return -EINVAL;
}
rc = dasd_format(base->block, &fdata);
dasd_put_device(base);
return rc;
}
#ifdef CONFIG_DASD_PROFILE
/*
* Reset device profile information
*/
static int dasd_ioctl_reset_profile(struct dasd_block *block)
{
dasd_profile_reset(&block->profile);
return 0;
}
/*
* Return device profile information
*/
static int dasd_ioctl_read_profile(struct dasd_block *block, void __user *argp)
{
struct dasd_profile_info_t *data;
int rc = 0;
data = kmalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
spin_lock_bh(&block->profile.lock);
if (block->profile.data) {
data->dasd_io_reqs = block->profile.data->dasd_io_reqs;
data->dasd_io_sects = block->profile.data->dasd_io_sects;
memcpy(data->dasd_io_secs, block->profile.data->dasd_io_secs,
sizeof(data->dasd_io_secs));
memcpy(data->dasd_io_times, block->profile.data->dasd_io_times,
sizeof(data->dasd_io_times));
memcpy(data->dasd_io_timps, block->profile.data->dasd_io_timps,
sizeof(data->dasd_io_timps));
memcpy(data->dasd_io_time1, block->profile.data->dasd_io_time1,
sizeof(data->dasd_io_time1));
memcpy(data->dasd_io_time2, block->profile.data->dasd_io_time2,
sizeof(data->dasd_io_time2));
memcpy(data->dasd_io_time2ps,
block->profile.data->dasd_io_time2ps,
sizeof(data->dasd_io_time2ps));
memcpy(data->dasd_io_time3, block->profile.data->dasd_io_time3,
sizeof(data->dasd_io_time3));
memcpy(data->dasd_io_nr_req,
block->profile.data->dasd_io_nr_req,
sizeof(data->dasd_io_nr_req));
spin_unlock_bh(&block->profile.lock);
} else {
spin_unlock_bh(&block->profile.lock);
rc = -EIO;
goto out;
}
if (copy_to_user(argp, data, sizeof(*data)))
rc = -EFAULT;
out:
kfree(data);
return rc;
}
#else
static int dasd_ioctl_reset_profile(struct dasd_block *block)
{
return -ENOSYS;
}
static int dasd_ioctl_read_profile(struct dasd_block *block, void __user *argp)
{
return -ENOSYS;
}
#endif
/*
* Return dasd information. Used for BIODASDINFO and BIODASDINFO2.
*/
static int dasd_ioctl_information(struct dasd_block *block,
unsigned int cmd, void __user *argp)
{
struct dasd_information2_t *dasd_info;
unsigned long flags;
int rc;
struct dasd_device *base;
struct ccw_device *cdev;
struct ccw_dev_id dev_id;
base = block->base;
if (!base->discipline || !base->discipline->fill_info)
return -EINVAL;
dasd_info = kzalloc(sizeof(struct dasd_information2_t), GFP_KERNEL);
if (dasd_info == NULL)
return -ENOMEM;
rc = base->discipline->fill_info(base, dasd_info);
if (rc) {
kfree(dasd_info);
return rc;
}
cdev = base->cdev;
ccw_device_get_id(cdev, &dev_id);
dasd_info->devno = dev_id.devno;
dasd_info->schid = _ccw_device_get_subchannel_number(base->cdev);
dasd_info->cu_type = cdev->id.cu_type;
dasd_info->cu_model = cdev->id.cu_model;
dasd_info->dev_type = cdev->id.dev_type;
dasd_info->dev_model = cdev->id.dev_model;
dasd_info->status = base->state;
/*
* The open_count is increased for every opener, that includes
* the blkdev_get in dasd_scan_partitions.
* This must be hidden from user-space.
*/
dasd_info->open_count = atomic_read(&block->open_count);
if (!block->bdev)
dasd_info->open_count++;
/*
* check if device is really formatted
* LDL / CDL was returned by 'fill_info'
*/
if ((base->state < DASD_STATE_READY) ||
(dasd_check_blocksize(block->bp_block)))
dasd_info->format = DASD_FORMAT_NONE;
dasd_info->features |=
((base->features & DASD_FEATURE_READONLY) != 0);
memcpy(dasd_info->type, base->discipline->name, 4);
if (block->request_queue->request_fn) {
struct list_head *l;
#ifdef DASD_EXTENDED_PROFILING
{
struct list_head *l;
spin_lock_irqsave(&block->lock, flags);
list_for_each(l, &block->request_queue->queue_head)
dasd_info->req_queue_len++;
spin_unlock_irqrestore(&block->lock, flags);
}
#endif /* DASD_EXTENDED_PROFILING */
spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags);
list_for_each(l, &base->ccw_queue)
dasd_info->chanq_len++;
spin_unlock_irqrestore(get_ccwdev_lock(base->cdev),
flags);
}
rc = 0;
if (copy_to_user(argp, dasd_info,
((cmd == (unsigned int) BIODASDINFO2) ?
sizeof(struct dasd_information2_t) :
sizeof(struct dasd_information_t))))
rc = -EFAULT;
kfree(dasd_info);
return rc;
}
/*
* Set read only
*/
static int
dasd_ioctl_set_ro(struct block_device *bdev, void __user *argp)
{
struct dasd_device *base;
int intval, rc;
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
if (bdev != bdev->bd_contains)
// ro setting is not allowed for partitions
return -EINVAL;
if (get_user(intval, (int __user *)argp))
return -EFAULT;
base = dasd_device_from_gendisk(bdev->bd_disk);
if (!base)
return -ENODEV;
if (!intval && test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) {
dasd_put_device(base);
return -EROFS;
}
set_disk_ro(bdev->bd_disk, intval);
rc = dasd_set_feature(base->cdev, DASD_FEATURE_READONLY, intval);
dasd_put_device(base);
return rc;
}
static int dasd_ioctl_readall_cmb(struct dasd_block *block, unsigned int cmd,
struct cmbdata __user *argp)
{
size_t size = _IOC_SIZE(cmd);
struct cmbdata data;
int ret;
ret = cmf_readall(block->base->cdev, &data);
if (!ret && copy_to_user(argp, &data, min(size, sizeof(*argp))))
return -EFAULT;
return ret;
}
int dasd_ioctl(struct block_device *bdev, fmode_t mode,
unsigned int cmd, unsigned long arg)
{
struct dasd_block *block;
struct dasd_device *base;
void __user *argp;
int rc;
if (is_compat_task())
argp = compat_ptr(arg);
else
argp = (void __user *)arg;
if ((_IOC_DIR(cmd) != _IOC_NONE) && !arg) {
PRINT_DEBUG("empty data ptr");
return -EINVAL;
}
base = dasd_device_from_gendisk(bdev->bd_disk);
if (!base)
return -ENODEV;
block = base->block;
rc = 0;
switch (cmd) {
case BIODASDDISABLE:
rc = dasd_ioctl_disable(bdev);
break;
case BIODASDENABLE:
rc = dasd_ioctl_enable(bdev);
break;
case BIODASDQUIESCE:
rc = dasd_ioctl_quiesce(block);
break;
case BIODASDRESUME:
rc = dasd_ioctl_resume(block);
break;
case BIODASDFMT:
rc = dasd_ioctl_format(bdev, argp);
break;
case BIODASDINFO:
rc = dasd_ioctl_information(block, cmd, argp);
break;
case BIODASDINFO2:
rc = dasd_ioctl_information(block, cmd, argp);
break;
case BIODASDPRRD:
rc = dasd_ioctl_read_profile(block, argp);
break;
case BIODASDPRRST:
rc = dasd_ioctl_reset_profile(block);
break;
case BLKROSET:
rc = dasd_ioctl_set_ro(bdev, argp);
break;
case DASDAPIVER:
rc = dasd_ioctl_api_version(argp);
break;
case BIODASDCMFENABLE:
rc = enable_cmf(base->cdev);
break;
case BIODASDCMFDISABLE:
rc = disable_cmf(base->cdev);
break;
case BIODASDREADALLCMB:
rc = dasd_ioctl_readall_cmb(block, cmd, argp);
break;
default:
/* if the discipline has an ioctl method try it. */
if (base->discipline->ioctl) {
rc = base->discipline->ioctl(block, cmd, argp);
if (rc == -ENOIOCTLCMD)
rc = -EINVAL;
} else
rc = -EINVAL;
}
dasd_put_device(base);
return rc;
}
| gpl-2.0 |
MasterPlexus/kernel_i8200 | drivers/net/wireless/orinoco/orinoco_tmd.c | 5717 | 6541 | /* orinoco_tmd.c
*
* Driver for Prism II devices which would usually be driven by orinoco_cs,
* but are connected to the PCI bus by a TMD7160.
*
* Copyright (C) 2003 Joerg Dorchain <joerg AT dorchain.net>
* based heavily upon orinoco_plx.c Copyright (C) 2001 Daniel Barlow
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*
* The actual driving is done by main.c, this is just resource
* allocation stuff.
*
* This driver is modeled after the orinoco_plx driver. The main
* difference is that the TMD chip has only IO port ranges and doesn't
* provide access to the PCMCIA attribute space.
*
* Pheecom sells cards with the TMD chip as "ASIC version"
*/
#define DRIVER_NAME "orinoco_tmd"
#define PFX DRIVER_NAME ": "
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <pcmcia/cisreg.h>
#include "orinoco.h"
#include "orinoco_pci.h"
#define COR_VALUE (COR_LEVEL_REQ | COR_FUNC_ENA) /* Enable PC card with interrupt in level trigger */
#define COR_RESET (0x80) /* reset bit in the COR register */
#define TMD_RESET_TIME (500) /* milliseconds */
/*
* Do a soft reset of the card using the Configuration Option Register
*/
static int orinoco_tmd_cor_reset(struct orinoco_private *priv)
{
struct hermes *hw = &priv->hw;
struct orinoco_pci_card *card = priv->card;
unsigned long timeout;
u16 reg;
iowrite8(COR_VALUE | COR_RESET, card->bridge_io);
mdelay(1);
iowrite8(COR_VALUE, card->bridge_io);
mdelay(1);
/* Just in case, wait more until the card is no longer busy */
timeout = jiffies + (TMD_RESET_TIME * HZ / 1000);
reg = hermes_read_regn(hw, CMD);
while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) {
mdelay(1);
reg = hermes_read_regn(hw, CMD);
}
/* Still busy? */
if (reg & HERMES_CMD_BUSY) {
printk(KERN_ERR PFX "Busy timeout\n");
return -ETIMEDOUT;
}
return 0;
}
static int orinoco_tmd_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int err;
struct orinoco_private *priv;
struct orinoco_pci_card *card;
void __iomem *hermes_io, *bridge_io;
err = pci_enable_device(pdev);
if (err) {
printk(KERN_ERR PFX "Cannot enable PCI device\n");
return err;
}
err = pci_request_regions(pdev, DRIVER_NAME);
if (err) {
printk(KERN_ERR PFX "Cannot obtain PCI resources\n");
goto fail_resources;
}
bridge_io = pci_iomap(pdev, 1, 0);
if (!bridge_io) {
printk(KERN_ERR PFX "Cannot map bridge registers\n");
err = -EIO;
goto fail_map_bridge;
}
hermes_io = pci_iomap(pdev, 2, 0);
if (!hermes_io) {
printk(KERN_ERR PFX "Cannot map chipset registers\n");
err = -EIO;
goto fail_map_hermes;
}
/* Allocate network device */
priv = alloc_orinocodev(sizeof(*card), &pdev->dev,
orinoco_tmd_cor_reset, NULL);
if (!priv) {
printk(KERN_ERR PFX "Cannot allocate network device\n");
err = -ENOMEM;
goto fail_alloc;
}
card = priv->card;
card->bridge_io = bridge_io;
hermes_struct_init(&priv->hw, hermes_io, HERMES_16BIT_REGSPACING);
err = request_irq(pdev->irq, orinoco_interrupt, IRQF_SHARED,
DRIVER_NAME, priv);
if (err) {
printk(KERN_ERR PFX "Cannot allocate IRQ %d\n", pdev->irq);
err = -EBUSY;
goto fail_irq;
}
err = orinoco_tmd_cor_reset(priv);
if (err) {
printk(KERN_ERR PFX "Initial reset failed\n");
goto fail;
}
err = orinoco_init(priv);
if (err) {
printk(KERN_ERR PFX "orinoco_init() failed\n");
goto fail;
}
err = orinoco_if_add(priv, 0, 0, NULL);
if (err) {
printk(KERN_ERR PFX "orinoco_if_add() failed\n");
goto fail;
}
pci_set_drvdata(pdev, priv);
return 0;
fail:
free_irq(pdev->irq, priv);
fail_irq:
pci_set_drvdata(pdev, NULL);
free_orinocodev(priv);
fail_alloc:
pci_iounmap(pdev, hermes_io);
fail_map_hermes:
pci_iounmap(pdev, bridge_io);
fail_map_bridge:
pci_release_regions(pdev);
fail_resources:
pci_disable_device(pdev);
return err;
}
static void __devexit orinoco_tmd_remove_one(struct pci_dev *pdev)
{
struct orinoco_private *priv = pci_get_drvdata(pdev);
struct orinoco_pci_card *card = priv->card;
orinoco_if_del(priv);
free_irq(pdev->irq, priv);
pci_set_drvdata(pdev, NULL);
free_orinocodev(priv);
pci_iounmap(pdev, priv->hw.iobase);
pci_iounmap(pdev, card->bridge_io);
pci_release_regions(pdev);
pci_disable_device(pdev);
}
static DEFINE_PCI_DEVICE_TABLE(orinoco_tmd_id_table) = {
{0x15e8, 0x0131, PCI_ANY_ID, PCI_ANY_ID,}, /* NDC and OEMs, e.g. pheecom */
{0,},
};
MODULE_DEVICE_TABLE(pci, orinoco_tmd_id_table);
static struct pci_driver orinoco_tmd_driver = {
.name = DRIVER_NAME,
.id_table = orinoco_tmd_id_table,
.probe = orinoco_tmd_init_one,
.remove = __devexit_p(orinoco_tmd_remove_one),
.suspend = orinoco_pci_suspend,
.resume = orinoco_pci_resume,
};
static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION
" (Joerg Dorchain <joerg@dorchain.net>)";
MODULE_AUTHOR("Joerg Dorchain <joerg@dorchain.net>");
MODULE_DESCRIPTION("Driver for wireless LAN cards using the TMD7160 PCI bridge");
MODULE_LICENSE("Dual MPL/GPL");
static int __init orinoco_tmd_init(void)
{
printk(KERN_DEBUG "%s\n", version);
return pci_register_driver(&orinoco_tmd_driver);
}
static void __exit orinoco_tmd_exit(void)
{
pci_unregister_driver(&orinoco_tmd_driver);
}
module_init(orinoco_tmd_init);
module_exit(orinoco_tmd_exit);
/*
* Local variables:
* c-indent-level: 8
* c-basic-offset: 8
* tab-width: 8
* End:
*/
| gpl-2.0 |
SM-G920P/TeamSPR_Kernel_OLD | drivers/uwb/uwb-debug.c | 8277 | 9593 | /*
* Ultra Wide Band
* Debug support
*
* Copyright (C) 2005-2006 Intel Corporation
* Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
* Copyright (C) 2008 Cambridge Silicon Radio Ltd.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* FIXME: doc
*/
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/notifier.h>
#include <linux/device.h>
#include <linux/debugfs.h>
#include <linux/uaccess.h>
#include <linux/seq_file.h>
#include <linux/uwb/debug-cmd.h>
#include "uwb-internal.h"
/*
* Debug interface
*
* Per radio controller debugfs files (in uwb/uwbN/):
*
* command: Flexible command interface (see <linux/uwb/debug-cmd.h>).
*
* reservations: information on reservations.
*
* accept: Set to true (Y or 1) to accept reservation requests from
* peers.
*
* drp_avail: DRP availability information.
*/
struct uwb_dbg {
struct uwb_pal pal;
u32 accept;
struct list_head rsvs;
struct dentry *root_d;
struct dentry *command_f;
struct dentry *reservations_f;
struct dentry *accept_f;
struct dentry *drp_avail_f;
spinlock_t list_lock;
};
static struct dentry *root_dir;
static void uwb_dbg_rsv_cb(struct uwb_rsv *rsv)
{
struct uwb_dbg *dbg = rsv->pal_priv;
uwb_rsv_dump("debug", rsv);
if (rsv->state == UWB_RSV_STATE_NONE) {
spin_lock(&dbg->list_lock);
list_del(&rsv->pal_node);
spin_unlock(&dbg->list_lock);
uwb_rsv_destroy(rsv);
}
}
static int cmd_rsv_establish(struct uwb_rc *rc,
struct uwb_dbg_cmd_rsv_establish *cmd)
{
struct uwb_mac_addr macaddr;
struct uwb_rsv *rsv;
struct uwb_dev *target;
int ret;
memcpy(&macaddr, cmd->target, sizeof(macaddr));
target = uwb_dev_get_by_macaddr(rc, &macaddr);
if (target == NULL)
return -ENODEV;
rsv = uwb_rsv_create(rc, uwb_dbg_rsv_cb, rc->dbg);
if (rsv == NULL) {
uwb_dev_put(target);
return -ENOMEM;
}
rsv->target.type = UWB_RSV_TARGET_DEV;
rsv->target.dev = target;
rsv->type = cmd->type;
rsv->max_mas = cmd->max_mas;
rsv->min_mas = cmd->min_mas;
rsv->max_interval = cmd->max_interval;
ret = uwb_rsv_establish(rsv);
if (ret)
uwb_rsv_destroy(rsv);
else {
spin_lock(&(rc->dbg)->list_lock);
list_add_tail(&rsv->pal_node, &rc->dbg->rsvs);
spin_unlock(&(rc->dbg)->list_lock);
}
return ret;
}
static int cmd_rsv_terminate(struct uwb_rc *rc,
struct uwb_dbg_cmd_rsv_terminate *cmd)
{
struct uwb_rsv *rsv, *found = NULL;
int i = 0;
spin_lock(&(rc->dbg)->list_lock);
list_for_each_entry(rsv, &rc->dbg->rsvs, pal_node) {
if (i == cmd->index) {
found = rsv;
uwb_rsv_get(found);
break;
}
i++;
}
spin_unlock(&(rc->dbg)->list_lock);
if (!found)
return -EINVAL;
uwb_rsv_terminate(found);
uwb_rsv_put(found);
return 0;
}
static int cmd_ie_add(struct uwb_rc *rc, struct uwb_dbg_cmd_ie *ie_to_add)
{
return uwb_rc_ie_add(rc,
(const struct uwb_ie_hdr *) ie_to_add->data,
ie_to_add->len);
}
static int cmd_ie_rm(struct uwb_rc *rc, struct uwb_dbg_cmd_ie *ie_to_rm)
{
return uwb_rc_ie_rm(rc, ie_to_rm->data[0]);
}
static ssize_t command_write(struct file *file, const char __user *buf,
size_t len, loff_t *off)
{
struct uwb_rc *rc = file->private_data;
struct uwb_dbg_cmd cmd;
int ret = 0;
if (len != sizeof(struct uwb_dbg_cmd))
return -EINVAL;
if (copy_from_user(&cmd, buf, len) != 0)
return -EFAULT;
switch (cmd.type) {
case UWB_DBG_CMD_RSV_ESTABLISH:
ret = cmd_rsv_establish(rc, &cmd.rsv_establish);
break;
case UWB_DBG_CMD_RSV_TERMINATE:
ret = cmd_rsv_terminate(rc, &cmd.rsv_terminate);
break;
case UWB_DBG_CMD_IE_ADD:
ret = cmd_ie_add(rc, &cmd.ie_add);
break;
case UWB_DBG_CMD_IE_RM:
ret = cmd_ie_rm(rc, &cmd.ie_rm);
break;
case UWB_DBG_CMD_RADIO_START:
ret = uwb_radio_start(&rc->dbg->pal);
break;
case UWB_DBG_CMD_RADIO_STOP:
uwb_radio_stop(&rc->dbg->pal);
break;
default:
return -EINVAL;
}
return ret < 0 ? ret : len;
}
static const struct file_operations command_fops = {
.open = simple_open,
.write = command_write,
.read = NULL,
.llseek = no_llseek,
.owner = THIS_MODULE,
};
static int reservations_print(struct seq_file *s, void *p)
{
struct uwb_rc *rc = s->private;
struct uwb_rsv *rsv;
mutex_lock(&rc->rsvs_mutex);
list_for_each_entry(rsv, &rc->reservations, rc_node) {
struct uwb_dev_addr devaddr;
char owner[UWB_ADDR_STRSIZE], target[UWB_ADDR_STRSIZE];
bool is_owner;
char buf[72];
uwb_dev_addr_print(owner, sizeof(owner), &rsv->owner->dev_addr);
if (rsv->target.type == UWB_RSV_TARGET_DEV) {
devaddr = rsv->target.dev->dev_addr;
is_owner = &rc->uwb_dev == rsv->owner;
} else {
devaddr = rsv->target.devaddr;
is_owner = true;
}
uwb_dev_addr_print(target, sizeof(target), &devaddr);
seq_printf(s, "%c %s -> %s: %s\n",
is_owner ? 'O' : 'T',
owner, target, uwb_rsv_state_str(rsv->state));
seq_printf(s, " stream: %d type: %s\n",
rsv->stream, uwb_rsv_type_str(rsv->type));
bitmap_scnprintf(buf, sizeof(buf), rsv->mas.bm, UWB_NUM_MAS);
seq_printf(s, " %s\n", buf);
}
mutex_unlock(&rc->rsvs_mutex);
return 0;
}
static int reservations_open(struct inode *inode, struct file *file)
{
return single_open(file, reservations_print, inode->i_private);
}
static const struct file_operations reservations_fops = {
.open = reservations_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.owner = THIS_MODULE,
};
static int drp_avail_print(struct seq_file *s, void *p)
{
struct uwb_rc *rc = s->private;
char buf[72];
bitmap_scnprintf(buf, sizeof(buf), rc->drp_avail.global, UWB_NUM_MAS);
seq_printf(s, "global: %s\n", buf);
bitmap_scnprintf(buf, sizeof(buf), rc->drp_avail.local, UWB_NUM_MAS);
seq_printf(s, "local: %s\n", buf);
bitmap_scnprintf(buf, sizeof(buf), rc->drp_avail.pending, UWB_NUM_MAS);
seq_printf(s, "pending: %s\n", buf);
return 0;
}
static int drp_avail_open(struct inode *inode, struct file *file)
{
return single_open(file, drp_avail_print, inode->i_private);
}
static const struct file_operations drp_avail_fops = {
.open = drp_avail_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.owner = THIS_MODULE,
};
static void uwb_dbg_channel_changed(struct uwb_pal *pal, int channel)
{
struct device *dev = &pal->rc->uwb_dev.dev;
if (channel > 0)
dev_info(dev, "debug: channel %d started\n", channel);
else
dev_info(dev, "debug: channel stopped\n");
}
static void uwb_dbg_new_rsv(struct uwb_pal *pal, struct uwb_rsv *rsv)
{
struct uwb_dbg *dbg = container_of(pal, struct uwb_dbg, pal);
if (dbg->accept) {
spin_lock(&dbg->list_lock);
list_add_tail(&rsv->pal_node, &dbg->rsvs);
spin_unlock(&dbg->list_lock);
uwb_rsv_accept(rsv, uwb_dbg_rsv_cb, dbg);
}
}
/**
* uwb_dbg_add_rc - add a debug interface for a radio controller
* @rc: the radio controller
*/
void uwb_dbg_add_rc(struct uwb_rc *rc)
{
rc->dbg = kzalloc(sizeof(struct uwb_dbg), GFP_KERNEL);
if (rc->dbg == NULL)
return;
INIT_LIST_HEAD(&rc->dbg->rsvs);
spin_lock_init(&(rc->dbg)->list_lock);
uwb_pal_init(&rc->dbg->pal);
rc->dbg->pal.rc = rc;
rc->dbg->pal.channel_changed = uwb_dbg_channel_changed;
rc->dbg->pal.new_rsv = uwb_dbg_new_rsv;
uwb_pal_register(&rc->dbg->pal);
if (root_dir) {
rc->dbg->root_d = debugfs_create_dir(dev_name(&rc->uwb_dev.dev),
root_dir);
rc->dbg->command_f = debugfs_create_file("command", 0200,
rc->dbg->root_d, rc,
&command_fops);
rc->dbg->reservations_f = debugfs_create_file("reservations", 0444,
rc->dbg->root_d, rc,
&reservations_fops);
rc->dbg->accept_f = debugfs_create_bool("accept", 0644,
rc->dbg->root_d,
&rc->dbg->accept);
rc->dbg->drp_avail_f = debugfs_create_file("drp_avail", 0444,
rc->dbg->root_d, rc,
&drp_avail_fops);
}
}
/**
* uwb_dbg_del_rc - remove a radio controller's debug interface
* @rc: the radio controller
*/
void uwb_dbg_del_rc(struct uwb_rc *rc)
{
struct uwb_rsv *rsv, *t;
if (rc->dbg == NULL)
return;
list_for_each_entry_safe(rsv, t, &rc->dbg->rsvs, pal_node) {
uwb_rsv_terminate(rsv);
}
uwb_pal_unregister(&rc->dbg->pal);
if (root_dir) {
debugfs_remove(rc->dbg->drp_avail_f);
debugfs_remove(rc->dbg->accept_f);
debugfs_remove(rc->dbg->reservations_f);
debugfs_remove(rc->dbg->command_f);
debugfs_remove(rc->dbg->root_d);
}
}
/**
* uwb_dbg_exit - initialize the debug interface sub-module
*/
void uwb_dbg_init(void)
{
root_dir = debugfs_create_dir("uwb", NULL);
}
/**
* uwb_dbg_exit - clean-up the debug interface sub-module
*/
void uwb_dbg_exit(void)
{
debugfs_remove(root_dir);
}
/**
* uwb_dbg_create_pal_dir - create a debugfs directory for a PAL
* @pal: The PAL.
*/
struct dentry *uwb_dbg_create_pal_dir(struct uwb_pal *pal)
{
struct uwb_rc *rc = pal->rc;
if (root_dir && rc->dbg && rc->dbg->root_d && pal->name)
return debugfs_create_dir(pal->name, rc->dbg->root_d);
return NULL;
}
| gpl-2.0 |
Tasssadar/android_kernel_google_msm | drivers/usb/c67x00/c67x00-sched.c | 8277 | 30484 | /*
* c67x00-sched.c: Cypress C67X00 USB Host Controller Driver - TD scheduling
*
* Copyright (C) 2006-2008 Barco N.V.
* Derived from the Cypress cy7c67200/300 ezusb linux driver and
* based on multiple host controller drivers inside the linux kernel.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA.
*/
#include <linux/kthread.h>
#include <linux/slab.h>
#include "c67x00.h"
#include "c67x00-hcd.h"
/*
* These are the stages for a control urb, they are kept
* in both urb->interval and td->privdata.
*/
#define SETUP_STAGE 0
#define DATA_STAGE 1
#define STATUS_STAGE 2
/* -------------------------------------------------------------------------- */
/**
* struct c67x00_ep_data: Host endpoint data structure
*/
struct c67x00_ep_data {
struct list_head queue;
struct list_head node;
struct usb_host_endpoint *hep;
struct usb_device *dev;
u16 next_frame; /* For int/isoc transactions */
};
/**
* struct c67x00_td
*
* Hardware parts are little endiannes, SW in CPU endianess.
*/
struct c67x00_td {
/* HW specific part */
__le16 ly_base_addr; /* Bytes 0-1 */
__le16 port_length; /* Bytes 2-3 */
u8 pid_ep; /* Byte 4 */
u8 dev_addr; /* Byte 5 */
u8 ctrl_reg; /* Byte 6 */
u8 status; /* Byte 7 */
u8 retry_cnt; /* Byte 8 */
#define TT_OFFSET 2
#define TT_CONTROL 0
#define TT_ISOCHRONOUS 1
#define TT_BULK 2
#define TT_INTERRUPT 3
u8 residue; /* Byte 9 */
__le16 next_td_addr; /* Bytes 10-11 */
/* SW part */
struct list_head td_list;
u16 td_addr;
void *data;
struct urb *urb;
unsigned long privdata;
/* These are needed for handling the toggle bits:
* an urb can be dequeued while a td is in progress
* after checking the td, the toggle bit might need to
* be fixed */
struct c67x00_ep_data *ep_data;
unsigned int pipe;
};
struct c67x00_urb_priv {
struct list_head hep_node;
struct urb *urb;
int port;
int cnt; /* packet number for isoc */
int status;
struct c67x00_ep_data *ep_data;
};
#define td_udev(td) ((td)->ep_data->dev)
#define CY_TD_SIZE 12
#define TD_PIDEP_OFFSET 0x04
#define TD_PIDEPMASK_PID 0xF0
#define TD_PIDEPMASK_EP 0x0F
#define TD_PORTLENMASK_DL 0x02FF
#define TD_PORTLENMASK_PN 0xC000
#define TD_STATUS_OFFSET 0x07
#define TD_STATUSMASK_ACK 0x01
#define TD_STATUSMASK_ERR 0x02
#define TD_STATUSMASK_TMOUT 0x04
#define TD_STATUSMASK_SEQ 0x08
#define TD_STATUSMASK_SETUP 0x10
#define TD_STATUSMASK_OVF 0x20
#define TD_STATUSMASK_NAK 0x40
#define TD_STATUSMASK_STALL 0x80
#define TD_ERROR_MASK (TD_STATUSMASK_ERR | TD_STATUSMASK_TMOUT | \
TD_STATUSMASK_STALL)
#define TD_RETRYCNT_OFFSET 0x08
#define TD_RETRYCNTMASK_ACT_FLG 0x10
#define TD_RETRYCNTMASK_TX_TYPE 0x0C
#define TD_RETRYCNTMASK_RTY_CNT 0x03
#define TD_RESIDUE_OVERFLOW 0x80
#define TD_PID_IN 0x90
/* Residue: signed 8bits, neg -> OVERFLOW, pos -> UNDERFLOW */
#define td_residue(td) ((__s8)(td->residue))
#define td_ly_base_addr(td) (__le16_to_cpu((td)->ly_base_addr))
#define td_port_length(td) (__le16_to_cpu((td)->port_length))
#define td_next_td_addr(td) (__le16_to_cpu((td)->next_td_addr))
#define td_active(td) ((td)->retry_cnt & TD_RETRYCNTMASK_ACT_FLG)
#define td_length(td) (td_port_length(td) & TD_PORTLENMASK_DL)
#define td_sequence_ok(td) (!td->status || \
(!(td->status & TD_STATUSMASK_SEQ) == \
!(td->ctrl_reg & SEQ_SEL)))
#define td_acked(td) (!td->status || \
(td->status & TD_STATUSMASK_ACK))
#define td_actual_bytes(td) (td_length(td) - td_residue(td))
/* -------------------------------------------------------------------------- */
#ifdef DEBUG
/**
* dbg_td - Dump the contents of the TD
*/
static void dbg_td(struct c67x00_hcd *c67x00, struct c67x00_td *td, char *msg)
{
struct device *dev = c67x00_hcd_dev(c67x00);
dev_dbg(dev, "### %s at 0x%04x\n", msg, td->td_addr);
dev_dbg(dev, "urb: 0x%p\n", td->urb);
dev_dbg(dev, "endpoint: %4d\n", usb_pipeendpoint(td->pipe));
dev_dbg(dev, "pipeout: %4d\n", usb_pipeout(td->pipe));
dev_dbg(dev, "ly_base_addr: 0x%04x\n", td_ly_base_addr(td));
dev_dbg(dev, "port_length: 0x%04x\n", td_port_length(td));
dev_dbg(dev, "pid_ep: 0x%02x\n", td->pid_ep);
dev_dbg(dev, "dev_addr: 0x%02x\n", td->dev_addr);
dev_dbg(dev, "ctrl_reg: 0x%02x\n", td->ctrl_reg);
dev_dbg(dev, "status: 0x%02x\n", td->status);
dev_dbg(dev, "retry_cnt: 0x%02x\n", td->retry_cnt);
dev_dbg(dev, "residue: 0x%02x\n", td->residue);
dev_dbg(dev, "next_td_addr: 0x%04x\n", td_next_td_addr(td));
dev_dbg(dev, "data:");
print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
td->data, td_length(td), 1);
}
#else /* DEBUG */
static inline void
dbg_td(struct c67x00_hcd *c67x00, struct c67x00_td *td, char *msg) { }
#endif /* DEBUG */
/* -------------------------------------------------------------------------- */
/* Helper functions */
static inline u16 c67x00_get_current_frame_number(struct c67x00_hcd *c67x00)
{
return c67x00_ll_husb_get_frame(c67x00->sie) & HOST_FRAME_MASK;
}
/**
* frame_add
* Software wraparound for framenumbers.
*/
static inline u16 frame_add(u16 a, u16 b)
{
return (a + b) & HOST_FRAME_MASK;
}
/**
* frame_after - is frame a after frame b
*/
static inline int frame_after(u16 a, u16 b)
{
return ((HOST_FRAME_MASK + a - b) & HOST_FRAME_MASK) <
(HOST_FRAME_MASK / 2);
}
/**
* frame_after_eq - is frame a after or equal to frame b
*/
static inline int frame_after_eq(u16 a, u16 b)
{
return ((HOST_FRAME_MASK + 1 + a - b) & HOST_FRAME_MASK) <
(HOST_FRAME_MASK / 2);
}
/* -------------------------------------------------------------------------- */
/**
* c67x00_release_urb - remove link from all tds to this urb
* Disconnects the urb from it's tds, so that it can be given back.
* pre: urb->hcpriv != NULL
*/
static void c67x00_release_urb(struct c67x00_hcd *c67x00, struct urb *urb)
{
struct c67x00_td *td;
struct c67x00_urb_priv *urbp;
BUG_ON(!urb);
c67x00->urb_count--;
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
c67x00->urb_iso_count--;
if (c67x00->urb_iso_count == 0)
c67x00->max_frame_bw = MAX_FRAME_BW_STD;
}
/* TODO this might be not so efficient when we've got many urbs!
* Alternatives:
* * only clear when needed
* * keep a list of tds with each urbp
*/
list_for_each_entry(td, &c67x00->td_list, td_list)
if (urb == td->urb)
td->urb = NULL;
urbp = urb->hcpriv;
urb->hcpriv = NULL;
list_del(&urbp->hep_node);
kfree(urbp);
}
/* -------------------------------------------------------------------------- */
static struct c67x00_ep_data *
c67x00_ep_data_alloc(struct c67x00_hcd *c67x00, struct urb *urb)
{
struct usb_host_endpoint *hep = urb->ep;
struct c67x00_ep_data *ep_data;
int type;
c67x00->current_frame = c67x00_get_current_frame_number(c67x00);
/* Check if endpoint already has a c67x00_ep_data struct allocated */
if (hep->hcpriv) {
ep_data = hep->hcpriv;
if (frame_after(c67x00->current_frame, ep_data->next_frame))
ep_data->next_frame =
frame_add(c67x00->current_frame, 1);
return hep->hcpriv;
}
/* Allocate and initialize a new c67x00 endpoint data structure */
ep_data = kzalloc(sizeof(*ep_data), GFP_ATOMIC);
if (!ep_data)
return NULL;
INIT_LIST_HEAD(&ep_data->queue);
INIT_LIST_HEAD(&ep_data->node);
ep_data->hep = hep;
/* hold a reference to udev as long as this endpoint lives,
* this is needed to possibly fix the data toggle */
ep_data->dev = usb_get_dev(urb->dev);
hep->hcpriv = ep_data;
/* For ISOC and INT endpoints, start ASAP: */
ep_data->next_frame = frame_add(c67x00->current_frame, 1);
/* Add the endpoint data to one of the pipe lists; must be added
in order of endpoint address */
type = usb_pipetype(urb->pipe);
if (list_empty(&ep_data->node)) {
list_add(&ep_data->node, &c67x00->list[type]);
} else {
struct c67x00_ep_data *prev;
list_for_each_entry(prev, &c67x00->list[type], node) {
if (prev->hep->desc.bEndpointAddress >
hep->desc.bEndpointAddress) {
list_add(&ep_data->node, prev->node.prev);
break;
}
}
}
return ep_data;
}
static int c67x00_ep_data_free(struct usb_host_endpoint *hep)
{
struct c67x00_ep_data *ep_data = hep->hcpriv;
if (!ep_data)
return 0;
if (!list_empty(&ep_data->queue))
return -EBUSY;
usb_put_dev(ep_data->dev);
list_del(&ep_data->queue);
list_del(&ep_data->node);
kfree(ep_data);
hep->hcpriv = NULL;
return 0;
}
void c67x00_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
{
struct c67x00_hcd *c67x00 = hcd_to_c67x00_hcd(hcd);
unsigned long flags;
if (!list_empty(&ep->urb_list))
dev_warn(c67x00_hcd_dev(c67x00), "error: urb list not empty\n");
spin_lock_irqsave(&c67x00->lock, flags);
/* loop waiting for all transfers in the endpoint queue to complete */
while (c67x00_ep_data_free(ep)) {
/* Drop the lock so we can sleep waiting for the hardware */
spin_unlock_irqrestore(&c67x00->lock, flags);
/* it could happen that we reinitialize this completion, while
* somebody was waiting for that completion. The timeout and
* while loop handle such cases, but this might be improved */
INIT_COMPLETION(c67x00->endpoint_disable);
c67x00_sched_kick(c67x00);
wait_for_completion_timeout(&c67x00->endpoint_disable, 1 * HZ);
spin_lock_irqsave(&c67x00->lock, flags);
}
spin_unlock_irqrestore(&c67x00->lock, flags);
}
/* -------------------------------------------------------------------------- */
static inline int get_root_port(struct usb_device *dev)
{
while (dev->parent->parent)
dev = dev->parent;
return dev->portnum;
}
int c67x00_urb_enqueue(struct usb_hcd *hcd,
struct urb *urb, gfp_t mem_flags)
{
int ret;
unsigned long flags;
struct c67x00_urb_priv *urbp;
struct c67x00_hcd *c67x00 = hcd_to_c67x00_hcd(hcd);
int port = get_root_port(urb->dev)-1;
spin_lock_irqsave(&c67x00->lock, flags);
/* Make sure host controller is running */
if (!HC_IS_RUNNING(hcd->state)) {
ret = -ENODEV;
goto err_not_linked;
}
ret = usb_hcd_link_urb_to_ep(hcd, urb);
if (ret)
goto err_not_linked;
/* Allocate and initialize urb private data */
urbp = kzalloc(sizeof(*urbp), mem_flags);
if (!urbp) {
ret = -ENOMEM;
goto err_urbp;
}
INIT_LIST_HEAD(&urbp->hep_node);
urbp->urb = urb;
urbp->port = port;
urbp->ep_data = c67x00_ep_data_alloc(c67x00, urb);
if (!urbp->ep_data) {
ret = -ENOMEM;
goto err_epdata;
}
/* TODO claim bandwidth with usb_claim_bandwidth?
* also release it somewhere! */
urb->hcpriv = urbp;
urb->actual_length = 0; /* Nothing received/transmitted yet */
switch (usb_pipetype(urb->pipe)) {
case PIPE_CONTROL:
urb->interval = SETUP_STAGE;
break;
case PIPE_INTERRUPT:
break;
case PIPE_BULK:
break;
case PIPE_ISOCHRONOUS:
if (c67x00->urb_iso_count == 0)
c67x00->max_frame_bw = MAX_FRAME_BW_ISO;
c67x00->urb_iso_count++;
/* Assume always URB_ISO_ASAP, FIXME */
if (list_empty(&urbp->ep_data->queue))
urb->start_frame = urbp->ep_data->next_frame;
else {
/* Go right after the last one */
struct urb *last_urb;
last_urb = list_entry(urbp->ep_data->queue.prev,
struct c67x00_urb_priv,
hep_node)->urb;
urb->start_frame =
frame_add(last_urb->start_frame,
last_urb->number_of_packets *
last_urb->interval);
}
urbp->cnt = 0;
break;
}
/* Add the URB to the endpoint queue */
list_add_tail(&urbp->hep_node, &urbp->ep_data->queue);
/* If this is the only URB, kick start the controller */
if (!c67x00->urb_count++)
c67x00_ll_hpi_enable_sofeop(c67x00->sie);
c67x00_sched_kick(c67x00);
spin_unlock_irqrestore(&c67x00->lock, flags);
return 0;
err_epdata:
kfree(urbp);
err_urbp:
usb_hcd_unlink_urb_from_ep(hcd, urb);
err_not_linked:
spin_unlock_irqrestore(&c67x00->lock, flags);
return ret;
}
int c67x00_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
{
struct c67x00_hcd *c67x00 = hcd_to_c67x00_hcd(hcd);
unsigned long flags;
int rc;
spin_lock_irqsave(&c67x00->lock, flags);
rc = usb_hcd_check_unlink_urb(hcd, urb, status);
if (rc)
goto done;
c67x00_release_urb(c67x00, urb);
usb_hcd_unlink_urb_from_ep(hcd, urb);
spin_unlock(&c67x00->lock);
usb_hcd_giveback_urb(hcd, urb, status);
spin_lock(&c67x00->lock);
spin_unlock_irqrestore(&c67x00->lock, flags);
return 0;
done:
spin_unlock_irqrestore(&c67x00->lock, flags);
return rc;
}
/* -------------------------------------------------------------------------- */
/*
* pre: c67x00 locked, urb unlocked
*/
static void
c67x00_giveback_urb(struct c67x00_hcd *c67x00, struct urb *urb, int status)
{
struct c67x00_urb_priv *urbp;
if (!urb)
return;
urbp = urb->hcpriv;
urbp->status = status;
list_del_init(&urbp->hep_node);
c67x00_release_urb(c67x00, urb);
usb_hcd_unlink_urb_from_ep(c67x00_hcd_to_hcd(c67x00), urb);
spin_unlock(&c67x00->lock);
usb_hcd_giveback_urb(c67x00_hcd_to_hcd(c67x00), urb, urbp->status);
spin_lock(&c67x00->lock);
}
/* -------------------------------------------------------------------------- */
static int c67x00_claim_frame_bw(struct c67x00_hcd *c67x00, struct urb *urb,
int len, int periodic)
{
struct c67x00_urb_priv *urbp = urb->hcpriv;
int bit_time;
/* According to the C67x00 BIOS user manual, page 3-18,19, the
* following calculations provide the full speed bit times for
* a transaction.
*
* FS(in) = 112.5 + 9.36*BC + HOST_DELAY
* FS(in,iso) = 90.5 + 9.36*BC + HOST_DELAY
* FS(out) = 112.5 + 9.36*BC + HOST_DELAY
* FS(out,iso) = 78.4 + 9.36*BC + HOST_DELAY
* LS(in) = 802.4 + 75.78*BC + HOST_DELAY
* LS(out) = 802.6 + 74.67*BC + HOST_DELAY
*
* HOST_DELAY == 106 for the c67200 and c67300.
*/
/* make calculations in 1/100 bit times to maintain resolution */
if (urbp->ep_data->dev->speed == USB_SPEED_LOW) {
/* Low speed pipe */
if (usb_pipein(urb->pipe))
bit_time = 80240 + 7578*len;
else
bit_time = 80260 + 7467*len;
} else {
/* FS pipes */
if (usb_pipeisoc(urb->pipe))
bit_time = usb_pipein(urb->pipe) ? 9050 : 7840;
else
bit_time = 11250;
bit_time += 936*len;
}
/* Scale back down to integer bit times. Use a host delay of 106.
* (this is the only place it is used) */
bit_time = ((bit_time+50) / 100) + 106;
if (unlikely(bit_time + c67x00->bandwidth_allocated >=
c67x00->max_frame_bw))
return -EMSGSIZE;
if (unlikely(c67x00->next_td_addr + CY_TD_SIZE >=
c67x00->td_base_addr + SIE_TD_SIZE))
return -EMSGSIZE;
if (unlikely(c67x00->next_buf_addr + len >=
c67x00->buf_base_addr + SIE_TD_BUF_SIZE))
return -EMSGSIZE;
if (periodic) {
if (unlikely(bit_time + c67x00->periodic_bw_allocated >=
MAX_PERIODIC_BW(c67x00->max_frame_bw)))
return -EMSGSIZE;
c67x00->periodic_bw_allocated += bit_time;
}
c67x00->bandwidth_allocated += bit_time;
return 0;
}
/* -------------------------------------------------------------------------- */
/**
* td_addr and buf_addr must be word aligned
*/
static int c67x00_create_td(struct c67x00_hcd *c67x00, struct urb *urb,
void *data, int len, int pid, int toggle,
unsigned long privdata)
{
struct c67x00_td *td;
struct c67x00_urb_priv *urbp = urb->hcpriv;
const __u8 active_flag = 1, retry_cnt = 1;
__u8 cmd = 0;
int tt = 0;
if (c67x00_claim_frame_bw(c67x00, urb, len, usb_pipeisoc(urb->pipe)
|| usb_pipeint(urb->pipe)))
return -EMSGSIZE; /* Not really an error, but expected */
td = kzalloc(sizeof(*td), GFP_ATOMIC);
if (!td)
return -ENOMEM;
td->pipe = urb->pipe;
td->ep_data = urbp->ep_data;
if ((td_udev(td)->speed == USB_SPEED_LOW) &&
!(c67x00->low_speed_ports & (1 << urbp->port)))
cmd |= PREAMBLE_EN;
switch (usb_pipetype(td->pipe)) {
case PIPE_ISOCHRONOUS:
tt = TT_ISOCHRONOUS;
cmd |= ISO_EN;
break;
case PIPE_CONTROL:
tt = TT_CONTROL;
break;
case PIPE_BULK:
tt = TT_BULK;
break;
case PIPE_INTERRUPT:
tt = TT_INTERRUPT;
break;
}
if (toggle)
cmd |= SEQ_SEL;
cmd |= ARM_EN;
/* SW part */
td->td_addr = c67x00->next_td_addr;
c67x00->next_td_addr = c67x00->next_td_addr + CY_TD_SIZE;
/* HW part */
td->ly_base_addr = __cpu_to_le16(c67x00->next_buf_addr);
td->port_length = __cpu_to_le16((c67x00->sie->sie_num << 15) |
(urbp->port << 14) | (len & 0x3FF));
td->pid_ep = ((pid & 0xF) << TD_PIDEP_OFFSET) |
(usb_pipeendpoint(td->pipe) & 0xF);
td->dev_addr = usb_pipedevice(td->pipe) & 0x7F;
td->ctrl_reg = cmd;
td->status = 0;
td->retry_cnt = (tt << TT_OFFSET) | (active_flag << 4) | retry_cnt;
td->residue = 0;
td->next_td_addr = __cpu_to_le16(c67x00->next_td_addr);
/* SW part */
td->data = data;
td->urb = urb;
td->privdata = privdata;
c67x00->next_buf_addr += (len + 1) & ~0x01; /* properly align */
list_add_tail(&td->td_list, &c67x00->td_list);
return 0;
}
static inline void c67x00_release_td(struct c67x00_td *td)
{
list_del_init(&td->td_list);
kfree(td);
}
/* -------------------------------------------------------------------------- */
static int c67x00_add_data_urb(struct c67x00_hcd *c67x00, struct urb *urb)
{
int remaining;
int toggle;
int pid;
int ret = 0;
int maxps;
int need_empty;
toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
usb_pipeout(urb->pipe));
remaining = urb->transfer_buffer_length - urb->actual_length;
maxps = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
need_empty = (urb->transfer_flags & URB_ZERO_PACKET) &&
usb_pipeout(urb->pipe) && !(remaining % maxps);
while (remaining || need_empty) {
int len;
char *td_buf;
len = (remaining > maxps) ? maxps : remaining;
if (!len)
need_empty = 0;
pid = usb_pipeout(urb->pipe) ? USB_PID_OUT : USB_PID_IN;
td_buf = urb->transfer_buffer + urb->transfer_buffer_length -
remaining;
ret = c67x00_create_td(c67x00, urb, td_buf, len, pid, toggle,
DATA_STAGE);
if (ret)
return ret; /* td wasn't created */
toggle ^= 1;
remaining -= len;
if (usb_pipecontrol(urb->pipe))
break;
}
return 0;
}
/**
* return 0 in case more bandwidth is available, else errorcode
*/
static int c67x00_add_ctrl_urb(struct c67x00_hcd *c67x00, struct urb *urb)
{
int ret;
int pid;
switch (urb->interval) {
default:
case SETUP_STAGE:
ret = c67x00_create_td(c67x00, urb, urb->setup_packet,
8, USB_PID_SETUP, 0, SETUP_STAGE);
if (ret)
return ret;
urb->interval = SETUP_STAGE;
usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
usb_pipeout(urb->pipe), 1);
break;
case DATA_STAGE:
if (urb->transfer_buffer_length) {
ret = c67x00_add_data_urb(c67x00, urb);
if (ret)
return ret;
break;
} /* else fallthrough */
case STATUS_STAGE:
pid = !usb_pipeout(urb->pipe) ? USB_PID_OUT : USB_PID_IN;
ret = c67x00_create_td(c67x00, urb, NULL, 0, pid, 1,
STATUS_STAGE);
if (ret)
return ret;
break;
}
return 0;
}
/*
* return 0 in case more bandwidth is available, else errorcode
*/
static int c67x00_add_int_urb(struct c67x00_hcd *c67x00, struct urb *urb)
{
struct c67x00_urb_priv *urbp = urb->hcpriv;
if (frame_after_eq(c67x00->current_frame, urbp->ep_data->next_frame)) {
urbp->ep_data->next_frame =
frame_add(urbp->ep_data->next_frame, urb->interval);
return c67x00_add_data_urb(c67x00, urb);
}
return 0;
}
static int c67x00_add_iso_urb(struct c67x00_hcd *c67x00, struct urb *urb)
{
struct c67x00_urb_priv *urbp = urb->hcpriv;
if (frame_after_eq(c67x00->current_frame, urbp->ep_data->next_frame)) {
char *td_buf;
int len, pid, ret;
BUG_ON(urbp->cnt >= urb->number_of_packets);
td_buf = urb->transfer_buffer +
urb->iso_frame_desc[urbp->cnt].offset;
len = urb->iso_frame_desc[urbp->cnt].length;
pid = usb_pipeout(urb->pipe) ? USB_PID_OUT : USB_PID_IN;
ret = c67x00_create_td(c67x00, urb, td_buf, len, pid, 0,
urbp->cnt);
if (ret) {
printk(KERN_DEBUG "create failed: %d\n", ret);
urb->iso_frame_desc[urbp->cnt].actual_length = 0;
urb->iso_frame_desc[urbp->cnt].status = ret;
if (urbp->cnt + 1 == urb->number_of_packets)
c67x00_giveback_urb(c67x00, urb, 0);
}
urbp->ep_data->next_frame =
frame_add(urbp->ep_data->next_frame, urb->interval);
urbp->cnt++;
}
return 0;
}
/* -------------------------------------------------------------------------- */
static void c67x00_fill_from_list(struct c67x00_hcd *c67x00, int type,
int (*add)(struct c67x00_hcd *, struct urb *))
{
struct c67x00_ep_data *ep_data;
struct urb *urb;
/* traverse every endpoint on the list */
list_for_each_entry(ep_data, &c67x00->list[type], node) {
if (!list_empty(&ep_data->queue)) {
/* and add the first urb */
/* isochronous transfer rely on this */
urb = list_entry(ep_data->queue.next,
struct c67x00_urb_priv,
hep_node)->urb;
add(c67x00, urb);
}
}
}
static void c67x00_fill_frame(struct c67x00_hcd *c67x00)
{
struct c67x00_td *td, *ttd;
/* Check if we can proceed */
if (!list_empty(&c67x00->td_list)) {
dev_warn(c67x00_hcd_dev(c67x00),
"TD list not empty! This should not happen!\n");
list_for_each_entry_safe(td, ttd, &c67x00->td_list, td_list) {
dbg_td(c67x00, td, "Unprocessed td");
c67x00_release_td(td);
}
}
/* Reinitialize variables */
c67x00->bandwidth_allocated = 0;
c67x00->periodic_bw_allocated = 0;
c67x00->next_td_addr = c67x00->td_base_addr;
c67x00->next_buf_addr = c67x00->buf_base_addr;
/* Fill the list */
c67x00_fill_from_list(c67x00, PIPE_ISOCHRONOUS, c67x00_add_iso_urb);
c67x00_fill_from_list(c67x00, PIPE_INTERRUPT, c67x00_add_int_urb);
c67x00_fill_from_list(c67x00, PIPE_CONTROL, c67x00_add_ctrl_urb);
c67x00_fill_from_list(c67x00, PIPE_BULK, c67x00_add_data_urb);
}
/* -------------------------------------------------------------------------- */
/**
* Get TD from C67X00
*/
static inline void
c67x00_parse_td(struct c67x00_hcd *c67x00, struct c67x00_td *td)
{
c67x00_ll_read_mem_le16(c67x00->sie->dev,
td->td_addr, td, CY_TD_SIZE);
if (usb_pipein(td->pipe) && td_actual_bytes(td))
c67x00_ll_read_mem_le16(c67x00->sie->dev, td_ly_base_addr(td),
td->data, td_actual_bytes(td));
}
static int c67x00_td_to_error(struct c67x00_hcd *c67x00, struct c67x00_td *td)
{
if (td->status & TD_STATUSMASK_ERR) {
dbg_td(c67x00, td, "ERROR_FLAG");
return -EILSEQ;
}
if (td->status & TD_STATUSMASK_STALL) {
/* dbg_td(c67x00, td, "STALL"); */
return -EPIPE;
}
if (td->status & TD_STATUSMASK_TMOUT) {
dbg_td(c67x00, td, "TIMEOUT");
return -ETIMEDOUT;
}
return 0;
}
static inline int c67x00_end_of_data(struct c67x00_td *td)
{
int maxps, need_empty, remaining;
struct urb *urb = td->urb;
int act_bytes;
act_bytes = td_actual_bytes(td);
if (unlikely(!act_bytes))
return 1; /* This was an empty packet */
maxps = usb_maxpacket(td_udev(td), td->pipe, usb_pipeout(td->pipe));
if (unlikely(act_bytes < maxps))
return 1; /* Smaller then full packet */
remaining = urb->transfer_buffer_length - urb->actual_length;
need_empty = (urb->transfer_flags & URB_ZERO_PACKET) &&
usb_pipeout(urb->pipe) && !(remaining % maxps);
if (unlikely(!remaining && !need_empty))
return 1;
return 0;
}
/* -------------------------------------------------------------------------- */
/* Remove all td's from the list which come
* after last_td and are meant for the same pipe.
* This is used when a short packet has occurred */
static inline void c67x00_clear_pipe(struct c67x00_hcd *c67x00,
struct c67x00_td *last_td)
{
struct c67x00_td *td, *tmp;
td = last_td;
tmp = last_td;
while (td->td_list.next != &c67x00->td_list) {
td = list_entry(td->td_list.next, struct c67x00_td, td_list);
if (td->pipe == last_td->pipe) {
c67x00_release_td(td);
td = tmp;
}
tmp = td;
}
}
/* -------------------------------------------------------------------------- */
static void c67x00_handle_successful_td(struct c67x00_hcd *c67x00,
struct c67x00_td *td)
{
struct urb *urb = td->urb;
if (!urb)
return;
urb->actual_length += td_actual_bytes(td);
switch (usb_pipetype(td->pipe)) {
/* isochronous tds are handled separately */
case PIPE_CONTROL:
switch (td->privdata) {
case SETUP_STAGE:
urb->interval =
urb->transfer_buffer_length ?
DATA_STAGE : STATUS_STAGE;
/* Don't count setup_packet with normal data: */
urb->actual_length = 0;
break;
case DATA_STAGE:
if (c67x00_end_of_data(td)) {
urb->interval = STATUS_STAGE;
c67x00_clear_pipe(c67x00, td);
}
break;
case STATUS_STAGE:
urb->interval = 0;
c67x00_giveback_urb(c67x00, urb, 0);
break;
}
break;
case PIPE_INTERRUPT:
case PIPE_BULK:
if (unlikely(c67x00_end_of_data(td))) {
c67x00_clear_pipe(c67x00, td);
c67x00_giveback_urb(c67x00, urb, 0);
}
break;
}
}
static void c67x00_handle_isoc(struct c67x00_hcd *c67x00, struct c67x00_td *td)
{
struct urb *urb = td->urb;
struct c67x00_urb_priv *urbp;
int cnt;
if (!urb)
return;
urbp = urb->hcpriv;
cnt = td->privdata;
if (td->status & TD_ERROR_MASK)
urb->error_count++;
urb->iso_frame_desc[cnt].actual_length = td_actual_bytes(td);
urb->iso_frame_desc[cnt].status = c67x00_td_to_error(c67x00, td);
if (cnt + 1 == urb->number_of_packets) /* Last packet */
c67x00_giveback_urb(c67x00, urb, 0);
}
/* -------------------------------------------------------------------------- */
/**
* c67x00_check_td_list - handle tds which have been processed by the c67x00
* pre: current_td == 0
*/
static inline void c67x00_check_td_list(struct c67x00_hcd *c67x00)
{
struct c67x00_td *td, *tmp;
struct urb *urb;
int ack_ok;
int clear_endpoint;
list_for_each_entry_safe(td, tmp, &c67x00->td_list, td_list) {
/* get the TD */
c67x00_parse_td(c67x00, td);
urb = td->urb; /* urb can be NULL! */
ack_ok = 0;
clear_endpoint = 1;
/* Handle isochronous transfers separately */
if (usb_pipeisoc(td->pipe)) {
clear_endpoint = 0;
c67x00_handle_isoc(c67x00, td);
goto cont;
}
/* When an error occurs, all td's for that pipe go into an
* inactive state. This state matches successful transfers so
* we must make sure not to service them. */
if (td->status & TD_ERROR_MASK) {
c67x00_giveback_urb(c67x00, urb,
c67x00_td_to_error(c67x00, td));
goto cont;
}
if ((td->status & TD_STATUSMASK_NAK) || !td_sequence_ok(td) ||
!td_acked(td))
goto cont;
/* Sequence ok and acked, don't need to fix toggle */
ack_ok = 1;
if (unlikely(td->status & TD_STATUSMASK_OVF)) {
if (td_residue(td) & TD_RESIDUE_OVERFLOW) {
/* Overflow */
c67x00_giveback_urb(c67x00, urb, -EOVERFLOW);
goto cont;
}
}
clear_endpoint = 0;
c67x00_handle_successful_td(c67x00, td);
cont:
if (clear_endpoint)
c67x00_clear_pipe(c67x00, td);
if (ack_ok)
usb_settoggle(td_udev(td), usb_pipeendpoint(td->pipe),
usb_pipeout(td->pipe),
!(td->ctrl_reg & SEQ_SEL));
/* next in list could have been removed, due to clear_pipe! */
tmp = list_entry(td->td_list.next, typeof(*td), td_list);
c67x00_release_td(td);
}
}
/* -------------------------------------------------------------------------- */
static inline int c67x00_all_tds_processed(struct c67x00_hcd *c67x00)
{
/* If all tds are processed, we can check the previous frame (if
* there was any) and start our next frame.
*/
return !c67x00_ll_husb_get_current_td(c67x00->sie);
}
/**
* Send td to C67X00
*/
static void c67x00_send_td(struct c67x00_hcd *c67x00, struct c67x00_td *td)
{
int len = td_length(td);
if (len && ((td->pid_ep & TD_PIDEPMASK_PID) != TD_PID_IN))
c67x00_ll_write_mem_le16(c67x00->sie->dev, td_ly_base_addr(td),
td->data, len);
c67x00_ll_write_mem_le16(c67x00->sie->dev,
td->td_addr, td, CY_TD_SIZE);
}
static void c67x00_send_frame(struct c67x00_hcd *c67x00)
{
struct c67x00_td *td;
if (list_empty(&c67x00->td_list))
dev_warn(c67x00_hcd_dev(c67x00),
"%s: td list should not be empty here!\n",
__func__);
list_for_each_entry(td, &c67x00->td_list, td_list) {
if (td->td_list.next == &c67x00->td_list)
td->next_td_addr = 0; /* Last td in list */
c67x00_send_td(c67x00, td);
}
c67x00_ll_husb_set_current_td(c67x00->sie, c67x00->td_base_addr);
}
/* -------------------------------------------------------------------------- */
/**
* c67x00_do_work - Schedulers state machine
*/
static void c67x00_do_work(struct c67x00_hcd *c67x00)
{
spin_lock(&c67x00->lock);
/* Make sure all tds are processed */
if (!c67x00_all_tds_processed(c67x00))
goto out;
c67x00_check_td_list(c67x00);
/* no td's are being processed (current == 0)
* and all have been "checked" */
complete(&c67x00->endpoint_disable);
if (!list_empty(&c67x00->td_list))
goto out;
c67x00->current_frame = c67x00_get_current_frame_number(c67x00);
if (c67x00->current_frame == c67x00->last_frame)
goto out; /* Don't send tds in same frame */
c67x00->last_frame = c67x00->current_frame;
/* If no urbs are scheduled, our work is done */
if (!c67x00->urb_count) {
c67x00_ll_hpi_disable_sofeop(c67x00->sie);
goto out;
}
c67x00_fill_frame(c67x00);
if (!list_empty(&c67x00->td_list))
/* TD's have been added to the frame */
c67x00_send_frame(c67x00);
out:
spin_unlock(&c67x00->lock);
}
/* -------------------------------------------------------------------------- */
static void c67x00_sched_tasklet(unsigned long __c67x00)
{
struct c67x00_hcd *c67x00 = (struct c67x00_hcd *)__c67x00;
c67x00_do_work(c67x00);
}
void c67x00_sched_kick(struct c67x00_hcd *c67x00)
{
tasklet_hi_schedule(&c67x00->tasklet);
}
int c67x00_sched_start_scheduler(struct c67x00_hcd *c67x00)
{
tasklet_init(&c67x00->tasklet, c67x00_sched_tasklet,
(unsigned long)c67x00);
return 0;
}
void c67x00_sched_stop_scheduler(struct c67x00_hcd *c67x00)
{
tasklet_kill(&c67x00->tasklet);
}
| gpl-2.0 |
fhasovic/LG-G2-D802-Kernel | drivers/net/can/sja1000/kvaser_pci.c | 9045 | 10436 | /*
* Copyright (C) 2008 Per Dalen <per.dalen@cnw.se>
*
* Parts of this software are based on (derived) the following:
*
* - Kvaser linux driver, version 4.72 BETA
* Copyright (C) 2002-2007 KVASER AB
*
* - Lincan driver, version 0.3.3, OCERA project
* Copyright (C) 2004 Pavel Pisa
* Copyright (C) 2001 Arnaud Westenberg
*
* - Socketcan SJA1000 drivers
* Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
* Copyright (c) 2002-2007 Volkswagen Group Electronic Research
* Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
* 38106 Braunschweig, GERMANY
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the version 2 of the GNU General Public License
* as published by the Free Software Foundation
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/can/dev.h>
#include <linux/io.h>
#include "sja1000.h"
#define DRV_NAME "kvaser_pci"
MODULE_AUTHOR("Per Dalen <per.dalen@cnw.se>");
MODULE_DESCRIPTION("Socket-CAN driver for KVASER PCAN PCI cards");
MODULE_SUPPORTED_DEVICE("KVASER PCAN PCI CAN card");
MODULE_LICENSE("GPL v2");
#define MAX_NO_OF_CHANNELS 4 /* max no of channels on a single card */
struct kvaser_pci {
int channel;
struct pci_dev *pci_dev;
struct net_device *slave_dev[MAX_NO_OF_CHANNELS-1];
void __iomem *conf_addr;
void __iomem *res_addr;
int no_channels;
u8 xilinx_ver;
};
#define KVASER_PCI_CAN_CLOCK (16000000 / 2)
/*
* The board configuration is probably following:
* RX1 is connected to ground.
* TX1 is not connected.
* CLKO is not connected.
* Setting the OCR register to 0xDA is a good idea.
* This means normal output mode , push-pull and the correct polarity.
*/
#define KVASER_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
/*
* In the CDR register, you should set CBP to 1.
* You will probably also want to set the clock divider value to 0
* (meaning divide-by-2), the Pelican bit, and the clock-off bit
* (you will have no need for CLKOUT anyway).
*/
#define KVASER_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
/*
* These register values are valid for revision 14 of the Xilinx logic.
*/
#define XILINX_VERINT 7 /* Lower nibble simulate interrupts,
high nibble version number. */
#define XILINX_PRESUMED_VERSION 14
/*
* Important S5920 registers
*/
#define S5920_INTCSR 0x38
#define S5920_PTCR 0x60
#define INTCSR_ADDON_INTENABLE_M 0x2000
#define KVASER_PCI_PORT_BYTES 0x20
#define PCI_CONFIG_PORT_SIZE 0x80 /* size of the config io-memory */
#define PCI_PORT_SIZE 0x80 /* size of a channel io-memory */
#define PCI_PORT_XILINX_SIZE 0x08 /* size of a xilinx io-memory */
#define KVASER_PCI_VENDOR_ID1 0x10e8 /* the PCI device and vendor IDs */
#define KVASER_PCI_DEVICE_ID1 0x8406
#define KVASER_PCI_VENDOR_ID2 0x1a07 /* the PCI device and vendor IDs */
#define KVASER_PCI_DEVICE_ID2 0x0008
static DEFINE_PCI_DEVICE_TABLE(kvaser_pci_tbl) = {
{KVASER_PCI_VENDOR_ID1, KVASER_PCI_DEVICE_ID1, PCI_ANY_ID, PCI_ANY_ID,},
{KVASER_PCI_VENDOR_ID2, KVASER_PCI_DEVICE_ID2, PCI_ANY_ID, PCI_ANY_ID,},
{ 0,}
};
MODULE_DEVICE_TABLE(pci, kvaser_pci_tbl);
static u8 kvaser_pci_read_reg(const struct sja1000_priv *priv, int port)
{
return ioread8(priv->reg_base + port);
}
static void kvaser_pci_write_reg(const struct sja1000_priv *priv,
int port, u8 val)
{
iowrite8(val, priv->reg_base + port);
}
static void kvaser_pci_disable_irq(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct kvaser_pci *board = priv->priv;
u32 intcsr;
/* Disable interrupts from card */
intcsr = ioread32(board->conf_addr + S5920_INTCSR);
intcsr &= ~INTCSR_ADDON_INTENABLE_M;
iowrite32(intcsr, board->conf_addr + S5920_INTCSR);
}
static void kvaser_pci_enable_irq(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct kvaser_pci *board = priv->priv;
u32 tmp_en_io;
/* Enable interrupts from card */
tmp_en_io = ioread32(board->conf_addr + S5920_INTCSR);
tmp_en_io |= INTCSR_ADDON_INTENABLE_M;
iowrite32(tmp_en_io, board->conf_addr + S5920_INTCSR);
}
static int number_of_sja1000_chip(void __iomem *base_addr)
{
u8 status;
int i;
for (i = 0; i < MAX_NO_OF_CHANNELS; i++) {
/* reset chip */
iowrite8(MOD_RM, base_addr +
(i * KVASER_PCI_PORT_BYTES) + REG_MOD);
status = ioread8(base_addr +
(i * KVASER_PCI_PORT_BYTES) + REG_MOD);
/* check reset bit */
if (!(status & MOD_RM))
break;
}
return i;
}
static void kvaser_pci_del_chan(struct net_device *dev)
{
struct sja1000_priv *priv;
struct kvaser_pci *board;
int i;
if (!dev)
return;
priv = netdev_priv(dev);
board = priv->priv;
if (!board)
return;
dev_info(&board->pci_dev->dev, "Removing device %s\n",
dev->name);
/* Disable PCI interrupts */
kvaser_pci_disable_irq(dev);
for (i = 0; i < board->no_channels - 1; i++) {
if (board->slave_dev[i]) {
dev_info(&board->pci_dev->dev, "Removing device %s\n",
board->slave_dev[i]->name);
unregister_sja1000dev(board->slave_dev[i]);
free_sja1000dev(board->slave_dev[i]);
}
}
unregister_sja1000dev(dev);
pci_iounmap(board->pci_dev, priv->reg_base);
pci_iounmap(board->pci_dev, board->conf_addr);
pci_iounmap(board->pci_dev, board->res_addr);
free_sja1000dev(dev);
}
static int kvaser_pci_add_chan(struct pci_dev *pdev, int channel,
struct net_device **master_dev,
void __iomem *conf_addr,
void __iomem *res_addr,
void __iomem *base_addr)
{
struct net_device *dev;
struct sja1000_priv *priv;
struct kvaser_pci *board;
int err, init_step;
dev = alloc_sja1000dev(sizeof(struct kvaser_pci));
if (dev == NULL)
return -ENOMEM;
priv = netdev_priv(dev);
board = priv->priv;
board->pci_dev = pdev;
board->channel = channel;
/* S5920 */
board->conf_addr = conf_addr;
/* XILINX board wide address */
board->res_addr = res_addr;
if (channel == 0) {
board->xilinx_ver =
ioread8(board->res_addr + XILINX_VERINT) >> 4;
init_step = 2;
/* Assert PTADR# - we're in passive mode so the other bits are
not important */
iowrite32(0x80808080UL, board->conf_addr + S5920_PTCR);
/* Enable interrupts from card */
kvaser_pci_enable_irq(dev);
} else {
struct sja1000_priv *master_priv = netdev_priv(*master_dev);
struct kvaser_pci *master_board = master_priv->priv;
master_board->slave_dev[channel - 1] = dev;
master_board->no_channels = channel + 1;
board->xilinx_ver = master_board->xilinx_ver;
}
priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES;
priv->read_reg = kvaser_pci_read_reg;
priv->write_reg = kvaser_pci_write_reg;
priv->can.clock.freq = KVASER_PCI_CAN_CLOCK;
priv->ocr = KVASER_PCI_OCR;
priv->cdr = KVASER_PCI_CDR;
priv->irq_flags = IRQF_SHARED;
dev->irq = pdev->irq;
init_step = 4;
dev_info(&pdev->dev, "reg_base=%p conf_addr=%p irq=%d\n",
priv->reg_base, board->conf_addr, dev->irq);
SET_NETDEV_DEV(dev, &pdev->dev);
/* Register SJA1000 device */
err = register_sja1000dev(dev);
if (err) {
dev_err(&pdev->dev, "Registering device failed (err=%d)\n",
err);
goto failure;
}
if (channel == 0)
*master_dev = dev;
return 0;
failure:
kvaser_pci_del_chan(dev);
return err;
}
static int __devinit kvaser_pci_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int err;
struct net_device *master_dev = NULL;
struct sja1000_priv *priv;
struct kvaser_pci *board;
int no_channels;
void __iomem *base_addr = NULL;
void __iomem *conf_addr = NULL;
void __iomem *res_addr = NULL;
int i;
dev_info(&pdev->dev, "initializing device %04x:%04x\n",
pdev->vendor, pdev->device);
err = pci_enable_device(pdev);
if (err)
goto failure;
err = pci_request_regions(pdev, DRV_NAME);
if (err)
goto failure_release_pci;
/* S5920 */
conf_addr = pci_iomap(pdev, 0, PCI_CONFIG_PORT_SIZE);
if (conf_addr == NULL) {
err = -ENODEV;
goto failure_release_regions;
}
/* XILINX board wide address */
res_addr = pci_iomap(pdev, 2, PCI_PORT_XILINX_SIZE);
if (res_addr == NULL) {
err = -ENOMEM;
goto failure_iounmap;
}
base_addr = pci_iomap(pdev, 1, PCI_PORT_SIZE);
if (base_addr == NULL) {
err = -ENOMEM;
goto failure_iounmap;
}
no_channels = number_of_sja1000_chip(base_addr);
if (no_channels == 0) {
err = -ENOMEM;
goto failure_iounmap;
}
for (i = 0; i < no_channels; i++) {
err = kvaser_pci_add_chan(pdev, i, &master_dev,
conf_addr, res_addr,
base_addr);
if (err)
goto failure_cleanup;
}
priv = netdev_priv(master_dev);
board = priv->priv;
dev_info(&pdev->dev, "xilinx version=%d number of channels=%d\n",
board->xilinx_ver, board->no_channels);
pci_set_drvdata(pdev, master_dev);
return 0;
failure_cleanup:
kvaser_pci_del_chan(master_dev);
failure_iounmap:
if (conf_addr != NULL)
pci_iounmap(pdev, conf_addr);
if (res_addr != NULL)
pci_iounmap(pdev, res_addr);
if (base_addr != NULL)
pci_iounmap(pdev, base_addr);
failure_release_regions:
pci_release_regions(pdev);
failure_release_pci:
pci_disable_device(pdev);
failure:
return err;
}
static void __devexit kvaser_pci_remove_one(struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
kvaser_pci_del_chan(dev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
static struct pci_driver kvaser_pci_driver = {
.name = DRV_NAME,
.id_table = kvaser_pci_tbl,
.probe = kvaser_pci_init_one,
.remove = __devexit_p(kvaser_pci_remove_one),
};
static int __init kvaser_pci_init(void)
{
return pci_register_driver(&kvaser_pci_driver);
}
static void __exit kvaser_pci_exit(void)
{
pci_unregister_driver(&kvaser_pci_driver);
}
module_init(kvaser_pci_init);
module_exit(kvaser_pci_exit);
| gpl-2.0 |
geeknik/StupidFast | drivers/net/can/sja1000/kvaser_pci.c | 9045 | 10436 | /*
* Copyright (C) 2008 Per Dalen <per.dalen@cnw.se>
*
* Parts of this software are based on (derived) the following:
*
* - Kvaser linux driver, version 4.72 BETA
* Copyright (C) 2002-2007 KVASER AB
*
* - Lincan driver, version 0.3.3, OCERA project
* Copyright (C) 2004 Pavel Pisa
* Copyright (C) 2001 Arnaud Westenberg
*
* - Socketcan SJA1000 drivers
* Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
* Copyright (c) 2002-2007 Volkswagen Group Electronic Research
* Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
* 38106 Braunschweig, GERMANY
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the version 2 of the GNU General Public License
* as published by the Free Software Foundation
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/can/dev.h>
#include <linux/io.h>
#include "sja1000.h"
#define DRV_NAME "kvaser_pci"
MODULE_AUTHOR("Per Dalen <per.dalen@cnw.se>");
MODULE_DESCRIPTION("Socket-CAN driver for KVASER PCAN PCI cards");
MODULE_SUPPORTED_DEVICE("KVASER PCAN PCI CAN card");
MODULE_LICENSE("GPL v2");
#define MAX_NO_OF_CHANNELS 4 /* max no of channels on a single card */
struct kvaser_pci {
int channel;
struct pci_dev *pci_dev;
struct net_device *slave_dev[MAX_NO_OF_CHANNELS-1];
void __iomem *conf_addr;
void __iomem *res_addr;
int no_channels;
u8 xilinx_ver;
};
#define KVASER_PCI_CAN_CLOCK (16000000 / 2)
/*
* The board configuration is probably following:
* RX1 is connected to ground.
* TX1 is not connected.
* CLKO is not connected.
* Setting the OCR register to 0xDA is a good idea.
* This means normal output mode , push-pull and the correct polarity.
*/
#define KVASER_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
/*
* In the CDR register, you should set CBP to 1.
* You will probably also want to set the clock divider value to 0
* (meaning divide-by-2), the Pelican bit, and the clock-off bit
* (you will have no need for CLKOUT anyway).
*/
#define KVASER_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
/*
* These register values are valid for revision 14 of the Xilinx logic.
*/
#define XILINX_VERINT 7 /* Lower nibble simulate interrupts,
high nibble version number. */
#define XILINX_PRESUMED_VERSION 14
/*
* Important S5920 registers
*/
#define S5920_INTCSR 0x38
#define S5920_PTCR 0x60
#define INTCSR_ADDON_INTENABLE_M 0x2000
#define KVASER_PCI_PORT_BYTES 0x20
#define PCI_CONFIG_PORT_SIZE 0x80 /* size of the config io-memory */
#define PCI_PORT_SIZE 0x80 /* size of a channel io-memory */
#define PCI_PORT_XILINX_SIZE 0x08 /* size of a xilinx io-memory */
#define KVASER_PCI_VENDOR_ID1 0x10e8 /* the PCI device and vendor IDs */
#define KVASER_PCI_DEVICE_ID1 0x8406
#define KVASER_PCI_VENDOR_ID2 0x1a07 /* the PCI device and vendor IDs */
#define KVASER_PCI_DEVICE_ID2 0x0008
static DEFINE_PCI_DEVICE_TABLE(kvaser_pci_tbl) = {
{KVASER_PCI_VENDOR_ID1, KVASER_PCI_DEVICE_ID1, PCI_ANY_ID, PCI_ANY_ID,},
{KVASER_PCI_VENDOR_ID2, KVASER_PCI_DEVICE_ID2, PCI_ANY_ID, PCI_ANY_ID,},
{ 0,}
};
MODULE_DEVICE_TABLE(pci, kvaser_pci_tbl);
static u8 kvaser_pci_read_reg(const struct sja1000_priv *priv, int port)
{
return ioread8(priv->reg_base + port);
}
static void kvaser_pci_write_reg(const struct sja1000_priv *priv,
int port, u8 val)
{
iowrite8(val, priv->reg_base + port);
}
static void kvaser_pci_disable_irq(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct kvaser_pci *board = priv->priv;
u32 intcsr;
/* Disable interrupts from card */
intcsr = ioread32(board->conf_addr + S5920_INTCSR);
intcsr &= ~INTCSR_ADDON_INTENABLE_M;
iowrite32(intcsr, board->conf_addr + S5920_INTCSR);
}
static void kvaser_pci_enable_irq(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct kvaser_pci *board = priv->priv;
u32 tmp_en_io;
/* Enable interrupts from card */
tmp_en_io = ioread32(board->conf_addr + S5920_INTCSR);
tmp_en_io |= INTCSR_ADDON_INTENABLE_M;
iowrite32(tmp_en_io, board->conf_addr + S5920_INTCSR);
}
static int number_of_sja1000_chip(void __iomem *base_addr)
{
u8 status;
int i;
for (i = 0; i < MAX_NO_OF_CHANNELS; i++) {
/* reset chip */
iowrite8(MOD_RM, base_addr +
(i * KVASER_PCI_PORT_BYTES) + REG_MOD);
status = ioread8(base_addr +
(i * KVASER_PCI_PORT_BYTES) + REG_MOD);
/* check reset bit */
if (!(status & MOD_RM))
break;
}
return i;
}
static void kvaser_pci_del_chan(struct net_device *dev)
{
struct sja1000_priv *priv;
struct kvaser_pci *board;
int i;
if (!dev)
return;
priv = netdev_priv(dev);
board = priv->priv;
if (!board)
return;
dev_info(&board->pci_dev->dev, "Removing device %s\n",
dev->name);
/* Disable PCI interrupts */
kvaser_pci_disable_irq(dev);
for (i = 0; i < board->no_channels - 1; i++) {
if (board->slave_dev[i]) {
dev_info(&board->pci_dev->dev, "Removing device %s\n",
board->slave_dev[i]->name);
unregister_sja1000dev(board->slave_dev[i]);
free_sja1000dev(board->slave_dev[i]);
}
}
unregister_sja1000dev(dev);
pci_iounmap(board->pci_dev, priv->reg_base);
pci_iounmap(board->pci_dev, board->conf_addr);
pci_iounmap(board->pci_dev, board->res_addr);
free_sja1000dev(dev);
}
static int kvaser_pci_add_chan(struct pci_dev *pdev, int channel,
struct net_device **master_dev,
void __iomem *conf_addr,
void __iomem *res_addr,
void __iomem *base_addr)
{
struct net_device *dev;
struct sja1000_priv *priv;
struct kvaser_pci *board;
int err, init_step;
dev = alloc_sja1000dev(sizeof(struct kvaser_pci));
if (dev == NULL)
return -ENOMEM;
priv = netdev_priv(dev);
board = priv->priv;
board->pci_dev = pdev;
board->channel = channel;
/* S5920 */
board->conf_addr = conf_addr;
/* XILINX board wide address */
board->res_addr = res_addr;
if (channel == 0) {
board->xilinx_ver =
ioread8(board->res_addr + XILINX_VERINT) >> 4;
init_step = 2;
/* Assert PTADR# - we're in passive mode so the other bits are
not important */
iowrite32(0x80808080UL, board->conf_addr + S5920_PTCR);
/* Enable interrupts from card */
kvaser_pci_enable_irq(dev);
} else {
struct sja1000_priv *master_priv = netdev_priv(*master_dev);
struct kvaser_pci *master_board = master_priv->priv;
master_board->slave_dev[channel - 1] = dev;
master_board->no_channels = channel + 1;
board->xilinx_ver = master_board->xilinx_ver;
}
priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES;
priv->read_reg = kvaser_pci_read_reg;
priv->write_reg = kvaser_pci_write_reg;
priv->can.clock.freq = KVASER_PCI_CAN_CLOCK;
priv->ocr = KVASER_PCI_OCR;
priv->cdr = KVASER_PCI_CDR;
priv->irq_flags = IRQF_SHARED;
dev->irq = pdev->irq;
init_step = 4;
dev_info(&pdev->dev, "reg_base=%p conf_addr=%p irq=%d\n",
priv->reg_base, board->conf_addr, dev->irq);
SET_NETDEV_DEV(dev, &pdev->dev);
/* Register SJA1000 device */
err = register_sja1000dev(dev);
if (err) {
dev_err(&pdev->dev, "Registering device failed (err=%d)\n",
err);
goto failure;
}
if (channel == 0)
*master_dev = dev;
return 0;
failure:
kvaser_pci_del_chan(dev);
return err;
}
static int __devinit kvaser_pci_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int err;
struct net_device *master_dev = NULL;
struct sja1000_priv *priv;
struct kvaser_pci *board;
int no_channels;
void __iomem *base_addr = NULL;
void __iomem *conf_addr = NULL;
void __iomem *res_addr = NULL;
int i;
dev_info(&pdev->dev, "initializing device %04x:%04x\n",
pdev->vendor, pdev->device);
err = pci_enable_device(pdev);
if (err)
goto failure;
err = pci_request_regions(pdev, DRV_NAME);
if (err)
goto failure_release_pci;
/* S5920 */
conf_addr = pci_iomap(pdev, 0, PCI_CONFIG_PORT_SIZE);
if (conf_addr == NULL) {
err = -ENODEV;
goto failure_release_regions;
}
/* XILINX board wide address */
res_addr = pci_iomap(pdev, 2, PCI_PORT_XILINX_SIZE);
if (res_addr == NULL) {
err = -ENOMEM;
goto failure_iounmap;
}
base_addr = pci_iomap(pdev, 1, PCI_PORT_SIZE);
if (base_addr == NULL) {
err = -ENOMEM;
goto failure_iounmap;
}
no_channels = number_of_sja1000_chip(base_addr);
if (no_channels == 0) {
err = -ENOMEM;
goto failure_iounmap;
}
for (i = 0; i < no_channels; i++) {
err = kvaser_pci_add_chan(pdev, i, &master_dev,
conf_addr, res_addr,
base_addr);
if (err)
goto failure_cleanup;
}
priv = netdev_priv(master_dev);
board = priv->priv;
dev_info(&pdev->dev, "xilinx version=%d number of channels=%d\n",
board->xilinx_ver, board->no_channels);
pci_set_drvdata(pdev, master_dev);
return 0;
failure_cleanup:
kvaser_pci_del_chan(master_dev);
failure_iounmap:
if (conf_addr != NULL)
pci_iounmap(pdev, conf_addr);
if (res_addr != NULL)
pci_iounmap(pdev, res_addr);
if (base_addr != NULL)
pci_iounmap(pdev, base_addr);
failure_release_regions:
pci_release_regions(pdev);
failure_release_pci:
pci_disable_device(pdev);
failure:
return err;
}
static void __devexit kvaser_pci_remove_one(struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
kvaser_pci_del_chan(dev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
static struct pci_driver kvaser_pci_driver = {
.name = DRV_NAME,
.id_table = kvaser_pci_tbl,
.probe = kvaser_pci_init_one,
.remove = __devexit_p(kvaser_pci_remove_one),
};
static int __init kvaser_pci_init(void)
{
return pci_register_driver(&kvaser_pci_driver);
}
static void __exit kvaser_pci_exit(void)
{
pci_unregister_driver(&kvaser_pci_driver);
}
module_init(kvaser_pci_init);
module_exit(kvaser_pci_exit);
| gpl-2.0 |
Negamann303/kernel-ng2-negalite | drivers/isdn/gigaset/asyncdata.c | 9557 | 17022 | /*
* Common data handling layer for ser_gigaset and usb_gigaset
*
* Copyright (c) 2005 by Tilman Schmidt <tilman@imap.cc>,
* Hansjoerg Lipp <hjlipp@web.de>,
* Stefan Eilers.
*
* =====================================================================
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* =====================================================================
*/
#include "gigaset.h"
#include <linux/crc-ccitt.h>
#include <linux/bitrev.h>
#include <linux/export.h>
/* check if byte must be stuffed/escaped
* I'm not sure which data should be encoded.
* Therefore I will go the hard way and encode every value
* less than 0x20, the flag sequence and the control escape char.
*/
static inline int muststuff(unsigned char c)
{
if (c < PPP_TRANS) return 1;
if (c == PPP_FLAG) return 1;
if (c == PPP_ESCAPE) return 1;
/* other possible candidates: */
/* 0x91: XON with parity set */
/* 0x93: XOFF with parity set */
return 0;
}
/* == data input =========================================================== */
/* process a block of received bytes in command mode
* (mstate != MS_LOCKED && (inputstate & INS_command))
* Append received bytes to the command response buffer and forward them
* line by line to the response handler. Exit whenever a mode/state change
* might have occurred.
* Note: Received lines may be terminated by CR, LF, or CR LF, which will be
* removed before passing the line to the response handler.
* Return value:
* number of processed bytes
*/
static unsigned cmd_loop(unsigned numbytes, struct inbuf_t *inbuf)
{
unsigned char *src = inbuf->data + inbuf->head;
struct cardstate *cs = inbuf->cs;
unsigned cbytes = cs->cbytes;
unsigned procbytes = 0;
unsigned char c;
while (procbytes < numbytes) {
c = *src++;
procbytes++;
switch (c) {
case '\n':
if (cbytes == 0 && cs->respdata[0] == '\r') {
/* collapse LF with preceding CR */
cs->respdata[0] = 0;
break;
}
/* --v-- fall through --v-- */
case '\r':
/* end of message line, pass to response handler */
if (cbytes >= MAX_RESP_SIZE) {
dev_warn(cs->dev, "response too large (%d)\n",
cbytes);
cbytes = MAX_RESP_SIZE;
}
cs->cbytes = cbytes;
gigaset_dbg_buffer(DEBUG_TRANSCMD, "received response",
cbytes, cs->respdata);
gigaset_handle_modem_response(cs);
cbytes = 0;
/* store EOL byte for CRLF collapsing */
cs->respdata[0] = c;
/* cs->dle may have changed */
if (cs->dle && !(inbuf->inputstate & INS_DLE_command))
inbuf->inputstate &= ~INS_command;
/* return for reevaluating state */
goto exit;
case DLE_FLAG:
if (inbuf->inputstate & INS_DLE_char) {
/* quoted DLE: clear quote flag */
inbuf->inputstate &= ~INS_DLE_char;
} else if (cs->dle ||
(inbuf->inputstate & INS_DLE_command)) {
/* DLE escape, pass up for handling */
inbuf->inputstate |= INS_DLE_char;
goto exit;
}
/* quoted or not in DLE mode: treat as regular data */
/* --v-- fall through --v-- */
default:
/* append to line buffer if possible */
if (cbytes < MAX_RESP_SIZE)
cs->respdata[cbytes] = c;
cbytes++;
}
}
exit:
cs->cbytes = cbytes;
return procbytes;
}
/* process a block of received bytes in lock mode
* All received bytes are passed unmodified to the tty i/f.
* Return value:
* number of processed bytes
*/
static unsigned lock_loop(unsigned numbytes, struct inbuf_t *inbuf)
{
unsigned char *src = inbuf->data + inbuf->head;
gigaset_dbg_buffer(DEBUG_LOCKCMD, "received response", numbytes, src);
gigaset_if_receive(inbuf->cs, src, numbytes);
return numbytes;
}
/* process a block of received bytes in HDLC data mode
* (mstate != MS_LOCKED && !(inputstate & INS_command) && proto2 == L2_HDLC)
* Collect HDLC frames, undoing byte stuffing and watching for DLE escapes.
* When a frame is complete, check the FCS and pass valid frames to the LL.
* If DLE is encountered, return immediately to let the caller handle it.
* Return value:
* number of processed bytes
*/
static unsigned hdlc_loop(unsigned numbytes, struct inbuf_t *inbuf)
{
struct cardstate *cs = inbuf->cs;
struct bc_state *bcs = cs->bcs;
int inputstate = bcs->inputstate;
__u16 fcs = bcs->rx_fcs;
struct sk_buff *skb = bcs->rx_skb;
unsigned char *src = inbuf->data + inbuf->head;
unsigned procbytes = 0;
unsigned char c;
if (inputstate & INS_byte_stuff) {
if (!numbytes)
return 0;
inputstate &= ~INS_byte_stuff;
goto byte_stuff;
}
while (procbytes < numbytes) {
c = *src++;
procbytes++;
if (c == DLE_FLAG) {
if (inputstate & INS_DLE_char) {
/* quoted DLE: clear quote flag */
inputstate &= ~INS_DLE_char;
} else if (cs->dle || (inputstate & INS_DLE_command)) {
/* DLE escape, pass up for handling */
inputstate |= INS_DLE_char;
break;
}
}
if (c == PPP_ESCAPE) {
/* byte stuffing indicator: pull in next byte */
if (procbytes >= numbytes) {
/* end of buffer, save for later processing */
inputstate |= INS_byte_stuff;
break;
}
byte_stuff:
c = *src++;
procbytes++;
if (c == DLE_FLAG) {
if (inputstate & INS_DLE_char) {
/* quoted DLE: clear quote flag */
inputstate &= ~INS_DLE_char;
} else if (cs->dle ||
(inputstate & INS_DLE_command)) {
/* DLE escape, pass up for handling */
inputstate |=
INS_DLE_char | INS_byte_stuff;
break;
}
}
c ^= PPP_TRANS;
#ifdef CONFIG_GIGASET_DEBUG
if (!muststuff(c))
gig_dbg(DEBUG_HDLC, "byte stuffed: 0x%02x", c);
#endif
} else if (c == PPP_FLAG) {
/* end of frame: process content if any */
if (inputstate & INS_have_data) {
gig_dbg(DEBUG_HDLC,
"7e----------------------------");
/* check and pass received frame */
if (!skb) {
/* skipped frame */
gigaset_isdn_rcv_err(bcs);
} else if (skb->len < 2) {
/* frame too short for FCS */
dev_warn(cs->dev,
"short frame (%d)\n",
skb->len);
gigaset_isdn_rcv_err(bcs);
dev_kfree_skb_any(skb);
} else if (fcs != PPP_GOODFCS) {
/* frame check error */
dev_err(cs->dev,
"Checksum failed, %u bytes corrupted!\n",
skb->len);
gigaset_isdn_rcv_err(bcs);
dev_kfree_skb_any(skb);
} else {
/* good frame */
__skb_trim(skb, skb->len - 2);
gigaset_skb_rcvd(bcs, skb);
}
/* prepare reception of next frame */
inputstate &= ~INS_have_data;
skb = gigaset_new_rx_skb(bcs);
} else {
/* empty frame (7E 7E) */
#ifdef CONFIG_GIGASET_DEBUG
++bcs->emptycount;
#endif
if (!skb) {
/* skipped (?) */
gigaset_isdn_rcv_err(bcs);
skb = gigaset_new_rx_skb(bcs);
}
}
fcs = PPP_INITFCS;
continue;
#ifdef CONFIG_GIGASET_DEBUG
} else if (muststuff(c)) {
/* Should not happen. Possible after ZDLE=1<CR><LF>. */
gig_dbg(DEBUG_HDLC, "not byte stuffed: 0x%02x", c);
#endif
}
/* regular data byte, append to skb */
#ifdef CONFIG_GIGASET_DEBUG
if (!(inputstate & INS_have_data)) {
gig_dbg(DEBUG_HDLC, "7e (%d x) ================",
bcs->emptycount);
bcs->emptycount = 0;
}
#endif
inputstate |= INS_have_data;
if (skb) {
if (skb->len >= bcs->rx_bufsize) {
dev_warn(cs->dev, "received packet too long\n");
dev_kfree_skb_any(skb);
/* skip remainder of packet */
bcs->rx_skb = skb = NULL;
} else {
*__skb_put(skb, 1) = c;
fcs = crc_ccitt_byte(fcs, c);
}
}
}
bcs->inputstate = inputstate;
bcs->rx_fcs = fcs;
return procbytes;
}
/* process a block of received bytes in transparent data mode
* (mstate != MS_LOCKED && !(inputstate & INS_command) && proto2 != L2_HDLC)
* Invert bytes, undoing byte stuffing and watching for DLE escapes.
* If DLE is encountered, return immediately to let the caller handle it.
* Return value:
* number of processed bytes
*/
static unsigned iraw_loop(unsigned numbytes, struct inbuf_t *inbuf)
{
struct cardstate *cs = inbuf->cs;
struct bc_state *bcs = cs->bcs;
int inputstate = bcs->inputstate;
struct sk_buff *skb = bcs->rx_skb;
unsigned char *src = inbuf->data + inbuf->head;
unsigned procbytes = 0;
unsigned char c;
if (!skb) {
/* skip this block */
gigaset_new_rx_skb(bcs);
return numbytes;
}
while (procbytes < numbytes && skb->len < bcs->rx_bufsize) {
c = *src++;
procbytes++;
if (c == DLE_FLAG) {
if (inputstate & INS_DLE_char) {
/* quoted DLE: clear quote flag */
inputstate &= ~INS_DLE_char;
} else if (cs->dle || (inputstate & INS_DLE_command)) {
/* DLE escape, pass up for handling */
inputstate |= INS_DLE_char;
break;
}
}
/* regular data byte: append to current skb */
inputstate |= INS_have_data;
*__skb_put(skb, 1) = bitrev8(c);
}
/* pass data up */
if (inputstate & INS_have_data) {
gigaset_skb_rcvd(bcs, skb);
inputstate &= ~INS_have_data;
gigaset_new_rx_skb(bcs);
}
bcs->inputstate = inputstate;
return procbytes;
}
/* process DLE escapes
* Called whenever a DLE sequence might be encountered in the input stream.
* Either processes the entire DLE sequence or, if that isn't possible,
* notes the fact that an initial DLE has been received in the INS_DLE_char
* inputstate flag and resumes processing of the sequence on the next call.
*/
static void handle_dle(struct inbuf_t *inbuf)
{
struct cardstate *cs = inbuf->cs;
if (cs->mstate == MS_LOCKED)
return; /* no DLE processing in lock mode */
if (!(inbuf->inputstate & INS_DLE_char)) {
/* no DLE pending */
if (inbuf->data[inbuf->head] == DLE_FLAG &&
(cs->dle || inbuf->inputstate & INS_DLE_command)) {
/* start of DLE sequence */
inbuf->head++;
if (inbuf->head == inbuf->tail ||
inbuf->head == RBUFSIZE) {
/* end of buffer, save for later processing */
inbuf->inputstate |= INS_DLE_char;
return;
}
} else {
/* regular data byte */
return;
}
}
/* consume pending DLE */
inbuf->inputstate &= ~INS_DLE_char;
switch (inbuf->data[inbuf->head]) {
case 'X': /* begin of event message */
if (inbuf->inputstate & INS_command)
dev_notice(cs->dev,
"received <DLE>X in command mode\n");
inbuf->inputstate |= INS_command | INS_DLE_command;
inbuf->head++; /* byte consumed */
break;
case '.': /* end of event message */
if (!(inbuf->inputstate & INS_DLE_command))
dev_notice(cs->dev,
"received <DLE>. without <DLE>X\n");
inbuf->inputstate &= ~INS_DLE_command;
/* return to data mode if in DLE mode */
if (cs->dle)
inbuf->inputstate &= ~INS_command;
inbuf->head++; /* byte consumed */
break;
case DLE_FLAG: /* DLE in data stream */
/* mark as quoted */
inbuf->inputstate |= INS_DLE_char;
if (!(cs->dle || inbuf->inputstate & INS_DLE_command))
dev_notice(cs->dev,
"received <DLE><DLE> not in DLE mode\n");
break; /* quoted byte left in buffer */
default:
dev_notice(cs->dev, "received <DLE><%02x>\n",
inbuf->data[inbuf->head]);
/* quoted byte left in buffer */
}
}
/**
* gigaset_m10x_input() - process a block of data received from the device
* @inbuf: received data and device descriptor structure.
*
* Called by hardware module {ser,usb}_gigaset with a block of received
* bytes. Separates the bytes received over the serial data channel into
* user data and command replies (locked/unlocked) according to the
* current state of the interface.
*/
void gigaset_m10x_input(struct inbuf_t *inbuf)
{
struct cardstate *cs = inbuf->cs;
unsigned numbytes, procbytes;
gig_dbg(DEBUG_INTR, "buffer state: %u -> %u", inbuf->head, inbuf->tail);
while (inbuf->head != inbuf->tail) {
/* check for DLE escape */
handle_dle(inbuf);
/* process a contiguous block of bytes */
numbytes = (inbuf->head > inbuf->tail ?
RBUFSIZE : inbuf->tail) - inbuf->head;
gig_dbg(DEBUG_INTR, "processing %u bytes", numbytes);
/*
* numbytes may be 0 if handle_dle() ate the last byte.
* This does no harm, *_loop() will just return 0 immediately.
*/
if (cs->mstate == MS_LOCKED)
procbytes = lock_loop(numbytes, inbuf);
else if (inbuf->inputstate & INS_command)
procbytes = cmd_loop(numbytes, inbuf);
else if (cs->bcs->proto2 == L2_HDLC)
procbytes = hdlc_loop(numbytes, inbuf);
else
procbytes = iraw_loop(numbytes, inbuf);
inbuf->head += procbytes;
/* check for buffer wraparound */
if (inbuf->head >= RBUFSIZE)
inbuf->head = 0;
gig_dbg(DEBUG_INTR, "head set to %u", inbuf->head);
}
}
EXPORT_SYMBOL_GPL(gigaset_m10x_input);
/* == data output ========================================================== */
/*
* Encode a data packet into an octet stuffed HDLC frame with FCS,
* opening and closing flags, preserving headroom data.
* parameters:
* skb skb containing original packet (freed upon return)
* Return value:
* pointer to newly allocated skb containing the result frame
* and the original link layer header, NULL on error
*/
static struct sk_buff *HDLC_Encode(struct sk_buff *skb)
{
struct sk_buff *hdlc_skb;
__u16 fcs;
unsigned char c;
unsigned char *cp;
int len;
unsigned int stuf_cnt;
stuf_cnt = 0;
fcs = PPP_INITFCS;
cp = skb->data;
len = skb->len;
while (len--) {
if (muststuff(*cp))
stuf_cnt++;
fcs = crc_ccitt_byte(fcs, *cp++);
}
fcs ^= 0xffff; /* complement */
/* size of new buffer: original size + number of stuffing bytes
* + 2 bytes FCS + 2 stuffing bytes for FCS (if needed) + 2 flag bytes
* + room for link layer header
*/
hdlc_skb = dev_alloc_skb(skb->len + stuf_cnt + 6 + skb->mac_len);
if (!hdlc_skb) {
dev_kfree_skb_any(skb);
return NULL;
}
/* Copy link layer header into new skb */
skb_reset_mac_header(hdlc_skb);
skb_reserve(hdlc_skb, skb->mac_len);
memcpy(skb_mac_header(hdlc_skb), skb_mac_header(skb), skb->mac_len);
hdlc_skb->mac_len = skb->mac_len;
/* Add flag sequence in front of everything.. */
*(skb_put(hdlc_skb, 1)) = PPP_FLAG;
/* Perform byte stuffing while copying data. */
while (skb->len--) {
if (muststuff(*skb->data)) {
*(skb_put(hdlc_skb, 1)) = PPP_ESCAPE;
*(skb_put(hdlc_skb, 1)) = (*skb->data++) ^ PPP_TRANS;
} else
*(skb_put(hdlc_skb, 1)) = *skb->data++;
}
/* Finally add FCS (byte stuffed) and flag sequence */
c = (fcs & 0x00ff); /* least significant byte first */
if (muststuff(c)) {
*(skb_put(hdlc_skb, 1)) = PPP_ESCAPE;
c ^= PPP_TRANS;
}
*(skb_put(hdlc_skb, 1)) = c;
c = ((fcs >> 8) & 0x00ff);
if (muststuff(c)) {
*(skb_put(hdlc_skb, 1)) = PPP_ESCAPE;
c ^= PPP_TRANS;
}
*(skb_put(hdlc_skb, 1)) = c;
*(skb_put(hdlc_skb, 1)) = PPP_FLAG;
dev_kfree_skb_any(skb);
return hdlc_skb;
}
/*
* Encode a data packet into an octet stuffed raw bit inverted frame,
* preserving headroom data.
* parameters:
* skb skb containing original packet (freed upon return)
* Return value:
* pointer to newly allocated skb containing the result frame
* and the original link layer header, NULL on error
*/
static struct sk_buff *iraw_encode(struct sk_buff *skb)
{
struct sk_buff *iraw_skb;
unsigned char c;
unsigned char *cp;
int len;
/* size of new buffer (worst case = every byte must be stuffed):
* 2 * original size + room for link layer header
*/
iraw_skb = dev_alloc_skb(2 * skb->len + skb->mac_len);
if (!iraw_skb) {
dev_kfree_skb_any(skb);
return NULL;
}
/* copy link layer header into new skb */
skb_reset_mac_header(iraw_skb);
skb_reserve(iraw_skb, skb->mac_len);
memcpy(skb_mac_header(iraw_skb), skb_mac_header(skb), skb->mac_len);
iraw_skb->mac_len = skb->mac_len;
/* copy and stuff data */
cp = skb->data;
len = skb->len;
while (len--) {
c = bitrev8(*cp++);
if (c == DLE_FLAG)
*(skb_put(iraw_skb, 1)) = c;
*(skb_put(iraw_skb, 1)) = c;
}
dev_kfree_skb_any(skb);
return iraw_skb;
}
/**
* gigaset_m10x_send_skb() - queue an skb for sending
* @bcs: B channel descriptor structure.
* @skb: data to send.
*
* Called by LL to encode and queue an skb for sending, and start
* transmission if necessary.
* Once the payload data has been transmitted completely, gigaset_skb_sent()
* will be called with the skb's link layer header preserved.
*
* Return value:
* number of bytes accepted for sending (skb->len) if ok,
* error code < 0 (eg. -ENOMEM) on error
*/
int gigaset_m10x_send_skb(struct bc_state *bcs, struct sk_buff *skb)
{
struct cardstate *cs = bcs->cs;
unsigned len = skb->len;
unsigned long flags;
if (bcs->proto2 == L2_HDLC)
skb = HDLC_Encode(skb);
else
skb = iraw_encode(skb);
if (!skb) {
dev_err(cs->dev,
"unable to allocate memory for encoding!\n");
return -ENOMEM;
}
skb_queue_tail(&bcs->squeue, skb);
spin_lock_irqsave(&cs->lock, flags);
if (cs->connected)
tasklet_schedule(&cs->write_tasklet);
spin_unlock_irqrestore(&cs->lock, flags);
return len; /* ok so far */
}
EXPORT_SYMBOL_GPL(gigaset_m10x_send_skb);
| gpl-2.0 |
keily90/tf101-nv-linux | drivers/net/wireless/zd1211rw/zd_rf_uw2453.c | 10581 | 15773 | /* ZD1211 USB-WLAN driver for Linux
*
* Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
* Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include "zd_rf.h"
#include "zd_usb.h"
#include "zd_chip.h"
/* This RF programming code is based upon the code found in v2.16.0.0 of the
* ZyDAS vendor driver. Unlike other RF's, Ubec publish full technical specs
* for this RF on their website, so we're able to understand more than
* usual as to what is going on. Thumbs up for Ubec for doing that. */
/* The 3-wire serial interface provides access to 8 write-only registers.
* The data format is a 4 bit register address followed by a 20 bit value. */
#define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff))
/* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
* fractional divide ratio) and 3 (VCO config).
*
* We configure the RF to produce an interrupt when the PLL is locked onto
* the configured frequency. During initialization, we run through a variety
* of different VCO configurations on channel 1 until we detect a PLL lock.
* When this happens, we remember which VCO configuration produced the lock
* and use it later. Actually, we use the configuration *after* the one that
* produced the lock, which seems odd, but it works.
*
* If we do not see a PLL lock on any standard VCO config, we fall back on an
* autocal configuration, which has a fixed (as opposed to per-channel) VCO
* config and different synth values from the standard set (divide ratio
* is still shared with the standard set). */
/* The per-channel synth values for all standard VCO configurations. These get
* written to register 1. */
static const u8 uw2453_std_synth[] = {
RF_CHANNEL( 1) = 0x47,
RF_CHANNEL( 2) = 0x47,
RF_CHANNEL( 3) = 0x67,
RF_CHANNEL( 4) = 0x67,
RF_CHANNEL( 5) = 0x67,
RF_CHANNEL( 6) = 0x67,
RF_CHANNEL( 7) = 0x57,
RF_CHANNEL( 8) = 0x57,
RF_CHANNEL( 9) = 0x57,
RF_CHANNEL(10) = 0x57,
RF_CHANNEL(11) = 0x77,
RF_CHANNEL(12) = 0x77,
RF_CHANNEL(13) = 0x77,
RF_CHANNEL(14) = 0x4f,
};
/* This table stores the synthesizer fractional divide ratio for *all* VCO
* configurations (both standard and autocal). These get written to register 2.
*/
static const u16 uw2453_synth_divide[] = {
RF_CHANNEL( 1) = 0x999,
RF_CHANNEL( 2) = 0x99b,
RF_CHANNEL( 3) = 0x998,
RF_CHANNEL( 4) = 0x99a,
RF_CHANNEL( 5) = 0x999,
RF_CHANNEL( 6) = 0x99b,
RF_CHANNEL( 7) = 0x998,
RF_CHANNEL( 8) = 0x99a,
RF_CHANNEL( 9) = 0x999,
RF_CHANNEL(10) = 0x99b,
RF_CHANNEL(11) = 0x998,
RF_CHANNEL(12) = 0x99a,
RF_CHANNEL(13) = 0x999,
RF_CHANNEL(14) = 0xccc,
};
/* Here is the data for all the standard VCO configurations. We shrink our
* table a little by observing that both channels in a consecutive pair share
* the same value. We also observe that the high 4 bits ([0:3] in the specs)
* are all 'Reserved' and are always set to 0x4 - we chop them off in the data
* below. */
#define CHAN_TO_PAIRIDX(a) ((a - 1) / 2)
#define RF_CHANPAIR(a,b) [CHAN_TO_PAIRIDX(a)]
static const u16 uw2453_std_vco_cfg[][7] = {
{ /* table 1 */
RF_CHANPAIR( 1, 2) = 0x664d,
RF_CHANPAIR( 3, 4) = 0x604d,
RF_CHANPAIR( 5, 6) = 0x6675,
RF_CHANPAIR( 7, 8) = 0x6475,
RF_CHANPAIR( 9, 10) = 0x6655,
RF_CHANPAIR(11, 12) = 0x6455,
RF_CHANPAIR(13, 14) = 0x6665,
},
{ /* table 2 */
RF_CHANPAIR( 1, 2) = 0x666d,
RF_CHANPAIR( 3, 4) = 0x606d,
RF_CHANPAIR( 5, 6) = 0x664d,
RF_CHANPAIR( 7, 8) = 0x644d,
RF_CHANPAIR( 9, 10) = 0x6675,
RF_CHANPAIR(11, 12) = 0x6475,
RF_CHANPAIR(13, 14) = 0x6655,
},
{ /* table 3 */
RF_CHANPAIR( 1, 2) = 0x665d,
RF_CHANPAIR( 3, 4) = 0x605d,
RF_CHANPAIR( 5, 6) = 0x666d,
RF_CHANPAIR( 7, 8) = 0x646d,
RF_CHANPAIR( 9, 10) = 0x664d,
RF_CHANPAIR(11, 12) = 0x644d,
RF_CHANPAIR(13, 14) = 0x6675,
},
{ /* table 4 */
RF_CHANPAIR( 1, 2) = 0x667d,
RF_CHANPAIR( 3, 4) = 0x607d,
RF_CHANPAIR( 5, 6) = 0x665d,
RF_CHANPAIR( 7, 8) = 0x645d,
RF_CHANPAIR( 9, 10) = 0x666d,
RF_CHANPAIR(11, 12) = 0x646d,
RF_CHANPAIR(13, 14) = 0x664d,
},
{ /* table 5 */
RF_CHANPAIR( 1, 2) = 0x6643,
RF_CHANPAIR( 3, 4) = 0x6043,
RF_CHANPAIR( 5, 6) = 0x667d,
RF_CHANPAIR( 7, 8) = 0x647d,
RF_CHANPAIR( 9, 10) = 0x665d,
RF_CHANPAIR(11, 12) = 0x645d,
RF_CHANPAIR(13, 14) = 0x666d,
},
{ /* table 6 */
RF_CHANPAIR( 1, 2) = 0x6663,
RF_CHANPAIR( 3, 4) = 0x6063,
RF_CHANPAIR( 5, 6) = 0x6643,
RF_CHANPAIR( 7, 8) = 0x6443,
RF_CHANPAIR( 9, 10) = 0x667d,
RF_CHANPAIR(11, 12) = 0x647d,
RF_CHANPAIR(13, 14) = 0x665d,
},
{ /* table 7 */
RF_CHANPAIR( 1, 2) = 0x6653,
RF_CHANPAIR( 3, 4) = 0x6053,
RF_CHANPAIR( 5, 6) = 0x6663,
RF_CHANPAIR( 7, 8) = 0x6463,
RF_CHANPAIR( 9, 10) = 0x6643,
RF_CHANPAIR(11, 12) = 0x6443,
RF_CHANPAIR(13, 14) = 0x667d,
},
{ /* table 8 */
RF_CHANPAIR( 1, 2) = 0x6673,
RF_CHANPAIR( 3, 4) = 0x6073,
RF_CHANPAIR( 5, 6) = 0x6653,
RF_CHANPAIR( 7, 8) = 0x6453,
RF_CHANPAIR( 9, 10) = 0x6663,
RF_CHANPAIR(11, 12) = 0x6463,
RF_CHANPAIR(13, 14) = 0x6643,
},
{ /* table 9 */
RF_CHANPAIR( 1, 2) = 0x664b,
RF_CHANPAIR( 3, 4) = 0x604b,
RF_CHANPAIR( 5, 6) = 0x6673,
RF_CHANPAIR( 7, 8) = 0x6473,
RF_CHANPAIR( 9, 10) = 0x6653,
RF_CHANPAIR(11, 12) = 0x6453,
RF_CHANPAIR(13, 14) = 0x6663,
},
{ /* table 10 */
RF_CHANPAIR( 1, 2) = 0x666b,
RF_CHANPAIR( 3, 4) = 0x606b,
RF_CHANPAIR( 5, 6) = 0x664b,
RF_CHANPAIR( 7, 8) = 0x644b,
RF_CHANPAIR( 9, 10) = 0x6673,
RF_CHANPAIR(11, 12) = 0x6473,
RF_CHANPAIR(13, 14) = 0x6653,
},
{ /* table 11 */
RF_CHANPAIR( 1, 2) = 0x665b,
RF_CHANPAIR( 3, 4) = 0x605b,
RF_CHANPAIR( 5, 6) = 0x666b,
RF_CHANPAIR( 7, 8) = 0x646b,
RF_CHANPAIR( 9, 10) = 0x664b,
RF_CHANPAIR(11, 12) = 0x644b,
RF_CHANPAIR(13, 14) = 0x6673,
},
};
/* The per-channel synth values for autocal. These get written to register 1. */
static const u16 uw2453_autocal_synth[] = {
RF_CHANNEL( 1) = 0x6847,
RF_CHANNEL( 2) = 0x6847,
RF_CHANNEL( 3) = 0x6867,
RF_CHANNEL( 4) = 0x6867,
RF_CHANNEL( 5) = 0x6867,
RF_CHANNEL( 6) = 0x6867,
RF_CHANNEL( 7) = 0x6857,
RF_CHANNEL( 8) = 0x6857,
RF_CHANNEL( 9) = 0x6857,
RF_CHANNEL(10) = 0x6857,
RF_CHANNEL(11) = 0x6877,
RF_CHANNEL(12) = 0x6877,
RF_CHANNEL(13) = 0x6877,
RF_CHANNEL(14) = 0x684f,
};
/* The VCO configuration for autocal (all channels) */
static const u16 UW2453_AUTOCAL_VCO_CFG = 0x6662;
/* TX gain settings. The array index corresponds to the TX power integration
* values found in the EEPROM. The values get written to register 7. */
static u32 uw2453_txgain[] = {
[0x00] = 0x0e313,
[0x01] = 0x0fb13,
[0x02] = 0x0e093,
[0x03] = 0x0f893,
[0x04] = 0x0ea93,
[0x05] = 0x1f093,
[0x06] = 0x1f493,
[0x07] = 0x1f693,
[0x08] = 0x1f393,
[0x09] = 0x1f35b,
[0x0a] = 0x1e6db,
[0x0b] = 0x1ff3f,
[0x0c] = 0x1ffff,
[0x0d] = 0x361d7,
[0x0e] = 0x37fbf,
[0x0f] = 0x3ff8b,
[0x10] = 0x3ff33,
[0x11] = 0x3fb3f,
[0x12] = 0x3ffff,
};
/* RF-specific structure */
struct uw2453_priv {
/* index into synth/VCO config tables where PLL lock was found
* -1 means autocal */
int config;
};
#define UW2453_PRIV(rf) ((struct uw2453_priv *) (rf)->priv)
static int uw2453_synth_set_channel(struct zd_chip *chip, int channel,
bool autocal)
{
int r;
int idx = channel - 1;
u32 val;
if (autocal)
val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);
else
val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);
r = zd_rfwrite_locked(chip, val, RF_RV_BITS);
if (r)
return r;
return zd_rfwrite_locked(chip,
UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);
}
static int uw2453_write_vco_cfg(struct zd_chip *chip, u16 value)
{
/* vendor driver always sets these upper bits even though the specs say
* they are reserved */
u32 val = 0x40000 | value;
return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);
}
static int uw2453_init_mode(struct zd_chip *chip)
{
static const u32 rv[] = {
UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */
UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */
UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */
UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */
};
return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
}
static int uw2453_set_tx_gain_level(struct zd_chip *chip, int channel)
{
u8 int_value = chip->pwr_int_values[channel - 1];
if (int_value >= ARRAY_SIZE(uw2453_txgain)) {
dev_dbg_f(zd_chip_dev(chip), "can't configure TX gain for "
"int value %x on channel %d\n", int_value, channel);
return 0;
}
return zd_rfwrite_locked(chip,
UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);
}
static int uw2453_init_hw(struct zd_rf *rf)
{
int i, r;
int found_config = -1;
u16 intr_status;
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs[] = {
{ ZD_CR10, 0x89 }, { ZD_CR15, 0x20 },
{ ZD_CR17, 0x28 }, /* 6112 no change */
{ ZD_CR23, 0x38 }, { ZD_CR24, 0x20 }, { ZD_CR26, 0x93 },
{ ZD_CR27, 0x15 }, { ZD_CR28, 0x3e }, { ZD_CR29, 0x00 },
{ ZD_CR33, 0x28 }, { ZD_CR34, 0x30 },
{ ZD_CR35, 0x43 }, /* 6112 3e->43 */
{ ZD_CR41, 0x24 }, { ZD_CR44, 0x32 },
{ ZD_CR46, 0x92 }, /* 6112 96->92 */
{ ZD_CR47, 0x1e },
{ ZD_CR48, 0x04 }, /* 5602 Roger */
{ ZD_CR49, 0xfa }, { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 },
{ ZD_CR81, 0x30 }, { ZD_CR87, 0x0a }, { ZD_CR89, 0x04 },
{ ZD_CR91, 0x00 }, { ZD_CR92, 0x0a }, { ZD_CR98, 0x8d },
{ ZD_CR99, 0x28 }, { ZD_CR100, 0x02 },
{ ZD_CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */
{ ZD_CR102, 0x27 },
{ ZD_CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f
* 6221 1f->1c
*/
{ ZD_CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */
{ ZD_CR109, 0x13 },
{ ZD_CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */
{ ZD_CR111, 0x13 }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 },
{ ZD_CR114, 0x23 }, /* 6221 27->23 */
{ ZD_CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */
{ ZD_CR116, 0x24 }, /* 6220 1c->24 */
{ ZD_CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */
{ ZD_CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */
{ ZD_CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */
{ ZD_CR120, 0x4f },
{ ZD_CR121, 0x1f }, /* 6220 4f->1f */
{ ZD_CR122, 0xf0 }, { ZD_CR123, 0x57 }, { ZD_CR125, 0xad },
{ ZD_CR126, 0x6c }, { ZD_CR127, 0x03 },
{ ZD_CR128, 0x14 }, /* 6302 12->11 */
{ ZD_CR129, 0x12 }, /* 6301 10->0f */
{ ZD_CR130, 0x10 }, { ZD_CR137, 0x50 }, { ZD_CR138, 0xa8 },
{ ZD_CR144, 0xac }, { ZD_CR146, 0x20 }, { ZD_CR252, 0xff },
{ ZD_CR253, 0xff },
};
static const u32 rv[] = {
UW2453_REGWRITE(4, 0x2b), /* configure receiver gain */
UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */
UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */
UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */
/* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins,
* RSSI circuit powered down, reduced RSSI range */
UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */
/* synthesizer configuration for channel 1 */
UW2453_REGWRITE(1, 0x47),
UW2453_REGWRITE(2, 0x999),
/* disable manual VCO band selection */
UW2453_REGWRITE(3, 0x7602),
/* enable manual VCO band selection, configure current level */
UW2453_REGWRITE(3, 0x46063),
};
r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
if (r)
return r;
r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
if (r)
return r;
r = uw2453_init_mode(chip);
if (r)
return r;
/* Try all standard VCO configuration settings on channel 1 */
for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) {
/* Configure synthesizer for channel 1 */
r = uw2453_synth_set_channel(chip, 1, false);
if (r)
return r;
/* Write VCO config */
r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]);
if (r)
return r;
/* ack interrupt event */
r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG);
if (r)
return r;
/* check interrupt status */
r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG);
if (r)
return r;
if (!(intr_status & 0xf)) {
dev_dbg_f(zd_chip_dev(chip),
"PLL locked on configuration %d\n", i);
found_config = i;
break;
}
}
if (found_config == -1) {
/* autocal */
dev_dbg_f(zd_chip_dev(chip),
"PLL did not lock, using autocal\n");
r = uw2453_synth_set_channel(chip, 1, true);
if (r)
return r;
r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG);
if (r)
return r;
}
/* To match the vendor driver behaviour, we use the configuration after
* the one that produced a lock. */
UW2453_PRIV(rf)->config = found_config + 1;
return zd_iowrite16_locked(chip, 0x06, ZD_CR203);
}
static int uw2453_set_channel(struct zd_rf *rf, u8 channel)
{
int r;
u16 vco_cfg;
int config = UW2453_PRIV(rf)->config;
bool autocal = (config == -1);
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs[] = {
{ ZD_CR80, 0x30 }, { ZD_CR81, 0x30 }, { ZD_CR79, 0x58 },
{ ZD_CR12, 0xf0 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x58 },
};
r = uw2453_synth_set_channel(chip, channel, autocal);
if (r)
return r;
if (autocal)
vco_cfg = UW2453_AUTOCAL_VCO_CFG;
else
vco_cfg = uw2453_std_vco_cfg[config][CHAN_TO_PAIRIDX(channel)];
r = uw2453_write_vco_cfg(chip, vco_cfg);
if (r)
return r;
r = uw2453_init_mode(chip);
if (r)
return r;
r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
if (r)
return r;
r = uw2453_set_tx_gain_level(chip, channel);
if (r)
return r;
return zd_iowrite16_locked(chip, 0x06, ZD_CR203);
}
static int uw2453_switch_radio_on(struct zd_rf *rf)
{
int r;
struct zd_chip *chip = zd_rf_to_chip(rf);
struct zd_ioreq16 ioreqs[] = {
{ ZD_CR11, 0x00 }, { ZD_CR251, 0x3f },
};
/* enter RXTX mode */
r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);
if (r)
return r;
if (zd_chip_is_zd1211b(chip))
ioreqs[1].value = 0x7f;
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
}
static int uw2453_switch_radio_off(struct zd_rf *rf)
{
int r;
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs[] = {
{ ZD_CR11, 0x04 }, { ZD_CR251, 0x2f },
};
/* enter IDLE mode */
/* FIXME: shouldn't we go to SLEEP? sent email to zydas */
r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);
if (r)
return r;
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
}
static void uw2453_clear(struct zd_rf *rf)
{
kfree(rf->priv);
}
int zd_rf_init_uw2453(struct zd_rf *rf)
{
rf->init_hw = uw2453_init_hw;
rf->set_channel = uw2453_set_channel;
rf->switch_radio_on = uw2453_switch_radio_on;
rf->switch_radio_off = uw2453_switch_radio_off;
rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
rf->clear = uw2453_clear;
/* we have our own TX integration code */
rf->update_channel_int = 0;
rf->priv = kmalloc(sizeof(struct uw2453_priv), GFP_KERNEL);
if (rf->priv == NULL)
return -ENOMEM;
return 0;
}
| gpl-2.0 |
Pantech-Discover/android_kernel_pantech_magnus | arch/x86/math-emu/reg_add_sub.c | 14421 | 8847 | /*---------------------------------------------------------------------------+
| reg_add_sub.c |
| |
| Functions to add or subtract two registers and put the result in a third. |
| |
| Copyright (C) 1992,1993,1997 |
| W. Metzenthen, 22 Parker St, Ormond, Vic 3163, Australia |
| E-mail billm@suburbia.net |
| |
| |
+---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------+
| For each function, the destination may be any FPU_REG, including one of |
| the source FPU_REGs. |
| Each function returns 0 if the answer is o.k., otherwise a non-zero |
| value is returned, indicating either an exception condition or an |
| internal error. |
+---------------------------------------------------------------------------*/
#include "exception.h"
#include "reg_constant.h"
#include "fpu_emu.h"
#include "control_w.h"
#include "fpu_system.h"
static
int add_sub_specials(FPU_REG const *a, u_char taga, u_char signa,
FPU_REG const *b, u_char tagb, u_char signb,
FPU_REG * dest, int deststnr, int control_w);
/*
Operates on st(0) and st(n), or on st(0) and temporary data.
The destination must be one of the source st(x).
*/
int FPU_add(FPU_REG const *b, u_char tagb, int deststnr, int control_w)
{
FPU_REG *a = &st(0);
FPU_REG *dest = &st(deststnr);
u_char signb = getsign(b);
u_char taga = FPU_gettag0();
u_char signa = getsign(a);
u_char saved_sign = getsign(dest);
int diff, tag, expa, expb;
if (!(taga | tagb)) {
expa = exponent(a);
expb = exponent(b);
valid_add:
/* Both registers are valid */
if (!(signa ^ signb)) {
/* signs are the same */
tag =
FPU_u_add(a, b, dest, control_w, signa, expa, expb);
} else {
/* The signs are different, so do a subtraction */
diff = expa - expb;
if (!diff) {
diff = a->sigh - b->sigh; /* This works only if the ms bits
are identical. */
if (!diff) {
diff = a->sigl > b->sigl;
if (!diff)
diff = -(a->sigl < b->sigl);
}
}
if (diff > 0) {
tag =
FPU_u_sub(a, b, dest, control_w, signa,
expa, expb);
} else if (diff < 0) {
tag =
FPU_u_sub(b, a, dest, control_w, signb,
expb, expa);
} else {
FPU_copy_to_regi(&CONST_Z, TAG_Zero, deststnr);
/* sign depends upon rounding mode */
setsign(dest, ((control_w & CW_RC) != RC_DOWN)
? SIGN_POS : SIGN_NEG);
return TAG_Zero;
}
}
if (tag < 0) {
setsign(dest, saved_sign);
return tag;
}
FPU_settagi(deststnr, tag);
return tag;
}
if (taga == TAG_Special)
taga = FPU_Special(a);
if (tagb == TAG_Special)
tagb = FPU_Special(b);
if (((taga == TAG_Valid) && (tagb == TW_Denormal))
|| ((taga == TW_Denormal) && (tagb == TAG_Valid))
|| ((taga == TW_Denormal) && (tagb == TW_Denormal))) {
FPU_REG x, y;
if (denormal_operand() < 0)
return FPU_Exception;
FPU_to_exp16(a, &x);
FPU_to_exp16(b, &y);
a = &x;
b = &y;
expa = exponent16(a);
expb = exponent16(b);
goto valid_add;
}
if ((taga == TW_NaN) || (tagb == TW_NaN)) {
if (deststnr == 0)
return real_2op_NaN(b, tagb, deststnr, a);
else
return real_2op_NaN(a, taga, deststnr, a);
}
return add_sub_specials(a, taga, signa, b, tagb, signb,
dest, deststnr, control_w);
}
/* Subtract b from a. (a-b) -> dest */
int FPU_sub(int flags, int rm, int control_w)
{
FPU_REG const *a, *b;
FPU_REG *dest;
u_char taga, tagb, signa, signb, saved_sign, sign;
int diff, tag = 0, expa, expb, deststnr;
a = &st(0);
taga = FPU_gettag0();
deststnr = 0;
if (flags & LOADED) {
b = (FPU_REG *) rm;
tagb = flags & 0x0f;
} else {
b = &st(rm);
tagb = FPU_gettagi(rm);
if (flags & DEST_RM)
deststnr = rm;
}
signa = getsign(a);
signb = getsign(b);
if (flags & REV) {
signa ^= SIGN_NEG;
signb ^= SIGN_NEG;
}
dest = &st(deststnr);
saved_sign = getsign(dest);
if (!(taga | tagb)) {
expa = exponent(a);
expb = exponent(b);
valid_subtract:
/* Both registers are valid */
diff = expa - expb;
if (!diff) {
diff = a->sigh - b->sigh; /* Works only if ms bits are identical */
if (!diff) {
diff = a->sigl > b->sigl;
if (!diff)
diff = -(a->sigl < b->sigl);
}
}
switch ((((int)signa) * 2 + signb) / SIGN_NEG) {
case 0: /* P - P */
case 3: /* N - N */
if (diff > 0) {
/* |a| > |b| */
tag =
FPU_u_sub(a, b, dest, control_w, signa,
expa, expb);
} else if (diff == 0) {
FPU_copy_to_regi(&CONST_Z, TAG_Zero, deststnr);
/* sign depends upon rounding mode */
setsign(dest, ((control_w & CW_RC) != RC_DOWN)
? SIGN_POS : SIGN_NEG);
return TAG_Zero;
} else {
sign = signa ^ SIGN_NEG;
tag =
FPU_u_sub(b, a, dest, control_w, sign, expb,
expa);
}
break;
case 1: /* P - N */
tag =
FPU_u_add(a, b, dest, control_w, SIGN_POS, expa,
expb);
break;
case 2: /* N - P */
tag =
FPU_u_add(a, b, dest, control_w, SIGN_NEG, expa,
expb);
break;
#ifdef PARANOID
default:
EXCEPTION(EX_INTERNAL | 0x111);
return -1;
#endif
}
if (tag < 0) {
setsign(dest, saved_sign);
return tag;
}
FPU_settagi(deststnr, tag);
return tag;
}
if (taga == TAG_Special)
taga = FPU_Special(a);
if (tagb == TAG_Special)
tagb = FPU_Special(b);
if (((taga == TAG_Valid) && (tagb == TW_Denormal))
|| ((taga == TW_Denormal) && (tagb == TAG_Valid))
|| ((taga == TW_Denormal) && (tagb == TW_Denormal))) {
FPU_REG x, y;
if (denormal_operand() < 0)
return FPU_Exception;
FPU_to_exp16(a, &x);
FPU_to_exp16(b, &y);
a = &x;
b = &y;
expa = exponent16(a);
expb = exponent16(b);
goto valid_subtract;
}
if ((taga == TW_NaN) || (tagb == TW_NaN)) {
FPU_REG const *d1, *d2;
if (flags & REV) {
d1 = b;
d2 = a;
} else {
d1 = a;
d2 = b;
}
if (flags & LOADED)
return real_2op_NaN(b, tagb, deststnr, d1);
if (flags & DEST_RM)
return real_2op_NaN(a, taga, deststnr, d2);
else
return real_2op_NaN(b, tagb, deststnr, d2);
}
return add_sub_specials(a, taga, signa, b, tagb, signb ^ SIGN_NEG,
dest, deststnr, control_w);
}
static
int add_sub_specials(FPU_REG const *a, u_char taga, u_char signa,
FPU_REG const *b, u_char tagb, u_char signb,
FPU_REG * dest, int deststnr, int control_w)
{
if (((taga == TW_Denormal) || (tagb == TW_Denormal))
&& (denormal_operand() < 0))
return FPU_Exception;
if (taga == TAG_Zero) {
if (tagb == TAG_Zero) {
/* Both are zero, result will be zero. */
u_char different_signs = signa ^ signb;
FPU_copy_to_regi(a, TAG_Zero, deststnr);
if (different_signs) {
/* Signs are different. */
/* Sign of answer depends upon rounding mode. */
setsign(dest, ((control_w & CW_RC) != RC_DOWN)
? SIGN_POS : SIGN_NEG);
} else
setsign(dest, signa); /* signa may differ from the sign of a. */
return TAG_Zero;
} else {
reg_copy(b, dest);
if ((tagb == TW_Denormal) && (b->sigh & 0x80000000)) {
/* A pseudoDenormal, convert it. */
addexponent(dest, 1);
tagb = TAG_Valid;
} else if (tagb > TAG_Empty)
tagb = TAG_Special;
setsign(dest, signb); /* signb may differ from the sign of b. */
FPU_settagi(deststnr, tagb);
return tagb;
}
} else if (tagb == TAG_Zero) {
reg_copy(a, dest);
if ((taga == TW_Denormal) && (a->sigh & 0x80000000)) {
/* A pseudoDenormal */
addexponent(dest, 1);
taga = TAG_Valid;
} else if (taga > TAG_Empty)
taga = TAG_Special;
setsign(dest, signa); /* signa may differ from the sign of a. */
FPU_settagi(deststnr, taga);
return taga;
} else if (taga == TW_Infinity) {
if ((tagb != TW_Infinity) || (signa == signb)) {
FPU_copy_to_regi(a, TAG_Special, deststnr);
setsign(dest, signa); /* signa may differ from the sign of a. */
return taga;
}
/* Infinity-Infinity is undefined. */
return arith_invalid(deststnr);
} else if (tagb == TW_Infinity) {
FPU_copy_to_regi(b, TAG_Special, deststnr);
setsign(dest, signb); /* signb may differ from the sign of b. */
return tagb;
}
#ifdef PARANOID
EXCEPTION(EX_INTERNAL | 0x101);
#endif
return FPU_Exception;
}
| gpl-2.0 |
bizcuite/Kernel_ICS_Archos_Gen8 | drivers/net/skfp/rmt.c | 14677 | 16576 | /******************************************************************************
*
* (C)Copyright 1998,1999 SysKonnect,
* a business unit of Schneider & Koch & Co. Datensysteme GmbH.
*
* See the file "skfddi.c" for further information.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* The information in this file is provided "AS IS" without warranty.
*
******************************************************************************/
/*
SMT RMT
Ring Management
*/
/*
* Hardware independent state machine implemantation
* The following external SMT functions are referenced :
*
* queue_event()
* smt_timer_start()
* smt_timer_stop()
*
* The following external HW dependent functions are referenced :
* sm_ma_control()
* sm_mac_check_beacon_claim()
*
* The following HW dependent events are required :
* RM_RING_OP
* RM_RING_NON_OP
* RM_MY_BEACON
* RM_OTHER_BEACON
* RM_MY_CLAIM
* RM_TRT_EXP
* RM_VALID_CLAIM
*
*/
#include "h/types.h"
#include "h/fddi.h"
#include "h/smc.h"
#define KERNEL
#include "h/smtstate.h"
#ifndef lint
static const char ID_sccs[] = "@(#)rmt.c 2.13 99/07/02 (C) SK " ;
#endif
/*
* FSM Macros
*/
#define AFLAG 0x10
#define GO_STATE(x) (smc->mib.m[MAC0].fddiMACRMTState = (x)|AFLAG)
#define ACTIONS_DONE() (smc->mib.m[MAC0].fddiMACRMTState &= ~AFLAG)
#define ACTIONS(x) (x|AFLAG)
#define RM0_ISOLATED 0
#define RM1_NON_OP 1 /* not operational */
#define RM2_RING_OP 2 /* ring operational */
#define RM3_DETECT 3 /* detect dupl addresses */
#define RM4_NON_OP_DUP 4 /* dupl. addr detected */
#define RM5_RING_OP_DUP 5 /* ring oper. with dupl. addr */
#define RM6_DIRECTED 6 /* sending directed beacons */
#define RM7_TRACE 7 /* trace initiated */
#ifdef DEBUG
/*
* symbolic state names
*/
static const char * const rmt_states[] = {
"RM0_ISOLATED","RM1_NON_OP","RM2_RING_OP","RM3_DETECT",
"RM4_NON_OP_DUP","RM5_RING_OP_DUP","RM6_DIRECTED",
"RM7_TRACE"
} ;
/*
* symbolic event names
*/
static const char * const rmt_events[] = {
"NONE","RM_RING_OP","RM_RING_NON_OP","RM_MY_BEACON",
"RM_OTHER_BEACON","RM_MY_CLAIM","RM_TRT_EXP","RM_VALID_CLAIM",
"RM_JOIN","RM_LOOP","RM_DUP_ADDR","RM_ENABLE_FLAG",
"RM_TIMEOUT_NON_OP","RM_TIMEOUT_T_STUCK",
"RM_TIMEOUT_ANNOUNCE","RM_TIMEOUT_T_DIRECT",
"RM_TIMEOUT_D_MAX","RM_TIMEOUT_POLL","RM_TX_STATE_CHANGE"
} ;
#endif
/*
* Globals
* in struct s_rmt
*/
/*
* function declarations
*/
static void rmt_fsm(struct s_smc *smc, int cmd);
static void start_rmt_timer0(struct s_smc *smc, u_long value, int event);
static void start_rmt_timer1(struct s_smc *smc, u_long value, int event);
static void start_rmt_timer2(struct s_smc *smc, u_long value, int event);
static void stop_rmt_timer0(struct s_smc *smc);
static void stop_rmt_timer1(struct s_smc *smc);
static void stop_rmt_timer2(struct s_smc *smc);
static void rmt_dup_actions(struct s_smc *smc);
static void rmt_reinsert_actions(struct s_smc *smc);
static void rmt_leave_actions(struct s_smc *smc);
static void rmt_new_dup_actions(struct s_smc *smc);
#ifndef SUPERNET_3
extern void restart_trt_for_dbcn() ;
#endif /*SUPERNET_3*/
/*
init RMT state machine
clear all RMT vars and flags
*/
void rmt_init(struct s_smc *smc)
{
smc->mib.m[MAC0].fddiMACRMTState = ACTIONS(RM0_ISOLATED) ;
smc->r.dup_addr_test = DA_NONE ;
smc->r.da_flag = 0 ;
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
smc->r.sm_ma_avail = FALSE ;
smc->r.loop_avail = 0 ;
smc->r.bn_flag = 0 ;
smc->r.jm_flag = 0 ;
smc->r.no_flag = TRUE ;
}
/*
RMT state machine
called by dispatcher
do
display state change
process event
until SM is stable
*/
void rmt(struct s_smc *smc, int event)
{
int state ;
do {
DB_RMT("RMT : state %s%s",
(smc->mib.m[MAC0].fddiMACRMTState & AFLAG) ? "ACTIONS " : "",
rmt_states[smc->mib.m[MAC0].fddiMACRMTState & ~AFLAG]) ;
DB_RMT(" event %s\n",rmt_events[event],0) ;
state = smc->mib.m[MAC0].fddiMACRMTState ;
rmt_fsm(smc,event) ;
event = 0 ;
} while (state != smc->mib.m[MAC0].fddiMACRMTState) ;
rmt_state_change(smc,(int)smc->mib.m[MAC0].fddiMACRMTState) ;
}
/*
process RMT event
*/
static void rmt_fsm(struct s_smc *smc, int cmd)
{
/*
* RM00-RM70 : from all states
*/
if (!smc->r.rm_join && !smc->r.rm_loop &&
smc->mib.m[MAC0].fddiMACRMTState != ACTIONS(RM0_ISOLATED) &&
smc->mib.m[MAC0].fddiMACRMTState != RM0_ISOLATED) {
RS_SET(smc,RS_NORINGOP) ;
rmt_indication(smc,0) ;
GO_STATE(RM0_ISOLATED) ;
return ;
}
switch(smc->mib.m[MAC0].fddiMACRMTState) {
case ACTIONS(RM0_ISOLATED) :
stop_rmt_timer0(smc) ;
stop_rmt_timer1(smc) ;
stop_rmt_timer2(smc) ;
/*
* Disable MAC.
*/
sm_ma_control(smc,MA_OFFLINE) ;
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
smc->r.loop_avail = FALSE ;
smc->r.sm_ma_avail = FALSE ;
smc->r.no_flag = TRUE ;
DB_RMTN(1,"RMT : ISOLATED\n",0,0) ;
ACTIONS_DONE() ;
break ;
case RM0_ISOLATED :
/*RM01*/
if (smc->r.rm_join || smc->r.rm_loop) {
/*
* According to the standard the MAC must be reset
* here. The FORMAC will be initialized and Claim
* and Beacon Frames will be uploaded to the MAC.
* So any change of Treq will take effect NOW.
*/
sm_ma_control(smc,MA_RESET) ;
GO_STATE(RM1_NON_OP) ;
break ;
}
break ;
case ACTIONS(RM1_NON_OP) :
start_rmt_timer0(smc,smc->s.rmt_t_non_op,RM_TIMEOUT_NON_OP) ;
stop_rmt_timer1(smc) ;
stop_rmt_timer2(smc) ;
sm_ma_control(smc,MA_BEACON) ;
DB_RMTN(1,"RMT : RING DOWN\n",0,0) ;
RS_SET(smc,RS_NORINGOP) ;
smc->r.sm_ma_avail = FALSE ;
rmt_indication(smc,0) ;
ACTIONS_DONE() ;
break ;
case RM1_NON_OP :
/*RM12*/
if (cmd == RM_RING_OP) {
RS_SET(smc,RS_RINGOPCHANGE) ;
GO_STATE(RM2_RING_OP) ;
break ;
}
/*RM13*/
else if (cmd == RM_TIMEOUT_NON_OP) {
smc->r.bn_flag = FALSE ;
smc->r.no_flag = TRUE ;
GO_STATE(RM3_DETECT) ;
break ;
}
break ;
case ACTIONS(RM2_RING_OP) :
stop_rmt_timer0(smc) ;
stop_rmt_timer1(smc) ;
stop_rmt_timer2(smc) ;
smc->r.no_flag = FALSE ;
if (smc->r.rm_loop)
smc->r.loop_avail = TRUE ;
if (smc->r.rm_join) {
smc->r.sm_ma_avail = TRUE ;
if (smc->mib.m[MAC0].fddiMACMA_UnitdataEnable)
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = TRUE ;
else
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
}
DB_RMTN(1,"RMT : RING UP\n",0,0) ;
RS_CLEAR(smc,RS_NORINGOP) ;
RS_SET(smc,RS_RINGOPCHANGE) ;
rmt_indication(smc,1) ;
smt_stat_counter(smc,0) ;
ACTIONS_DONE() ;
break ;
case RM2_RING_OP :
/*RM21*/
if (cmd == RM_RING_NON_OP) {
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
smc->r.loop_avail = FALSE ;
RS_SET(smc,RS_RINGOPCHANGE) ;
GO_STATE(RM1_NON_OP) ;
break ;
}
/*RM22a*/
else if (cmd == RM_ENABLE_FLAG) {
if (smc->mib.m[MAC0].fddiMACMA_UnitdataEnable)
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = TRUE ;
else
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
}
/*RM25*/
else if (smc->r.dup_addr_test == DA_FAILED) {
smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
smc->r.loop_avail = FALSE ;
smc->r.da_flag = TRUE ;
GO_STATE(RM5_RING_OP_DUP) ;
break ;
}
break ;
case ACTIONS(RM3_DETECT) :
start_rmt_timer0(smc,smc->s.mac_d_max*2,RM_TIMEOUT_D_MAX) ;
start_rmt_timer1(smc,smc->s.rmt_t_stuck,RM_TIMEOUT_T_STUCK) ;
start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL) ;
sm_mac_check_beacon_claim(smc) ;
DB_RMTN(1,"RMT : RM3_DETECT\n",0,0) ;
ACTIONS_DONE() ;
break ;
case RM3_DETECT :
if (cmd == RM_TIMEOUT_POLL) {
start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL);
sm_mac_check_beacon_claim(smc) ;
break ;
}
if (cmd == RM_TIMEOUT_D_MAX) {
smc->r.timer0_exp = TRUE ;
}
/*
*jd(22-Feb-1999)
* We need a time ">= 2*mac_d_max" since we had finished
* Claim or Beacon state. So we will restart timer0 at
* every state change.
*/
if (cmd == RM_TX_STATE_CHANGE) {
start_rmt_timer0(smc,
smc->s.mac_d_max*2,
RM_TIMEOUT_D_MAX) ;
}
/*RM32*/
if (cmd == RM_RING_OP) {
GO_STATE(RM2_RING_OP) ;
break ;
}
/*RM33a*/
else if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON)
&& smc->r.bn_flag) {
smc->r.bn_flag = FALSE ;
}
/*RM33b*/
else if (cmd == RM_TRT_EXP && !smc->r.bn_flag) {
int tx ;
/*
* set bn_flag only if in state T4 or T5:
* only if we're the beaconer should we start the
* trace !
*/
if ((tx = sm_mac_get_tx_state(smc)) == 4 || tx == 5) {
DB_RMTN(2,"RMT : DETECT && TRT_EXPIRED && T4/T5\n",0,0);
smc->r.bn_flag = TRUE ;
/*
* If one of the upstream stations beaconed
* and the link to the upstream neighbor is
* lost we need to restart the stuck timer to
* check the "stuck beacon" condition.
*/
start_rmt_timer1(smc,smc->s.rmt_t_stuck,
RM_TIMEOUT_T_STUCK) ;
}
/*
* We do NOT need to clear smc->r.bn_flag in case of
* not being in state T4 or T5, because the flag
* must be cleared in order to get in this condition.
*/
DB_RMTN(2,
"RMT : sm_mac_get_tx_state() = %d (bn_flag = %d)\n",
tx,smc->r.bn_flag) ;
}
/*RM34a*/
else if (cmd == RM_MY_CLAIM && smc->r.timer0_exp) {
rmt_new_dup_actions(smc) ;
GO_STATE(RM4_NON_OP_DUP) ;
break ;
}
/*RM34b*/
else if (cmd == RM_MY_BEACON && smc->r.timer0_exp) {
rmt_new_dup_actions(smc) ;
GO_STATE(RM4_NON_OP_DUP) ;
break ;
}
/*RM34c*/
else if (cmd == RM_VALID_CLAIM) {
rmt_new_dup_actions(smc) ;
GO_STATE(RM4_NON_OP_DUP) ;
break ;
}
/*RM36*/
else if (cmd == RM_TIMEOUT_T_STUCK &&
smc->r.rm_join && smc->r.bn_flag) {
GO_STATE(RM6_DIRECTED) ;
break ;
}
break ;
case ACTIONS(RM4_NON_OP_DUP) :
start_rmt_timer0(smc,smc->s.rmt_t_announce,RM_TIMEOUT_ANNOUNCE);
start_rmt_timer1(smc,smc->s.rmt_t_stuck,RM_TIMEOUT_T_STUCK) ;
start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL) ;
sm_mac_check_beacon_claim(smc) ;
DB_RMTN(1,"RMT : RM4_NON_OP_DUP\n",0,0) ;
ACTIONS_DONE() ;
break ;
case RM4_NON_OP_DUP :
if (cmd == RM_TIMEOUT_POLL) {
start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL);
sm_mac_check_beacon_claim(smc) ;
break ;
}
/*RM41*/
if (!smc->r.da_flag) {
GO_STATE(RM1_NON_OP) ;
break ;
}
/*RM44a*/
else if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON) &&
smc->r.bn_flag) {
smc->r.bn_flag = FALSE ;
}
/*RM44b*/
else if (cmd == RM_TRT_EXP && !smc->r.bn_flag) {
int tx ;
/*
* set bn_flag only if in state T4 or T5:
* only if we're the beaconer should we start the
* trace !
*/
if ((tx = sm_mac_get_tx_state(smc)) == 4 || tx == 5) {
DB_RMTN(2,"RMT : NOPDUP && TRT_EXPIRED && T4/T5\n",0,0);
smc->r.bn_flag = TRUE ;
/*
* If one of the upstream stations beaconed
* and the link to the upstream neighbor is
* lost we need to restart the stuck timer to
* check the "stuck beacon" condition.
*/
start_rmt_timer1(smc,smc->s.rmt_t_stuck,
RM_TIMEOUT_T_STUCK) ;
}
/*
* We do NOT need to clear smc->r.bn_flag in case of
* not being in state T4 or T5, because the flag
* must be cleared in order to get in this condition.
*/
DB_RMTN(2,
"RMT : sm_mac_get_tx_state() = %d (bn_flag = %d)\n",
tx,smc->r.bn_flag) ;
}
/*RM44c*/
else if (cmd == RM_TIMEOUT_ANNOUNCE && !smc->r.bn_flag) {
rmt_dup_actions(smc) ;
}
/*RM45*/
else if (cmd == RM_RING_OP) {
smc->r.no_flag = FALSE ;
GO_STATE(RM5_RING_OP_DUP) ;
break ;
}
/*RM46*/
else if (cmd == RM_TIMEOUT_T_STUCK &&
smc->r.rm_join && smc->r.bn_flag) {
GO_STATE(RM6_DIRECTED) ;
break ;
}
break ;
case ACTIONS(RM5_RING_OP_DUP) :
stop_rmt_timer0(smc) ;
stop_rmt_timer1(smc) ;
stop_rmt_timer2(smc) ;
DB_RMTN(1,"RMT : RM5_RING_OP_DUP\n",0,0) ;
ACTIONS_DONE() ;
break;
case RM5_RING_OP_DUP :
/*RM52*/
if (smc->r.dup_addr_test == DA_PASSED) {
smc->r.da_flag = FALSE ;
GO_STATE(RM2_RING_OP) ;
break ;
}
/*RM54*/
else if (cmd == RM_RING_NON_OP) {
smc->r.jm_flag = FALSE ;
smc->r.bn_flag = FALSE ;
GO_STATE(RM4_NON_OP_DUP) ;
break ;
}
break ;
case ACTIONS(RM6_DIRECTED) :
start_rmt_timer0(smc,smc->s.rmt_t_direct,RM_TIMEOUT_T_DIRECT) ;
stop_rmt_timer1(smc) ;
start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL) ;
sm_ma_control(smc,MA_DIRECTED) ;
RS_SET(smc,RS_BEACON) ;
DB_RMTN(1,"RMT : RM6_DIRECTED\n",0,0) ;
ACTIONS_DONE() ;
break ;
case RM6_DIRECTED :
/*RM63*/
if (cmd == RM_TIMEOUT_POLL) {
start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL);
sm_mac_check_beacon_claim(smc) ;
#ifndef SUPERNET_3
/* Because of problems with the Supernet II chip set
* sending of Directed Beacon will stop after 165ms
* therefore restart_trt_for_dbcn(smc) will be called
* to prevent this.
*/
restart_trt_for_dbcn(smc) ;
#endif /*SUPERNET_3*/
break ;
}
if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON) &&
!smc->r.da_flag) {
smc->r.bn_flag = FALSE ;
GO_STATE(RM3_DETECT) ;
break ;
}
/*RM64*/
else if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON) &&
smc->r.da_flag) {
smc->r.bn_flag = FALSE ;
GO_STATE(RM4_NON_OP_DUP) ;
break ;
}
/*RM67*/
else if (cmd == RM_TIMEOUT_T_DIRECT) {
GO_STATE(RM7_TRACE) ;
break ;
}
break ;
case ACTIONS(RM7_TRACE) :
stop_rmt_timer0(smc) ;
stop_rmt_timer1(smc) ;
stop_rmt_timer2(smc) ;
smc->e.trace_prop |= ENTITY_BIT(ENTITY_MAC) ;
queue_event(smc,EVENT_ECM,EC_TRACE_PROP) ;
DB_RMTN(1,"RMT : RM7_TRACE\n",0,0) ;
ACTIONS_DONE() ;
break ;
case RM7_TRACE :
break ;
default:
SMT_PANIC(smc,SMT_E0122, SMT_E0122_MSG) ;
break;
}
}
/*
* (jd) RMT duplicate address actions
* leave the ring or reinsert just as configured
*/
static void rmt_dup_actions(struct s_smc *smc)
{
if (smc->r.jm_flag) {
}
else {
if (smc->s.rmt_dup_mac_behavior) {
SMT_ERR_LOG(smc,SMT_E0138, SMT_E0138_MSG) ;
rmt_reinsert_actions(smc) ;
}
else {
SMT_ERR_LOG(smc,SMT_E0135, SMT_E0135_MSG) ;
rmt_leave_actions(smc) ;
}
}
}
/*
* Reconnect to the Ring
*/
static void rmt_reinsert_actions(struct s_smc *smc)
{
queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
queue_event(smc,EVENT_ECM,EC_CONNECT) ;
}
/*
* duplicate address detected
*/
static void rmt_new_dup_actions(struct s_smc *smc)
{
smc->r.da_flag = TRUE ;
smc->r.bn_flag = FALSE ;
smc->r.jm_flag = FALSE ;
/*
* we have three options : change address, jam or leave
* we leave the ring as default
* Optionally it's possible to reinsert after leaving the Ring
* but this will not conform with SMT Spec.
*/
if (smc->s.rmt_dup_mac_behavior) {
SMT_ERR_LOG(smc,SMT_E0138, SMT_E0138_MSG) ;
rmt_reinsert_actions(smc) ;
}
else {
SMT_ERR_LOG(smc,SMT_E0135, SMT_E0135_MSG) ;
rmt_leave_actions(smc) ;
}
}
/*
* leave the ring
*/
static void rmt_leave_actions(struct s_smc *smc)
{
queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
/*
* Note: Do NOT try again later. (with please reconnect)
* The station must be left from the ring!
*/
}
/*
* SMT timer interface
* start RMT timer 0
*/
static void start_rmt_timer0(struct s_smc *smc, u_long value, int event)
{
smc->r.timer0_exp = FALSE ; /* clear timer event flag */
smt_timer_start(smc,&smc->r.rmt_timer0,value,EV_TOKEN(EVENT_RMT,event));
}
/*
* SMT timer interface
* start RMT timer 1
*/
static void start_rmt_timer1(struct s_smc *smc, u_long value, int event)
{
smc->r.timer1_exp = FALSE ; /* clear timer event flag */
smt_timer_start(smc,&smc->r.rmt_timer1,value,EV_TOKEN(EVENT_RMT,event));
}
/*
* SMT timer interface
* start RMT timer 2
*/
static void start_rmt_timer2(struct s_smc *smc, u_long value, int event)
{
smc->r.timer2_exp = FALSE ; /* clear timer event flag */
smt_timer_start(smc,&smc->r.rmt_timer2,value,EV_TOKEN(EVENT_RMT,event));
}
/*
* SMT timer interface
* stop RMT timer 0
*/
static void stop_rmt_timer0(struct s_smc *smc)
{
if (smc->r.rmt_timer0.tm_active)
smt_timer_stop(smc,&smc->r.rmt_timer0) ;
}
/*
* SMT timer interface
* stop RMT timer 1
*/
static void stop_rmt_timer1(struct s_smc *smc)
{
if (smc->r.rmt_timer1.tm_active)
smt_timer_stop(smc,&smc->r.rmt_timer1) ;
}
/*
* SMT timer interface
* stop RMT timer 2
*/
static void stop_rmt_timer2(struct s_smc *smc)
{
if (smc->r.rmt_timer2.tm_active)
smt_timer_stop(smc,&smc->r.rmt_timer2) ;
}
| gpl-2.0 |
slayher/android_kernel_omap | arch/arm/mach-pxa/corgi_ssp.c | 598 | 7384 | /*
* SSP control code for Sharp Corgi devices
*
* Copyright (c) 2004-2005 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <mach/ssp.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/regs-ssp.h>
#include "sharpsl.h"
static DEFINE_SPINLOCK(corgi_ssp_lock);
static struct ssp_dev corgi_ssp_dev;
static struct ssp_state corgi_ssp_state;
static struct corgissp_machinfo *ssp_machinfo;
/*
* There are three devices connected to the SSP interface:
* 1. A touchscreen controller (TI ADS7846 compatible)
* 2. An LCD controller (with some Backlight functionality)
* 3. A battery monitoring IC (Maxim MAX1111)
*
* Each device uses a different speed/mode of communication.
*
* The touchscreen is very sensitive and the most frequently used
* so the port is left configured for this.
*
* Devices are selected using Chip Selects on GPIOs.
*/
/*
* ADS7846 Routines
*/
unsigned long corgi_ssp_ads7846_putget(ulong data)
{
unsigned long flag;
u32 ret = 0;
spin_lock_irqsave(&corgi_ssp_lock, flag);
if (ssp_machinfo->cs_ads7846 >= 0)
GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
ssp_write_word(&corgi_ssp_dev,data);
ssp_read_word(&corgi_ssp_dev, &ret);
if (ssp_machinfo->cs_ads7846 >= 0)
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
return ret;
}
/*
* NOTE: These functions should always be called in interrupt context
* and use the _lock and _unlock functions. They are very time sensitive.
*/
void corgi_ssp_ads7846_lock(void)
{
spin_lock(&corgi_ssp_lock);
if (ssp_machinfo->cs_ads7846 >= 0)
GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
}
void corgi_ssp_ads7846_unlock(void)
{
if (ssp_machinfo->cs_ads7846 >= 0)
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
spin_unlock(&corgi_ssp_lock);
}
void corgi_ssp_ads7846_put(ulong data)
{
ssp_write_word(&corgi_ssp_dev,data);
}
unsigned long corgi_ssp_ads7846_get(void)
{
u32 ret = 0;
ssp_read_word(&corgi_ssp_dev, &ret);
return ret;
}
EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
EXPORT_SYMBOL(corgi_ssp_ads7846_put);
EXPORT_SYMBOL(corgi_ssp_ads7846_get);
/*
* LCD/Backlight Routines
*/
unsigned long corgi_ssp_dac_put(ulong data)
{
unsigned long flag, sscr1 = SSCR1_SPH;
u32 tmp;
spin_lock_irqsave(&corgi_ssp_lock, flag);
if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
sscr1 = 0;
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
ssp_enable(&corgi_ssp_dev);
if (ssp_machinfo->cs_lcdcon >= 0)
GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
ssp_write_word(&corgi_ssp_dev,data);
/* Read null data back from device to prevent SSP overflow */
ssp_read_word(&corgi_ssp_dev, &tmp);
if (ssp_machinfo->cs_lcdcon >= 0)
GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
ssp_enable(&corgi_ssp_dev);
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
return 0;
}
void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
{
corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
}
void corgi_ssp_blduty_set(int duty)
{
corgi_ssp_lcdtg_send(0x02,duty);
}
EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
EXPORT_SYMBOL(corgi_ssp_blduty_set);
/*
* Max1111 Routines
*/
int corgi_ssp_max1111_get(ulong data)
{
unsigned long flag;
long voltage = 0, voltage1 = 0, voltage2 = 0;
spin_lock_irqsave(&corgi_ssp_lock, flag);
if (ssp_machinfo->cs_max1111 >= 0)
GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
ssp_enable(&corgi_ssp_dev);
udelay(1);
/* TB1/RB1 */
ssp_write_word(&corgi_ssp_dev,data);
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
/* TB12/RB2 */
ssp_write_word(&corgi_ssp_dev,0);
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
/* TB13/RB3*/
ssp_write_word(&corgi_ssp_dev,0);
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
ssp_enable(&corgi_ssp_dev);
if (ssp_machinfo->cs_max1111 >= 0)
GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
if (voltage1 & 0xc0 || voltage2 & 0x3f)
voltage = -1;
else
voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
return voltage;
}
EXPORT_SYMBOL(corgi_ssp_max1111_get);
/*
* Support Routines
*/
void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
{
ssp_machinfo = machinfo;
}
static int __init corgi_ssp_probe(struct platform_device *dev)
{
int ret;
/* Chip Select - Disable All */
if (ssp_machinfo->cs_lcdcon >= 0)
pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH);
if (ssp_machinfo->cs_max1111 >= 0)
pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
if (ssp_machinfo->cs_ads7846 >= 0)
pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
if (ret)
printk(KERN_ERR "Unable to register SSP handler!\n");
else {
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
ssp_enable(&corgi_ssp_dev);
}
return ret;
}
static int corgi_ssp_remove(struct platform_device *dev)
{
ssp_exit(&corgi_ssp_dev);
return 0;
}
static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
{
ssp_flush(&corgi_ssp_dev);
ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
return 0;
}
static int corgi_ssp_resume(struct platform_device *dev)
{
if (ssp_machinfo->cs_lcdcon >= 0)
GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */
if (ssp_machinfo->cs_max1111 >= 0)
GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
if (ssp_machinfo->cs_ads7846 >= 0)
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
ssp_enable(&corgi_ssp_dev);
return 0;
}
static struct platform_driver corgissp_driver = {
.probe = corgi_ssp_probe,
.remove = corgi_ssp_remove,
.suspend = corgi_ssp_suspend,
.resume = corgi_ssp_resume,
.driver = {
.name = "corgi-ssp",
},
};
int __init corgi_ssp_init(void)
{
return platform_driver_register(&corgissp_driver);
}
arch_initcall(corgi_ssp_init);
| gpl-2.0 |
dongsupark/linux | arch/arm64/kernel/smp_spin_table.c | 598 | 3426 | /*
* Spin Table SMP initialisation
*
* Copyright (C) 2013 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <asm/cacheflush.h>
#include <asm/cpu_ops.h>
#include <asm/cputype.h>
#include <asm/io.h>
#include <asm/smp_plat.h>
extern void secondary_holding_pen(void);
volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
static phys_addr_t cpu_release_addr[NR_CPUS];
/*
* Write secondary_holding_pen_release in a way that is guaranteed to be
* visible to all observers, irrespective of whether they're taking part
* in coherency or not. This is necessary for the hotplug code to work
* reliably.
*/
static void write_pen_release(u64 val)
{
void *start = (void *)&secondary_holding_pen_release;
unsigned long size = sizeof(secondary_holding_pen_release);
secondary_holding_pen_release = val;
__flush_dcache_area(start, size);
}
static int smp_spin_table_cpu_init(unsigned int cpu)
{
struct device_node *dn;
dn = of_get_cpu_node(cpu, NULL);
if (!dn)
return -ENODEV;
/*
* Determine the address from which the CPU is polling.
*/
if (of_property_read_u64(dn, "cpu-release-addr",
&cpu_release_addr[cpu])) {
pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
cpu);
return -1;
}
return 0;
}
static int smp_spin_table_cpu_prepare(unsigned int cpu)
{
__le64 __iomem *release_addr;
if (!cpu_release_addr[cpu])
return -ENODEV;
/*
* The cpu-release-addr may or may not be inside the linear mapping.
* As ioremap_cache will either give us a new mapping or reuse the
* existing linear mapping, we can use it to cover both cases. In
* either case the memory will be MT_NORMAL.
*/
release_addr = ioremap_cache(cpu_release_addr[cpu],
sizeof(*release_addr));
if (!release_addr)
return -ENOMEM;
/*
* We write the release address as LE regardless of the native
* endianess of the kernel. Therefore, any boot-loaders that
* read this address need to convert this address to the
* boot-loader's endianess before jumping. This is mandated by
* the boot protocol.
*/
writeq_relaxed(__pa(secondary_holding_pen), release_addr);
__flush_dcache_area((__force void *)release_addr,
sizeof(*release_addr));
/*
* Send an event to wake up the secondary CPU.
*/
sev();
iounmap(release_addr);
return 0;
}
static int smp_spin_table_cpu_boot(unsigned int cpu)
{
/*
* Update the pen release flag.
*/
write_pen_release(cpu_logical_map(cpu));
/*
* Send an event, causing the secondaries to read pen_release.
*/
sev();
return 0;
}
const struct cpu_operations smp_spin_table_ops = {
.name = "spin-table",
.cpu_init = smp_spin_table_cpu_init,
.cpu_prepare = smp_spin_table_cpu_prepare,
.cpu_boot = smp_spin_table_cpu_boot,
};
| gpl-2.0 |
jamal-ahmad/Logging-Kernel | drivers/hwtracing/stm/console.c | 598 | 2187 | /*
* Simple kernel console driver for STM devices
* Copyright (c) 2014, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* STM console will send kernel messages over STM devices to a trace host.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/slab.h>
#include <linux/stm.h>
static int stm_console_link(struct stm_source_data *data);
static void stm_console_unlink(struct stm_source_data *data);
static struct stm_console {
struct stm_source_data data;
struct console console;
} stm_console = {
.data = {
.name = "console",
.nr_chans = 1,
.link = stm_console_link,
.unlink = stm_console_unlink,
},
};
static void
stm_console_write(struct console *con, const char *buf, unsigned len)
{
struct stm_console *sc = container_of(con, struct stm_console, console);
stm_source_write(&sc->data, 0, buf, len);
}
static int stm_console_link(struct stm_source_data *data)
{
struct stm_console *sc = container_of(data, struct stm_console, data);
strcpy(sc->console.name, "stm_console");
sc->console.write = stm_console_write;
sc->console.flags = CON_ENABLED | CON_PRINTBUFFER;
register_console(&sc->console);
return 0;
}
static void stm_console_unlink(struct stm_source_data *data)
{
struct stm_console *sc = container_of(data, struct stm_console, data);
unregister_console(&sc->console);
}
static int stm_console_init(void)
{
return stm_source_register_device(NULL, &stm_console.data);
}
static void stm_console_exit(void)
{
stm_source_unregister_device(&stm_console.data);
}
module_init(stm_console_init);
module_exit(stm_console_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("stm_console driver");
MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@linux.intel.com>");
| gpl-2.0 |
PyYoshi/android_kernel_kyocera_isw12k | drivers/video/msm/lcdc_chimei_wxga.c | 854 | 5167 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/pwm.h>
#ifdef CONFIG_PMIC8058_PWM
#include <linux/mfd/pmic8058.h>
#include <linux/pmic8058-pwm.h>
#endif
#include <mach/gpio.h>
#include "msm_fb.h"
static struct pwm_device *bl_pwm;
#define PWM_FREQ_HZ 210
#define PWM_PERIOD_USEC (USEC_PER_SEC / PWM_FREQ_HZ)
#define PWM_DUTY_LEVEL (PWM_PERIOD_USEC / PWM_LEVEL)
#define PWM_LEVEL 15
static struct msm_panel_common_pdata *cm_pdata;
static struct platform_device *cm_fbpdev;
static int led_pwm; /* pm8058 gpio 24, channel 0 */
static int led_en; /* pm8058 gpio 1 */
static int lvds_pwr_down; /* msm gpio 30 */
static int chimei_bl_level = 1;
static void lcdc_chimei_set_backlight(int level)
{
int ret;
if (bl_pwm) {
ret = pwm_config(bl_pwm, PWM_DUTY_LEVEL * level,
PWM_PERIOD_USEC);
if (ret) {
pr_err("%s: pwm_config on pwm failed %d\n",
__func__, ret);
return;
}
ret = pwm_enable(bl_pwm);
if (ret) {
pr_err("%s: pwm_enable on pwm failed %d\n",
__func__, ret);
return;
}
}
chimei_bl_level = level;
}
static int lcdc_chimei_panel_on(struct platform_device *pdev)
{
int ret;
/* panel powered on here */
ret = gpio_request(lvds_pwr_down, "lvds_pwr_down");
if (ret == 0) {
/* output, pull high to enable */
gpio_direction_output(lvds_pwr_down, 1);
} else {
pr_err("%s: lvds_pwr_down=%d, gpio_request failed\n",
__func__, lvds_pwr_down);
}
msleep(200);
/* power on led pwm power >= 200 ms */
if (chimei_bl_level == 0)
chimei_bl_level = 1;
lcdc_chimei_set_backlight(chimei_bl_level);
msleep(10);
ret = gpio_request(led_en, "led_en");
if (ret == 0) {
/* output, pull high */
gpio_direction_output(led_en, 1);
} else {
pr_err("%s: led_en=%d, gpio_request failed\n",
__func__, led_en);
}
return ret;
}
static int lcdc_chimei_panel_off(struct platform_device *pdev)
{
/* pull low to disable */
gpio_set_value_cansleep(led_en, 0);
gpio_free(led_en);
msleep(10);
lcdc_chimei_set_backlight(0);
msleep(200);
/* power off led pwm power >= 200 ms */
/* pull low to shut down lvds */
gpio_set_value_cansleep(lvds_pwr_down, 0);
gpio_free(lvds_pwr_down);
/* panel power off here */
return 0;
}
static void lcdc_chimei_panel_backlight(struct msm_fb_data_type *mfd)
{
lcdc_chimei_set_backlight(mfd->bl_level);
}
static int __devinit chimei_probe(struct platform_device *pdev)
{
int rc = 0;
if (pdev->id == 0) {
cm_pdata = pdev->dev.platform_data;
if (cm_pdata == NULL) {
pr_err("%s: no PWM gpio specified\n", __func__);
return 0;
}
led_pwm = cm_pdata->gpio_num[0];
led_en = cm_pdata->gpio_num[1];
lvds_pwr_down = cm_pdata->gpio_num[2];
pr_info("%s: led_pwm=%d led_en=%d lvds_pwr_down=%d\n",
__func__, led_pwm, led_en, lvds_pwr_down);
return 0;
}
if (cm_pdata == NULL)
return -ENODEV;
bl_pwm = pwm_request(led_pwm, "backlight");
if (bl_pwm == NULL || IS_ERR(bl_pwm)) {
pr_err("%s pwm_request() failed\n", __func__);
bl_pwm = NULL;
}
cm_fbpdev = msm_fb_add_device(pdev);
if (!cm_fbpdev) {
dev_err(&pdev->dev, "failed to add msm_fb device\n");
rc = -ENODEV;
goto probe_exit;
}
probe_exit:
return rc;
}
static struct platform_driver this_driver = {
.probe = chimei_probe,
.driver = {
.name = "lcdc_chimei_lvds_wxga",
},
};
static struct msm_fb_panel_data chimei_panel_data = {
.on = lcdc_chimei_panel_on,
.off = lcdc_chimei_panel_off,
.set_backlight = lcdc_chimei_panel_backlight,
};
static struct platform_device this_device = {
.name = "lcdc_chimei_lvds_wxga",
.id = 1,
.dev = {
.platform_data = &chimei_panel_data,
}
};
static int __init lcdc_chimei_lvds_panel_init(void)
{
int ret;
struct msm_panel_info *pinfo;
if (msm_fb_detect_client("lcdc_chimei_wxga"))
return 0;
ret = platform_driver_register(&this_driver);
if (ret)
return ret;
pinfo = &chimei_panel_data.panel_info;
pinfo->xres = 1366;
pinfo->yres = 768;
MSM_FB_SINGLE_MODE_PANEL(pinfo);
pinfo->type = LCDC_PANEL;
pinfo->pdest = DISPLAY_1;
pinfo->wait_cycle = 0;
pinfo->bpp = 18;
pinfo->fb_num = 2;
pinfo->clk_rate = 69300000;
pinfo->bl_max = PWM_LEVEL;
pinfo->bl_min = 1;
/*
* this panel is operated by de,
* vsycn and hsync are ignored
*/
pinfo->lcdc.h_back_porch = 108;
pinfo->lcdc.h_front_porch = 0;
pinfo->lcdc.h_pulse_width = 1;
pinfo->lcdc.v_back_porch = 0;
pinfo->lcdc.v_front_porch = 16;
pinfo->lcdc.v_pulse_width = 1;
pinfo->lcdc.border_clr = 0;
pinfo->lcdc.underflow_clr = 0xff;
pinfo->lcdc.hsync_skew = 0;
ret = platform_device_register(&this_device);
if (ret)
platform_driver_unregister(&this_driver);
return ret;
}
module_init(lcdc_chimei_lvds_panel_init);
| gpl-2.0 |
aeroevan/vivo_w-kernel | arch/blackfin/mach-bf561/boards/ezkit.c | 854 | 11608 | /*
* Copyright 2004-2009 Analog Devices Inc.
* 2005 National ICT Australia (NICTA)
* Aidan Williams <aidan@nicta.com.au>
*
* Licensed under the GPL-2 or later.
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
/*
* Name the Board for the /proc/cpuinfo
*/
const char bfin_board_name[] = "ADI BF561-EZKIT";
#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
#include <linux/usb/isp1760.h>
static struct resource bfin_isp1760_resources[] = {
[0] = {
.start = 0x2C0F0000,
.end = 0x203C0000 + 0xfffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = IORESOURCE_IRQ,
},
};
static struct isp1760_platform_data isp1760_priv = {
.is_isp1761 = 0,
.bus_width_16 = 1,
.port1_otg = 0,
.analog_oc = 0,
.dack_polarity_high = 0,
.dreq_polarity_high = 0,
};
static struct platform_device bfin_isp1760_device = {
.name = "isp1760",
.id = 0,
.dev = {
.platform_data = &isp1760_priv,
},
.num_resources = ARRAY_SIZE(bfin_isp1760_resources),
.resource = bfin_isp1760_resources,
};
#endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
static struct resource isp1362_hcd_resources[] = {
{
.start = 0x2c060000,
.end = 0x2c060000,
.flags = IORESOURCE_MEM,
}, {
.start = 0x2c060004,
.end = 0x2c060004,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF8,
.end = IRQ_PF8,
.flags = IORESOURCE_IRQ,
},
};
static struct isp1362_platform_data isp1362_priv = {
.sel15Kres = 1,
.clknotstop = 0,
.oc_enable = 0,
.int_act_high = 0,
.int_edge_triggered = 0,
.remote_wakeup_connected = 0,
.no_power_switching = 1,
.power_switching_mode = 0,
};
static struct platform_device isp1362_hcd_device = {
.name = "isp1362-hcd",
.id = 0,
.dev = {
.platform_data = &isp1362_priv,
},
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
.resource = isp1362_hcd_resources,
};
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
static struct resource net2272_bfin_resources[] = {
{
.start = 0x2C000000,
.end = 0x2C000000 + 0x7F,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct platform_device net2272_bfin_device = {
.name = "net2272",
.id = -1,
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
.resource = net2272_bfin_resources,
};
#endif
/*
* USB-LAN EzExtender board
* Driver needs to know address, irq and flag pin.
*/
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
#include <linux/smc91x.h>
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_32BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
{
.name = "smc91x-regs",
.start = 0x2C010300,
.end = 0x2C010300 + 16,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF9,
.end = IRQ_PF9,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &smc91x_info,
},
};
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
static struct resource bfin_uart0_resources[] = {
{
.start = BFIN_UART_THR,
.end = BFIN_UART_GCTL+2,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART_RX,
.end = IRQ_UART_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_UART_ERROR,
.end = IRQ_UART_ERROR,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_UART_TX,
.end = CH_UART_TX,
.flags = IORESOURCE_DMA,
},
{
.start = CH_UART_RX,
.end = CH_UART_RX,
.flags = IORESOURCE_DMA,
},
};
unsigned short bfin_uart0_peripherals[] = {
P_UART0_TX, P_UART0_RX, 0
};
static struct platform_device bfin_uart0_device = {
.name = "bfin-uart",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
.resource = bfin_uart0_resources,
.dev = {
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
},
};
#endif
#endif
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
#ifdef CONFIG_BFIN_SIR0
static struct resource bfin_sir0_resources[] = {
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART0_RX,
.end = IRQ_UART0_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_UART0_RX,
.end = CH_UART0_RX+1,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device bfin_sir0_device = {
.name = "bfin_sir",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
.resource = bfin_sir0_resources,
};
#endif
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition ezkit_partitions[] = {
{
.name = "bootloader(nor)",
.size = 0x40000,
.offset = 0,
}, {
.name = "linux kernel(nor)",
.size = 0x1C0000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
static struct physmap_flash_data ezkit_flash_data = {
.width = 2,
.parts = ezkit_partitions,
.nr_parts = ARRAY_SIZE(ezkit_partitions),
};
static struct resource ezkit_flash_resource = {
.start = 0x20000000,
.end = 0x207fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device ezkit_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &ezkit_flash_data,
},
.num_resources = 1,
.resource = &ezkit_flash_resource,
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
[0] = {
.start = SPI0_REGBASE,
.end = SPI0_REGBASE + 0xFF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CH_SPI,
.end = CH_SPI,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = IRQ_SPI,
.end = IRQ_SPI,
.flags = IORESOURCE_IRQ,
}
};
/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
.num_chipselect = 8,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
static struct platform_device bfin_spi0_device = {
.name = "bfin-spi",
.id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource,
.dev = {
.platform_data = &bfin_spi0_info, /* Passed to driver */
},
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
{
.modalias = "ad1836",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.controller_data = &ad1836_spi_chip_info,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/input.h>
#include <linux/gpio_keys.h>
static struct gpio_keys_button bfin_gpio_keys_table[] = {
{BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
{BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
{BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
{BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
};
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
.buttons = bfin_gpio_keys_table,
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
};
static struct platform_device bfin_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &bfin_gpio_keys_data,
},
};
#endif
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
#include <linux/i2c-gpio.h>
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = 1,
.scl_pin = 0,
.sda_is_open_drain = 0,
.scl_is_open_drain = 0,
.udelay = 40,
};
static struct platform_device i2c_gpio_device = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = &i2c_gpio_data,
},
};
#endif
static const unsigned int cclk_vlev_datasheet[] =
{
VRPAIR(VLEV_085, 250000000),
VRPAIR(VLEV_090, 300000000),
VRPAIR(VLEV_095, 313000000),
VRPAIR(VLEV_100, 350000000),
VRPAIR(VLEV_105, 400000000),
VRPAIR(VLEV_110, 444000000),
VRPAIR(VLEV_115, 450000000),
VRPAIR(VLEV_120, 475000000),
VRPAIR(VLEV_125, 500000000),
VRPAIR(VLEV_130, 600000000),
};
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
.tuple_tab = cclk_vlev_datasheet,
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
.vr_settling_time = 25 /* us */,
};
static struct platform_device bfin_dpmc = {
.name = "bfin dpmc",
.dev = {
.platform_data = &bfin_dmpc_vreg_data,
},
};
static struct platform_device *ezkit_devices[] __initdata = {
&bfin_dpmc,
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
&smc91x_device,
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
&net2272_bfin_device,
#endif
#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
&bfin_isp1760_device,
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device,
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
&bfin_uart0_device,
#endif
#endif
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
#ifdef CONFIG_BFIN_SIR0
&bfin_sir0_device,
#endif
#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
&bfin_device_gpiokeys,
#endif
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
&i2c_gpio_device,
#endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
&isp1362_hcd_device,
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&ezkit_flash_device,
#endif
};
static int __init ezkit_init(void)
{
int ret;
printk(KERN_INFO "%s(): registering device resources\n", __func__);
ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
if (ret < 0)
return ret;
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
SSYNC();
#endif
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
return 0;
}
arch_initcall(ezkit_init);
static struct platform_device *ezkit_early_devices[] __initdata = {
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
#ifdef CONFIG_SERIAL_BFIN_UART0
&bfin_uart0_device,
#endif
#endif
};
void __init native_machine_early_platform_add_devices(void)
{
printk(KERN_INFO "register early platform devices\n");
early_platform_add_devices(ezkit_early_devices,
ARRAY_SIZE(ezkit_early_devices));
}
| gpl-2.0 |
loansindi/linux | drivers/ata/libata-trace.c | 854 | 4427 | /*
* libata-trace.c - trace functions for libata
*
* Copyright 2015 Hannes Reinecke
* Copyright 2015 SUSE Linux GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/trace_seq.h>
#include <trace/events/libata.h>
const char *
libata_trace_parse_status(struct trace_seq *p, unsigned char status)
{
const char *ret = trace_seq_buffer_ptr(p);
trace_seq_printf(p, "{ ");
if (status & ATA_BUSY)
trace_seq_printf(p, "BUSY ");
if (status & ATA_DRDY)
trace_seq_printf(p, "DRDY ");
if (status & ATA_DF)
trace_seq_printf(p, "DF ");
if (status & ATA_DSC)
trace_seq_printf(p, "DSC ");
if (status & ATA_DRQ)
trace_seq_printf(p, "DRQ ");
if (status & ATA_CORR)
trace_seq_printf(p, "CORR ");
if (status & ATA_SENSE)
trace_seq_printf(p, "SENSE ");
if (status & ATA_ERR)
trace_seq_printf(p, "ERR ");
trace_seq_putc(p, '}');
trace_seq_putc(p, 0);
return ret;
}
const char *
libata_trace_parse_eh_action(struct trace_seq *p, unsigned int eh_action)
{
const char *ret = trace_seq_buffer_ptr(p);
trace_seq_printf(p, "%x", eh_action);
if (eh_action) {
trace_seq_printf(p, "{ ");
if (eh_action & ATA_EH_REVALIDATE)
trace_seq_printf(p, "REVALIDATE ");
if (eh_action & (ATA_EH_SOFTRESET | ATA_EH_HARDRESET))
trace_seq_printf(p, "RESET ");
else if (eh_action & ATA_EH_SOFTRESET)
trace_seq_printf(p, "SOFTRESET ");
else if (eh_action & ATA_EH_HARDRESET)
trace_seq_printf(p, "HARDRESET ");
if (eh_action & ATA_EH_ENABLE_LINK)
trace_seq_printf(p, "ENABLE_LINK ");
if (eh_action & ATA_EH_PARK)
trace_seq_printf(p, "PARK ");
trace_seq_putc(p, '}');
}
trace_seq_putc(p, 0);
return ret;
}
const char *
libata_trace_parse_eh_err_mask(struct trace_seq *p, unsigned int eh_err_mask)
{
const char *ret = trace_seq_buffer_ptr(p);
trace_seq_printf(p, "%x", eh_err_mask);
if (eh_err_mask) {
trace_seq_printf(p, "{ ");
if (eh_err_mask & AC_ERR_DEV)
trace_seq_printf(p, "DEV ");
if (eh_err_mask & AC_ERR_HSM)
trace_seq_printf(p, "HSM ");
if (eh_err_mask & AC_ERR_TIMEOUT)
trace_seq_printf(p, "TIMEOUT ");
if (eh_err_mask & AC_ERR_MEDIA)
trace_seq_printf(p, "MEDIA ");
if (eh_err_mask & AC_ERR_ATA_BUS)
trace_seq_printf(p, "ATA_BUS ");
if (eh_err_mask & AC_ERR_HOST_BUS)
trace_seq_printf(p, "HOST_BUS ");
if (eh_err_mask & AC_ERR_SYSTEM)
trace_seq_printf(p, "SYSTEM ");
if (eh_err_mask & AC_ERR_INVALID)
trace_seq_printf(p, "INVALID ");
if (eh_err_mask & AC_ERR_OTHER)
trace_seq_printf(p, "OTHER ");
if (eh_err_mask & AC_ERR_NODEV_HINT)
trace_seq_printf(p, "NODEV_HINT ");
if (eh_err_mask & AC_ERR_NCQ)
trace_seq_printf(p, "NCQ ");
trace_seq_putc(p, '}');
}
trace_seq_putc(p, 0);
return ret;
}
const char *
libata_trace_parse_qc_flags(struct trace_seq *p, unsigned int qc_flags)
{
const char *ret = trace_seq_buffer_ptr(p);
trace_seq_printf(p, "%x", qc_flags);
if (qc_flags) {
trace_seq_printf(p, "{ ");
if (qc_flags & ATA_QCFLAG_ACTIVE)
trace_seq_printf(p, "ACTIVE ");
if (qc_flags & ATA_QCFLAG_DMAMAP)
trace_seq_printf(p, "DMAMAP ");
if (qc_flags & ATA_QCFLAG_IO)
trace_seq_printf(p, "IO ");
if (qc_flags & ATA_QCFLAG_RESULT_TF)
trace_seq_printf(p, "RESULT_TF ");
if (qc_flags & ATA_QCFLAG_CLEAR_EXCL)
trace_seq_printf(p, "CLEAR_EXCL ");
if (qc_flags & ATA_QCFLAG_QUIET)
trace_seq_printf(p, "QUIET ");
if (qc_flags & ATA_QCFLAG_RETRY)
trace_seq_printf(p, "RETRY ");
if (qc_flags & ATA_QCFLAG_FAILED)
trace_seq_printf(p, "FAILED ");
if (qc_flags & ATA_QCFLAG_SENSE_VALID)
trace_seq_printf(p, "SENSE_VALID ");
if (qc_flags & ATA_QCFLAG_EH_SCHEDULED)
trace_seq_printf(p, "EH_SCHEDULED ");
trace_seq_putc(p, '}');
}
trace_seq_putc(p, 0);
return ret;
}
| gpl-2.0 |
JPG-Consulting/linux | arch/s390/appldata/appldata_net_sum.c | 2390 | 4263 | /*
* Data gathering module for Linux-VM Monitor Stream, Stage 1.
* Collects accumulated network statistics (Packets received/transmitted,
* dropped, errors, ...).
*
* Copyright IBM Corp. 2003, 2006
*
* Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/kernel_stat.h>
#include <linux/netdevice.h>
#include <net/net_namespace.h>
#include "appldata.h"
/*
* Network data
*
* This is accessed as binary data by z/VM. If changes to it can't be avoided,
* the structure version (product ID, see appldata_base.c) needs to be changed
* as well and all documentation and z/VM applications using it must be updated.
*
* The record layout is documented in the Linux for zSeries Device Drivers
* book:
* http://oss.software.ibm.com/developerworks/opensource/linux390/index.shtml
*/
struct appldata_net_sum_data {
u64 timestamp;
u32 sync_count_1; /* after VM collected the record data, */
u32 sync_count_2; /* sync_count_1 and sync_count_2 should be the
same. If not, the record has been updated on
the Linux side while VM was collecting the
(possibly corrupt) data */
u32 nr_interfaces; /* nr. of network interfaces being monitored */
u32 padding; /* next value is 64-bit aligned, so these */
/* 4 byte would be padded out by compiler */
u64 rx_packets; /* total packets received */
u64 tx_packets; /* total packets transmitted */
u64 rx_bytes; /* total bytes received */
u64 tx_bytes; /* total bytes transmitted */
u64 rx_errors; /* bad packets received */
u64 tx_errors; /* packet transmit problems */
u64 rx_dropped; /* no space in linux buffers */
u64 tx_dropped; /* no space available in linux */
u64 collisions; /* collisions while transmitting */
} __packed;
/*
* appldata_get_net_sum_data()
*
* gather accumulated network statistics
*/
static void appldata_get_net_sum_data(void *data)
{
int i;
struct appldata_net_sum_data *net_data;
struct net_device *dev;
unsigned long rx_packets, tx_packets, rx_bytes, tx_bytes, rx_errors,
tx_errors, rx_dropped, tx_dropped, collisions;
net_data = data;
net_data->sync_count_1++;
i = 0;
rx_packets = 0;
tx_packets = 0;
rx_bytes = 0;
tx_bytes = 0;
rx_errors = 0;
tx_errors = 0;
rx_dropped = 0;
tx_dropped = 0;
collisions = 0;
rcu_read_lock();
for_each_netdev_rcu(&init_net, dev) {
const struct rtnl_link_stats64 *stats;
struct rtnl_link_stats64 temp;
stats = dev_get_stats(dev, &temp);
rx_packets += stats->rx_packets;
tx_packets += stats->tx_packets;
rx_bytes += stats->rx_bytes;
tx_bytes += stats->tx_bytes;
rx_errors += stats->rx_errors;
tx_errors += stats->tx_errors;
rx_dropped += stats->rx_dropped;
tx_dropped += stats->tx_dropped;
collisions += stats->collisions;
i++;
}
rcu_read_unlock();
net_data->nr_interfaces = i;
net_data->rx_packets = rx_packets;
net_data->tx_packets = tx_packets;
net_data->rx_bytes = rx_bytes;
net_data->tx_bytes = tx_bytes;
net_data->rx_errors = rx_errors;
net_data->tx_errors = tx_errors;
net_data->rx_dropped = rx_dropped;
net_data->tx_dropped = tx_dropped;
net_data->collisions = collisions;
net_data->timestamp = get_tod_clock();
net_data->sync_count_2++;
}
static struct appldata_ops ops = {
.name = "net_sum",
.record_nr = APPLDATA_RECORD_NET_SUM_ID,
.size = sizeof(struct appldata_net_sum_data),
.callback = &appldata_get_net_sum_data,
.owner = THIS_MODULE,
.mod_lvl = {0xF0, 0xF0}, /* EBCDIC "00" */
};
/*
* appldata_net_init()
*
* init data, register ops
*/
static int __init appldata_net_init(void)
{
int ret;
ops.data = kzalloc(sizeof(struct appldata_net_sum_data), GFP_KERNEL);
if (!ops.data)
return -ENOMEM;
ret = appldata_register_ops(&ops);
if (ret)
kfree(ops.data);
return ret;
}
/*
* appldata_net_exit()
*
* unregister ops
*/
static void __exit appldata_net_exit(void)
{
appldata_unregister_ops(&ops);
kfree(ops.data);
}
module_init(appldata_net_init);
module_exit(appldata_net_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Gerald Schaefer");
MODULE_DESCRIPTION("Linux-VM Monitor Stream, accumulated network statistics");
| gpl-2.0 |
HONO/CM10_Kernel | arch/x86/kernel/acpi/cstate.c | 2646 | 4980 | /*
* Copyright (C) 2005 Intel Corporation
* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
* - Added _PDC for SMP C-states on Intel CPUs
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/sched.h>
#include <acpi/processor.h>
#include <asm/acpi.h>
#include <asm/mwait.h>
/*
* Initialize bm_flags based on the CPU cache properties
* On SMP it depends on cache configuration
* - When cache is not shared among all CPUs, we flush cache
* before entering C3.
* - When cache is shared among all CPUs, we use bm_check
* mechanism as in UP case
*
* This routine is called only after all the CPUs are online
*/
void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
unsigned int cpu)
{
struct cpuinfo_x86 *c = &cpu_data(cpu);
flags->bm_check = 0;
if (num_online_cpus() == 1)
flags->bm_check = 1;
else if (c->x86_vendor == X86_VENDOR_INTEL) {
/*
* Today all MP CPUs that support C3 share cache.
* And caches should not be flushed by software while
* entering C3 type state.
*/
flags->bm_check = 1;
}
/*
* On all recent Intel platforms, ARB_DISABLE is a nop.
* So, set bm_control to zero to indicate that ARB_DISABLE
* is not required while entering C3 type state on
* P4, Core and beyond CPUs
*/
if (c->x86_vendor == X86_VENDOR_INTEL &&
(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
flags->bm_control = 0;
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
/* The code below handles cstate entry with monitor-mwait pair on Intel*/
struct cstate_entry {
struct {
unsigned int eax;
unsigned int ecx;
} states[ACPI_PROCESSOR_MAX_POWER];
};
static struct cstate_entry __percpu *cpu_cstate_entry; /* per CPU ptr */
static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
#define NATIVE_CSTATE_BEYOND_HALT (2)
static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
{
struct acpi_processor_cx *cx = _cx;
long retval;
unsigned int eax, ebx, ecx, edx;
unsigned int edx_part;
unsigned int cstate_type; /* C-state type and not ACPI C-state type */
unsigned int num_cstate_subtype;
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
/* Check whether this particular cx_type (in CST) is supported or not */
cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
MWAIT_CSTATE_MASK) + 1;
edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
retval = 0;
if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
retval = -1;
goto out;
}
/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
!(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
retval = -1;
goto out;
}
if (!mwait_supported[cstate_type]) {
mwait_supported[cstate_type] = 1;
printk(KERN_DEBUG
"Monitor-Mwait will be used to enter C-%d "
"state\n", cx->type);
}
snprintf(cx->desc,
ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
cx->address);
out:
return retval;
}
int acpi_processor_ffh_cstate_probe(unsigned int cpu,
struct acpi_processor_cx *cx, struct acpi_power_register *reg)
{
struct cstate_entry *percpu_entry;
struct cpuinfo_x86 *c = &cpu_data(cpu);
long retval;
if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
return -1;
if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
return -1;
percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
percpu_entry->states[cx->index].eax = 0;
percpu_entry->states[cx->index].ecx = 0;
/* Make sure we are running on right CPU */
retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
if (retval == 0) {
/* Use the hint in CST */
percpu_entry->states[cx->index].eax = cx->address;
percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
}
/*
* For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
* then we should skip checking BM_STS for this C-state.
* ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
*/
if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
cx->bm_sts_skip = 1;
return retval;
}
EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
{
unsigned int cpu = smp_processor_id();
struct cstate_entry *percpu_entry;
percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
percpu_entry->states[cx->index].ecx);
}
EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
static int __init ffh_cstate_init(void)
{
struct cpuinfo_x86 *c = &boot_cpu_data;
if (c->x86_vendor != X86_VENDOR_INTEL)
return -1;
cpu_cstate_entry = alloc_percpu(struct cstate_entry);
return 0;
}
static void __exit ffh_cstate_exit(void)
{
free_percpu(cpu_cstate_entry);
cpu_cstate_entry = NULL;
}
arch_initcall(ffh_cstate_init);
__exitcall(ffh_cstate_exit);
| gpl-2.0 |
javifo/android_kernel_samsung_smdk4412 | fs/nfs/getroot.c | 3158 | 6746 | /* getroot.c: get the root dentry for an NFS mount
*
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/time.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/stat.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/sunrpc/clnt.h>
#include <linux/sunrpc/stats.h>
#include <linux/nfs_fs.h>
#include <linux/nfs_mount.h>
#include <linux/nfs4_mount.h>
#include <linux/lockd/bind.h>
#include <linux/seq_file.h>
#include <linux/mount.h>
#include <linux/nfs_idmap.h>
#include <linux/vfs.h>
#include <linux/namei.h>
#include <linux/security.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include "nfs4_fs.h"
#include "delegation.h"
#include "internal.h"
#define NFSDBG_FACILITY NFSDBG_CLIENT
/*
* Set the superblock root dentry.
* Note that this function frees the inode in case of error.
*/
static int nfs_superblock_set_dummy_root(struct super_block *sb, struct inode *inode)
{
/* The mntroot acts as the dummy root dentry for this superblock */
if (sb->s_root == NULL) {
sb->s_root = d_alloc_root(inode);
if (sb->s_root == NULL) {
iput(inode);
return -ENOMEM;
}
ihold(inode);
/*
* Ensure that this dentry is invisible to d_find_alias().
* Otherwise, it may be spliced into the tree by
* d_materialise_unique if a parent directory from the same
* filesystem gets mounted at a later time.
* This again causes shrink_dcache_for_umount_subtree() to
* Oops, since the test for IS_ROOT() will fail.
*/
spin_lock(&sb->s_root->d_inode->i_lock);
spin_lock(&sb->s_root->d_lock);
list_del_init(&sb->s_root->d_alias);
spin_unlock(&sb->s_root->d_lock);
spin_unlock(&sb->s_root->d_inode->i_lock);
}
return 0;
}
/*
* get an NFS2/NFS3 root dentry from the root filehandle
*/
struct dentry *nfs_get_root(struct super_block *sb, struct nfs_fh *mntfh,
const char *devname)
{
struct nfs_server *server = NFS_SB(sb);
struct nfs_fsinfo fsinfo;
struct dentry *ret;
struct inode *inode;
void *name = kstrdup(devname, GFP_KERNEL);
int error;
if (!name)
return ERR_PTR(-ENOMEM);
/* get the actual root for this mount */
fsinfo.fattr = nfs_alloc_fattr();
if (fsinfo.fattr == NULL) {
kfree(name);
return ERR_PTR(-ENOMEM);
}
error = server->nfs_client->rpc_ops->getroot(server, mntfh, &fsinfo);
if (error < 0) {
dprintk("nfs_get_root: getattr error = %d\n", -error);
ret = ERR_PTR(error);
goto out;
}
inode = nfs_fhget(sb, mntfh, fsinfo.fattr);
if (IS_ERR(inode)) {
dprintk("nfs_get_root: get root inode failed\n");
ret = ERR_CAST(inode);
goto out;
}
error = nfs_superblock_set_dummy_root(sb, inode);
if (error != 0) {
ret = ERR_PTR(error);
goto out;
}
/* root dentries normally start off anonymous and get spliced in later
* if the dentry tree reaches them; however if the dentry already
* exists, we'll pick it up at this point and use it as the root
*/
ret = d_obtain_alias(inode);
if (IS_ERR(ret)) {
dprintk("nfs_get_root: get root dentry failed\n");
goto out;
}
security_d_instantiate(ret, inode);
spin_lock(&ret->d_lock);
if (IS_ROOT(ret) && !(ret->d_flags & DCACHE_NFSFS_RENAMED)) {
ret->d_fsdata = name;
name = NULL;
}
spin_unlock(&ret->d_lock);
out:
if (name)
kfree(name);
nfs_free_fattr(fsinfo.fattr);
return ret;
}
#ifdef CONFIG_NFS_V4
int nfs4_get_rootfh(struct nfs_server *server, struct nfs_fh *mntfh)
{
struct nfs_fsinfo fsinfo;
int ret = -ENOMEM;
dprintk("--> nfs4_get_rootfh()\n");
fsinfo.fattr = nfs_alloc_fattr();
if (fsinfo.fattr == NULL)
goto out;
/* Start by getting the root filehandle from the server */
ret = server->nfs_client->rpc_ops->getroot(server, mntfh, &fsinfo);
if (ret < 0) {
dprintk("nfs4_get_rootfh: getroot error = %d\n", -ret);
goto out;
}
if (!(fsinfo.fattr->valid & NFS_ATTR_FATTR_TYPE)
|| !S_ISDIR(fsinfo.fattr->mode)) {
printk(KERN_ERR "nfs4_get_rootfh:"
" getroot encountered non-directory\n");
ret = -ENOTDIR;
goto out;
}
if (fsinfo.fattr->valid & NFS_ATTR_FATTR_V4_REFERRAL) {
printk(KERN_ERR "nfs4_get_rootfh:"
" getroot obtained referral\n");
ret = -EREMOTE;
goto out;
}
memcpy(&server->fsid, &fsinfo.fattr->fsid, sizeof(server->fsid));
out:
nfs_free_fattr(fsinfo.fattr);
dprintk("<-- nfs4_get_rootfh() = %d\n", ret);
return ret;
}
/*
* get an NFS4 root dentry from the root filehandle
*/
struct dentry *nfs4_get_root(struct super_block *sb, struct nfs_fh *mntfh,
const char *devname)
{
struct nfs_server *server = NFS_SB(sb);
struct nfs_fattr *fattr = NULL;
struct dentry *ret;
struct inode *inode;
void *name = kstrdup(devname, GFP_KERNEL);
int error;
dprintk("--> nfs4_get_root()\n");
if (!name)
return ERR_PTR(-ENOMEM);
/* get the info about the server and filesystem */
error = nfs4_server_capabilities(server, mntfh);
if (error < 0) {
dprintk("nfs_get_root: getcaps error = %d\n",
-error);
kfree(name);
return ERR_PTR(error);
}
fattr = nfs_alloc_fattr();
if (fattr == NULL) {
kfree(name);
return ERR_PTR(-ENOMEM);
}
/* get the actual root for this mount */
error = server->nfs_client->rpc_ops->getattr(server, mntfh, fattr);
if (error < 0) {
dprintk("nfs_get_root: getattr error = %d\n", -error);
ret = ERR_PTR(error);
goto out;
}
if (fattr->valid & NFS_ATTR_FATTR_FSID &&
!nfs_fsid_equal(&server->fsid, &fattr->fsid))
memcpy(&server->fsid, &fattr->fsid, sizeof(server->fsid));
inode = nfs_fhget(sb, mntfh, fattr);
if (IS_ERR(inode)) {
dprintk("nfs_get_root: get root inode failed\n");
ret = ERR_CAST(inode);
goto out;
}
error = nfs_superblock_set_dummy_root(sb, inode);
if (error != 0) {
ret = ERR_PTR(error);
goto out;
}
/* root dentries normally start off anonymous and get spliced in later
* if the dentry tree reaches them; however if the dentry already
* exists, we'll pick it up at this point and use it as the root
*/
ret = d_obtain_alias(inode);
if (IS_ERR(ret)) {
dprintk("nfs_get_root: get root dentry failed\n");
goto out;
}
security_d_instantiate(ret, inode);
spin_lock(&ret->d_lock);
if (IS_ROOT(ret) && !(ret->d_flags & DCACHE_NFSFS_RENAMED)) {
ret->d_fsdata = name;
name = NULL;
}
spin_unlock(&ret->d_lock);
out:
if (name)
kfree(name);
nfs_free_fattr(fattr);
dprintk("<-- nfs4_get_root()\n");
return ret;
}
#endif /* CONFIG_NFS_V4 */
| gpl-2.0 |
jollaman999/msm-mako-lollipop-mr1 | arch/hexagon/kernel/traps.c | 3158 | 10685 | /*
* Kernel traps/events for Hexagon processor
*
* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
#include <linux/kdebug.h>
#include <linux/syscalls.h>
#include <linux/signal.h>
#include <linux/tracehook.h>
#include <asm/traps.h>
#include <asm/vm_fault.h>
#include <asm/syscall.h>
#include <asm/registers.h>
#include <asm/unistd.h>
#include <asm/sections.h>
#ifdef CONFIG_KGDB
# include <linux/kgdb.h>
#endif
#define TRAP_SYSCALL 1
#define TRAP_DEBUG 0xdb
void __init trap_init(void)
{
}
#ifdef CONFIG_GENERIC_BUG
/* Maybe should resemble arch/sh/kernel/traps.c ?? */
int is_valid_bugaddr(unsigned long addr)
{
return 1;
}
#endif /* CONFIG_GENERIC_BUG */
static const char *ex_name(int ex)
{
switch (ex) {
case HVM_GE_C_XPROT:
case HVM_GE_C_XUSER:
return "Execute protection fault";
case HVM_GE_C_RPROT:
case HVM_GE_C_RUSER:
return "Read protection fault";
case HVM_GE_C_WPROT:
case HVM_GE_C_WUSER:
return "Write protection fault";
case HVM_GE_C_XMAL:
return "Misaligned instruction";
case HVM_GE_C_RMAL:
return "Misaligned data load";
case HVM_GE_C_WMAL:
return "Misaligned data store";
case HVM_GE_C_INVI:
case HVM_GE_C_PRIVI:
return "Illegal instruction";
case HVM_GE_C_BUS:
return "Precise bus error";
case HVM_GE_C_CACHE:
return "Cache error";
case 0xdb:
return "Debugger trap";
default:
return "Unrecognized exception";
}
}
static void do_show_stack(struct task_struct *task, unsigned long *fp,
unsigned long ip)
{
int kstack_depth_to_print = 24;
unsigned long offset, size;
const char *name = NULL;
unsigned long *newfp;
unsigned long low, high;
char tmpstr[128];
char *modname;
int i;
if (task == NULL)
task = current;
printk(KERN_INFO "CPU#%d, %s/%d, Call Trace:\n",
raw_smp_processor_id(), task->comm,
task_pid_nr(task));
if (fp == NULL) {
if (task == current) {
asm("%0 = r30" : "=r" (fp));
} else {
fp = (unsigned long *)
((struct hexagon_switch_stack *)
task->thread.switch_sp)->fp;
}
}
if ((((unsigned long) fp) & 0x3) || ((unsigned long) fp < 0x1000)) {
printk(KERN_INFO "-- Corrupt frame pointer %p\n", fp);
return;
}
/* Saved link reg is one word above FP */
if (!ip)
ip = *(fp+1);
/* Expect kernel stack to be in-bounds */
low = (unsigned long)task_stack_page(task);
high = low + THREAD_SIZE - 8;
low += sizeof(struct thread_info);
for (i = 0; i < kstack_depth_to_print; i++) {
name = kallsyms_lookup(ip, &size, &offset, &modname, tmpstr);
printk(KERN_INFO "[%p] 0x%lx: %s + 0x%lx", fp, ip, name,
offset);
if (((unsigned long) fp < low) || (high < (unsigned long) fp))
printk(KERN_CONT " (FP out of bounds!)");
if (modname)
printk(KERN_CONT " [%s] ", modname);
printk(KERN_CONT "\n");
newfp = (unsigned long *) *fp;
if (((unsigned long) newfp) & 0x3) {
printk(KERN_INFO "-- Corrupt frame pointer %p\n",
newfp);
break;
}
/* Attempt to continue past exception. */
if (0 == newfp) {
struct pt_regs *regs = (struct pt_regs *) (((void *)fp)
+ 8);
if (regs->syscall_nr != -1) {
printk(KERN_INFO "-- trap0 -- syscall_nr: %ld",
regs->syscall_nr);
printk(KERN_CONT " psp: %lx elr: %lx\n",
pt_psp(regs), pt_elr(regs));
break;
} else {
/* really want to see more ... */
kstack_depth_to_print += 6;
printk(KERN_INFO "-- %s (0x%lx) badva: %lx\n",
ex_name(pt_cause(regs)), pt_cause(regs),
pt_badva(regs));
}
newfp = (unsigned long *) regs->r30;
ip = pt_elr(regs);
} else {
ip = *(newfp + 1);
}
/* If link reg is null, we are done. */
if (ip == 0x0)
break;
/* If newfp isn't larger, we're tracing garbage. */
if (newfp > fp)
fp = newfp;
else
break;
}
}
void show_stack(struct task_struct *task, unsigned long *fp)
{
/* Saved link reg is one word above FP */
do_show_stack(task, fp, 0);
}
void dump_stack(void)
{
unsigned long *fp;
asm("%0 = r30" : "=r" (fp));
show_stack(current, fp);
}
EXPORT_SYMBOL(dump_stack);
int die(const char *str, struct pt_regs *regs, long err)
{
static struct {
spinlock_t lock;
int counter;
} die = {
.lock = __SPIN_LOCK_UNLOCKED(die.lock),
.counter = 0
};
console_verbose();
oops_enter();
spin_lock_irq(&die.lock);
bust_spinlocks(1);
printk(KERN_EMERG "Oops: %s[#%d]:\n", str, ++die.counter);
if (notify_die(DIE_OOPS, str, regs, err, pt_cause(regs), SIGSEGV) ==
NOTIFY_STOP)
return 1;
print_modules();
show_regs(regs);
do_show_stack(current, ®s->r30, pt_elr(regs));
bust_spinlocks(0);
add_taint(TAINT_DIE);
spin_unlock_irq(&die.lock);
if (in_interrupt())
panic("Fatal exception in interrupt");
if (panic_on_oops)
panic("Fatal exception");
oops_exit();
do_exit(err);
return 0;
}
int die_if_kernel(char *str, struct pt_regs *regs, long err)
{
if (!user_mode(regs))
return die(str, regs, err);
else
return 0;
}
/*
* It's not clear that misaligned fetches are ever recoverable.
*/
static void misaligned_instruction(struct pt_regs *regs)
{
die_if_kernel("Misaligned Instruction", regs, 0);
force_sig(SIGBUS, current);
}
/*
* Misaligned loads and stores, on the other hand, can be
* emulated, and probably should be, some day. But for now
* they will be considered fatal.
*/
static void misaligned_data_load(struct pt_regs *regs)
{
die_if_kernel("Misaligned Data Load", regs, 0);
force_sig(SIGBUS, current);
}
static void misaligned_data_store(struct pt_regs *regs)
{
die_if_kernel("Misaligned Data Store", regs, 0);
force_sig(SIGBUS, current);
}
static void illegal_instruction(struct pt_regs *regs)
{
die_if_kernel("Illegal Instruction", regs, 0);
force_sig(SIGILL, current);
}
/*
* Precise bus errors may be recoverable with a a retry,
* but for now, treat them as irrecoverable.
*/
static void precise_bus_error(struct pt_regs *regs)
{
die_if_kernel("Precise Bus Error", regs, 0);
force_sig(SIGBUS, current);
}
/*
* If anything is to be done here other than panic,
* it will probably be complex and migrate to another
* source module. For now, just die.
*/
static void cache_error(struct pt_regs *regs)
{
die("Cache Error", regs, 0);
}
/*
* General exception handler
*/
void do_genex(struct pt_regs *regs)
{
/*
* Decode Cause and Dispatch
*/
switch (pt_cause(regs)) {
case HVM_GE_C_XPROT:
case HVM_GE_C_XUSER:
execute_protection_fault(regs);
break;
case HVM_GE_C_RPROT:
case HVM_GE_C_RUSER:
read_protection_fault(regs);
break;
case HVM_GE_C_WPROT:
case HVM_GE_C_WUSER:
write_protection_fault(regs);
break;
case HVM_GE_C_XMAL:
misaligned_instruction(regs);
break;
case HVM_GE_C_RMAL:
misaligned_data_load(regs);
break;
case HVM_GE_C_WMAL:
misaligned_data_store(regs);
break;
case HVM_GE_C_INVI:
case HVM_GE_C_PRIVI:
illegal_instruction(regs);
break;
case HVM_GE_C_BUS:
precise_bus_error(regs);
break;
case HVM_GE_C_CACHE:
cache_error(regs);
break;
default:
/* Halt and catch fire */
panic("Unrecognized exception 0x%lx\n", pt_cause(regs));
break;
}
}
/* Indirect system call dispatch */
long sys_syscall(void)
{
printk(KERN_ERR "sys_syscall invoked!\n");
return -ENOSYS;
}
void do_trap0(struct pt_regs *regs)
{
unsigned long syscallret = 0;
syscall_fn syscall;
switch (pt_cause(regs)) {
case TRAP_SYSCALL:
/* System call is trap0 #1 */
/* allow strace to catch syscall args */
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACE) &&
tracehook_report_syscall_entry(regs)))
return; /* return -ENOSYS somewhere? */
/* Interrupts should be re-enabled for syscall processing */
__vmsetie(VM_INT_ENABLE);
/*
* System call number is in r6, arguments in r0..r5.
* Fortunately, no Linux syscall has more than 6 arguments,
* and Hexagon ABI passes first 6 arguments in registers.
* 64-bit arguments are passed in odd/even register pairs.
* Fortunately, we have no system calls that take more
* than three arguments with more than one 64-bit value.
* Should that change, we'd need to redesign to copy
* between user and kernel stacks.
*/
regs->syscall_nr = regs->r06;
/*
* GPR R0 carries the first parameter, and is also used
* to report the return value. We need a backup of
* the user's value in case we need to do a late restart
* of the system call.
*/
regs->restart_r0 = regs->r00;
if ((unsigned long) regs->syscall_nr >= __NR_syscalls) {
regs->r00 = -1;
} else {
syscall = (syscall_fn)
(sys_call_table[regs->syscall_nr]);
syscallret = syscall(regs->r00, regs->r01,
regs->r02, regs->r03,
regs->r04, regs->r05);
}
/*
* If it was a sigreturn system call, don't overwrite
* r0 value in stack frame with return value.
*
* __NR_sigreturn doesn't seem to exist in new unistd.h
*/
if (regs->syscall_nr != __NR_rt_sigreturn)
regs->r00 = syscallret;
/* allow strace to get the syscall return state */
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACE)))
tracehook_report_syscall_exit(regs, 0);
break;
case TRAP_DEBUG:
/* Trap0 0xdb is debug breakpoint */
if (user_mode(regs)) {
struct siginfo info;
info.si_signo = SIGTRAP;
info.si_errno = 0;
/*
* Some architecures add some per-thread state
* to distinguish between breakpoint traps and
* trace traps. We may want to do that, and
* set the si_code value appropriately, or we
* may want to use a different trap0 flavor.
*/
info.si_code = TRAP_BRKPT;
info.si_addr = (void __user *) pt_elr(regs);
send_sig_info(SIGTRAP, &info, current);
} else {
#ifdef CONFIG_KGDB
kgdb_handle_exception(pt_cause(regs), SIGTRAP,
TRAP_BRKPT, regs);
#endif
}
break;
}
/* Ignore other trap0 codes for now, especially 0 (Angel calls) */
}
/*
* Machine check exception handler
*/
void do_machcheck(struct pt_regs *regs)
{
/* Halt and catch fire */
__vmstop();
}
| gpl-2.0 |
w1ndy/linux | drivers/video/fbdev/omap2/dss/overlay-sysfs.c | 4438 | 9819 | /*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define DSS_SUBSYS_NAME "OVERLAY"
#include <linux/module.h>
#include <linux/err.h>
#include <linux/sysfs.h>
#include <linux/kobject.h>
#include <linux/platform_device.h>
#include <video/omapdss.h>
#include "dss.h"
#include "dss_features.h"
static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name);
}
static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%s\n",
ovl->manager ? ovl->manager->name : "<none>");
}
static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,
size_t size)
{
int i, r;
struct omap_overlay_manager *mgr = NULL;
struct omap_overlay_manager *old_mgr;
int len = size;
if (buf[size-1] == '\n')
--len;
if (len > 0) {
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
mgr = omap_dss_get_overlay_manager(i);
if (sysfs_streq(buf, mgr->name))
break;
mgr = NULL;
}
}
if (len > 0 && mgr == NULL)
return -EINVAL;
if (mgr)
DSSDBG("manager %s found\n", mgr->name);
if (mgr == ovl->manager)
return size;
old_mgr = ovl->manager;
r = dispc_runtime_get();
if (r)
return r;
/* detach old manager */
if (old_mgr) {
r = ovl->unset_manager(ovl);
if (r) {
DSSERR("detach failed\n");
goto err;
}
r = old_mgr->apply(old_mgr);
if (r)
goto err;
}
if (mgr) {
r = ovl->set_manager(ovl, mgr);
if (r) {
DSSERR("Failed to attach overlay\n");
goto err;
}
r = mgr->apply(mgr);
if (r)
goto err;
}
dispc_runtime_put();
return size;
err:
dispc_runtime_put();
return r;
}
static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d,%d\n",
info.width, info.height);
}
static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d\n", info.screen_width);
}
static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d,%d\n",
info.pos_x, info.pos_y);
}
static ssize_t overlay_position_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
char *last;
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
info.pos_x = simple_strtoul(buf, &last, 10);
++last;
if (last - buf >= size)
return -EINVAL;
info.pos_y = simple_strtoul(last, &last, 10);
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d,%d\n",
info.out_width, info.out_height);
}
static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
char *last;
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
info.out_width = simple_strtoul(buf, &last, 10);
++last;
if (last - buf >= size)
return -EINVAL;
info.out_height = simple_strtoul(last, &last, 10);
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n", ovl->is_enabled(ovl));
}
static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf,
size_t size)
{
int r;
bool enable;
r = strtobool(buf, &enable);
if (r)
return r;
if (enable)
r = ovl->enable(ovl);
else
r = ovl->disable(ovl);
if (r)
return r;
return size;
}
static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d\n",
info.global_alpha);
}
static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
u8 alpha;
struct omap_overlay_info info;
if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
return -ENODEV;
r = kstrtou8(buf, 0, &alpha);
if (r)
return r;
ovl->get_overlay_info(ovl, &info);
info.global_alpha = alpha;
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_pre_mult_alpha_show(struct omap_overlay *ovl,
char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d\n",
info.pre_mult_alpha);
}
static ssize_t overlay_pre_mult_alpha_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
u8 alpha;
struct omap_overlay_info info;
if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
return -ENODEV;
r = kstrtou8(buf, 0, &alpha);
if (r)
return r;
ovl->get_overlay_info(ovl, &info);
info.pre_mult_alpha = alpha;
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_zorder_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return snprintf(buf, PAGE_SIZE, "%d\n", info.zorder);
}
static ssize_t overlay_zorder_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
u8 zorder;
struct omap_overlay_info info;
if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
return -ENODEV;
r = kstrtou8(buf, 0, &zorder);
if (r)
return r;
ovl->get_overlay_info(ovl, &info);
info.zorder = zorder;
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
struct overlay_attribute {
struct attribute attr;
ssize_t (*show)(struct omap_overlay *, char *);
ssize_t (*store)(struct omap_overlay *, const char *, size_t);
};
#define OVERLAY_ATTR(_name, _mode, _show, _store) \
struct overlay_attribute overlay_attr_##_name = \
__ATTR(_name, _mode, _show, _store)
static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
overlay_manager_show, overlay_manager_store);
static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
overlay_position_show, overlay_position_store);
static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
overlay_output_size_show, overlay_output_size_store);
static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
overlay_enabled_show, overlay_enabled_store);
static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR,
overlay_global_alpha_show, overlay_global_alpha_store);
static OVERLAY_ATTR(pre_mult_alpha, S_IRUGO|S_IWUSR,
overlay_pre_mult_alpha_show,
overlay_pre_mult_alpha_store);
static OVERLAY_ATTR(zorder, S_IRUGO|S_IWUSR,
overlay_zorder_show, overlay_zorder_store);
static struct attribute *overlay_sysfs_attrs[] = {
&overlay_attr_name.attr,
&overlay_attr_manager.attr,
&overlay_attr_input_size.attr,
&overlay_attr_screen_width.attr,
&overlay_attr_position.attr,
&overlay_attr_output_size.attr,
&overlay_attr_enabled.attr,
&overlay_attr_global_alpha.attr,
&overlay_attr_pre_mult_alpha.attr,
&overlay_attr_zorder.attr,
NULL
};
static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr,
char *buf)
{
struct omap_overlay *overlay;
struct overlay_attribute *overlay_attr;
overlay = container_of(kobj, struct omap_overlay, kobj);
overlay_attr = container_of(attr, struct overlay_attribute, attr);
if (!overlay_attr->show)
return -ENOENT;
return overlay_attr->show(overlay, buf);
}
static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
const char *buf, size_t size)
{
struct omap_overlay *overlay;
struct overlay_attribute *overlay_attr;
overlay = container_of(kobj, struct omap_overlay, kobj);
overlay_attr = container_of(attr, struct overlay_attribute, attr);
if (!overlay_attr->store)
return -ENOENT;
return overlay_attr->store(overlay, buf, size);
}
static const struct sysfs_ops overlay_sysfs_ops = {
.show = overlay_attr_show,
.store = overlay_attr_store,
};
static struct kobj_type overlay_ktype = {
.sysfs_ops = &overlay_sysfs_ops,
.default_attrs = overlay_sysfs_attrs,
};
int dss_overlay_kobj_init(struct omap_overlay *ovl,
struct platform_device *pdev)
{
return kobject_init_and_add(&ovl->kobj, &overlay_ktype,
&pdev->dev.kobj, "overlay%d", ovl->id);
}
void dss_overlay_kobj_uninit(struct omap_overlay *ovl)
{
kobject_del(&ovl->kobj);
kobject_put(&ovl->kobj);
}
| gpl-2.0 |
Loller79/Solid_Kernel-GEEHRC-Bricked | arch/openrisc/kernel/idle.c | 4694 | 1886 | /*
* OpenRISC idle.c
*
* Linux architectural port borrowing liberally from similar works of
* others. All original copyrights apply as per the original source
* declaration.
*
* Modifications for the OpenRISC architecture:
* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Idle daemon for or32. Idle daemon will handle any action
* that needs to be taken when the system becomes idle.
*/
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/tick.h>
#include <asm/pgtable.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/pgalloc.h>
void (*powersave) (void) = NULL;
static inline void pm_idle(void)
{
barrier();
}
void cpu_idle(void)
{
set_thread_flag(TIF_POLLING_NRFLAG);
/* endless idle loop with no priority at all */
while (1) {
tick_nohz_idle_enter();
rcu_idle_enter();
while (!need_resched()) {
check_pgt_cache();
rmb();
clear_thread_flag(TIF_POLLING_NRFLAG);
local_irq_disable();
/* Don't trace irqs off for idle */
stop_critical_timings();
if (!need_resched() && powersave != NULL)
powersave();
start_critical_timings();
local_irq_enable();
set_thread_flag(TIF_POLLING_NRFLAG);
}
rcu_idle_exit();
tick_nohz_idle_exit();
preempt_enable_no_resched();
schedule();
preempt_disable();
}
}
| gpl-2.0 |
Hundsbuah/Note3_Samsung_Source_Drops | drivers/video/grvga.c | 4950 | 14819 | /*
* Driver for Aeroflex Gaisler SVGACTRL framebuffer device.
*
* 2011 (c) Aeroflex Gaisler AB
*
* Full documentation of the core can be found here:
* http://www.gaisler.com/products/grlib/grip.pdf
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Contributors: Kristoffer Glembo <kristoffer@gaisler.com>
*
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/io.h>
struct grvga_regs {
u32 status; /* 0x00 */
u32 video_length; /* 0x04 */
u32 front_porch; /* 0x08 */
u32 sync_length; /* 0x0C */
u32 line_length; /* 0x10 */
u32 fb_pos; /* 0x14 */
u32 clk_vector[4]; /* 0x18 */
u32 clut; /* 0x20 */
};
struct grvga_par {
struct grvga_regs *regs;
u32 color_palette[16]; /* 16 entry pseudo palette used by fbcon in true color mode */
int clk_sel;
int fb_alloced; /* = 1 if framebuffer is allocated in main memory */
};
static const struct fb_videomode grvga_modedb[] = {
{
/* 640x480 @ 60 Hz */
NULL, 60, 640, 480, 40000, 48, 16, 39, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 60 Hz */
NULL, 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 72 Hz */
NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 60 Hz */
NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}
};
static struct fb_fix_screeninfo grvga_fix __devinitdata = {
.id = "AG SVGACTRL",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static int grvga_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct grvga_par *par = info->par;
int i;
if (!var->xres)
var->xres = 1;
if (!var->yres)
var->yres = 1;
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 24)
var->bits_per_pixel = 24;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
else
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = 2*var->yres;
if (info->fix.smem_len) {
if ((var->yres_virtual*var->xres_virtual*var->bits_per_pixel/8) > info->fix.smem_len)
return -ENOMEM;
}
/* Which clocks that are available can be read out in these registers */
for (i = 0; i <= 3 ; i++) {
if (var->pixclock == par->regs->clk_vector[i])
break;
}
if (i <= 3)
par->clk_sel = i;
else
return -EINVAL;
switch (info->var.bits_per_pixel) {
case 8:
var->red = (struct fb_bitfield) {0, 8, 0}; /* offset, length, msb-right */
var->green = (struct fb_bitfield) {0, 8, 0};
var->blue = (struct fb_bitfield) {0, 8, 0};
var->transp = (struct fb_bitfield) {0, 0, 0};
break;
case 16:
var->red = (struct fb_bitfield) {11, 5, 0};
var->green = (struct fb_bitfield) {5, 6, 0};
var->blue = (struct fb_bitfield) {0, 5, 0};
var->transp = (struct fb_bitfield) {0, 0, 0};
break;
case 24:
case 32:
var->red = (struct fb_bitfield) {16, 8, 0};
var->green = (struct fb_bitfield) {8, 8, 0};
var->blue = (struct fb_bitfield) {0, 8, 0};
var->transp = (struct fb_bitfield) {24, 8, 0};
break;
default:
return -EINVAL;
}
return 0;
}
static int grvga_set_par(struct fb_info *info)
{
u32 func = 0;
struct grvga_par *par = info->par;
__raw_writel(((info->var.yres - 1) << 16) | (info->var.xres - 1),
&par->regs->video_length);
__raw_writel((info->var.lower_margin << 16) | (info->var.right_margin),
&par->regs->front_porch);
__raw_writel((info->var.vsync_len << 16) | (info->var.hsync_len),
&par->regs->sync_length);
__raw_writel(((info->var.yres + info->var.lower_margin + info->var.upper_margin + info->var.vsync_len - 1) << 16) |
(info->var.xres + info->var.right_margin + info->var.left_margin + info->var.hsync_len - 1),
&par->regs->line_length);
switch (info->var.bits_per_pixel) {
case 8:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
func = 1;
break;
case 16:
info->fix.visual = FB_VISUAL_TRUECOLOR;
func = 2;
break;
case 24:
case 32:
info->fix.visual = FB_VISUAL_TRUECOLOR;
func = 3;
break;
default:
return -EINVAL;
}
__raw_writel((par->clk_sel << 6) | (func << 4) | 1,
&par->regs->status);
info->fix.line_length = (info->var.xres_virtual*info->var.bits_per_pixel)/8;
return 0;
}
static int grvga_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info)
{
struct grvga_par *par;
par = info->par;
if (regno >= 256) /* Size of CLUT */
return -EINVAL;
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
#undef CNVT_TOHW
/* In PSEUDOCOLOR we use the hardware CLUT */
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
__raw_writel((regno << 24) | (red << 16) | (green << 8) | blue,
&par->regs->clut);
/* Truecolor uses the pseudo palette */
else if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
if (regno >= 16)
return -EINVAL;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
((u32 *) (info->pseudo_palette))[regno] = v;
}
return 0;
}
static int grvga_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct grvga_par *par = info->par;
struct fb_fix_screeninfo *fix = &info->fix;
u32 base_addr;
if (var->xoffset != 0)
return -EINVAL;
base_addr = fix->smem_start + (var->yoffset * fix->line_length);
base_addr &= ~3UL;
/* Set framebuffer base address */
__raw_writel(base_addr,
&par->regs->fb_pos);
return 0;
}
static struct fb_ops grvga_ops = {
.owner = THIS_MODULE,
.fb_check_var = grvga_check_var,
.fb_set_par = grvga_set_par,
.fb_setcolreg = grvga_setcolreg,
.fb_pan_display = grvga_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit
};
static int __devinit grvga_parse_custom(char *options,
struct fb_var_screeninfo *screendata)
{
char *this_opt;
int count = 0;
if (!options || !*options)
return -1;
while ((this_opt = strsep(&options, " ")) != NULL) {
if (!*this_opt)
continue;
switch (count) {
case 0:
screendata->pixclock = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 1:
screendata->xres = screendata->xres_virtual = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 2:
screendata->right_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 3:
screendata->hsync_len = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 4:
screendata->left_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 5:
screendata->yres = screendata->yres_virtual = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 6:
screendata->lower_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 7:
screendata->vsync_len = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 8:
screendata->upper_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 9:
screendata->bits_per_pixel = simple_strtoul(this_opt, NULL, 0);
count++;
break;
default:
return -1;
}
}
screendata->activate = FB_ACTIVATE_NOW;
screendata->vmode = FB_VMODE_NONINTERLACED;
return 0;
}
static int __devinit grvga_probe(struct platform_device *dev)
{
struct fb_info *info;
int retval = -ENOMEM;
unsigned long virtual_start;
unsigned long grvga_fix_addr = 0;
unsigned long physical_start = 0;
unsigned long grvga_mem_size = 0;
struct grvga_par *par = NULL;
char *options = NULL, *mode_opt = NULL;
info = framebuffer_alloc(sizeof(struct grvga_par), &dev->dev);
if (!info) {
dev_err(&dev->dev, "framebuffer_alloc failed\n");
return -ENOMEM;
}
/* Expecting: "grvga: modestring, [addr:<framebuffer physical address>], [size:<framebuffer size>]
*
* If modestring is custom:<custom mode string> we parse the string which then contains all videoparameters
* If address is left out, we allocate memory,
* if size is left out we only allocate enough to support the given mode.
*/
if (fb_get_options("grvga", &options)) {
retval = -ENODEV;
goto err;
}
if (!options || !*options)
options = "640x480-8@60";
while (1) {
char *this_opt = strsep(&options, ",");
if (!this_opt)
break;
if (!strncmp(this_opt, "custom", 6)) {
if (grvga_parse_custom(this_opt, &info->var) < 0) {
dev_err(&dev->dev, "Failed to parse custom mode (%s).\n", this_opt);
retval = -EINVAL;
goto err1;
}
} else if (!strncmp(this_opt, "addr", 4))
grvga_fix_addr = simple_strtoul(this_opt + 5, NULL, 16);
else if (!strncmp(this_opt, "size", 4))
grvga_mem_size = simple_strtoul(this_opt + 5, NULL, 0);
else
mode_opt = this_opt;
}
par = info->par;
info->fbops = &grvga_ops;
info->fix = grvga_fix;
info->pseudo_palette = par->color_palette;
info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
info->fix.smem_len = grvga_mem_size;
if (!request_mem_region(dev->resource[0].start, resource_size(&dev->resource[0]), "grlib-svgactrl regs")) {
dev_err(&dev->dev, "registers already mapped\n");
retval = -EBUSY;
goto err;
}
par->regs = of_ioremap(&dev->resource[0], 0,
resource_size(&dev->resource[0]),
"grlib-svgactrl regs");
if (!par->regs) {
dev_err(&dev->dev, "failed to map registers\n");
retval = -ENOMEM;
goto err1;
}
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0) {
dev_err(&dev->dev, "failed to allocate mem with fb_alloc_cmap\n");
retval = -ENOMEM;
goto err2;
}
if (mode_opt) {
retval = fb_find_mode(&info->var, info, mode_opt,
grvga_modedb, sizeof(grvga_modedb), &grvga_modedb[0], 8);
if (!retval || retval == 4) {
retval = -EINVAL;
goto err3;
}
}
if (!grvga_mem_size)
grvga_mem_size = info->var.xres_virtual * info->var.yres_virtual * info->var.bits_per_pixel/8;
if (grvga_fix_addr) {
/* Got framebuffer base address from argument list */
physical_start = grvga_fix_addr;
if (!request_mem_region(physical_start, grvga_mem_size, dev->name)) {
dev_err(&dev->dev, "failed to request memory region\n");
retval = -ENOMEM;
goto err3;
}
virtual_start = (unsigned long) ioremap(physical_start, grvga_mem_size);
if (!virtual_start) {
dev_err(&dev->dev, "error mapping framebuffer memory\n");
retval = -ENOMEM;
goto err4;
}
} else { /* Allocate frambuffer memory */
unsigned long page;
virtual_start = (unsigned long) __get_free_pages(GFP_DMA,
get_order(grvga_mem_size));
if (!virtual_start) {
dev_err(&dev->dev,
"unable to allocate framebuffer memory (%lu bytes)\n",
grvga_mem_size);
retval = -ENOMEM;
goto err3;
}
physical_start = dma_map_single(&dev->dev, (void *)virtual_start, grvga_mem_size, DMA_TO_DEVICE);
/* Set page reserved so that mmap will work. This is necessary
* since we'll be remapping normal memory.
*/
for (page = virtual_start;
page < PAGE_ALIGN(virtual_start + grvga_mem_size);
page += PAGE_SIZE) {
SetPageReserved(virt_to_page(page));
}
par->fb_alloced = 1;
}
memset((unsigned long *) virtual_start, 0, grvga_mem_size);
info->screen_base = (char __iomem *) virtual_start;
info->fix.smem_start = physical_start;
info->fix.smem_len = grvga_mem_size;
dev_set_drvdata(&dev->dev, info);
dev_info(&dev->dev,
"Aeroflex Gaisler framebuffer device (fb%d), %dx%d-%d, using %luK of video memory @ %p\n",
info->node, info->var.xres, info->var.yres, info->var.bits_per_pixel,
grvga_mem_size >> 10, info->screen_base);
retval = register_framebuffer(info);
if (retval < 0) {
dev_err(&dev->dev, "failed to register framebuffer\n");
goto err4;
}
__raw_writel(physical_start, &par->regs->fb_pos);
__raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */
&par->regs->status);
return 0;
err4:
dev_set_drvdata(&dev->dev, NULL);
if (grvga_fix_addr) {
release_mem_region(physical_start, grvga_mem_size);
iounmap((void *)virtual_start);
} else
kfree((void *)virtual_start);
err3:
fb_dealloc_cmap(&info->cmap);
err2:
of_iounmap(&dev->resource[0], par->regs,
resource_size(&dev->resource[0]));
err1:
release_mem_region(dev->resource[0].start, resource_size(&dev->resource[0]));
err:
framebuffer_release(info);
return retval;
}
static int __devexit grvga_remove(struct platform_device *device)
{
struct fb_info *info = dev_get_drvdata(&device->dev);
struct grvga_par *par = info->par;
if (info) {
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
of_iounmap(&device->resource[0], par->regs,
resource_size(&device->resource[0]));
release_mem_region(device->resource[0].start, resource_size(&device->resource[0]));
if (!par->fb_alloced) {
release_mem_region(info->fix.smem_start, info->fix.smem_len);
iounmap(info->screen_base);
} else
kfree((void *)info->screen_base);
framebuffer_release(info);
dev_set_drvdata(&device->dev, NULL);
}
return 0;
}
static struct of_device_id svgactrl_of_match[] = {
{
.name = "GAISLER_SVGACTRL",
},
{
.name = "01_063",
},
{},
};
MODULE_DEVICE_TABLE(of, svgactrl_of_match);
static struct platform_driver grvga_driver = {
.driver = {
.name = "grlib-svgactrl",
.owner = THIS_MODULE,
.of_match_table = svgactrl_of_match,
},
.probe = grvga_probe,
.remove = __devexit_p(grvga_remove),
};
static int __init grvga_init(void)
{
return platform_driver_register(&grvga_driver);
}
static void __exit grvga_exit(void)
{
platform_driver_unregister(&grvga_driver);
}
module_init(grvga_init);
module_exit(grvga_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Aeroflex Gaisler");
MODULE_DESCRIPTION("Aeroflex Gaisler framebuffer device driver");
| gpl-2.0 |
multirom-m8/kernel_htc_m8gpe | drivers/ide/ide-legacy.c | 10070 | 1282 | #include <linux/kernel.h>
#include <linux/export.h>
#include <linux/ide.h>
static void ide_legacy_init_one(struct ide_hw **hws, struct ide_hw *hw,
u8 port_no, const struct ide_port_info *d,
unsigned long config)
{
unsigned long base, ctl;
int irq;
if (port_no == 0) {
base = 0x1f0;
ctl = 0x3f6;
irq = 14;
} else {
base = 0x170;
ctl = 0x376;
irq = 15;
}
if (!request_region(base, 8, d->name)) {
printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
d->name, base, base + 7);
return;
}
if (!request_region(ctl, 1, d->name)) {
printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
d->name, ctl);
release_region(base, 8);
return;
}
ide_std_init_ports(hw, base, ctl);
hw->irq = irq;
hw->config = config;
hws[port_no] = hw;
}
int ide_legacy_device_add(const struct ide_port_info *d, unsigned long config)
{
struct ide_hw hw[2], *hws[] = { NULL, NULL };
memset(&hw, 0, sizeof(hw));
if ((d->host_flags & IDE_HFLAG_QD_2ND_PORT) == 0)
ide_legacy_init_one(hws, &hw[0], 0, d, config);
ide_legacy_init_one(hws, &hw[1], 1, d, config);
if (hws[0] == NULL && hws[1] == NULL &&
(d->host_flags & IDE_HFLAG_SINGLE))
return -ENOENT;
return ide_host_add(d, hws, 2, NULL);
}
EXPORT_SYMBOL_GPL(ide_legacy_device_add);
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.